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5b1c2028 LD |
1 | /* |
2 | * Maxim MAX77620 Regulator driver | |
3 | * | |
4 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | |
5 | * | |
6 | * Author: Mallikarjun Kasoju <mkasoju@nvidia.com> | |
7 | * Laxman Dewangan <ldewangan@nvidia.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms and conditions of the GNU General Public License, | |
11 | * version 2, as published by the Free Software Foundation. | |
12 | */ | |
13 | ||
14 | #include <linux/init.h> | |
15 | #include <linux/mfd/max77620.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/of.h> | |
18 | #include <linux/platform_device.h> | |
19 | #include <linux/regmap.h> | |
20 | #include <linux/regulator/driver.h> | |
21 | #include <linux/regulator/machine.h> | |
22 | #include <linux/regulator/of_regulator.h> | |
23 | ||
24 | #define max77620_rails(_name) "max77620-"#_name | |
25 | ||
26 | /* Power Mode */ | |
27 | #define MAX77620_POWER_MODE_NORMAL 3 | |
28 | #define MAX77620_POWER_MODE_LPM 2 | |
29 | #define MAX77620_POWER_MODE_GLPM 1 | |
30 | #define MAX77620_POWER_MODE_DISABLE 0 | |
31 | ||
32 | /* SD Slew Rate */ | |
33 | #define MAX77620_SD_SR_13_75 0 | |
34 | #define MAX77620_SD_SR_27_5 1 | |
35 | #define MAX77620_SD_SR_55 2 | |
36 | #define MAX77620_SD_SR_100 3 | |
37 | ||
38 | enum max77620_regulators { | |
39 | MAX77620_REGULATOR_ID_SD0, | |
40 | MAX77620_REGULATOR_ID_SD1, | |
41 | MAX77620_REGULATOR_ID_SD2, | |
42 | MAX77620_REGULATOR_ID_SD3, | |
43 | MAX77620_REGULATOR_ID_SD4, | |
44 | MAX77620_REGULATOR_ID_LDO0, | |
45 | MAX77620_REGULATOR_ID_LDO1, | |
46 | MAX77620_REGULATOR_ID_LDO2, | |
47 | MAX77620_REGULATOR_ID_LDO3, | |
48 | MAX77620_REGULATOR_ID_LDO4, | |
49 | MAX77620_REGULATOR_ID_LDO5, | |
50 | MAX77620_REGULATOR_ID_LDO6, | |
51 | MAX77620_REGULATOR_ID_LDO7, | |
52 | MAX77620_REGULATOR_ID_LDO8, | |
53 | MAX77620_NUM_REGS, | |
54 | }; | |
55 | ||
56 | /* Regulator types */ | |
57 | enum max77620_regulator_type { | |
58 | MAX77620_REGULATOR_TYPE_SD, | |
59 | MAX77620_REGULATOR_TYPE_LDO_N, | |
60 | MAX77620_REGULATOR_TYPE_LDO_P, | |
61 | }; | |
62 | ||
63 | struct max77620_regulator_info { | |
64 | u8 type; | |
5b1c2028 LD |
65 | u8 fps_addr; |
66 | u8 volt_addr; | |
67 | u8 cfg_addr; | |
5b1c2028 LD |
68 | u8 power_mode_mask; |
69 | u8 power_mode_shift; | |
70 | u8 remote_sense_addr; | |
71 | u8 remote_sense_mask; | |
72 | struct regulator_desc desc; | |
73 | }; | |
74 | ||
75 | struct max77620_regulator_pdata { | |
76 | struct regulator_init_data *reg_idata; | |
77 | int active_fps_src; | |
78 | int active_fps_pd_slot; | |
79 | int active_fps_pu_slot; | |
80 | int suspend_fps_src; | |
81 | int suspend_fps_pd_slot; | |
82 | int suspend_fps_pu_slot; | |
83 | int current_mode; | |
5aa43599 | 84 | int ramp_rate_setting; |
5b1c2028 LD |
85 | }; |
86 | ||
87 | struct max77620_regulator { | |
88 | struct device *dev; | |
89 | struct regmap *rmap; | |
90 | struct max77620_regulator_info *rinfo[MAX77620_NUM_REGS]; | |
91 | struct max77620_regulator_pdata reg_pdata[MAX77620_NUM_REGS]; | |
5b1c2028 LD |
92 | int enable_power_mode[MAX77620_NUM_REGS]; |
93 | int current_power_mode[MAX77620_NUM_REGS]; | |
94 | int active_fps_src[MAX77620_NUM_REGS]; | |
95 | }; | |
96 | ||
97 | #define fps_src_name(fps_src) \ | |
98 | (fps_src == MAX77620_FPS_SRC_0 ? "FPS_SRC_0" : \ | |
99 | fps_src == MAX77620_FPS_SRC_1 ? "FPS_SRC_1" : \ | |
100 | fps_src == MAX77620_FPS_SRC_2 ? "FPS_SRC_2" : "FPS_SRC_NONE") | |
101 | ||
102 | static int max77620_regulator_get_fps_src(struct max77620_regulator *pmic, | |
103 | int id) | |
104 | { | |
105 | struct max77620_regulator_info *rinfo = pmic->rinfo[id]; | |
106 | unsigned int val; | |
107 | int ret; | |
108 | ||
109 | ret = regmap_read(pmic->rmap, rinfo->fps_addr, &val); | |
110 | if (ret < 0) { | |
111 | dev_err(pmic->dev, "Reg 0x%02x read failed %d\n", | |
112 | rinfo->fps_addr, ret); | |
113 | return ret; | |
114 | } | |
115 | ||
116 | return (val & MAX77620_FPS_SRC_MASK) >> MAX77620_FPS_SRC_SHIFT; | |
117 | } | |
118 | ||
119 | static int max77620_regulator_set_fps_src(struct max77620_regulator *pmic, | |
120 | int fps_src, int id) | |
121 | { | |
122 | struct max77620_regulator_info *rinfo = pmic->rinfo[id]; | |
123 | unsigned int val; | |
124 | int ret; | |
125 | ||
126 | switch (fps_src) { | |
127 | case MAX77620_FPS_SRC_0: | |
128 | case MAX77620_FPS_SRC_1: | |
129 | case MAX77620_FPS_SRC_2: | |
130 | case MAX77620_FPS_SRC_NONE: | |
131 | break; | |
132 | ||
133 | case MAX77620_FPS_SRC_DEF: | |
134 | ret = regmap_read(pmic->rmap, rinfo->fps_addr, &val); | |
135 | if (ret < 0) { | |
136 | dev_err(pmic->dev, "Reg 0x%02x read failed %d\n", | |
137 | rinfo->fps_addr, ret); | |
138 | return ret; | |
139 | } | |
140 | ret = (val & MAX77620_FPS_SRC_MASK) >> MAX77620_FPS_SRC_SHIFT; | |
141 | pmic->active_fps_src[id] = ret; | |
142 | return 0; | |
143 | ||
144 | default: | |
145 | dev_err(pmic->dev, "Invalid FPS %d for regulator %d\n", | |
146 | fps_src, id); | |
147 | return -EINVAL; | |
148 | } | |
149 | ||
150 | ret = regmap_update_bits(pmic->rmap, rinfo->fps_addr, | |
151 | MAX77620_FPS_SRC_MASK, | |
152 | fps_src << MAX77620_FPS_SRC_SHIFT); | |
153 | if (ret < 0) { | |
154 | dev_err(pmic->dev, "Reg 0x%02x update failed %d\n", | |
155 | rinfo->fps_addr, ret); | |
156 | return ret; | |
157 | } | |
158 | pmic->active_fps_src[id] = fps_src; | |
159 | ||
160 | return 0; | |
161 | } | |
162 | ||
163 | static int max77620_regulator_set_fps_slots(struct max77620_regulator *pmic, | |
164 | int id, bool is_suspend) | |
165 | { | |
166 | struct max77620_regulator_pdata *rpdata = &pmic->reg_pdata[id]; | |
167 | struct max77620_regulator_info *rinfo = pmic->rinfo[id]; | |
168 | unsigned int val = 0; | |
169 | unsigned int mask = 0; | |
170 | int pu = rpdata->active_fps_pu_slot; | |
171 | int pd = rpdata->active_fps_pd_slot; | |
172 | int ret = 0; | |
173 | ||
174 | if (is_suspend) { | |
175 | pu = rpdata->suspend_fps_pu_slot; | |
176 | pd = rpdata->suspend_fps_pd_slot; | |
177 | } | |
178 | ||
179 | /* FPS power up period setting */ | |
180 | if (pu >= 0) { | |
181 | val |= (pu << MAX77620_FPS_PU_PERIOD_SHIFT); | |
182 | mask |= MAX77620_FPS_PU_PERIOD_MASK; | |
183 | } | |
184 | ||
185 | /* FPS power down period setting */ | |
186 | if (pd >= 0) { | |
187 | val |= (pd << MAX77620_FPS_PD_PERIOD_SHIFT); | |
188 | mask |= MAX77620_FPS_PD_PERIOD_MASK; | |
189 | } | |
190 | ||
191 | if (mask) { | |
192 | ret = regmap_update_bits(pmic->rmap, rinfo->fps_addr, | |
193 | mask, val); | |
194 | if (ret < 0) { | |
195 | dev_err(pmic->dev, "Reg 0x%02x update failed: %d\n", | |
196 | rinfo->fps_addr, ret); | |
197 | return ret; | |
198 | } | |
199 | } | |
200 | ||
201 | return ret; | |
202 | } | |
203 | ||
204 | static int max77620_regulator_set_power_mode(struct max77620_regulator *pmic, | |
205 | int power_mode, int id) | |
206 | { | |
207 | struct max77620_regulator_info *rinfo = pmic->rinfo[id]; | |
208 | u8 mask = rinfo->power_mode_mask; | |
209 | u8 shift = rinfo->power_mode_shift; | |
210 | u8 addr; | |
211 | int ret; | |
212 | ||
213 | switch (rinfo->type) { | |
214 | case MAX77620_REGULATOR_TYPE_SD: | |
215 | addr = rinfo->cfg_addr; | |
216 | break; | |
217 | default: | |
218 | addr = rinfo->volt_addr; | |
219 | break; | |
220 | } | |
221 | ||
222 | ret = regmap_update_bits(pmic->rmap, addr, mask, power_mode << shift); | |
223 | if (ret < 0) { | |
224 | dev_err(pmic->dev, "Regulator %d mode set failed: %d\n", | |
225 | id, ret); | |
226 | return ret; | |
227 | } | |
228 | pmic->current_power_mode[id] = power_mode; | |
229 | ||
230 | return ret; | |
231 | } | |
232 | ||
233 | static int max77620_regulator_get_power_mode(struct max77620_regulator *pmic, | |
234 | int id) | |
235 | { | |
236 | struct max77620_regulator_info *rinfo = pmic->rinfo[id]; | |
237 | unsigned int val, addr; | |
238 | u8 mask = rinfo->power_mode_mask; | |
239 | u8 shift = rinfo->power_mode_shift; | |
240 | int ret; | |
241 | ||
242 | switch (rinfo->type) { | |
243 | case MAX77620_REGULATOR_TYPE_SD: | |
244 | addr = rinfo->cfg_addr; | |
245 | break; | |
246 | default: | |
247 | addr = rinfo->volt_addr; | |
248 | break; | |
249 | } | |
250 | ||
251 | ret = regmap_read(pmic->rmap, addr, &val); | |
252 | if (ret < 0) { | |
253 | dev_err(pmic->dev, "Regulator %d: Reg 0x%02x read failed: %d\n", | |
254 | id, addr, ret); | |
255 | return ret; | |
256 | } | |
257 | ||
258 | return (val & mask) >> shift; | |
259 | } | |
260 | ||
261 | static int max77620_read_slew_rate(struct max77620_regulator *pmic, int id) | |
262 | { | |
263 | struct max77620_regulator_info *rinfo = pmic->rinfo[id]; | |
264 | unsigned int rval; | |
265 | int slew_rate; | |
266 | int ret; | |
267 | ||
aad76f74 AL |
268 | ret = regmap_read(pmic->rmap, rinfo->cfg_addr, &rval); |
269 | if (ret < 0) { | |
270 | dev_err(pmic->dev, "Register 0x%02x read failed: %d\n", | |
271 | rinfo->cfg_addr, ret); | |
272 | return ret; | |
273 | } | |
274 | ||
5b1c2028 LD |
275 | switch (rinfo->type) { |
276 | case MAX77620_REGULATOR_TYPE_SD: | |
5b1c2028 LD |
277 | slew_rate = (rval >> MAX77620_SD_SR_SHIFT) & 0x3; |
278 | switch (slew_rate) { | |
279 | case 0: | |
280 | slew_rate = 13750; | |
281 | break; | |
282 | case 1: | |
283 | slew_rate = 27500; | |
284 | break; | |
285 | case 2: | |
286 | slew_rate = 55000; | |
287 | break; | |
288 | case 3: | |
289 | slew_rate = 100000; | |
290 | break; | |
291 | } | |
292 | rinfo->desc.ramp_delay = slew_rate; | |
293 | break; | |
294 | default: | |
5b1c2028 LD |
295 | slew_rate = rval & 0x1; |
296 | switch (slew_rate) { | |
297 | case 0: | |
298 | slew_rate = 100000; | |
299 | break; | |
300 | case 1: | |
301 | slew_rate = 5000; | |
302 | break; | |
303 | } | |
304 | rinfo->desc.ramp_delay = slew_rate; | |
305 | break; | |
306 | } | |
307 | ||
308 | return 0; | |
309 | } | |
310 | ||
5aa43599 LD |
311 | static int max77620_set_slew_rate(struct max77620_regulator *pmic, int id, |
312 | int slew_rate) | |
313 | { | |
314 | struct max77620_regulator_info *rinfo = pmic->rinfo[id]; | |
315 | unsigned int val; | |
316 | int ret; | |
317 | u8 mask; | |
318 | ||
319 | if (rinfo->type == MAX77620_REGULATOR_TYPE_SD) { | |
320 | if (slew_rate <= 13750) | |
321 | val = 0; | |
322 | else if (slew_rate <= 27500) | |
323 | val = 1; | |
324 | else if (slew_rate <= 55000) | |
325 | val = 2; | |
326 | else | |
327 | val = 3; | |
328 | val <<= MAX77620_SD_SR_SHIFT; | |
329 | mask = MAX77620_SD_SR_MASK; | |
330 | } else { | |
331 | if (slew_rate <= 5000) | |
332 | val = 1; | |
333 | else | |
334 | val = 0; | |
335 | mask = MAX77620_LDO_SLEW_RATE_MASK; | |
336 | } | |
337 | ||
338 | ret = regmap_update_bits(pmic->rmap, rinfo->cfg_addr, mask, val); | |
339 | if (ret < 0) { | |
340 | dev_err(pmic->dev, "Regulator %d slew rate set failed: %d\n", | |
341 | id, ret); | |
342 | return ret; | |
343 | } | |
344 | ||
345 | return 0; | |
346 | } | |
347 | ||
5b1c2028 LD |
348 | static int max77620_init_pmic(struct max77620_regulator *pmic, int id) |
349 | { | |
350 | struct max77620_regulator_pdata *rpdata = &pmic->reg_pdata[id]; | |
351 | int ret; | |
352 | ||
353 | /* Update power mode */ | |
354 | ret = max77620_regulator_get_power_mode(pmic, id); | |
355 | if (ret < 0) | |
356 | return ret; | |
357 | ||
358 | pmic->current_power_mode[id] = ret; | |
359 | pmic->enable_power_mode[id] = MAX77620_POWER_MODE_NORMAL; | |
360 | ||
361 | if (rpdata->active_fps_src == MAX77620_FPS_SRC_DEF) { | |
362 | ret = max77620_regulator_get_fps_src(pmic, id); | |
363 | if (ret < 0) | |
364 | return ret; | |
365 | rpdata->active_fps_src = ret; | |
366 | } | |
367 | ||
368 | /* If rails are externally control of FPS then enable it always. */ | |
369 | if (rpdata->active_fps_src == MAX77620_FPS_SRC_NONE) { | |
370 | ret = max77620_regulator_set_power_mode(pmic, | |
371 | pmic->enable_power_mode[id], id); | |
372 | if (ret < 0) | |
373 | return ret; | |
374 | } else { | |
375 | if (pmic->current_power_mode[id] != | |
376 | pmic->enable_power_mode[id]) { | |
377 | ret = max77620_regulator_set_power_mode(pmic, | |
378 | pmic->enable_power_mode[id], id); | |
379 | if (ret < 0) | |
380 | return ret; | |
381 | } | |
382 | } | |
383 | ||
384 | ret = max77620_regulator_set_fps_src(pmic, rpdata->active_fps_src, id); | |
385 | if (ret < 0) | |
386 | return ret; | |
387 | ||
388 | ret = max77620_regulator_set_fps_slots(pmic, id, false); | |
389 | if (ret < 0) | |
390 | return ret; | |
391 | ||
5aa43599 LD |
392 | if (rpdata->ramp_rate_setting) { |
393 | ret = max77620_set_slew_rate(pmic, id, | |
394 | rpdata->ramp_rate_setting); | |
395 | if (ret < 0) | |
396 | return ret; | |
397 | } | |
398 | ||
5b1c2028 LD |
399 | return 0; |
400 | } | |
401 | ||
402 | static int max77620_regulator_enable(struct regulator_dev *rdev) | |
403 | { | |
404 | struct max77620_regulator *pmic = rdev_get_drvdata(rdev); | |
405 | int id = rdev_get_id(rdev); | |
406 | ||
407 | if (pmic->active_fps_src[id] != MAX77620_FPS_SRC_NONE) | |
408 | return 0; | |
409 | ||
410 | return max77620_regulator_set_power_mode(pmic, | |
411 | pmic->enable_power_mode[id], id); | |
412 | } | |
413 | ||
414 | static int max77620_regulator_disable(struct regulator_dev *rdev) | |
415 | { | |
416 | struct max77620_regulator *pmic = rdev_get_drvdata(rdev); | |
417 | int id = rdev_get_id(rdev); | |
418 | ||
419 | if (pmic->active_fps_src[id] != MAX77620_FPS_SRC_NONE) | |
420 | return 0; | |
421 | ||
422 | return max77620_regulator_set_power_mode(pmic, | |
423 | MAX77620_POWER_MODE_DISABLE, id); | |
424 | } | |
425 | ||
426 | static int max77620_regulator_is_enabled(struct regulator_dev *rdev) | |
427 | { | |
428 | struct max77620_regulator *pmic = rdev_get_drvdata(rdev); | |
429 | int id = rdev_get_id(rdev); | |
430 | int ret = 1; | |
431 | ||
432 | if (pmic->active_fps_src[id] != MAX77620_FPS_SRC_NONE) | |
433 | return 1; | |
434 | ||
435 | ret = max77620_regulator_get_power_mode(pmic, id); | |
436 | if (ret < 0) | |
437 | return ret; | |
438 | ||
439 | if (ret != MAX77620_POWER_MODE_DISABLE) | |
440 | return 1; | |
441 | ||
442 | return 0; | |
443 | } | |
444 | ||
445 | static int max77620_regulator_set_mode(struct regulator_dev *rdev, | |
446 | unsigned int mode) | |
447 | { | |
448 | struct max77620_regulator *pmic = rdev_get_drvdata(rdev); | |
449 | int id = rdev_get_id(rdev); | |
450 | struct max77620_regulator_info *rinfo = pmic->rinfo[id]; | |
451 | struct max77620_regulator_pdata *rpdata = &pmic->reg_pdata[id]; | |
452 | bool fpwm = false; | |
453 | int power_mode; | |
454 | int ret; | |
455 | u8 val; | |
456 | ||
457 | switch (mode) { | |
458 | case REGULATOR_MODE_FAST: | |
459 | fpwm = true; | |
460 | power_mode = MAX77620_POWER_MODE_NORMAL; | |
461 | break; | |
462 | ||
463 | case REGULATOR_MODE_NORMAL: | |
464 | power_mode = MAX77620_POWER_MODE_NORMAL; | |
465 | break; | |
466 | ||
467 | case REGULATOR_MODE_IDLE: | |
468 | power_mode = MAX77620_POWER_MODE_LPM; | |
469 | break; | |
470 | ||
471 | default: | |
472 | dev_err(pmic->dev, "Regulator %d mode %d is invalid\n", | |
473 | id, mode); | |
474 | return -EINVAL; | |
475 | } | |
476 | ||
477 | if (rinfo->type != MAX77620_REGULATOR_TYPE_SD) | |
478 | goto skip_fpwm; | |
479 | ||
480 | val = (fpwm) ? MAX77620_SD_FPWM_MASK : 0; | |
481 | ret = regmap_update_bits(pmic->rmap, rinfo->cfg_addr, | |
482 | MAX77620_SD_FPWM_MASK, val); | |
483 | if (ret < 0) { | |
484 | dev_err(pmic->dev, "Reg 0x%02x update failed: %d\n", | |
485 | rinfo->cfg_addr, ret); | |
486 | return ret; | |
487 | } | |
488 | rpdata->current_mode = mode; | |
489 | ||
490 | skip_fpwm: | |
491 | ret = max77620_regulator_set_power_mode(pmic, power_mode, id); | |
492 | if (ret < 0) | |
493 | return ret; | |
494 | ||
495 | pmic->enable_power_mode[id] = power_mode; | |
496 | ||
497 | return 0; | |
498 | } | |
499 | ||
500 | static unsigned int max77620_regulator_get_mode(struct regulator_dev *rdev) | |
501 | { | |
502 | struct max77620_regulator *pmic = rdev_get_drvdata(rdev); | |
503 | int id = rdev_get_id(rdev); | |
504 | struct max77620_regulator_info *rinfo = pmic->rinfo[id]; | |
505 | int fpwm = 0; | |
506 | int ret; | |
507 | int pm_mode, reg_mode; | |
508 | unsigned int val; | |
509 | ||
510 | ret = max77620_regulator_get_power_mode(pmic, id); | |
511 | if (ret < 0) | |
512 | return 0; | |
513 | ||
514 | pm_mode = ret; | |
515 | ||
516 | if (rinfo->type == MAX77620_REGULATOR_TYPE_SD) { | |
517 | ret = regmap_read(pmic->rmap, rinfo->cfg_addr, &val); | |
518 | if (ret < 0) { | |
519 | dev_err(pmic->dev, "Reg 0x%02x read failed: %d\n", | |
520 | rinfo->cfg_addr, ret); | |
521 | return ret; | |
522 | } | |
523 | fpwm = !!(val & MAX77620_SD_FPWM_MASK); | |
524 | } | |
525 | ||
526 | switch (pm_mode) { | |
527 | case MAX77620_POWER_MODE_NORMAL: | |
528 | case MAX77620_POWER_MODE_DISABLE: | |
529 | if (fpwm) | |
530 | reg_mode = REGULATOR_MODE_FAST; | |
531 | else | |
532 | reg_mode = REGULATOR_MODE_NORMAL; | |
533 | break; | |
534 | case MAX77620_POWER_MODE_LPM: | |
535 | case MAX77620_POWER_MODE_GLPM: | |
536 | reg_mode = REGULATOR_MODE_IDLE; | |
537 | break; | |
538 | default: | |
539 | return 0; | |
540 | } | |
541 | ||
542 | return reg_mode; | |
543 | } | |
544 | ||
545 | static int max77620_regulator_set_ramp_delay(struct regulator_dev *rdev, | |
546 | int ramp_delay) | |
547 | { | |
548 | struct max77620_regulator *pmic = rdev_get_drvdata(rdev); | |
549 | int id = rdev_get_id(rdev); | |
5aa43599 | 550 | struct max77620_regulator_pdata *rpdata = &pmic->reg_pdata[id]; |
5b1c2028 | 551 | |
5aa43599 LD |
552 | /* Device specific ramp rate setting tells that platform has |
553 | * different ramp rate from advertised value. In this case, | |
554 | * do not configure anything and just return success. | |
555 | */ | |
556 | if (rpdata->ramp_rate_setting) | |
557 | return 0; | |
5b1c2028 | 558 | |
5aa43599 | 559 | return max77620_set_slew_rate(pmic, id, ramp_delay); |
5b1c2028 LD |
560 | } |
561 | ||
562 | static int max77620_of_parse_cb(struct device_node *np, | |
563 | const struct regulator_desc *desc, | |
564 | struct regulator_config *config) | |
565 | { | |
566 | struct max77620_regulator *pmic = config->driver_data; | |
567 | struct max77620_regulator_pdata *rpdata = &pmic->reg_pdata[desc->id]; | |
568 | u32 pval; | |
569 | int ret; | |
570 | ||
571 | ret = of_property_read_u32(np, "maxim,active-fps-source", &pval); | |
572 | rpdata->active_fps_src = (!ret) ? pval : MAX77620_FPS_SRC_DEF; | |
573 | ||
574 | ret = of_property_read_u32(np, "maxim,active-fps-power-up-slot", &pval); | |
575 | rpdata->active_fps_pu_slot = (!ret) ? pval : -1; | |
576 | ||
577 | ret = of_property_read_u32( | |
578 | np, "maxim,active-fps-power-down-slot", &pval); | |
579 | rpdata->active_fps_pd_slot = (!ret) ? pval : -1; | |
580 | ||
581 | ret = of_property_read_u32(np, "maxim,suspend-fps-source", &pval); | |
582 | rpdata->suspend_fps_src = (!ret) ? pval : -1; | |
583 | ||
584 | ret = of_property_read_u32( | |
585 | np, "maxim,suspend-fps-power-up-slot", &pval); | |
586 | rpdata->suspend_fps_pu_slot = (!ret) ? pval : -1; | |
587 | ||
588 | ret = of_property_read_u32( | |
589 | np, "maxim,suspend-fps-power-down-slot", &pval); | |
590 | rpdata->suspend_fps_pd_slot = (!ret) ? pval : -1; | |
591 | ||
5aa43599 LD |
592 | ret = of_property_read_u32(np, "maxim,ramp-rate-setting", &pval); |
593 | rpdata->ramp_rate_setting = (!ret) ? pval : 0; | |
594 | ||
5b1c2028 LD |
595 | return max77620_init_pmic(pmic, desc->id); |
596 | } | |
597 | ||
598 | static struct regulator_ops max77620_regulator_ops = { | |
599 | .is_enabled = max77620_regulator_is_enabled, | |
600 | .enable = max77620_regulator_enable, | |
601 | .disable = max77620_regulator_disable, | |
602 | .list_voltage = regulator_list_voltage_linear, | |
603 | .map_voltage = regulator_map_voltage_linear, | |
604 | .get_voltage_sel = regulator_get_voltage_sel_regmap, | |
605 | .set_voltage_sel = regulator_set_voltage_sel_regmap, | |
606 | .set_mode = max77620_regulator_set_mode, | |
607 | .get_mode = max77620_regulator_get_mode, | |
608 | .set_ramp_delay = max77620_regulator_set_ramp_delay, | |
609 | .set_voltage_time_sel = regulator_set_voltage_time_sel, | |
51817f46 | 610 | .set_active_discharge = regulator_set_active_discharge_regmap, |
5b1c2028 LD |
611 | }; |
612 | ||
613 | #define MAX77620_SD_CNF2_ROVS_EN_NONE 0 | |
614 | #define RAIL_SD(_id, _name, _sname, _volt_mask, _min_uV, _max_uV, \ | |
615 | _step_uV, _rs_add, _rs_mask) \ | |
616 | [MAX77620_REGULATOR_ID_##_id] = { \ | |
617 | .type = MAX77620_REGULATOR_TYPE_SD, \ | |
5b1c2028 LD |
618 | .volt_addr = MAX77620_REG_##_id, \ |
619 | .cfg_addr = MAX77620_REG_##_id##_CFG, \ | |
620 | .fps_addr = MAX77620_REG_FPS_##_id, \ | |
621 | .remote_sense_addr = _rs_add, \ | |
622 | .remote_sense_mask = MAX77620_SD_CNF2_ROVS_EN_##_rs_mask, \ | |
5b1c2028 LD |
623 | .power_mode_mask = MAX77620_SD_POWER_MODE_MASK, \ |
624 | .power_mode_shift = MAX77620_SD_POWER_MODE_SHIFT, \ | |
625 | .desc = { \ | |
626 | .name = max77620_rails(_name), \ | |
627 | .of_match = of_match_ptr(#_name), \ | |
628 | .regulators_node = of_match_ptr("regulators"), \ | |
629 | .of_parse_cb = max77620_of_parse_cb, \ | |
630 | .supply_name = _sname, \ | |
631 | .id = MAX77620_REGULATOR_ID_##_id, \ | |
632 | .ops = &max77620_regulator_ops, \ | |
633 | .n_voltages = ((_max_uV - _min_uV) / _step_uV) + 1, \ | |
634 | .min_uV = _min_uV, \ | |
635 | .uV_step = _step_uV, \ | |
636 | .enable_time = 500, \ | |
637 | .vsel_mask = MAX77620_##_volt_mask##_VOLT_MASK, \ | |
638 | .vsel_reg = MAX77620_REG_##_id, \ | |
51817f46 LD |
639 | .active_discharge_off = 0, \ |
640 | .active_discharge_on = MAX77620_SD_CFG1_ADE_ENABLE, \ | |
641 | .active_discharge_mask = MAX77620_SD_CFG1_ADE_MASK, \ | |
642 | .active_discharge_reg = MAX77620_REG_##_id##_CFG, \ | |
5b1c2028 LD |
643 | .type = REGULATOR_VOLTAGE, \ |
644 | }, \ | |
645 | } | |
646 | ||
647 | #define RAIL_LDO(_id, _name, _sname, _type, _min_uV, _max_uV, _step_uV) \ | |
648 | [MAX77620_REGULATOR_ID_##_id] = { \ | |
649 | .type = MAX77620_REGULATOR_TYPE_LDO_##_type, \ | |
5b1c2028 LD |
650 | .volt_addr = MAX77620_REG_##_id##_CFG, \ |
651 | .cfg_addr = MAX77620_REG_##_id##_CFG2, \ | |
652 | .fps_addr = MAX77620_REG_FPS_##_id, \ | |
653 | .remote_sense_addr = 0xFF, \ | |
5b1c2028 LD |
654 | .power_mode_mask = MAX77620_LDO_POWER_MODE_MASK, \ |
655 | .power_mode_shift = MAX77620_LDO_POWER_MODE_SHIFT, \ | |
656 | .desc = { \ | |
657 | .name = max77620_rails(_name), \ | |
658 | .of_match = of_match_ptr(#_name), \ | |
659 | .regulators_node = of_match_ptr("regulators"), \ | |
660 | .of_parse_cb = max77620_of_parse_cb, \ | |
661 | .supply_name = _sname, \ | |
662 | .id = MAX77620_REGULATOR_ID_##_id, \ | |
663 | .ops = &max77620_regulator_ops, \ | |
664 | .n_voltages = ((_max_uV - _min_uV) / _step_uV) + 1, \ | |
665 | .min_uV = _min_uV, \ | |
666 | .uV_step = _step_uV, \ | |
667 | .enable_time = 500, \ | |
668 | .vsel_mask = MAX77620_LDO_VOLT_MASK, \ | |
669 | .vsel_reg = MAX77620_REG_##_id##_CFG, \ | |
51817f46 LD |
670 | .active_discharge_off = 0, \ |
671 | .active_discharge_on = MAX77620_LDO_CFG2_ADE_ENABLE, \ | |
672 | .active_discharge_mask = MAX77620_LDO_CFG2_ADE_MASK, \ | |
673 | .active_discharge_reg = MAX77620_REG_##_id##_CFG2, \ | |
5b1c2028 LD |
674 | .type = REGULATOR_VOLTAGE, \ |
675 | }, \ | |
676 | } | |
677 | ||
678 | static struct max77620_regulator_info max77620_regs_info[MAX77620_NUM_REGS] = { | |
679 | RAIL_SD(SD0, sd0, "in-sd0", SD0, 600000, 1400000, 12500, 0x22, SD0), | |
680 | RAIL_SD(SD1, sd1, "in-sd1", SD1, 600000, 1550000, 12500, 0x22, SD1), | |
681 | RAIL_SD(SD2, sd2, "in-sd2", SDX, 600000, 3787500, 12500, 0xFF, NONE), | |
682 | RAIL_SD(SD3, sd3, "in-sd3", SDX, 600000, 3787500, 12500, 0xFF, NONE), | |
683 | RAIL_SD(SD4, sd4, "in-sd4", SDX, 600000, 3787500, 12500, 0xFF, NONE), | |
684 | ||
685 | RAIL_LDO(LDO0, ldo0, "in-ldo0-1", N, 800000, 2375000, 25000), | |
686 | RAIL_LDO(LDO1, ldo1, "in-ldo0-1", N, 800000, 2375000, 25000), | |
687 | RAIL_LDO(LDO2, ldo2, "in-ldo2", P, 800000, 3950000, 50000), | |
688 | RAIL_LDO(LDO3, ldo3, "in-ldo3-5", P, 800000, 3950000, 50000), | |
689 | RAIL_LDO(LDO4, ldo4, "in-ldo4-6", P, 800000, 1587500, 12500), | |
690 | RAIL_LDO(LDO5, ldo5, "in-ldo3-5", P, 800000, 3950000, 50000), | |
691 | RAIL_LDO(LDO6, ldo6, "in-ldo4-6", P, 800000, 3950000, 50000), | |
692 | RAIL_LDO(LDO7, ldo7, "in-ldo7-8", N, 800000, 3950000, 50000), | |
693 | RAIL_LDO(LDO8, ldo8, "in-ldo7-8", N, 800000, 3950000, 50000), | |
694 | }; | |
695 | ||
696 | static struct max77620_regulator_info max20024_regs_info[MAX77620_NUM_REGS] = { | |
697 | RAIL_SD(SD0, sd0, "in-sd0", SD0, 800000, 1587500, 12500, 0x22, SD0), | |
698 | RAIL_SD(SD1, sd1, "in-sd1", SD1, 600000, 3387500, 12500, 0x22, SD1), | |
699 | RAIL_SD(SD2, sd2, "in-sd2", SDX, 600000, 3787500, 12500, 0xFF, NONE), | |
700 | RAIL_SD(SD3, sd3, "in-sd3", SDX, 600000, 3787500, 12500, 0xFF, NONE), | |
701 | RAIL_SD(SD4, sd4, "in-sd4", SDX, 600000, 3787500, 12500, 0xFF, NONE), | |
702 | ||
703 | RAIL_LDO(LDO0, ldo0, "in-ldo0-1", N, 800000, 2375000, 25000), | |
704 | RAIL_LDO(LDO1, ldo1, "in-ldo0-1", N, 800000, 2375000, 25000), | |
705 | RAIL_LDO(LDO2, ldo2, "in-ldo2", P, 800000, 3950000, 50000), | |
706 | RAIL_LDO(LDO3, ldo3, "in-ldo3-5", P, 800000, 3950000, 50000), | |
707 | RAIL_LDO(LDO4, ldo4, "in-ldo4-6", P, 800000, 1587500, 12500), | |
708 | RAIL_LDO(LDO5, ldo5, "in-ldo3-5", P, 800000, 3950000, 50000), | |
709 | RAIL_LDO(LDO6, ldo6, "in-ldo4-6", P, 800000, 3950000, 50000), | |
710 | RAIL_LDO(LDO7, ldo7, "in-ldo7-8", N, 800000, 3950000, 50000), | |
711 | RAIL_LDO(LDO8, ldo8, "in-ldo7-8", N, 800000, 3950000, 50000), | |
712 | }; | |
713 | ||
714 | static int max77620_regulator_probe(struct platform_device *pdev) | |
715 | { | |
716 | struct max77620_chip *max77620_chip = dev_get_drvdata(pdev->dev.parent); | |
717 | struct max77620_regulator_info *rinfo; | |
718 | struct device *dev = &pdev->dev; | |
719 | struct regulator_config config = { }; | |
720 | struct max77620_regulator *pmic; | |
721 | int ret = 0; | |
722 | int id; | |
723 | ||
724 | pmic = devm_kzalloc(dev, sizeof(*pmic), GFP_KERNEL); | |
725 | if (!pmic) | |
726 | return -ENOMEM; | |
727 | ||
728 | platform_set_drvdata(pdev, pmic); | |
729 | pmic->dev = dev; | |
730 | pmic->rmap = max77620_chip->rmap; | |
731 | if (!dev->of_node) | |
732 | dev->of_node = pdev->dev.parent->of_node; | |
733 | ||
734 | switch (max77620_chip->chip_id) { | |
735 | case MAX77620: | |
736 | rinfo = max77620_regs_info; | |
737 | break; | |
738 | default: | |
739 | rinfo = max20024_regs_info; | |
740 | break; | |
741 | } | |
742 | ||
743 | config.regmap = pmic->rmap; | |
744 | config.dev = dev; | |
745 | config.driver_data = pmic; | |
746 | ||
747 | for (id = 0; id < MAX77620_NUM_REGS; id++) { | |
748 | struct regulator_dev *rdev; | |
749 | struct regulator_desc *rdesc; | |
750 | ||
751 | if ((max77620_chip->chip_id == MAX77620) && | |
752 | (id == MAX77620_REGULATOR_ID_SD4)) | |
753 | continue; | |
754 | ||
755 | rdesc = &rinfo[id].desc; | |
756 | pmic->rinfo[id] = &max77620_regs_info[id]; | |
757 | pmic->enable_power_mode[id] = MAX77620_POWER_MODE_NORMAL; | |
5b1c2028 LD |
758 | |
759 | ret = max77620_read_slew_rate(pmic, id); | |
760 | if (ret < 0) | |
761 | return ret; | |
762 | ||
763 | rdev = devm_regulator_register(dev, rdesc, &config); | |
764 | if (IS_ERR(rdev)) { | |
765 | ret = PTR_ERR(rdev); | |
766 | dev_err(dev, "Regulator registration %s failed: %d\n", | |
767 | rdesc->name, ret); | |
768 | return ret; | |
769 | } | |
770 | } | |
771 | ||
772 | return 0; | |
773 | } | |
774 | ||
775 | #ifdef CONFIG_PM_SLEEP | |
776 | static int max77620_regulator_suspend(struct device *dev) | |
777 | { | |
778 | struct max77620_regulator *pmic = dev_get_drvdata(dev); | |
779 | struct max77620_regulator_pdata *reg_pdata; | |
780 | int id; | |
781 | ||
782 | for (id = 0; id < MAX77620_NUM_REGS; id++) { | |
783 | reg_pdata = &pmic->reg_pdata[id]; | |
784 | ||
785 | max77620_regulator_set_fps_slots(pmic, id, true); | |
786 | if (reg_pdata->suspend_fps_src < 0) | |
787 | continue; | |
788 | ||
789 | max77620_regulator_set_fps_src(pmic, reg_pdata->suspend_fps_src, | |
790 | id); | |
791 | } | |
792 | ||
793 | return 0; | |
794 | } | |
795 | ||
796 | static int max77620_regulator_resume(struct device *dev) | |
797 | { | |
798 | struct max77620_regulator *pmic = dev_get_drvdata(dev); | |
799 | struct max77620_regulator_pdata *reg_pdata; | |
800 | int id; | |
801 | ||
802 | for (id = 0; id < MAX77620_NUM_REGS; id++) { | |
803 | reg_pdata = &pmic->reg_pdata[id]; | |
804 | ||
805 | max77620_regulator_set_fps_slots(pmic, id, false); | |
806 | if (reg_pdata->active_fps_src < 0) | |
807 | continue; | |
808 | max77620_regulator_set_fps_src(pmic, reg_pdata->active_fps_src, | |
809 | id); | |
810 | } | |
811 | ||
812 | return 0; | |
813 | } | |
814 | #endif | |
815 | ||
816 | static const struct dev_pm_ops max77620_regulator_pm_ops = { | |
817 | SET_SYSTEM_SLEEP_PM_OPS(max77620_regulator_suspend, | |
818 | max77620_regulator_resume) | |
819 | }; | |
820 | ||
821 | static const struct platform_device_id max77620_regulator_devtype[] = { | |
822 | { .name = "max77620-pmic", }, | |
823 | { .name = "max20024-pmic", }, | |
824 | {}, | |
825 | }; | |
826 | MODULE_DEVICE_TABLE(platform, max77620_regulator_devtype); | |
827 | ||
828 | static struct platform_driver max77620_regulator_driver = { | |
829 | .probe = max77620_regulator_probe, | |
830 | .id_table = max77620_regulator_devtype, | |
831 | .driver = { | |
832 | .name = "max77620-pmic", | |
833 | .pm = &max77620_regulator_pm_ops, | |
834 | }, | |
835 | }; | |
836 | ||
837 | module_platform_driver(max77620_regulator_driver); | |
838 | ||
839 | MODULE_DESCRIPTION("MAX77620/MAX20024 regulator driver"); | |
840 | MODULE_AUTHOR("Mallikarjun Kasoju <mkasoju@nvidia.com>"); | |
841 | MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>"); | |
5b1c2028 | 842 | MODULE_LICENSE("GPL v2"); |