Commit | Line | Data |
---|---|---|
e5ce4208 GG |
1 | /* |
2 | * Driver for Regulator part of Palmas PMIC Chips | |
3 | * | |
7be859f7 | 4 | * Copyright 2011-2013 Texas Instruments Inc. |
e5ce4208 GG |
5 | * |
6 | * Author: Graeme Gregory <gg@slimlogic.co.uk> | |
a7dddf27 | 7 | * Author: Ian Lartey <ian@slimlogic.co.uk> |
e5ce4208 GG |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms of the GNU General Public License as published by the | |
11 | * Free Software Foundation; either version 2 of the License, or (at your | |
12 | * option) any later version. | |
13 | * | |
14 | */ | |
15 | ||
16 | #include <linux/kernel.h> | |
17 | #include <linux/module.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/err.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/regulator/driver.h> | |
22 | #include <linux/regulator/machine.h> | |
23 | #include <linux/slab.h> | |
24 | #include <linux/regmap.h> | |
25 | #include <linux/mfd/palmas.h> | |
a361cd9f GG |
26 | #include <linux/of.h> |
27 | #include <linux/of_platform.h> | |
28 | #include <linux/regulator/of_regulator.h> | |
e5ce4208 GG |
29 | |
30 | struct regs_info { | |
31 | char *name; | |
504382c9 | 32 | char *sname; |
e5ce4208 GG |
33 | u8 vsel_addr; |
34 | u8 ctrl_addr; | |
35 | u8 tstep_addr; | |
36 | }; | |
37 | ||
38 | static const struct regs_info palmas_regs_info[] = { | |
39 | { | |
40 | .name = "SMPS12", | |
504382c9 | 41 | .sname = "smps1-in", |
e5ce4208 GG |
42 | .vsel_addr = PALMAS_SMPS12_VOLTAGE, |
43 | .ctrl_addr = PALMAS_SMPS12_CTRL, | |
44 | .tstep_addr = PALMAS_SMPS12_TSTEP, | |
45 | }, | |
46 | { | |
47 | .name = "SMPS123", | |
504382c9 | 48 | .sname = "smps1-in", |
e5ce4208 GG |
49 | .vsel_addr = PALMAS_SMPS12_VOLTAGE, |
50 | .ctrl_addr = PALMAS_SMPS12_CTRL, | |
51 | .tstep_addr = PALMAS_SMPS12_TSTEP, | |
52 | }, | |
53 | { | |
54 | .name = "SMPS3", | |
504382c9 | 55 | .sname = "smps3-in", |
e5ce4208 GG |
56 | .vsel_addr = PALMAS_SMPS3_VOLTAGE, |
57 | .ctrl_addr = PALMAS_SMPS3_CTRL, | |
58 | }, | |
59 | { | |
60 | .name = "SMPS45", | |
504382c9 | 61 | .sname = "smps4-in", |
e5ce4208 GG |
62 | .vsel_addr = PALMAS_SMPS45_VOLTAGE, |
63 | .ctrl_addr = PALMAS_SMPS45_CTRL, | |
64 | .tstep_addr = PALMAS_SMPS45_TSTEP, | |
65 | }, | |
66 | { | |
67 | .name = "SMPS457", | |
504382c9 | 68 | .sname = "smps4-in", |
e5ce4208 GG |
69 | .vsel_addr = PALMAS_SMPS45_VOLTAGE, |
70 | .ctrl_addr = PALMAS_SMPS45_CTRL, | |
71 | .tstep_addr = PALMAS_SMPS45_TSTEP, | |
72 | }, | |
73 | { | |
74 | .name = "SMPS6", | |
504382c9 | 75 | .sname = "smps6-in", |
e5ce4208 GG |
76 | .vsel_addr = PALMAS_SMPS6_VOLTAGE, |
77 | .ctrl_addr = PALMAS_SMPS6_CTRL, | |
78 | .tstep_addr = PALMAS_SMPS6_TSTEP, | |
79 | }, | |
80 | { | |
81 | .name = "SMPS7", | |
504382c9 | 82 | .sname = "smps7-in", |
e5ce4208 GG |
83 | .vsel_addr = PALMAS_SMPS7_VOLTAGE, |
84 | .ctrl_addr = PALMAS_SMPS7_CTRL, | |
85 | }, | |
86 | { | |
87 | .name = "SMPS8", | |
504382c9 | 88 | .sname = "smps8-in", |
e5ce4208 GG |
89 | .vsel_addr = PALMAS_SMPS8_VOLTAGE, |
90 | .ctrl_addr = PALMAS_SMPS8_CTRL, | |
91 | .tstep_addr = PALMAS_SMPS8_TSTEP, | |
92 | }, | |
93 | { | |
94 | .name = "SMPS9", | |
504382c9 | 95 | .sname = "smps9-in", |
e5ce4208 GG |
96 | .vsel_addr = PALMAS_SMPS9_VOLTAGE, |
97 | .ctrl_addr = PALMAS_SMPS9_CTRL, | |
98 | }, | |
99 | { | |
77409d9b | 100 | .name = "SMPS10_OUT2", |
504382c9 | 101 | .sname = "smps10-in", |
e31089c6 | 102 | .ctrl_addr = PALMAS_SMPS10_CTRL, |
e5ce4208 | 103 | }, |
77409d9b KVA |
104 | { |
105 | .name = "SMPS10_OUT1", | |
106 | .sname = "smps10-out2", | |
107 | .ctrl_addr = PALMAS_SMPS10_CTRL, | |
108 | }, | |
e5ce4208 GG |
109 | { |
110 | .name = "LDO1", | |
504382c9 | 111 | .sname = "ldo1-in", |
e5ce4208 GG |
112 | .vsel_addr = PALMAS_LDO1_VOLTAGE, |
113 | .ctrl_addr = PALMAS_LDO1_CTRL, | |
114 | }, | |
115 | { | |
116 | .name = "LDO2", | |
504382c9 | 117 | .sname = "ldo2-in", |
e5ce4208 GG |
118 | .vsel_addr = PALMAS_LDO2_VOLTAGE, |
119 | .ctrl_addr = PALMAS_LDO2_CTRL, | |
120 | }, | |
121 | { | |
122 | .name = "LDO3", | |
504382c9 | 123 | .sname = "ldo3-in", |
e5ce4208 GG |
124 | .vsel_addr = PALMAS_LDO3_VOLTAGE, |
125 | .ctrl_addr = PALMAS_LDO3_CTRL, | |
126 | }, | |
127 | { | |
128 | .name = "LDO4", | |
504382c9 | 129 | .sname = "ldo4-in", |
e5ce4208 GG |
130 | .vsel_addr = PALMAS_LDO4_VOLTAGE, |
131 | .ctrl_addr = PALMAS_LDO4_CTRL, | |
132 | }, | |
133 | { | |
134 | .name = "LDO5", | |
504382c9 | 135 | .sname = "ldo5-in", |
e5ce4208 GG |
136 | .vsel_addr = PALMAS_LDO5_VOLTAGE, |
137 | .ctrl_addr = PALMAS_LDO5_CTRL, | |
138 | }, | |
139 | { | |
140 | .name = "LDO6", | |
504382c9 | 141 | .sname = "ldo6-in", |
e5ce4208 GG |
142 | .vsel_addr = PALMAS_LDO6_VOLTAGE, |
143 | .ctrl_addr = PALMAS_LDO6_CTRL, | |
144 | }, | |
145 | { | |
146 | .name = "LDO7", | |
504382c9 | 147 | .sname = "ldo7-in", |
e5ce4208 GG |
148 | .vsel_addr = PALMAS_LDO7_VOLTAGE, |
149 | .ctrl_addr = PALMAS_LDO7_CTRL, | |
150 | }, | |
151 | { | |
152 | .name = "LDO8", | |
504382c9 | 153 | .sname = "ldo8-in", |
e5ce4208 GG |
154 | .vsel_addr = PALMAS_LDO8_VOLTAGE, |
155 | .ctrl_addr = PALMAS_LDO8_CTRL, | |
156 | }, | |
157 | { | |
158 | .name = "LDO9", | |
504382c9 | 159 | .sname = "ldo9-in", |
e5ce4208 GG |
160 | .vsel_addr = PALMAS_LDO9_VOLTAGE, |
161 | .ctrl_addr = PALMAS_LDO9_CTRL, | |
162 | }, | |
163 | { | |
164 | .name = "LDOLN", | |
504382c9 | 165 | .sname = "ldoln-in", |
e5ce4208 GG |
166 | .vsel_addr = PALMAS_LDOLN_VOLTAGE, |
167 | .ctrl_addr = PALMAS_LDOLN_CTRL, | |
168 | }, | |
169 | { | |
170 | .name = "LDOUSB", | |
504382c9 | 171 | .sname = "ldousb-in", |
e5ce4208 GG |
172 | .vsel_addr = PALMAS_LDOUSB_VOLTAGE, |
173 | .ctrl_addr = PALMAS_LDOUSB_CTRL, | |
174 | }, | |
aa07f027 LD |
175 | { |
176 | .name = "REGEN1", | |
177 | .ctrl_addr = PALMAS_REGEN1_CTRL, | |
178 | }, | |
179 | { | |
180 | .name = "REGEN2", | |
181 | .ctrl_addr = PALMAS_REGEN2_CTRL, | |
182 | }, | |
183 | { | |
184 | .name = "REGEN3", | |
185 | .ctrl_addr = PALMAS_REGEN3_CTRL, | |
186 | }, | |
187 | { | |
188 | .name = "SYSEN1", | |
189 | .ctrl_addr = PALMAS_SYSEN1_CTRL, | |
190 | }, | |
191 | { | |
192 | .name = "SYSEN2", | |
193 | .ctrl_addr = PALMAS_SYSEN2_CTRL, | |
194 | }, | |
e5ce4208 GG |
195 | }; |
196 | ||
28d1e8cd LD |
197 | static unsigned int palmas_smps_ramp_delay[4] = {0, 10000, 5000, 2500}; |
198 | ||
e5ce4208 GG |
199 | #define SMPS_CTRL_MODE_OFF 0x00 |
200 | #define SMPS_CTRL_MODE_ON 0x01 | |
201 | #define SMPS_CTRL_MODE_ECO 0x02 | |
202 | #define SMPS_CTRL_MODE_PWM 0x03 | |
203 | ||
204 | /* These values are derived from the data sheet. And are the number of steps | |
205 | * where there is a voltage change, the ranges at beginning and end of register | |
206 | * max/min values where there are no change are ommitted. | |
207 | * | |
208 | * So they are basically (maxV-minV)/stepV | |
209 | */ | |
a7dddf27 | 210 | #define PALMAS_SMPS_NUM_VOLTAGES 117 |
e5ce4208 GG |
211 | #define PALMAS_SMPS10_NUM_VOLTAGES 2 |
212 | #define PALMAS_LDO_NUM_VOLTAGES 50 | |
213 | ||
214 | #define SMPS10_VSEL (1<<3) | |
215 | #define SMPS10_BOOST_EN (1<<2) | |
216 | #define SMPS10_BYPASS_EN (1<<1) | |
217 | #define SMPS10_SWITCH_EN (1<<0) | |
218 | ||
219 | #define REGULATOR_SLAVE 0 | |
220 | ||
221 | static int palmas_smps_read(struct palmas *palmas, unsigned int reg, | |
222 | unsigned int *dest) | |
223 | { | |
224 | unsigned int addr; | |
225 | ||
226 | addr = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, reg); | |
227 | ||
228 | return regmap_read(palmas->regmap[REGULATOR_SLAVE], addr, dest); | |
229 | } | |
230 | ||
231 | static int palmas_smps_write(struct palmas *palmas, unsigned int reg, | |
232 | unsigned int value) | |
233 | { | |
234 | unsigned int addr; | |
235 | ||
236 | addr = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, reg); | |
237 | ||
238 | return regmap_write(palmas->regmap[REGULATOR_SLAVE], addr, value); | |
239 | } | |
240 | ||
241 | static int palmas_ldo_read(struct palmas *palmas, unsigned int reg, | |
242 | unsigned int *dest) | |
243 | { | |
244 | unsigned int addr; | |
245 | ||
246 | addr = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE, reg); | |
247 | ||
248 | return regmap_read(palmas->regmap[REGULATOR_SLAVE], addr, dest); | |
249 | } | |
250 | ||
251 | static int palmas_ldo_write(struct palmas *palmas, unsigned int reg, | |
252 | unsigned int value) | |
253 | { | |
254 | unsigned int addr; | |
255 | ||
256 | addr = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE, reg); | |
257 | ||
258 | return regmap_write(palmas->regmap[REGULATOR_SLAVE], addr, value); | |
259 | } | |
260 | ||
261 | static int palmas_is_enabled_smps(struct regulator_dev *dev) | |
262 | { | |
263 | struct palmas_pmic *pmic = rdev_get_drvdata(dev); | |
264 | int id = rdev_get_id(dev); | |
265 | unsigned int reg; | |
266 | ||
267 | palmas_smps_read(pmic->palmas, palmas_regs_info[id].ctrl_addr, ®); | |
268 | ||
269 | reg &= PALMAS_SMPS12_CTRL_STATUS_MASK; | |
270 | reg >>= PALMAS_SMPS12_CTRL_STATUS_SHIFT; | |
271 | ||
272 | return !!(reg); | |
273 | } | |
274 | ||
275 | static int palmas_enable_smps(struct regulator_dev *dev) | |
276 | { | |
277 | struct palmas_pmic *pmic = rdev_get_drvdata(dev); | |
278 | int id = rdev_get_id(dev); | |
279 | unsigned int reg; | |
280 | ||
281 | palmas_smps_read(pmic->palmas, palmas_regs_info[id].ctrl_addr, ®); | |
282 | ||
283 | reg &= ~PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK; | |
51d3a0c9 LD |
284 | if (pmic->current_reg_mode[id]) |
285 | reg |= pmic->current_reg_mode[id]; | |
286 | else | |
287 | reg |= SMPS_CTRL_MODE_ON; | |
e5ce4208 GG |
288 | |
289 | palmas_smps_write(pmic->palmas, palmas_regs_info[id].ctrl_addr, reg); | |
290 | ||
291 | return 0; | |
292 | } | |
293 | ||
294 | static int palmas_disable_smps(struct regulator_dev *dev) | |
295 | { | |
296 | struct palmas_pmic *pmic = rdev_get_drvdata(dev); | |
297 | int id = rdev_get_id(dev); | |
298 | unsigned int reg; | |
299 | ||
300 | palmas_smps_read(pmic->palmas, palmas_regs_info[id].ctrl_addr, ®); | |
301 | ||
302 | reg &= ~PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK; | |
303 | ||
304 | palmas_smps_write(pmic->palmas, palmas_regs_info[id].ctrl_addr, reg); | |
305 | ||
306 | return 0; | |
307 | } | |
308 | ||
e5ce4208 GG |
309 | static int palmas_set_mode_smps(struct regulator_dev *dev, unsigned int mode) |
310 | { | |
311 | struct palmas_pmic *pmic = rdev_get_drvdata(dev); | |
312 | int id = rdev_get_id(dev); | |
313 | unsigned int reg; | |
51d3a0c9 | 314 | bool rail_enable = true; |
e5ce4208 GG |
315 | |
316 | palmas_smps_read(pmic->palmas, palmas_regs_info[id].ctrl_addr, ®); | |
999f0c7c | 317 | reg &= ~PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK; |
e5ce4208 | 318 | |
51d3a0c9 LD |
319 | if (reg == SMPS_CTRL_MODE_OFF) |
320 | rail_enable = false; | |
321 | ||
e5ce4208 GG |
322 | switch (mode) { |
323 | case REGULATOR_MODE_NORMAL: | |
324 | reg |= SMPS_CTRL_MODE_ON; | |
325 | break; | |
326 | case REGULATOR_MODE_IDLE: | |
327 | reg |= SMPS_CTRL_MODE_ECO; | |
328 | break; | |
329 | case REGULATOR_MODE_FAST: | |
330 | reg |= SMPS_CTRL_MODE_PWM; | |
331 | break; | |
332 | default: | |
333 | return -EINVAL; | |
334 | } | |
e5ce4208 | 335 | |
51d3a0c9 LD |
336 | pmic->current_reg_mode[id] = reg & PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK; |
337 | if (rail_enable) | |
338 | palmas_smps_write(pmic->palmas, | |
339 | palmas_regs_info[id].ctrl_addr, reg); | |
e5ce4208 GG |
340 | return 0; |
341 | } | |
342 | ||
343 | static unsigned int palmas_get_mode_smps(struct regulator_dev *dev) | |
344 | { | |
345 | struct palmas_pmic *pmic = rdev_get_drvdata(dev); | |
346 | int id = rdev_get_id(dev); | |
347 | unsigned int reg; | |
348 | ||
51d3a0c9 | 349 | reg = pmic->current_reg_mode[id] & PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK; |
e5ce4208 GG |
350 | |
351 | switch (reg) { | |
352 | case SMPS_CTRL_MODE_ON: | |
353 | return REGULATOR_MODE_NORMAL; | |
354 | case SMPS_CTRL_MODE_ECO: | |
355 | return REGULATOR_MODE_IDLE; | |
356 | case SMPS_CTRL_MODE_PWM: | |
357 | return REGULATOR_MODE_FAST; | |
358 | } | |
359 | ||
360 | return 0; | |
361 | } | |
362 | ||
363 | static int palmas_list_voltage_smps(struct regulator_dev *dev, | |
364 | unsigned selector) | |
365 | { | |
366 | struct palmas_pmic *pmic = rdev_get_drvdata(dev); | |
367 | int id = rdev_get_id(dev); | |
368 | int mult = 1; | |
369 | ||
e5ce4208 GG |
370 | /* Read the multiplier set in VSEL register to return |
371 | * the correct voltage. | |
372 | */ | |
373 | if (pmic->range[id]) | |
374 | mult = 2; | |
375 | ||
ad02e846 AL |
376 | if (selector == 0) |
377 | return 0; | |
378 | else if (selector < 6) | |
379 | return 500000 * mult; | |
380 | else | |
381 | /* Voltage is linear mapping starting from selector 6, | |
382 | * volt = (0.49V + ((selector - 5) * 0.01V)) * RANGE | |
383 | * RANGE is either x1 or x2 | |
384 | */ | |
385 | return (490000 + ((selector - 5) * 10000)) * mult; | |
e5ce4208 GG |
386 | } |
387 | ||
388 | static int palmas_map_voltage_smps(struct regulator_dev *rdev, | |
389 | int min_uV, int max_uV) | |
390 | { | |
8a165df7 AL |
391 | struct palmas_pmic *pmic = rdev_get_drvdata(rdev); |
392 | int id = rdev_get_id(rdev); | |
e5ce4208 GG |
393 | int ret, voltage; |
394 | ||
8a165df7 AL |
395 | if (min_uV == 0) |
396 | return 0; | |
397 | ||
398 | if (pmic->range[id]) { /* RANGE is x2 */ | |
399 | if (min_uV < 1000000) | |
400 | min_uV = 1000000; | |
ad02e846 | 401 | ret = DIV_ROUND_UP(min_uV - 1000000, 20000) + 6; |
8a165df7 AL |
402 | } else { /* RANGE is x1 */ |
403 | if (min_uV < 500000) | |
404 | min_uV = 500000; | |
ad02e846 | 405 | ret = DIV_ROUND_UP(min_uV - 500000, 10000) + 6; |
8a165df7 | 406 | } |
e5ce4208 GG |
407 | |
408 | /* Map back into a voltage to verify we're still in bounds */ | |
409 | voltage = palmas_list_voltage_smps(rdev, ret); | |
410 | if (voltage < min_uV || voltage > max_uV) | |
411 | return -EINVAL; | |
412 | ||
413 | return ret; | |
414 | } | |
415 | ||
28d1e8cd LD |
416 | static int palma_smps_set_voltage_smps_time_sel(struct regulator_dev *rdev, |
417 | unsigned int old_selector, unsigned int new_selector) | |
418 | { | |
419 | struct palmas_pmic *pmic = rdev_get_drvdata(rdev); | |
420 | int id = rdev_get_id(rdev); | |
421 | int old_uv, new_uv; | |
422 | unsigned int ramp_delay = pmic->ramp_delay[id]; | |
423 | ||
424 | if (!ramp_delay) | |
425 | return 0; | |
426 | ||
427 | old_uv = palmas_list_voltage_smps(rdev, old_selector); | |
428 | if (old_uv < 0) | |
429 | return old_uv; | |
430 | ||
431 | new_uv = palmas_list_voltage_smps(rdev, new_selector); | |
432 | if (new_uv < 0) | |
433 | return new_uv; | |
434 | ||
435 | return DIV_ROUND_UP(abs(old_uv - new_uv), ramp_delay); | |
436 | } | |
437 | ||
438 | static int palmas_smps_set_ramp_delay(struct regulator_dev *rdev, | |
439 | int ramp_delay) | |
440 | { | |
441 | struct palmas_pmic *pmic = rdev_get_drvdata(rdev); | |
442 | int id = rdev_get_id(rdev); | |
443 | unsigned int reg = 0; | |
444 | unsigned int addr = palmas_regs_info[id].tstep_addr; | |
445 | int ret; | |
446 | ||
f22c2bae AL |
447 | /* SMPS3 and SMPS7 do not have tstep_addr setting */ |
448 | switch (id) { | |
449 | case PALMAS_REG_SMPS3: | |
450 | case PALMAS_REG_SMPS7: | |
451 | return 0; | |
452 | } | |
453 | ||
28d1e8cd LD |
454 | if (ramp_delay <= 0) |
455 | reg = 0; | |
0ea34b57 | 456 | else if (ramp_delay <= 2500) |
28d1e8cd | 457 | reg = 3; |
0ea34b57 | 458 | else if (ramp_delay <= 5000) |
28d1e8cd LD |
459 | reg = 2; |
460 | else | |
461 | reg = 1; | |
462 | ||
463 | ret = palmas_smps_write(pmic->palmas, addr, reg); | |
464 | if (ret < 0) { | |
465 | dev_err(pmic->palmas->dev, "TSTEP write failed: %d\n", ret); | |
466 | return ret; | |
467 | } | |
468 | ||
469 | pmic->ramp_delay[id] = palmas_smps_ramp_delay[reg]; | |
470 | return ret; | |
471 | } | |
472 | ||
e5ce4208 GG |
473 | static struct regulator_ops palmas_ops_smps = { |
474 | .is_enabled = palmas_is_enabled_smps, | |
475 | .enable = palmas_enable_smps, | |
476 | .disable = palmas_disable_smps, | |
477 | .set_mode = palmas_set_mode_smps, | |
478 | .get_mode = palmas_get_mode_smps, | |
bdc4baac AL |
479 | .get_voltage_sel = regulator_get_voltage_sel_regmap, |
480 | .set_voltage_sel = regulator_set_voltage_sel_regmap, | |
e5ce4208 GG |
481 | .list_voltage = palmas_list_voltage_smps, |
482 | .map_voltage = palmas_map_voltage_smps, | |
28d1e8cd LD |
483 | .set_voltage_time_sel = palma_smps_set_voltage_smps_time_sel, |
484 | .set_ramp_delay = palmas_smps_set_ramp_delay, | |
e5ce4208 GG |
485 | }; |
486 | ||
e5ce4208 GG |
487 | static struct regulator_ops palmas_ops_smps10 = { |
488 | .is_enabled = regulator_is_enabled_regmap, | |
489 | .enable = regulator_enable_regmap, | |
490 | .disable = regulator_disable_regmap, | |
491 | .get_voltage_sel = regulator_get_voltage_sel_regmap, | |
492 | .set_voltage_sel = regulator_set_voltage_sel_regmap, | |
8029a006 AL |
493 | .list_voltage = regulator_list_voltage_linear, |
494 | .map_voltage = regulator_map_voltage_linear, | |
77409d9b KVA |
495 | .set_bypass = regulator_set_bypass_regmap, |
496 | .get_bypass = regulator_get_bypass_regmap, | |
e5ce4208 GG |
497 | }; |
498 | ||
499 | static int palmas_is_enabled_ldo(struct regulator_dev *dev) | |
500 | { | |
501 | struct palmas_pmic *pmic = rdev_get_drvdata(dev); | |
502 | int id = rdev_get_id(dev); | |
503 | unsigned int reg; | |
504 | ||
505 | palmas_ldo_read(pmic->palmas, palmas_regs_info[id].ctrl_addr, ®); | |
506 | ||
507 | reg &= PALMAS_LDO1_CTRL_STATUS; | |
508 | ||
509 | return !!(reg); | |
510 | } | |
511 | ||
e5ce4208 GG |
512 | static struct regulator_ops palmas_ops_ldo = { |
513 | .is_enabled = palmas_is_enabled_ldo, | |
514 | .enable = regulator_enable_regmap, | |
515 | .disable = regulator_disable_regmap, | |
4a247a96 AL |
516 | .get_voltage_sel = regulator_get_voltage_sel_regmap, |
517 | .set_voltage_sel = regulator_set_voltage_sel_regmap, | |
9119ff6a AL |
518 | .list_voltage = regulator_list_voltage_linear, |
519 | .map_voltage = regulator_map_voltage_linear, | |
e5ce4208 GG |
520 | }; |
521 | ||
aa07f027 LD |
522 | static struct regulator_ops palmas_ops_extreg = { |
523 | .is_enabled = regulator_is_enabled_regmap, | |
524 | .enable = regulator_enable_regmap, | |
525 | .disable = regulator_disable_regmap, | |
526 | }; | |
527 | ||
e5ce4208 GG |
528 | /* |
529 | * setup the hardware based sleep configuration of the SMPS/LDO regulators | |
530 | * from the platform data. This is different to the software based control | |
531 | * supported by the regulator framework as it is controlled by toggling | |
532 | * pins on the PMIC such as PREQ, SYSEN, ... | |
533 | */ | |
534 | static int palmas_smps_init(struct palmas *palmas, int id, | |
535 | struct palmas_reg_init *reg_init) | |
536 | { | |
537 | unsigned int reg; | |
538 | unsigned int addr; | |
539 | int ret; | |
540 | ||
541 | addr = palmas_regs_info[id].ctrl_addr; | |
542 | ||
543 | ret = palmas_smps_read(palmas, addr, ®); | |
544 | if (ret) | |
545 | return ret; | |
546 | ||
fedd89b1 | 547 | switch (id) { |
77409d9b KVA |
548 | case PALMAS_REG_SMPS10_OUT1: |
549 | case PALMAS_REG_SMPS10_OUT2: | |
30590d04 LD |
550 | reg &= ~PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK; |
551 | if (reg_init->mode_sleep) | |
fedd89b1 AL |
552 | reg |= reg_init->mode_sleep << |
553 | PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT; | |
fedd89b1 AL |
554 | break; |
555 | default: | |
e5ce4208 GG |
556 | if (reg_init->warm_reset) |
557 | reg |= PALMAS_SMPS12_CTRL_WR_S; | |
30590d04 LD |
558 | else |
559 | reg &= ~PALMAS_SMPS12_CTRL_WR_S; | |
e5ce4208 GG |
560 | |
561 | if (reg_init->roof_floor) | |
562 | reg |= PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN; | |
30590d04 LD |
563 | else |
564 | reg &= ~PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN; | |
e5ce4208 | 565 | |
30590d04 LD |
566 | reg &= ~PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK; |
567 | if (reg_init->mode_sleep) | |
e5ce4208 GG |
568 | reg |= reg_init->mode_sleep << |
569 | PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT; | |
e5ce4208 | 570 | } |
fedd89b1 | 571 | |
e5ce4208 GG |
572 | ret = palmas_smps_write(palmas, addr, reg); |
573 | if (ret) | |
574 | return ret; | |
575 | ||
e5ce4208 GG |
576 | if (palmas_regs_info[id].vsel_addr && reg_init->vsel) { |
577 | addr = palmas_regs_info[id].vsel_addr; | |
578 | ||
579 | reg = reg_init->vsel; | |
580 | ||
581 | ret = palmas_smps_write(palmas, addr, reg); | |
582 | if (ret) | |
583 | return ret; | |
584 | } | |
585 | ||
586 | ||
587 | return 0; | |
588 | } | |
589 | ||
590 | static int palmas_ldo_init(struct palmas *palmas, int id, | |
591 | struct palmas_reg_init *reg_init) | |
592 | { | |
593 | unsigned int reg; | |
594 | unsigned int addr; | |
595 | int ret; | |
596 | ||
597 | addr = palmas_regs_info[id].ctrl_addr; | |
598 | ||
2735daeb | 599 | ret = palmas_ldo_read(palmas, addr, ®); |
e5ce4208 GG |
600 | if (ret) |
601 | return ret; | |
602 | ||
603 | if (reg_init->warm_reset) | |
604 | reg |= PALMAS_LDO1_CTRL_WR_S; | |
30590d04 LD |
605 | else |
606 | reg &= ~PALMAS_LDO1_CTRL_WR_S; | |
e5ce4208 GG |
607 | |
608 | if (reg_init->mode_sleep) | |
609 | reg |= PALMAS_LDO1_CTRL_MODE_SLEEP; | |
30590d04 LD |
610 | else |
611 | reg &= ~PALMAS_LDO1_CTRL_MODE_SLEEP; | |
e5ce4208 | 612 | |
2735daeb | 613 | ret = palmas_ldo_write(palmas, addr, reg); |
e5ce4208 GG |
614 | if (ret) |
615 | return ret; | |
616 | ||
617 | return 0; | |
618 | } | |
619 | ||
aa07f027 LD |
620 | static int palmas_extreg_init(struct palmas *palmas, int id, |
621 | struct palmas_reg_init *reg_init) | |
622 | { | |
623 | unsigned int addr; | |
624 | int ret; | |
625 | unsigned int val = 0; | |
626 | ||
627 | addr = palmas_regs_info[id].ctrl_addr; | |
628 | ||
629 | if (reg_init->mode_sleep) | |
630 | val = PALMAS_REGEN1_CTRL_MODE_SLEEP; | |
631 | ||
632 | ret = palmas_update_bits(palmas, PALMAS_RESOURCE_BASE, | |
633 | addr, PALMAS_REGEN1_CTRL_MODE_SLEEP, val); | |
634 | if (ret < 0) { | |
635 | dev_err(palmas->dev, "Resource reg 0x%02x update failed %d\n", | |
636 | addr, ret); | |
637 | return ret; | |
638 | } | |
639 | return 0; | |
640 | } | |
641 | ||
17c11a76 LD |
642 | static void palmas_enable_ldo8_track(struct palmas *palmas) |
643 | { | |
644 | unsigned int reg; | |
645 | unsigned int addr; | |
646 | int ret; | |
647 | ||
648 | addr = palmas_regs_info[PALMAS_REG_LDO8].ctrl_addr; | |
649 | ||
650 | ret = palmas_ldo_read(palmas, addr, ®); | |
651 | if (ret) { | |
652 | dev_err(palmas->dev, "Error in reading ldo8 control reg\n"); | |
653 | return; | |
654 | } | |
655 | ||
656 | reg |= PALMAS_LDO8_CTRL_LDO_TRACKING_EN; | |
657 | ret = palmas_ldo_write(palmas, addr, reg); | |
658 | if (ret < 0) { | |
659 | dev_err(palmas->dev, "Error in enabling tracking mode\n"); | |
660 | return; | |
661 | } | |
662 | /* | |
663 | * When SMPS45 is set to off and LDO8 tracking is enabled, the LDO8 | |
664 | * output is defined by the LDO8_VOLTAGE.VSEL register divided by two, | |
665 | * and can be set from 0.45 to 1.65 V. | |
666 | */ | |
667 | addr = palmas_regs_info[PALMAS_REG_LDO8].vsel_addr; | |
668 | ret = palmas_ldo_read(palmas, addr, ®); | |
669 | if (ret) { | |
670 | dev_err(palmas->dev, "Error in reading ldo8 voltage reg\n"); | |
671 | return; | |
672 | } | |
673 | ||
674 | reg = (reg << 1) & PALMAS_LDO8_VOLTAGE_VSEL_MASK; | |
675 | ret = palmas_ldo_write(palmas, addr, reg); | |
676 | if (ret < 0) | |
677 | dev_err(palmas->dev, "Error in setting ldo8 voltage reg\n"); | |
678 | ||
679 | return; | |
680 | } | |
681 | ||
a361cd9f GG |
682 | static struct of_regulator_match palmas_matches[] = { |
683 | { .name = "smps12", }, | |
684 | { .name = "smps123", }, | |
685 | { .name = "smps3", }, | |
686 | { .name = "smps45", }, | |
687 | { .name = "smps457", }, | |
688 | { .name = "smps6", }, | |
689 | { .name = "smps7", }, | |
690 | { .name = "smps8", }, | |
691 | { .name = "smps9", }, | |
77409d9b KVA |
692 | { .name = "smps10_out2", }, |
693 | { .name = "smps10_out1", }, | |
a361cd9f GG |
694 | { .name = "ldo1", }, |
695 | { .name = "ldo2", }, | |
696 | { .name = "ldo3", }, | |
697 | { .name = "ldo4", }, | |
698 | { .name = "ldo5", }, | |
699 | { .name = "ldo6", }, | |
700 | { .name = "ldo7", }, | |
701 | { .name = "ldo8", }, | |
702 | { .name = "ldo9", }, | |
703 | { .name = "ldoln", }, | |
704 | { .name = "ldousb", }, | |
aa07f027 LD |
705 | { .name = "regen1", }, |
706 | { .name = "regen2", }, | |
707 | { .name = "regen3", }, | |
708 | { .name = "sysen1", }, | |
709 | { .name = "sysen2", }, | |
a361cd9f GG |
710 | }; |
711 | ||
a5023574 | 712 | static void palmas_dt_to_pdata(struct device *dev, |
a361cd9f GG |
713 | struct device_node *node, |
714 | struct palmas_pmic_platform_data *pdata) | |
715 | { | |
716 | struct device_node *regulators; | |
717 | u32 prop; | |
718 | int idx, ret; | |
719 | ||
c92f5dd2 | 720 | node = of_node_get(node); |
a361cd9f GG |
721 | regulators = of_find_node_by_name(node, "regulators"); |
722 | if (!regulators) { | |
723 | dev_info(dev, "regulator node not found\n"); | |
724 | return; | |
725 | } | |
726 | ||
727 | ret = of_regulator_match(dev, regulators, palmas_matches, | |
728 | PALMAS_NUM_REGS); | |
c92f5dd2 | 729 | of_node_put(regulators); |
a361cd9f GG |
730 | if (ret < 0) { |
731 | dev_err(dev, "Error parsing regulator init data: %d\n", ret); | |
732 | return; | |
733 | } | |
734 | ||
735 | for (idx = 0; idx < PALMAS_NUM_REGS; idx++) { | |
736 | if (!palmas_matches[idx].init_data || | |
737 | !palmas_matches[idx].of_node) | |
738 | continue; | |
739 | ||
740 | pdata->reg_data[idx] = palmas_matches[idx].init_data; | |
741 | ||
742 | pdata->reg_init[idx] = devm_kzalloc(dev, | |
743 | sizeof(struct palmas_reg_init), GFP_KERNEL); | |
744 | ||
7be859f7 | 745 | pdata->reg_init[idx]->warm_reset = |
71f2146f AL |
746 | of_property_read_bool(palmas_matches[idx].of_node, |
747 | "ti,warm-reset"); | |
a361cd9f | 748 | |
7be859f7 GG |
749 | pdata->reg_init[idx]->roof_floor = |
750 | of_property_read_bool(palmas_matches[idx].of_node, | |
751 | "ti,roof-floor"); | |
a361cd9f GG |
752 | |
753 | ret = of_property_read_u32(palmas_matches[idx].of_node, | |
3c870e3f | 754 | "ti,mode-sleep", &prop); |
a361cd9f GG |
755 | if (!ret) |
756 | pdata->reg_init[idx]->mode_sleep = prop; | |
757 | ||
7be859f7 GG |
758 | ret = of_property_read_bool(palmas_matches[idx].of_node, |
759 | "ti,smps-range"); | |
760 | if (ret) | |
761 | pdata->reg_init[idx]->vsel = | |
762 | PALMAS_SMPS12_VOLTAGE_RANGE; | |
a361cd9f | 763 | |
17c11a76 LD |
764 | if (idx == PALMAS_REG_LDO8) |
765 | pdata->enable_ldo8_tracking = of_property_read_bool( | |
766 | palmas_matches[idx].of_node, | |
767 | "ti,enable-ldo8-tracking"); | |
a361cd9f GG |
768 | } |
769 | ||
7be859f7 | 770 | pdata->ldo6_vibrator = of_property_read_bool(node, "ti,ldo6-vibrator"); |
a361cd9f GG |
771 | } |
772 | ||
773 | ||
bbcf50b1 | 774 | static int palmas_regulators_probe(struct platform_device *pdev) |
e5ce4208 GG |
775 | { |
776 | struct palmas *palmas = dev_get_drvdata(pdev->dev.parent); | |
dff91d0b | 777 | struct palmas_pmic_platform_data *pdata = dev_get_platdata(&pdev->dev); |
a361cd9f | 778 | struct device_node *node = pdev->dev.of_node; |
e5ce4208 GG |
779 | struct regulator_dev *rdev; |
780 | struct regulator_config config = { }; | |
781 | struct palmas_pmic *pmic; | |
782 | struct palmas_reg_init *reg_init; | |
783 | int id = 0, ret; | |
784 | unsigned int addr, reg; | |
785 | ||
a361cd9f GG |
786 | if (node && !pdata) { |
787 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); | |
788 | ||
789 | if (!pdata) | |
790 | return -ENOMEM; | |
791 | ||
792 | palmas_dt_to_pdata(&pdev->dev, node, pdata); | |
793 | } | |
e5ce4208 GG |
794 | |
795 | pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL); | |
796 | if (!pmic) | |
797 | return -ENOMEM; | |
798 | ||
799 | pmic->dev = &pdev->dev; | |
800 | pmic->palmas = palmas; | |
801 | palmas->pmic = pmic; | |
802 | platform_set_drvdata(pdev, pmic); | |
803 | ||
804 | ret = palmas_smps_read(palmas, PALMAS_SMPS_CTRL, ®); | |
805 | if (ret) | |
1c9d2d71 | 806 | return ret; |
e5ce4208 GG |
807 | |
808 | if (reg & PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN) | |
809 | pmic->smps123 = 1; | |
810 | ||
811 | if (reg & PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN) | |
812 | pmic->smps457 = 1; | |
813 | ||
814 | config.regmap = palmas->regmap[REGULATOR_SLAVE]; | |
815 | config.dev = &pdev->dev; | |
816 | config.driver_data = pmic; | |
817 | ||
818 | for (id = 0; id < PALMAS_REG_LDO1; id++) { | |
28d1e8cd | 819 | bool ramp_delay_support = false; |
e5ce4208 GG |
820 | |
821 | /* | |
822 | * Miss out regulators which are not available due | |
823 | * to slaving configurations. | |
824 | */ | |
825 | switch (id) { | |
826 | case PALMAS_REG_SMPS12: | |
827 | case PALMAS_REG_SMPS3: | |
828 | if (pmic->smps123) | |
829 | continue; | |
28d1e8cd LD |
830 | if (id == PALMAS_REG_SMPS12) |
831 | ramp_delay_support = true; | |
e5ce4208 GG |
832 | break; |
833 | case PALMAS_REG_SMPS123: | |
834 | if (!pmic->smps123) | |
835 | continue; | |
28d1e8cd | 836 | ramp_delay_support = true; |
e5ce4208 GG |
837 | break; |
838 | case PALMAS_REG_SMPS45: | |
839 | case PALMAS_REG_SMPS7: | |
840 | if (pmic->smps457) | |
841 | continue; | |
28d1e8cd LD |
842 | if (id == PALMAS_REG_SMPS45) |
843 | ramp_delay_support = true; | |
e5ce4208 GG |
844 | break; |
845 | case PALMAS_REG_SMPS457: | |
846 | if (!pmic->smps457) | |
847 | continue; | |
28d1e8cd LD |
848 | ramp_delay_support = true; |
849 | break; | |
77409d9b KVA |
850 | case PALMAS_REG_SMPS10_OUT1: |
851 | case PALMAS_REG_SMPS10_OUT2: | |
1ffb0be3 K |
852 | if (!PALMAS_PMIC_HAS(palmas, SMPS10_BOOST)) |
853 | continue; | |
28d1e8cd LD |
854 | } |
855 | ||
3f4d6364 | 856 | if ((id == PALMAS_REG_SMPS6) || (id == PALMAS_REG_SMPS8)) |
28d1e8cd LD |
857 | ramp_delay_support = true; |
858 | ||
859 | if (ramp_delay_support) { | |
860 | addr = palmas_regs_info[id].tstep_addr; | |
861 | ret = palmas_smps_read(pmic->palmas, addr, ®); | |
862 | if (ret < 0) { | |
863 | dev_err(&pdev->dev, | |
864 | "reading TSTEP reg failed: %d\n", ret); | |
865 | goto err_unregister_regulator; | |
866 | } | |
867 | pmic->desc[id].ramp_delay = | |
868 | palmas_smps_ramp_delay[reg & 0x3]; | |
869 | pmic->ramp_delay[id] = pmic->desc[id].ramp_delay; | |
e5ce4208 GG |
870 | } |
871 | ||
bdc4baac AL |
872 | /* Initialise sleep/init values from platform data */ |
873 | if (pdata && pdata->reg_init[id]) { | |
874 | reg_init = pdata->reg_init[id]; | |
875 | ret = palmas_smps_init(palmas, id, reg_init); | |
876 | if (ret) | |
877 | goto err_unregister_regulator; | |
878 | } | |
879 | ||
e5ce4208 GG |
880 | /* Register the regulators */ |
881 | pmic->desc[id].name = palmas_regs_info[id].name; | |
882 | pmic->desc[id].id = id; | |
883 | ||
fedd89b1 | 884 | switch (id) { |
77409d9b KVA |
885 | case PALMAS_REG_SMPS10_OUT1: |
886 | case PALMAS_REG_SMPS10_OUT2: | |
e5ce4208 GG |
887 | pmic->desc[id].n_voltages = PALMAS_SMPS10_NUM_VOLTAGES; |
888 | pmic->desc[id].ops = &palmas_ops_smps10; | |
12565b16 AL |
889 | pmic->desc[id].vsel_reg = |
890 | PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, | |
891 | PALMAS_SMPS10_CTRL); | |
e5ce4208 | 892 | pmic->desc[id].vsel_mask = SMPS10_VSEL; |
a68de074 GG |
893 | pmic->desc[id].enable_reg = |
894 | PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, | |
f232168d | 895 | PALMAS_SMPS10_CTRL); |
77409d9b KVA |
896 | if (id == PALMAS_REG_SMPS10_OUT1) |
897 | pmic->desc[id].enable_mask = SMPS10_SWITCH_EN; | |
898 | else | |
899 | pmic->desc[id].enable_mask = SMPS10_BOOST_EN; | |
900 | pmic->desc[id].bypass_reg = | |
901 | PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, | |
902 | PALMAS_SMPS10_CTRL); | |
903 | pmic->desc[id].bypass_mask = SMPS10_BYPASS_EN; | |
8029a006 AL |
904 | pmic->desc[id].min_uV = 3750000; |
905 | pmic->desc[id].uV_step = 1250000; | |
fedd89b1 AL |
906 | break; |
907 | default: | |
bdc4baac AL |
908 | /* |
909 | * Read and store the RANGE bit for later use | |
910 | * This must be done before regulator is probed, | |
51d3a0c9 LD |
911 | * otherwise we error in probe with unsupportable |
912 | * ranges. Read the current smps mode for later use. | |
bdc4baac | 913 | */ |
e5ce4208 GG |
914 | addr = palmas_regs_info[id].vsel_addr; |
915 | ||
916 | ret = palmas_smps_read(pmic->palmas, addr, ®); | |
917 | if (ret) | |
918 | goto err_unregister_regulator; | |
919 | if (reg & PALMAS_SMPS12_VOLTAGE_RANGE) | |
920 | pmic->range[id] = 1; | |
bdc4baac AL |
921 | |
922 | pmic->desc[id].ops = &palmas_ops_smps; | |
923 | pmic->desc[id].n_voltages = PALMAS_SMPS_NUM_VOLTAGES; | |
924 | pmic->desc[id].vsel_reg = | |
925 | PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, | |
926 | palmas_regs_info[id].vsel_addr); | |
927 | pmic->desc[id].vsel_mask = | |
928 | PALMAS_SMPS12_VOLTAGE_VSEL_MASK; | |
51d3a0c9 LD |
929 | |
930 | /* Read the smps mode for later use. */ | |
931 | addr = palmas_regs_info[id].ctrl_addr; | |
932 | ret = palmas_smps_read(pmic->palmas, addr, ®); | |
933 | if (ret) | |
934 | goto err_unregister_regulator; | |
935 | pmic->current_reg_mode[id] = reg & | |
936 | PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK; | |
e5ce4208 GG |
937 | } |
938 | ||
bdc4baac AL |
939 | pmic->desc[id].type = REGULATOR_VOLTAGE; |
940 | pmic->desc[id].owner = THIS_MODULE; | |
941 | ||
a361cd9f | 942 | if (pdata) |
e5ce4208 GG |
943 | config.init_data = pdata->reg_data[id]; |
944 | else | |
945 | config.init_data = NULL; | |
946 | ||
504382c9 | 947 | pmic->desc[id].supply_name = palmas_regs_info[id].sname; |
a361cd9f GG |
948 | config.of_node = palmas_matches[id].of_node; |
949 | ||
e5ce4208 GG |
950 | rdev = regulator_register(&pmic->desc[id], &config); |
951 | if (IS_ERR(rdev)) { | |
952 | dev_err(&pdev->dev, | |
953 | "failed to register %s regulator\n", | |
954 | pdev->name); | |
955 | ret = PTR_ERR(rdev); | |
956 | goto err_unregister_regulator; | |
957 | } | |
958 | ||
959 | /* Save regulator for cleanup */ | |
960 | pmic->rdev[id] = rdev; | |
961 | } | |
962 | ||
963 | /* Start this loop from the id left from previous loop */ | |
964 | for (; id < PALMAS_NUM_REGS; id++) { | |
965 | ||
966 | /* Miss out regulators which are not available due | |
967 | * to alternate functions. | |
968 | */ | |
969 | ||
970 | /* Register the regulators */ | |
971 | pmic->desc[id].name = palmas_regs_info[id].name; | |
972 | pmic->desc[id].id = id; | |
e5ce4208 GG |
973 | pmic->desc[id].type = REGULATOR_VOLTAGE; |
974 | pmic->desc[id].owner = THIS_MODULE; | |
aa07f027 LD |
975 | |
976 | if (id < PALMAS_REG_REGEN1) { | |
977 | pmic->desc[id].n_voltages = PALMAS_LDO_NUM_VOLTAGES; | |
978 | pmic->desc[id].ops = &palmas_ops_ldo; | |
979 | pmic->desc[id].min_uV = 900000; | |
980 | pmic->desc[id].uV_step = 50000; | |
981 | pmic->desc[id].linear_min_sel = 1; | |
982 | pmic->desc[id].vsel_reg = | |
983 | PALMAS_BASE_TO_REG(PALMAS_LDO_BASE, | |
4a247a96 | 984 | palmas_regs_info[id].vsel_addr); |
aa07f027 LD |
985 | pmic->desc[id].vsel_mask = |
986 | PALMAS_LDO1_VOLTAGE_VSEL_MASK; | |
987 | pmic->desc[id].enable_reg = | |
988 | PALMAS_BASE_TO_REG(PALMAS_LDO_BASE, | |
989 | palmas_regs_info[id].ctrl_addr); | |
990 | pmic->desc[id].enable_mask = | |
991 | PALMAS_LDO1_CTRL_MODE_ACTIVE; | |
17c11a76 LD |
992 | |
993 | /* Check if LDO8 is in tracking mode or not */ | |
994 | if (pdata && (id == PALMAS_REG_LDO8) && | |
995 | pdata->enable_ldo8_tracking) { | |
996 | palmas_enable_ldo8_track(palmas); | |
3df4a81c | 997 | pmic->desc[id].min_uV = 450000; |
17c11a76 LD |
998 | pmic->desc[id].uV_step = 25000; |
999 | } | |
aa07f027 LD |
1000 | } else { |
1001 | pmic->desc[id].n_voltages = 1; | |
1002 | pmic->desc[id].ops = &palmas_ops_extreg; | |
1003 | pmic->desc[id].enable_reg = | |
1004 | PALMAS_BASE_TO_REG(PALMAS_RESOURCE_BASE, | |
a68de074 | 1005 | palmas_regs_info[id].ctrl_addr); |
aa07f027 LD |
1006 | pmic->desc[id].enable_mask = |
1007 | PALMAS_REGEN1_CTRL_MODE_ACTIVE; | |
1008 | } | |
e5ce4208 | 1009 | |
a361cd9f | 1010 | if (pdata) |
e5ce4208 GG |
1011 | config.init_data = pdata->reg_data[id]; |
1012 | else | |
1013 | config.init_data = NULL; | |
1014 | ||
504382c9 | 1015 | pmic->desc[id].supply_name = palmas_regs_info[id].sname; |
a361cd9f GG |
1016 | config.of_node = palmas_matches[id].of_node; |
1017 | ||
e5ce4208 GG |
1018 | rdev = regulator_register(&pmic->desc[id], &config); |
1019 | if (IS_ERR(rdev)) { | |
1020 | dev_err(&pdev->dev, | |
1021 | "failed to register %s regulator\n", | |
1022 | pdev->name); | |
1023 | ret = PTR_ERR(rdev); | |
1024 | goto err_unregister_regulator; | |
1025 | } | |
1026 | ||
1027 | /* Save regulator for cleanup */ | |
1028 | pmic->rdev[id] = rdev; | |
1029 | ||
1030 | /* Initialise sleep/init values from platform data */ | |
a361cd9f | 1031 | if (pdata) { |
e5ce4208 GG |
1032 | reg_init = pdata->reg_init[id]; |
1033 | if (reg_init) { | |
aa07f027 LD |
1034 | if (id < PALMAS_REG_REGEN1) |
1035 | ret = palmas_ldo_init(palmas, | |
1036 | id, reg_init); | |
1037 | else | |
1038 | ret = palmas_extreg_init(palmas, | |
1039 | id, reg_init); | |
1c9d2d71 AL |
1040 | if (ret) { |
1041 | regulator_unregister(pmic->rdev[id]); | |
e5ce4208 | 1042 | goto err_unregister_regulator; |
1c9d2d71 | 1043 | } |
e5ce4208 GG |
1044 | } |
1045 | } | |
1046 | } | |
1047 | ||
17c11a76 | 1048 | |
e5ce4208 GG |
1049 | return 0; |
1050 | ||
1051 | err_unregister_regulator: | |
1052 | while (--id >= 0) | |
1053 | regulator_unregister(pmic->rdev[id]); | |
e5ce4208 GG |
1054 | return ret; |
1055 | } | |
1056 | ||
bbcf50b1 | 1057 | static int palmas_regulators_remove(struct platform_device *pdev) |
e5ce4208 GG |
1058 | { |
1059 | struct palmas_pmic *pmic = platform_get_drvdata(pdev); | |
1060 | int id; | |
1061 | ||
1062 | for (id = 0; id < PALMAS_NUM_REGS; id++) | |
1063 | regulator_unregister(pmic->rdev[id]); | |
e5ce4208 GG |
1064 | return 0; |
1065 | } | |
1066 | ||
3d68dfe3 | 1067 | static struct of_device_id of_palmas_match_tbl[] = { |
a361cd9f | 1068 | { .compatible = "ti,palmas-pmic", }, |
7be859f7 GG |
1069 | { .compatible = "ti,twl6035-pmic", }, |
1070 | { .compatible = "ti,twl6036-pmic", }, | |
1071 | { .compatible = "ti,twl6037-pmic", }, | |
1072 | { .compatible = "ti,tps65913-pmic", }, | |
1073 | { .compatible = "ti,tps65914-pmic", }, | |
1074 | { .compatible = "ti,tps80036-pmic", }, | |
b5c46787 | 1075 | { .compatible = "ti,tps659038-pmic", }, |
a361cd9f GG |
1076 | { /* end */ } |
1077 | }; | |
1078 | ||
e5ce4208 GG |
1079 | static struct platform_driver palmas_driver = { |
1080 | .driver = { | |
1081 | .name = "palmas-pmic", | |
a361cd9f | 1082 | .of_match_table = of_palmas_match_tbl, |
e5ce4208 GG |
1083 | .owner = THIS_MODULE, |
1084 | }, | |
bbcf50b1 LD |
1085 | .probe = palmas_regulators_probe, |
1086 | .remove = palmas_regulators_remove, | |
e5ce4208 GG |
1087 | }; |
1088 | ||
1089 | static int __init palmas_init(void) | |
1090 | { | |
1091 | return platform_driver_register(&palmas_driver); | |
1092 | } | |
1093 | subsys_initcall(palmas_init); | |
1094 | ||
1095 | static void __exit palmas_exit(void) | |
1096 | { | |
1097 | platform_driver_unregister(&palmas_driver); | |
1098 | } | |
1099 | module_exit(palmas_exit); | |
1100 | ||
1101 | MODULE_AUTHOR("Graeme Gregory <gg@slimlogic.co.uk>"); | |
1102 | MODULE_DESCRIPTION("Palmas voltage regulator driver"); | |
1103 | MODULE_LICENSE("GPL"); | |
1104 | MODULE_ALIAS("platform:palmas-pmic"); | |
a361cd9f | 1105 | MODULE_DEVICE_TABLE(of, of_palmas_match_tbl); |