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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/pablo/nftables
[deliverable/linux.git] / drivers / regulator / palmas-regulator.c
CommitLineData
e5ce4208
GG		 1/*
2 * Driver for Regulator part of Palmas PMIC Chips
3 *
7be859f7 4 * Copyright 2011-2013 Texas Instruments Inc.
e5ce4208
GG		 5 *
6 * Author: Graeme Gregory <gg@slimlogic.co.uk>
a7dddf27 7 * Author: Ian Lartey <ian@slimlogic.co.uk>
e5ce4208
GG		 8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 */
15
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/init.h>
19#include <linux/err.h>
20#include <linux/platform_device.h>
21#include <linux/regulator/driver.h>
22#include <linux/regulator/machine.h>
23#include <linux/slab.h>
24#include <linux/regmap.h>
25#include <linux/mfd/palmas.h>
a361cd9f
GG		 26#include <linux/of.h>
27#include <linux/of_platform.h>
28#include <linux/regulator/of_regulator.h>
e5ce4208
GG		 29
30struct regs_info {
31 char *name;
504382c9 32 char *sname;
e5ce4208
GG		 33 u8 vsel_addr;
34 u8 ctrl_addr;
35 u8 tstep_addr;
32b6d3f6 36 int sleep_id;
e5ce4208
GG		 37};
38
39static const struct regs_info palmas_regs_info[] = {
40 {
41 .name = "SMPS12",
504382c9 42 .sname = "smps1-in",
e5ce4208
GG		 43 .vsel_addr = PALMAS_SMPS12_VOLTAGE,
44 .ctrl_addr = PALMAS_SMPS12_CTRL,
45 .tstep_addr = PALMAS_SMPS12_TSTEP,
32b6d3f6 46 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS12,
e5ce4208
GG		 47 },
48 {
49 .name = "SMPS123",
504382c9 50 .sname = "smps1-in",
e5ce4208
GG		 51 .vsel_addr = PALMAS_SMPS12_VOLTAGE,
52 .ctrl_addr = PALMAS_SMPS12_CTRL,
53 .tstep_addr = PALMAS_SMPS12_TSTEP,
32b6d3f6 54 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS12,
e5ce4208
GG		 55 },
56 {
57 .name = "SMPS3",
504382c9 58 .sname = "smps3-in",
e5ce4208
GG		 59 .vsel_addr = PALMAS_SMPS3_VOLTAGE,
60 .ctrl_addr = PALMAS_SMPS3_CTRL,
32b6d3f6 61 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS3,
e5ce4208
GG		 62 },
63 {
64 .name = "SMPS45",
504382c9 65 .sname = "smps4-in",
e5ce4208
GG		 66 .vsel_addr = PALMAS_SMPS45_VOLTAGE,
67 .ctrl_addr = PALMAS_SMPS45_CTRL,
68 .tstep_addr = PALMAS_SMPS45_TSTEP,
32b6d3f6 69 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS45,
e5ce4208
GG		 70 },
71 {
72 .name = "SMPS457",
504382c9 73 .sname = "smps4-in",
e5ce4208
GG		 74 .vsel_addr = PALMAS_SMPS45_VOLTAGE,
75 .ctrl_addr = PALMAS_SMPS45_CTRL,
76 .tstep_addr = PALMAS_SMPS45_TSTEP,
32b6d3f6 77 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS45,
e5ce4208
GG		 78 },
79 {
80 .name = "SMPS6",
504382c9 81 .sname = "smps6-in",
e5ce4208
GG		 82 .vsel_addr = PALMAS_SMPS6_VOLTAGE,
83 .ctrl_addr = PALMAS_SMPS6_CTRL,
84 .tstep_addr = PALMAS_SMPS6_TSTEP,
32b6d3f6 85 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS6,
e5ce4208
GG		 86 },
87 {
88 .name = "SMPS7",
504382c9 89 .sname = "smps7-in",
e5ce4208
GG		 90 .vsel_addr = PALMAS_SMPS7_VOLTAGE,
91 .ctrl_addr = PALMAS_SMPS7_CTRL,
32b6d3f6 92 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS7,
e5ce4208
GG		 93 },
94 {
95 .name = "SMPS8",
504382c9 96 .sname = "smps8-in",
e5ce4208
GG		 97 .vsel_addr = PALMAS_SMPS8_VOLTAGE,
98 .ctrl_addr = PALMAS_SMPS8_CTRL,
99 .tstep_addr = PALMAS_SMPS8_TSTEP,
32b6d3f6 100 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS8,
e5ce4208
GG		 101 },
102 {
103 .name = "SMPS9",
504382c9 104 .sname = "smps9-in",
e5ce4208
GG		 105 .vsel_addr = PALMAS_SMPS9_VOLTAGE,
106 .ctrl_addr = PALMAS_SMPS9_CTRL,
32b6d3f6 107 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS9,
e5ce4208
GG		 108 },
109 {
77409d9b 110 .name = "SMPS10_OUT2",
504382c9 111 .sname = "smps10-in",
e31089c6 112 .ctrl_addr = PALMAS_SMPS10_CTRL,
32b6d3f6 113 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS10,
e5ce4208 114 },
77409d9b
KVA		 115 {
116 .name = "SMPS10_OUT1",
117 .sname = "smps10-out2",
118 .ctrl_addr = PALMAS_SMPS10_CTRL,
32b6d3f6 119 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS10,
77409d9b 120 },
e5ce4208
GG		 121 {
122 .name = "LDO1",
504382c9 123 .sname = "ldo1-in",
e5ce4208
GG		 124 .vsel_addr = PALMAS_LDO1_VOLTAGE,
125 .ctrl_addr = PALMAS_LDO1_CTRL,
32b6d3f6 126 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO1,
e5ce4208
GG		 127 },
128 {
129 .name = "LDO2",
504382c9 130 .sname = "ldo2-in",
e5ce4208
GG		 131 .vsel_addr = PALMAS_LDO2_VOLTAGE,
132 .ctrl_addr = PALMAS_LDO2_CTRL,
32b6d3f6 133 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO2,
e5ce4208
GG		 134 },
135 {
136 .name = "LDO3",
504382c9 137 .sname = "ldo3-in",
e5ce4208
GG		 138 .vsel_addr = PALMAS_LDO3_VOLTAGE,
139 .ctrl_addr = PALMAS_LDO3_CTRL,
32b6d3f6 140 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO3,
e5ce4208
GG		 141 },
142 {
143 .name = "LDO4",
504382c9 144 .sname = "ldo4-in",
e5ce4208
GG		 145 .vsel_addr = PALMAS_LDO4_VOLTAGE,
146 .ctrl_addr = PALMAS_LDO4_CTRL,
32b6d3f6 147 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO4,
e5ce4208
GG		 148 },
149 {
150 .name = "LDO5",
504382c9 151 .sname = "ldo5-in",
e5ce4208
GG		 152 .vsel_addr = PALMAS_LDO5_VOLTAGE,
153 .ctrl_addr = PALMAS_LDO5_CTRL,
32b6d3f6 154 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO5,
e5ce4208
GG		 155 },
156 {
157 .name = "LDO6",
504382c9 158 .sname = "ldo6-in",
e5ce4208
GG		 159 .vsel_addr = PALMAS_LDO6_VOLTAGE,
160 .ctrl_addr = PALMAS_LDO6_CTRL,
32b6d3f6 161 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO6,
e5ce4208
GG		 162 },
163 {
164 .name = "LDO7",
504382c9 165 .sname = "ldo7-in",
e5ce4208
GG		 166 .vsel_addr = PALMAS_LDO7_VOLTAGE,
167 .ctrl_addr = PALMAS_LDO7_CTRL,
32b6d3f6 168 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO7,
e5ce4208
GG		 169 },
170 {
171 .name = "LDO8",
504382c9 172 .sname = "ldo8-in",
e5ce4208
GG		 173 .vsel_addr = PALMAS_LDO8_VOLTAGE,
174 .ctrl_addr = PALMAS_LDO8_CTRL,
32b6d3f6 175 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO8,
e5ce4208
GG		 176 },
177 {
178 .name = "LDO9",
504382c9 179 .sname = "ldo9-in",
e5ce4208
GG		 180 .vsel_addr = PALMAS_LDO9_VOLTAGE,
181 .ctrl_addr = PALMAS_LDO9_CTRL,
32b6d3f6 182 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO9,
e5ce4208
GG		 183 },
184 {
185 .name = "LDOLN",
504382c9 186 .sname = "ldoln-in",
e5ce4208
GG		 187 .vsel_addr = PALMAS_LDOLN_VOLTAGE,
188 .ctrl_addr = PALMAS_LDOLN_CTRL,
32b6d3f6 189 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDOLN,
e5ce4208
GG		 190 },
191 {
192 .name = "LDOUSB",
504382c9 193 .sname = "ldousb-in",
e5ce4208
GG		 194 .vsel_addr = PALMAS_LDOUSB_VOLTAGE,
195 .ctrl_addr = PALMAS_LDOUSB_CTRL,
32b6d3f6 196 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDOUSB,
e5ce4208 197 },
aa07f027
LD		 198 {
199 .name = "REGEN1",
200 .ctrl_addr = PALMAS_REGEN1_CTRL,
32b6d3f6 201 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_REGEN1,
aa07f027
LD		 202 },
203 {
204 .name = "REGEN2",
205 .ctrl_addr = PALMAS_REGEN2_CTRL,
32b6d3f6 206 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_REGEN2,
aa07f027
LD		 207 },
208 {
209 .name = "REGEN3",
210 .ctrl_addr = PALMAS_REGEN3_CTRL,
32b6d3f6 211 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_REGEN3,
aa07f027
LD		 212 },
213 {
214 .name = "SYSEN1",
215 .ctrl_addr = PALMAS_SYSEN1_CTRL,
32b6d3f6 216 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SYSEN1,
aa07f027
LD		 217 },
218 {
219 .name = "SYSEN2",
220 .ctrl_addr = PALMAS_SYSEN2_CTRL,
32b6d3f6 221 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SYSEN2,
aa07f027 222 },
e5ce4208
GG		 223};
224
28d1e8cd
LD		 225static unsigned int palmas_smps_ramp_delay[4] = {0, 10000, 5000, 2500};
226
e5ce4208
GG		 227#define SMPS_CTRL_MODE_OFF 0x00
228#define SMPS_CTRL_MODE_ON 0x01
229#define SMPS_CTRL_MODE_ECO 0x02
230#define SMPS_CTRL_MODE_PWM 0x03
231
0f45aa84 232#define PALMAS_SMPS_NUM_VOLTAGES 122
e5ce4208
GG		 233#define PALMAS_SMPS10_NUM_VOLTAGES 2
234#define PALMAS_LDO_NUM_VOLTAGES 50
235
236#define SMPS10_VSEL (1<<3)
237#define SMPS10_BOOST_EN (1<<2)
238#define SMPS10_BYPASS_EN (1<<1)
239#define SMPS10_SWITCH_EN (1<<0)
240
241#define REGULATOR_SLAVE 0
242
243static int palmas_smps_read(struct palmas *palmas, unsigned int reg,
244 unsigned int *dest)
245{
246 unsigned int addr;
247
248 addr = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, reg);
249
250 return regmap_read(palmas->regmap[REGULATOR_SLAVE], addr, dest);
251}
252
253static int palmas_smps_write(struct palmas *palmas, unsigned int reg,
254 unsigned int value)
255{
256 unsigned int addr;
257
258 addr = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, reg);
259
260 return regmap_write(palmas->regmap[REGULATOR_SLAVE], addr, value);
261}
262
263static int palmas_ldo_read(struct palmas *palmas, unsigned int reg,
264 unsigned int *dest)
265{
266 unsigned int addr;
267
268 addr = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE, reg);
269
270 return regmap_read(palmas->regmap[REGULATOR_SLAVE], addr, dest);
271}
272
273static int palmas_ldo_write(struct palmas *palmas, unsigned int reg,
274 unsigned int value)
275{
276 unsigned int addr;
277
278 addr = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE, reg);
279
280 return regmap_write(palmas->regmap[REGULATOR_SLAVE], addr, value);
281}
282
283static int palmas_is_enabled_smps(struct regulator_dev *dev)
284{
285 struct palmas_pmic *pmic = rdev_get_drvdata(dev);
286 int id = rdev_get_id(dev);
287 unsigned int reg;
288
289 palmas_smps_read(pmic->palmas, palmas_regs_info[id].ctrl_addr, &reg);
290
291 reg &= PALMAS_SMPS12_CTRL_STATUS_MASK;
292 reg >>= PALMAS_SMPS12_CTRL_STATUS_SHIFT;
293
294 return !!(reg);
295}
296
297static int palmas_enable_smps(struct regulator_dev *dev)
298{
299 struct palmas_pmic *pmic = rdev_get_drvdata(dev);
300 int id = rdev_get_id(dev);
301 unsigned int reg;
302
303 palmas_smps_read(pmic->palmas, palmas_regs_info[id].ctrl_addr, &reg);
304
305 reg &= ~PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
51d3a0c9
LD		 306 if (pmic->current_reg_mode[id])
307 reg |= pmic->current_reg_mode[id];
308 else
309 reg |= SMPS_CTRL_MODE_ON;
e5ce4208
GG		 310
311 palmas_smps_write(pmic->palmas, palmas_regs_info[id].ctrl_addr, reg);
312
313 return 0;
314}
315
316static int palmas_disable_smps(struct regulator_dev *dev)
317{
318 struct palmas_pmic *pmic = rdev_get_drvdata(dev);
319 int id = rdev_get_id(dev);
320 unsigned int reg;
321
322 palmas_smps_read(pmic->palmas, palmas_regs_info[id].ctrl_addr, &reg);
323
324 reg &= ~PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
325
326 palmas_smps_write(pmic->palmas, palmas_regs_info[id].ctrl_addr, reg);
327
328 return 0;
329}
330
e5ce4208
GG		 331static int palmas_set_mode_smps(struct regulator_dev *dev, unsigned int mode)
332{
333 struct palmas_pmic *pmic = rdev_get_drvdata(dev);
334 int id = rdev_get_id(dev);
335 unsigned int reg;
51d3a0c9 336 bool rail_enable = true;
e5ce4208
GG		 337
338 palmas_smps_read(pmic->palmas, palmas_regs_info[id].ctrl_addr, &reg);
999f0c7c 339 reg &= ~PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
e5ce4208 340
51d3a0c9
LD		 341 if (reg == SMPS_CTRL_MODE_OFF)
342 rail_enable = false;
343
e5ce4208
GG		 344 switch (mode) {
345 case REGULATOR_MODE_NORMAL:
346 reg |= SMPS_CTRL_MODE_ON;
347 break;
348 case REGULATOR_MODE_IDLE:
349 reg |= SMPS_CTRL_MODE_ECO;
350 break;
351 case REGULATOR_MODE_FAST:
352 reg |= SMPS_CTRL_MODE_PWM;
353 break;
354 default:
355 return -EINVAL;
356 }
e5ce4208 357
51d3a0c9
LD		 358 pmic->current_reg_mode[id] = reg & PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
359 if (rail_enable)
360 palmas_smps_write(pmic->palmas,
361 palmas_regs_info[id].ctrl_addr, reg);
e5ce4208
GG		 362 return 0;
363}
364
365static unsigned int palmas_get_mode_smps(struct regulator_dev *dev)
366{
367 struct palmas_pmic *pmic = rdev_get_drvdata(dev);
368 int id = rdev_get_id(dev);
369 unsigned int reg;
370
51d3a0c9 371 reg = pmic->current_reg_mode[id] & PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
e5ce4208
GG		 372
373 switch (reg) {
374 case SMPS_CTRL_MODE_ON:
375 return REGULATOR_MODE_NORMAL;
376 case SMPS_CTRL_MODE_ECO:
377 return REGULATOR_MODE_IDLE;
378 case SMPS_CTRL_MODE_PWM:
379 return REGULATOR_MODE_FAST;
380 }
381
382 return 0;
383}
384
385static int palmas_list_voltage_smps(struct regulator_dev *dev,
386 unsigned selector)
387{
388 struct palmas_pmic *pmic = rdev_get_drvdata(dev);
389 int id = rdev_get_id(dev);
390 int mult = 1;
391
e5ce4208
GG		 392 /* Read the multiplier set in VSEL register to return
393 * the correct voltage.
394 */
395 if (pmic->range[id])
396 mult = 2;
397
ad02e846
AL		 398 if (selector == 0)
399 return 0;
400 else if (selector < 6)
401 return 500000 * mult;
402 else
403 /* Voltage is linear mapping starting from selector 6,
404 * volt = (0.49V + ((selector - 5) * 0.01V)) * RANGE
405 * RANGE is either x1 or x2
406 */
407 return (490000 + ((selector - 5) * 10000)) * mult;
e5ce4208
GG		 408}
409
410static int palmas_map_voltage_smps(struct regulator_dev *rdev,
411 int min_uV, int max_uV)
412{
8a165df7
AL		 413 struct palmas_pmic *pmic = rdev_get_drvdata(rdev);
414 int id = rdev_get_id(rdev);
e5ce4208
GG		 415 int ret, voltage;
416
8a165df7
AL		 417 if (min_uV == 0)
418 return 0;
419
420 if (pmic->range[id]) { /* RANGE is x2 */
421 if (min_uV < 1000000)
422 min_uV = 1000000;
ad02e846 423 ret = DIV_ROUND_UP(min_uV - 1000000, 20000) + 6;
8a165df7
AL		 424 } else { /* RANGE is x1 */
425 if (min_uV < 500000)
426 min_uV = 500000;
ad02e846 427 ret = DIV_ROUND_UP(min_uV - 500000, 10000) + 6;
8a165df7 428 }
e5ce4208
GG		 429
430 /* Map back into a voltage to verify we're still in bounds */
431 voltage = palmas_list_voltage_smps(rdev, ret);
432 if (voltage < min_uV || voltage > max_uV)
433 return -EINVAL;
434
435 return ret;
436}
437
28d1e8cd
LD		 438static int palma_smps_set_voltage_smps_time_sel(struct regulator_dev *rdev,
439 unsigned int old_selector, unsigned int new_selector)
440{
441 struct palmas_pmic *pmic = rdev_get_drvdata(rdev);
442 int id = rdev_get_id(rdev);
443 int old_uv, new_uv;
444 unsigned int ramp_delay = pmic->ramp_delay[id];
445
446 if (!ramp_delay)
447 return 0;
448
449 old_uv = palmas_list_voltage_smps(rdev, old_selector);
450 if (old_uv < 0)
451 return old_uv;
452
453 new_uv = palmas_list_voltage_smps(rdev, new_selector);
454 if (new_uv < 0)
455 return new_uv;
456
457 return DIV_ROUND_UP(abs(old_uv - new_uv), ramp_delay);
458}
459
460static int palmas_smps_set_ramp_delay(struct regulator_dev *rdev,
461 int ramp_delay)
462{
463 struct palmas_pmic *pmic = rdev_get_drvdata(rdev);
464 int id = rdev_get_id(rdev);
465 unsigned int reg = 0;
466 unsigned int addr = palmas_regs_info[id].tstep_addr;
467 int ret;
468
f22c2bae
AL		 469 /* SMPS3 and SMPS7 do not have tstep_addr setting */
470 switch (id) {
471 case PALMAS_REG_SMPS3:
472 case PALMAS_REG_SMPS7:
473 return 0;
474 }
475
28d1e8cd
LD		 476 if (ramp_delay <= 0)
477 reg = 0;
0ea34b57 478 else if (ramp_delay <= 2500)
28d1e8cd 479 reg = 3;
0ea34b57 480 else if (ramp_delay <= 5000)
28d1e8cd
LD		 481 reg = 2;
482 else
483 reg = 1;
484
485 ret = palmas_smps_write(pmic->palmas, addr, reg);
486 if (ret < 0) {
487 dev_err(pmic->palmas->dev, "TSTEP write failed: %d\n", ret);
488 return ret;
489 }
490
491 pmic->ramp_delay[id] = palmas_smps_ramp_delay[reg];
492 return ret;
493}
494
e5ce4208
GG		 495static struct regulator_ops palmas_ops_smps = {
496 .is_enabled = palmas_is_enabled_smps,
497 .enable = palmas_enable_smps,
498 .disable = palmas_disable_smps,
499 .set_mode = palmas_set_mode_smps,
500 .get_mode = palmas_get_mode_smps,
bdc4baac
AL		 501 .get_voltage_sel = regulator_get_voltage_sel_regmap,
502 .set_voltage_sel = regulator_set_voltage_sel_regmap,
e5ce4208
GG		 503 .list_voltage = palmas_list_voltage_smps,
504 .map_voltage = palmas_map_voltage_smps,
28d1e8cd
LD		 505 .set_voltage_time_sel = palma_smps_set_voltage_smps_time_sel,
506 .set_ramp_delay = palmas_smps_set_ramp_delay,
e5ce4208
GG		 507};
508
32b6d3f6
LD		 509static struct regulator_ops palmas_ops_ext_control_smps = {
510 .set_mode = palmas_set_mode_smps,
511 .get_mode = palmas_get_mode_smps,
512 .get_voltage_sel = regulator_get_voltage_sel_regmap,
513 .set_voltage_sel = regulator_set_voltage_sel_regmap,
514 .list_voltage = palmas_list_voltage_smps,
515 .map_voltage = palmas_map_voltage_smps,
516 .set_voltage_time_sel = palma_smps_set_voltage_smps_time_sel,
517 .set_ramp_delay = palmas_smps_set_ramp_delay,
518};
519
e5ce4208
GG		 520static struct regulator_ops palmas_ops_smps10 = {
521 .is_enabled = regulator_is_enabled_regmap,
522 .enable = regulator_enable_regmap,
523 .disable = regulator_disable_regmap,
524 .get_voltage_sel = regulator_get_voltage_sel_regmap,
525 .set_voltage_sel = regulator_set_voltage_sel_regmap,
8029a006
AL		 526 .list_voltage = regulator_list_voltage_linear,
527 .map_voltage = regulator_map_voltage_linear,
77409d9b
KVA		 528 .set_bypass = regulator_set_bypass_regmap,
529 .get_bypass = regulator_get_bypass_regmap,
e5ce4208
GG		 530};
531
532static int palmas_is_enabled_ldo(struct regulator_dev *dev)
533{
534 struct palmas_pmic *pmic = rdev_get_drvdata(dev);
535 int id = rdev_get_id(dev);
536 unsigned int reg;
537
538 palmas_ldo_read(pmic->palmas, palmas_regs_info[id].ctrl_addr, &reg);
539
540 reg &= PALMAS_LDO1_CTRL_STATUS;
541
542 return !!(reg);
543}
544
e5ce4208
GG		 545static struct regulator_ops palmas_ops_ldo = {
546 .is_enabled = palmas_is_enabled_ldo,
547 .enable = regulator_enable_regmap,
548 .disable = regulator_disable_regmap,
4a247a96
AL		 549 .get_voltage_sel = regulator_get_voltage_sel_regmap,
550 .set_voltage_sel = regulator_set_voltage_sel_regmap,
9119ff6a
AL		 551 .list_voltage = regulator_list_voltage_linear,
552 .map_voltage = regulator_map_voltage_linear,
e5ce4208
GG		 553};
554
32b6d3f6
LD		 555static struct regulator_ops palmas_ops_ext_control_ldo = {
556 .get_voltage_sel = regulator_get_voltage_sel_regmap,
557 .set_voltage_sel = regulator_set_voltage_sel_regmap,
558 .list_voltage = regulator_list_voltage_linear,
559 .map_voltage = regulator_map_voltage_linear,
560};
561
aa07f027
LD		 562static struct regulator_ops palmas_ops_extreg = {
563 .is_enabled = regulator_is_enabled_regmap,
564 .enable = regulator_enable_regmap,
565 .disable = regulator_disable_regmap,
566};
567
32b6d3f6
LD		 568static struct regulator_ops palmas_ops_ext_control_extreg = {
569};
570
571static int palmas_regulator_config_external(struct palmas *palmas, int id,
572 struct palmas_reg_init *reg_init)
573{
574 int sleep_id = palmas_regs_info[id].sleep_id;
575 int ret;
576
577 ret = palmas_ext_control_req_config(palmas, sleep_id,
578 reg_init->roof_floor, true);
579 if (ret < 0)
580 dev_err(palmas->dev,
581 "Ext control config for regulator %d failed %d\n",
582 id, ret);
583 return ret;
584}
585
e5ce4208
GG		 586/*
587 * setup the hardware based sleep configuration of the SMPS/LDO regulators
588 * from the platform data. This is different to the software based control
589 * supported by the regulator framework as it is controlled by toggling
590 * pins on the PMIC such as PREQ, SYSEN, ...
591 */
592static int palmas_smps_init(struct palmas *palmas, int id,
593 struct palmas_reg_init *reg_init)
594{
595 unsigned int reg;
596 unsigned int addr;
597 int ret;
598
599 addr = palmas_regs_info[id].ctrl_addr;
600
601 ret = palmas_smps_read(palmas, addr, &reg);
602 if (ret)
603 return ret;
604
fedd89b1 605 switch (id) {
77409d9b
KVA		 606 case PALMAS_REG_SMPS10_OUT1:
607 case PALMAS_REG_SMPS10_OUT2:
30590d04
LD		 608 reg &= ~PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK;
609 if (reg_init->mode_sleep)
fedd89b1
AL		 610 reg |= reg_init->mode_sleep <<
611 PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT;
fedd89b1
AL		 612 break;
613 default:
e5ce4208
GG		 614 if (reg_init->warm_reset)
615 reg |= PALMAS_SMPS12_CTRL_WR_S;
30590d04
LD		 616 else
617 reg &= ~PALMAS_SMPS12_CTRL_WR_S;
e5ce4208
GG		 618
619 if (reg_init->roof_floor)
620 reg |= PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN;
30590d04
LD		 621 else
622 reg &= ~PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN;
e5ce4208 623
30590d04
LD		 624 reg &= ~PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK;
625 if (reg_init->mode_sleep)
e5ce4208
GG		 626 reg |= reg_init->mode_sleep <<
627 PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT;
e5ce4208 628 }
fedd89b1 629
e5ce4208
GG		 630 ret = palmas_smps_write(palmas, addr, reg);
631 if (ret)
632 return ret;
633
e5ce4208
GG		 634 if (palmas_regs_info[id].vsel_addr && reg_init->vsel) {
635 addr = palmas_regs_info[id].vsel_addr;
636
637 reg = reg_init->vsel;
638
639 ret = palmas_smps_write(palmas, addr, reg);
640 if (ret)
641 return ret;
642 }
643
32b6d3f6
LD		 644 if (reg_init->roof_floor && (id != PALMAS_REG_SMPS10_OUT1) &&
645 (id != PALMAS_REG_SMPS10_OUT2)) {
646 /* Enable externally controlled regulator */
647 addr = palmas_regs_info[id].ctrl_addr;
648 ret = palmas_smps_read(palmas, addr, &reg);
649 if (ret < 0)
650 return ret;
e5ce4208 651
32b6d3f6
LD		 652 if (!(reg & PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK)) {
653 reg |= SMPS_CTRL_MODE_ON;
654 ret = palmas_smps_write(palmas, addr, reg);
655 if (ret < 0)
656 return ret;
657 }
658 return palmas_regulator_config_external(palmas, id, reg_init);
659 }
e5ce4208
GG		 660 return 0;
661}
662
663static int palmas_ldo_init(struct palmas *palmas, int id,
664 struct palmas_reg_init *reg_init)
665{
666 unsigned int reg;
667 unsigned int addr;
668 int ret;
669
670 addr = palmas_regs_info[id].ctrl_addr;
671
2735daeb 672 ret = palmas_ldo_read(palmas, addr, &reg);
e5ce4208
GG		 673 if (ret)
674 return ret;
675
676 if (reg_init->warm_reset)
677 reg |= PALMAS_LDO1_CTRL_WR_S;
30590d04
LD		 678 else
679 reg &= ~PALMAS_LDO1_CTRL_WR_S;
e5ce4208
GG		 680
681 if (reg_init->mode_sleep)
682 reg |= PALMAS_LDO1_CTRL_MODE_SLEEP;
30590d04
LD		 683 else
684 reg &= ~PALMAS_LDO1_CTRL_MODE_SLEEP;
e5ce4208 685
2735daeb 686 ret = palmas_ldo_write(palmas, addr, reg);
e5ce4208
GG		 687 if (ret)
688 return ret;
689
32b6d3f6
LD		 690 if (reg_init->roof_floor) {
691 /* Enable externally controlled regulator */
692 addr = palmas_regs_info[id].ctrl_addr;
693 ret = palmas_update_bits(palmas, PALMAS_LDO_BASE,
694 addr, PALMAS_LDO1_CTRL_MODE_ACTIVE,
695 PALMAS_LDO1_CTRL_MODE_ACTIVE);
696 if (ret < 0) {
697 dev_err(palmas->dev,
698 "LDO Register 0x%02x update failed %d\n",
699 addr, ret);
700 return ret;
701 }
702 return palmas_regulator_config_external(palmas, id, reg_init);
703 }
e5ce4208
GG		 704 return 0;
705}
706
aa07f027
LD		 707static int palmas_extreg_init(struct palmas *palmas, int id,
708 struct palmas_reg_init *reg_init)
709{
710 unsigned int addr;
711 int ret;
712 unsigned int val = 0;
713
714 addr = palmas_regs_info[id].ctrl_addr;
715
716 if (reg_init->mode_sleep)
717 val = PALMAS_REGEN1_CTRL_MODE_SLEEP;
718
719 ret = palmas_update_bits(palmas, PALMAS_RESOURCE_BASE,
720 addr, PALMAS_REGEN1_CTRL_MODE_SLEEP, val);
721 if (ret < 0) {
722 dev_err(palmas->dev, "Resource reg 0x%02x update failed %d\n",
723 addr, ret);
724 return ret;
725 }
32b6d3f6
LD		 726
727 if (reg_init->roof_floor) {
728 /* Enable externally controlled regulator */
729 addr = palmas_regs_info[id].ctrl_addr;
730 ret = palmas_update_bits(palmas, PALMAS_RESOURCE_BASE,
731 addr, PALMAS_REGEN1_CTRL_MODE_ACTIVE,
732 PALMAS_REGEN1_CTRL_MODE_ACTIVE);
733 if (ret < 0) {
734 dev_err(palmas->dev,
735 "Resource Register 0x%02x update failed %d\n",
736 addr, ret);
737 return ret;
738 }
739 return palmas_regulator_config_external(palmas, id, reg_init);
740 }
aa07f027
LD		 741 return 0;
742}
743
17c11a76
LD		 744static void palmas_enable_ldo8_track(struct palmas *palmas)
745{
746 unsigned int reg;
747 unsigned int addr;
748 int ret;
749
750 addr = palmas_regs_info[PALMAS_REG_LDO8].ctrl_addr;
751
752 ret = palmas_ldo_read(palmas, addr, &reg);
753 if (ret) {
754 dev_err(palmas->dev, "Error in reading ldo8 control reg\n");
755 return;
756 }
757
758 reg |= PALMAS_LDO8_CTRL_LDO_TRACKING_EN;
759 ret = palmas_ldo_write(palmas, addr, reg);
760 if (ret < 0) {
761 dev_err(palmas->dev, "Error in enabling tracking mode\n");
762 return;
763 }
764 /*
765 * When SMPS45 is set to off and LDO8 tracking is enabled, the LDO8
766 * output is defined by the LDO8_VOLTAGE.VSEL register divided by two,
767 * and can be set from 0.45 to 1.65 V.
768 */
769 addr = palmas_regs_info[PALMAS_REG_LDO8].vsel_addr;
770 ret = palmas_ldo_read(palmas, addr, &reg);
771 if (ret) {
772 dev_err(palmas->dev, "Error in reading ldo8 voltage reg\n");
773 return;
774 }
775
776 reg = (reg << 1) & PALMAS_LDO8_VOLTAGE_VSEL_MASK;
777 ret = palmas_ldo_write(palmas, addr, reg);
778 if (ret < 0)
779 dev_err(palmas->dev, "Error in setting ldo8 voltage reg\n");
780
781 return;
782}
783
a361cd9f
GG		 784static struct of_regulator_match palmas_matches[] = {
785 { .name = "smps12", },
786 { .name = "smps123", },
787 { .name = "smps3", },
788 { .name = "smps45", },
789 { .name = "smps457", },
790 { .name = "smps6", },
791 { .name = "smps7", },
792 { .name = "smps8", },
793 { .name = "smps9", },
77409d9b
KVA		 794 { .name = "smps10_out2", },
795 { .name = "smps10_out1", },
a361cd9f
GG		 796 { .name = "ldo1", },
797 { .name = "ldo2", },
798 { .name = "ldo3", },
799 { .name = "ldo4", },
800 { .name = "ldo5", },
801 { .name = "ldo6", },
802 { .name = "ldo7", },
803 { .name = "ldo8", },
804 { .name = "ldo9", },
805 { .name = "ldoln", },
806 { .name = "ldousb", },
aa07f027
LD		 807 { .name = "regen1", },
808 { .name = "regen2", },
809 { .name = "regen3", },
810 { .name = "sysen1", },
811 { .name = "sysen2", },
a361cd9f
GG		 812};
813
a5023574 814static void palmas_dt_to_pdata(struct device *dev,
a361cd9f
GG		 815 struct device_node *node,
816 struct palmas_pmic_platform_data *pdata)
817{
818 struct device_node *regulators;
819 u32 prop;
820 int idx, ret;
821
c92f5dd2 822 node = of_node_get(node);
acc1ccad 823 regulators = of_get_child_by_name(node, "regulators");
a361cd9f
GG		 824 if (!regulators) {
825 dev_info(dev, "regulator node not found\n");
826 return;
827 }
828
829 ret = of_regulator_match(dev, regulators, palmas_matches,
830 PALMAS_NUM_REGS);
c92f5dd2 831 of_node_put(regulators);
a361cd9f
GG		 832 if (ret < 0) {
833 dev_err(dev, "Error parsing regulator init data: %d\n", ret);
834 return;
835 }
836
837 for (idx = 0; idx < PALMAS_NUM_REGS; idx++) {
838 if (!palmas_matches[idx].init_data ||
839 !palmas_matches[idx].of_node)
840 continue;
841
842 pdata->reg_data[idx] = palmas_matches[idx].init_data;
843
844 pdata->reg_init[idx] = devm_kzalloc(dev,
845 sizeof(struct palmas_reg_init), GFP_KERNEL);
846
7be859f7 847 pdata->reg_init[idx]->warm_reset =
71f2146f
AL		 848 of_property_read_bool(palmas_matches[idx].of_node,
849 "ti,warm-reset");
a361cd9f 850
32b6d3f6
LD		 851 ret = of_property_read_u32(palmas_matches[idx].of_node,
852 "ti,roof-floor", &prop);
853 /* EINVAL: Property not found */
854 if (ret != -EINVAL) {
855 int econtrol;
856
857 /* use default value, when no value is specified */
858 econtrol = PALMAS_EXT_CONTROL_NSLEEP;
859 if (!ret) {
860 switch (prop) {
861 case 1:
862 econtrol = PALMAS_EXT_CONTROL_ENABLE1;
863 break;
864 case 2:
865 econtrol = PALMAS_EXT_CONTROL_ENABLE2;
866 break;
867 case 3:
868 econtrol = PALMAS_EXT_CONTROL_NSLEEP;
869 break;
870 default:
871 WARN_ON(1);
872 dev_warn(dev,
873 "%s: Invalid roof-floor option: %u\n",
874 palmas_matches[idx].name, prop);
875 break;
876 }
877 }
878 pdata->reg_init[idx]->roof_floor = econtrol;
879 }
a361cd9f
GG		 880
881 ret = of_property_read_u32(palmas_matches[idx].of_node,
3c870e3f 882 "ti,mode-sleep", &prop);
a361cd9f
GG		 883 if (!ret)
884 pdata->reg_init[idx]->mode_sleep = prop;
885
7be859f7
GG		 886 ret = of_property_read_bool(palmas_matches[idx].of_node,
887 "ti,smps-range");
888 if (ret)
889 pdata->reg_init[idx]->vsel =
890 PALMAS_SMPS12_VOLTAGE_RANGE;
a361cd9f 891
17c11a76
LD		 892 if (idx == PALMAS_REG_LDO8)
893 pdata->enable_ldo8_tracking = of_property_read_bool(
894 palmas_matches[idx].of_node,
895 "ti,enable-ldo8-tracking");
a361cd9f
GG		 896 }
897
7be859f7 898 pdata->ldo6_vibrator = of_property_read_bool(node, "ti,ldo6-vibrator");
a361cd9f
GG		 899}
900
901
bbcf50b1 902static int palmas_regulators_probe(struct platform_device *pdev)
e5ce4208
GG		 903{
904 struct palmas *palmas = dev_get_drvdata(pdev->dev.parent);
dff91d0b 905 struct palmas_pmic_platform_data *pdata = dev_get_platdata(&pdev->dev);
a361cd9f 906 struct device_node *node = pdev->dev.of_node;
e5ce4208
GG		 907 struct regulator_dev *rdev;
908 struct regulator_config config = { };
909 struct palmas_pmic *pmic;
910 struct palmas_reg_init *reg_init;
911 int id = 0, ret;
912 unsigned int addr, reg;
913
a361cd9f
GG		 914 if (node && !pdata) {
915 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
916
917 if (!pdata)
918 return -ENOMEM;
919
920 palmas_dt_to_pdata(&pdev->dev, node, pdata);
921 }
e5ce4208
GG		 922
923 pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL);
924 if (!pmic)
925 return -ENOMEM;
926
927 pmic->dev = &pdev->dev;
928 pmic->palmas = palmas;
929 palmas->pmic = pmic;
930 platform_set_drvdata(pdev, pmic);
931
932 ret = palmas_smps_read(palmas, PALMAS_SMPS_CTRL, &reg);
933 if (ret)
1c9d2d71 934 return ret;
e5ce4208
GG		 935
936 if (reg & PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN)
937 pmic->smps123 = 1;
938
939 if (reg & PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN)
940 pmic->smps457 = 1;
941
942 config.regmap = palmas->regmap[REGULATOR_SLAVE];
943 config.dev = &pdev->dev;
944 config.driver_data = pmic;
945
946 for (id = 0; id < PALMAS_REG_LDO1; id++) {
28d1e8cd 947 bool ramp_delay_support = false;
e5ce4208
GG		 948
949 /*
950 * Miss out regulators which are not available due
951 * to slaving configurations.
952 */
953 switch (id) {
954 case PALMAS_REG_SMPS12:
955 case PALMAS_REG_SMPS3:
956 if (pmic->smps123)
957 continue;
28d1e8cd
LD		 958 if (id == PALMAS_REG_SMPS12)
959 ramp_delay_support = true;
e5ce4208
GG		 960 break;
961 case PALMAS_REG_SMPS123:
962 if (!pmic->smps123)
963 continue;
28d1e8cd 964 ramp_delay_support = true;
e5ce4208
GG		 965 break;
966 case PALMAS_REG_SMPS45:
967 case PALMAS_REG_SMPS7:
968 if (pmic->smps457)
969 continue;
28d1e8cd
LD		 970 if (id == PALMAS_REG_SMPS45)
971 ramp_delay_support = true;
e5ce4208
GG		 972 break;
973 case PALMAS_REG_SMPS457:
974 if (!pmic->smps457)
975 continue;
28d1e8cd
LD		 976 ramp_delay_support = true;
977 break;
77409d9b
KVA		 978 case PALMAS_REG_SMPS10_OUT1:
979 case PALMAS_REG_SMPS10_OUT2:
1ffb0be3
K		 980 if (!PALMAS_PMIC_HAS(palmas, SMPS10_BOOST))
981 continue;
28d1e8cd
LD		 982 }
983
3f4d6364 984 if ((id == PALMAS_REG_SMPS6) || (id == PALMAS_REG_SMPS8))
28d1e8cd
LD		 985 ramp_delay_support = true;
986
987 if (ramp_delay_support) {
988 addr = palmas_regs_info[id].tstep_addr;
989 ret = palmas_smps_read(pmic->palmas, addr, &reg);
990 if (ret < 0) {
991 dev_err(&pdev->dev,
992 "reading TSTEP reg failed: %d\n", ret);
51c86b3e 993 return ret;
28d1e8cd
LD		 994 }
995 pmic->desc[id].ramp_delay =
996 palmas_smps_ramp_delay[reg & 0x3];
997 pmic->ramp_delay[id] = pmic->desc[id].ramp_delay;
e5ce4208
GG		 998 }
999
bdc4baac
AL		 1000 /* Initialise sleep/init values from platform data */
1001 if (pdata && pdata->reg_init[id]) {
1002 reg_init = pdata->reg_init[id];
1003 ret = palmas_smps_init(palmas, id, reg_init);
1004 if (ret)
51c86b3e 1005 return ret;
32b6d3f6
LD		 1006 } else {
1007 reg_init = NULL;
bdc4baac
AL		 1008 }
1009
e5ce4208
GG		 1010 /* Register the regulators */
1011 pmic->desc[id].name = palmas_regs_info[id].name;
1012 pmic->desc[id].id = id;
1013
fedd89b1 1014 switch (id) {
77409d9b
KVA		 1015 case PALMAS_REG_SMPS10_OUT1:
1016 case PALMAS_REG_SMPS10_OUT2:
e5ce4208
GG		 1017 pmic->desc[id].n_voltages = PALMAS_SMPS10_NUM_VOLTAGES;
1018 pmic->desc[id].ops = &palmas_ops_smps10;
12565b16
AL		 1019 pmic->desc[id].vsel_reg =
1020 PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
1021 PALMAS_SMPS10_CTRL);
e5ce4208 1022 pmic->desc[id].vsel_mask = SMPS10_VSEL;
a68de074
GG		 1023 pmic->desc[id].enable_reg =
1024 PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
f232168d 1025 PALMAS_SMPS10_CTRL);
77409d9b
KVA		 1026 if (id == PALMAS_REG_SMPS10_OUT1)
1027 pmic->desc[id].enable_mask = SMPS10_SWITCH_EN;
1028 else
1029 pmic->desc[id].enable_mask = SMPS10_BOOST_EN;
1030 pmic->desc[id].bypass_reg =
1031 PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
1032 PALMAS_SMPS10_CTRL);
1033 pmic->desc[id].bypass_mask = SMPS10_BYPASS_EN;
8029a006
AL		 1034 pmic->desc[id].min_uV = 3750000;
1035 pmic->desc[id].uV_step = 1250000;
fedd89b1
AL		 1036 break;
1037 default:
bdc4baac
AL		 1038 /*
1039 * Read and store the RANGE bit for later use
1040 * This must be done before regulator is probed,
51d3a0c9
LD		 1041 * otherwise we error in probe with unsupportable
1042 * ranges. Read the current smps mode for later use.
bdc4baac 1043 */
e5ce4208
GG		 1044 addr = palmas_regs_info[id].vsel_addr;
1045
1046 ret = palmas_smps_read(pmic->palmas, addr, &reg);
1047 if (ret)
51c86b3e 1048 return ret;
e5ce4208
GG		 1049 if (reg & PALMAS_SMPS12_VOLTAGE_RANGE)
1050 pmic->range[id] = 1;
bdc4baac 1051
32b6d3f6
LD		 1052 if (reg_init && reg_init->roof_floor)
1053 pmic->desc[id].ops =
1054 &palmas_ops_ext_control_smps;
1055 else
1056 pmic->desc[id].ops = &palmas_ops_smps;
bdc4baac
AL		 1057 pmic->desc[id].n_voltages = PALMAS_SMPS_NUM_VOLTAGES;
1058 pmic->desc[id].vsel_reg =
1059 PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
1060 palmas_regs_info[id].vsel_addr);
1061 pmic->desc[id].vsel_mask =
1062 PALMAS_SMPS12_VOLTAGE_VSEL_MASK;
51d3a0c9
LD		 1063
1064 /* Read the smps mode for later use. */
1065 addr = palmas_regs_info[id].ctrl_addr;
1066 ret = palmas_smps_read(pmic->palmas, addr, &reg);
1067 if (ret)
51c86b3e 1068 return ret;
51d3a0c9
LD		 1069 pmic->current_reg_mode[id] = reg &
1070 PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
e5ce4208
GG		 1071 }
1072
bdc4baac
AL		 1073 pmic->desc[id].type = REGULATOR_VOLTAGE;
1074 pmic->desc[id].owner = THIS_MODULE;
1075
a361cd9f 1076 if (pdata)
e5ce4208
GG		 1077 config.init_data = pdata->reg_data[id];
1078 else
1079 config.init_data = NULL;
1080
504382c9 1081 pmic->desc[id].supply_name = palmas_regs_info[id].sname;
a361cd9f
GG		 1082 config.of_node = palmas_matches[id].of_node;
1083
51c86b3e
SK		 1084 rdev = devm_regulator_register(&pdev->dev, &pmic->desc[id],
1085 &config);
e5ce4208
GG		 1086 if (IS_ERR(rdev)) {
1087 dev_err(&pdev->dev,
1088 "failed to register %s regulator\n",
1089 pdev->name);
51c86b3e 1090 return PTR_ERR(rdev);
e5ce4208
GG		 1091 }
1092
1093 /* Save regulator for cleanup */
1094 pmic->rdev[id] = rdev;
1095 }
1096
1097 /* Start this loop from the id left from previous loop */
1098 for (; id < PALMAS_NUM_REGS; id++) {
32b6d3f6
LD		 1099 if (pdata && pdata->reg_init[id])
1100 reg_init = pdata->reg_init[id];
1101 else
1102 reg_init = NULL;
e5ce4208
GG		 1103
1104 /* Miss out regulators which are not available due
1105 * to alternate functions.
1106 */
1107
1108 /* Register the regulators */
1109 pmic->desc[id].name = palmas_regs_info[id].name;
1110 pmic->desc[id].id = id;
e5ce4208
GG		 1111 pmic->desc[id].type = REGULATOR_VOLTAGE;
1112 pmic->desc[id].owner = THIS_MODULE;
aa07f027
LD		 1113
1114 if (id < PALMAS_REG_REGEN1) {
1115 pmic->desc[id].n_voltages = PALMAS_LDO_NUM_VOLTAGES;
32b6d3f6
LD		 1116 if (reg_init && reg_init->roof_floor)
1117 pmic->desc[id].ops =
1118 &palmas_ops_ext_control_ldo;
1119 else
1120 pmic->desc[id].ops = &palmas_ops_ldo;
aa07f027
LD		 1121 pmic->desc[id].min_uV = 900000;
1122 pmic->desc[id].uV_step = 50000;
1123 pmic->desc[id].linear_min_sel = 1;
087d30e3 1124 pmic->desc[id].enable_time = 500;
aa07f027
LD		 1125 pmic->desc[id].vsel_reg =
1126 PALMAS_BASE_TO_REG(PALMAS_LDO_BASE,
4a247a96 1127 palmas_regs_info[id].vsel_addr);
aa07f027
LD		 1128 pmic->desc[id].vsel_mask =
1129 PALMAS_LDO1_VOLTAGE_VSEL_MASK;
1130 pmic->desc[id].enable_reg =
1131 PALMAS_BASE_TO_REG(PALMAS_LDO_BASE,
1132 palmas_regs_info[id].ctrl_addr);
1133 pmic->desc[id].enable_mask =
1134 PALMAS_LDO1_CTRL_MODE_ACTIVE;
17c11a76
LD		 1135
1136 /* Check if LDO8 is in tracking mode or not */
1137 if (pdata && (id == PALMAS_REG_LDO8) &&
1138 pdata->enable_ldo8_tracking) {
1139 palmas_enable_ldo8_track(palmas);
3df4a81c 1140 pmic->desc[id].min_uV = 450000;
17c11a76
LD		 1141 pmic->desc[id].uV_step = 25000;
1142 }
087d30e3
LD		 1143
1144 /* LOD6 in vibrator mode will have enable time 2000us */
1145 if (pdata && pdata->ldo6_vibrator &&
1146 (id == PALMAS_REG_LDO6))
1147 pmic->desc[id].enable_time = 2000;
aa07f027
LD		 1148 } else {
1149 pmic->desc[id].n_voltages = 1;
32b6d3f6
LD		 1150 if (reg_init && reg_init->roof_floor)
1151 pmic->desc[id].ops =
1152 &palmas_ops_ext_control_extreg;
1153 else
1154 pmic->desc[id].ops = &palmas_ops_extreg;
aa07f027
LD		 1155 pmic->desc[id].enable_reg =
1156 PALMAS_BASE_TO_REG(PALMAS_RESOURCE_BASE,
a68de074 1157 palmas_regs_info[id].ctrl_addr);
aa07f027
LD		 1158 pmic->desc[id].enable_mask =
1159 PALMAS_REGEN1_CTRL_MODE_ACTIVE;
1160 }
e5ce4208 1161
a361cd9f 1162 if (pdata)
e5ce4208
GG		 1163 config.init_data = pdata->reg_data[id];
1164 else
1165 config.init_data = NULL;
1166
504382c9 1167 pmic->desc[id].supply_name = palmas_regs_info[id].sname;
a361cd9f
GG		 1168 config.of_node = palmas_matches[id].of_node;
1169
51c86b3e
SK		 1170 rdev = devm_regulator_register(&pdev->dev, &pmic->desc[id],
1171 &config);
e5ce4208
GG		 1172 if (IS_ERR(rdev)) {
1173 dev_err(&pdev->dev,
1174 "failed to register %s regulator\n",
1175 pdev->name);
51c86b3e 1176 return PTR_ERR(rdev);
e5ce4208
GG		 1177 }
1178
1179 /* Save regulator for cleanup */
1180 pmic->rdev[id] = rdev;
1181
1182 /* Initialise sleep/init values from platform data */
a361cd9f 1183 if (pdata) {
e5ce4208
GG		 1184 reg_init = pdata->reg_init[id];
1185 if (reg_init) {
aa07f027
LD		 1186 if (id < PALMAS_REG_REGEN1)
1187 ret = palmas_ldo_init(palmas,
1188 id, reg_init);
1189 else
1190 ret = palmas_extreg_init(palmas,
1191 id, reg_init);
cb2e45e3 1192 if (ret)
51c86b3e 1193 return ret;
e5ce4208
GG		 1194 }
1195 }
1196 }
1197
17c11a76 1198
e5ce4208 1199 return 0;
e5ce4208
GG		 1200}
1201
3d68dfe3 1202static struct of_device_id of_palmas_match_tbl[] = {
a361cd9f 1203 { .compatible = "ti,palmas-pmic", },
7be859f7
GG		 1204 { .compatible = "ti,twl6035-pmic", },
1205 { .compatible = "ti,twl6036-pmic", },
1206 { .compatible = "ti,twl6037-pmic", },
1207 { .compatible = "ti,tps65913-pmic", },
1208 { .compatible = "ti,tps65914-pmic", },
1209 { .compatible = "ti,tps80036-pmic", },
b5c46787 1210 { .compatible = "ti,tps659038-pmic", },
a361cd9f
GG		 1211 { /* end */ }
1212};
1213
e5ce4208
GG		 1214static struct platform_driver palmas_driver = {
1215 .driver = {
1216 .name = "palmas-pmic",
a361cd9f 1217 .of_match_table = of_palmas_match_tbl,
e5ce4208
GG		 1218 .owner = THIS_MODULE,
1219 },
bbcf50b1 1220 .probe = palmas_regulators_probe,
e5ce4208
GG		 1221};
1222
1223static int __init palmas_init(void)
1224{
1225 return platform_driver_register(&palmas_driver);
1226}
1227subsys_initcall(palmas_init);
1228
1229static void __exit palmas_exit(void)
1230{
1231 platform_driver_unregister(&palmas_driver);
1232}
1233module_exit(palmas_exit);
1234
1235MODULE_AUTHOR("Graeme Gregory <gg@slimlogic.co.uk>");
1236MODULE_DESCRIPTION("Palmas voltage regulator driver");
1237MODULE_LICENSE("GPL");
1238MODULE_ALIAS("platform:palmas-pmic");
a361cd9f 1239MODULE_DEVICE_TABLE(of, of_palmas_match_tbl);
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