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e5ce4208 GG |
1 | /* |
2 | * Driver for Regulator part of Palmas PMIC Chips | |
3 | * | |
7be859f7 | 4 | * Copyright 2011-2013 Texas Instruments Inc. |
e5ce4208 GG |
5 | * |
6 | * Author: Graeme Gregory <gg@slimlogic.co.uk> | |
a7dddf27 | 7 | * Author: Ian Lartey <ian@slimlogic.co.uk> |
e5ce4208 GG |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms of the GNU General Public License as published by the | |
11 | * Free Software Foundation; either version 2 of the License, or (at your | |
12 | * option) any later version. | |
13 | * | |
14 | */ | |
15 | ||
16 | #include <linux/kernel.h> | |
17 | #include <linux/module.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/err.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/regulator/driver.h> | |
22 | #include <linux/regulator/machine.h> | |
23 | #include <linux/slab.h> | |
24 | #include <linux/regmap.h> | |
25 | #include <linux/mfd/palmas.h> | |
a361cd9f GG |
26 | #include <linux/of.h> |
27 | #include <linux/of_platform.h> | |
28 | #include <linux/regulator/of_regulator.h> | |
e5ce4208 | 29 | |
dbabd624 | 30 | static const struct regulator_linear_range smps_low_ranges[] = { |
6b7f2d82 | 31 | REGULATOR_LINEAR_RANGE(0, 0x0, 0x0, 0), |
dbabd624 K |
32 | REGULATOR_LINEAR_RANGE(500000, 0x1, 0x6, 0), |
33 | REGULATOR_LINEAR_RANGE(510000, 0x7, 0x79, 10000), | |
34 | REGULATOR_LINEAR_RANGE(1650000, 0x7A, 0x7f, 0), | |
35 | }; | |
36 | ||
37 | static const struct regulator_linear_range smps_high_ranges[] = { | |
6b7f2d82 | 38 | REGULATOR_LINEAR_RANGE(0, 0x0, 0x0, 0), |
dbabd624 K |
39 | REGULATOR_LINEAR_RANGE(1000000, 0x1, 0x6, 0), |
40 | REGULATOR_LINEAR_RANGE(1020000, 0x7, 0x79, 20000), | |
41 | REGULATOR_LINEAR_RANGE(3300000, 0x7A, 0x7f, 0), | |
42 | }; | |
43 | ||
6839cd6f | 44 | static struct palmas_regs_info palmas_generic_regs_info[] = { |
e5ce4208 GG |
45 | { |
46 | .name = "SMPS12", | |
504382c9 | 47 | .sname = "smps1-in", |
e5ce4208 GG |
48 | .vsel_addr = PALMAS_SMPS12_VOLTAGE, |
49 | .ctrl_addr = PALMAS_SMPS12_CTRL, | |
50 | .tstep_addr = PALMAS_SMPS12_TSTEP, | |
32b6d3f6 | 51 | .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS12, |
e5ce4208 GG |
52 | }, |
53 | { | |
54 | .name = "SMPS123", | |
504382c9 | 55 | .sname = "smps1-in", |
e5ce4208 GG |
56 | .vsel_addr = PALMAS_SMPS12_VOLTAGE, |
57 | .ctrl_addr = PALMAS_SMPS12_CTRL, | |
58 | .tstep_addr = PALMAS_SMPS12_TSTEP, | |
32b6d3f6 | 59 | .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS12, |
e5ce4208 GG |
60 | }, |
61 | { | |
62 | .name = "SMPS3", | |
504382c9 | 63 | .sname = "smps3-in", |
e5ce4208 GG |
64 | .vsel_addr = PALMAS_SMPS3_VOLTAGE, |
65 | .ctrl_addr = PALMAS_SMPS3_CTRL, | |
32b6d3f6 | 66 | .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS3, |
e5ce4208 GG |
67 | }, |
68 | { | |
69 | .name = "SMPS45", | |
504382c9 | 70 | .sname = "smps4-in", |
e5ce4208 GG |
71 | .vsel_addr = PALMAS_SMPS45_VOLTAGE, |
72 | .ctrl_addr = PALMAS_SMPS45_CTRL, | |
73 | .tstep_addr = PALMAS_SMPS45_TSTEP, | |
32b6d3f6 | 74 | .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS45, |
e5ce4208 GG |
75 | }, |
76 | { | |
77 | .name = "SMPS457", | |
504382c9 | 78 | .sname = "smps4-in", |
e5ce4208 GG |
79 | .vsel_addr = PALMAS_SMPS45_VOLTAGE, |
80 | .ctrl_addr = PALMAS_SMPS45_CTRL, | |
81 | .tstep_addr = PALMAS_SMPS45_TSTEP, | |
32b6d3f6 | 82 | .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS45, |
e5ce4208 GG |
83 | }, |
84 | { | |
85 | .name = "SMPS6", | |
504382c9 | 86 | .sname = "smps6-in", |
e5ce4208 GG |
87 | .vsel_addr = PALMAS_SMPS6_VOLTAGE, |
88 | .ctrl_addr = PALMAS_SMPS6_CTRL, | |
89 | .tstep_addr = PALMAS_SMPS6_TSTEP, | |
32b6d3f6 | 90 | .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS6, |
e5ce4208 GG |
91 | }, |
92 | { | |
93 | .name = "SMPS7", | |
504382c9 | 94 | .sname = "smps7-in", |
e5ce4208 GG |
95 | .vsel_addr = PALMAS_SMPS7_VOLTAGE, |
96 | .ctrl_addr = PALMAS_SMPS7_CTRL, | |
32b6d3f6 | 97 | .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS7, |
e5ce4208 GG |
98 | }, |
99 | { | |
100 | .name = "SMPS8", | |
504382c9 | 101 | .sname = "smps8-in", |
e5ce4208 GG |
102 | .vsel_addr = PALMAS_SMPS8_VOLTAGE, |
103 | .ctrl_addr = PALMAS_SMPS8_CTRL, | |
104 | .tstep_addr = PALMAS_SMPS8_TSTEP, | |
32b6d3f6 | 105 | .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS8, |
e5ce4208 GG |
106 | }, |
107 | { | |
108 | .name = "SMPS9", | |
504382c9 | 109 | .sname = "smps9-in", |
e5ce4208 GG |
110 | .vsel_addr = PALMAS_SMPS9_VOLTAGE, |
111 | .ctrl_addr = PALMAS_SMPS9_CTRL, | |
32b6d3f6 | 112 | .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS9, |
e5ce4208 GG |
113 | }, |
114 | { | |
77409d9b | 115 | .name = "SMPS10_OUT2", |
504382c9 | 116 | .sname = "smps10-in", |
e31089c6 | 117 | .ctrl_addr = PALMAS_SMPS10_CTRL, |
32b6d3f6 | 118 | .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS10, |
e5ce4208 | 119 | }, |
77409d9b KVA |
120 | { |
121 | .name = "SMPS10_OUT1", | |
122 | .sname = "smps10-out2", | |
123 | .ctrl_addr = PALMAS_SMPS10_CTRL, | |
32b6d3f6 | 124 | .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS10, |
77409d9b | 125 | }, |
e5ce4208 GG |
126 | { |
127 | .name = "LDO1", | |
504382c9 | 128 | .sname = "ldo1-in", |
e5ce4208 GG |
129 | .vsel_addr = PALMAS_LDO1_VOLTAGE, |
130 | .ctrl_addr = PALMAS_LDO1_CTRL, | |
32b6d3f6 | 131 | .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO1, |
e5ce4208 GG |
132 | }, |
133 | { | |
134 | .name = "LDO2", | |
504382c9 | 135 | .sname = "ldo2-in", |
e5ce4208 GG |
136 | .vsel_addr = PALMAS_LDO2_VOLTAGE, |
137 | .ctrl_addr = PALMAS_LDO2_CTRL, | |
32b6d3f6 | 138 | .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO2, |
e5ce4208 GG |
139 | }, |
140 | { | |
141 | .name = "LDO3", | |
504382c9 | 142 | .sname = "ldo3-in", |
e5ce4208 GG |
143 | .vsel_addr = PALMAS_LDO3_VOLTAGE, |
144 | .ctrl_addr = PALMAS_LDO3_CTRL, | |
32b6d3f6 | 145 | .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO3, |
e5ce4208 GG |
146 | }, |
147 | { | |
148 | .name = "LDO4", | |
504382c9 | 149 | .sname = "ldo4-in", |
e5ce4208 GG |
150 | .vsel_addr = PALMAS_LDO4_VOLTAGE, |
151 | .ctrl_addr = PALMAS_LDO4_CTRL, | |
32b6d3f6 | 152 | .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO4, |
e5ce4208 GG |
153 | }, |
154 | { | |
155 | .name = "LDO5", | |
504382c9 | 156 | .sname = "ldo5-in", |
e5ce4208 GG |
157 | .vsel_addr = PALMAS_LDO5_VOLTAGE, |
158 | .ctrl_addr = PALMAS_LDO5_CTRL, | |
32b6d3f6 | 159 | .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO5, |
e5ce4208 GG |
160 | }, |
161 | { | |
162 | .name = "LDO6", | |
504382c9 | 163 | .sname = "ldo6-in", |
e5ce4208 GG |
164 | .vsel_addr = PALMAS_LDO6_VOLTAGE, |
165 | .ctrl_addr = PALMAS_LDO6_CTRL, | |
32b6d3f6 | 166 | .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO6, |
e5ce4208 GG |
167 | }, |
168 | { | |
169 | .name = "LDO7", | |
504382c9 | 170 | .sname = "ldo7-in", |
e5ce4208 GG |
171 | .vsel_addr = PALMAS_LDO7_VOLTAGE, |
172 | .ctrl_addr = PALMAS_LDO7_CTRL, | |
32b6d3f6 | 173 | .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO7, |
e5ce4208 GG |
174 | }, |
175 | { | |
176 | .name = "LDO8", | |
504382c9 | 177 | .sname = "ldo8-in", |
e5ce4208 GG |
178 | .vsel_addr = PALMAS_LDO8_VOLTAGE, |
179 | .ctrl_addr = PALMAS_LDO8_CTRL, | |
32b6d3f6 | 180 | .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO8, |
e5ce4208 GG |
181 | }, |
182 | { | |
183 | .name = "LDO9", | |
504382c9 | 184 | .sname = "ldo9-in", |
e5ce4208 GG |
185 | .vsel_addr = PALMAS_LDO9_VOLTAGE, |
186 | .ctrl_addr = PALMAS_LDO9_CTRL, | |
32b6d3f6 | 187 | .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO9, |
e5ce4208 GG |
188 | }, |
189 | { | |
190 | .name = "LDOLN", | |
504382c9 | 191 | .sname = "ldoln-in", |
e5ce4208 GG |
192 | .vsel_addr = PALMAS_LDOLN_VOLTAGE, |
193 | .ctrl_addr = PALMAS_LDOLN_CTRL, | |
32b6d3f6 | 194 | .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDOLN, |
e5ce4208 GG |
195 | }, |
196 | { | |
197 | .name = "LDOUSB", | |
504382c9 | 198 | .sname = "ldousb-in", |
e5ce4208 GG |
199 | .vsel_addr = PALMAS_LDOUSB_VOLTAGE, |
200 | .ctrl_addr = PALMAS_LDOUSB_CTRL, | |
32b6d3f6 | 201 | .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDOUSB, |
e5ce4208 | 202 | }, |
aa07f027 LD |
203 | { |
204 | .name = "REGEN1", | |
205 | .ctrl_addr = PALMAS_REGEN1_CTRL, | |
32b6d3f6 | 206 | .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_REGEN1, |
aa07f027 LD |
207 | }, |
208 | { | |
209 | .name = "REGEN2", | |
210 | .ctrl_addr = PALMAS_REGEN2_CTRL, | |
32b6d3f6 | 211 | .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_REGEN2, |
aa07f027 LD |
212 | }, |
213 | { | |
214 | .name = "REGEN3", | |
215 | .ctrl_addr = PALMAS_REGEN3_CTRL, | |
32b6d3f6 | 216 | .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_REGEN3, |
aa07f027 LD |
217 | }, |
218 | { | |
219 | .name = "SYSEN1", | |
220 | .ctrl_addr = PALMAS_SYSEN1_CTRL, | |
32b6d3f6 | 221 | .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SYSEN1, |
aa07f027 LD |
222 | }, |
223 | { | |
224 | .name = "SYSEN2", | |
225 | .ctrl_addr = PALMAS_SYSEN2_CTRL, | |
32b6d3f6 | 226 | .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SYSEN2, |
aa07f027 | 227 | }, |
e5ce4208 GG |
228 | }; |
229 | ||
e7cf34ef | 230 | static struct palmas_regs_info tps65917_regs_info[] = { |
d6f83370 K |
231 | { |
232 | .name = "SMPS1", | |
233 | .sname = "smps1-in", | |
234 | .vsel_addr = TPS65917_SMPS1_VOLTAGE, | |
235 | .ctrl_addr = TPS65917_SMPS1_CTRL, | |
236 | .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS1, | |
237 | }, | |
238 | { | |
239 | .name = "SMPS2", | |
240 | .sname = "smps2-in", | |
241 | .vsel_addr = TPS65917_SMPS2_VOLTAGE, | |
242 | .ctrl_addr = TPS65917_SMPS2_CTRL, | |
243 | .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS2, | |
244 | }, | |
245 | { | |
246 | .name = "SMPS3", | |
247 | .sname = "smps3-in", | |
248 | .vsel_addr = TPS65917_SMPS3_VOLTAGE, | |
249 | .ctrl_addr = TPS65917_SMPS3_CTRL, | |
250 | .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS3, | |
251 | }, | |
252 | { | |
253 | .name = "SMPS4", | |
254 | .sname = "smps4-in", | |
255 | .vsel_addr = TPS65917_SMPS4_VOLTAGE, | |
256 | .ctrl_addr = TPS65917_SMPS4_CTRL, | |
257 | .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS4, | |
258 | }, | |
259 | { | |
260 | .name = "SMPS5", | |
261 | .sname = "smps5-in", | |
262 | .vsel_addr = TPS65917_SMPS5_VOLTAGE, | |
263 | .ctrl_addr = TPS65917_SMPS5_CTRL, | |
264 | .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS5, | |
265 | }, | |
266 | { | |
267 | .name = "LDO1", | |
268 | .sname = "ldo1-in", | |
269 | .vsel_addr = TPS65917_LDO1_VOLTAGE, | |
270 | .ctrl_addr = TPS65917_LDO1_CTRL, | |
271 | .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO1, | |
272 | }, | |
273 | { | |
274 | .name = "LDO2", | |
275 | .sname = "ldo2-in", | |
276 | .vsel_addr = TPS65917_LDO2_VOLTAGE, | |
277 | .ctrl_addr = TPS65917_LDO2_CTRL, | |
278 | .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO2, | |
279 | }, | |
280 | { | |
281 | .name = "LDO3", | |
282 | .sname = "ldo3-in", | |
283 | .vsel_addr = TPS65917_LDO3_VOLTAGE, | |
284 | .ctrl_addr = TPS65917_LDO3_CTRL, | |
285 | .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO3, | |
286 | }, | |
287 | { | |
288 | .name = "LDO4", | |
289 | .sname = "ldo4-in", | |
290 | .vsel_addr = TPS65917_LDO4_VOLTAGE, | |
291 | .ctrl_addr = TPS65917_LDO4_CTRL, | |
292 | .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO4, | |
293 | }, | |
294 | { | |
295 | .name = "LDO5", | |
296 | .sname = "ldo5-in", | |
297 | .vsel_addr = TPS65917_LDO5_VOLTAGE, | |
298 | .ctrl_addr = TPS65917_LDO5_CTRL, | |
299 | .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO5, | |
300 | }, | |
301 | { | |
302 | .name = "REGEN1", | |
303 | .ctrl_addr = TPS65917_REGEN1_CTRL, | |
304 | .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_REGEN1, | |
305 | }, | |
306 | { | |
307 | .name = "REGEN2", | |
308 | .ctrl_addr = TPS65917_REGEN2_CTRL, | |
309 | .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_REGEN2, | |
310 | }, | |
311 | { | |
312 | .name = "REGEN3", | |
313 | .ctrl_addr = TPS65917_REGEN3_CTRL, | |
314 | .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_REGEN3, | |
315 | }, | |
316 | }; | |
317 | ||
cac9e916 K |
318 | #define EXTERNAL_REQUESTOR(_id, _offset, _pos) \ |
319 | [PALMAS_EXTERNAL_REQSTR_ID_##_id] = { \ | |
320 | .id = PALMAS_EXTERNAL_REQSTR_ID_##_id, \ | |
321 | .reg_offset = _offset, \ | |
322 | .bit_pos = _pos, \ | |
323 | } | |
324 | ||
4b09e17b | 325 | static struct palmas_sleep_requestor_info palma_sleep_req_info[] = { |
cac9e916 K |
326 | EXTERNAL_REQUESTOR(REGEN1, 0, 0), |
327 | EXTERNAL_REQUESTOR(REGEN2, 0, 1), | |
328 | EXTERNAL_REQUESTOR(SYSEN1, 0, 2), | |
329 | EXTERNAL_REQUESTOR(SYSEN2, 0, 3), | |
330 | EXTERNAL_REQUESTOR(CLK32KG, 0, 4), | |
331 | EXTERNAL_REQUESTOR(CLK32KGAUDIO, 0, 5), | |
332 | EXTERNAL_REQUESTOR(REGEN3, 0, 6), | |
333 | EXTERNAL_REQUESTOR(SMPS12, 1, 0), | |
334 | EXTERNAL_REQUESTOR(SMPS3, 1, 1), | |
335 | EXTERNAL_REQUESTOR(SMPS45, 1, 2), | |
336 | EXTERNAL_REQUESTOR(SMPS6, 1, 3), | |
337 | EXTERNAL_REQUESTOR(SMPS7, 1, 4), | |
338 | EXTERNAL_REQUESTOR(SMPS8, 1, 5), | |
339 | EXTERNAL_REQUESTOR(SMPS9, 1, 6), | |
340 | EXTERNAL_REQUESTOR(SMPS10, 1, 7), | |
341 | EXTERNAL_REQUESTOR(LDO1, 2, 0), | |
342 | EXTERNAL_REQUESTOR(LDO2, 2, 1), | |
343 | EXTERNAL_REQUESTOR(LDO3, 2, 2), | |
344 | EXTERNAL_REQUESTOR(LDO4, 2, 3), | |
345 | EXTERNAL_REQUESTOR(LDO5, 2, 4), | |
346 | EXTERNAL_REQUESTOR(LDO6, 2, 5), | |
347 | EXTERNAL_REQUESTOR(LDO7, 2, 6), | |
348 | EXTERNAL_REQUESTOR(LDO8, 2, 7), | |
349 | EXTERNAL_REQUESTOR(LDO9, 3, 0), | |
350 | EXTERNAL_REQUESTOR(LDOLN, 3, 1), | |
351 | EXTERNAL_REQUESTOR(LDOUSB, 3, 2), | |
352 | }; | |
353 | ||
d6f83370 K |
354 | #define EXTERNAL_REQUESTOR_TPS65917(_id, _offset, _pos) \ |
355 | [TPS65917_EXTERNAL_REQSTR_ID_##_id] = { \ | |
356 | .id = TPS65917_EXTERNAL_REQSTR_ID_##_id, \ | |
357 | .reg_offset = _offset, \ | |
358 | .bit_pos = _pos, \ | |
359 | } | |
360 | ||
361 | static struct palmas_sleep_requestor_info tps65917_sleep_req_info[] = { | |
362 | EXTERNAL_REQUESTOR_TPS65917(REGEN1, 0, 0), | |
363 | EXTERNAL_REQUESTOR_TPS65917(REGEN2, 0, 1), | |
364 | EXTERNAL_REQUESTOR_TPS65917(REGEN3, 0, 6), | |
365 | EXTERNAL_REQUESTOR_TPS65917(SMPS1, 1, 0), | |
366 | EXTERNAL_REQUESTOR_TPS65917(SMPS2, 1, 1), | |
367 | EXTERNAL_REQUESTOR_TPS65917(SMPS3, 1, 2), | |
368 | EXTERNAL_REQUESTOR_TPS65917(SMPS4, 1, 3), | |
369 | EXTERNAL_REQUESTOR_TPS65917(SMPS5, 1, 4), | |
370 | EXTERNAL_REQUESTOR_TPS65917(LDO1, 2, 0), | |
371 | EXTERNAL_REQUESTOR_TPS65917(LDO2, 2, 1), | |
372 | EXTERNAL_REQUESTOR_TPS65917(LDO3, 2, 2), | |
373 | EXTERNAL_REQUESTOR_TPS65917(LDO4, 2, 3), | |
374 | EXTERNAL_REQUESTOR_TPS65917(LDO5, 2, 4), | |
375 | }; | |
376 | ||
28d1e8cd LD |
377 | static unsigned int palmas_smps_ramp_delay[4] = {0, 10000, 5000, 2500}; |
378 | ||
e5ce4208 GG |
379 | #define SMPS_CTRL_MODE_OFF 0x00 |
380 | #define SMPS_CTRL_MODE_ON 0x01 | |
381 | #define SMPS_CTRL_MODE_ECO 0x02 | |
382 | #define SMPS_CTRL_MODE_PWM 0x03 | |
383 | ||
0f45aa84 | 384 | #define PALMAS_SMPS_NUM_VOLTAGES 122 |
e5ce4208 GG |
385 | #define PALMAS_SMPS10_NUM_VOLTAGES 2 |
386 | #define PALMAS_LDO_NUM_VOLTAGES 50 | |
387 | ||
388 | #define SMPS10_VSEL (1<<3) | |
389 | #define SMPS10_BOOST_EN (1<<2) | |
390 | #define SMPS10_BYPASS_EN (1<<1) | |
391 | #define SMPS10_SWITCH_EN (1<<0) | |
392 | ||
393 | #define REGULATOR_SLAVE 0 | |
394 | ||
395 | static int palmas_smps_read(struct palmas *palmas, unsigned int reg, | |
396 | unsigned int *dest) | |
397 | { | |
398 | unsigned int addr; | |
399 | ||
400 | addr = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, reg); | |
401 | ||
402 | return regmap_read(palmas->regmap[REGULATOR_SLAVE], addr, dest); | |
403 | } | |
404 | ||
405 | static int palmas_smps_write(struct palmas *palmas, unsigned int reg, | |
406 | unsigned int value) | |
407 | { | |
408 | unsigned int addr; | |
409 | ||
410 | addr = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, reg); | |
411 | ||
412 | return regmap_write(palmas->regmap[REGULATOR_SLAVE], addr, value); | |
413 | } | |
414 | ||
415 | static int palmas_ldo_read(struct palmas *palmas, unsigned int reg, | |
416 | unsigned int *dest) | |
417 | { | |
418 | unsigned int addr; | |
419 | ||
420 | addr = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE, reg); | |
421 | ||
422 | return regmap_read(palmas->regmap[REGULATOR_SLAVE], addr, dest); | |
423 | } | |
424 | ||
425 | static int palmas_ldo_write(struct palmas *palmas, unsigned int reg, | |
426 | unsigned int value) | |
427 | { | |
428 | unsigned int addr; | |
429 | ||
430 | addr = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE, reg); | |
431 | ||
432 | return regmap_write(palmas->regmap[REGULATOR_SLAVE], addr, value); | |
433 | } | |
434 | ||
e5ce4208 GG |
435 | static int palmas_set_mode_smps(struct regulator_dev *dev, unsigned int mode) |
436 | { | |
cf910b6b | 437 | int id = rdev_get_id(dev); |
e5ce4208 | 438 | struct palmas_pmic *pmic = rdev_get_drvdata(dev); |
cac9e916 | 439 | struct palmas_pmic_driver_data *ddata = pmic->palmas->pmic_ddata; |
cf910b6b | 440 | struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id]; |
e5ce4208 | 441 | unsigned int reg; |
51d3a0c9 | 442 | bool rail_enable = true; |
e5ce4208 | 443 | |
cf910b6b | 444 | palmas_smps_read(pmic->palmas, rinfo->ctrl_addr, ®); |
cac9e916 | 445 | |
999f0c7c | 446 | reg &= ~PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK; |
e5ce4208 | 447 | |
51d3a0c9 LD |
448 | if (reg == SMPS_CTRL_MODE_OFF) |
449 | rail_enable = false; | |
450 | ||
e5ce4208 GG |
451 | switch (mode) { |
452 | case REGULATOR_MODE_NORMAL: | |
453 | reg |= SMPS_CTRL_MODE_ON; | |
454 | break; | |
455 | case REGULATOR_MODE_IDLE: | |
456 | reg |= SMPS_CTRL_MODE_ECO; | |
457 | break; | |
458 | case REGULATOR_MODE_FAST: | |
459 | reg |= SMPS_CTRL_MODE_PWM; | |
460 | break; | |
461 | default: | |
462 | return -EINVAL; | |
463 | } | |
e5ce4208 | 464 | |
51d3a0c9 LD |
465 | pmic->current_reg_mode[id] = reg & PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK; |
466 | if (rail_enable) | |
cf910b6b | 467 | palmas_smps_write(pmic->palmas, rinfo->ctrl_addr, reg); |
318dbb02 NM |
468 | |
469 | /* Switch the enable value to ensure this is used for enable */ | |
470 | pmic->desc[id].enable_val = pmic->current_reg_mode[id]; | |
471 | ||
e5ce4208 GG |
472 | return 0; |
473 | } | |
474 | ||
475 | static unsigned int palmas_get_mode_smps(struct regulator_dev *dev) | |
476 | { | |
477 | struct palmas_pmic *pmic = rdev_get_drvdata(dev); | |
478 | int id = rdev_get_id(dev); | |
479 | unsigned int reg; | |
480 | ||
51d3a0c9 | 481 | reg = pmic->current_reg_mode[id] & PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK; |
e5ce4208 GG |
482 | |
483 | switch (reg) { | |
484 | case SMPS_CTRL_MODE_ON: | |
485 | return REGULATOR_MODE_NORMAL; | |
486 | case SMPS_CTRL_MODE_ECO: | |
487 | return REGULATOR_MODE_IDLE; | |
488 | case SMPS_CTRL_MODE_PWM: | |
489 | return REGULATOR_MODE_FAST; | |
490 | } | |
491 | ||
492 | return 0; | |
493 | } | |
494 | ||
28d1e8cd LD |
495 | static int palmas_smps_set_ramp_delay(struct regulator_dev *rdev, |
496 | int ramp_delay) | |
497 | { | |
cf910b6b | 498 | int id = rdev_get_id(rdev); |
28d1e8cd | 499 | struct palmas_pmic *pmic = rdev_get_drvdata(rdev); |
cac9e916 | 500 | struct palmas_pmic_driver_data *ddata = pmic->palmas->pmic_ddata; |
cf910b6b | 501 | struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id]; |
28d1e8cd | 502 | unsigned int reg = 0; |
28d1e8cd LD |
503 | int ret; |
504 | ||
f22c2bae AL |
505 | /* SMPS3 and SMPS7 do not have tstep_addr setting */ |
506 | switch (id) { | |
507 | case PALMAS_REG_SMPS3: | |
508 | case PALMAS_REG_SMPS7: | |
509 | return 0; | |
510 | } | |
511 | ||
28d1e8cd LD |
512 | if (ramp_delay <= 0) |
513 | reg = 0; | |
0ea34b57 | 514 | else if (ramp_delay <= 2500) |
28d1e8cd | 515 | reg = 3; |
0ea34b57 | 516 | else if (ramp_delay <= 5000) |
28d1e8cd LD |
517 | reg = 2; |
518 | else | |
519 | reg = 1; | |
520 | ||
cf910b6b | 521 | ret = palmas_smps_write(pmic->palmas, rinfo->tstep_addr, reg); |
28d1e8cd LD |
522 | if (ret < 0) { |
523 | dev_err(pmic->palmas->dev, "TSTEP write failed: %d\n", ret); | |
524 | return ret; | |
525 | } | |
526 | ||
527 | pmic->ramp_delay[id] = palmas_smps_ramp_delay[reg]; | |
528 | return ret; | |
529 | } | |
530 | ||
e5ce4208 | 531 | static struct regulator_ops palmas_ops_smps = { |
dbabd624 K |
532 | .is_enabled = regulator_is_enabled_regmap, |
533 | .enable = regulator_enable_regmap, | |
534 | .disable = regulator_disable_regmap, | |
e5ce4208 GG |
535 | .set_mode = palmas_set_mode_smps, |
536 | .get_mode = palmas_get_mode_smps, | |
bdc4baac AL |
537 | .get_voltage_sel = regulator_get_voltage_sel_regmap, |
538 | .set_voltage_sel = regulator_set_voltage_sel_regmap, | |
dbabd624 K |
539 | .list_voltage = regulator_list_voltage_linear_range, |
540 | .map_voltage = regulator_map_voltage_linear_range, | |
541 | .set_voltage_time_sel = regulator_set_voltage_time_sel, | |
28d1e8cd | 542 | .set_ramp_delay = palmas_smps_set_ramp_delay, |
e5ce4208 GG |
543 | }; |
544 | ||
32b6d3f6 LD |
545 | static struct regulator_ops palmas_ops_ext_control_smps = { |
546 | .set_mode = palmas_set_mode_smps, | |
547 | .get_mode = palmas_get_mode_smps, | |
548 | .get_voltage_sel = regulator_get_voltage_sel_regmap, | |
549 | .set_voltage_sel = regulator_set_voltage_sel_regmap, | |
dbabd624 K |
550 | .list_voltage = regulator_list_voltage_linear_range, |
551 | .map_voltage = regulator_map_voltage_linear_range, | |
552 | .set_voltage_time_sel = regulator_set_voltage_time_sel, | |
32b6d3f6 LD |
553 | .set_ramp_delay = palmas_smps_set_ramp_delay, |
554 | }; | |
555 | ||
e5ce4208 GG |
556 | static struct regulator_ops palmas_ops_smps10 = { |
557 | .is_enabled = regulator_is_enabled_regmap, | |
558 | .enable = regulator_enable_regmap, | |
559 | .disable = regulator_disable_regmap, | |
560 | .get_voltage_sel = regulator_get_voltage_sel_regmap, | |
561 | .set_voltage_sel = regulator_set_voltage_sel_regmap, | |
8029a006 AL |
562 | .list_voltage = regulator_list_voltage_linear, |
563 | .map_voltage = regulator_map_voltage_linear, | |
77409d9b KVA |
564 | .set_bypass = regulator_set_bypass_regmap, |
565 | .get_bypass = regulator_get_bypass_regmap, | |
e5ce4208 GG |
566 | }; |
567 | ||
d6f83370 K |
568 | static struct regulator_ops tps65917_ops_smps = { |
569 | .is_enabled = regulator_is_enabled_regmap, | |
570 | .enable = regulator_enable_regmap, | |
571 | .disable = regulator_disable_regmap, | |
572 | .set_mode = palmas_set_mode_smps, | |
573 | .get_mode = palmas_get_mode_smps, | |
574 | .get_voltage_sel = regulator_get_voltage_sel_regmap, | |
575 | .set_voltage_sel = regulator_set_voltage_sel_regmap, | |
576 | .list_voltage = regulator_list_voltage_linear_range, | |
577 | .map_voltage = regulator_map_voltage_linear_range, | |
578 | .set_voltage_time_sel = regulator_set_voltage_time_sel, | |
579 | }; | |
580 | ||
581 | static struct regulator_ops tps65917_ops_ext_control_smps = { | |
582 | .set_mode = palmas_set_mode_smps, | |
583 | .get_mode = palmas_get_mode_smps, | |
584 | .get_voltage_sel = regulator_get_voltage_sel_regmap, | |
585 | .set_voltage_sel = regulator_set_voltage_sel_regmap, | |
586 | .list_voltage = regulator_list_voltage_linear_range, | |
587 | .map_voltage = regulator_map_voltage_linear_range, | |
588 | }; | |
589 | ||
e5ce4208 GG |
590 | static int palmas_is_enabled_ldo(struct regulator_dev *dev) |
591 | { | |
cf910b6b | 592 | int id = rdev_get_id(dev); |
e5ce4208 | 593 | struct palmas_pmic *pmic = rdev_get_drvdata(dev); |
cac9e916 | 594 | struct palmas_pmic_driver_data *ddata = pmic->palmas->pmic_ddata; |
cf910b6b | 595 | struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id]; |
e5ce4208 GG |
596 | unsigned int reg; |
597 | ||
cf910b6b | 598 | palmas_ldo_read(pmic->palmas, rinfo->ctrl_addr, ®); |
e5ce4208 GG |
599 | |
600 | reg &= PALMAS_LDO1_CTRL_STATUS; | |
601 | ||
602 | return !!(reg); | |
603 | } | |
604 | ||
e5ce4208 GG |
605 | static struct regulator_ops palmas_ops_ldo = { |
606 | .is_enabled = palmas_is_enabled_ldo, | |
607 | .enable = regulator_enable_regmap, | |
608 | .disable = regulator_disable_regmap, | |
4a247a96 AL |
609 | .get_voltage_sel = regulator_get_voltage_sel_regmap, |
610 | .set_voltage_sel = regulator_set_voltage_sel_regmap, | |
9119ff6a AL |
611 | .list_voltage = regulator_list_voltage_linear, |
612 | .map_voltage = regulator_map_voltage_linear, | |
e5ce4208 GG |
613 | }; |
614 | ||
b554e145 K |
615 | static struct regulator_ops palmas_ops_ldo9 = { |
616 | .is_enabled = palmas_is_enabled_ldo, | |
617 | .enable = regulator_enable_regmap, | |
618 | .disable = regulator_disable_regmap, | |
619 | .get_voltage_sel = regulator_get_voltage_sel_regmap, | |
620 | .set_voltage_sel = regulator_set_voltage_sel_regmap, | |
621 | .list_voltage = regulator_list_voltage_linear, | |
622 | .map_voltage = regulator_map_voltage_linear, | |
623 | .set_bypass = regulator_set_bypass_regmap, | |
624 | .get_bypass = regulator_get_bypass_regmap, | |
625 | }; | |
626 | ||
32b6d3f6 LD |
627 | static struct regulator_ops palmas_ops_ext_control_ldo = { |
628 | .get_voltage_sel = regulator_get_voltage_sel_regmap, | |
629 | .set_voltage_sel = regulator_set_voltage_sel_regmap, | |
630 | .list_voltage = regulator_list_voltage_linear, | |
631 | .map_voltage = regulator_map_voltage_linear, | |
632 | }; | |
633 | ||
aa07f027 LD |
634 | static struct regulator_ops palmas_ops_extreg = { |
635 | .is_enabled = regulator_is_enabled_regmap, | |
636 | .enable = regulator_enable_regmap, | |
637 | .disable = regulator_disable_regmap, | |
638 | }; | |
639 | ||
32b6d3f6 LD |
640 | static struct regulator_ops palmas_ops_ext_control_extreg = { |
641 | }; | |
642 | ||
d6f83370 K |
643 | static struct regulator_ops tps65917_ops_ldo = { |
644 | .is_enabled = palmas_is_enabled_ldo, | |
645 | .enable = regulator_enable_regmap, | |
646 | .disable = regulator_disable_regmap, | |
647 | .get_voltage_sel = regulator_get_voltage_sel_regmap, | |
648 | .set_voltage_sel = regulator_set_voltage_sel_regmap, | |
649 | .list_voltage = regulator_list_voltage_linear, | |
650 | .map_voltage = regulator_map_voltage_linear, | |
651 | .set_voltage_time_sel = regulator_set_voltage_time_sel, | |
652 | }; | |
653 | ||
b554e145 K |
654 | static struct regulator_ops tps65917_ops_ldo_1_2 = { |
655 | .is_enabled = palmas_is_enabled_ldo, | |
656 | .enable = regulator_enable_regmap, | |
657 | .disable = regulator_disable_regmap, | |
658 | .get_voltage_sel = regulator_get_voltage_sel_regmap, | |
659 | .set_voltage_sel = regulator_set_voltage_sel_regmap, | |
660 | .list_voltage = regulator_list_voltage_linear, | |
661 | .map_voltage = regulator_map_voltage_linear, | |
662 | .set_voltage_time_sel = regulator_set_voltage_time_sel, | |
663 | .set_bypass = regulator_set_bypass_regmap, | |
664 | .get_bypass = regulator_get_bypass_regmap, | |
665 | }; | |
666 | ||
32b6d3f6 LD |
667 | static int palmas_regulator_config_external(struct palmas *palmas, int id, |
668 | struct palmas_reg_init *reg_init) | |
669 | { | |
cf910b6b NM |
670 | struct palmas_pmic_driver_data *ddata = palmas->pmic_ddata; |
671 | struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id]; | |
32b6d3f6 LD |
672 | int ret; |
673 | ||
cf910b6b NM |
674 | ret = palmas_ext_control_req_config(palmas, rinfo->sleep_id, |
675 | reg_init->roof_floor, true); | |
32b6d3f6 LD |
676 | if (ret < 0) |
677 | dev_err(palmas->dev, | |
678 | "Ext control config for regulator %d failed %d\n", | |
679 | id, ret); | |
680 | return ret; | |
681 | } | |
682 | ||
e5ce4208 GG |
683 | /* |
684 | * setup the hardware based sleep configuration of the SMPS/LDO regulators | |
685 | * from the platform data. This is different to the software based control | |
686 | * supported by the regulator framework as it is controlled by toggling | |
687 | * pins on the PMIC such as PREQ, SYSEN, ... | |
688 | */ | |
689 | static int palmas_smps_init(struct palmas *palmas, int id, | |
690 | struct palmas_reg_init *reg_init) | |
691 | { | |
692 | unsigned int reg; | |
e5ce4208 | 693 | int ret; |
cac9e916 | 694 | struct palmas_pmic_driver_data *ddata = palmas->pmic_ddata; |
cf910b6b NM |
695 | struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id]; |
696 | unsigned int addr = rinfo->ctrl_addr; | |
e5ce4208 GG |
697 | |
698 | ret = palmas_smps_read(palmas, addr, ®); | |
699 | if (ret) | |
700 | return ret; | |
701 | ||
fedd89b1 | 702 | switch (id) { |
77409d9b KVA |
703 | case PALMAS_REG_SMPS10_OUT1: |
704 | case PALMAS_REG_SMPS10_OUT2: | |
30590d04 LD |
705 | reg &= ~PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK; |
706 | if (reg_init->mode_sleep) | |
fedd89b1 AL |
707 | reg |= reg_init->mode_sleep << |
708 | PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT; | |
fedd89b1 AL |
709 | break; |
710 | default: | |
e5ce4208 GG |
711 | if (reg_init->warm_reset) |
712 | reg |= PALMAS_SMPS12_CTRL_WR_S; | |
30590d04 LD |
713 | else |
714 | reg &= ~PALMAS_SMPS12_CTRL_WR_S; | |
e5ce4208 GG |
715 | |
716 | if (reg_init->roof_floor) | |
717 | reg |= PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN; | |
30590d04 LD |
718 | else |
719 | reg &= ~PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN; | |
e5ce4208 | 720 | |
30590d04 LD |
721 | reg &= ~PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK; |
722 | if (reg_init->mode_sleep) | |
e5ce4208 GG |
723 | reg |= reg_init->mode_sleep << |
724 | PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT; | |
e5ce4208 | 725 | } |
fedd89b1 | 726 | |
e5ce4208 GG |
727 | ret = palmas_smps_write(palmas, addr, reg); |
728 | if (ret) | |
729 | return ret; | |
730 | ||
cf910b6b | 731 | if (rinfo->vsel_addr && reg_init->vsel) { |
e5ce4208 GG |
732 | |
733 | reg = reg_init->vsel; | |
734 | ||
cf910b6b | 735 | ret = palmas_smps_write(palmas, rinfo->vsel_addr, reg); |
e5ce4208 GG |
736 | if (ret) |
737 | return ret; | |
738 | } | |
739 | ||
32b6d3f6 LD |
740 | if (reg_init->roof_floor && (id != PALMAS_REG_SMPS10_OUT1) && |
741 | (id != PALMAS_REG_SMPS10_OUT2)) { | |
742 | /* Enable externally controlled regulator */ | |
32b6d3f6 LD |
743 | ret = palmas_smps_read(palmas, addr, ®); |
744 | if (ret < 0) | |
745 | return ret; | |
e5ce4208 | 746 | |
32b6d3f6 LD |
747 | if (!(reg & PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK)) { |
748 | reg |= SMPS_CTRL_MODE_ON; | |
749 | ret = palmas_smps_write(palmas, addr, reg); | |
750 | if (ret < 0) | |
751 | return ret; | |
752 | } | |
753 | return palmas_regulator_config_external(palmas, id, reg_init); | |
754 | } | |
e5ce4208 GG |
755 | return 0; |
756 | } | |
757 | ||
758 | static int palmas_ldo_init(struct palmas *palmas, int id, | |
759 | struct palmas_reg_init *reg_init) | |
760 | { | |
761 | unsigned int reg; | |
762 | unsigned int addr; | |
763 | int ret; | |
cac9e916 | 764 | struct palmas_pmic_driver_data *ddata = palmas->pmic_ddata; |
cf910b6b | 765 | struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id]; |
cac9e916 | 766 | |
cf910b6b | 767 | addr = rinfo->ctrl_addr; |
e5ce4208 | 768 | |
2735daeb | 769 | ret = palmas_ldo_read(palmas, addr, ®); |
e5ce4208 GG |
770 | if (ret) |
771 | return ret; | |
772 | ||
773 | if (reg_init->warm_reset) | |
774 | reg |= PALMAS_LDO1_CTRL_WR_S; | |
30590d04 LD |
775 | else |
776 | reg &= ~PALMAS_LDO1_CTRL_WR_S; | |
e5ce4208 GG |
777 | |
778 | if (reg_init->mode_sleep) | |
779 | reg |= PALMAS_LDO1_CTRL_MODE_SLEEP; | |
30590d04 LD |
780 | else |
781 | reg &= ~PALMAS_LDO1_CTRL_MODE_SLEEP; | |
e5ce4208 | 782 | |
2735daeb | 783 | ret = palmas_ldo_write(palmas, addr, reg); |
e5ce4208 GG |
784 | if (ret) |
785 | return ret; | |
786 | ||
32b6d3f6 LD |
787 | if (reg_init->roof_floor) { |
788 | /* Enable externally controlled regulator */ | |
32b6d3f6 LD |
789 | ret = palmas_update_bits(palmas, PALMAS_LDO_BASE, |
790 | addr, PALMAS_LDO1_CTRL_MODE_ACTIVE, | |
791 | PALMAS_LDO1_CTRL_MODE_ACTIVE); | |
792 | if (ret < 0) { | |
793 | dev_err(palmas->dev, | |
794 | "LDO Register 0x%02x update failed %d\n", | |
795 | addr, ret); | |
796 | return ret; | |
797 | } | |
798 | return palmas_regulator_config_external(palmas, id, reg_init); | |
799 | } | |
e5ce4208 GG |
800 | return 0; |
801 | } | |
802 | ||
aa07f027 LD |
803 | static int palmas_extreg_init(struct palmas *palmas, int id, |
804 | struct palmas_reg_init *reg_init) | |
805 | { | |
806 | unsigned int addr; | |
807 | int ret; | |
808 | unsigned int val = 0; | |
cac9e916 | 809 | struct palmas_pmic_driver_data *ddata = palmas->pmic_ddata; |
cf910b6b | 810 | struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id]; |
cac9e916 | 811 | |
cf910b6b | 812 | addr = rinfo->ctrl_addr; |
aa07f027 LD |
813 | |
814 | if (reg_init->mode_sleep) | |
815 | val = PALMAS_REGEN1_CTRL_MODE_SLEEP; | |
816 | ||
817 | ret = palmas_update_bits(palmas, PALMAS_RESOURCE_BASE, | |
818 | addr, PALMAS_REGEN1_CTRL_MODE_SLEEP, val); | |
819 | if (ret < 0) { | |
820 | dev_err(palmas->dev, "Resource reg 0x%02x update failed %d\n", | |
821 | addr, ret); | |
822 | return ret; | |
823 | } | |
32b6d3f6 LD |
824 | |
825 | if (reg_init->roof_floor) { | |
826 | /* Enable externally controlled regulator */ | |
32b6d3f6 LD |
827 | ret = palmas_update_bits(palmas, PALMAS_RESOURCE_BASE, |
828 | addr, PALMAS_REGEN1_CTRL_MODE_ACTIVE, | |
829 | PALMAS_REGEN1_CTRL_MODE_ACTIVE); | |
830 | if (ret < 0) { | |
831 | dev_err(palmas->dev, | |
832 | "Resource Register 0x%02x update failed %d\n", | |
833 | addr, ret); | |
834 | return ret; | |
835 | } | |
836 | return palmas_regulator_config_external(palmas, id, reg_init); | |
837 | } | |
aa07f027 LD |
838 | return 0; |
839 | } | |
840 | ||
17c11a76 LD |
841 | static void palmas_enable_ldo8_track(struct palmas *palmas) |
842 | { | |
843 | unsigned int reg; | |
844 | unsigned int addr; | |
845 | int ret; | |
cac9e916 | 846 | struct palmas_pmic_driver_data *ddata = palmas->pmic_ddata; |
cf910b6b | 847 | struct palmas_regs_info *rinfo; |
cac9e916 | 848 | |
cf910b6b NM |
849 | rinfo = &ddata->palmas_regs_info[PALMAS_REG_LDO8]; |
850 | addr = rinfo->ctrl_addr; | |
17c11a76 LD |
851 | |
852 | ret = palmas_ldo_read(palmas, addr, ®); | |
853 | if (ret) { | |
854 | dev_err(palmas->dev, "Error in reading ldo8 control reg\n"); | |
855 | return; | |
856 | } | |
857 | ||
858 | reg |= PALMAS_LDO8_CTRL_LDO_TRACKING_EN; | |
859 | ret = palmas_ldo_write(palmas, addr, reg); | |
860 | if (ret < 0) { | |
861 | dev_err(palmas->dev, "Error in enabling tracking mode\n"); | |
862 | return; | |
863 | } | |
864 | /* | |
865 | * When SMPS45 is set to off and LDO8 tracking is enabled, the LDO8 | |
866 | * output is defined by the LDO8_VOLTAGE.VSEL register divided by two, | |
867 | * and can be set from 0.45 to 1.65 V. | |
868 | */ | |
cf910b6b | 869 | addr = rinfo->vsel_addr; |
17c11a76 LD |
870 | ret = palmas_ldo_read(palmas, addr, ®); |
871 | if (ret) { | |
872 | dev_err(palmas->dev, "Error in reading ldo8 voltage reg\n"); | |
873 | return; | |
874 | } | |
875 | ||
876 | reg = (reg << 1) & PALMAS_LDO8_VOLTAGE_VSEL_MASK; | |
877 | ret = palmas_ldo_write(palmas, addr, reg); | |
878 | if (ret < 0) | |
879 | dev_err(palmas->dev, "Error in setting ldo8 voltage reg\n"); | |
880 | ||
881 | return; | |
882 | } | |
883 | ||
cac9e916 K |
884 | static int palmas_ldo_registration(struct palmas_pmic *pmic, |
885 | struct palmas_pmic_driver_data *ddata, | |
886 | struct palmas_pmic_platform_data *pdata, | |
887 | const char *pdev_name, | |
888 | struct regulator_config config) | |
a361cd9f | 889 | { |
cac9e916 K |
890 | int id, ret; |
891 | struct regulator_dev *rdev; | |
892 | struct palmas_reg_init *reg_init; | |
cf910b6b | 893 | struct palmas_regs_info *rinfo; |
429222d0 | 894 | struct regulator_desc *desc; |
a361cd9f | 895 | |
cac9e916 K |
896 | for (id = ddata->ldo_begin; id < ddata->max_reg; id++) { |
897 | if (pdata && pdata->reg_init[id]) | |
898 | reg_init = pdata->reg_init[id]; | |
899 | else | |
900 | reg_init = NULL; | |
a361cd9f | 901 | |
cf910b6b | 902 | rinfo = &ddata->palmas_regs_info[id]; |
cac9e916 K |
903 | /* Miss out regulators which are not available due |
904 | * to alternate functions. | |
905 | */ | |
a361cd9f | 906 | |
cac9e916 | 907 | /* Register the regulators */ |
429222d0 NM |
908 | desc = &pmic->desc[id]; |
909 | desc->name = rinfo->name; | |
910 | desc->id = id; | |
911 | desc->type = REGULATOR_VOLTAGE; | |
912 | desc->owner = THIS_MODULE; | |
a361cd9f | 913 | |
cac9e916 | 914 | if (id < PALMAS_REG_REGEN1) { |
429222d0 | 915 | desc->n_voltages = PALMAS_LDO_NUM_VOLTAGES; |
cac9e916 | 916 | if (reg_init && reg_init->roof_floor) |
429222d0 | 917 | desc->ops = &palmas_ops_ext_control_ldo; |
cac9e916 | 918 | else |
429222d0 NM |
919 | desc->ops = &palmas_ops_ldo; |
920 | desc->min_uV = 900000; | |
921 | desc->uV_step = 50000; | |
922 | desc->linear_min_sel = 1; | |
923 | desc->enable_time = 500; | |
924 | desc->vsel_reg = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE, | |
925 | rinfo->vsel_addr); | |
926 | desc->vsel_mask = PALMAS_LDO1_VOLTAGE_VSEL_MASK; | |
927 | desc->enable_reg = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE, | |
928 | rinfo->ctrl_addr); | |
929 | desc->enable_mask = PALMAS_LDO1_CTRL_MODE_ACTIVE; | |
a361cd9f | 930 | |
cac9e916 K |
931 | /* Check if LDO8 is in tracking mode or not */ |
932 | if (pdata && (id == PALMAS_REG_LDO8) && | |
933 | pdata->enable_ldo8_tracking) { | |
934 | palmas_enable_ldo8_track(pmic->palmas); | |
429222d0 NM |
935 | desc->min_uV = 450000; |
936 | desc->uV_step = 25000; | |
cac9e916 | 937 | } |
a361cd9f | 938 | |
cac9e916 K |
939 | /* LOD6 in vibrator mode will have enable time 2000us */ |
940 | if (pdata && pdata->ldo6_vibrator && | |
941 | (id == PALMAS_REG_LDO6)) | |
429222d0 | 942 | desc->enable_time = 2000; |
b554e145 K |
943 | |
944 | if (id == PALMAS_REG_LDO9) { | |
945 | desc->ops = &palmas_ops_ldo9; | |
946 | desc->bypass_reg = desc->enable_reg; | |
947 | desc->bypass_mask = | |
948 | PALMAS_LDO9_CTRL_LDO_BYPASS_EN; | |
949 | } | |
cac9e916 | 950 | } else { |
e999c728 K |
951 | if (!ddata->has_regen3 && id == PALMAS_REG_REGEN3) |
952 | continue; | |
953 | ||
429222d0 | 954 | desc->n_voltages = 1; |
cac9e916 | 955 | if (reg_init && reg_init->roof_floor) |
429222d0 | 956 | desc->ops = &palmas_ops_ext_control_extreg; |
cac9e916 | 957 | else |
429222d0 NM |
958 | desc->ops = &palmas_ops_extreg; |
959 | desc->enable_reg = | |
cac9e916 | 960 | PALMAS_BASE_TO_REG(PALMAS_RESOURCE_BASE, |
cf910b6b | 961 | rinfo->ctrl_addr); |
429222d0 | 962 | desc->enable_mask = PALMAS_REGEN1_CTRL_MODE_ACTIVE; |
cac9e916 | 963 | } |
a361cd9f | 964 | |
cac9e916 K |
965 | if (pdata) |
966 | config.init_data = pdata->reg_data[id]; | |
967 | else | |
968 | config.init_data = NULL; | |
32b6d3f6 | 969 | |
429222d0 | 970 | desc->supply_name = rinfo->sname; |
cac9e916 | 971 | config.of_node = ddata->palmas_matches[id].of_node; |
a361cd9f | 972 | |
429222d0 | 973 | rdev = devm_regulator_register(pmic->dev, desc, &config); |
cac9e916 K |
974 | if (IS_ERR(rdev)) { |
975 | dev_err(pmic->dev, | |
976 | "failed to register %s regulator\n", | |
977 | pdev_name); | |
978 | return PTR_ERR(rdev); | |
979 | } | |
a361cd9f | 980 | |
cac9e916 K |
981 | /* Save regulator for cleanup */ |
982 | pmic->rdev[id] = rdev; | |
a361cd9f | 983 | |
cac9e916 K |
984 | /* Initialise sleep/init values from platform data */ |
985 | if (pdata) { | |
986 | reg_init = pdata->reg_init[id]; | |
987 | if (reg_init) { | |
988 | if (id <= ddata->ldo_end) | |
989 | ret = palmas_ldo_init(pmic->palmas, id, | |
990 | reg_init); | |
991 | else | |
992 | ret = palmas_extreg_init(pmic->palmas, | |
993 | id, reg_init); | |
994 | if (ret) | |
995 | return ret; | |
996 | } | |
997 | } | |
a361cd9f GG |
998 | } |
999 | ||
cac9e916 | 1000 | return 0; |
a361cd9f GG |
1001 | } |
1002 | ||
d6f83370 K |
1003 | static int tps65917_ldo_registration(struct palmas_pmic *pmic, |
1004 | struct palmas_pmic_driver_data *ddata, | |
1005 | struct palmas_pmic_platform_data *pdata, | |
1006 | const char *pdev_name, | |
1007 | struct regulator_config config) | |
1008 | { | |
1009 | int id, ret; | |
1010 | struct regulator_dev *rdev; | |
1011 | struct palmas_reg_init *reg_init; | |
cf910b6b | 1012 | struct palmas_regs_info *rinfo; |
429222d0 | 1013 | struct regulator_desc *desc; |
d6f83370 K |
1014 | |
1015 | for (id = ddata->ldo_begin; id < ddata->max_reg; id++) { | |
1016 | if (pdata && pdata->reg_init[id]) | |
1017 | reg_init = pdata->reg_init[id]; | |
1018 | else | |
1019 | reg_init = NULL; | |
1020 | ||
1021 | /* Miss out regulators which are not available due | |
1022 | * to alternate functions. | |
1023 | */ | |
cf910b6b | 1024 | rinfo = &ddata->palmas_regs_info[id]; |
d6f83370 K |
1025 | |
1026 | /* Register the regulators */ | |
429222d0 NM |
1027 | desc = &pmic->desc[id]; |
1028 | desc->name = rinfo->name; | |
1029 | desc->id = id; | |
1030 | desc->type = REGULATOR_VOLTAGE; | |
1031 | desc->owner = THIS_MODULE; | |
d6f83370 K |
1032 | |
1033 | if (id < TPS65917_REG_REGEN1) { | |
429222d0 | 1034 | desc->n_voltages = PALMAS_LDO_NUM_VOLTAGES; |
d6f83370 | 1035 | if (reg_init && reg_init->roof_floor) |
429222d0 | 1036 | desc->ops = &palmas_ops_ext_control_ldo; |
d6f83370 | 1037 | else |
429222d0 NM |
1038 | desc->ops = &tps65917_ops_ldo; |
1039 | desc->min_uV = 900000; | |
1040 | desc->uV_step = 50000; | |
1041 | desc->linear_min_sel = 1; | |
1042 | desc->enable_time = 500; | |
1043 | desc->vsel_reg = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE, | |
1044 | rinfo->vsel_addr); | |
1045 | desc->vsel_mask = PALMAS_LDO1_VOLTAGE_VSEL_MASK; | |
1046 | desc->enable_reg = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE, | |
1047 | rinfo->ctrl_addr); | |
1048 | desc->enable_mask = PALMAS_LDO1_CTRL_MODE_ACTIVE; | |
d6f83370 K |
1049 | /* |
1050 | * To be confirmed. Discussion on going with PMIC Team. | |
1051 | * It is of the order of ~60mV/uS. | |
1052 | */ | |
429222d0 | 1053 | desc->ramp_delay = 2500; |
b554e145 K |
1054 | if (id == TPS65917_REG_LDO1 || |
1055 | id == TPS65917_REG_LDO2) { | |
1056 | desc->ops = &tps65917_ops_ldo_1_2; | |
1057 | desc->bypass_reg = desc->enable_reg; | |
1058 | desc->bypass_mask = | |
1059 | TPS65917_LDO1_CTRL_BYPASS_EN; | |
1060 | } | |
d6f83370 | 1061 | } else { |
429222d0 | 1062 | desc->n_voltages = 1; |
d6f83370 | 1063 | if (reg_init && reg_init->roof_floor) |
429222d0 | 1064 | desc->ops = &palmas_ops_ext_control_extreg; |
d6f83370 | 1065 | else |
429222d0 NM |
1066 | desc->ops = &palmas_ops_extreg; |
1067 | desc->enable_reg = | |
d6f83370 | 1068 | PALMAS_BASE_TO_REG(PALMAS_RESOURCE_BASE, |
cf910b6b | 1069 | rinfo->ctrl_addr); |
429222d0 | 1070 | desc->enable_mask = PALMAS_REGEN1_CTRL_MODE_ACTIVE; |
d6f83370 K |
1071 | } |
1072 | ||
1073 | if (pdata) | |
1074 | config.init_data = pdata->reg_data[id]; | |
1075 | else | |
1076 | config.init_data = NULL; | |
1077 | ||
429222d0 | 1078 | desc->supply_name = rinfo->sname; |
d6f83370 K |
1079 | config.of_node = ddata->palmas_matches[id].of_node; |
1080 | ||
429222d0 | 1081 | rdev = devm_regulator_register(pmic->dev, desc, &config); |
d6f83370 K |
1082 | if (IS_ERR(rdev)) { |
1083 | dev_err(pmic->dev, | |
1084 | "failed to register %s regulator\n", | |
1085 | pdev_name); | |
1086 | return PTR_ERR(rdev); | |
1087 | } | |
1088 | ||
1089 | /* Save regulator for cleanup */ | |
1090 | pmic->rdev[id] = rdev; | |
1091 | ||
1092 | /* Initialise sleep/init values from platform data */ | |
1093 | if (pdata) { | |
1094 | reg_init = pdata->reg_init[id]; | |
1095 | if (reg_init) { | |
1096 | if (id < TPS65917_REG_REGEN1) | |
1097 | ret = palmas_ldo_init(pmic->palmas, | |
1098 | id, reg_init); | |
1099 | else | |
1100 | ret = palmas_extreg_init(pmic->palmas, | |
1101 | id, reg_init); | |
1102 | if (ret) | |
1103 | return ret; | |
1104 | } | |
1105 | } | |
1106 | } | |
1107 | ||
1108 | return 0; | |
1109 | } | |
1110 | ||
cac9e916 K |
1111 | static int palmas_smps_registration(struct palmas_pmic *pmic, |
1112 | struct palmas_pmic_driver_data *ddata, | |
1113 | struct palmas_pmic_platform_data *pdata, | |
1114 | const char *pdev_name, | |
1115 | struct regulator_config config) | |
e5ce4208 | 1116 | { |
cac9e916 K |
1117 | int id, ret; |
1118 | unsigned int addr, reg; | |
e5ce4208 | 1119 | struct regulator_dev *rdev; |
e5ce4208 | 1120 | struct palmas_reg_init *reg_init; |
cf910b6b | 1121 | struct palmas_regs_info *rinfo; |
429222d0 | 1122 | struct regulator_desc *desc; |
e5ce4208 | 1123 | |
cac9e916 | 1124 | for (id = ddata->smps_start; id <= ddata->smps_end; id++) { |
28d1e8cd | 1125 | bool ramp_delay_support = false; |
e5ce4208 GG |
1126 | |
1127 | /* | |
1128 | * Miss out regulators which are not available due | |
1129 | * to slaving configurations. | |
1130 | */ | |
1131 | switch (id) { | |
1132 | case PALMAS_REG_SMPS12: | |
1133 | case PALMAS_REG_SMPS3: | |
1134 | if (pmic->smps123) | |
1135 | continue; | |
28d1e8cd LD |
1136 | if (id == PALMAS_REG_SMPS12) |
1137 | ramp_delay_support = true; | |
e5ce4208 GG |
1138 | break; |
1139 | case PALMAS_REG_SMPS123: | |
1140 | if (!pmic->smps123) | |
1141 | continue; | |
28d1e8cd | 1142 | ramp_delay_support = true; |
e5ce4208 GG |
1143 | break; |
1144 | case PALMAS_REG_SMPS45: | |
1145 | case PALMAS_REG_SMPS7: | |
1146 | if (pmic->smps457) | |
1147 | continue; | |
28d1e8cd LD |
1148 | if (id == PALMAS_REG_SMPS45) |
1149 | ramp_delay_support = true; | |
e5ce4208 GG |
1150 | break; |
1151 | case PALMAS_REG_SMPS457: | |
1152 | if (!pmic->smps457) | |
1153 | continue; | |
28d1e8cd LD |
1154 | ramp_delay_support = true; |
1155 | break; | |
77409d9b KVA |
1156 | case PALMAS_REG_SMPS10_OUT1: |
1157 | case PALMAS_REG_SMPS10_OUT2: | |
cac9e916 | 1158 | if (!PALMAS_PMIC_HAS(pmic->palmas, SMPS10_BOOST)) |
1ffb0be3 | 1159 | continue; |
28d1e8cd | 1160 | } |
cf910b6b | 1161 | rinfo = &ddata->palmas_regs_info[id]; |
429222d0 | 1162 | desc = &pmic->desc[id]; |
28d1e8cd | 1163 | |
3f4d6364 | 1164 | if ((id == PALMAS_REG_SMPS6) || (id == PALMAS_REG_SMPS8)) |
28d1e8cd LD |
1165 | ramp_delay_support = true; |
1166 | ||
1167 | if (ramp_delay_support) { | |
cf910b6b | 1168 | addr = rinfo->tstep_addr; |
28d1e8cd LD |
1169 | ret = palmas_smps_read(pmic->palmas, addr, ®); |
1170 | if (ret < 0) { | |
cac9e916 | 1171 | dev_err(pmic->dev, |
28d1e8cd | 1172 | "reading TSTEP reg failed: %d\n", ret); |
51c86b3e | 1173 | return ret; |
28d1e8cd | 1174 | } |
429222d0 NM |
1175 | desc->ramp_delay = palmas_smps_ramp_delay[reg & 0x3]; |
1176 | pmic->ramp_delay[id] = desc->ramp_delay; | |
e5ce4208 GG |
1177 | } |
1178 | ||
bdc4baac AL |
1179 | /* Initialise sleep/init values from platform data */ |
1180 | if (pdata && pdata->reg_init[id]) { | |
1181 | reg_init = pdata->reg_init[id]; | |
cac9e916 | 1182 | ret = palmas_smps_init(pmic->palmas, id, reg_init); |
bdc4baac | 1183 | if (ret) |
51c86b3e | 1184 | return ret; |
32b6d3f6 LD |
1185 | } else { |
1186 | reg_init = NULL; | |
bdc4baac AL |
1187 | } |
1188 | ||
e5ce4208 | 1189 | /* Register the regulators */ |
429222d0 NM |
1190 | desc->name = rinfo->name; |
1191 | desc->id = id; | |
e5ce4208 | 1192 | |
fedd89b1 | 1193 | switch (id) { |
77409d9b KVA |
1194 | case PALMAS_REG_SMPS10_OUT1: |
1195 | case PALMAS_REG_SMPS10_OUT2: | |
429222d0 NM |
1196 | desc->n_voltages = PALMAS_SMPS10_NUM_VOLTAGES; |
1197 | desc->ops = &palmas_ops_smps10; | |
1198 | desc->vsel_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, | |
1199 | PALMAS_SMPS10_CTRL); | |
1200 | desc->vsel_mask = SMPS10_VSEL; | |
1201 | desc->enable_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, | |
1202 | PALMAS_SMPS10_CTRL); | |
77409d9b | 1203 | if (id == PALMAS_REG_SMPS10_OUT1) |
429222d0 | 1204 | desc->enable_mask = SMPS10_SWITCH_EN; |
77409d9b | 1205 | else |
429222d0 NM |
1206 | desc->enable_mask = SMPS10_BOOST_EN; |
1207 | desc->bypass_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, | |
1208 | PALMAS_SMPS10_CTRL); | |
1209 | desc->bypass_mask = SMPS10_BYPASS_EN; | |
1210 | desc->min_uV = 3750000; | |
1211 | desc->uV_step = 1250000; | |
fedd89b1 AL |
1212 | break; |
1213 | default: | |
bdc4baac AL |
1214 | /* |
1215 | * Read and store the RANGE bit for later use | |
1216 | * This must be done before regulator is probed, | |
51d3a0c9 LD |
1217 | * otherwise we error in probe with unsupportable |
1218 | * ranges. Read the current smps mode for later use. | |
bdc4baac | 1219 | */ |
cf910b6b | 1220 | addr = rinfo->vsel_addr; |
429222d0 | 1221 | desc->n_linear_ranges = 3; |
e5ce4208 GG |
1222 | |
1223 | ret = palmas_smps_read(pmic->palmas, addr, ®); | |
1224 | if (ret) | |
51c86b3e | 1225 | return ret; |
e5ce4208 GG |
1226 | if (reg & PALMAS_SMPS12_VOLTAGE_RANGE) |
1227 | pmic->range[id] = 1; | |
dbabd624 | 1228 | if (pmic->range[id]) |
429222d0 | 1229 | desc->linear_ranges = smps_high_ranges; |
dbabd624 | 1230 | else |
429222d0 | 1231 | desc->linear_ranges = smps_low_ranges; |
bdc4baac | 1232 | |
32b6d3f6 | 1233 | if (reg_init && reg_init->roof_floor) |
429222d0 | 1234 | desc->ops = &palmas_ops_ext_control_smps; |
32b6d3f6 | 1235 | else |
429222d0 NM |
1236 | desc->ops = &palmas_ops_smps; |
1237 | desc->n_voltages = PALMAS_SMPS_NUM_VOLTAGES; | |
1238 | desc->vsel_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, | |
1239 | rinfo->vsel_addr); | |
1240 | desc->vsel_mask = PALMAS_SMPS12_VOLTAGE_VSEL_MASK; | |
51d3a0c9 LD |
1241 | |
1242 | /* Read the smps mode for later use. */ | |
cf910b6b | 1243 | addr = rinfo->ctrl_addr; |
51d3a0c9 LD |
1244 | ret = palmas_smps_read(pmic->palmas, addr, ®); |
1245 | if (ret) | |
51c86b3e | 1246 | return ret; |
51d3a0c9 LD |
1247 | pmic->current_reg_mode[id] = reg & |
1248 | PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK; | |
318dbb02 | 1249 | |
429222d0 NM |
1250 | desc->enable_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, |
1251 | rinfo->ctrl_addr); | |
1252 | desc->enable_mask = PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK; | |
318dbb02 | 1253 | /* set_mode overrides this value */ |
429222d0 | 1254 | desc->enable_val = SMPS_CTRL_MODE_ON; |
e5ce4208 GG |
1255 | } |
1256 | ||
429222d0 NM |
1257 | desc->type = REGULATOR_VOLTAGE; |
1258 | desc->owner = THIS_MODULE; | |
bdc4baac | 1259 | |
a361cd9f | 1260 | if (pdata) |
e5ce4208 GG |
1261 | config.init_data = pdata->reg_data[id]; |
1262 | else | |
1263 | config.init_data = NULL; | |
1264 | ||
429222d0 | 1265 | desc->supply_name = rinfo->sname; |
cac9e916 | 1266 | config.of_node = ddata->palmas_matches[id].of_node; |
a361cd9f | 1267 | |
429222d0 | 1268 | rdev = devm_regulator_register(pmic->dev, desc, &config); |
e5ce4208 | 1269 | if (IS_ERR(rdev)) { |
cac9e916 | 1270 | dev_err(pmic->dev, |
e5ce4208 | 1271 | "failed to register %s regulator\n", |
cac9e916 | 1272 | pdev_name); |
51c86b3e | 1273 | return PTR_ERR(rdev); |
e5ce4208 GG |
1274 | } |
1275 | ||
1276 | /* Save regulator for cleanup */ | |
1277 | pmic->rdev[id] = rdev; | |
1278 | } | |
1279 | ||
cac9e916 K |
1280 | return 0; |
1281 | } | |
e5ce4208 | 1282 | |
d6f83370 K |
1283 | static int tps65917_smps_registration(struct palmas_pmic *pmic, |
1284 | struct palmas_pmic_driver_data *ddata, | |
1285 | struct palmas_pmic_platform_data *pdata, | |
1286 | const char *pdev_name, | |
1287 | struct regulator_config config) | |
1288 | { | |
1289 | int id, ret; | |
1290 | unsigned int addr, reg; | |
1291 | struct regulator_dev *rdev; | |
1292 | struct palmas_reg_init *reg_init; | |
cf910b6b | 1293 | struct palmas_regs_info *rinfo; |
429222d0 | 1294 | struct regulator_desc *desc; |
d6f83370 K |
1295 | |
1296 | for (id = ddata->smps_start; id <= ddata->smps_end; id++) { | |
1297 | /* | |
1298 | * Miss out regulators which are not available due | |
1299 | * to slaving configurations. | |
1300 | */ | |
429222d0 NM |
1301 | desc = &pmic->desc[id]; |
1302 | desc->n_linear_ranges = 3; | |
d6f83370 K |
1303 | if ((id == TPS65917_REG_SMPS2) && pmic->smps12) |
1304 | continue; | |
1305 | ||
1306 | /* Initialise sleep/init values from platform data */ | |
1307 | if (pdata && pdata->reg_init[id]) { | |
1308 | reg_init = pdata->reg_init[id]; | |
1309 | ret = palmas_smps_init(pmic->palmas, id, reg_init); | |
1310 | if (ret) | |
1311 | return ret; | |
1312 | } else { | |
1313 | reg_init = NULL; | |
1314 | } | |
cf910b6b | 1315 | rinfo = &ddata->palmas_regs_info[id]; |
d6f83370 K |
1316 | |
1317 | /* Register the regulators */ | |
429222d0 NM |
1318 | desc->name = rinfo->name; |
1319 | desc->id = id; | |
d6f83370 K |
1320 | |
1321 | /* | |
1322 | * Read and store the RANGE bit for later use | |
1323 | * This must be done before regulator is probed, | |
1324 | * otherwise we error in probe with unsupportable | |
1325 | * ranges. Read the current smps mode for later use. | |
1326 | */ | |
cf910b6b | 1327 | addr = rinfo->vsel_addr; |
d6f83370 K |
1328 | |
1329 | ret = palmas_smps_read(pmic->palmas, addr, ®); | |
1330 | if (ret) | |
1331 | return ret; | |
1332 | if (reg & TPS65917_SMPS1_VOLTAGE_RANGE) | |
1333 | pmic->range[id] = 1; | |
1334 | ||
1335 | if (pmic->range[id]) | |
429222d0 NM |
1336 | desc->linear_ranges = smps_high_ranges; |
1337 | else | |
1338 | desc->linear_ranges = smps_low_ranges; | |
d6f83370 K |
1339 | |
1340 | if (reg_init && reg_init->roof_floor) | |
429222d0 | 1341 | desc->ops = &tps65917_ops_ext_control_smps; |
d6f83370 | 1342 | else |
429222d0 NM |
1343 | desc->ops = &tps65917_ops_smps; |
1344 | desc->n_voltages = PALMAS_SMPS_NUM_VOLTAGES; | |
1345 | desc->vsel_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, | |
1346 | rinfo->vsel_addr); | |
1347 | desc->vsel_mask = PALMAS_SMPS12_VOLTAGE_VSEL_MASK; | |
1348 | desc->ramp_delay = 2500; | |
d6f83370 K |
1349 | |
1350 | /* Read the smps mode for later use. */ | |
cf910b6b | 1351 | addr = rinfo->ctrl_addr; |
d6f83370 K |
1352 | ret = palmas_smps_read(pmic->palmas, addr, ®); |
1353 | if (ret) | |
1354 | return ret; | |
1355 | pmic->current_reg_mode[id] = reg & | |
1356 | PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK; | |
b632815e NM |
1357 | desc->enable_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, |
1358 | rinfo->ctrl_addr); | |
1359 | desc->enable_mask = PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK; | |
1360 | /* set_mode overrides this value */ | |
1361 | desc->enable_val = SMPS_CTRL_MODE_ON; | |
d6f83370 | 1362 | |
429222d0 NM |
1363 | desc->type = REGULATOR_VOLTAGE; |
1364 | desc->owner = THIS_MODULE; | |
d6f83370 K |
1365 | |
1366 | if (pdata) | |
1367 | config.init_data = pdata->reg_data[id]; | |
1368 | else | |
1369 | config.init_data = NULL; | |
1370 | ||
429222d0 | 1371 | desc->supply_name = rinfo->sname; |
d6f83370 K |
1372 | config.of_node = ddata->palmas_matches[id].of_node; |
1373 | ||
429222d0 | 1374 | rdev = devm_regulator_register(pmic->dev, desc, &config); |
d6f83370 K |
1375 | if (IS_ERR(rdev)) { |
1376 | dev_err(pmic->dev, | |
1377 | "failed to register %s regulator\n", | |
1378 | pdev_name); | |
1379 | return PTR_ERR(rdev); | |
1380 | } | |
1381 | ||
1382 | /* Save regulator for cleanup */ | |
1383 | pmic->rdev[id] = rdev; | |
1384 | } | |
1385 | ||
1386 | return 0; | |
1387 | } | |
1388 | ||
cac9e916 K |
1389 | static struct of_regulator_match palmas_matches[] = { |
1390 | { .name = "smps12", }, | |
1391 | { .name = "smps123", }, | |
1392 | { .name = "smps3", }, | |
1393 | { .name = "smps45", }, | |
1394 | { .name = "smps457", }, | |
1395 | { .name = "smps6", }, | |
1396 | { .name = "smps7", }, | |
1397 | { .name = "smps8", }, | |
1398 | { .name = "smps9", }, | |
1399 | { .name = "smps10_out2", }, | |
1400 | { .name = "smps10_out1", }, | |
1401 | { .name = "ldo1", }, | |
1402 | { .name = "ldo2", }, | |
1403 | { .name = "ldo3", }, | |
1404 | { .name = "ldo4", }, | |
1405 | { .name = "ldo5", }, | |
1406 | { .name = "ldo6", }, | |
1407 | { .name = "ldo7", }, | |
1408 | { .name = "ldo8", }, | |
1409 | { .name = "ldo9", }, | |
1410 | { .name = "ldoln", }, | |
1411 | { .name = "ldousb", }, | |
1412 | { .name = "regen1", }, | |
1413 | { .name = "regen2", }, | |
1414 | { .name = "regen3", }, | |
1415 | { .name = "sysen1", }, | |
1416 | { .name = "sysen2", }, | |
1417 | }; | |
e5ce4208 | 1418 | |
d6f83370 K |
1419 | static struct of_regulator_match tps65917_matches[] = { |
1420 | { .name = "smps1", }, | |
1421 | { .name = "smps2", }, | |
1422 | { .name = "smps3", }, | |
1423 | { .name = "smps4", }, | |
1424 | { .name = "smps5", }, | |
1425 | { .name = "ldo1", }, | |
1426 | { .name = "ldo2", }, | |
1427 | { .name = "ldo3", }, | |
1428 | { .name = "ldo4", }, | |
1429 | { .name = "ldo5", }, | |
1430 | { .name = "regen1", }, | |
1431 | { .name = "regen2", }, | |
1432 | { .name = "regen3", }, | |
1433 | { .name = "sysen1", }, | |
1434 | { .name = "sysen2", }, | |
1435 | }; | |
1436 | ||
4b09e17b | 1437 | static struct palmas_pmic_driver_data palmas_ddata = { |
cac9e916 K |
1438 | .smps_start = PALMAS_REG_SMPS12, |
1439 | .smps_end = PALMAS_REG_SMPS10_OUT1, | |
1440 | .ldo_begin = PALMAS_REG_LDO1, | |
1441 | .ldo_end = PALMAS_REG_LDOUSB, | |
1442 | .max_reg = PALMAS_NUM_REGS, | |
e999c728 | 1443 | .has_regen3 = true, |
6839cd6f | 1444 | .palmas_regs_info = palmas_generic_regs_info, |
cac9e916 K |
1445 | .palmas_matches = palmas_matches, |
1446 | .sleep_req_info = palma_sleep_req_info, | |
1447 | .smps_register = palmas_smps_registration, | |
1448 | .ldo_register = palmas_ldo_registration, | |
1449 | }; | |
aa07f027 | 1450 | |
4b09e17b | 1451 | static struct palmas_pmic_driver_data tps65917_ddata = { |
d6f83370 K |
1452 | .smps_start = TPS65917_REG_SMPS1, |
1453 | .smps_end = TPS65917_REG_SMPS5, | |
1454 | .ldo_begin = TPS65917_REG_LDO1, | |
1455 | .ldo_end = TPS65917_REG_LDO5, | |
1456 | .max_reg = TPS65917_NUM_REGS, | |
e999c728 | 1457 | .has_regen3 = true, |
d6f83370 K |
1458 | .palmas_regs_info = tps65917_regs_info, |
1459 | .palmas_matches = tps65917_matches, | |
1460 | .sleep_req_info = tps65917_sleep_req_info, | |
1461 | .smps_register = tps65917_smps_registration, | |
1462 | .ldo_register = tps65917_ldo_registration, | |
1463 | }; | |
1464 | ||
cac9e916 K |
1465 | static void palmas_dt_to_pdata(struct device *dev, |
1466 | struct device_node *node, | |
1467 | struct palmas_pmic_platform_data *pdata, | |
1468 | struct palmas_pmic_driver_data *ddata) | |
1469 | { | |
1470 | struct device_node *regulators; | |
1471 | u32 prop; | |
1472 | int idx, ret; | |
17c11a76 | 1473 | |
cac9e916 K |
1474 | regulators = of_get_child_by_name(node, "regulators"); |
1475 | if (!regulators) { | |
1476 | dev_info(dev, "regulator node not found\n"); | |
1477 | return; | |
1478 | } | |
087d30e3 | 1479 | |
cac9e916 K |
1480 | ret = of_regulator_match(dev, regulators, ddata->palmas_matches, |
1481 | ddata->max_reg); | |
1482 | of_node_put(regulators); | |
1483 | if (ret < 0) { | |
1484 | dev_err(dev, "Error parsing regulator init data: %d\n", ret); | |
1485 | return; | |
1486 | } | |
e5ce4208 | 1487 | |
cac9e916 K |
1488 | for (idx = 0; idx < ddata->max_reg; idx++) { |
1489 | if (!ddata->palmas_matches[idx].init_data || | |
1490 | !ddata->palmas_matches[idx].of_node) | |
1491 | continue; | |
e5ce4208 | 1492 | |
cac9e916 | 1493 | pdata->reg_data[idx] = ddata->palmas_matches[idx].init_data; |
a361cd9f | 1494 | |
cac9e916 K |
1495 | pdata->reg_init[idx] = devm_kzalloc(dev, |
1496 | sizeof(struct palmas_reg_init), GFP_KERNEL); | |
e5ce4208 | 1497 | |
cac9e916 K |
1498 | pdata->reg_init[idx]->warm_reset = |
1499 | of_property_read_bool(ddata->palmas_matches[idx].of_node, | |
1500 | "ti,warm-reset"); | |
e5ce4208 | 1501 | |
cac9e916 K |
1502 | ret = of_property_read_u32(ddata->palmas_matches[idx].of_node, |
1503 | "ti,roof-floor", &prop); | |
1504 | /* EINVAL: Property not found */ | |
1505 | if (ret != -EINVAL) { | |
1506 | int econtrol; | |
1507 | ||
1508 | /* use default value, when no value is specified */ | |
1509 | econtrol = PALMAS_EXT_CONTROL_NSLEEP; | |
1510 | if (!ret) { | |
1511 | switch (prop) { | |
1512 | case 1: | |
1513 | econtrol = PALMAS_EXT_CONTROL_ENABLE1; | |
1514 | break; | |
1515 | case 2: | |
1516 | econtrol = PALMAS_EXT_CONTROL_ENABLE2; | |
1517 | break; | |
1518 | case 3: | |
1519 | econtrol = PALMAS_EXT_CONTROL_NSLEEP; | |
1520 | break; | |
1521 | default: | |
1522 | WARN_ON(1); | |
1523 | dev_warn(dev, | |
1524 | "%s: Invalid roof-floor option: %u\n", | |
1525 | palmas_matches[idx].name, prop); | |
1526 | break; | |
1527 | } | |
e5ce4208 | 1528 | } |
cac9e916 | 1529 | pdata->reg_init[idx]->roof_floor = econtrol; |
e5ce4208 | 1530 | } |
e5ce4208 | 1531 | |
cac9e916 K |
1532 | ret = of_property_read_u32(ddata->palmas_matches[idx].of_node, |
1533 | "ti,mode-sleep", &prop); | |
1534 | if (!ret) | |
1535 | pdata->reg_init[idx]->mode_sleep = prop; | |
17c11a76 | 1536 | |
cac9e916 K |
1537 | ret = of_property_read_bool(ddata->palmas_matches[idx].of_node, |
1538 | "ti,smps-range"); | |
1539 | if (ret) | |
1540 | pdata->reg_init[idx]->vsel = | |
1541 | PALMAS_SMPS12_VOLTAGE_RANGE; | |
1542 | ||
1543 | if (idx == PALMAS_REG_LDO8) | |
1544 | pdata->enable_ldo8_tracking = of_property_read_bool( | |
1545 | ddata->palmas_matches[idx].of_node, | |
1546 | "ti,enable-ldo8-tracking"); | |
1547 | } | |
1548 | ||
1549 | pdata->ldo6_vibrator = of_property_read_bool(node, "ti,ldo6-vibrator"); | |
e5ce4208 GG |
1550 | } |
1551 | ||
cdbf6f0e | 1552 | static const struct of_device_id of_palmas_match_tbl[] = { |
cac9e916 K |
1553 | { |
1554 | .compatible = "ti,palmas-pmic", | |
1555 | .data = &palmas_ddata, | |
1556 | }, | |
1557 | { | |
1558 | .compatible = "ti,twl6035-pmic", | |
1559 | .data = &palmas_ddata, | |
1560 | }, | |
1561 | { | |
1562 | .compatible = "ti,twl6036-pmic", | |
1563 | .data = &palmas_ddata, | |
1564 | }, | |
1565 | { | |
1566 | .compatible = "ti,twl6037-pmic", | |
1567 | .data = &palmas_ddata, | |
1568 | }, | |
1569 | { | |
1570 | .compatible = "ti,tps65913-pmic", | |
1571 | .data = &palmas_ddata, | |
1572 | }, | |
1573 | { | |
1574 | .compatible = "ti,tps65914-pmic", | |
1575 | .data = &palmas_ddata, | |
1576 | }, | |
1577 | { | |
1578 | .compatible = "ti,tps80036-pmic", | |
1579 | .data = &palmas_ddata, | |
1580 | }, | |
1581 | { | |
1582 | .compatible = "ti,tps659038-pmic", | |
1583 | .data = &palmas_ddata, | |
d6f83370 K |
1584 | }, |
1585 | { | |
1586 | .compatible = "ti,tps65917-pmic", | |
1587 | .data = &tps65917_ddata, | |
cac9e916 | 1588 | }, |
a361cd9f GG |
1589 | { /* end */ } |
1590 | }; | |
1591 | ||
cac9e916 K |
1592 | static int palmas_regulators_probe(struct platform_device *pdev) |
1593 | { | |
1594 | struct palmas *palmas = dev_get_drvdata(pdev->dev.parent); | |
1595 | struct palmas_pmic_platform_data *pdata = dev_get_platdata(&pdev->dev); | |
1596 | struct device_node *node = pdev->dev.of_node; | |
1597 | struct palmas_pmic_driver_data *driver_data; | |
1598 | struct regulator_config config = { }; | |
1599 | struct palmas_pmic *pmic; | |
1600 | const char *pdev_name; | |
1601 | const struct of_device_id *match; | |
1602 | int ret = 0; | |
1603 | unsigned int reg; | |
1604 | ||
1605 | match = of_match_device(of_match_ptr(of_palmas_match_tbl), &pdev->dev); | |
1606 | ||
1607 | if (!match) | |
1608 | return -ENODATA; | |
1609 | ||
1610 | driver_data = (struct palmas_pmic_driver_data *)match->data; | |
1611 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); | |
1612 | if (!pdata) | |
1613 | return -ENOMEM; | |
1614 | ||
1615 | pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL); | |
1616 | if (!pmic) | |
1617 | return -ENOMEM; | |
1618 | ||
e999c728 | 1619 | if (of_device_is_compatible(node, "ti,tps659038-pmic")) { |
e03826d5 K |
1620 | palmas_generic_regs_info[PALMAS_REG_REGEN2].ctrl_addr = |
1621 | TPS659038_REGEN2_CTRL; | |
e999c728 K |
1622 | palmas_ddata.has_regen3 = false; |
1623 | } | |
e03826d5 | 1624 | |
cac9e916 K |
1625 | pmic->dev = &pdev->dev; |
1626 | pmic->palmas = palmas; | |
1627 | palmas->pmic = pmic; | |
1628 | platform_set_drvdata(pdev, pmic); | |
1629 | pmic->palmas->pmic_ddata = driver_data; | |
1630 | ||
1631 | palmas_dt_to_pdata(&pdev->dev, node, pdata, driver_data); | |
1632 | ||
1633 | ret = palmas_smps_read(palmas, PALMAS_SMPS_CTRL, ®); | |
1634 | if (ret) | |
1635 | return ret; | |
1636 | ||
1637 | if (reg & PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN) | |
1638 | pmic->smps123 = 1; | |
1639 | ||
1640 | if (reg & PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN) | |
1641 | pmic->smps457 = 1; | |
1642 | ||
1643 | config.regmap = palmas->regmap[REGULATOR_SLAVE]; | |
1644 | config.dev = &pdev->dev; | |
1645 | config.driver_data = pmic; | |
1646 | pdev_name = pdev->name; | |
1647 | ||
1648 | ret = driver_data->smps_register(pmic, driver_data, pdata, pdev_name, | |
1649 | config); | |
1650 | if (ret) | |
1651 | return ret; | |
1652 | ||
1653 | ret = driver_data->ldo_register(pmic, driver_data, pdata, pdev_name, | |
1654 | config); | |
1655 | ||
1656 | return ret; | |
1657 | } | |
1658 | ||
e5ce4208 GG |
1659 | static struct platform_driver palmas_driver = { |
1660 | .driver = { | |
1661 | .name = "palmas-pmic", | |
a361cd9f | 1662 | .of_match_table = of_palmas_match_tbl, |
e5ce4208 | 1663 | }, |
bbcf50b1 | 1664 | .probe = palmas_regulators_probe, |
e5ce4208 GG |
1665 | }; |
1666 | ||
1667 | static int __init palmas_init(void) | |
1668 | { | |
1669 | return platform_driver_register(&palmas_driver); | |
1670 | } | |
1671 | subsys_initcall(palmas_init); | |
1672 | ||
1673 | static void __exit palmas_exit(void) | |
1674 | { | |
1675 | platform_driver_unregister(&palmas_driver); | |
1676 | } | |
1677 | module_exit(palmas_exit); | |
1678 | ||
1679 | MODULE_AUTHOR("Graeme Gregory <gg@slimlogic.co.uk>"); | |
1680 | MODULE_DESCRIPTION("Palmas voltage regulator driver"); | |
1681 | MODULE_LICENSE("GPL"); | |
1682 | MODULE_ALIAS("platform:palmas-pmic"); | |
a361cd9f | 1683 | MODULE_DEVICE_TABLE(of, of_palmas_match_tbl); |