Commit | Line | Data |
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9767ec7f SK |
1 | /* |
2 | * s5m8767.c | |
3 | * | |
4 | * Copyright (c) 2011 Samsung Electronics Co., Ltd | |
5 | * http://www.samsung.com | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License as published by the | |
9 | * Free Software Foundation; either version 2 of the License, or (at your | |
10 | * option) any later version. | |
11 | * | |
12 | */ | |
13 | ||
14 | #include <linux/bug.h> | |
9767ec7f SK |
15 | #include <linux/err.h> |
16 | #include <linux/gpio.h> | |
26aec009 | 17 | #include <linux/of_gpio.h> |
9767ec7f SK |
18 | #include <linux/slab.h> |
19 | #include <linux/module.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/regulator/driver.h> | |
22 | #include <linux/regulator/machine.h> | |
54227bcf SK |
23 | #include <linux/mfd/samsung/core.h> |
24 | #include <linux/mfd/samsung/s5m8767.h> | |
26aec009 | 25 | #include <linux/regulator/of_regulator.h> |
d13733f4 | 26 | #include <linux/regmap.h> |
26aec009 ADK |
27 | |
28 | #define S5M8767_OPMODE_NORMAL_MODE 0x1 | |
9767ec7f SK |
29 | |
30 | struct s5m8767_info { | |
31 | struct device *dev; | |
63063bfb | 32 | struct sec_pmic_dev *iodev; |
9767ec7f SK |
33 | int num_regulators; |
34 | struct regulator_dev **rdev; | |
63063bfb | 35 | struct sec_opmode_data *opmode; |
9767ec7f SK |
36 | |
37 | int ramp_delay; | |
38 | bool buck2_ramp; | |
39 | bool buck3_ramp; | |
40 | bool buck4_ramp; | |
41 | ||
42 | bool buck2_gpiodvs; | |
43 | bool buck3_gpiodvs; | |
44 | bool buck4_gpiodvs; | |
45 | u8 buck2_vol[8]; | |
46 | u8 buck3_vol[8]; | |
47 | u8 buck4_vol[8]; | |
48 | int buck_gpios[3]; | |
c848bc85 | 49 | int buck_ds[3]; |
9767ec7f SK |
50 | int buck_gpioindex; |
51 | }; | |
52 | ||
63063bfb | 53 | struct sec_voltage_desc { |
9767ec7f SK |
54 | int max; |
55 | int min; | |
56 | int step; | |
57 | }; | |
58 | ||
63063bfb | 59 | static const struct sec_voltage_desc buck_voltage_val1 = { |
9767ec7f SK |
60 | .max = 2225000, |
61 | .min = 650000, | |
62 | .step = 6250, | |
63 | }; | |
64 | ||
63063bfb | 65 | static const struct sec_voltage_desc buck_voltage_val2 = { |
9767ec7f SK |
66 | .max = 1600000, |
67 | .min = 600000, | |
68 | .step = 6250, | |
69 | }; | |
70 | ||
63063bfb | 71 | static const struct sec_voltage_desc buck_voltage_val3 = { |
9767ec7f SK |
72 | .max = 3000000, |
73 | .min = 750000, | |
74 | .step = 12500, | |
75 | }; | |
76 | ||
63063bfb | 77 | static const struct sec_voltage_desc ldo_voltage_val1 = { |
9767ec7f SK |
78 | .max = 3950000, |
79 | .min = 800000, | |
80 | .step = 50000, | |
81 | }; | |
82 | ||
63063bfb | 83 | static const struct sec_voltage_desc ldo_voltage_val2 = { |
9767ec7f SK |
84 | .max = 2375000, |
85 | .min = 800000, | |
86 | .step = 25000, | |
87 | }; | |
88 | ||
63063bfb | 89 | static const struct sec_voltage_desc *reg_voltage_map[] = { |
9767ec7f SK |
90 | [S5M8767_LDO1] = &ldo_voltage_val2, |
91 | [S5M8767_LDO2] = &ldo_voltage_val2, | |
92 | [S5M8767_LDO3] = &ldo_voltage_val1, | |
93 | [S5M8767_LDO4] = &ldo_voltage_val1, | |
94 | [S5M8767_LDO5] = &ldo_voltage_val1, | |
95 | [S5M8767_LDO6] = &ldo_voltage_val2, | |
96 | [S5M8767_LDO7] = &ldo_voltage_val2, | |
97 | [S5M8767_LDO8] = &ldo_voltage_val2, | |
98 | [S5M8767_LDO9] = &ldo_voltage_val1, | |
99 | [S5M8767_LDO10] = &ldo_voltage_val1, | |
100 | [S5M8767_LDO11] = &ldo_voltage_val1, | |
101 | [S5M8767_LDO12] = &ldo_voltage_val1, | |
102 | [S5M8767_LDO13] = &ldo_voltage_val1, | |
103 | [S5M8767_LDO14] = &ldo_voltage_val1, | |
104 | [S5M8767_LDO15] = &ldo_voltage_val2, | |
105 | [S5M8767_LDO16] = &ldo_voltage_val1, | |
106 | [S5M8767_LDO17] = &ldo_voltage_val1, | |
107 | [S5M8767_LDO18] = &ldo_voltage_val1, | |
108 | [S5M8767_LDO19] = &ldo_voltage_val1, | |
109 | [S5M8767_LDO20] = &ldo_voltage_val1, | |
110 | [S5M8767_LDO21] = &ldo_voltage_val1, | |
111 | [S5M8767_LDO22] = &ldo_voltage_val1, | |
112 | [S5M8767_LDO23] = &ldo_voltage_val1, | |
113 | [S5M8767_LDO24] = &ldo_voltage_val1, | |
114 | [S5M8767_LDO25] = &ldo_voltage_val1, | |
115 | [S5M8767_LDO26] = &ldo_voltage_val1, | |
116 | [S5M8767_LDO27] = &ldo_voltage_val1, | |
117 | [S5M8767_LDO28] = &ldo_voltage_val1, | |
118 | [S5M8767_BUCK1] = &buck_voltage_val1, | |
119 | [S5M8767_BUCK2] = &buck_voltage_val2, | |
120 | [S5M8767_BUCK3] = &buck_voltage_val2, | |
121 | [S5M8767_BUCK4] = &buck_voltage_val2, | |
122 | [S5M8767_BUCK5] = &buck_voltage_val1, | |
123 | [S5M8767_BUCK6] = &buck_voltage_val1, | |
463616ea KK |
124 | [S5M8767_BUCK7] = &buck_voltage_val3, |
125 | [S5M8767_BUCK8] = &buck_voltage_val3, | |
9767ec7f SK |
126 | [S5M8767_BUCK9] = &buck_voltage_val3, |
127 | }; | |
128 | ||
5ceba7ba | 129 | static unsigned int s5m8767_opmode_reg[][4] = { |
7e44bb83 SK |
130 | /* {OFF, ON, LOWPOWER, SUSPEND} */ |
131 | /* LDO1 ... LDO28 */ | |
132 | {0x0, 0x3, 0x2, 0x1}, /* LDO1 */ | |
133 | {0x0, 0x3, 0x2, 0x1}, | |
134 | {0x0, 0x3, 0x2, 0x1}, | |
135 | {0x0, 0x0, 0x0, 0x0}, | |
136 | {0x0, 0x3, 0x2, 0x1}, /* LDO5 */ | |
137 | {0x0, 0x3, 0x2, 0x1}, | |
138 | {0x0, 0x3, 0x2, 0x1}, | |
139 | {0x0, 0x3, 0x2, 0x1}, | |
140 | {0x0, 0x3, 0x2, 0x1}, | |
141 | {0x0, 0x3, 0x2, 0x1}, /* LDO10 */ | |
142 | {0x0, 0x3, 0x2, 0x1}, | |
143 | {0x0, 0x3, 0x2, 0x1}, | |
144 | {0x0, 0x3, 0x2, 0x1}, | |
145 | {0x0, 0x3, 0x2, 0x1}, | |
146 | {0x0, 0x3, 0x2, 0x1}, /* LDO15 */ | |
147 | {0x0, 0x3, 0x2, 0x1}, | |
148 | {0x0, 0x3, 0x2, 0x1}, | |
149 | {0x0, 0x0, 0x0, 0x0}, | |
150 | {0x0, 0x3, 0x2, 0x1}, | |
151 | {0x0, 0x3, 0x2, 0x1}, /* LDO20 */ | |
152 | {0x0, 0x3, 0x2, 0x1}, | |
153 | {0x0, 0x3, 0x2, 0x1}, | |
154 | {0x0, 0x0, 0x0, 0x0}, | |
155 | {0x0, 0x3, 0x2, 0x1}, | |
156 | {0x0, 0x3, 0x2, 0x1}, /* LDO25 */ | |
157 | {0x0, 0x3, 0x2, 0x1}, | |
158 | {0x0, 0x3, 0x2, 0x1}, | |
159 | {0x0, 0x3, 0x2, 0x1}, /* LDO28 */ | |
160 | ||
161 | /* BUCK1 ... BUCK9 */ | |
162 | {0x0, 0x3, 0x1, 0x1}, /* BUCK1 */ | |
163 | {0x0, 0x3, 0x1, 0x1}, | |
164 | {0x0, 0x3, 0x1, 0x1}, | |
165 | {0x0, 0x3, 0x1, 0x1}, | |
166 | {0x0, 0x3, 0x2, 0x1}, /* BUCK5 */ | |
167 | {0x0, 0x3, 0x1, 0x1}, | |
168 | {0x0, 0x3, 0x1, 0x1}, | |
169 | {0x0, 0x3, 0x1, 0x1}, | |
170 | {0x0, 0x3, 0x1, 0x1}, /* BUCK9 */ | |
171 | }; | |
172 | ||
173 | static int s5m8767_get_register(struct regulator_dev *rdev, int *reg, | |
174 | int *enable_ctrl) | |
9767ec7f | 175 | { |
9bb096ff | 176 | int i, reg_id = rdev_get_id(rdev); |
7e44bb83 SK |
177 | unsigned int mode; |
178 | struct s5m8767_info *s5m8767 = rdev_get_drvdata(rdev); | |
9767ec7f SK |
179 | |
180 | switch (reg_id) { | |
181 | case S5M8767_LDO1 ... S5M8767_LDO2: | |
182 | *reg = S5M8767_REG_LDO1CTRL + (reg_id - S5M8767_LDO1); | |
183 | break; | |
184 | case S5M8767_LDO3 ... S5M8767_LDO28: | |
185 | *reg = S5M8767_REG_LDO3CTRL + (reg_id - S5M8767_LDO3); | |
186 | break; | |
187 | case S5M8767_BUCK1: | |
188 | *reg = S5M8767_REG_BUCK1CTRL1; | |
189 | break; | |
190 | case S5M8767_BUCK2 ... S5M8767_BUCK4: | |
191 | *reg = S5M8767_REG_BUCK2CTRL + (reg_id - S5M8767_BUCK2) * 9; | |
192 | break; | |
193 | case S5M8767_BUCK5: | |
194 | *reg = S5M8767_REG_BUCK5CTRL1; | |
195 | break; | |
196 | case S5M8767_BUCK6 ... S5M8767_BUCK9: | |
197 | *reg = S5M8767_REG_BUCK6CTRL1 + (reg_id - S5M8767_BUCK6) * 2; | |
198 | break; | |
199 | default: | |
200 | return -EINVAL; | |
201 | } | |
202 | ||
9bb096ff ADK |
203 | for (i = 0; i < s5m8767->num_regulators; i++) { |
204 | if (s5m8767->opmode[i].id == reg_id) { | |
205 | mode = s5m8767->opmode[i].mode; | |
206 | break; | |
207 | } | |
208 | } | |
209 | ||
210 | if (i < s5m8767->num_regulators) | |
211 | *enable_ctrl = | |
212 | s5m8767_opmode_reg[reg_id][mode] << S5M8767_ENCTRL_SHIFT; | |
213 | ||
9767ec7f SK |
214 | return 0; |
215 | } | |
216 | ||
217 | static int s5m8767_reg_is_enabled(struct regulator_dev *rdev) | |
218 | { | |
219 | struct s5m8767_info *s5m8767 = rdev_get_drvdata(rdev); | |
220 | int ret, reg; | |
79b53d19 | 221 | int enable_ctrl; |
3ef30398 | 222 | unsigned int val; |
9767ec7f | 223 | |
7e44bb83 | 224 | ret = s5m8767_get_register(rdev, ®, &enable_ctrl); |
9767ec7f SK |
225 | if (ret == -EINVAL) |
226 | return 1; | |
227 | else if (ret) | |
228 | return ret; | |
229 | ||
d13733f4 | 230 | ret = regmap_read(s5m8767->iodev->regmap_pmic, reg, &val); |
9767ec7f SK |
231 | if (ret) |
232 | return ret; | |
233 | ||
79b53d19 | 234 | return (val & S5M8767_ENCTRL_MASK) == enable_ctrl; |
9767ec7f SK |
235 | } |
236 | ||
237 | static int s5m8767_reg_enable(struct regulator_dev *rdev) | |
238 | { | |
239 | struct s5m8767_info *s5m8767 = rdev_get_drvdata(rdev); | |
240 | int ret, reg; | |
79b53d19 | 241 | int enable_ctrl; |
9767ec7f | 242 | |
7e44bb83 | 243 | ret = s5m8767_get_register(rdev, ®, &enable_ctrl); |
9767ec7f SK |
244 | if (ret) |
245 | return ret; | |
246 | ||
d13733f4 KK |
247 | return regmap_update_bits(s5m8767->iodev->regmap_pmic, reg, |
248 | S5M8767_ENCTRL_MASK, enable_ctrl); | |
9767ec7f SK |
249 | } |
250 | ||
251 | static int s5m8767_reg_disable(struct regulator_dev *rdev) | |
252 | { | |
253 | struct s5m8767_info *s5m8767 = rdev_get_drvdata(rdev); | |
d13733f4 | 254 | int ret, reg, enable_ctrl; |
9767ec7f | 255 | |
7e44bb83 | 256 | ret = s5m8767_get_register(rdev, ®, &enable_ctrl); |
9767ec7f SK |
257 | if (ret) |
258 | return ret; | |
259 | ||
d13733f4 KK |
260 | return regmap_update_bits(s5m8767->iodev->regmap_pmic, reg, |
261 | S5M8767_ENCTRL_MASK, ~S5M8767_ENCTRL_MASK); | |
9767ec7f SK |
262 | } |
263 | ||
31a932e1 | 264 | static int s5m8767_get_vsel_reg(int reg_id, struct s5m8767_info *s5m8767) |
9767ec7f | 265 | { |
9767ec7f SK |
266 | int reg; |
267 | ||
268 | switch (reg_id) { | |
269 | case S5M8767_LDO1 ... S5M8767_LDO2: | |
270 | reg = S5M8767_REG_LDO1CTRL + (reg_id - S5M8767_LDO1); | |
271 | break; | |
272 | case S5M8767_LDO3 ... S5M8767_LDO28: | |
273 | reg = S5M8767_REG_LDO3CTRL + (reg_id - S5M8767_LDO3); | |
274 | break; | |
275 | case S5M8767_BUCK1: | |
276 | reg = S5M8767_REG_BUCK1CTRL2; | |
277 | break; | |
278 | case S5M8767_BUCK2: | |
da130ab2 | 279 | reg = S5M8767_REG_BUCK2DVS1; |
0a41685f AL |
280 | if (s5m8767->buck2_gpiodvs) |
281 | reg += s5m8767->buck_gpioindex; | |
9767ec7f SK |
282 | break; |
283 | case S5M8767_BUCK3: | |
da130ab2 | 284 | reg = S5M8767_REG_BUCK3DVS1; |
0a41685f AL |
285 | if (s5m8767->buck3_gpiodvs) |
286 | reg += s5m8767->buck_gpioindex; | |
9767ec7f SK |
287 | break; |
288 | case S5M8767_BUCK4: | |
da130ab2 | 289 | reg = S5M8767_REG_BUCK4DVS1; |
0a41685f AL |
290 | if (s5m8767->buck4_gpiodvs) |
291 | reg += s5m8767->buck_gpioindex; | |
9767ec7f SK |
292 | break; |
293 | case S5M8767_BUCK5: | |
294 | reg = S5M8767_REG_BUCK5CTRL2; | |
295 | break; | |
296 | case S5M8767_BUCK6 ... S5M8767_BUCK9: | |
297 | reg = S5M8767_REG_BUCK6CTRL2 + (reg_id - S5M8767_BUCK6) * 2; | |
298 | break; | |
299 | default: | |
300 | return -EINVAL; | |
301 | } | |
302 | ||
31a932e1 | 303 | return reg; |
9767ec7f SK |
304 | } |
305 | ||
854f73ec AL |
306 | static int s5m8767_convert_voltage_to_sel(const struct sec_voltage_desc *desc, |
307 | int min_vol) | |
9767ec7f | 308 | { |
5b5e977c | 309 | int selector = 0; |
9767ec7f SK |
310 | |
311 | if (desc == NULL) | |
312 | return -EINVAL; | |
313 | ||
854f73ec | 314 | if (min_vol > desc->max) |
9767ec7f SK |
315 | return -EINVAL; |
316 | ||
94e85a3c AL |
317 | if (min_vol < desc->min) |
318 | min_vol = desc->min; | |
319 | ||
320 | selector = DIV_ROUND_UP(min_vol - desc->min, desc->step); | |
9767ec7f | 321 | |
854f73ec | 322 | if (desc->min + desc->step * selector > desc->max) |
9767ec7f SK |
323 | return -EINVAL; |
324 | ||
5b5e977c | 325 | return selector; |
9767ec7f SK |
326 | } |
327 | ||
df2643cf | 328 | static inline int s5m8767_set_high(struct s5m8767_info *s5m8767) |
321d2aba AL |
329 | { |
330 | int temp_index = s5m8767->buck_gpioindex; | |
331 | ||
332 | gpio_set_value(s5m8767->buck_gpios[0], (temp_index >> 2) & 0x1); | |
333 | gpio_set_value(s5m8767->buck_gpios[1], (temp_index >> 1) & 0x1); | |
334 | gpio_set_value(s5m8767->buck_gpios[2], temp_index & 0x1); | |
df2643cf SK |
335 | |
336 | return 0; | |
321d2aba AL |
337 | } |
338 | ||
df2643cf | 339 | static inline int s5m8767_set_low(struct s5m8767_info *s5m8767) |
321d2aba AL |
340 | { |
341 | int temp_index = s5m8767->buck_gpioindex; | |
342 | ||
343 | gpio_set_value(s5m8767->buck_gpios[2], temp_index & 0x1); | |
344 | gpio_set_value(s5m8767->buck_gpios[1], (temp_index >> 1) & 0x1); | |
345 | gpio_set_value(s5m8767->buck_gpios[0], (temp_index >> 2) & 0x1); | |
df2643cf SK |
346 | |
347 | return 0; | |
321d2aba AL |
348 | } |
349 | ||
df2643cf SK |
350 | static int s5m8767_set_voltage_sel(struct regulator_dev *rdev, |
351 | unsigned selector) | |
9767ec7f SK |
352 | { |
353 | struct s5m8767_info *s5m8767 = rdev_get_drvdata(rdev); | |
20a14b84 | 354 | int reg_id = rdev_get_id(rdev); |
31a932e1 | 355 | int old_index, index = 0; |
321d2aba | 356 | u8 *buck234_vol = NULL; |
9767ec7f SK |
357 | |
358 | switch (reg_id) { | |
359 | case S5M8767_LDO1 ... S5M8767_LDO28: | |
9767ec7f SK |
360 | break; |
361 | case S5M8767_BUCK1 ... S5M8767_BUCK6: | |
321d2aba AL |
362 | if (reg_id == S5M8767_BUCK2 && s5m8767->buck2_gpiodvs) |
363 | buck234_vol = &s5m8767->buck2_vol[0]; | |
364 | else if (reg_id == S5M8767_BUCK3 && s5m8767->buck3_gpiodvs) | |
365 | buck234_vol = &s5m8767->buck3_vol[0]; | |
366 | else if (reg_id == S5M8767_BUCK4 && s5m8767->buck4_gpiodvs) | |
367 | buck234_vol = &s5m8767->buck4_vol[0]; | |
9767ec7f SK |
368 | break; |
369 | case S5M8767_BUCK7 ... S5M8767_BUCK8: | |
370 | return -EINVAL; | |
371 | case S5M8767_BUCK9: | |
9767ec7f SK |
372 | break; |
373 | default: | |
374 | return -EINVAL; | |
375 | } | |
376 | ||
321d2aba AL |
377 | /* buck234_vol != NULL means to control buck234 voltage via DVS GPIO */ |
378 | if (buck234_vol) { | |
df2643cf | 379 | while (*buck234_vol != selector) { |
321d2aba AL |
380 | buck234_vol++; |
381 | index++; | |
382 | } | |
383 | old_index = s5m8767->buck_gpioindex; | |
384 | s5m8767->buck_gpioindex = index; | |
385 | ||
386 | if (index > old_index) | |
df2643cf | 387 | return s5m8767_set_high(s5m8767); |
321d2aba | 388 | else |
df2643cf | 389 | return s5m8767_set_low(s5m8767); |
321d2aba | 390 | } else { |
31a932e1 | 391 | return regulator_set_voltage_sel_regmap(rdev, selector); |
321d2aba | 392 | } |
9767ec7f SK |
393 | } |
394 | ||
9767ec7f SK |
395 | static int s5m8767_set_voltage_time_sel(struct regulator_dev *rdev, |
396 | unsigned int old_sel, | |
397 | unsigned int new_sel) | |
398 | { | |
399 | struct s5m8767_info *s5m8767 = rdev_get_drvdata(rdev); | |
63063bfb | 400 | const struct sec_voltage_desc *desc; |
20a14b84 | 401 | int reg_id = rdev_get_id(rdev); |
9767ec7f | 402 | |
9767ec7f SK |
403 | desc = reg_voltage_map[reg_id]; |
404 | ||
9d88fc0b | 405 | if ((old_sel < new_sel) && s5m8767->ramp_delay) |
89e0f0e4 | 406 | return DIV_ROUND_UP(desc->step * (new_sel - old_sel), |
0f8b9c77 | 407 | s5m8767->ramp_delay * 1000); |
89e0f0e4 | 408 | return 0; |
9767ec7f SK |
409 | } |
410 | ||
d35aad0c | 411 | static struct regulator_ops s5m8767_ops = { |
e2eb169b | 412 | .list_voltage = regulator_list_voltage_linear, |
9767ec7f SK |
413 | .is_enabled = s5m8767_reg_is_enabled, |
414 | .enable = s5m8767_reg_enable, | |
415 | .disable = s5m8767_reg_disable, | |
31a932e1 | 416 | .get_voltage_sel = regulator_get_voltage_sel_regmap, |
df2643cf | 417 | .set_voltage_sel = s5m8767_set_voltage_sel, |
9767ec7f SK |
418 | .set_voltage_time_sel = s5m8767_set_voltage_time_sel, |
419 | }; | |
420 | ||
e2eb169b | 421 | static struct regulator_ops s5m8767_buck78_ops = { |
463616ea | 422 | .list_voltage = regulator_list_voltage_linear, |
e2eb169b AL |
423 | .is_enabled = s5m8767_reg_is_enabled, |
424 | .enable = s5m8767_reg_enable, | |
425 | .disable = s5m8767_reg_disable, | |
463616ea KK |
426 | .get_voltage_sel = regulator_get_voltage_sel_regmap, |
427 | .set_voltage_sel = regulator_set_voltage_sel_regmap, | |
e2eb169b AL |
428 | }; |
429 | ||
65896e73 AL |
430 | #define s5m8767_regulator_desc(_name) { \ |
431 | .name = #_name, \ | |
432 | .id = S5M8767_##_name, \ | |
433 | .ops = &s5m8767_ops, \ | |
9767ec7f SK |
434 | .type = REGULATOR_VOLTAGE, \ |
435 | .owner = THIS_MODULE, \ | |
436 | } | |
437 | ||
e2eb169b AL |
438 | #define s5m8767_regulator_buck78_desc(_name) { \ |
439 | .name = #_name, \ | |
440 | .id = S5M8767_##_name, \ | |
441 | .ops = &s5m8767_buck78_ops, \ | |
442 | .type = REGULATOR_VOLTAGE, \ | |
443 | .owner = THIS_MODULE, \ | |
444 | } | |
445 | ||
9767ec7f | 446 | static struct regulator_desc regulators[] = { |
65896e73 AL |
447 | s5m8767_regulator_desc(LDO1), |
448 | s5m8767_regulator_desc(LDO2), | |
449 | s5m8767_regulator_desc(LDO3), | |
450 | s5m8767_regulator_desc(LDO4), | |
451 | s5m8767_regulator_desc(LDO5), | |
452 | s5m8767_regulator_desc(LDO6), | |
453 | s5m8767_regulator_desc(LDO7), | |
454 | s5m8767_regulator_desc(LDO8), | |
455 | s5m8767_regulator_desc(LDO9), | |
456 | s5m8767_regulator_desc(LDO10), | |
457 | s5m8767_regulator_desc(LDO11), | |
458 | s5m8767_regulator_desc(LDO12), | |
459 | s5m8767_regulator_desc(LDO13), | |
460 | s5m8767_regulator_desc(LDO14), | |
461 | s5m8767_regulator_desc(LDO15), | |
462 | s5m8767_regulator_desc(LDO16), | |
463 | s5m8767_regulator_desc(LDO17), | |
464 | s5m8767_regulator_desc(LDO18), | |
465 | s5m8767_regulator_desc(LDO19), | |
466 | s5m8767_regulator_desc(LDO20), | |
467 | s5m8767_regulator_desc(LDO21), | |
468 | s5m8767_regulator_desc(LDO22), | |
469 | s5m8767_regulator_desc(LDO23), | |
470 | s5m8767_regulator_desc(LDO24), | |
471 | s5m8767_regulator_desc(LDO25), | |
472 | s5m8767_regulator_desc(LDO26), | |
473 | s5m8767_regulator_desc(LDO27), | |
474 | s5m8767_regulator_desc(LDO28), | |
475 | s5m8767_regulator_desc(BUCK1), | |
476 | s5m8767_regulator_desc(BUCK2), | |
477 | s5m8767_regulator_desc(BUCK3), | |
478 | s5m8767_regulator_desc(BUCK4), | |
479 | s5m8767_regulator_desc(BUCK5), | |
480 | s5m8767_regulator_desc(BUCK6), | |
e2eb169b AL |
481 | s5m8767_regulator_buck78_desc(BUCK7), |
482 | s5m8767_regulator_buck78_desc(BUCK8), | |
65896e73 | 483 | s5m8767_regulator_desc(BUCK9), |
9767ec7f SK |
484 | }; |
485 | ||
26aec009 ADK |
486 | #ifdef CONFIG_OF |
487 | static int s5m8767_pmic_dt_parse_dvs_gpio(struct sec_pmic_dev *iodev, | |
488 | struct sec_platform_data *pdata, | |
489 | struct device_node *pmic_np) | |
490 | { | |
491 | int i, gpio; | |
492 | ||
493 | for (i = 0; i < 3; i++) { | |
494 | gpio = of_get_named_gpio(pmic_np, | |
495 | "s5m8767,pmic-buck-dvs-gpios", i); | |
496 | if (!gpio_is_valid(gpio)) { | |
497 | dev_err(iodev->dev, "invalid gpio[%d]: %d\n", i, gpio); | |
498 | return -EINVAL; | |
499 | } | |
500 | pdata->buck_gpios[i] = gpio; | |
501 | } | |
502 | return 0; | |
503 | } | |
504 | ||
505 | static int s5m8767_pmic_dt_parse_ds_gpio(struct sec_pmic_dev *iodev, | |
506 | struct sec_platform_data *pdata, | |
507 | struct device_node *pmic_np) | |
508 | { | |
509 | int i, gpio; | |
510 | ||
511 | for (i = 0; i < 3; i++) { | |
512 | gpio = of_get_named_gpio(pmic_np, | |
513 | "s5m8767,pmic-buck-ds-gpios", i); | |
514 | if (!gpio_is_valid(gpio)) { | |
515 | dev_err(iodev->dev, "invalid gpio[%d]: %d\n", i, gpio); | |
516 | return -EINVAL; | |
517 | } | |
518 | pdata->buck_ds[i] = gpio; | |
519 | } | |
520 | return 0; | |
521 | } | |
522 | ||
cbb0ed49 | 523 | static int s5m8767_pmic_dt_parse_pdata(struct platform_device *pdev, |
26aec009 ADK |
524 | struct sec_platform_data *pdata) |
525 | { | |
cbb0ed49 | 526 | struct sec_pmic_dev *iodev = dev_get_drvdata(pdev->dev.parent); |
26aec009 ADK |
527 | struct device_node *pmic_np, *regulators_np, *reg_np; |
528 | struct sec_regulator_data *rdata; | |
529 | struct sec_opmode_data *rmode; | |
04f9f068 | 530 | unsigned int i, dvs_voltage_nr = 8, ret; |
26aec009 ADK |
531 | |
532 | pmic_np = iodev->dev->of_node; | |
533 | if (!pmic_np) { | |
534 | dev_err(iodev->dev, "could not find pmic sub-node\n"); | |
535 | return -ENODEV; | |
536 | } | |
537 | ||
4e52c03d | 538 | regulators_np = of_get_child_by_name(pmic_np, "regulators"); |
26aec009 ADK |
539 | if (!regulators_np) { |
540 | dev_err(iodev->dev, "could not find regulators sub-node\n"); | |
541 | return -EINVAL; | |
542 | } | |
543 | ||
544 | /* count the number of regulators to be supported in pmic */ | |
1f91b6f6 | 545 | pdata->num_regulators = of_get_child_count(regulators_np); |
26aec009 | 546 | |
cbb0ed49 | 547 | rdata = devm_kzalloc(&pdev->dev, sizeof(*rdata) * |
26aec009 ADK |
548 | pdata->num_regulators, GFP_KERNEL); |
549 | if (!rdata) { | |
550 | dev_err(iodev->dev, | |
551 | "could not allocate memory for regulator data\n"); | |
552 | return -ENOMEM; | |
553 | } | |
554 | ||
cbb0ed49 | 555 | rmode = devm_kzalloc(&pdev->dev, sizeof(*rmode) * |
26aec009 | 556 | pdata->num_regulators, GFP_KERNEL); |
720a9717 | 557 | if (!rmode) { |
26aec009 ADK |
558 | dev_err(iodev->dev, |
559 | "could not allocate memory for regulator mode\n"); | |
560 | return -ENOMEM; | |
561 | } | |
562 | ||
563 | pdata->regulators = rdata; | |
564 | pdata->opmode = rmode; | |
565 | for_each_child_of_node(regulators_np, reg_np) { | |
566 | for (i = 0; i < ARRAY_SIZE(regulators); i++) | |
567 | if (!of_node_cmp(reg_np->name, regulators[i].name)) | |
568 | break; | |
569 | ||
570 | if (i == ARRAY_SIZE(regulators)) { | |
571 | dev_warn(iodev->dev, | |
572 | "don't know how to configure regulator %s\n", | |
573 | reg_np->name); | |
574 | continue; | |
575 | } | |
576 | ||
577 | rdata->id = i; | |
578 | rdata->initdata = of_get_regulator_init_data( | |
cbb0ed49 | 579 | &pdev->dev, reg_np); |
26aec009 ADK |
580 | rdata->reg_node = reg_np; |
581 | rdata++; | |
582 | rmode->id = i; | |
583 | if (of_property_read_u32(reg_np, "op_mode", | |
584 | &rmode->mode)) { | |
585 | dev_warn(iodev->dev, | |
586 | "no op_mode property property at %s\n", | |
587 | reg_np->full_name); | |
588 | ||
589 | rmode->mode = S5M8767_OPMODE_NORMAL_MODE; | |
590 | } | |
591 | rmode++; | |
592 | } | |
593 | ||
b7db01f3 SK |
594 | of_node_put(regulators_np); |
595 | ||
04f9f068 | 596 | if (of_get_property(pmic_np, "s5m8767,pmic-buck2-uses-gpio-dvs", NULL)) { |
26aec009 ADK |
597 | pdata->buck2_gpiodvs = true; |
598 | ||
04f9f068 CC |
599 | if (of_property_read_u32_array(pmic_np, |
600 | "s5m8767,pmic-buck2-dvs-voltage", | |
601 | pdata->buck2_voltage, dvs_voltage_nr)) { | |
602 | dev_err(iodev->dev, "buck2 voltages not specified\n"); | |
603 | return -EINVAL; | |
604 | } | |
605 | } | |
606 | ||
607 | if (of_get_property(pmic_np, "s5m8767,pmic-buck3-uses-gpio-dvs", NULL)) { | |
26aec009 ADK |
608 | pdata->buck3_gpiodvs = true; |
609 | ||
04f9f068 CC |
610 | if (of_property_read_u32_array(pmic_np, |
611 | "s5m8767,pmic-buck3-dvs-voltage", | |
612 | pdata->buck3_voltage, dvs_voltage_nr)) { | |
613 | dev_err(iodev->dev, "buck3 voltages not specified\n"); | |
614 | return -EINVAL; | |
615 | } | |
616 | } | |
617 | ||
618 | if (of_get_property(pmic_np, "s5m8767,pmic-buck4-uses-gpio-dvs", NULL)) { | |
26aec009 ADK |
619 | pdata->buck4_gpiodvs = true; |
620 | ||
04f9f068 CC |
621 | if (of_property_read_u32_array(pmic_np, |
622 | "s5m8767,pmic-buck4-dvs-voltage", | |
623 | pdata->buck4_voltage, dvs_voltage_nr)) { | |
624 | dev_err(iodev->dev, "buck4 voltages not specified\n"); | |
625 | return -EINVAL; | |
626 | } | |
627 | } | |
628 | ||
26aec009 ADK |
629 | if (pdata->buck2_gpiodvs || pdata->buck3_gpiodvs || |
630 | pdata->buck4_gpiodvs) { | |
631 | ret = s5m8767_pmic_dt_parse_dvs_gpio(iodev, pdata, pmic_np); | |
632 | if (ret) | |
633 | return -EINVAL; | |
634 | ||
635 | if (of_property_read_u32(pmic_np, | |
636 | "s5m8767,pmic-buck-default-dvs-idx", | |
637 | &pdata->buck_default_idx)) { | |
638 | pdata->buck_default_idx = 0; | |
639 | } else { | |
640 | if (pdata->buck_default_idx >= 8) { | |
641 | pdata->buck_default_idx = 0; | |
642 | dev_info(iodev->dev, | |
643 | "invalid value for default dvs index, use 0\n"); | |
644 | } | |
645 | } | |
26aec009 ADK |
646 | } |
647 | ||
648 | ret = s5m8767_pmic_dt_parse_ds_gpio(iodev, pdata, pmic_np); | |
649 | if (ret) | |
650 | return -EINVAL; | |
651 | ||
033054e8 CC |
652 | if (of_get_property(pmic_np, "s5m8767,pmic-buck2-ramp-enable", NULL)) |
653 | pdata->buck2_ramp_enable = true; | |
26aec009 | 654 | |
033054e8 CC |
655 | if (of_get_property(pmic_np, "s5m8767,pmic-buck3-ramp-enable", NULL)) |
656 | pdata->buck3_ramp_enable = true; | |
26aec009 | 657 | |
033054e8 CC |
658 | if (of_get_property(pmic_np, "s5m8767,pmic-buck4-ramp-enable", NULL)) |
659 | pdata->buck4_ramp_enable = true; | |
660 | ||
661 | if (pdata->buck2_ramp_enable || pdata->buck3_ramp_enable | |
662 | || pdata->buck4_ramp_enable) { | |
663 | if (of_property_read_u32(pmic_np, "s5m8767,pmic-buck-ramp-delay", | |
664 | &pdata->buck_ramp_delay)) | |
665 | pdata->buck_ramp_delay = 0; | |
26aec009 ADK |
666 | } |
667 | ||
668 | return 0; | |
669 | } | |
670 | #else | |
cbb0ed49 | 671 | static int s5m8767_pmic_dt_parse_pdata(struct platform_device *pdev, |
26aec009 ADK |
672 | struct sec_platform_data *pdata) |
673 | { | |
674 | return 0; | |
675 | } | |
676 | #endif /* CONFIG_OF */ | |
677 | ||
a5023574 | 678 | static int s5m8767_pmic_probe(struct platform_device *pdev) |
9767ec7f | 679 | { |
63063bfb | 680 | struct sec_pmic_dev *iodev = dev_get_drvdata(pdev->dev.parent); |
26aec009 | 681 | struct sec_platform_data *pdata = iodev->pdata; |
c172708d | 682 | struct regulator_config config = { }; |
9767ec7f SK |
683 | struct regulator_dev **rdev; |
684 | struct s5m8767_info *s5m8767; | |
c848bc85 | 685 | int i, ret, size, buck_init; |
9767ec7f | 686 | |
e81d7bc8 AL |
687 | if (!pdata) { |
688 | dev_err(pdev->dev.parent, "Platform data not supplied\n"); | |
689 | return -ENODEV; | |
690 | } | |
691 | ||
26aec009 | 692 | if (iodev->dev->of_node) { |
cbb0ed49 | 693 | ret = s5m8767_pmic_dt_parse_pdata(pdev, pdata); |
26aec009 ADK |
694 | if (ret) |
695 | return ret; | |
696 | } | |
697 | ||
6c4efe24 AL |
698 | if (pdata->buck2_gpiodvs) { |
699 | if (pdata->buck3_gpiodvs || pdata->buck4_gpiodvs) { | |
700 | dev_err(&pdev->dev, "S5M8767 GPIO DVS NOT VALID\n"); | |
701 | return -EINVAL; | |
702 | } | |
703 | } | |
704 | ||
705 | if (pdata->buck3_gpiodvs) { | |
706 | if (pdata->buck2_gpiodvs || pdata->buck4_gpiodvs) { | |
707 | dev_err(&pdev->dev, "S5M8767 GPIO DVS NOT VALID\n"); | |
708 | return -EINVAL; | |
709 | } | |
710 | } | |
711 | ||
712 | if (pdata->buck4_gpiodvs) { | |
713 | if (pdata->buck2_gpiodvs || pdata->buck3_gpiodvs) { | |
714 | dev_err(&pdev->dev, "S5M8767 GPIO DVS NOT VALID\n"); | |
715 | return -EINVAL; | |
716 | } | |
717 | } | |
718 | ||
9767ec7f SK |
719 | s5m8767 = devm_kzalloc(&pdev->dev, sizeof(struct s5m8767_info), |
720 | GFP_KERNEL); | |
721 | if (!s5m8767) | |
722 | return -ENOMEM; | |
723 | ||
724 | size = sizeof(struct regulator_dev *) * (S5M8767_REG_MAX - 2); | |
725 | s5m8767->rdev = devm_kzalloc(&pdev->dev, size, GFP_KERNEL); | |
726 | if (!s5m8767->rdev) | |
727 | return -ENOMEM; | |
728 | ||
729 | rdev = s5m8767->rdev; | |
730 | s5m8767->dev = &pdev->dev; | |
731 | s5m8767->iodev = iodev; | |
9bb096ff | 732 | s5m8767->num_regulators = pdata->num_regulators; |
9767ec7f | 733 | platform_set_drvdata(pdev, s5m8767); |
9767ec7f SK |
734 | |
735 | s5m8767->buck_gpioindex = pdata->buck_default_idx; | |
736 | s5m8767->buck2_gpiodvs = pdata->buck2_gpiodvs; | |
737 | s5m8767->buck3_gpiodvs = pdata->buck3_gpiodvs; | |
738 | s5m8767->buck4_gpiodvs = pdata->buck4_gpiodvs; | |
739 | s5m8767->buck_gpios[0] = pdata->buck_gpios[0]; | |
740 | s5m8767->buck_gpios[1] = pdata->buck_gpios[1]; | |
741 | s5m8767->buck_gpios[2] = pdata->buck_gpios[2]; | |
c848bc85 SK |
742 | s5m8767->buck_ds[0] = pdata->buck_ds[0]; |
743 | s5m8767->buck_ds[1] = pdata->buck_ds[1]; | |
744 | s5m8767->buck_ds[2] = pdata->buck_ds[2]; | |
745 | ||
9767ec7f SK |
746 | s5m8767->ramp_delay = pdata->buck_ramp_delay; |
747 | s5m8767->buck2_ramp = pdata->buck2_ramp_enable; | |
748 | s5m8767->buck3_ramp = pdata->buck3_ramp_enable; | |
749 | s5m8767->buck4_ramp = pdata->buck4_ramp_enable; | |
7e44bb83 | 750 | s5m8767->opmode = pdata->opmode; |
9767ec7f | 751 | |
c848bc85 | 752 | buck_init = s5m8767_convert_voltage_to_sel(&buck_voltage_val2, |
854f73ec | 753 | pdata->buck2_init); |
c848bc85 | 754 | |
d13733f4 KK |
755 | regmap_write(s5m8767->iodev->regmap_pmic, S5M8767_REG_BUCK2DVS2, |
756 | buck_init); | |
c848bc85 SK |
757 | |
758 | buck_init = s5m8767_convert_voltage_to_sel(&buck_voltage_val2, | |
854f73ec | 759 | pdata->buck3_init); |
c848bc85 | 760 | |
d13733f4 KK |
761 | regmap_write(s5m8767->iodev->regmap_pmic, S5M8767_REG_BUCK3DVS2, |
762 | buck_init); | |
c848bc85 SK |
763 | |
764 | buck_init = s5m8767_convert_voltage_to_sel(&buck_voltage_val2, | |
854f73ec | 765 | pdata->buck4_init); |
c848bc85 | 766 | |
d13733f4 KK |
767 | regmap_write(s5m8767->iodev->regmap_pmic, S5M8767_REG_BUCK4DVS2, |
768 | buck_init); | |
c848bc85 | 769 | |
9767ec7f SK |
770 | for (i = 0; i < 8; i++) { |
771 | if (s5m8767->buck2_gpiodvs) { | |
772 | s5m8767->buck2_vol[i] = | |
5b5e977c | 773 | s5m8767_convert_voltage_to_sel( |
9767ec7f | 774 | &buck_voltage_val2, |
854f73ec | 775 | pdata->buck2_voltage[i]); |
9767ec7f SK |
776 | } |
777 | ||
778 | if (s5m8767->buck3_gpiodvs) { | |
779 | s5m8767->buck3_vol[i] = | |
5b5e977c | 780 | s5m8767_convert_voltage_to_sel( |
9767ec7f | 781 | &buck_voltage_val2, |
854f73ec | 782 | pdata->buck3_voltage[i]); |
9767ec7f SK |
783 | } |
784 | ||
785 | if (s5m8767->buck4_gpiodvs) { | |
786 | s5m8767->buck4_vol[i] = | |
5b5e977c | 787 | s5m8767_convert_voltage_to_sel( |
9767ec7f | 788 | &buck_voltage_val2, |
854f73ec | 789 | pdata->buck4_voltage[i]); |
9767ec7f SK |
790 | } |
791 | } | |
792 | ||
76c854d1 ADK |
793 | if (pdata->buck2_gpiodvs || pdata->buck3_gpiodvs || |
794 | pdata->buck4_gpiodvs) { | |
795 | ||
796 | if (!gpio_is_valid(pdata->buck_gpios[0]) || | |
797 | !gpio_is_valid(pdata->buck_gpios[1]) || | |
798 | !gpio_is_valid(pdata->buck_gpios[2])) { | |
799 | dev_err(&pdev->dev, "GPIO NOT VALID\n"); | |
800 | return -EINVAL; | |
801 | } | |
802 | ||
5febb3c9 AL |
803 | ret = devm_gpio_request(&pdev->dev, pdata->buck_gpios[0], |
804 | "S5M8767 SET1"); | |
805 | if (ret) | |
806 | return ret; | |
807 | ||
808 | ret = devm_gpio_request(&pdev->dev, pdata->buck_gpios[1], | |
809 | "S5M8767 SET2"); | |
810 | if (ret) | |
811 | return ret; | |
812 | ||
813 | ret = devm_gpio_request(&pdev->dev, pdata->buck_gpios[2], | |
814 | "S5M8767 SET3"); | |
815 | if (ret) | |
816 | return ret; | |
817 | ||
c848bc85 SK |
818 | /* SET1 GPIO */ |
819 | gpio_direction_output(pdata->buck_gpios[0], | |
820 | (s5m8767->buck_gpioindex >> 2) & 0x1); | |
821 | /* SET2 GPIO */ | |
822 | gpio_direction_output(pdata->buck_gpios[1], | |
823 | (s5m8767->buck_gpioindex >> 1) & 0x1); | |
824 | /* SET3 GPIO */ | |
825 | gpio_direction_output(pdata->buck_gpios[2], | |
826 | (s5m8767->buck_gpioindex >> 0) & 0x1); | |
9767ec7f SK |
827 | } |
828 | ||
5febb3c9 AL |
829 | ret = devm_gpio_request(&pdev->dev, pdata->buck_ds[0], "S5M8767 DS2"); |
830 | if (ret) | |
831 | return ret; | |
c848bc85 | 832 | |
5febb3c9 AL |
833 | ret = devm_gpio_request(&pdev->dev, pdata->buck_ds[1], "S5M8767 DS3"); |
834 | if (ret) | |
835 | return ret; | |
c848bc85 | 836 | |
5febb3c9 AL |
837 | ret = devm_gpio_request(&pdev->dev, pdata->buck_ds[2], "S5M8767 DS4"); |
838 | if (ret) | |
839 | return ret; | |
c848bc85 SK |
840 | |
841 | /* DS2 GPIO */ | |
842 | gpio_direction_output(pdata->buck_ds[0], 0x0); | |
843 | /* DS3 GPIO */ | |
844 | gpio_direction_output(pdata->buck_ds[1], 0x0); | |
845 | /* DS4 GPIO */ | |
846 | gpio_direction_output(pdata->buck_ds[2], 0x0); | |
847 | ||
848 | if (pdata->buck2_gpiodvs || pdata->buck3_gpiodvs || | |
849 | pdata->buck4_gpiodvs) { | |
d13733f4 KK |
850 | regmap_update_bits(s5m8767->iodev->regmap_pmic, |
851 | S5M8767_REG_BUCK2CTRL, 1 << 1, | |
852 | (pdata->buck2_gpiodvs) ? (1 << 1) : (0 << 1)); | |
853 | regmap_update_bits(s5m8767->iodev->regmap_pmic, | |
854 | S5M8767_REG_BUCK3CTRL, 1 << 1, | |
855 | (pdata->buck3_gpiodvs) ? (1 << 1) : (0 << 1)); | |
856 | regmap_update_bits(s5m8767->iodev->regmap_pmic, | |
857 | S5M8767_REG_BUCK4CTRL, 1 << 1, | |
858 | (pdata->buck4_gpiodvs) ? (1 << 1) : (0 << 1)); | |
c848bc85 | 859 | } |
9767ec7f SK |
860 | |
861 | /* Initialize GPIO DVS registers */ | |
862 | for (i = 0; i < 8; i++) { | |
863 | if (s5m8767->buck2_gpiodvs) { | |
d13733f4 KK |
864 | regmap_write(s5m8767->iodev->regmap_pmic, |
865 | S5M8767_REG_BUCK2DVS1 + i, | |
866 | s5m8767->buck2_vol[i]); | |
9767ec7f SK |
867 | } |
868 | ||
869 | if (s5m8767->buck3_gpiodvs) { | |
d13733f4 KK |
870 | regmap_write(s5m8767->iodev->regmap_pmic, |
871 | S5M8767_REG_BUCK3DVS1 + i, | |
872 | s5m8767->buck3_vol[i]); | |
9767ec7f SK |
873 | } |
874 | ||
875 | if (s5m8767->buck4_gpiodvs) { | |
d13733f4 KK |
876 | regmap_write(s5m8767->iodev->regmap_pmic, |
877 | S5M8767_REG_BUCK4DVS1 + i, | |
878 | s5m8767->buck4_vol[i]); | |
9767ec7f SK |
879 | } |
880 | } | |
9767ec7f SK |
881 | |
882 | if (s5m8767->buck2_ramp) | |
d13733f4 KK |
883 | regmap_update_bits(s5m8767->iodev->regmap_pmic, |
884 | S5M8767_REG_DVSRAMP, 0x08, 0x08); | |
9767ec7f SK |
885 | |
886 | if (s5m8767->buck3_ramp) | |
d13733f4 KK |
887 | regmap_update_bits(s5m8767->iodev->regmap_pmic, |
888 | S5M8767_REG_DVSRAMP, 0x04, 0x04); | |
9767ec7f SK |
889 | |
890 | if (s5m8767->buck4_ramp) | |
d13733f4 KK |
891 | regmap_update_bits(s5m8767->iodev->regmap_pmic, |
892 | S5M8767_REG_DVSRAMP, 0x02, 0x02); | |
9767ec7f SK |
893 | |
894 | if (s5m8767->buck2_ramp || s5m8767->buck3_ramp | |
895 | || s5m8767->buck4_ramp) { | |
f37ff6b6 | 896 | unsigned int val; |
9767ec7f | 897 | switch (s5m8767->ramp_delay) { |
1af142c6 | 898 | case 5: |
f37ff6b6 | 899 | val = S5M8767_DVS_BUCK_RAMP_5; |
1af142c6 SK |
900 | break; |
901 | case 10: | |
f37ff6b6 | 902 | val = S5M8767_DVS_BUCK_RAMP_10; |
047ec220 | 903 | break; |
9767ec7f | 904 | case 25: |
f37ff6b6 | 905 | val = S5M8767_DVS_BUCK_RAMP_25; |
047ec220 | 906 | break; |
9767ec7f | 907 | case 50: |
f37ff6b6 | 908 | val = S5M8767_DVS_BUCK_RAMP_50; |
047ec220 | 909 | break; |
9767ec7f | 910 | case 100: |
f37ff6b6 | 911 | val = S5M8767_DVS_BUCK_RAMP_100; |
047ec220 | 912 | break; |
9767ec7f | 913 | default: |
f37ff6b6 | 914 | val = S5M8767_DVS_BUCK_RAMP_10; |
9767ec7f | 915 | } |
d13733f4 KK |
916 | regmap_update_bits(s5m8767->iodev->regmap_pmic, |
917 | S5M8767_REG_DVSRAMP, | |
918 | S5M8767_DVS_BUCK_RAMP_MASK, | |
919 | val << S5M8767_DVS_BUCK_RAMP_SHIFT); | |
9767ec7f SK |
920 | } |
921 | ||
922 | for (i = 0; i < pdata->num_regulators; i++) { | |
63063bfb | 923 | const struct sec_voltage_desc *desc; |
9767ec7f SK |
924 | int id = pdata->regulators[i].id; |
925 | ||
926 | desc = reg_voltage_map[id]; | |
e2eb169b | 927 | if (desc) { |
9767ec7f SK |
928 | regulators[id].n_voltages = |
929 | (desc->max - desc->min) / desc->step + 1; | |
e2eb169b AL |
930 | regulators[id].min_uV = desc->min; |
931 | regulators[id].uV_step = desc->step; | |
31a932e1 AL |
932 | regulators[id].vsel_reg = |
933 | s5m8767_get_vsel_reg(id, s5m8767); | |
934 | if (id < S5M8767_BUCK1) | |
935 | regulators[id].vsel_mask = 0x3f; | |
936 | else | |
937 | regulators[id].vsel_mask = 0xff; | |
e2eb169b | 938 | } |
9767ec7f | 939 | |
c172708d MB |
940 | config.dev = s5m8767->dev; |
941 | config.init_data = pdata->regulators[i].initdata; | |
942 | config.driver_data = s5m8767; | |
3e1e4a5f | 943 | config.regmap = iodev->regmap_pmic; |
26aec009 | 944 | config.of_node = pdata->regulators[i].reg_node; |
c172708d | 945 | |
f0db475d MB |
946 | rdev[i] = devm_regulator_register(&pdev->dev, ®ulators[id], |
947 | &config); | |
9767ec7f SK |
948 | if (IS_ERR(rdev[i])) { |
949 | ret = PTR_ERR(rdev[i]); | |
950 | dev_err(s5m8767->dev, "regulator init failed for %d\n", | |
951 | id); | |
f0db475d | 952 | return ret; |
9767ec7f SK |
953 | } |
954 | } | |
955 | ||
9767ec7f SK |
956 | return 0; |
957 | } | |
958 | ||
959 | static const struct platform_device_id s5m8767_pmic_id[] = { | |
960 | { "s5m8767-pmic", 0}, | |
961 | { }, | |
962 | }; | |
963 | MODULE_DEVICE_TABLE(platform, s5m8767_pmic_id); | |
964 | ||
965 | static struct platform_driver s5m8767_pmic_driver = { | |
966 | .driver = { | |
967 | .name = "s5m8767-pmic", | |
968 | .owner = THIS_MODULE, | |
969 | }, | |
970 | .probe = s5m8767_pmic_probe, | |
9767ec7f SK |
971 | .id_table = s5m8767_pmic_id, |
972 | }; | |
973 | ||
974 | static int __init s5m8767_pmic_init(void) | |
975 | { | |
976 | return platform_driver_register(&s5m8767_pmic_driver); | |
977 | } | |
978 | subsys_initcall(s5m8767_pmic_init); | |
979 | ||
980 | static void __exit s5m8767_pmic_exit(void) | |
981 | { | |
982 | platform_driver_unregister(&s5m8767_pmic_driver); | |
983 | } | |
984 | module_exit(s5m8767_pmic_exit); | |
985 | ||
986 | /* Module information */ | |
987 | MODULE_AUTHOR("Sangbeom Kim <sbkim73@samsung.com>"); | |
988 | MODULE_DESCRIPTION("SAMSUNG S5M8767 Regulator Driver"); | |
989 | MODULE_LICENSE("GPL"); |