[deliverable/linux.git] / drivers / rtc / rtc-ac100.c

/*
 * RTC Driver for X-Powers AC100
 *
 * Copyright (c) 2016 Chen-Yu Tsai
 *
 * Chen-Yu Tsai <wens@csie.org>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 */

#include <linux/bcd.h>
#include <linux/clk-provider.h>
#include <linux/device.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/mfd/ac100.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/rtc.h>
#include <linux/types.h>

/* Control register */
#define AC100_RTC_CTRL_24HOUR	BIT(0)

/* Clock output register bits */
#define AC100_CLKOUT_PRE_DIV_SHIFT	5
#define AC100_CLKOUT_PRE_DIV_WIDTH	3
#define AC100_CLKOUT_MUX_SHIFT		4
#define AC100_CLKOUT_MUX_WIDTH		1
#define AC100_CLKOUT_DIV_SHIFT		1
#define AC100_CLKOUT_DIV_WIDTH		3
#define AC100_CLKOUT_EN			BIT(0)

/* RTC */
#define AC100_RTC_SEC_MASK	GENMASK(6, 0)
#define AC100_RTC_MIN_MASK	GENMASK(6, 0)
#define AC100_RTC_HOU_MASK	GENMASK(5, 0)
#define AC100_RTC_WEE_MASK	GENMASK(2, 0)
#define AC100_RTC_DAY_MASK	GENMASK(5, 0)
#define AC100_RTC_MON_MASK	GENMASK(4, 0)
#define AC100_RTC_YEA_MASK	GENMASK(7, 0)
#define AC100_RTC_YEA_LEAP	BIT(15)
#define AC100_RTC_UPD_TRIGGER	BIT(15)

/* Alarm (wall clock) */
#define AC100_ALM_INT_ENABLE	BIT(0)

#define AC100_ALM_SEC_MASK	GENMASK(6, 0)
#define AC100_ALM_MIN_MASK	GENMASK(6, 0)
#define AC100_ALM_HOU_MASK	GENMASK(5, 0)
#define AC100_ALM_WEE_MASK	GENMASK(2, 0)
#define AC100_ALM_DAY_MASK	GENMASK(5, 0)
#define AC100_ALM_MON_MASK	GENMASK(4, 0)
#define AC100_ALM_YEA_MASK	GENMASK(7, 0)
#define AC100_ALM_ENABLE_FLAG	BIT(15)
#define AC100_ALM_UPD_TRIGGER	BIT(15)

/*
 * The year parameter passed to the driver is usually an offset relative to
 * the year 1900. This macro is used to convert this offset to another one
 * relative to the minimum year allowed by the hardware.
 *
 * The year range is 1970 - 2069. This range is selected to match Allwinner's
 * driver.
 */
#define AC100_YEAR_MIN				1970
#define AC100_YEAR_MAX				2069
#define AC100_YEAR_OFF				(AC100_YEAR_MIN - 1900)

struct ac100_clkout {
	struct clk_hw hw;
	struct regmap *regmap;
	u8 offset;
};

#define to_ac100_clkout(_hw) container_of(_hw, struct ac100_clkout, hw)

#define AC100_RTC_32K_NAME	"ac100-rtc-32k"
#define AC100_RTC_32K_RATE	32768
#define AC100_CLKOUT_NUM	3

static const char * const ac100_clkout_names[AC100_CLKOUT_NUM] = {
	"ac100-cko1-rtc",
	"ac100-cko2-rtc",
	"ac100-cko3-rtc",
};

struct ac100_rtc_dev {
	struct rtc_device *rtc;
	struct device *dev;
	struct regmap *regmap;
	int irq;
	unsigned long alarm;

	struct clk_hw *rtc_32k_clk;
	struct ac100_clkout clks[AC100_CLKOUT_NUM];
	struct clk_hw_onecell_data *clk_data;
};

/**
 * Clock controls for 3 clock output pins
 */

static const struct clk_div_table ac100_clkout_prediv[] = {
	{ .val = 0, .div = 1 },
	{ .val = 1, .div = 2 },
	{ .val = 2, .div = 4 },
	{ .val = 3, .div = 8 },
	{ .val = 4, .div = 16 },
	{ .val = 5, .div = 32 },
	{ .val = 6, .div = 64 },
	{ .val = 7, .div = 122 },
	{ },
};

/* Abuse the fact that one parent is 32768 Hz, and the other is 4 MHz */
static unsigned long ac100_clkout_recalc_rate(struct clk_hw *hw,
					      unsigned long prate)
{
	struct ac100_clkout *clk = to_ac100_clkout(hw);
	unsigned int reg, div;

	regmap_read(clk->regmap, clk->offset, &reg);

	/* Handle pre-divider first */
	if (prate != AC100_RTC_32K_RATE) {
		div = (reg >> AC100_CLKOUT_PRE_DIV_SHIFT) &
			((1 << AC100_CLKOUT_PRE_DIV_WIDTH) - 1);
		prate = divider_recalc_rate(hw, prate, div,
					    ac100_clkout_prediv, 0);
	}

	div = (reg >> AC100_CLKOUT_DIV_SHIFT) &
		(BIT(AC100_CLKOUT_DIV_WIDTH) - 1);
	return divider_recalc_rate(hw, prate, div, NULL,
				   CLK_DIVIDER_POWER_OF_TWO);
}

static long ac100_clkout_round_rate(struct clk_hw *hw, unsigned long rate,
				    unsigned long prate)
{
	unsigned long best_rate = 0, tmp_rate, tmp_prate;
	int i;

	if (prate == AC100_RTC_32K_RATE)
		return divider_round_rate(hw, rate, &prate, NULL,
					  AC100_CLKOUT_DIV_WIDTH,
					  CLK_DIVIDER_POWER_OF_TWO);

	for (i = 0; ac100_clkout_prediv[i].div; i++) {
		tmp_prate = DIV_ROUND_UP(prate, ac100_clkout_prediv[i].val);
		tmp_rate = divider_round_rate(hw, rate, &tmp_prate, NULL,
					      AC100_CLKOUT_DIV_WIDTH,
					      CLK_DIVIDER_POWER_OF_TWO);

		if (tmp_rate > rate)
			continue;
		if (rate - tmp_rate < best_rate - tmp_rate)
			best_rate = tmp_rate;
	}

	return best_rate;
}

static int ac100_clkout_determine_rate(struct clk_hw *hw,
				       struct clk_rate_request *req)
{
	struct clk_hw *best_parent;
	unsigned long best = 0;
	int i, num_parents = clk_hw_get_num_parents(hw);

	for (i = 0; i < num_parents; i++) {
		struct clk_hw *parent = clk_hw_get_parent_by_index(hw, i);
		unsigned long tmp, prate = clk_hw_get_rate(parent);

		tmp = ac100_clkout_round_rate(hw, req->rate, prate);

		if (tmp > req->rate)
			continue;
		if (req->rate - tmp < req->rate - best) {
			best = tmp;
			best_parent = parent;
		}
	}

	if (!best)
		return -EINVAL;

	req->best_parent_hw = best_parent;
	req->best_parent_rate = best;
	req->rate = best;

	return 0;
}

static int ac100_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
				 unsigned long prate)
{
	struct ac100_clkout *clk = to_ac100_clkout(hw);
	int div = 0, pre_div = 0;

	do {
		div = divider_get_val(rate * ac100_clkout_prediv[pre_div].div,
				      prate, NULL, AC100_CLKOUT_DIV_WIDTH,
				      CLK_DIVIDER_POWER_OF_TWO);
		if (div >= 0)
			break;
	} while (prate != AC100_RTC_32K_RATE &&
		 ac100_clkout_prediv[++pre_div].div);

	if (div < 0)
		return div;

	pre_div = ac100_clkout_prediv[pre_div].val;

	regmap_update_bits(clk->regmap, clk->offset,
			   ((1 << AC100_CLKOUT_DIV_WIDTH) - 1) << AC100_CLKOUT_DIV_SHIFT |
			   ((1 << AC100_CLKOUT_PRE_DIV_WIDTH) - 1) << AC100_CLKOUT_PRE_DIV_SHIFT,
			   (div - 1) << AC100_CLKOUT_DIV_SHIFT |
			   (pre_div - 1) << AC100_CLKOUT_PRE_DIV_SHIFT);

	return 0;
}

static int ac100_clkout_prepare(struct clk_hw *hw)
{
	struct ac100_clkout *clk = to_ac100_clkout(hw);

	return regmap_update_bits(clk->regmap, clk->offset, AC100_CLKOUT_EN,
				  AC100_CLKOUT_EN);
}

static void ac100_clkout_unprepare(struct clk_hw *hw)
{
	struct ac100_clkout *clk = to_ac100_clkout(hw);

	regmap_update_bits(clk->regmap, clk->offset, AC100_CLKOUT_EN, 0);
}

static int ac100_clkout_is_prepared(struct clk_hw *hw)
{
	struct ac100_clkout *clk = to_ac100_clkout(hw);
	unsigned int reg;

	regmap_read(clk->regmap, clk->offset, &reg);

	return reg & AC100_CLKOUT_EN;
}

static u8 ac100_clkout_get_parent(struct clk_hw *hw)
{
	struct ac100_clkout *clk = to_ac100_clkout(hw);
	unsigned int reg;

	regmap_read(clk->regmap, clk->offset, &reg);

	return (reg >> AC100_CLKOUT_MUX_SHIFT) & 0x1;
}

static int ac100_clkout_set_parent(struct clk_hw *hw, u8 index)
{
	struct ac100_clkout *clk = to_ac100_clkout(hw);

	return regmap_update_bits(clk->regmap, clk->offset,
				  BIT(AC100_CLKOUT_MUX_SHIFT),
				  index ? BIT(AC100_CLKOUT_MUX_SHIFT) : 0);
}

static const struct clk_ops ac100_clkout_ops = {
	.prepare	= ac100_clkout_prepare,
	.unprepare	= ac100_clkout_unprepare,
	.is_prepared	= ac100_clkout_is_prepared,
	.recalc_rate	= ac100_clkout_recalc_rate,
	.determine_rate	= ac100_clkout_determine_rate,
	.get_parent	= ac100_clkout_get_parent,
	.set_parent	= ac100_clkout_set_parent,
	.set_rate	= ac100_clkout_set_rate,
};

static int ac100_rtc_register_clks(struct ac100_rtc_dev *chip)
{
	struct device_node *np = chip->dev->of_node;
	const char *parents[2] = {AC100_RTC_32K_NAME};
	int i, ret;

	chip->clk_data = devm_kzalloc(chip->dev, sizeof(*chip->clk_data) +
						 sizeof(*chip->clk_data->hws) *
						 AC100_CLKOUT_NUM,
						 GFP_KERNEL);
	if (!chip->clk_data)
		return -ENOMEM;

	chip->rtc_32k_clk = clk_hw_register_fixed_rate(chip->dev,
						       AC100_RTC_32K_NAME,
						       NULL, 0,
						       AC100_RTC_32K_RATE);
	if (IS_ERR(chip->rtc_32k_clk)) {
		ret = PTR_ERR(chip->rtc_32k_clk);
		dev_err(chip->dev, "Failed to register RTC-32k clock: %d\n",
			ret);
		return ret;
	}

	parents[1] = of_clk_get_parent_name(np, 0);
	if (!parents[1]) {
		dev_err(chip->dev, "Failed to get ADDA 4M clock\n");
		return -EINVAL;
	}

	for (i = 0; i < AC100_CLKOUT_NUM; i++) {
		struct ac100_clkout *clk = &chip->clks[i];
		struct clk_init_data init = {
			.name = ac100_clkout_names[i],
			.ops = &ac100_clkout_ops,
			.parent_names = parents,
			.num_parents = ARRAY_SIZE(parents),
			.flags = 0,
		};

		of_property_read_string_index(np, "clock-output-names",
					      i, &init.name);
		clk->regmap = chip->regmap;
		clk->offset = AC100_CLKOUT_CTRL1 + i;
		clk->hw.init = &init;

		ret = devm_clk_hw_register(chip->dev, &clk->hw);
		if (ret) {
			dev_err(chip->dev, "Failed to register clk '%s': %d\n",
				init.name, ret);
			goto err_unregister_rtc_32k;
		}

		chip->clk_data->hws[i] = &clk->hw;
	}

	chip->clk_data->num = i;
	ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, chip->clk_data);
	if (ret)
		goto err_unregister_rtc_32k;

	return 0;

err_unregister_rtc_32k:
	clk_unregister_fixed_rate(chip->rtc_32k_clk->clk);

	return ret;
}

static void ac100_rtc_unregister_clks(struct ac100_rtc_dev *chip)
{
	of_clk_del_provider(chip->dev->of_node);
	clk_unregister_fixed_rate(chip->rtc_32k_clk->clk);
}

/**
 * RTC related bits
 */
static int ac100_rtc_get_time(struct device *dev, struct rtc_time *rtc_tm)
{
	struct ac100_rtc_dev *chip = dev_get_drvdata(dev);
	struct regmap *regmap = chip->regmap;
	u16 reg[7];
	int ret;

	ret = regmap_bulk_read(regmap, AC100_RTC_SEC, reg, 7);
	if (ret)
		return ret;

	rtc_tm->tm_sec  = bcd2bin(reg[0] & AC100_RTC_SEC_MASK);
	rtc_tm->tm_min  = bcd2bin(reg[1] & AC100_RTC_MIN_MASK);
	rtc_tm->tm_hour = bcd2bin(reg[2] & AC100_RTC_HOU_MASK);
	rtc_tm->tm_wday = bcd2bin(reg[3] & AC100_RTC_WEE_MASK);
	rtc_tm->tm_mday = bcd2bin(reg[4] & AC100_RTC_DAY_MASK);
	rtc_tm->tm_mon  = bcd2bin(reg[5] & AC100_RTC_MON_MASK) - 1;
	rtc_tm->tm_year = bcd2bin(reg[6] & AC100_RTC_YEA_MASK) +
			  AC100_YEAR_OFF;

	return rtc_valid_tm(rtc_tm);
}

static int ac100_rtc_set_time(struct device *dev, struct rtc_time *rtc_tm)
{
	struct ac100_rtc_dev *chip = dev_get_drvdata(dev);
	struct regmap *regmap = chip->regmap;
	int year;
	u16 reg[8];

	/* our RTC has a limited year range... */
	year = rtc_tm->tm_year - AC100_YEAR_OFF;
	if (year < 0 || year > (AC100_YEAR_MAX - 1900)) {
		dev_err(dev, "rtc only supports year in range %d - %d\n",
			AC100_YEAR_MIN, AC100_YEAR_MAX);
		return -EINVAL;
	}

	/* convert to BCD */
	reg[0] = bin2bcd(rtc_tm->tm_sec)     & AC100_RTC_SEC_MASK;
	reg[1] = bin2bcd(rtc_tm->tm_min)     & AC100_RTC_MIN_MASK;
	reg[2] = bin2bcd(rtc_tm->tm_hour)    & AC100_RTC_HOU_MASK;
	reg[3] = bin2bcd(rtc_tm->tm_wday)    & AC100_RTC_WEE_MASK;
	reg[4] = bin2bcd(rtc_tm->tm_mday)    & AC100_RTC_DAY_MASK;
	reg[5] = bin2bcd(rtc_tm->tm_mon + 1) & AC100_RTC_MON_MASK;
	reg[6] = bin2bcd(year)		     & AC100_RTC_YEA_MASK;
	/* trigger write */
	reg[7] = AC100_RTC_UPD_TRIGGER;

	/* Is it a leap year? */
	if (is_leap_year(year + AC100_YEAR_OFF + 1900))
		reg[6] |= AC100_RTC_YEA_LEAP;

	return regmap_bulk_write(regmap, AC100_RTC_SEC, reg, 8);
}

static int ac100_rtc_alarm_irq_enable(struct device *dev, unsigned int en)
{
	struct ac100_rtc_dev *chip = dev_get_drvdata(dev);
	struct regmap *regmap = chip->regmap;
	unsigned int val;

	val = en ? AC100_ALM_INT_ENABLE : 0;

	return regmap_write(regmap, AC100_ALM_INT_ENA, val);
}

static int ac100_rtc_get_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct ac100_rtc_dev *chip = dev_get_drvdata(dev);
	struct regmap *regmap = chip->regmap;
	struct rtc_time *alrm_tm = &alrm->time;
	u16 reg[7];
	unsigned int val;
	int ret;

	ret = regmap_read(regmap, AC100_ALM_INT_ENA, &val);
	if (ret)
		return ret;

	alrm->enabled = !!(val & AC100_ALM_INT_ENABLE);

	ret = regmap_bulk_read(regmap, AC100_ALM_SEC, reg, 7);
	if (ret)
		return ret;

	alrm_tm->tm_sec  = bcd2bin(reg[0] & AC100_ALM_SEC_MASK);
	alrm_tm->tm_min  = bcd2bin(reg[1] & AC100_ALM_MIN_MASK);
	alrm_tm->tm_hour = bcd2bin(reg[2] & AC100_ALM_HOU_MASK);
	alrm_tm->tm_wday = bcd2bin(reg[3] & AC100_ALM_WEE_MASK);
	alrm_tm->tm_mday = bcd2bin(reg[4] & AC100_ALM_DAY_MASK);
	alrm_tm->tm_mon  = bcd2bin(reg[5] & AC100_ALM_MON_MASK) - 1;
	alrm_tm->tm_year = bcd2bin(reg[6] & AC100_ALM_YEA_MASK) +
			   AC100_YEAR_OFF;

	return 0;
}

static int ac100_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct ac100_rtc_dev *chip = dev_get_drvdata(dev);
	struct regmap *regmap = chip->regmap;
	struct rtc_time *alrm_tm = &alrm->time;
	u16 reg[8];
	int year;
	int ret;

	/* our alarm has a limited year range... */
	year = alrm_tm->tm_year - AC100_YEAR_OFF;
	if (year < 0 || year > (AC100_YEAR_MAX - 1900)) {
		dev_err(dev, "alarm only supports year in range %d - %d\n",
			AC100_YEAR_MIN, AC100_YEAR_MAX);
		return -EINVAL;
	}

	/* convert to BCD */
	reg[0] = (bin2bcd(alrm_tm->tm_sec)  & AC100_ALM_SEC_MASK) |
			AC100_ALM_ENABLE_FLAG;
	reg[1] = (bin2bcd(alrm_tm->tm_min)  & AC100_ALM_MIN_MASK) |
			AC100_ALM_ENABLE_FLAG;
	reg[2] = (bin2bcd(alrm_tm->tm_hour) & AC100_ALM_HOU_MASK) |
			AC100_ALM_ENABLE_FLAG;
	/* Do not enable weekday alarm */
	reg[3] = bin2bcd(alrm_tm->tm_wday) & AC100_ALM_WEE_MASK;
	reg[4] = (bin2bcd(alrm_tm->tm_mday) & AC100_ALM_DAY_MASK) |
			AC100_ALM_ENABLE_FLAG;
	reg[5] = (bin2bcd(alrm_tm->tm_mon + 1)  & AC100_ALM_MON_MASK) |
			AC100_ALM_ENABLE_FLAG;
	reg[6] = (bin2bcd(year) & AC100_ALM_YEA_MASK) |
			AC100_ALM_ENABLE_FLAG;
	/* trigger write */
	reg[7] = AC100_ALM_UPD_TRIGGER;

	ret = regmap_bulk_write(regmap, AC100_ALM_SEC, reg, 8);
	if (ret)
		return ret;

	return ac100_rtc_alarm_irq_enable(dev, alrm->enabled);
}

static irqreturn_t ac100_rtc_irq(int irq, void *data)
{
	struct ac100_rtc_dev *chip = data;
	struct regmap *regmap = chip->regmap;
	unsigned int val = 0;
	int ret;

	mutex_lock(&chip->rtc->ops_lock);

	/* read status */
	ret = regmap_read(regmap, AC100_ALM_INT_STA, &val);
	if (ret)
		goto out;

	if (val & AC100_ALM_INT_ENABLE) {
		/* signal rtc framework */
		rtc_update_irq(chip->rtc, 1, RTC_AF | RTC_IRQF);

		/* clear status */
		ret = regmap_write(regmap, AC100_ALM_INT_STA, val);
		if (ret)
			goto out;

		/* disable interrupt */
		ret = ac100_rtc_alarm_irq_enable(chip->dev, 0);
		if (ret)
			goto out;
	}

out:
	mutex_unlock(&chip->rtc->ops_lock);
	return IRQ_HANDLED;
}

static const struct rtc_class_ops ac100_rtc_ops = {
	.read_time	  = ac100_rtc_get_time,
	.set_time	  = ac100_rtc_set_time,
	.read_alarm	  = ac100_rtc_get_alarm,
	.set_alarm	  = ac100_rtc_set_alarm,
	.alarm_irq_enable = ac100_rtc_alarm_irq_enable,
};

static int ac100_rtc_probe(struct platform_device *pdev)
{
	struct ac100_dev *ac100 = dev_get_drvdata(pdev->dev.parent);
	struct ac100_rtc_dev *chip;
	int ret;

	chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
	platform_set_drvdata(pdev, chip);
	chip->dev = &pdev->dev;
	chip->regmap = ac100->regmap;

	chip->irq = platform_get_irq(pdev, 0);
	if (chip->irq < 0) {
		dev_err(&pdev->dev, "No IRQ resource\n");
		return chip->irq;
	}

	ret = devm_request_threaded_irq(&pdev->dev, chip->irq, NULL,
					ac100_rtc_irq,
					IRQF_SHARED | IRQF_ONESHOT,
					dev_name(&pdev->dev), chip);
	if (ret) {
		dev_err(&pdev->dev, "Could not request IRQ\n");
		return ret;
	}

	/* always use 24 hour mode */
	regmap_write_bits(chip->regmap, AC100_RTC_CTRL, AC100_RTC_CTRL_24HOUR,
			  AC100_RTC_CTRL_24HOUR);

	/* disable counter alarm interrupt */
	regmap_write(chip->regmap, AC100_ALM_INT_ENA, 0);

	/* clear counter alarm pending interrupts */
	regmap_write(chip->regmap, AC100_ALM_INT_STA, AC100_ALM_INT_ENABLE);

	chip->rtc = devm_rtc_device_register(&pdev->dev, "rtc-ac100",
					     &ac100_rtc_ops, THIS_MODULE);
	if (IS_ERR(chip->rtc)) {
		dev_err(&pdev->dev, "unable to register device\n");
		return PTR_ERR(chip->rtc);
	}

	ret = ac100_rtc_register_clks(chip);
	if (ret)
		return ret;

	dev_info(&pdev->dev, "RTC enabled\n");

	return 0;
}

static int ac100_rtc_remove(struct platform_device *pdev)
{
	struct ac100_rtc_dev *chip = platform_get_drvdata(pdev);

	ac100_rtc_unregister_clks(chip);

	return 0;
}

static const struct of_device_id ac100_rtc_match[] = {
	{ .compatible = "x-powers,ac100-rtc" },
	{ },
};
MODULE_DEVICE_TABLE(of, ac100_rtc_match);

static struct platform_driver ac100_rtc_driver = {
	.probe		= ac100_rtc_probe,
	.remove		= ac100_rtc_remove,
	.driver		= {
		.name		= "ac100-rtc",
		.of_match_table	= of_match_ptr(ac100_rtc_match),
	},
};
module_platform_driver(ac100_rtc_driver);

MODULE_DESCRIPTION("X-Powers AC100 RTC driver");
MODULE_AUTHOR("Chen-Yu Tsai <wens@csie.org>");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
d00a18a4 CYT	1	/*
	2	* RTC Driver for X-Powers AC100
	3	*
	4	* Copyright (c) 2016 Chen-Yu Tsai
	5	*
	6	* Chen-Yu Tsai <wens@csie.org>
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*
	12	* This program is distributed in the hope that it will be useful, but WITHOUT
	13	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	14	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	15	* more details.
	16	*/
	17
	18	#include <linux/bcd.h>
04940631	19	#include <linux/clk-provider.h>
d00a18a4 CYT	20	#include <linux/device.h>
	21	#include <linux/interrupt.h>
	22	#include <linux/kernel.h>
	23	#include <linux/mfd/ac100.h>
	24	#include <linux/module.h>
	25	#include <linux/mutex.h>
	26	#include <linux/of.h>
	27	#include <linux/platform_device.h>
	28	#include <linux/regmap.h>
	29	#include <linux/rtc.h>
	30	#include <linux/types.h>
	31
	32	/* Control register */
	33	#define AC100_RTC_CTRL_24HOUR BIT(0)
	34
04940631 CYT	35	/* Clock output register bits */
	36	#define AC100_CLKOUT_PRE_DIV_SHIFT 5
	37	#define AC100_CLKOUT_PRE_DIV_WIDTH 3
	38	#define AC100_CLKOUT_MUX_SHIFT 4
	39	#define AC100_CLKOUT_MUX_WIDTH 1
	40	#define AC100_CLKOUT_DIV_SHIFT 1
	41	#define AC100_CLKOUT_DIV_WIDTH 3
	42	#define AC100_CLKOUT_EN BIT(0)
	43
d00a18a4 CYT	44	/* RTC */
	45	#define AC100_RTC_SEC_MASK GENMASK(6, 0)
	46	#define AC100_RTC_MIN_MASK GENMASK(6, 0)
	47	#define AC100_RTC_HOU_MASK GENMASK(5, 0)
	48	#define AC100_RTC_WEE_MASK GENMASK(2, 0)
	49	#define AC100_RTC_DAY_MASK GENMASK(5, 0)
	50	#define AC100_RTC_MON_MASK GENMASK(4, 0)
	51	#define AC100_RTC_YEA_MASK GENMASK(7, 0)
	52	#define AC100_RTC_YEA_LEAP BIT(15)
	53	#define AC100_RTC_UPD_TRIGGER BIT(15)
	54
	55	/* Alarm (wall clock) */
	56	#define AC100_ALM_INT_ENABLE BIT(0)
	57
	58	#define AC100_ALM_SEC_MASK GENMASK(6, 0)
	59	#define AC100_ALM_MIN_MASK GENMASK(6, 0)
	60	#define AC100_ALM_HOU_MASK GENMASK(5, 0)
	61	#define AC100_ALM_WEE_MASK GENMASK(2, 0)
	62	#define AC100_ALM_DAY_MASK GENMASK(5, 0)
	63	#define AC100_ALM_MON_MASK GENMASK(4, 0)
	64	#define AC100_ALM_YEA_MASK GENMASK(7, 0)
	65	#define AC100_ALM_ENABLE_FLAG BIT(15)
	66	#define AC100_ALM_UPD_TRIGGER BIT(15)
	67
	68	/*
	69	* The year parameter passed to the driver is usually an offset relative to
	70	* the year 1900. This macro is used to convert this offset to another one
	71	* relative to the minimum year allowed by the hardware.
	72	*
	73	* The year range is 1970 - 2069. This range is selected to match Allwinner's
	74	* driver.
	75	*/
	76	#define AC100_YEAR_MIN 1970
	77	#define AC100_YEAR_MAX 2069
	78	#define AC100_YEAR_OFF (AC100_YEAR_MIN - 1900)
	79
04940631 CYT	80	struct ac100_clkout {
	81	struct clk_hw hw;
	82	struct regmap *regmap;
	83	u8 offset;
	84	};
	85
	86	#define to_ac100_clkout(_hw) container_of(_hw, struct ac100_clkout, hw)
	87
	88	#define AC100_RTC_32K_NAME "ac100-rtc-32k"
	89	#define AC100_RTC_32K_RATE 32768
	90	#define AC100_CLKOUT_NUM 3
	91
	92	static const char * const ac100_clkout_names[AC100_CLKOUT_NUM] = {
	93	"ac100-cko1-rtc",
	94	"ac100-cko2-rtc",
	95	"ac100-cko3-rtc",
	96	};
	97
d00a18a4 CYT	98	struct ac100_rtc_dev {
	99	struct rtc_device *rtc;
	100	struct device *dev;
	101	struct regmap *regmap;
	102	int irq;
	103	unsigned long alarm;
04940631 CYT	104
	105	struct clk_hw *rtc_32k_clk;
	106	struct ac100_clkout clks[AC100_CLKOUT_NUM];
	107	struct clk_hw_onecell_data *clk_data;
d00a18a4 CYT	108	};
d00a18a4 CYT	109
04940631 CYT	110	/**
	111	* Clock controls for 3 clock output pins
	112	*/
	113
	114	static const struct clk_div_table ac100_clkout_prediv[] = {
	115	{ .val = 0, .div = 1 },
	116	{ .val = 1, .div = 2 },
	117	{ .val = 2, .div = 4 },
	118	{ .val = 3, .div = 8 },
	119	{ .val = 4, .div = 16 },
	120	{ .val = 5, .div = 32 },
	121	{ .val = 6, .div = 64 },
	122	{ .val = 7, .div = 122 },
	123	{ },
	124	};
	125
	126	/* Abuse the fact that one parent is 32768 Hz, and the other is 4 MHz */
	127	static unsigned long ac100_clkout_recalc_rate(struct clk_hw *hw,
	128	unsigned long prate)
	129	{
	130	struct ac100_clkout *clk = to_ac100_clkout(hw);
	131	unsigned int reg, div;
	132
	133	regmap_read(clk->regmap, clk->offset, &reg);
	134
	135	/* Handle pre-divider first */
	136	if (prate != AC100_RTC_32K_RATE) {
	137	div = (reg >> AC100_CLKOUT_PRE_DIV_SHIFT) &
	138	((1 << AC100_CLKOUT_PRE_DIV_WIDTH) - 1);
	139	prate = divider_recalc_rate(hw, prate, div,
	140	ac100_clkout_prediv, 0);
	141	}
	142
	143	div = (reg >> AC100_CLKOUT_DIV_SHIFT) &
	144	(BIT(AC100_CLKOUT_DIV_WIDTH) - 1);
	145	return divider_recalc_rate(hw, prate, div, NULL,
	146	CLK_DIVIDER_POWER_OF_TWO);
	147	}
	148
	149	static long ac100_clkout_round_rate(struct clk_hw *hw, unsigned long rate,
	150	unsigned long prate)
	151	{
	152	unsigned long best_rate = 0, tmp_rate, tmp_prate;
	153	int i;
	154
	155	if (prate == AC100_RTC_32K_RATE)
	156	return divider_round_rate(hw, rate, &prate, NULL,
	157	AC100_CLKOUT_DIV_WIDTH,
	158	CLK_DIVIDER_POWER_OF_TWO);
	159
	160	for (i = 0; ac100_clkout_prediv[i].div; i++) {
	161	tmp_prate = DIV_ROUND_UP(prate, ac100_clkout_prediv[i].val);
	162	tmp_rate = divider_round_rate(hw, rate, &tmp_prate, NULL,
	163	AC100_CLKOUT_DIV_WIDTH,
	164	CLK_DIVIDER_POWER_OF_TWO);
	165
	166	if (tmp_rate > rate)
	167	continue;
	168	if (rate - tmp_rate < best_rate - tmp_rate)
	169	best_rate = tmp_rate;
	170	}
	171
	172	return best_rate;
	173	}
174
175	static int ac100_clkout_determine_rate(struct clk_hw *hw,
176	struct clk_rate_request *req)
177	{
178	struct clk_hw *best_parent;
179	unsigned long best = 0;
180	int i, num_parents = clk_hw_get_num_parents(hw);
181
182	for (i = 0; i < num_parents; i++) {
183	struct clk_hw *parent = clk_hw_get_parent_by_index(hw, i);
184	unsigned long tmp, prate = clk_hw_get_rate(parent);
185
186	tmp = ac100_clkout_round_rate(hw, req->rate, prate);
187
188	if (tmp > req->rate)
189	continue;
190	if (req->rate - tmp < req->rate - best) {
191	best = tmp;
192	best_parent = parent;
193	}
194	}
195
196	if (!best)
197	return -EINVAL;
198
199	req->best_parent_hw = best_parent;
200	req->best_parent_rate = best;
201	req->rate = best;
202
203	return 0;
204	}
205
206	static int ac100_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
207	unsigned long prate)
208	{
209	struct ac100_clkout *clk = to_ac100_clkout(hw);
210	int div = 0, pre_div = 0;
211
212	do {
213	div = divider_get_val(rate * ac100_clkout_prediv[pre_div].div,
214	prate, NULL, AC100_CLKOUT_DIV_WIDTH,
215	CLK_DIVIDER_POWER_OF_TWO);
216	if (div >= 0)
217	break;
218	} while (prate != AC100_RTC_32K_RATE &&
219	ac100_clkout_prediv[++pre_div].div);
220
221	if (div < 0)
222	return div;
223
224	pre_div = ac100_clkout_prediv[pre_div].val;
225
226	regmap_update_bits(clk->regmap, clk->offset,
227	((1 << AC100_CLKOUT_DIV_WIDTH) - 1) << AC100_CLKOUT_DIV_SHIFT \|
228	((1 << AC100_CLKOUT_PRE_DIV_WIDTH) - 1) << AC100_CLKOUT_PRE_DIV_SHIFT,
229	(div - 1) << AC100_CLKOUT_DIV_SHIFT \|
230	(pre_div - 1) << AC100_CLKOUT_PRE_DIV_SHIFT);
231
232	return 0;
233	}
234
235	static int ac100_clkout_prepare(struct clk_hw *hw)
236	{
237	struct ac100_clkout *clk = to_ac100_clkout(hw);
238
239	return regmap_update_bits(clk->regmap, clk->offset, AC100_CLKOUT_EN,
240	AC100_CLKOUT_EN);
241	}
242
243	static void ac100_clkout_unprepare(struct clk_hw *hw)
244	{
245	struct ac100_clkout *clk = to_ac100_clkout(hw);
246
247	regmap_update_bits(clk->regmap, clk->offset, AC100_CLKOUT_EN, 0);
248	}
249
250	static int ac100_clkout_is_prepared(struct clk_hw *hw)
251	{
252	struct ac100_clkout *clk = to_ac100_clkout(hw);
253	unsigned int reg;
254
255	regmap_read(clk->regmap, clk->offset, &reg);
256
257	return reg & AC100_CLKOUT_EN;
258	}
259
260	static u8 ac100_clkout_get_parent(struct clk_hw *hw)
261	{
262	struct ac100_clkout *clk = to_ac100_clkout(hw);
263	unsigned int reg;
264
265	regmap_read(clk->regmap, clk->offset, &reg);
266
267	return (reg >> AC100_CLKOUT_MUX_SHIFT) & 0x1;
268	}
269
270	static int ac100_clkout_set_parent(struct clk_hw *hw, u8 index)
271	{
272	struct ac100_clkout *clk = to_ac100_clkout(hw);
273
274	return regmap_update_bits(clk->regmap, clk->offset,
275	BIT(AC100_CLKOUT_MUX_SHIFT),
276	index ? BIT(AC100_CLKOUT_MUX_SHIFT) : 0);
277	}
278
279	static const struct clk_ops ac100_clkout_ops = {
280	.prepare = ac100_clkout_prepare,
281	.unprepare = ac100_clkout_unprepare,
282	.is_prepared = ac100_clkout_is_prepared,
283	.recalc_rate = ac100_clkout_recalc_rate,
284	.determine_rate = ac100_clkout_determine_rate,
285	.get_parent = ac100_clkout_get_parent,
286	.set_parent = ac100_clkout_set_parent,
287	.set_rate = ac100_clkout_set_rate,
288	};
289
290	static int ac100_rtc_register_clks(struct ac100_rtc_dev *chip)
291	{
292	struct device_node *np = chip->dev->of_node;
293	const char *parents[2] = {AC100_RTC_32K_NAME};
294	int i, ret;
295
296	chip->clk_data = devm_kzalloc(chip->dev, sizeof(*chip->clk_data) +
297	sizeof(chip->clk_data->hws)
298	AC100_CLKOUT_NUM,
299	GFP_KERNEL);
300	if (!chip->clk_data)
301	return -ENOMEM;
302
303	chip->rtc_32k_clk = clk_hw_register_fixed_rate(chip->dev,
304	AC100_RTC_32K_NAME,
305	NULL, 0,
306	AC100_RTC_32K_RATE);
307	if (IS_ERR(chip->rtc_32k_clk)) {
308	ret = PTR_ERR(chip->rtc_32k_clk);
309	dev_err(chip->dev, "Failed to register RTC-32k clock: %d\n",
310	ret);
311	return ret;
312	}
313
314	parents[1] = of_clk_get_parent_name(np, 0);
315	if (!parents[1]) {
316	dev_err(chip->dev, "Failed to get ADDA 4M clock\n");
317	return -EINVAL;
318	}
319
320	for (i = 0; i < AC100_CLKOUT_NUM; i++) {
321	struct ac100_clkout *clk = &chip->clks[i];
322	struct clk_init_data init = {
323	.name = ac100_clkout_names[i],
324	.ops = &ac100_clkout_ops,
325	.parent_names = parents,
326	.num_parents = ARRAY_SIZE(parents),
327	.flags = 0,
328	};
329
637cac7c CYT	330	of_property_read_string_index(np, "clock-output-names",
637cac7c CYT	331	i, &init.name);
04940631 CYT	332	clk->regmap = chip->regmap;
	333	clk->offset = AC100_CLKOUT_CTRL1 + i;
	334	clk->hw.init = &init;
	335
	336	ret = devm_clk_hw_register(chip->dev, &clk->hw);
	337	if (ret) {
	338	dev_err(chip->dev, "Failed to register clk '%s': %d\n",
	339	init.name, ret);
	340	goto err_unregister_rtc_32k;
	341	}
	342
	343	chip->clk_data->hws[i] = &clk->hw;
	344	}
	345
	346	chip->clk_data->num = i;
	347	ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, chip->clk_data);
	348	if (ret)
	349	goto err_unregister_rtc_32k;
	350
	351	return 0;
	352
	353	err_unregister_rtc_32k:
	354	clk_unregister_fixed_rate(chip->rtc_32k_clk->clk);
	355
	356	return ret;
	357	}
	358
	359	static void ac100_rtc_unregister_clks(struct ac100_rtc_dev *chip)
	360	{
	361	of_clk_del_provider(chip->dev->of_node);
	362	clk_unregister_fixed_rate(chip->rtc_32k_clk->clk);
	363	}
	364
	365	/**
	366	* RTC related bits
	367	*/
d00a18a4 CYT	368	static int ac100_rtc_get_time(struct device dev, struct rtc_time rtc_tm)
	369	{
	370	struct ac100_rtc_dev *chip = dev_get_drvdata(dev);
	371	struct regmap *regmap = chip->regmap;
	372	u16 reg[7];
	373	int ret;
	374
	375	ret = regmap_bulk_read(regmap, AC100_RTC_SEC, reg, 7);
	376	if (ret)
	377	return ret;
	378
	379	rtc_tm->tm_sec = bcd2bin(reg[0] & AC100_RTC_SEC_MASK);
	380	rtc_tm->tm_min = bcd2bin(reg[1] & AC100_RTC_MIN_MASK);
	381	rtc_tm->tm_hour = bcd2bin(reg[2] & AC100_RTC_HOU_MASK);
	382	rtc_tm->tm_wday = bcd2bin(reg[3] & AC100_RTC_WEE_MASK);
	383	rtc_tm->tm_mday = bcd2bin(reg[4] & AC100_RTC_DAY_MASK);
	384	rtc_tm->tm_mon = bcd2bin(reg[5] & AC100_RTC_MON_MASK) - 1;
	385	rtc_tm->tm_year = bcd2bin(reg[6] & AC100_RTC_YEA_MASK) +
	386	AC100_YEAR_OFF;
	387
	388	return rtc_valid_tm(rtc_tm);
	389	}
	390
	391	static int ac100_rtc_set_time(struct device dev, struct rtc_time rtc_tm)
	392	{
	393	struct ac100_rtc_dev *chip = dev_get_drvdata(dev);
	394	struct regmap *regmap = chip->regmap;
	395	int year;
	396	u16 reg[8];
	397
	398	/* our RTC has a limited year range... */
	399	year = rtc_tm->tm_year - AC100_YEAR_OFF;
	400	if (year < 0 \|\| year > (AC100_YEAR_MAX - 1900)) {
	401	dev_err(dev, "rtc only supports year in range %d - %d\n",
	402	AC100_YEAR_MIN, AC100_YEAR_MAX);
	403	return -EINVAL;
	404	}
	405
	406	/* convert to BCD */
	407	reg[0] = bin2bcd(rtc_tm->tm_sec) & AC100_RTC_SEC_MASK;
	408	reg[1] = bin2bcd(rtc_tm->tm_min) & AC100_RTC_MIN_MASK;
	409	reg[2] = bin2bcd(rtc_tm->tm_hour) & AC100_RTC_HOU_MASK;
	410	reg[3] = bin2bcd(rtc_tm->tm_wday) & AC100_RTC_WEE_MASK;
	411	reg[4] = bin2bcd(rtc_tm->tm_mday) & AC100_RTC_DAY_MASK;
	412	reg[5] = bin2bcd(rtc_tm->tm_mon + 1) & AC100_RTC_MON_MASK;
	413	reg[6] = bin2bcd(year) & AC100_RTC_YEA_MASK;
	414	/* trigger write */
	415	reg[7] = AC100_RTC_UPD_TRIGGER;
	416
	417	/* Is it a leap year? */
	418	if (is_leap_year(year + AC100_YEAR_OFF + 1900))
	419	reg[6] \|= AC100_RTC_YEA_LEAP;
	420
	421	return regmap_bulk_write(regmap, AC100_RTC_SEC, reg, 8);
	422	}
	423
	424	static int ac100_rtc_alarm_irq_enable(struct device *dev, unsigned int en)
	425	{
	426	struct ac100_rtc_dev *chip = dev_get_drvdata(dev);
	427	struct regmap *regmap = chip->regmap;
	428	unsigned int val;
	429
	430	val = en ? AC100_ALM_INT_ENABLE : 0;
	431
432	return regmap_write(regmap, AC100_ALM_INT_ENA, val);
433	}
434
435	static int ac100_rtc_get_alarm(struct device dev, struct rtc_wkalrm alrm)
436	{
437	struct ac100_rtc_dev *chip = dev_get_drvdata(dev);
438	struct regmap *regmap = chip->regmap;
439	struct rtc_time *alrm_tm = &alrm->time;
440	u16 reg[7];
441	unsigned int val;
442	int ret;
443
444	ret = regmap_read(regmap, AC100_ALM_INT_ENA, &val);
445	if (ret)
446	return ret;
447
448	alrm->enabled = !!(val & AC100_ALM_INT_ENABLE);
449
450	ret = regmap_bulk_read(regmap, AC100_ALM_SEC, reg, 7);
451	if (ret)
452	return ret;
453
454	alrm_tm->tm_sec = bcd2bin(reg[0] & AC100_ALM_SEC_MASK);
455	alrm_tm->tm_min = bcd2bin(reg[1] & AC100_ALM_MIN_MASK);
456	alrm_tm->tm_hour = bcd2bin(reg[2] & AC100_ALM_HOU_MASK);
457	alrm_tm->tm_wday = bcd2bin(reg[3] & AC100_ALM_WEE_MASK);
458	alrm_tm->tm_mday = bcd2bin(reg[4] & AC100_ALM_DAY_MASK);
459	alrm_tm->tm_mon = bcd2bin(reg[5] & AC100_ALM_MON_MASK) - 1;
460	alrm_tm->tm_year = bcd2bin(reg[6] & AC100_ALM_YEA_MASK) +
461	AC100_YEAR_OFF;
462
463	return 0;
464	}
465
466	static int ac100_rtc_set_alarm(struct device dev, struct rtc_wkalrm alrm)
467	{
468	struct ac100_rtc_dev *chip = dev_get_drvdata(dev);
469	struct regmap *regmap = chip->regmap;
470	struct rtc_time *alrm_tm = &alrm->time;
471	u16 reg[8];
472	int year;
473	int ret;
474
475	/* our alarm has a limited year range... */
476	year = alrm_tm->tm_year - AC100_YEAR_OFF;
477	if (year < 0 \|\| year > (AC100_YEAR_MAX - 1900)) {
478	dev_err(dev, "alarm only supports year in range %d - %d\n",
479	AC100_YEAR_MIN, AC100_YEAR_MAX);
480	return -EINVAL;
481	}
482
483	/* convert to BCD */
484	reg[0] = (bin2bcd(alrm_tm->tm_sec) & AC100_ALM_SEC_MASK) \|
485	AC100_ALM_ENABLE_FLAG;
486	reg[1] = (bin2bcd(alrm_tm->tm_min) & AC100_ALM_MIN_MASK) \|
487	AC100_ALM_ENABLE_FLAG;
488	reg[2] = (bin2bcd(alrm_tm->tm_hour) & AC100_ALM_HOU_MASK) \|
489	AC100_ALM_ENABLE_FLAG;
490	/* Do not enable weekday alarm */
491	reg[3] = bin2bcd(alrm_tm->tm_wday) & AC100_ALM_WEE_MASK;
492	reg[4] = (bin2bcd(alrm_tm->tm_mday) & AC100_ALM_DAY_MASK) \|
493	AC100_ALM_ENABLE_FLAG;
494	reg[5] = (bin2bcd(alrm_tm->tm_mon + 1) & AC100_ALM_MON_MASK) \|
495	AC100_ALM_ENABLE_FLAG;
496	reg[6] = (bin2bcd(year) & AC100_ALM_YEA_MASK) \|
497	AC100_ALM_ENABLE_FLAG;
498	/* trigger write */
499	reg[7] = AC100_ALM_UPD_TRIGGER;
500
501	ret = regmap_bulk_write(regmap, AC100_ALM_SEC, reg, 8);
502	if (ret)
503	return ret;
504
505	return ac100_rtc_alarm_irq_enable(dev, alrm->enabled);
506	}
507
508	static irqreturn_t ac100_rtc_irq(int irq, void *data)
509	{
510	struct ac100_rtc_dev *chip = data;
511	struct regmap *regmap = chip->regmap;
512	unsigned int val = 0;
513	int ret;
514
515	mutex_lock(&chip->rtc->ops_lock);
516
517	/* read status */
518	ret = regmap_read(regmap, AC100_ALM_INT_STA, &val);
519	if (ret)
520	goto out;
521
522	if (val & AC100_ALM_INT_ENABLE) {
523	/* signal rtc framework */
524	rtc_update_irq(chip->rtc, 1, RTC_AF \| RTC_IRQF);
525
526	/* clear status */
527	ret = regmap_write(regmap, AC100_ALM_INT_STA, val);
528	if (ret)
529	goto out;
530
531	/* disable interrupt */
532	ret = ac100_rtc_alarm_irq_enable(chip->dev, 0);
533	if (ret)
534	goto out;
535	}
536
537	out:
538	mutex_unlock(&chip->rtc->ops_lock);
539	return IRQ_HANDLED;
540	}
541
542	static const struct rtc_class_ops ac100_rtc_ops = {
543	.read_time = ac100_rtc_get_time,
544	.set_time = ac100_rtc_set_time,
545	.read_alarm = ac100_rtc_get_alarm,
546	.set_alarm = ac100_rtc_set_alarm,
547	.alarm_irq_enable = ac100_rtc_alarm_irq_enable,
548	};
549
550	static int ac100_rtc_probe(struct platform_device *pdev)
551	{
552	struct ac100_dev *ac100 = dev_get_drvdata(pdev->dev.parent);
553	struct ac100_rtc_dev *chip;
554	int ret;
555
556	chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
557	platform_set_drvdata(pdev, chip);
558	chip->dev = &pdev->dev;
559	chip->regmap = ac100->regmap;
560
561	chip->irq = platform_get_irq(pdev, 0);
562	if (chip->irq < 0) {
563	dev_err(&pdev->dev, "No IRQ resource\n");
564	return chip->irq;
565	}
566
567	ret = devm_request_threaded_irq(&pdev->dev, chip->irq, NULL,
568	ac100_rtc_irq,
569	IRQF_SHARED \| IRQF_ONESHOT,
570	dev_name(&pdev->dev), chip);
571	if (ret) {
572	dev_err(&pdev->dev, "Could not request IRQ\n");
573	return ret;
574	}
575
576	/* always use 24 hour mode */
577	regmap_write_bits(chip->regmap, AC100_RTC_CTRL, AC100_RTC_CTRL_24HOUR,
578	AC100_RTC_CTRL_24HOUR);
579
580	/* disable counter alarm interrupt */
581	regmap_write(chip->regmap, AC100_ALM_INT_ENA, 0);
582
583	/* clear counter alarm pending interrupts */
584	regmap_write(chip->regmap, AC100_ALM_INT_STA, AC100_ALM_INT_ENABLE);
585
586	chip->rtc = devm_rtc_device_register(&pdev->dev, "rtc-ac100",
587	&ac100_rtc_ops, THIS_MODULE);
588	if (IS_ERR(chip->rtc)) {
589	dev_err(&pdev->dev, "unable to register device\n");
590	return PTR_ERR(chip->rtc);
591	}
592
04940631 CYT	593	ret = ac100_rtc_register_clks(chip);
	594	if (ret)
	595	return ret;
	596
d00a18a4 CYT	597	dev_info(&pdev->dev, "RTC enabled\n");
	598
	599	return 0;
	600	}
	601
04940631 CYT	602	static int ac100_rtc_remove(struct platform_device *pdev)
	603	{
	604	struct ac100_rtc_dev *chip = platform_get_drvdata(pdev);
	605
	606	ac100_rtc_unregister_clks(chip);
	607
	608	return 0;
	609	}
	610
d00a18a4 CYT	611	static const struct of_device_id ac100_rtc_match[] = {
	612	{ .compatible = "x-powers,ac100-rtc" },
	613	{ },
	614	};
	615	MODULE_DEVICE_TABLE(of, ac100_rtc_match);
	616
	617	static struct platform_driver ac100_rtc_driver = {
	618	.probe = ac100_rtc_probe,
04940631	619	.remove = ac100_rtc_remove,
d00a18a4 CYT	620	.driver = {
	621	.name = "ac100-rtc",
	622	.of_match_table = of_match_ptr(ac100_rtc_match),
	623	},
	624	};
	625	module_platform_driver(ac100_rtc_driver);
	626
	627	MODULE_DESCRIPTION("X-Powers AC100 RTC driver");
	628	MODULE_AUTHOR("Chen-Yu Tsai <wens@csie.org>");
	629	MODULE_LICENSE("GPL v2");