[deliverable/linux.git] / drivers / rtc / rtc-at91sam9.c

/*
 * "RTT as Real Time Clock" driver for AT91SAM9 SoC family
 *
 * (C) 2007 Michel Benoit
 *
 * Based on rtc-at91rm9200.c by Rick Bronson
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/time.h>
#include <linux/rtc.h>
#include <linux/interrupt.h>
#include <linux/ioctl.h>
#include <linux/slab.h>
#include <linux/platform_data/atmel.h>
#include <linux/io.h>

/*
 * This driver uses two configurable hardware resources that live in the
 * AT91SAM9 backup power domain (intended to be powered at all times)
 * to implement the Real Time Clock interfaces
 *
 *  - A "Real-time Timer" (RTT) counts up in seconds from a base time.
 *    We can't assign the counter value (CRTV) ... but we can reset it.
 *
 *  - One of the "General Purpose Backup Registers" (GPBRs) holds the
 *    base time, normally an offset from the beginning of the POSIX
 *    epoch (1970-Jan-1 00:00:00 UTC).  Some systems also include the
 *    local timezone's offset.
 *
 * The RTC's value is the RTT counter plus that offset.  The RTC's alarm
 * is likewise a base (ALMV) plus that offset.
 *
 * Not all RTTs will be used as RTCs; some systems have multiple RTTs to
 * choose from, or a "real" RTC module.  All systems have multiple GPBR
 * registers available, likewise usable for more than "RTC" support.
 */

#define AT91_RTT_MR		0x00			/* Real-time Mode Register */
#define AT91_RTT_RTPRES		(0xffff << 0)		/* Real-time Timer Prescaler Value */
#define AT91_RTT_ALMIEN		(1 << 16)		/* Alarm Interrupt Enable */
#define AT91_RTT_RTTINCIEN	(1 << 17)		/* Real Time Timer Increment Interrupt Enable */
#define AT91_RTT_RTTRST		(1 << 18)		/* Real Time Timer Restart */

#define AT91_RTT_AR		0x04			/* Real-time Alarm Register */
#define AT91_RTT_ALMV		(0xffffffff)		/* Alarm Value */

#define AT91_RTT_VR		0x08			/* Real-time Value Register */
#define AT91_RTT_CRTV		(0xffffffff)		/* Current Real-time Value */

#define AT91_RTT_SR		0x0c			/* Real-time Status Register */
#define AT91_RTT_ALMS		(1 << 0)		/* Real-time Alarm Status */
#define AT91_RTT_RTTINC		(1 << 1)		/* Real-time Timer Increment */

#define AT91_SLOW_CLOCK		32768

/*
 * We store ALARM_DISABLED in ALMV to record that no alarm is set.
 * It's also the reset value for that field.
 */
#define ALARM_DISABLED	((u32)~0)


struct sam9_rtc {
	void __iomem		*rtt;
	struct rtc_device	*rtcdev;
	u32			imr;
	void __iomem		*gpbr;
	int 			irq;
};

#define rtt_readl(rtc, field) \
	__raw_readl((rtc)->rtt + AT91_RTT_ ## field)
#define rtt_writel(rtc, field, val) \
	__raw_writel((val), (rtc)->rtt + AT91_RTT_ ## field)

#define gpbr_readl(rtc) \
	__raw_readl((rtc)->gpbr)
#define gpbr_writel(rtc, val) \
	__raw_writel((val), (rtc)->gpbr)

/*
 * Read current time and date in RTC
 */
static int at91_rtc_readtime(struct device *dev, struct rtc_time *tm)
{
	struct sam9_rtc *rtc = dev_get_drvdata(dev);
	u32 secs, secs2;
	u32 offset;

	/* read current time offset */
	offset = gpbr_readl(rtc);
	if (offset == 0)
		return -EILSEQ;

	/* reread the counter to help sync the two clock domains */
	secs = rtt_readl(rtc, VR);
	secs2 = rtt_readl(rtc, VR);
	if (secs != secs2)
		secs = rtt_readl(rtc, VR);

	rtc_time_to_tm(offset + secs, tm);

	dev_dbg(dev, "%s: %4d-%02d-%02d %02d:%02d:%02d\n", "readtime",
		1900 + tm->tm_year, tm->tm_mon, tm->tm_mday,
		tm->tm_hour, tm->tm_min, tm->tm_sec);

	return 0;
}

/*
 * Set current time and date in RTC
 */
static int at91_rtc_settime(struct device *dev, struct rtc_time *tm)
{
	struct sam9_rtc *rtc = dev_get_drvdata(dev);
	int err;
	u32 offset, alarm, mr;
	unsigned long secs;

	dev_dbg(dev, "%s: %4d-%02d-%02d %02d:%02d:%02d\n", "settime",
		1900 + tm->tm_year, tm->tm_mon, tm->tm_mday,
		tm->tm_hour, tm->tm_min, tm->tm_sec);

	err = rtc_tm_to_time(tm, &secs);
	if (err != 0)
		return err;

	mr = rtt_readl(rtc, MR);

	/* disable interrupts */
	rtt_writel(rtc, MR, mr & ~(AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN));

	/* read current time offset */
	offset = gpbr_readl(rtc);

	/* store the new base time in a battery backup register */
	secs += 1;
	gpbr_writel(rtc, secs);

	/* adjust the alarm time for the new base */
	alarm = rtt_readl(rtc, AR);
	if (alarm != ALARM_DISABLED) {
		if (offset > secs) {
			/* time jumped backwards, increase time until alarm */
			alarm += (offset - secs);
		} else if ((alarm + offset) > secs) {
			/* time jumped forwards, decrease time until alarm */
			alarm -= (secs - offset);
		} else {
			/* time jumped past the alarm, disable alarm */
			alarm = ALARM_DISABLED;
			mr &= ~AT91_RTT_ALMIEN;
		}
		rtt_writel(rtc, AR, alarm);
	}

	/* reset the timer, and re-enable interrupts */
	rtt_writel(rtc, MR, mr | AT91_RTT_RTTRST);

	return 0;
}

static int at91_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct sam9_rtc *rtc = dev_get_drvdata(dev);
	struct rtc_time *tm = &alrm->time;
	u32 alarm = rtt_readl(rtc, AR);
	u32 offset;

	offset = gpbr_readl(rtc);
	if (offset == 0)
		return -EILSEQ;

	memset(alrm, 0, sizeof(*alrm));
	if (alarm != ALARM_DISABLED && offset != 0) {
		rtc_time_to_tm(offset + alarm, tm);

		dev_dbg(dev, "%s: %4d-%02d-%02d %02d:%02d:%02d\n", "readalarm",
			1900 + tm->tm_year, tm->tm_mon, tm->tm_mday,
			tm->tm_hour, tm->tm_min, tm->tm_sec);

		if (rtt_readl(rtc, MR) & AT91_RTT_ALMIEN)
			alrm->enabled = 1;
	}

	return 0;
}

static int at91_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct sam9_rtc *rtc = dev_get_drvdata(dev);
	struct rtc_time *tm = &alrm->time;
	unsigned long secs;
	u32 offset;
	u32 mr;
	int err;

	err = rtc_tm_to_time(tm, &secs);
	if (err != 0)
		return err;

	offset = gpbr_readl(rtc);
	if (offset == 0) {
		/* time is not set */
		return -EILSEQ;
	}
	mr = rtt_readl(rtc, MR);
	rtt_writel(rtc, MR, mr & ~AT91_RTT_ALMIEN);

	/* alarm in the past? finish and leave disabled */
	if (secs <= offset) {
		rtt_writel(rtc, AR, ALARM_DISABLED);
		return 0;
	}

	/* else set alarm and maybe enable it */
	rtt_writel(rtc, AR, secs - offset);
	if (alrm->enabled)
		rtt_writel(rtc, MR, mr | AT91_RTT_ALMIEN);

	dev_dbg(dev, "%s: %4d-%02d-%02d %02d:%02d:%02d\n", "setalarm",
		tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_hour,
		tm->tm_min, tm->tm_sec);

	return 0;
}

static int at91_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
	struct sam9_rtc *rtc = dev_get_drvdata(dev);
	u32 mr = rtt_readl(rtc, MR);

	dev_dbg(dev, "alarm_irq_enable: enabled=%08x, mr %08x\n", enabled, mr);
	if (enabled)
		rtt_writel(rtc, MR, mr | AT91_RTT_ALMIEN);
	else
		rtt_writel(rtc, MR, mr & ~AT91_RTT_ALMIEN);
	return 0;
}

/*
 * Provide additional RTC information in /proc/driver/rtc
 */
static int at91_rtc_proc(struct device *dev, struct seq_file *seq)
{
	struct sam9_rtc *rtc = dev_get_drvdata(dev);
	u32 mr = mr = rtt_readl(rtc, MR);

	seq_printf(seq, "update_IRQ\t: %s\n",
			(mr & AT91_RTT_RTTINCIEN) ? "yes" : "no");
	return 0;
}

/*
 * IRQ handler for the RTC
 */
static irqreturn_t at91_rtc_interrupt(int irq, void *_rtc)
{
	struct sam9_rtc *rtc = _rtc;
	u32 sr, mr;
	unsigned long events = 0;

	/* Shared interrupt may be for another device.  Note: reading
	 * SR clears it, so we must only read it in this irq handler!
	 */
	mr = rtt_readl(rtc, MR) & (AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN);
	sr = rtt_readl(rtc, SR) & (mr >> 16);
	if (!sr)
		return IRQ_NONE;

	/* alarm status */
	if (sr & AT91_RTT_ALMS)
		events |= (RTC_AF | RTC_IRQF);

	/* timer update/increment */
	if (sr & AT91_RTT_RTTINC)
		events |= (RTC_UF | RTC_IRQF);

	rtc_update_irq(rtc->rtcdev, 1, events);

	pr_debug("%s: num=%ld, events=0x%02lx\n", __func__,
		events >> 8, events & 0x000000FF);

	return IRQ_HANDLED;
}

static const struct rtc_class_ops at91_rtc_ops = {
	.read_time	= at91_rtc_readtime,
	.set_time	= at91_rtc_settime,
	.read_alarm	= at91_rtc_readalarm,
	.set_alarm	= at91_rtc_setalarm,
	.proc		= at91_rtc_proc,
	.alarm_irq_enable = at91_rtc_alarm_irq_enable,
};

/*
 * Initialize and install RTC driver
 */
static int at91_rtc_probe(struct platform_device *pdev)
{
	struct resource	*r, *r_gpbr;
	struct sam9_rtc	*rtc;
	int		ret, irq;
	u32		mr;

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	r_gpbr = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	if (!r || !r_gpbr) {
		dev_err(&pdev->dev, "need 2 ressources\n");
		return -ENODEV;
	}

	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		dev_err(&pdev->dev, "failed to get interrupt resource\n");
		return irq;
	}

	rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
	if (!rtc)
		return -ENOMEM;

	rtc->irq = irq;

	/* platform setup code should have handled this; sigh */
	if (!device_can_wakeup(&pdev->dev))
		device_init_wakeup(&pdev->dev, 1);

	platform_set_drvdata(pdev, rtc);
	rtc->rtt = devm_ioremap(&pdev->dev, r->start, resource_size(r));
	if (!rtc->rtt) {
		dev_err(&pdev->dev, "failed to map registers, aborting.\n");
		return -ENOMEM;
	}

	rtc->gpbr = devm_ioremap(&pdev->dev, r_gpbr->start,
				resource_size(r_gpbr));
	if (!rtc->gpbr) {
		dev_err(&pdev->dev, "failed to map gpbr registers, aborting.\n");
		return -ENOMEM;
	}

	mr = rtt_readl(rtc, MR);

	/* unless RTT is counting at 1 Hz, re-initialize it */
	if ((mr & AT91_RTT_RTPRES) != AT91_SLOW_CLOCK) {
		mr = AT91_RTT_RTTRST | (AT91_SLOW_CLOCK & AT91_RTT_RTPRES);
		gpbr_writel(rtc, 0);
	}

	/* disable all interrupts (same as on shutdown path) */
	mr &= ~(AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN);
	rtt_writel(rtc, MR, mr);

	rtc->rtcdev = devm_rtc_device_register(&pdev->dev, pdev->name,
					&at91_rtc_ops, THIS_MODULE);
	if (IS_ERR(rtc->rtcdev))
		return PTR_ERR(rtc->rtcdev);

	/* register irq handler after we know what name we'll use */
	ret = devm_request_irq(&pdev->dev, rtc->irq, at91_rtc_interrupt,
				IRQF_SHARED, dev_name(&rtc->rtcdev->dev), rtc);
	if (ret) {
		dev_dbg(&pdev->dev, "can't share IRQ %d?\n", rtc->irq);
		return ret;
	}

	/* NOTE:  sam9260 rev A silicon has a ROM bug which resets the
	 * RTT on at least some reboots.  If you have that chip, you must
	 * initialize the time from some external source like a GPS, wall
	 * clock, discrete RTC, etc
	 */

	if (gpbr_readl(rtc) == 0)
		dev_warn(&pdev->dev, "%s: SET TIME!\n",
				dev_name(&rtc->rtcdev->dev));

	return 0;
}

/*
 * Disable and remove the RTC driver
 */
static int at91_rtc_remove(struct platform_device *pdev)
{
	struct sam9_rtc	*rtc = platform_get_drvdata(pdev);
	u32		mr = rtt_readl(rtc, MR);

	/* disable all interrupts */
	rtt_writel(rtc, MR, mr & ~(AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN));

	return 0;
}

static void at91_rtc_shutdown(struct platform_device *pdev)
{
	struct sam9_rtc	*rtc = platform_get_drvdata(pdev);
	u32		mr = rtt_readl(rtc, MR);

	rtc->imr = mr & (AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN);
	rtt_writel(rtc, MR, mr & ~rtc->imr);
}

#ifdef CONFIG_PM_SLEEP

/* AT91SAM9 RTC Power management control */

static int at91_rtc_suspend(struct device *dev)
{
	struct sam9_rtc	*rtc = dev_get_drvdata(dev);
	u32		mr = rtt_readl(rtc, MR);

	/*
	 * This IRQ is shared with DBGU and other hardware which isn't
	 * necessarily a wakeup event source.
	 */
	rtc->imr = mr & (AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN);
	if (rtc->imr) {
		if (device_may_wakeup(dev) && (mr & AT91_RTT_ALMIEN)) {
			enable_irq_wake(rtc->irq);
			/* don't let RTTINC cause wakeups */
			if (mr & AT91_RTT_RTTINCIEN)
				rtt_writel(rtc, MR, mr & ~AT91_RTT_RTTINCIEN);
		} else
			rtt_writel(rtc, MR, mr & ~rtc->imr);
	}

	return 0;
}

static int at91_rtc_resume(struct device *dev)
{
	struct sam9_rtc	*rtc = dev_get_drvdata(dev);
	u32		mr;

	if (rtc->imr) {
		if (device_may_wakeup(dev))
			disable_irq_wake(rtc->irq);
		mr = rtt_readl(rtc, MR);
		rtt_writel(rtc, MR, mr | rtc->imr);
	}

	return 0;
}
#endif

static SIMPLE_DEV_PM_OPS(at91_rtc_pm_ops, at91_rtc_suspend, at91_rtc_resume);

static struct platform_driver at91_rtc_driver = {
	.probe		= at91_rtc_probe,
	.remove		= at91_rtc_remove,
	.shutdown	= at91_rtc_shutdown,
	.driver		= {
		.name	= "rtc-at91sam9",
		.owner	= THIS_MODULE,
		.pm	= &at91_rtc_pm_ops,
	},
};

module_platform_driver(at91_rtc_driver);

MODULE_AUTHOR("Michel Benoit");
MODULE_DESCRIPTION("RTC driver for Atmel AT91SAM9x");
MODULE_LICENSE("GPL");
Commit	Line	Data
4cdf854f DB	1	/*
	2	* "RTT as Real Time Clock" driver for AT91SAM9 SoC family
	3	*
	4	* (C) 2007 Michel Benoit
	5	*
	6	* Based on rtc-at91rm9200.c by Rick Bronson
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License
	10	* as published by the Free Software Foundation; either version
	11	* 2 of the License, or (at your option) any later version.
	12	*/
	13
	14	#include <linux/module.h>
	15	#include <linux/kernel.h>
	16	#include <linux/platform_device.h>
	17	#include <linux/time.h>
	18	#include <linux/rtc.h>
	19	#include <linux/interrupt.h>
	20	#include <linux/ioctl.h>
5a0e3ad6	21	#include <linux/slab.h>
bcd2360c	22	#include <linux/platform_data/atmel.h>
9d42e465	23	#include <linux/io.h>
4cdf854f	24
4cdf854f DB	25	/*
	26	* This driver uses two configurable hardware resources that live in the
	27	* AT91SAM9 backup power domain (intended to be powered at all times)
	28	* to implement the Real Time Clock interfaces
	29	*
	30	* - A "Real-time Timer" (RTT) counts up in seconds from a base time.
	31	* We can't assign the counter value (CRTV) ... but we can reset it.
	32	*
	33	* - One of the "General Purpose Backup Registers" (GPBRs) holds the
	34	* base time, normally an offset from the beginning of the POSIX
	35	* epoch (1970-Jan-1 00:00:00 UTC). Some systems also include the
	36	* local timezone's offset.
	37	*
	38	* The RTC's value is the RTT counter plus that offset. The RTC's alarm
	39	* is likewise a base (ALMV) plus that offset.
	40	*
	41	* Not all RTTs will be used as RTCs; some systems have multiple RTTs to
	42	* choose from, or a "real" RTC module. All systems have multiple GPBR
	43	* registers available, likewise usable for more than "RTC" support.
	44	*/
	45
6575bd7c BB	46	#define AT91_RTT_MR 0x00 /* Real-time Mode Register */
	47	#define AT91_RTT_RTPRES (0xffff << 0) /* Real-time Timer Prescaler Value */
	48	#define AT91_RTT_ALMIEN (1 << 16) /* Alarm Interrupt Enable */
	49	#define AT91_RTT_RTTINCIEN (1 << 17) /* Real Time Timer Increment Interrupt Enable */
	50	#define AT91_RTT_RTTRST (1 << 18) /* Real Time Timer Restart */
	51
	52	#define AT91_RTT_AR 0x04 /* Real-time Alarm Register */
	53	#define AT91_RTT_ALMV (0xffffffff) /* Alarm Value */
	54
	55	#define AT91_RTT_VR 0x08 /* Real-time Value Register */
	56	#define AT91_RTT_CRTV (0xffffffff) /* Current Real-time Value */
	57
	58	#define AT91_RTT_SR 0x0c /* Real-time Status Register */
	59	#define AT91_RTT_ALMS (1 << 0) /* Real-time Alarm Status */
	60	#define AT91_RTT_RTTINC (1 << 1) /* Real-time Timer Increment */
	61
	62	#define AT91_SLOW_CLOCK 32768
	63
4cdf854f DB	64	/*
	65	* We store ALARM_DISABLED in ALMV to record that no alarm is set.
	66	* It's also the reset value for that field.
	67	*/
	68	#define ALARM_DISABLED ((u32)~0)
	69
	70
	71	struct sam9_rtc {
	72	void __iomem *rtt;
	73	struct rtc_device *rtcdev;
	74	u32 imr;
b3af8b49	75	void __iomem *gpbr;
e402af6c	76	int irq;
4cdf854f DB	77	};
	78
	79	#define rtt_readl(rtc, field) \
	80	__raw_readl((rtc)->rtt + AT91_RTT_ ## field)
	81	#define rtt_writel(rtc, field, val) \
	82	__raw_writel((val), (rtc)->rtt + AT91_RTT_ ## field)
	83
	84	#define gpbr_readl(rtc) \
b3af8b49	85	__raw_readl((rtc)->gpbr)
4cdf854f	86	#define gpbr_writel(rtc, val) \
b3af8b49	87	__raw_writel((val), (rtc)->gpbr)
4cdf854f DB	88
	89	/*
	90	* Read current time and date in RTC
	91	*/
	92	static int at91_rtc_readtime(struct device dev, struct rtc_time tm)
	93	{
	94	struct sam9_rtc *rtc = dev_get_drvdata(dev);
	95	u32 secs, secs2;
	96	u32 offset;
	97
	98	/* read current time offset */
	99	offset = gpbr_readl(rtc);
	100	if (offset == 0)
	101	return -EILSEQ;
	102
	103	/* reread the counter to help sync the two clock domains */
	104	secs = rtt_readl(rtc, VR);
	105	secs2 = rtt_readl(rtc, VR);
	106	if (secs != secs2)
	107	secs = rtt_readl(rtc, VR);
	108
	109	rtc_time_to_tm(offset + secs, tm);
	110
	111	dev_dbg(dev, "%s: %4d-%02d-%02d %02d:%02d:%02d\n", "readtime",
	112	1900 + tm->tm_year, tm->tm_mon, tm->tm_mday,
	113	tm->tm_hour, tm->tm_min, tm->tm_sec);
	114
	115	return 0;
	116	}
	117
	118	/*
	119	* Set current time and date in RTC
	120	*/
	121	static int at91_rtc_settime(struct device dev, struct rtc_time tm)
	122	{
	123	struct sam9_rtc *rtc = dev_get_drvdata(dev);
	124	int err;
	125	u32 offset, alarm, mr;
	126	unsigned long secs;
	127
	128	dev_dbg(dev, "%s: %4d-%02d-%02d %02d:%02d:%02d\n", "settime",
	129	1900 + tm->tm_year, tm->tm_mon, tm->tm_mday,
	130	tm->tm_hour, tm->tm_min, tm->tm_sec);
	131
	132	err = rtc_tm_to_time(tm, &secs);
	133	if (err != 0)
	134	return err;
	135
	136	mr = rtt_readl(rtc, MR);
	137
	138	/* disable interrupts */
	139	rtt_writel(rtc, MR, mr & ~(AT91_RTT_ALMIEN \| AT91_RTT_RTTINCIEN));
	140
	141	/* read current time offset */
	142	offset = gpbr_readl(rtc);
	143
	144	/* store the new base time in a battery backup register */
	145	secs += 1;
	146	gpbr_writel(rtc, secs);
	147
	148	/* adjust the alarm time for the new base */
	149	alarm = rtt_readl(rtc, AR);
	150	if (alarm != ALARM_DISABLED) {
	151	if (offset > secs) {
152	/* time jumped backwards, increase time until alarm */
153	alarm += (offset - secs);
154	} else if ((alarm + offset) > secs) {
155	/* time jumped forwards, decrease time until alarm */
156	alarm -= (secs - offset);
157	} else {
158	/* time jumped past the alarm, disable alarm */
159	alarm = ALARM_DISABLED;
160	mr &= ~AT91_RTT_ALMIEN;
161	}
162	rtt_writel(rtc, AR, alarm);
163	}
164
165	/* reset the timer, and re-enable interrupts */
166	rtt_writel(rtc, MR, mr \| AT91_RTT_RTTRST);
167
168	return 0;
169	}
170
171	static int at91_rtc_readalarm(struct device dev, struct rtc_wkalrm alrm)
172	{
173	struct sam9_rtc *rtc = dev_get_drvdata(dev);
174	struct rtc_time *tm = &alrm->time;
175	u32 alarm = rtt_readl(rtc, AR);
176	u32 offset;
177
178	offset = gpbr_readl(rtc);
179	if (offset == 0)
180	return -EILSEQ;
181
870a2761	182	memset(alrm, 0, sizeof(*alrm));
4cdf854f DB	183	if (alarm != ALARM_DISABLED && offset != 0) {
	184	rtc_time_to_tm(offset + alarm, tm);
	185
	186	dev_dbg(dev, "%s: %4d-%02d-%02d %02d:%02d:%02d\n", "readalarm",
	187	1900 + tm->tm_year, tm->tm_mon, tm->tm_mday,
	188	tm->tm_hour, tm->tm_min, tm->tm_sec);
	189
	190	if (rtt_readl(rtc, MR) & AT91_RTT_ALMIEN)
	191	alrm->enabled = 1;
	192	}
	193
	194	return 0;
	195	}
	196
	197	static int at91_rtc_setalarm(struct device dev, struct rtc_wkalrm alrm)
	198	{
	199	struct sam9_rtc *rtc = dev_get_drvdata(dev);
	200	struct rtc_time *tm = &alrm->time;
	201	unsigned long secs;
	202	u32 offset;
	203	u32 mr;
	204	int err;
	205
	206	err = rtc_tm_to_time(tm, &secs);
	207	if (err != 0)
	208	return err;
	209
	210	offset = gpbr_readl(rtc);
	211	if (offset == 0) {
	212	/* time is not set */
	213	return -EILSEQ;
	214	}
	215	mr = rtt_readl(rtc, MR);
	216	rtt_writel(rtc, MR, mr & ~AT91_RTT_ALMIEN);
	217
	218	/* alarm in the past? finish and leave disabled */
	219	if (secs <= offset) {
	220	rtt_writel(rtc, AR, ALARM_DISABLED);
	221	return 0;
	222	}
	223
	224	/* else set alarm and maybe enable it */
	225	rtt_writel(rtc, AR, secs - offset);
	226	if (alrm->enabled)
	227	rtt_writel(rtc, MR, mr \| AT91_RTT_ALMIEN);
	228
	229	dev_dbg(dev, "%s: %4d-%02d-%02d %02d:%02d:%02d\n", "setalarm",
	230	tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_hour,
	231	tm->tm_min, tm->tm_sec);
	232
	233	return 0;
	234	}
	235
16380c15 JS	236	static int at91_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
	237	{
	238	struct sam9_rtc *rtc = dev_get_drvdata(dev);
	239	u32 mr = rtt_readl(rtc, MR);
	240
	241	dev_dbg(dev, "alarm_irq_enable: enabled=%08x, mr %08x\n", enabled, mr);
	242	if (enabled)
	243	rtt_writel(rtc, MR, mr \| AT91_RTT_ALMIEN);
	244	else
	245	rtt_writel(rtc, MR, mr & ~AT91_RTT_ALMIEN);
	246	return 0;
	247	}
	248
4cdf854f DB	249	/*
	250	* Provide additional RTC information in /proc/driver/rtc
	251	*/
	252	static int at91_rtc_proc(struct device dev, struct seq_file seq)
	253	{
	254	struct sam9_rtc *rtc = dev_get_drvdata(dev);
	255	u32 mr = mr = rtt_readl(rtc, MR);
	256
	257	seq_printf(seq, "update_IRQ\t: %s\n",
	258	(mr & AT91_RTT_RTTINCIEN) ? "yes" : "no");
	259	return 0;
	260	}
	261
	262	/*
	263	* IRQ handler for the RTC
	264	*/
	265	static irqreturn_t at91_rtc_interrupt(int irq, void *_rtc)
	266	{
	267	struct sam9_rtc *rtc = _rtc;
	268	u32 sr, mr;
	269	unsigned long events = 0;
	270
	271	/* Shared interrupt may be for another device. Note: reading
	272	* SR clears it, so we must only read it in this irq handler!
	273	*/
	274	mr = rtt_readl(rtc, MR) & (AT91_RTT_ALMIEN \| AT91_RTT_RTTINCIEN);
9fedc9f1	275	sr = rtt_readl(rtc, SR) & (mr >> 16);
4cdf854f DB	276	if (!sr)
	277	return IRQ_NONE;
	278
	279	/* alarm status */
	280	if (sr & AT91_RTT_ALMS)
	281	events \|= (RTC_AF \| RTC_IRQF);
	282
	283	/* timer update/increment */
	284	if (sr & AT91_RTT_RTTINC)
	285	events \|= (RTC_UF \| RTC_IRQF);
	286
	287	rtc_update_irq(rtc->rtcdev, 1, events);
	288
2a4e2b87	289	pr_debug("%s: num=%ld, events=0x%02lx\n", __func__,
4cdf854f DB	290	events >> 8, events & 0x000000FF);
	291
	292	return IRQ_HANDLED;
	293	}
	294
	295	static const struct rtc_class_ops at91_rtc_ops = {
4cdf854f DB	296	.read_time = at91_rtc_readtime,
	297	.set_time = at91_rtc_settime,
	298	.read_alarm = at91_rtc_readalarm,
	299	.set_alarm = at91_rtc_setalarm,
	300	.proc = at91_rtc_proc,
d4035850	301	.alarm_irq_enable = at91_rtc_alarm_irq_enable,
4cdf854f DB	302	};
	303
	304	/*
	305	* Initialize and install RTC driver
	306	*/
5a167f45	307	static int at91_rtc_probe(struct platform_device *pdev)
4cdf854f	308	{
b3af8b49	309	struct resource r, r_gpbr;
4cdf854f	310	struct sam9_rtc *rtc;
e402af6c	311	int ret, irq;
4cdf854f DB	312	u32 mr;
	313
	314	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
b3af8b49 JCPV	315	r_gpbr = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	316	if (!r \|\| !r_gpbr) {
	317	dev_err(&pdev->dev, "need 2 ressources\n");
4cdf854f	318	return -ENODEV;
b3af8b49	319	}
4cdf854f	320
e402af6c LD	321	irq = platform_get_irq(pdev, 0);
	322	if (irq < 0) {
	323	dev_err(&pdev->dev, "failed to get interrupt resource\n");
	324	return irq;
	325	}
	326
9d42e465	327	rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
4cdf854f DB	328	if (!rtc)
	329	return -ENOMEM;
	330
e402af6c LD	331	rtc->irq = irq;
e402af6c LD	332
9fedc9f1 DB	333	/* platform setup code should have handled this; sigh */
	334	if (!device_can_wakeup(&pdev->dev))
	335	device_init_wakeup(&pdev->dev, 1);
	336
4cdf854f	337	platform_set_drvdata(pdev, rtc);
9d42e465	338	rtc->rtt = devm_ioremap(&pdev->dev, r->start, resource_size(r));
2dcc90e6 JCPV	339	if (!rtc->rtt) {
2dcc90e6 JCPV	340	dev_err(&pdev->dev, "failed to map registers, aborting.\n");
61cc483a	341	return -ENOMEM;
2dcc90e6	342	}
4cdf854f	343
9d42e465 JH	344	rtc->gpbr = devm_ioremap(&pdev->dev, r_gpbr->start,
9d42e465 JH	345	resource_size(r_gpbr));
b3af8b49 JCPV	346	if (!rtc->gpbr) {
b3af8b49 JCPV	347	dev_err(&pdev->dev, "failed to map gpbr registers, aborting.\n");
61cc483a	348	return -ENOMEM;
b3af8b49 JCPV	349	}
b3af8b49 JCPV	350
4cdf854f DB	351	mr = rtt_readl(rtc, MR);
	352
	353	/* unless RTT is counting at 1 Hz, re-initialize it */
	354	if ((mr & AT91_RTT_RTPRES) != AT91_SLOW_CLOCK) {
	355	mr = AT91_RTT_RTTRST \| (AT91_SLOW_CLOCK & AT91_RTT_RTPRES);
	356	gpbr_writel(rtc, 0);
	357	}
	358
	359	/* disable all interrupts (same as on shutdown path) */
	360	mr &= ~(AT91_RTT_ALMIEN \| AT91_RTT_RTTINCIEN);
	361	rtt_writel(rtc, MR, mr);
	362
9d42e465 JH	363	rtc->rtcdev = devm_rtc_device_register(&pdev->dev, pdev->name,
9d42e465 JH	364	&at91_rtc_ops, THIS_MODULE);
61cc483a JH	365	if (IS_ERR(rtc->rtcdev))
61cc483a JH	366	return PTR_ERR(rtc->rtcdev);
4cdf854f DB	367
4cdf854f DB	368	/* register irq handler after we know what name we'll use */
9d42e465 JH	369	ret = devm_request_irq(&pdev->dev, rtc->irq, at91_rtc_interrupt,
9d42e465 JH	370	IRQF_SHARED, dev_name(&rtc->rtcdev->dev), rtc);
4cdf854f	371	if (ret) {
e402af6c	372	dev_dbg(&pdev->dev, "can't share IRQ %d?\n", rtc->irq);
61cc483a	373	return ret;
4cdf854f DB	374	}
	375
	376	/* NOTE: sam9260 rev A silicon has a ROM bug which resets the
	377	* RTT on at least some reboots. If you have that chip, you must
	378	* initialize the time from some external source like a GPS, wall
	379	* clock, discrete RTC, etc
	380	*/
	381
	382	if (gpbr_readl(rtc) == 0)
	383	dev_warn(&pdev->dev, "%s: SET TIME!\n",
744bcb13	384	dev_name(&rtc->rtcdev->dev));
4cdf854f DB	385
4cdf854f DB	386	return 0;
4cdf854f DB	387	}
	388
	389	/*
	390	* Disable and remove the RTC driver
	391	*/
5a167f45	392	static int at91_rtc_remove(struct platform_device *pdev)
4cdf854f DB	393	{
	394	struct sam9_rtc *rtc = platform_get_drvdata(pdev);
	395	u32 mr = rtt_readl(rtc, MR);
	396
	397	/* disable all interrupts */
	398	rtt_writel(rtc, MR, mr & ~(AT91_RTT_ALMIEN \| AT91_RTT_RTTINCIEN));
4cdf854f	399
4cdf854f DB	400	return 0;
	401	}
	402
	403	static void at91_rtc_shutdown(struct platform_device *pdev)
	404	{
	405	struct sam9_rtc *rtc = platform_get_drvdata(pdev);
	406	u32 mr = rtt_readl(rtc, MR);
	407
	408	rtc->imr = mr & (AT91_RTT_ALMIEN \| AT91_RTT_RTTINCIEN);
	409	rtt_writel(rtc, MR, mr & ~rtc->imr);
	410	}
	411
4dc8eb13	412	#ifdef CONFIG_PM_SLEEP
4cdf854f DB	413
	414	/* AT91SAM9 RTC Power management control */
	415
4dc8eb13	416	static int at91_rtc_suspend(struct device *dev)
4cdf854f	417	{
4dc8eb13	418	struct sam9_rtc *rtc = dev_get_drvdata(dev);
4cdf854f DB	419	u32 mr = rtt_readl(rtc, MR);
	420
	421	/*
	422	* This IRQ is shared with DBGU and other hardware which isn't
	423	* necessarily a wakeup event source.
	424	*/
	425	rtc->imr = mr & (AT91_RTT_ALMIEN \| AT91_RTT_RTTINCIEN);
	426	if (rtc->imr) {
4dc8eb13	427	if (device_may_wakeup(dev) && (mr & AT91_RTT_ALMIEN)) {
e402af6c	428	enable_irq_wake(rtc->irq);
4cdf854f DB	429	/* don't let RTTINC cause wakeups */
	430	if (mr & AT91_RTT_RTTINCIEN)
	431	rtt_writel(rtc, MR, mr & ~AT91_RTT_RTTINCIEN);
	432	} else
	433	rtt_writel(rtc, MR, mr & ~rtc->imr);
	434	}
	435
	436	return 0;
	437	}
	438
4dc8eb13	439	static int at91_rtc_resume(struct device *dev)
4cdf854f	440	{
4dc8eb13	441	struct sam9_rtc *rtc = dev_get_drvdata(dev);
4cdf854f DB	442	u32 mr;
	443
	444	if (rtc->imr) {
4dc8eb13	445	if (device_may_wakeup(dev))
e402af6c	446	disable_irq_wake(rtc->irq);
4cdf854f DB	447	mr = rtt_readl(rtc, MR);
	448	rtt_writel(rtc, MR, mr \| rtc->imr);
	449	}
	450
	451	return 0;
	452	}
4cdf854f DB	453	#endif
4cdf854f DB	454
4dc8eb13 JH	455	static SIMPLE_DEV_PM_OPS(at91_rtc_pm_ops, at91_rtc_suspend, at91_rtc_resume);
4dc8eb13 JH	456
4cdf854f	457	static struct platform_driver at91_rtc_driver = {
205056a3	458	.probe = at91_rtc_probe,
5a167f45	459	.remove = at91_rtc_remove,
4cdf854f	460	.shutdown = at91_rtc_shutdown,
205056a3 JCPV	461	.driver = {
	462	.name = "rtc-at91sam9",
	463	.owner = THIS_MODULE,
4dc8eb13	464	.pm = &at91_rtc_pm_ops,
205056a3	465	},
4cdf854f DB	466	};
4cdf854f DB	467
477d30d7	468	module_platform_driver(at91_rtc_driver);
4cdf854f DB	469
	470	MODULE_AUTHOR("Michel Benoit");
	471	MODULE_DESCRIPTION("RTC driver for Atmel AT91SAM9x");
	472	MODULE_LICENSE("GPL");