mpt3sas: combine fw_event_work and its event_data
[deliverable/linux.git] / drivers / rtc / rtc-ds1307.c
CommitLineData
1abb0dc9
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1/*
2 * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips.
3 *
4 * Copyright (C) 2005 James Chapman (ds1337 core)
5 * Copyright (C) 2006 David Brownell
a2166858 6 * Copyright (C) 2009 Matthias Fuchs (rx8025 support)
bc48b902 7 * Copyright (C) 2012 Bertrand Achard (nvram access fixes)
1abb0dc9
DB
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/module.h>
15#include <linux/init.h>
16#include <linux/slab.h>
17#include <linux/i2c.h>
18#include <linux/string.h>
19#include <linux/rtc.h>
20#include <linux/bcd.h>
eb86c306 21#include <linux/rtc/ds1307.h>
1abb0dc9 22
40ce972d
DA
23/*
24 * We can't determine type by probing, but if we expect pre-Linux code
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25 * to have set the chip up as a clock (turning on the oscillator and
26 * setting the date and time), Linux can ignore the non-clock features.
27 * That's a natural job for a factory or repair bench.
1abb0dc9
DB
28 */
29enum ds_type {
045e0e85
DB
30 ds_1307,
31 ds_1337,
32 ds_1338,
33 ds_1339,
34 ds_1340,
33df2ee1 35 ds_1388,
97f902b7 36 ds_3231,
045e0e85 37 m41t00,
43fcb815 38 mcp7941x,
a2166858 39 rx_8025,
32d322bc 40 last_ds_type /* always last */
40ce972d 41 /* rs5c372 too? different address... */
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DB
42};
43
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44
45/* RTC registers don't differ much, except for the century flag */
46#define DS1307_REG_SECS 0x00 /* 00-59 */
47# define DS1307_BIT_CH 0x80
be5f59f4 48# define DS1340_BIT_nEOSC 0x80
43fcb815 49# define MCP7941X_BIT_ST 0x80
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DB
50#define DS1307_REG_MIN 0x01 /* 00-59 */
51#define DS1307_REG_HOUR 0x02 /* 00-23, or 1-12{am,pm} */
c065f35c
DB
52# define DS1307_BIT_12HR 0x40 /* in REG_HOUR */
53# define DS1307_BIT_PM 0x20 /* in REG_HOUR */
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DB
54# define DS1340_BIT_CENTURY_EN 0x80 /* in REG_HOUR */
55# define DS1340_BIT_CENTURY 0x40 /* in REG_HOUR */
56#define DS1307_REG_WDAY 0x03 /* 01-07 */
43fcb815 57# define MCP7941X_BIT_VBATEN 0x08
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DB
58#define DS1307_REG_MDAY 0x04 /* 01-31 */
59#define DS1307_REG_MONTH 0x05 /* 01-12 */
60# define DS1337_BIT_CENTURY 0x80 /* in REG_MONTH */
61#define DS1307_REG_YEAR 0x06 /* 00-99 */
62
40ce972d
DA
63/*
64 * Other registers (control, status, alarms, trickle charge, NVRAM, etc)
045e0e85
DB
65 * start at 7, and they differ a LOT. Only control and status matter for
66 * basic RTC date and time functionality; be careful using them.
1abb0dc9 67 */
045e0e85 68#define DS1307_REG_CONTROL 0x07 /* or ds1338 */
1abb0dc9 69# define DS1307_BIT_OUT 0x80
be5f59f4 70# define DS1338_BIT_OSF 0x20
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DB
71# define DS1307_BIT_SQWE 0x10
72# define DS1307_BIT_RS1 0x02
73# define DS1307_BIT_RS0 0x01
74#define DS1337_REG_CONTROL 0x0e
75# define DS1337_BIT_nEOSC 0x80
cb49a5e9 76# define DS1339_BIT_BBSQI 0x20
97f902b7 77# define DS3231_BIT_BBSQW 0x40 /* same as BBSQI */
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78# define DS1337_BIT_RS2 0x10
79# define DS1337_BIT_RS1 0x08
80# define DS1337_BIT_INTCN 0x04
81# define DS1337_BIT_A2IE 0x02
82# define DS1337_BIT_A1IE 0x01
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DB
83#define DS1340_REG_CONTROL 0x07
84# define DS1340_BIT_OUT 0x80
85# define DS1340_BIT_FT 0x40
86# define DS1340_BIT_CALIB_SIGN 0x20
87# define DS1340_M_CALIBRATION 0x1f
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RG
88#define DS1340_REG_FLAG 0x09
89# define DS1340_BIT_OSF 0x80
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90#define DS1337_REG_STATUS 0x0f
91# define DS1337_BIT_OSF 0x80
92# define DS1337_BIT_A2I 0x02
93# define DS1337_BIT_A1I 0x01
cb49a5e9 94#define DS1339_REG_ALARM1_SECS 0x07
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WS
95
96#define DS13XX_TRICKLE_CHARGER_MAGIC 0xa0
1abb0dc9 97
a2166858
MF
98#define RX8025_REG_CTRL1 0x0e
99# define RX8025_BIT_2412 0x20
100#define RX8025_REG_CTRL2 0x0f
101# define RX8025_BIT_PON 0x10
102# define RX8025_BIT_VDET 0x40
103# define RX8025_BIT_XST 0x20
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104
105
106struct ds1307 {
33df2ee1 107 u8 offset; /* register's offset */
cb49a5e9 108 u8 regs[11];
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109 u16 nvram_offset;
110 struct bin_attribute *nvram;
1abb0dc9 111 enum ds_type type;
cb49a5e9
RG
112 unsigned long flags;
113#define HAS_NVRAM 0 /* bit 0 == sysfs file active */
114#define HAS_ALARM 1 /* bit 1 == irq claimed */
045e0e85 115 struct i2c_client *client;
1abb0dc9 116 struct rtc_device *rtc;
cb49a5e9 117 struct work_struct work;
0cc43a18 118 s32 (*read_block_data)(const struct i2c_client *client, u8 command,
30e7b039 119 u8 length, u8 *values);
0cc43a18 120 s32 (*write_block_data)(const struct i2c_client *client, u8 command,
30e7b039 121 u8 length, const u8 *values);
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122};
123
045e0e85 124struct chip_desc {
045e0e85 125 unsigned alarm:1;
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126 u16 nvram_offset;
127 u16 nvram_size;
eb86c306 128 u16 trickle_charger_reg;
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DB
129};
130
32d322bc
WS
131static const struct chip_desc chips[last_ds_type] = {
132 [ds_1307] = {
9eab0a78
AB
133 .nvram_offset = 8,
134 .nvram_size = 56,
32d322bc
WS
135 },
136 [ds_1337] = {
137 .alarm = 1,
138 },
139 [ds_1338] = {
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AB
140 .nvram_offset = 8,
141 .nvram_size = 56,
32d322bc
WS
142 },
143 [ds_1339] = {
144 .alarm = 1,
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WS
145 .trickle_charger_reg = 0x10,
146 },
147 [ds_1340] = {
148 .trickle_charger_reg = 0x08,
149 },
150 [ds_1388] = {
151 .trickle_charger_reg = 0x0a,
32d322bc
WS
152 },
153 [ds_3231] = {
154 .alarm = 1,
155 },
9eab0a78 156 [mcp7941x] = {
1d1945d2 157 .alarm = 1,
9eab0a78
AB
158 /* this is battery backed SRAM */
159 .nvram_offset = 0x20,
160 .nvram_size = 0x40,
161 },
32d322bc 162};
045e0e85 163
3760f736
JD
164static const struct i2c_device_id ds1307_id[] = {
165 { "ds1307", ds_1307 },
166 { "ds1337", ds_1337 },
167 { "ds1338", ds_1338 },
168 { "ds1339", ds_1339 },
33df2ee1 169 { "ds1388", ds_1388 },
3760f736 170 { "ds1340", ds_1340 },
97f902b7 171 { "ds3231", ds_3231 },
3760f736 172 { "m41t00", m41t00 },
43fcb815 173 { "mcp7941x", mcp7941x },
31c1771c 174 { "pt7c4338", ds_1307 },
a2166858 175 { "rx8025", rx_8025 },
3760f736
JD
176 { }
177};
178MODULE_DEVICE_TABLE(i2c, ds1307_id);
1abb0dc9 179
cb49a5e9
RG
180/*----------------------------------------------------------------------*/
181
30e7b039
ES
182#define BLOCK_DATA_MAX_TRIES 10
183
0cc43a18
JD
184static s32 ds1307_read_block_data_once(const struct i2c_client *client,
185 u8 command, u8 length, u8 *values)
30e7b039
ES
186{
187 s32 i, data;
188
189 for (i = 0; i < length; i++) {
190 data = i2c_smbus_read_byte_data(client, command + i);
191 if (data < 0)
192 return data;
193 values[i] = data;
194 }
195 return i;
196}
197
0cc43a18 198static s32 ds1307_read_block_data(const struct i2c_client *client, u8 command,
30e7b039
ES
199 u8 length, u8 *values)
200{
bc48b902 201 u8 oldvalues[255];
30e7b039
ES
202 s32 ret;
203 int tries = 0;
204
205 dev_dbg(&client->dev, "ds1307_read_block_data (length=%d)\n", length);
206 ret = ds1307_read_block_data_once(client, command, length, values);
207 if (ret < 0)
208 return ret;
209 do {
210 if (++tries > BLOCK_DATA_MAX_TRIES) {
211 dev_err(&client->dev,
212 "ds1307_read_block_data failed\n");
213 return -EIO;
214 }
215 memcpy(oldvalues, values, length);
216 ret = ds1307_read_block_data_once(client, command, length,
217 values);
218 if (ret < 0)
219 return ret;
220 } while (memcmp(oldvalues, values, length));
221 return length;
222}
223
0cc43a18 224static s32 ds1307_write_block_data(const struct i2c_client *client, u8 command,
30e7b039
ES
225 u8 length, const u8 *values)
226{
bc48b902 227 u8 currvalues[255];
30e7b039
ES
228 int tries = 0;
229
230 dev_dbg(&client->dev, "ds1307_write_block_data (length=%d)\n", length);
231 do {
232 s32 i, ret;
233
234 if (++tries > BLOCK_DATA_MAX_TRIES) {
235 dev_err(&client->dev,
236 "ds1307_write_block_data failed\n");
237 return -EIO;
238 }
239 for (i = 0; i < length; i++) {
240 ret = i2c_smbus_write_byte_data(client, command + i,
241 values[i]);
242 if (ret < 0)
243 return ret;
244 }
245 ret = ds1307_read_block_data_once(client, command, length,
246 currvalues);
247 if (ret < 0)
248 return ret;
249 } while (memcmp(currvalues, values, length));
250 return length;
251}
252
253/*----------------------------------------------------------------------*/
254
bc48b902
BA
255/* These RTC devices are not designed to be connected to a SMbus adapter.
256 SMbus limits block operations length to 32 bytes, whereas it's not
257 limited on I2C buses. As a result, accesses may exceed 32 bytes;
258 in that case, split them into smaller blocks */
259
260static s32 ds1307_native_smbus_write_block_data(const struct i2c_client *client,
261 u8 command, u8 length, const u8 *values)
262{
263 u8 suboffset = 0;
264
265 if (length <= I2C_SMBUS_BLOCK_MAX)
266 return i2c_smbus_write_i2c_block_data(client,
267 command, length, values);
268
269 while (suboffset < length) {
270 s32 retval = i2c_smbus_write_i2c_block_data(client,
271 command + suboffset,
272 min(I2C_SMBUS_BLOCK_MAX, length - suboffset),
273 values + suboffset);
274 if (retval < 0)
275 return retval;
276
277 suboffset += I2C_SMBUS_BLOCK_MAX;
278 }
279 return length;
280}
281
282static s32 ds1307_native_smbus_read_block_data(const struct i2c_client *client,
283 u8 command, u8 length, u8 *values)
284{
285 u8 suboffset = 0;
286
287 if (length <= I2C_SMBUS_BLOCK_MAX)
288 return i2c_smbus_read_i2c_block_data(client,
289 command, length, values);
290
291 while (suboffset < length) {
292 s32 retval = i2c_smbus_read_i2c_block_data(client,
293 command + suboffset,
294 min(I2C_SMBUS_BLOCK_MAX, length - suboffset),
295 values + suboffset);
296 if (retval < 0)
297 return retval;
298
299 suboffset += I2C_SMBUS_BLOCK_MAX;
300 }
301 return length;
302}
303
304/*----------------------------------------------------------------------*/
305
cb49a5e9
RG
306/*
307 * The IRQ logic includes a "real" handler running in IRQ context just
308 * long enough to schedule this workqueue entry. We need a task context
309 * to talk to the RTC, since I2C I/O calls require that; and disable the
310 * IRQ until we clear its status on the chip, so that this handler can
311 * work with any type of triggering (not just falling edge).
312 *
313 * The ds1337 and ds1339 both have two alarms, but we only use the first
314 * one (with a "seconds" field). For ds1337 we expect nINTA is our alarm
315 * signal; ds1339 chips have only one alarm signal.
316 */
317static void ds1307_work(struct work_struct *work)
318{
319 struct ds1307 *ds1307;
320 struct i2c_client *client;
321 struct mutex *lock;
322 int stat, control;
323
324 ds1307 = container_of(work, struct ds1307, work);
325 client = ds1307->client;
326 lock = &ds1307->rtc->ops_lock;
327
328 mutex_lock(lock);
329 stat = i2c_smbus_read_byte_data(client, DS1337_REG_STATUS);
330 if (stat < 0)
331 goto out;
332
333 if (stat & DS1337_BIT_A1I) {
334 stat &= ~DS1337_BIT_A1I;
335 i2c_smbus_write_byte_data(client, DS1337_REG_STATUS, stat);
336
337 control = i2c_smbus_read_byte_data(client, DS1337_REG_CONTROL);
338 if (control < 0)
339 goto out;
340
341 control &= ~DS1337_BIT_A1IE;
342 i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL, control);
343
cb49a5e9 344 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
cb49a5e9
RG
345 }
346
347out:
348 if (test_bit(HAS_ALARM, &ds1307->flags))
349 enable_irq(client->irq);
350 mutex_unlock(lock);
351}
352
353static irqreturn_t ds1307_irq(int irq, void *dev_id)
354{
355 struct i2c_client *client = dev_id;
356 struct ds1307 *ds1307 = i2c_get_clientdata(client);
357
358 disable_irq_nosync(irq);
359 schedule_work(&ds1307->work);
360 return IRQ_HANDLED;
361}
362
363/*----------------------------------------------------------------------*/
364
1abb0dc9
DB
365static int ds1307_get_time(struct device *dev, struct rtc_time *t)
366{
367 struct ds1307 *ds1307 = dev_get_drvdata(dev);
368 int tmp;
369
045e0e85 370 /* read the RTC date and time registers all at once */
30e7b039 371 tmp = ds1307->read_block_data(ds1307->client,
33df2ee1 372 ds1307->offset, 7, ds1307->regs);
fed40b73 373 if (tmp != 7) {
1abb0dc9
DB
374 dev_err(dev, "%s error %d\n", "read", tmp);
375 return -EIO;
376 }
377
01a4ca16 378 dev_dbg(dev, "%s: %7ph\n", "read", ds1307->regs);
1abb0dc9 379
fe20ba70
AB
380 t->tm_sec = bcd2bin(ds1307->regs[DS1307_REG_SECS] & 0x7f);
381 t->tm_min = bcd2bin(ds1307->regs[DS1307_REG_MIN] & 0x7f);
1abb0dc9 382 tmp = ds1307->regs[DS1307_REG_HOUR] & 0x3f;
fe20ba70
AB
383 t->tm_hour = bcd2bin(tmp);
384 t->tm_wday = bcd2bin(ds1307->regs[DS1307_REG_WDAY] & 0x07) - 1;
385 t->tm_mday = bcd2bin(ds1307->regs[DS1307_REG_MDAY] & 0x3f);
1abb0dc9 386 tmp = ds1307->regs[DS1307_REG_MONTH] & 0x1f;
fe20ba70 387 t->tm_mon = bcd2bin(tmp) - 1;
1abb0dc9
DB
388
389 /* assume 20YY not 19YY, and ignore DS1337_BIT_CENTURY */
fe20ba70 390 t->tm_year = bcd2bin(ds1307->regs[DS1307_REG_YEAR]) + 100;
1abb0dc9
DB
391
392 dev_dbg(dev, "%s secs=%d, mins=%d, "
393 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
394 "read", t->tm_sec, t->tm_min,
395 t->tm_hour, t->tm_mday,
396 t->tm_mon, t->tm_year, t->tm_wday);
397
045e0e85
DB
398 /* initial clock setting can be undefined */
399 return rtc_valid_tm(t);
1abb0dc9
DB
400}
401
402static int ds1307_set_time(struct device *dev, struct rtc_time *t)
403{
404 struct ds1307 *ds1307 = dev_get_drvdata(dev);
405 int result;
406 int tmp;
407 u8 *buf = ds1307->regs;
408
409 dev_dbg(dev, "%s secs=%d, mins=%d, "
410 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
11966adc
JG
411 "write", t->tm_sec, t->tm_min,
412 t->tm_hour, t->tm_mday,
413 t->tm_mon, t->tm_year, t->tm_wday);
1abb0dc9 414
fe20ba70
AB
415 buf[DS1307_REG_SECS] = bin2bcd(t->tm_sec);
416 buf[DS1307_REG_MIN] = bin2bcd(t->tm_min);
417 buf[DS1307_REG_HOUR] = bin2bcd(t->tm_hour);
418 buf[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1);
419 buf[DS1307_REG_MDAY] = bin2bcd(t->tm_mday);
420 buf[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1);
1abb0dc9
DB
421
422 /* assume 20YY not 19YY */
423 tmp = t->tm_year - 100;
fe20ba70 424 buf[DS1307_REG_YEAR] = bin2bcd(tmp);
1abb0dc9 425
be5f59f4
RG
426 switch (ds1307->type) {
427 case ds_1337:
428 case ds_1339:
97f902b7 429 case ds_3231:
1abb0dc9 430 buf[DS1307_REG_MONTH] |= DS1337_BIT_CENTURY;
be5f59f4
RG
431 break;
432 case ds_1340:
1abb0dc9
DB
433 buf[DS1307_REG_HOUR] |= DS1340_BIT_CENTURY_EN
434 | DS1340_BIT_CENTURY;
be5f59f4 435 break;
43fcb815 436 case mcp7941x:
40ce972d
DA
437 /*
438 * these bits were cleared when preparing the date/time
439 * values and need to be set again before writing the
440 * buffer out to the device.
441 */
43fcb815
DA
442 buf[DS1307_REG_SECS] |= MCP7941X_BIT_ST;
443 buf[DS1307_REG_WDAY] |= MCP7941X_BIT_VBATEN;
444 break;
be5f59f4
RG
445 default:
446 break;
447 }
1abb0dc9 448
01a4ca16 449 dev_dbg(dev, "%s: %7ph\n", "write", buf);
1abb0dc9 450
33df2ee1
JT
451 result = ds1307->write_block_data(ds1307->client,
452 ds1307->offset, 7, buf);
fed40b73
BS
453 if (result < 0) {
454 dev_err(dev, "%s error %d\n", "write", result);
455 return result;
1abb0dc9
DB
456 }
457 return 0;
458}
459
74d88eb2 460static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t)
cb49a5e9
RG
461{
462 struct i2c_client *client = to_i2c_client(dev);
463 struct ds1307 *ds1307 = i2c_get_clientdata(client);
464 int ret;
465
466 if (!test_bit(HAS_ALARM, &ds1307->flags))
467 return -EINVAL;
468
469 /* read all ALARM1, ALARM2, and status registers at once */
30e7b039 470 ret = ds1307->read_block_data(client,
fed40b73
BS
471 DS1339_REG_ALARM1_SECS, 9, ds1307->regs);
472 if (ret != 9) {
cb49a5e9
RG
473 dev_err(dev, "%s error %d\n", "alarm read", ret);
474 return -EIO;
475 }
476
477 dev_dbg(dev, "%s: %02x %02x %02x %02x, %02x %02x %02x, %02x %02x\n",
478 "alarm read",
479 ds1307->regs[0], ds1307->regs[1],
480 ds1307->regs[2], ds1307->regs[3],
481 ds1307->regs[4], ds1307->regs[5],
482 ds1307->regs[6], ds1307->regs[7],
483 ds1307->regs[8]);
484
40ce972d
DA
485 /*
486 * report alarm time (ALARM1); assume 24 hour and day-of-month modes,
cb49a5e9
RG
487 * and that all four fields are checked matches
488 */
489 t->time.tm_sec = bcd2bin(ds1307->regs[0] & 0x7f);
490 t->time.tm_min = bcd2bin(ds1307->regs[1] & 0x7f);
491 t->time.tm_hour = bcd2bin(ds1307->regs[2] & 0x3f);
492 t->time.tm_mday = bcd2bin(ds1307->regs[3] & 0x3f);
493 t->time.tm_mon = -1;
494 t->time.tm_year = -1;
495 t->time.tm_wday = -1;
496 t->time.tm_yday = -1;
497 t->time.tm_isdst = -1;
498
499 /* ... and status */
500 t->enabled = !!(ds1307->regs[7] & DS1337_BIT_A1IE);
501 t->pending = !!(ds1307->regs[8] & DS1337_BIT_A1I);
502
503 dev_dbg(dev, "%s secs=%d, mins=%d, "
504 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
505 "alarm read", t->time.tm_sec, t->time.tm_min,
506 t->time.tm_hour, t->time.tm_mday,
507 t->enabled, t->pending);
508
509 return 0;
510}
511
74d88eb2 512static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t)
cb49a5e9 513{
40ce972d 514 struct i2c_client *client = to_i2c_client(dev);
cb49a5e9
RG
515 struct ds1307 *ds1307 = i2c_get_clientdata(client);
516 unsigned char *buf = ds1307->regs;
517 u8 control, status;
518 int ret;
519
520 if (!test_bit(HAS_ALARM, &ds1307->flags))
521 return -EINVAL;
522
523 dev_dbg(dev, "%s secs=%d, mins=%d, "
524 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
525 "alarm set", t->time.tm_sec, t->time.tm_min,
526 t->time.tm_hour, t->time.tm_mday,
527 t->enabled, t->pending);
528
529 /* read current status of both alarms and the chip */
30e7b039 530 ret = ds1307->read_block_data(client,
fed40b73
BS
531 DS1339_REG_ALARM1_SECS, 9, buf);
532 if (ret != 9) {
cb49a5e9
RG
533 dev_err(dev, "%s error %d\n", "alarm write", ret);
534 return -EIO;
535 }
536 control = ds1307->regs[7];
537 status = ds1307->regs[8];
538
539 dev_dbg(dev, "%s: %02x %02x %02x %02x, %02x %02x %02x, %02x %02x\n",
540 "alarm set (old status)",
541 ds1307->regs[0], ds1307->regs[1],
542 ds1307->regs[2], ds1307->regs[3],
543 ds1307->regs[4], ds1307->regs[5],
544 ds1307->regs[6], control, status);
545
546 /* set ALARM1, using 24 hour and day-of-month modes */
cb49a5e9
RG
547 buf[0] = bin2bcd(t->time.tm_sec);
548 buf[1] = bin2bcd(t->time.tm_min);
549 buf[2] = bin2bcd(t->time.tm_hour);
550 buf[3] = bin2bcd(t->time.tm_mday);
551
552 /* set ALARM2 to non-garbage */
553 buf[4] = 0;
554 buf[5] = 0;
555 buf[6] = 0;
556
557 /* optionally enable ALARM1 */
558 buf[7] = control & ~(DS1337_BIT_A1IE | DS1337_BIT_A2IE);
559 if (t->enabled) {
560 dev_dbg(dev, "alarm IRQ armed\n");
561 buf[7] |= DS1337_BIT_A1IE; /* only ALARM1 is used */
562 }
563 buf[8] = status & ~(DS1337_BIT_A1I | DS1337_BIT_A2I);
564
30e7b039 565 ret = ds1307->write_block_data(client,
fed40b73
BS
566 DS1339_REG_ALARM1_SECS, 9, buf);
567 if (ret < 0) {
cb49a5e9 568 dev_err(dev, "can't set alarm time\n");
fed40b73 569 return ret;
cb49a5e9
RG
570 }
571
572 return 0;
573}
574
16380c15 575static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled)
cb49a5e9
RG
576{
577 struct i2c_client *client = to_i2c_client(dev);
578 struct ds1307 *ds1307 = i2c_get_clientdata(client);
579 int ret;
580
16380c15
JS
581 if (!test_bit(HAS_ALARM, &ds1307->flags))
582 return -ENOTTY;
cb49a5e9 583
16380c15
JS
584 ret = i2c_smbus_read_byte_data(client, DS1337_REG_CONTROL);
585 if (ret < 0)
586 return ret;
cb49a5e9 587
16380c15 588 if (enabled)
cb49a5e9 589 ret |= DS1337_BIT_A1IE;
16380c15
JS
590 else
591 ret &= ~DS1337_BIT_A1IE;
cb49a5e9 592
16380c15
JS
593 ret = i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL, ret);
594 if (ret < 0)
595 return ret;
cb49a5e9
RG
596
597 return 0;
598}
599
ff8371ac 600static const struct rtc_class_ops ds13xx_rtc_ops = {
1abb0dc9
DB
601 .read_time = ds1307_get_time,
602 .set_time = ds1307_set_time,
74d88eb2
JR
603 .read_alarm = ds1337_read_alarm,
604 .set_alarm = ds1337_set_alarm,
16380c15 605 .alarm_irq_enable = ds1307_alarm_irq_enable,
1abb0dc9
DB
606};
607
682d73f6
DB
608/*----------------------------------------------------------------------*/
609
1d1945d2
SG
610/*
611 * Alarm support for mcp7941x devices.
612 */
613
614#define MCP7941X_REG_CONTROL 0x07
615# define MCP7941X_BIT_ALM0_EN 0x10
616# define MCP7941X_BIT_ALM1_EN 0x20
617#define MCP7941X_REG_ALARM0_BASE 0x0a
618#define MCP7941X_REG_ALARM0_CTRL 0x0d
619#define MCP7941X_REG_ALARM1_BASE 0x11
620#define MCP7941X_REG_ALARM1_CTRL 0x14
621# define MCP7941X_BIT_ALMX_IF (1 << 3)
622# define MCP7941X_BIT_ALMX_C0 (1 << 4)
623# define MCP7941X_BIT_ALMX_C1 (1 << 5)
624# define MCP7941X_BIT_ALMX_C2 (1 << 6)
625# define MCP7941X_BIT_ALMX_POL (1 << 7)
626# define MCP7941X_MSK_ALMX_MATCH (MCP7941X_BIT_ALMX_C0 | \
627 MCP7941X_BIT_ALMX_C1 | \
628 MCP7941X_BIT_ALMX_C2)
629
630static void mcp7941x_work(struct work_struct *work)
631{
632 struct ds1307 *ds1307 = container_of(work, struct ds1307, work);
633 struct i2c_client *client = ds1307->client;
634 int reg, ret;
635
636 mutex_lock(&ds1307->rtc->ops_lock);
637
638 /* Check and clear alarm 0 interrupt flag. */
639 reg = i2c_smbus_read_byte_data(client, MCP7941X_REG_ALARM0_CTRL);
640 if (reg < 0)
641 goto out;
642 if (!(reg & MCP7941X_BIT_ALMX_IF))
643 goto out;
644 reg &= ~MCP7941X_BIT_ALMX_IF;
645 ret = i2c_smbus_write_byte_data(client, MCP7941X_REG_ALARM0_CTRL, reg);
646 if (ret < 0)
647 goto out;
648
649 /* Disable alarm 0. */
650 reg = i2c_smbus_read_byte_data(client, MCP7941X_REG_CONTROL);
651 if (reg < 0)
652 goto out;
653 reg &= ~MCP7941X_BIT_ALM0_EN;
654 ret = i2c_smbus_write_byte_data(client, MCP7941X_REG_CONTROL, reg);
655 if (ret < 0)
656 goto out;
657
658 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
659
660out:
661 if (test_bit(HAS_ALARM, &ds1307->flags))
662 enable_irq(client->irq);
663 mutex_unlock(&ds1307->rtc->ops_lock);
664}
665
666static int mcp7941x_read_alarm(struct device *dev, struct rtc_wkalrm *t)
667{
668 struct i2c_client *client = to_i2c_client(dev);
669 struct ds1307 *ds1307 = i2c_get_clientdata(client);
670 u8 *regs = ds1307->regs;
671 int ret;
672
673 if (!test_bit(HAS_ALARM, &ds1307->flags))
674 return -EINVAL;
675
676 /* Read control and alarm 0 registers. */
677 ret = ds1307->read_block_data(client, MCP7941X_REG_CONTROL, 10, regs);
678 if (ret < 0)
679 return ret;
680
681 t->enabled = !!(regs[0] & MCP7941X_BIT_ALM0_EN);
682
683 /* Report alarm 0 time assuming 24-hour and day-of-month modes. */
684 t->time.tm_sec = bcd2bin(ds1307->regs[3] & 0x7f);
685 t->time.tm_min = bcd2bin(ds1307->regs[4] & 0x7f);
686 t->time.tm_hour = bcd2bin(ds1307->regs[5] & 0x3f);
687 t->time.tm_wday = bcd2bin(ds1307->regs[6] & 0x7) - 1;
688 t->time.tm_mday = bcd2bin(ds1307->regs[7] & 0x3f);
689 t->time.tm_mon = bcd2bin(ds1307->regs[8] & 0x1f) - 1;
690 t->time.tm_year = -1;
691 t->time.tm_yday = -1;
692 t->time.tm_isdst = -1;
693
694 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
695 "enabled=%d polarity=%d irq=%d match=%d\n", __func__,
696 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
697 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled,
698 !!(ds1307->regs[6] & MCP7941X_BIT_ALMX_POL),
699 !!(ds1307->regs[6] & MCP7941X_BIT_ALMX_IF),
700 (ds1307->regs[6] & MCP7941X_MSK_ALMX_MATCH) >> 4);
701
702 return 0;
703}
704
705static int mcp7941x_set_alarm(struct device *dev, struct rtc_wkalrm *t)
706{
707 struct i2c_client *client = to_i2c_client(dev);
708 struct ds1307 *ds1307 = i2c_get_clientdata(client);
709 unsigned char *regs = ds1307->regs;
710 int ret;
711
712 if (!test_bit(HAS_ALARM, &ds1307->flags))
713 return -EINVAL;
714
715 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
716 "enabled=%d pending=%d\n", __func__,
717 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
718 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
719 t->enabled, t->pending);
720
721 /* Read control and alarm 0 registers. */
722 ret = ds1307->read_block_data(client, MCP7941X_REG_CONTROL, 10, regs);
723 if (ret < 0)
724 return ret;
725
726 /* Set alarm 0, using 24-hour and day-of-month modes. */
727 regs[3] = bin2bcd(t->time.tm_sec);
728 regs[4] = bin2bcd(t->time.tm_min);
729 regs[5] = bin2bcd(t->time.tm_hour);
730 regs[6] = bin2bcd(t->time.tm_wday) + 1;
731 regs[7] = bin2bcd(t->time.tm_mday);
732 regs[8] = bin2bcd(t->time.tm_mon) + 1;
733
734 /* Clear the alarm 0 interrupt flag. */
735 regs[6] &= ~MCP7941X_BIT_ALMX_IF;
736 /* Set alarm match: second, minute, hour, day, date, month. */
737 regs[6] |= MCP7941X_MSK_ALMX_MATCH;
738
739 if (t->enabled)
740 regs[0] |= MCP7941X_BIT_ALM0_EN;
741 else
742 regs[0] &= ~MCP7941X_BIT_ALM0_EN;
743
744 ret = ds1307->write_block_data(client, MCP7941X_REG_CONTROL, 10, regs);
745 if (ret < 0)
746 return ret;
747
748 return 0;
749}
750
751static int mcp7941x_alarm_irq_enable(struct device *dev, unsigned int enabled)
752{
753 struct i2c_client *client = to_i2c_client(dev);
754 struct ds1307 *ds1307 = i2c_get_clientdata(client);
755 int reg;
756
757 if (!test_bit(HAS_ALARM, &ds1307->flags))
758 return -EINVAL;
759
760 reg = i2c_smbus_read_byte_data(client, MCP7941X_REG_CONTROL);
761 if (reg < 0)
762 return reg;
763
764 if (enabled)
765 reg |= MCP7941X_BIT_ALM0_EN;
766 else
767 reg &= ~MCP7941X_BIT_ALM0_EN;
768
769 return i2c_smbus_write_byte_data(client, MCP7941X_REG_CONTROL, reg);
770}
771
772static const struct rtc_class_ops mcp7941x_rtc_ops = {
773 .read_time = ds1307_get_time,
774 .set_time = ds1307_set_time,
775 .read_alarm = mcp7941x_read_alarm,
776 .set_alarm = mcp7941x_set_alarm,
777 .alarm_irq_enable = mcp7941x_alarm_irq_enable,
778};
779
780/*----------------------------------------------------------------------*/
781
682d73f6 782static ssize_t
2c3c8bea
CW
783ds1307_nvram_read(struct file *filp, struct kobject *kobj,
784 struct bin_attribute *attr,
682d73f6
DB
785 char *buf, loff_t off, size_t count)
786{
787 struct i2c_client *client;
788 struct ds1307 *ds1307;
682d73f6
DB
789 int result;
790
fcd8db00 791 client = kobj_to_i2c_client(kobj);
682d73f6
DB
792 ds1307 = i2c_get_clientdata(client);
793
9eab0a78 794 if (unlikely(off >= ds1307->nvram->size))
682d73f6 795 return 0;
9eab0a78
AB
796 if ((off + count) > ds1307->nvram->size)
797 count = ds1307->nvram->size - off;
682d73f6
DB
798 if (unlikely(!count))
799 return count;
800
9eab0a78
AB
801 result = ds1307->read_block_data(client, ds1307->nvram_offset + off,
802 count, buf);
fed40b73 803 if (result < 0)
682d73f6 804 dev_err(&client->dev, "%s error %d\n", "nvram read", result);
fed40b73 805 return result;
682d73f6
DB
806}
807
808static ssize_t
2c3c8bea
CW
809ds1307_nvram_write(struct file *filp, struct kobject *kobj,
810 struct bin_attribute *attr,
682d73f6
DB
811 char *buf, loff_t off, size_t count)
812{
813 struct i2c_client *client;
30e7b039 814 struct ds1307 *ds1307;
fed40b73 815 int result;
682d73f6 816
fcd8db00 817 client = kobj_to_i2c_client(kobj);
30e7b039 818 ds1307 = i2c_get_clientdata(client);
682d73f6 819
9eab0a78 820 if (unlikely(off >= ds1307->nvram->size))
682d73f6 821 return -EFBIG;
9eab0a78
AB
822 if ((off + count) > ds1307->nvram->size)
823 count = ds1307->nvram->size - off;
682d73f6
DB
824 if (unlikely(!count))
825 return count;
826
9eab0a78
AB
827 result = ds1307->write_block_data(client, ds1307->nvram_offset + off,
828 count, buf);
fed40b73
BS
829 if (result < 0) {
830 dev_err(&client->dev, "%s error %d\n", "nvram write", result);
831 return result;
832 }
833 return count;
682d73f6
DB
834}
835
682d73f6
DB
836/*----------------------------------------------------------------------*/
837
5a167f45
GKH
838static int ds1307_probe(struct i2c_client *client,
839 const struct i2c_device_id *id)
1abb0dc9
DB
840{
841 struct ds1307 *ds1307;
842 int err = -ENODEV;
1abb0dc9 843 int tmp;
3760f736 844 const struct chip_desc *chip = &chips[id->driver_data];
c065f35c 845 struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
c8b18da7 846 bool want_irq = false;
fed40b73 847 unsigned char *buf;
01ce893d 848 struct ds1307_platform_data *pdata = dev_get_platdata(&client->dev);
97f902b7
WS
849 static const int bbsqi_bitpos[] = {
850 [ds_1337] = 0,
851 [ds_1339] = DS1339_BIT_BBSQI,
852 [ds_3231] = DS3231_BIT_BBSQW,
853 };
1d1945d2 854 const struct rtc_class_ops *rtc_ops = &ds13xx_rtc_ops;
1abb0dc9 855
30e7b039
ES
856 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)
857 && !i2c_check_functionality(adapter, I2C_FUNC_SMBUS_I2C_BLOCK))
c065f35c
DB
858 return -EIO;
859
edca66d2 860 ds1307 = devm_kzalloc(&client->dev, sizeof(struct ds1307), GFP_KERNEL);
40ce972d 861 if (!ds1307)
c065f35c 862 return -ENOMEM;
045e0e85 863
1abb0dc9 864 i2c_set_clientdata(client, ds1307);
33df2ee1
JT
865
866 ds1307->client = client;
867 ds1307->type = id->driver_data;
33df2ee1 868
eb86c306
WS
869 if (pdata && pdata->trickle_charger_setup && chip->trickle_charger_reg)
870 i2c_smbus_write_byte_data(client, chip->trickle_charger_reg,
871 DS13XX_TRICKLE_CHARGER_MAGIC | pdata->trickle_charger_setup);
872
fed40b73 873 buf = ds1307->regs;
30e7b039 874 if (i2c_check_functionality(adapter, I2C_FUNC_SMBUS_I2C_BLOCK)) {
bc48b902
BA
875 ds1307->read_block_data = ds1307_native_smbus_read_block_data;
876 ds1307->write_block_data = ds1307_native_smbus_write_block_data;
30e7b039
ES
877 } else {
878 ds1307->read_block_data = ds1307_read_block_data;
879 ds1307->write_block_data = ds1307_write_block_data;
880 }
045e0e85
DB
881
882 switch (ds1307->type) {
883 case ds_1337:
884 case ds_1339:
97f902b7 885 case ds_3231:
be5f59f4 886 /* get registers that the "rtc" read below won't read... */
30e7b039 887 tmp = ds1307->read_block_data(ds1307->client,
fed40b73 888 DS1337_REG_CONTROL, 2, buf);
1abb0dc9 889 if (tmp != 2) {
6df80e21 890 dev_dbg(&client->dev, "read error %d\n", tmp);
1abb0dc9 891 err = -EIO;
edca66d2 892 goto exit;
1abb0dc9
DB
893 }
894
be5f59f4
RG
895 /* oscillator off? turn it on, so clock can tick. */
896 if (ds1307->regs[0] & DS1337_BIT_nEOSC)
cb49a5e9
RG
897 ds1307->regs[0] &= ~DS1337_BIT_nEOSC;
898
40ce972d
DA
899 /*
900 * Using IRQ? Disable the square wave and both alarms.
97f902b7
WS
901 * For some variants, be sure alarms can trigger when we're
902 * running on Vbackup (BBSQI/BBSQW)
cb49a5e9 903 */
b24a7267
WS
904 if (ds1307->client->irq > 0 && chip->alarm) {
905 INIT_WORK(&ds1307->work, ds1307_work);
906
97f902b7
WS
907 ds1307->regs[0] |= DS1337_BIT_INTCN
908 | bbsqi_bitpos[ds1307->type];
cb49a5e9 909 ds1307->regs[0] &= ~(DS1337_BIT_A2IE | DS1337_BIT_A1IE);
b24a7267
WS
910
911 want_irq = true;
cb49a5e9
RG
912 }
913
914 i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL,
915 ds1307->regs[0]);
be5f59f4
RG
916
917 /* oscillator fault? clear flag, and warn */
918 if (ds1307->regs[1] & DS1337_BIT_OSF) {
919 i2c_smbus_write_byte_data(client, DS1337_REG_STATUS,
920 ds1307->regs[1] & ~DS1337_BIT_OSF);
921 dev_warn(&client->dev, "SET TIME!\n");
1abb0dc9 922 }
045e0e85 923 break;
a2166858
MF
924
925 case rx_8025:
926 tmp = i2c_smbus_read_i2c_block_data(ds1307->client,
927 RX8025_REG_CTRL1 << 4 | 0x08, 2, buf);
928 if (tmp != 2) {
6df80e21 929 dev_dbg(&client->dev, "read error %d\n", tmp);
a2166858 930 err = -EIO;
edca66d2 931 goto exit;
a2166858
MF
932 }
933
934 /* oscillator off? turn it on, so clock can tick. */
935 if (!(ds1307->regs[1] & RX8025_BIT_XST)) {
936 ds1307->regs[1] |= RX8025_BIT_XST;
937 i2c_smbus_write_byte_data(client,
938 RX8025_REG_CTRL2 << 4 | 0x08,
939 ds1307->regs[1]);
940 dev_warn(&client->dev,
941 "oscillator stop detected - SET TIME!\n");
942 }
943
944 if (ds1307->regs[1] & RX8025_BIT_PON) {
945 ds1307->regs[1] &= ~RX8025_BIT_PON;
946 i2c_smbus_write_byte_data(client,
947 RX8025_REG_CTRL2 << 4 | 0x08,
948 ds1307->regs[1]);
949 dev_warn(&client->dev, "power-on detected\n");
950 }
951
952 if (ds1307->regs[1] & RX8025_BIT_VDET) {
953 ds1307->regs[1] &= ~RX8025_BIT_VDET;
954 i2c_smbus_write_byte_data(client,
955 RX8025_REG_CTRL2 << 4 | 0x08,
956 ds1307->regs[1]);
957 dev_warn(&client->dev, "voltage drop detected\n");
958 }
959
960 /* make sure we are running in 24hour mode */
961 if (!(ds1307->regs[0] & RX8025_BIT_2412)) {
962 u8 hour;
963
964 /* switch to 24 hour mode */
965 i2c_smbus_write_byte_data(client,
966 RX8025_REG_CTRL1 << 4 | 0x08,
967 ds1307->regs[0] |
968 RX8025_BIT_2412);
969
970 tmp = i2c_smbus_read_i2c_block_data(ds1307->client,
971 RX8025_REG_CTRL1 << 4 | 0x08, 2, buf);
972 if (tmp != 2) {
6df80e21 973 dev_dbg(&client->dev, "read error %d\n", tmp);
a2166858 974 err = -EIO;
edca66d2 975 goto exit;
a2166858
MF
976 }
977
978 /* correct hour */
979 hour = bcd2bin(ds1307->regs[DS1307_REG_HOUR]);
980 if (hour == 12)
981 hour = 0;
982 if (ds1307->regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
983 hour += 12;
984
985 i2c_smbus_write_byte_data(client,
986 DS1307_REG_HOUR << 4 | 0x08,
987 hour);
988 }
989 break;
33df2ee1
JT
990 case ds_1388:
991 ds1307->offset = 1; /* Seconds starts at 1 */
992 break;
1d1945d2
SG
993 case mcp7941x:
994 rtc_ops = &mcp7941x_rtc_ops;
995 if (ds1307->client->irq > 0 && chip->alarm) {
996 INIT_WORK(&ds1307->work, mcp7941x_work);
997 want_irq = true;
998 }
999 break;
045e0e85
DB
1000 default:
1001 break;
1002 }
1abb0dc9
DB
1003
1004read_rtc:
1005 /* read RTC registers */
96fc3a45 1006 tmp = ds1307->read_block_data(ds1307->client, ds1307->offset, 8, buf);
fed40b73 1007 if (tmp != 8) {
6df80e21 1008 dev_dbg(&client->dev, "read error %d\n", tmp);
1abb0dc9 1009 err = -EIO;
edca66d2 1010 goto exit;
1abb0dc9
DB
1011 }
1012
40ce972d
DA
1013 /*
1014 * minimal sanity checking; some chips (like DS1340) don't
1abb0dc9
DB
1015 * specify the extra bits as must-be-zero, but there are
1016 * still a few values that are clearly out-of-range.
1017 */
1018 tmp = ds1307->regs[DS1307_REG_SECS];
045e0e85
DB
1019 switch (ds1307->type) {
1020 case ds_1307:
045e0e85 1021 case m41t00:
be5f59f4 1022 /* clock halted? turn it on, so clock can tick. */
045e0e85 1023 if (tmp & DS1307_BIT_CH) {
be5f59f4
RG
1024 i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0);
1025 dev_warn(&client->dev, "SET TIME!\n");
045e0e85 1026 goto read_rtc;
1abb0dc9 1027 }
045e0e85 1028 break;
be5f59f4
RG
1029 case ds_1338:
1030 /* clock halted? turn it on, so clock can tick. */
045e0e85 1031 if (tmp & DS1307_BIT_CH)
be5f59f4
RG
1032 i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0);
1033
1034 /* oscillator fault? clear flag, and warn */
1035 if (ds1307->regs[DS1307_REG_CONTROL] & DS1338_BIT_OSF) {
1036 i2c_smbus_write_byte_data(client, DS1307_REG_CONTROL,
bd16f9eb 1037 ds1307->regs[DS1307_REG_CONTROL]
be5f59f4
RG
1038 & ~DS1338_BIT_OSF);
1039 dev_warn(&client->dev, "SET TIME!\n");
1040 goto read_rtc;
1041 }
045e0e85 1042 break;
fcd8db00
R
1043 case ds_1340:
1044 /* clock halted? turn it on, so clock can tick. */
1045 if (tmp & DS1340_BIT_nEOSC)
1046 i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0);
1047
1048 tmp = i2c_smbus_read_byte_data(client, DS1340_REG_FLAG);
1049 if (tmp < 0) {
6df80e21 1050 dev_dbg(&client->dev, "read error %d\n", tmp);
fcd8db00 1051 err = -EIO;
edca66d2 1052 goto exit;
fcd8db00
R
1053 }
1054
1055 /* oscillator fault? clear flag, and warn */
1056 if (tmp & DS1340_BIT_OSF) {
1057 i2c_smbus_write_byte_data(client, DS1340_REG_FLAG, 0);
1058 dev_warn(&client->dev, "SET TIME!\n");
1059 }
43fcb815
DA
1060 break;
1061 case mcp7941x:
1062 /* make sure that the backup battery is enabled */
1063 if (!(ds1307->regs[DS1307_REG_WDAY] & MCP7941X_BIT_VBATEN)) {
1064 i2c_smbus_write_byte_data(client, DS1307_REG_WDAY,
1065 ds1307->regs[DS1307_REG_WDAY]
1066 | MCP7941X_BIT_VBATEN);
1067 }
1068
1069 /* clock halted? turn it on, so clock can tick. */
1070 if (!(tmp & MCP7941X_BIT_ST)) {
1071 i2c_smbus_write_byte_data(client, DS1307_REG_SECS,
1072 MCP7941X_BIT_ST);
1073 dev_warn(&client->dev, "SET TIME!\n");
1074 goto read_rtc;
1075 }
1076
fcd8db00 1077 break;
32d322bc 1078 default:
045e0e85 1079 break;
1abb0dc9 1080 }
045e0e85 1081
1abb0dc9 1082 tmp = ds1307->regs[DS1307_REG_HOUR];
c065f35c
DB
1083 switch (ds1307->type) {
1084 case ds_1340:
1085 case m41t00:
40ce972d
DA
1086 /*
1087 * NOTE: ignores century bits; fix before deploying
c065f35c
DB
1088 * systems that will run through year 2100.
1089 */
1090 break;
a2166858
MF
1091 case rx_8025:
1092 break;
c065f35c
DB
1093 default:
1094 if (!(tmp & DS1307_BIT_12HR))
1095 break;
1096
40ce972d
DA
1097 /*
1098 * Be sure we're in 24 hour mode. Multi-master systems
c065f35c
DB
1099 * take note...
1100 */
fe20ba70 1101 tmp = bcd2bin(tmp & 0x1f);
c065f35c
DB
1102 if (tmp == 12)
1103 tmp = 0;
1104 if (ds1307->regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
1105 tmp += 12;
1abb0dc9 1106 i2c_smbus_write_byte_data(client,
96fc3a45 1107 ds1307->offset + DS1307_REG_HOUR,
fe20ba70 1108 bin2bcd(tmp));
1abb0dc9
DB
1109 }
1110
5ea73514 1111 device_set_wakeup_capable(&client->dev, want_irq);
edca66d2 1112 ds1307->rtc = devm_rtc_device_register(&client->dev, client->name,
1d1945d2 1113 rtc_ops, THIS_MODULE);
1abb0dc9 1114 if (IS_ERR(ds1307->rtc)) {
4071ea25 1115 return PTR_ERR(ds1307->rtc);
1abb0dc9
DB
1116 }
1117
cb49a5e9 1118 if (want_irq) {
43d15bcd 1119 err = request_irq(client->irq, ds1307_irq, IRQF_SHARED,
cb49a5e9
RG
1120 ds1307->rtc->name, client);
1121 if (err) {
4071ea25
AZ
1122 client->irq = 0;
1123 dev_err(&client->dev, "unable to request IRQ!\n");
1124 } else {
26b3c01f 1125
4071ea25
AZ
1126 set_bit(HAS_ALARM, &ds1307->flags);
1127 dev_dbg(&client->dev, "got IRQ %d\n", client->irq);
1128 }
cb49a5e9
RG
1129 }
1130
9eab0a78 1131 if (chip->nvram_size) {
4071ea25 1132
edca66d2
JH
1133 ds1307->nvram = devm_kzalloc(&client->dev,
1134 sizeof(struct bin_attribute),
1135 GFP_KERNEL);
9eab0a78 1136 if (!ds1307->nvram) {
4071ea25
AZ
1137 dev_err(&client->dev, "cannot allocate memory for nvram sysfs\n");
1138 } else {
1139
1140 ds1307->nvram->attr.name = "nvram";
1141 ds1307->nvram->attr.mode = S_IRUGO | S_IWUSR;
1142
1143 sysfs_bin_attr_init(ds1307->nvram);
1144
1145 ds1307->nvram->read = ds1307_nvram_read;
1146 ds1307->nvram->write = ds1307_nvram_write;
1147 ds1307->nvram->size = chip->nvram_size;
1148 ds1307->nvram_offset = chip->nvram_offset;
1149
1150 err = sysfs_create_bin_file(&client->dev.kobj,
1151 ds1307->nvram);
1152 if (err) {
1153 dev_err(&client->dev,
1154 "unable to create sysfs file: %s\n",
1155 ds1307->nvram->attr.name);
1156 } else {
1157 set_bit(HAS_NVRAM, &ds1307->flags);
1158 dev_info(&client->dev, "%zu bytes nvram\n",
1159 ds1307->nvram->size);
1160 }
9eab0a78 1161 }
682d73f6
DB
1162 }
1163
1abb0dc9
DB
1164 return 0;
1165
edca66d2 1166exit:
1abb0dc9
DB
1167 return err;
1168}
1169
5a167f45 1170static int ds1307_remove(struct i2c_client *client)
1abb0dc9 1171{
40ce972d 1172 struct ds1307 *ds1307 = i2c_get_clientdata(client);
cb49a5e9
RG
1173
1174 if (test_and_clear_bit(HAS_ALARM, &ds1307->flags)) {
1175 free_irq(client->irq, client);
1176 cancel_work_sync(&ds1307->work);
1177 }
1abb0dc9 1178
edca66d2 1179 if (test_and_clear_bit(HAS_NVRAM, &ds1307->flags))
9eab0a78 1180 sysfs_remove_bin_file(&client->dev.kobj, ds1307->nvram);
682d73f6 1181
1abb0dc9
DB
1182 return 0;
1183}
1184
1185static struct i2c_driver ds1307_driver = {
1186 .driver = {
c065f35c 1187 .name = "rtc-ds1307",
1abb0dc9
DB
1188 .owner = THIS_MODULE,
1189 },
c065f35c 1190 .probe = ds1307_probe,
5a167f45 1191 .remove = ds1307_remove,
3760f736 1192 .id_table = ds1307_id,
1abb0dc9
DB
1193};
1194
0abc9201 1195module_i2c_driver(ds1307_driver);
1abb0dc9
DB
1196
1197MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips");
1198MODULE_LICENSE("GPL");
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