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d00ed3cf DM |
1 | /* |
2 | * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved. | |
3 | * | |
4 | * The code contained herein is licensed under the GNU General Public | |
5 | * License. You may obtain a copy of the GNU General Public License | |
6 | * Version 2 or later at the following locations: | |
7 | * | |
8 | * http://www.opensource.org/licenses/gpl-license.html | |
9 | * http://www.gnu.org/copyleft/gpl.html | |
10 | */ | |
11 | ||
12 | #include <linux/io.h> | |
13 | #include <linux/rtc.h> | |
14 | #include <linux/module.h> | |
5a0e3ad6 | 15 | #include <linux/slab.h> |
d00ed3cf DM |
16 | #include <linux/interrupt.h> |
17 | #include <linux/platform_device.h> | |
18 | #include <linux/clk.h> | |
19 | ||
d00ed3cf DM |
20 | #define RTC_INPUT_CLK_32768HZ (0x00 << 5) |
21 | #define RTC_INPUT_CLK_32000HZ (0x01 << 5) | |
22 | #define RTC_INPUT_CLK_38400HZ (0x02 << 5) | |
23 | ||
24 | #define RTC_SW_BIT (1 << 0) | |
25 | #define RTC_ALM_BIT (1 << 2) | |
26 | #define RTC_1HZ_BIT (1 << 4) | |
27 | #define RTC_2HZ_BIT (1 << 7) | |
28 | #define RTC_SAM0_BIT (1 << 8) | |
29 | #define RTC_SAM1_BIT (1 << 9) | |
30 | #define RTC_SAM2_BIT (1 << 10) | |
31 | #define RTC_SAM3_BIT (1 << 11) | |
32 | #define RTC_SAM4_BIT (1 << 12) | |
33 | #define RTC_SAM5_BIT (1 << 13) | |
34 | #define RTC_SAM6_BIT (1 << 14) | |
35 | #define RTC_SAM7_BIT (1 << 15) | |
36 | #define PIT_ALL_ON (RTC_2HZ_BIT | RTC_SAM0_BIT | RTC_SAM1_BIT | \ | |
37 | RTC_SAM2_BIT | RTC_SAM3_BIT | RTC_SAM4_BIT | \ | |
38 | RTC_SAM5_BIT | RTC_SAM6_BIT | RTC_SAM7_BIT) | |
39 | ||
40 | #define RTC_ENABLE_BIT (1 << 7) | |
41 | ||
42 | #define MAX_PIE_NUM 9 | |
43 | #define MAX_PIE_FREQ 512 | |
44 | static const u32 PIE_BIT_DEF[MAX_PIE_NUM][2] = { | |
45 | { 2, RTC_2HZ_BIT }, | |
46 | { 4, RTC_SAM0_BIT }, | |
47 | { 8, RTC_SAM1_BIT }, | |
48 | { 16, RTC_SAM2_BIT }, | |
49 | { 32, RTC_SAM3_BIT }, | |
50 | { 64, RTC_SAM4_BIT }, | |
51 | { 128, RTC_SAM5_BIT }, | |
52 | { 256, RTC_SAM6_BIT }, | |
53 | { MAX_PIE_FREQ, RTC_SAM7_BIT }, | |
54 | }; | |
55 | ||
d00ed3cf DM |
56 | #define MXC_RTC_TIME 0 |
57 | #define MXC_RTC_ALARM 1 | |
58 | ||
59 | #define RTC_HOURMIN 0x00 /* 32bit rtc hour/min counter reg */ | |
60 | #define RTC_SECOND 0x04 /* 32bit rtc seconds counter reg */ | |
61 | #define RTC_ALRM_HM 0x08 /* 32bit rtc alarm hour/min reg */ | |
62 | #define RTC_ALRM_SEC 0x0C /* 32bit rtc alarm seconds reg */ | |
63 | #define RTC_RTCCTL 0x10 /* 32bit rtc control reg */ | |
64 | #define RTC_RTCISR 0x14 /* 32bit rtc interrupt status reg */ | |
65 | #define RTC_RTCIENR 0x18 /* 32bit rtc interrupt enable reg */ | |
66 | #define RTC_STPWCH 0x1C /* 32bit rtc stopwatch min reg */ | |
67 | #define RTC_DAYR 0x20 /* 32bit rtc days counter reg */ | |
68 | #define RTC_DAYALARM 0x24 /* 32bit rtc day alarm reg */ | |
69 | #define RTC_TEST1 0x28 /* 32bit rtc test reg 1 */ | |
70 | #define RTC_TEST2 0x2C /* 32bit rtc test reg 2 */ | |
71 | #define RTC_TEST3 0x30 /* 32bit rtc test reg 3 */ | |
72 | ||
bb1d34a2 SG |
73 | enum imx_rtc_type { |
74 | IMX1_RTC, | |
75 | IMX21_RTC, | |
76 | }; | |
77 | ||
d00ed3cf DM |
78 | struct rtc_plat_data { |
79 | struct rtc_device *rtc; | |
80 | void __iomem *ioaddr; | |
81 | int irq; | |
82 | struct clk *clk; | |
d00ed3cf | 83 | struct rtc_time g_rtc_alarm; |
bb1d34a2 | 84 | enum imx_rtc_type devtype; |
d00ed3cf DM |
85 | }; |
86 | ||
bb1d34a2 SG |
87 | static struct platform_device_id imx_rtc_devtype[] = { |
88 | { | |
89 | .name = "imx1-rtc", | |
90 | .driver_data = IMX1_RTC, | |
91 | }, { | |
92 | .name = "imx21-rtc", | |
93 | .driver_data = IMX21_RTC, | |
94 | }, { | |
95 | /* sentinel */ | |
96 | } | |
97 | }; | |
98 | MODULE_DEVICE_TABLE(platform, imx_rtc_devtype); | |
99 | ||
100 | static inline int is_imx1_rtc(struct rtc_plat_data *data) | |
101 | { | |
102 | return data->devtype == IMX1_RTC; | |
103 | } | |
104 | ||
d00ed3cf DM |
105 | /* |
106 | * This function is used to obtain the RTC time or the alarm value in | |
107 | * second. | |
108 | */ | |
109 | static u32 get_alarm_or_time(struct device *dev, int time_alarm) | |
110 | { | |
111 | struct platform_device *pdev = to_platform_device(dev); | |
112 | struct rtc_plat_data *pdata = platform_get_drvdata(pdev); | |
113 | void __iomem *ioaddr = pdata->ioaddr; | |
114 | u32 day = 0, hr = 0, min = 0, sec = 0, hr_min = 0; | |
115 | ||
116 | switch (time_alarm) { | |
117 | case MXC_RTC_TIME: | |
118 | day = readw(ioaddr + RTC_DAYR); | |
119 | hr_min = readw(ioaddr + RTC_HOURMIN); | |
120 | sec = readw(ioaddr + RTC_SECOND); | |
121 | break; | |
122 | case MXC_RTC_ALARM: | |
123 | day = readw(ioaddr + RTC_DAYALARM); | |
124 | hr_min = readw(ioaddr + RTC_ALRM_HM) & 0xffff; | |
125 | sec = readw(ioaddr + RTC_ALRM_SEC); | |
126 | break; | |
127 | } | |
128 | ||
129 | hr = hr_min >> 8; | |
130 | min = hr_min & 0xff; | |
131 | ||
132 | return (((day * 24 + hr) * 60) + min) * 60 + sec; | |
133 | } | |
134 | ||
135 | /* | |
136 | * This function sets the RTC alarm value or the time value. | |
137 | */ | |
138 | static void set_alarm_or_time(struct device *dev, int time_alarm, u32 time) | |
139 | { | |
140 | u32 day, hr, min, sec, temp; | |
141 | struct platform_device *pdev = to_platform_device(dev); | |
142 | struct rtc_plat_data *pdata = platform_get_drvdata(pdev); | |
143 | void __iomem *ioaddr = pdata->ioaddr; | |
144 | ||
145 | day = time / 86400; | |
146 | time -= day * 86400; | |
147 | ||
148 | /* time is within a day now */ | |
149 | hr = time / 3600; | |
150 | time -= hr * 3600; | |
151 | ||
152 | /* time is within an hour now */ | |
153 | min = time / 60; | |
154 | sec = time - min * 60; | |
155 | ||
156 | temp = (hr << 8) + min; | |
157 | ||
158 | switch (time_alarm) { | |
159 | case MXC_RTC_TIME: | |
160 | writew(day, ioaddr + RTC_DAYR); | |
161 | writew(sec, ioaddr + RTC_SECOND); | |
162 | writew(temp, ioaddr + RTC_HOURMIN); | |
163 | break; | |
164 | case MXC_RTC_ALARM: | |
165 | writew(day, ioaddr + RTC_DAYALARM); | |
166 | writew(sec, ioaddr + RTC_ALRM_SEC); | |
167 | writew(temp, ioaddr + RTC_ALRM_HM); | |
168 | break; | |
169 | } | |
170 | } | |
171 | ||
172 | /* | |
173 | * This function updates the RTC alarm registers and then clears all the | |
174 | * interrupt status bits. | |
175 | */ | |
176 | static int rtc_update_alarm(struct device *dev, struct rtc_time *alrm) | |
177 | { | |
178 | struct rtc_time alarm_tm, now_tm; | |
179 | unsigned long now, time; | |
d00ed3cf DM |
180 | struct platform_device *pdev = to_platform_device(dev); |
181 | struct rtc_plat_data *pdata = platform_get_drvdata(pdev); | |
182 | void __iomem *ioaddr = pdata->ioaddr; | |
183 | ||
184 | now = get_alarm_or_time(dev, MXC_RTC_TIME); | |
185 | rtc_time_to_tm(now, &now_tm); | |
186 | alarm_tm.tm_year = now_tm.tm_year; | |
187 | alarm_tm.tm_mon = now_tm.tm_mon; | |
188 | alarm_tm.tm_mday = now_tm.tm_mday; | |
189 | alarm_tm.tm_hour = alrm->tm_hour; | |
190 | alarm_tm.tm_min = alrm->tm_min; | |
191 | alarm_tm.tm_sec = alrm->tm_sec; | |
d00ed3cf DM |
192 | rtc_tm_to_time(&alarm_tm, &time); |
193 | ||
d00ed3cf DM |
194 | /* clear all the interrupt status bits */ |
195 | writew(readw(ioaddr + RTC_RTCISR), ioaddr + RTC_RTCISR); | |
196 | set_alarm_or_time(dev, MXC_RTC_ALARM, time); | |
197 | ||
c92182ee YK |
198 | return 0; |
199 | } | |
200 | ||
201 | static void mxc_rtc_irq_enable(struct device *dev, unsigned int bit, | |
202 | unsigned int enabled) | |
203 | { | |
204 | struct platform_device *pdev = to_platform_device(dev); | |
205 | struct rtc_plat_data *pdata = platform_get_drvdata(pdev); | |
206 | void __iomem *ioaddr = pdata->ioaddr; | |
207 | u32 reg; | |
208 | ||
209 | spin_lock_irq(&pdata->rtc->irq_lock); | |
210 | reg = readw(ioaddr + RTC_RTCIENR); | |
211 | ||
212 | if (enabled) | |
213 | reg |= bit; | |
214 | else | |
215 | reg &= ~bit; | |
216 | ||
217 | writew(reg, ioaddr + RTC_RTCIENR); | |
218 | spin_unlock_irq(&pdata->rtc->irq_lock); | |
d00ed3cf DM |
219 | } |
220 | ||
221 | /* This function is the RTC interrupt service routine. */ | |
222 | static irqreturn_t mxc_rtc_interrupt(int irq, void *dev_id) | |
223 | { | |
224 | struct platform_device *pdev = dev_id; | |
225 | struct rtc_plat_data *pdata = platform_get_drvdata(pdev); | |
226 | void __iomem *ioaddr = pdata->ioaddr; | |
b59f6d1f | 227 | unsigned long flags; |
d00ed3cf DM |
228 | u32 status; |
229 | u32 events = 0; | |
230 | ||
b59f6d1f | 231 | spin_lock_irqsave(&pdata->rtc->irq_lock, flags); |
d00ed3cf DM |
232 | status = readw(ioaddr + RTC_RTCISR) & readw(ioaddr + RTC_RTCIENR); |
233 | /* clear interrupt sources */ | |
234 | writew(status, ioaddr + RTC_RTCISR); | |
235 | ||
d00ed3cf | 236 | /* update irq data & counter */ |
c92182ee | 237 | if (status & RTC_ALM_BIT) { |
d00ed3cf | 238 | events |= (RTC_AF | RTC_IRQF); |
c92182ee YK |
239 | /* RTC alarm should be one-shot */ |
240 | mxc_rtc_irq_enable(&pdev->dev, RTC_ALM_BIT, 0); | |
241 | } | |
d00ed3cf DM |
242 | |
243 | if (status & RTC_1HZ_BIT) | |
244 | events |= (RTC_UF | RTC_IRQF); | |
245 | ||
246 | if (status & PIT_ALL_ON) | |
247 | events |= (RTC_PF | RTC_IRQF); | |
248 | ||
d00ed3cf | 249 | rtc_update_irq(pdata->rtc, 1, events); |
b59f6d1f | 250 | spin_unlock_irqrestore(&pdata->rtc->irq_lock, flags); |
d00ed3cf DM |
251 | |
252 | return IRQ_HANDLED; | |
253 | } | |
254 | ||
255 | /* | |
256 | * Clear all interrupts and release the IRQ | |
257 | */ | |
258 | static void mxc_rtc_release(struct device *dev) | |
259 | { | |
260 | struct platform_device *pdev = to_platform_device(dev); | |
261 | struct rtc_plat_data *pdata = platform_get_drvdata(pdev); | |
262 | void __iomem *ioaddr = pdata->ioaddr; | |
263 | ||
264 | spin_lock_irq(&pdata->rtc->irq_lock); | |
265 | ||
266 | /* Disable all rtc interrupts */ | |
267 | writew(0, ioaddr + RTC_RTCIENR); | |
268 | ||
269 | /* Clear all interrupt status */ | |
270 | writew(0xffffffff, ioaddr + RTC_RTCISR); | |
271 | ||
272 | spin_unlock_irq(&pdata->rtc->irq_lock); | |
273 | } | |
274 | ||
d00ed3cf DM |
275 | static int mxc_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) |
276 | { | |
277 | mxc_rtc_irq_enable(dev, RTC_ALM_BIT, enabled); | |
278 | return 0; | |
279 | } | |
280 | ||
d00ed3cf DM |
281 | /* |
282 | * This function reads the current RTC time into tm in Gregorian date. | |
283 | */ | |
284 | static int mxc_rtc_read_time(struct device *dev, struct rtc_time *tm) | |
285 | { | |
286 | u32 val; | |
287 | ||
288 | /* Avoid roll-over from reading the different registers */ | |
289 | do { | |
290 | val = get_alarm_or_time(dev, MXC_RTC_TIME); | |
291 | } while (val != get_alarm_or_time(dev, MXC_RTC_TIME)); | |
292 | ||
293 | rtc_time_to_tm(val, tm); | |
294 | ||
295 | return 0; | |
296 | } | |
297 | ||
298 | /* | |
299 | * This function sets the internal RTC time based on tm in Gregorian date. | |
300 | */ | |
301 | static int mxc_rtc_set_mmss(struct device *dev, unsigned long time) | |
302 | { | |
bb1d34a2 SG |
303 | struct platform_device *pdev = to_platform_device(dev); |
304 | struct rtc_plat_data *pdata = platform_get_drvdata(pdev); | |
305 | ||
7287be1d YK |
306 | /* |
307 | * TTC_DAYR register is 9-bit in MX1 SoC, save time and day of year only | |
308 | */ | |
bb1d34a2 | 309 | if (is_imx1_rtc(pdata)) { |
7287be1d YK |
310 | struct rtc_time tm; |
311 | ||
312 | rtc_time_to_tm(time, &tm); | |
313 | tm.tm_year = 70; | |
314 | rtc_tm_to_time(&tm, &time); | |
315 | } | |
316 | ||
d00ed3cf DM |
317 | /* Avoid roll-over from reading the different registers */ |
318 | do { | |
319 | set_alarm_or_time(dev, MXC_RTC_TIME, time); | |
320 | } while (time != get_alarm_or_time(dev, MXC_RTC_TIME)); | |
321 | ||
322 | return 0; | |
323 | } | |
324 | ||
325 | /* | |
326 | * This function reads the current alarm value into the passed in 'alrm' | |
327 | * argument. It updates the alrm's pending field value based on the whether | |
328 | * an alarm interrupt occurs or not. | |
329 | */ | |
330 | static int mxc_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) | |
331 | { | |
332 | struct platform_device *pdev = to_platform_device(dev); | |
333 | struct rtc_plat_data *pdata = platform_get_drvdata(pdev); | |
334 | void __iomem *ioaddr = pdata->ioaddr; | |
335 | ||
336 | rtc_time_to_tm(get_alarm_or_time(dev, MXC_RTC_ALARM), &alrm->time); | |
337 | alrm->pending = ((readw(ioaddr + RTC_RTCISR) & RTC_ALM_BIT)) ? 1 : 0; | |
338 | ||
339 | return 0; | |
340 | } | |
341 | ||
342 | /* | |
343 | * This function sets the RTC alarm based on passed in alrm. | |
344 | */ | |
345 | static int mxc_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) | |
346 | { | |
347 | struct platform_device *pdev = to_platform_device(dev); | |
348 | struct rtc_plat_data *pdata = platform_get_drvdata(pdev); | |
349 | int ret; | |
350 | ||
c92182ee | 351 | ret = rtc_update_alarm(dev, &alrm->time); |
d00ed3cf DM |
352 | if (ret) |
353 | return ret; | |
354 | ||
355 | memcpy(&pdata->g_rtc_alarm, &alrm->time, sizeof(struct rtc_time)); | |
356 | mxc_rtc_irq_enable(dev, RTC_ALM_BIT, alrm->enabled); | |
357 | ||
358 | return 0; | |
359 | } | |
360 | ||
361 | /* RTC layer */ | |
362 | static struct rtc_class_ops mxc_rtc_ops = { | |
363 | .release = mxc_rtc_release, | |
364 | .read_time = mxc_rtc_read_time, | |
365 | .set_mmss = mxc_rtc_set_mmss, | |
366 | .read_alarm = mxc_rtc_read_alarm, | |
367 | .set_alarm = mxc_rtc_set_alarm, | |
368 | .alarm_irq_enable = mxc_rtc_alarm_irq_enable, | |
d00ed3cf DM |
369 | }; |
370 | ||
5a167f45 | 371 | static int mxc_rtc_probe(struct platform_device *pdev) |
d00ed3cf | 372 | { |
d00ed3cf DM |
373 | struct resource *res; |
374 | struct rtc_device *rtc; | |
375 | struct rtc_plat_data *pdata = NULL; | |
376 | u32 reg; | |
c783a29e VZ |
377 | unsigned long rate; |
378 | int ret; | |
d00ed3cf | 379 | |
c783a29e | 380 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); |
d00ed3cf DM |
381 | if (!pdata) |
382 | return -ENOMEM; | |
383 | ||
bb1d34a2 SG |
384 | pdata->devtype = pdev->id_entry->driver_data; |
385 | ||
7c1d69ee JL |
386 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
387 | pdata->ioaddr = devm_ioremap_resource(&pdev->dev, res); | |
388 | if (IS_ERR(pdata->ioaddr)) | |
389 | return PTR_ERR(pdata->ioaddr); | |
d00ed3cf | 390 | |
0f3cde53 | 391 | pdata->clk = devm_clk_get(&pdev->dev, NULL); |
5cf8f57d VZ |
392 | if (IS_ERR(pdata->clk)) { |
393 | dev_err(&pdev->dev, "unable to get clock!\n"); | |
fbd5e754 | 394 | return PTR_ERR(pdata->clk); |
49908e73 | 395 | } |
d00ed3cf | 396 | |
1b3d2243 FE |
397 | ret = clk_prepare_enable(pdata->clk); |
398 | if (ret) | |
399 | return ret; | |
400 | ||
5cf8f57d | 401 | rate = clk_get_rate(pdata->clk); |
d00ed3cf DM |
402 | |
403 | if (rate == 32768) | |
404 | reg = RTC_INPUT_CLK_32768HZ; | |
405 | else if (rate == 32000) | |
406 | reg = RTC_INPUT_CLK_32000HZ; | |
407 | else if (rate == 38400) | |
408 | reg = RTC_INPUT_CLK_38400HZ; | |
409 | else { | |
c783a29e | 410 | dev_err(&pdev->dev, "rtc clock is not valid (%lu)\n", rate); |
d00ed3cf | 411 | ret = -EINVAL; |
5cf8f57d | 412 | goto exit_put_clk; |
d00ed3cf DM |
413 | } |
414 | ||
415 | reg |= RTC_ENABLE_BIT; | |
416 | writew(reg, (pdata->ioaddr + RTC_RTCCTL)); | |
417 | if (((readw(pdata->ioaddr + RTC_RTCCTL)) & RTC_ENABLE_BIT) == 0) { | |
418 | dev_err(&pdev->dev, "hardware module can't be enabled!\n"); | |
419 | ret = -EIO; | |
5cf8f57d | 420 | goto exit_put_clk; |
d00ed3cf DM |
421 | } |
422 | ||
d00ed3cf DM |
423 | platform_set_drvdata(pdev, pdata); |
424 | ||
425 | /* Configure and enable the RTC */ | |
426 | pdata->irq = platform_get_irq(pdev, 0); | |
427 | ||
428 | if (pdata->irq >= 0 && | |
c783a29e VZ |
429 | devm_request_irq(&pdev->dev, pdata->irq, mxc_rtc_interrupt, |
430 | IRQF_SHARED, pdev->name, pdev) < 0) { | |
d00ed3cf DM |
431 | dev_warn(&pdev->dev, "interrupt not available.\n"); |
432 | pdata->irq = -1; | |
433 | } | |
434 | ||
4a8282d0 | 435 | if (pdata->irq >= 0) |
c92182ee YK |
436 | device_init_wakeup(&pdev->dev, 1); |
437 | ||
033ca3ad | 438 | rtc = devm_rtc_device_register(&pdev->dev, pdev->name, &mxc_rtc_ops, |
5f54c8a0 WS |
439 | THIS_MODULE); |
440 | if (IS_ERR(rtc)) { | |
441 | ret = PTR_ERR(rtc); | |
d2f3a398 | 442 | goto exit_put_clk; |
5f54c8a0 WS |
443 | } |
444 | ||
445 | pdata->rtc = rtc; | |
446 | ||
d00ed3cf DM |
447 | return 0; |
448 | ||
449 | exit_put_clk: | |
0f3cde53 | 450 | clk_disable_unprepare(pdata->clk); |
d00ed3cf | 451 | |
d00ed3cf DM |
452 | return ret; |
453 | } | |
454 | ||
5a167f45 | 455 | static int mxc_rtc_remove(struct platform_device *pdev) |
d00ed3cf DM |
456 | { |
457 | struct rtc_plat_data *pdata = platform_get_drvdata(pdev); | |
458 | ||
0f3cde53 | 459 | clk_disable_unprepare(pdata->clk); |
d00ed3cf DM |
460 | |
461 | return 0; | |
462 | } | |
463 | ||
75634cc4 | 464 | #ifdef CONFIG_PM_SLEEP |
c92182ee YK |
465 | static int mxc_rtc_suspend(struct device *dev) |
466 | { | |
467 | struct rtc_plat_data *pdata = dev_get_drvdata(dev); | |
468 | ||
469 | if (device_may_wakeup(dev)) | |
470 | enable_irq_wake(pdata->irq); | |
471 | ||
472 | return 0; | |
473 | } | |
474 | ||
475 | static int mxc_rtc_resume(struct device *dev) | |
476 | { | |
477 | struct rtc_plat_data *pdata = dev_get_drvdata(dev); | |
478 | ||
479 | if (device_may_wakeup(dev)) | |
480 | disable_irq_wake(pdata->irq); | |
481 | ||
482 | return 0; | |
483 | } | |
c92182ee YK |
484 | #endif |
485 | ||
75634cc4 JH |
486 | static SIMPLE_DEV_PM_OPS(mxc_rtc_pm_ops, mxc_rtc_suspend, mxc_rtc_resume); |
487 | ||
d00ed3cf DM |
488 | static struct platform_driver mxc_rtc_driver = { |
489 | .driver = { | |
490 | .name = "mxc_rtc", | |
c92182ee | 491 | .pm = &mxc_rtc_pm_ops, |
d00ed3cf DM |
492 | .owner = THIS_MODULE, |
493 | }, | |
bb1d34a2 | 494 | .id_table = imx_rtc_devtype, |
be8b6d51 | 495 | .probe = mxc_rtc_probe, |
5a167f45 | 496 | .remove = mxc_rtc_remove, |
d00ed3cf DM |
497 | }; |
498 | ||
be8b6d51 | 499 | module_platform_driver(mxc_rtc_driver) |
d00ed3cf DM |
500 | |
501 | MODULE_AUTHOR("Daniel Mack <daniel@caiaq.de>"); | |
502 | MODULE_DESCRIPTION("RTC driver for Freescale MXC"); | |
503 | MODULE_LICENSE("GPL"); | |
504 |