Commit | Line | Data |
---|---|---|
db68b189 | 1 | /* |
10211ae3 | 2 | * TI OMAP Real Time Clock interface for Linux |
db68b189 DB |
3 | * |
4 | * Copyright (C) 2003 MontaVista Software, Inc. | |
5 | * Author: George G. Davis <gdavis@mvista.com> or <source@mvista.com> | |
6 | * | |
7 | * Copyright (C) 2006 David Brownell (new RTC framework) | |
0125138d | 8 | * Copyright (C) 2014 Johan Hovold <johan@kernel.org> |
db68b189 DB |
9 | * |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License | |
12 | * as published by the Free Software Foundation; either version | |
13 | * 2 of the License, or (at your option) any later version. | |
14 | */ | |
15 | ||
16 | #include <linux/kernel.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/ioport.h> | |
20 | #include <linux/delay.h> | |
21 | #include <linux/rtc.h> | |
22 | #include <linux/bcd.h> | |
23 | #include <linux/platform_device.h> | |
9e0344dc AM |
24 | #include <linux/of.h> |
25 | #include <linux/of_device.h> | |
fc9bd902 | 26 | #include <linux/pm_runtime.h> |
4b30c9fc | 27 | #include <linux/io.h> |
db68b189 | 28 | |
10211ae3 JH |
29 | /* |
30 | * The OMAP RTC is a year/month/day/hours/minutes/seconds BCD clock | |
db68b189 DB |
31 | * with century-range alarm matching, driven by the 32kHz clock. |
32 | * | |
33 | * The main user-visible ways it differs from PC RTCs are by omitting | |
34 | * "don't care" alarm fields and sub-second periodic IRQs, and having | |
35 | * an autoadjust mechanism to calibrate to the true oscillator rate. | |
36 | * | |
37 | * Board-specific wiring options include using split power mode with | |
38 | * RTC_OFF_NOFF used as the reset signal (so the RTC won't be reset), | |
39 | * and wiring RTC_WAKE_INT (so the RTC alarm can wake the system from | |
fa5b0782 SN |
40 | * low power modes) for OMAP1 boards (OMAP-L138 has this built into |
41 | * the SoC). See the BOARD-SPECIFIC CUSTOMIZATION comment. | |
db68b189 DB |
42 | */ |
43 | ||
db68b189 DB |
44 | /* RTC registers */ |
45 | #define OMAP_RTC_SECONDS_REG 0x00 | |
46 | #define OMAP_RTC_MINUTES_REG 0x04 | |
47 | #define OMAP_RTC_HOURS_REG 0x08 | |
48 | #define OMAP_RTC_DAYS_REG 0x0C | |
49 | #define OMAP_RTC_MONTHS_REG 0x10 | |
50 | #define OMAP_RTC_YEARS_REG 0x14 | |
51 | #define OMAP_RTC_WEEKS_REG 0x18 | |
52 | ||
53 | #define OMAP_RTC_ALARM_SECONDS_REG 0x20 | |
54 | #define OMAP_RTC_ALARM_MINUTES_REG 0x24 | |
55 | #define OMAP_RTC_ALARM_HOURS_REG 0x28 | |
56 | #define OMAP_RTC_ALARM_DAYS_REG 0x2c | |
57 | #define OMAP_RTC_ALARM_MONTHS_REG 0x30 | |
58 | #define OMAP_RTC_ALARM_YEARS_REG 0x34 | |
59 | ||
60 | #define OMAP_RTC_CTRL_REG 0x40 | |
61 | #define OMAP_RTC_STATUS_REG 0x44 | |
62 | #define OMAP_RTC_INTERRUPTS_REG 0x48 | |
63 | ||
64 | #define OMAP_RTC_COMP_LSB_REG 0x4c | |
65 | #define OMAP_RTC_COMP_MSB_REG 0x50 | |
66 | #define OMAP_RTC_OSC_REG 0x54 | |
67 | ||
cab1458c AM |
68 | #define OMAP_RTC_KICK0_REG 0x6c |
69 | #define OMAP_RTC_KICK1_REG 0x70 | |
70 | ||
8af750e3 HG |
71 | #define OMAP_RTC_IRQWAKEEN 0x7c |
72 | ||
222a12fc JH |
73 | #define OMAP_RTC_ALARM2_SECONDS_REG 0x80 |
74 | #define OMAP_RTC_ALARM2_MINUTES_REG 0x84 | |
75 | #define OMAP_RTC_ALARM2_HOURS_REG 0x88 | |
76 | #define OMAP_RTC_ALARM2_DAYS_REG 0x8c | |
77 | #define OMAP_RTC_ALARM2_MONTHS_REG 0x90 | |
78 | #define OMAP_RTC_ALARM2_YEARS_REG 0x94 | |
79 | ||
80 | #define OMAP_RTC_PMIC_REG 0x98 | |
81 | ||
db68b189 | 82 | /* OMAP_RTC_CTRL_REG bit fields: */ |
92adb96a SN |
83 | #define OMAP_RTC_CTRL_SPLIT BIT(7) |
84 | #define OMAP_RTC_CTRL_DISABLE BIT(6) | |
85 | #define OMAP_RTC_CTRL_SET_32_COUNTER BIT(5) | |
86 | #define OMAP_RTC_CTRL_TEST BIT(4) | |
87 | #define OMAP_RTC_CTRL_MODE_12_24 BIT(3) | |
88 | #define OMAP_RTC_CTRL_AUTO_COMP BIT(2) | |
89 | #define OMAP_RTC_CTRL_ROUND_30S BIT(1) | |
90 | #define OMAP_RTC_CTRL_STOP BIT(0) | |
db68b189 DB |
91 | |
92 | /* OMAP_RTC_STATUS_REG bit fields: */ | |
92adb96a | 93 | #define OMAP_RTC_STATUS_POWER_UP BIT(7) |
222a12fc | 94 | #define OMAP_RTC_STATUS_ALARM2 BIT(7) |
92adb96a SN |
95 | #define OMAP_RTC_STATUS_ALARM BIT(6) |
96 | #define OMAP_RTC_STATUS_1D_EVENT BIT(5) | |
97 | #define OMAP_RTC_STATUS_1H_EVENT BIT(4) | |
98 | #define OMAP_RTC_STATUS_1M_EVENT BIT(3) | |
99 | #define OMAP_RTC_STATUS_1S_EVENT BIT(2) | |
100 | #define OMAP_RTC_STATUS_RUN BIT(1) | |
101 | #define OMAP_RTC_STATUS_BUSY BIT(0) | |
db68b189 DB |
102 | |
103 | /* OMAP_RTC_INTERRUPTS_REG bit fields: */ | |
222a12fc | 104 | #define OMAP_RTC_INTERRUPTS_IT_ALARM2 BIT(4) |
92adb96a SN |
105 | #define OMAP_RTC_INTERRUPTS_IT_ALARM BIT(3) |
106 | #define OMAP_RTC_INTERRUPTS_IT_TIMER BIT(2) | |
db68b189 | 107 | |
cd914bba SN |
108 | /* OMAP_RTC_OSC_REG bit fields: */ |
109 | #define OMAP_RTC_OSC_32KCLK_EN BIT(6) | |
110 | ||
8af750e3 | 111 | /* OMAP_RTC_IRQWAKEEN bit fields: */ |
92adb96a | 112 | #define OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN BIT(1) |
8af750e3 | 113 | |
222a12fc JH |
114 | /* OMAP_RTC_PMIC bit fields: */ |
115 | #define OMAP_RTC_PMIC_POWER_EN_EN BIT(16) | |
116 | ||
cab1458c AM |
117 | /* OMAP_RTC_KICKER values */ |
118 | #define KICK0_VALUE 0x83e70b13 | |
119 | #define KICK1_VALUE 0x95a4f1e0 | |
120 | ||
9c28bd07 LV |
121 | struct omap_rtc; |
122 | ||
2153f949 JH |
123 | struct omap_rtc_device_type { |
124 | bool has_32kclk_en; | |
2153f949 | 125 | bool has_irqwakeen; |
222a12fc | 126 | bool has_pmic_mode; |
9291e340 | 127 | bool has_power_up_reset; |
9c28bd07 LV |
128 | void (*lock)(struct omap_rtc *rtc); |
129 | void (*unlock)(struct omap_rtc *rtc); | |
2153f949 | 130 | }; |
cd914bba | 131 | |
55ba953a JH |
132 | struct omap_rtc { |
133 | struct rtc_device *rtc; | |
134 | void __iomem *base; | |
135 | int irq_alarm; | |
136 | int irq_timer; | |
137 | u8 interrupts_reg; | |
222a12fc | 138 | bool is_pmic_controller; |
2153f949 | 139 | const struct omap_rtc_device_type *type; |
55ba953a | 140 | }; |
db68b189 | 141 | |
55ba953a JH |
142 | static inline u8 rtc_read(struct omap_rtc *rtc, unsigned int reg) |
143 | { | |
144 | return readb(rtc->base + reg); | |
145 | } | |
cab1458c | 146 | |
c253a896 JH |
147 | static inline u32 rtc_readl(struct omap_rtc *rtc, unsigned int reg) |
148 | { | |
149 | return readl(rtc->base + reg); | |
150 | } | |
151 | ||
55ba953a JH |
152 | static inline void rtc_write(struct omap_rtc *rtc, unsigned int reg, u8 val) |
153 | { | |
154 | writeb(val, rtc->base + reg); | |
155 | } | |
db68b189 | 156 | |
55ba953a JH |
157 | static inline void rtc_writel(struct omap_rtc *rtc, unsigned int reg, u32 val) |
158 | { | |
159 | writel(val, rtc->base + reg); | |
160 | } | |
db68b189 | 161 | |
9c28bd07 LV |
162 | static void am3352_rtc_unlock(struct omap_rtc *rtc) |
163 | { | |
164 | rtc_writel(rtc, OMAP_RTC_KICK0_REG, KICK0_VALUE); | |
165 | rtc_writel(rtc, OMAP_RTC_KICK1_REG, KICK1_VALUE); | |
166 | } | |
167 | ||
168 | static void am3352_rtc_lock(struct omap_rtc *rtc) | |
169 | { | |
170 | rtc_writel(rtc, OMAP_RTC_KICK0_REG, 0); | |
171 | rtc_writel(rtc, OMAP_RTC_KICK1_REG, 0); | |
172 | } | |
173 | ||
174 | static void default_rtc_unlock(struct omap_rtc *rtc) | |
175 | { | |
176 | } | |
177 | ||
178 | static void default_rtc_lock(struct omap_rtc *rtc) | |
179 | { | |
180 | } | |
181 | ||
10211ae3 JH |
182 | /* |
183 | * We rely on the rtc framework to handle locking (rtc->ops_lock), | |
db68b189 DB |
184 | * so the only other requirement is that register accesses which |
185 | * require BUSY to be clear are made with IRQs locally disabled | |
186 | */ | |
55ba953a | 187 | static void rtc_wait_not_busy(struct omap_rtc *rtc) |
db68b189 | 188 | { |
10211ae3 JH |
189 | int count; |
190 | u8 status; | |
db68b189 DB |
191 | |
192 | /* BUSY may stay active for 1/32768 second (~30 usec) */ | |
193 | for (count = 0; count < 50; count++) { | |
55ba953a | 194 | status = rtc_read(rtc, OMAP_RTC_STATUS_REG); |
10211ae3 | 195 | if (!(status & OMAP_RTC_STATUS_BUSY)) |
db68b189 DB |
196 | break; |
197 | udelay(1); | |
198 | } | |
199 | /* now we have ~15 usec to read/write various registers */ | |
200 | } | |
201 | ||
55ba953a | 202 | static irqreturn_t rtc_irq(int irq, void *dev_id) |
db68b189 | 203 | { |
10211ae3 JH |
204 | struct omap_rtc *rtc = dev_id; |
205 | unsigned long events = 0; | |
206 | u8 irq_data; | |
db68b189 | 207 | |
55ba953a | 208 | irq_data = rtc_read(rtc, OMAP_RTC_STATUS_REG); |
db68b189 DB |
209 | |
210 | /* alarm irq? */ | |
211 | if (irq_data & OMAP_RTC_STATUS_ALARM) { | |
9c28bd07 | 212 | rtc->type->unlock(rtc); |
55ba953a | 213 | rtc_write(rtc, OMAP_RTC_STATUS_REG, OMAP_RTC_STATUS_ALARM); |
9c28bd07 | 214 | rtc->type->lock(rtc); |
db68b189 DB |
215 | events |= RTC_IRQF | RTC_AF; |
216 | } | |
217 | ||
218 | /* 1/sec periodic/update irq? */ | |
219 | if (irq_data & OMAP_RTC_STATUS_1S_EVENT) | |
220 | events |= RTC_IRQF | RTC_UF; | |
221 | ||
55ba953a | 222 | rtc_update_irq(rtc->rtc, 1, events); |
db68b189 DB |
223 | |
224 | return IRQ_HANDLED; | |
225 | } | |
226 | ||
16380c15 JS |
227 | static int omap_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) |
228 | { | |
55ba953a | 229 | struct omap_rtc *rtc = dev_get_drvdata(dev); |
ab7f580b | 230 | u8 reg, irqwake_reg = 0; |
16380c15 JS |
231 | |
232 | local_irq_disable(); | |
55ba953a JH |
233 | rtc_wait_not_busy(rtc); |
234 | reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG); | |
2153f949 | 235 | if (rtc->type->has_irqwakeen) |
55ba953a | 236 | irqwake_reg = rtc_read(rtc, OMAP_RTC_IRQWAKEEN); |
ab7f580b LV |
237 | |
238 | if (enabled) { | |
16380c15 | 239 | reg |= OMAP_RTC_INTERRUPTS_IT_ALARM; |
ab7f580b LV |
240 | irqwake_reg |= OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN; |
241 | } else { | |
16380c15 | 242 | reg &= ~OMAP_RTC_INTERRUPTS_IT_ALARM; |
ab7f580b LV |
243 | irqwake_reg &= ~OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN; |
244 | } | |
55ba953a | 245 | rtc_wait_not_busy(rtc); |
9c28bd07 | 246 | rtc->type->unlock(rtc); |
55ba953a | 247 | rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, reg); |
2153f949 | 248 | if (rtc->type->has_irqwakeen) |
55ba953a | 249 | rtc_write(rtc, OMAP_RTC_IRQWAKEEN, irqwake_reg); |
9c28bd07 | 250 | rtc->type->lock(rtc); |
16380c15 JS |
251 | local_irq_enable(); |
252 | ||
253 | return 0; | |
254 | } | |
255 | ||
db68b189 DB |
256 | /* this hardware doesn't support "don't care" alarm fields */ |
257 | static int tm2bcd(struct rtc_time *tm) | |
258 | { | |
259 | if (rtc_valid_tm(tm) != 0) | |
260 | return -EINVAL; | |
261 | ||
fe20ba70 AB |
262 | tm->tm_sec = bin2bcd(tm->tm_sec); |
263 | tm->tm_min = bin2bcd(tm->tm_min); | |
264 | tm->tm_hour = bin2bcd(tm->tm_hour); | |
265 | tm->tm_mday = bin2bcd(tm->tm_mday); | |
db68b189 | 266 | |
fe20ba70 | 267 | tm->tm_mon = bin2bcd(tm->tm_mon + 1); |
db68b189 DB |
268 | |
269 | /* epoch == 1900 */ | |
270 | if (tm->tm_year < 100 || tm->tm_year > 199) | |
271 | return -EINVAL; | |
fe20ba70 | 272 | tm->tm_year = bin2bcd(tm->tm_year - 100); |
db68b189 DB |
273 | |
274 | return 0; | |
275 | } | |
276 | ||
277 | static void bcd2tm(struct rtc_time *tm) | |
278 | { | |
fe20ba70 AB |
279 | tm->tm_sec = bcd2bin(tm->tm_sec); |
280 | tm->tm_min = bcd2bin(tm->tm_min); | |
281 | tm->tm_hour = bcd2bin(tm->tm_hour); | |
282 | tm->tm_mday = bcd2bin(tm->tm_mday); | |
283 | tm->tm_mon = bcd2bin(tm->tm_mon) - 1; | |
db68b189 | 284 | /* epoch == 1900 */ |
fe20ba70 | 285 | tm->tm_year = bcd2bin(tm->tm_year) + 100; |
db68b189 DB |
286 | } |
287 | ||
cbbe326f | 288 | static void omap_rtc_read_time_raw(struct omap_rtc *rtc, struct rtc_time *tm) |
db68b189 | 289 | { |
55ba953a JH |
290 | tm->tm_sec = rtc_read(rtc, OMAP_RTC_SECONDS_REG); |
291 | tm->tm_min = rtc_read(rtc, OMAP_RTC_MINUTES_REG); | |
292 | tm->tm_hour = rtc_read(rtc, OMAP_RTC_HOURS_REG); | |
293 | tm->tm_mday = rtc_read(rtc, OMAP_RTC_DAYS_REG); | |
294 | tm->tm_mon = rtc_read(rtc, OMAP_RTC_MONTHS_REG); | |
295 | tm->tm_year = rtc_read(rtc, OMAP_RTC_YEARS_REG); | |
cbbe326f JH |
296 | } |
297 | ||
298 | static int omap_rtc_read_time(struct device *dev, struct rtc_time *tm) | |
299 | { | |
300 | struct omap_rtc *rtc = dev_get_drvdata(dev); | |
db68b189 | 301 | |
cbbe326f JH |
302 | /* we don't report wday/yday/isdst ... */ |
303 | local_irq_disable(); | |
304 | rtc_wait_not_busy(rtc); | |
305 | omap_rtc_read_time_raw(rtc, tm); | |
db68b189 DB |
306 | local_irq_enable(); |
307 | ||
308 | bcd2tm(tm); | |
10211ae3 | 309 | |
db68b189 DB |
310 | return 0; |
311 | } | |
312 | ||
313 | static int omap_rtc_set_time(struct device *dev, struct rtc_time *tm) | |
314 | { | |
55ba953a JH |
315 | struct omap_rtc *rtc = dev_get_drvdata(dev); |
316 | ||
db68b189 DB |
317 | if (tm2bcd(tm) < 0) |
318 | return -EINVAL; | |
10211ae3 | 319 | |
db68b189 | 320 | local_irq_disable(); |
55ba953a | 321 | rtc_wait_not_busy(rtc); |
db68b189 | 322 | |
9c28bd07 | 323 | rtc->type->unlock(rtc); |
55ba953a JH |
324 | rtc_write(rtc, OMAP_RTC_YEARS_REG, tm->tm_year); |
325 | rtc_write(rtc, OMAP_RTC_MONTHS_REG, tm->tm_mon); | |
326 | rtc_write(rtc, OMAP_RTC_DAYS_REG, tm->tm_mday); | |
327 | rtc_write(rtc, OMAP_RTC_HOURS_REG, tm->tm_hour); | |
328 | rtc_write(rtc, OMAP_RTC_MINUTES_REG, tm->tm_min); | |
329 | rtc_write(rtc, OMAP_RTC_SECONDS_REG, tm->tm_sec); | |
9c28bd07 | 330 | rtc->type->lock(rtc); |
db68b189 DB |
331 | |
332 | local_irq_enable(); | |
333 | ||
334 | return 0; | |
335 | } | |
336 | ||
337 | static int omap_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm) | |
338 | { | |
55ba953a | 339 | struct omap_rtc *rtc = dev_get_drvdata(dev); |
10211ae3 | 340 | u8 interrupts; |
55ba953a | 341 | |
db68b189 | 342 | local_irq_disable(); |
55ba953a | 343 | rtc_wait_not_busy(rtc); |
db68b189 | 344 | |
55ba953a JH |
345 | alm->time.tm_sec = rtc_read(rtc, OMAP_RTC_ALARM_SECONDS_REG); |
346 | alm->time.tm_min = rtc_read(rtc, OMAP_RTC_ALARM_MINUTES_REG); | |
347 | alm->time.tm_hour = rtc_read(rtc, OMAP_RTC_ALARM_HOURS_REG); | |
348 | alm->time.tm_mday = rtc_read(rtc, OMAP_RTC_ALARM_DAYS_REG); | |
349 | alm->time.tm_mon = rtc_read(rtc, OMAP_RTC_ALARM_MONTHS_REG); | |
350 | alm->time.tm_year = rtc_read(rtc, OMAP_RTC_ALARM_YEARS_REG); | |
db68b189 DB |
351 | |
352 | local_irq_enable(); | |
353 | ||
354 | bcd2tm(&alm->time); | |
10211ae3 JH |
355 | |
356 | interrupts = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG); | |
357 | alm->enabled = !!(interrupts & OMAP_RTC_INTERRUPTS_IT_ALARM); | |
db68b189 DB |
358 | |
359 | return 0; | |
360 | } | |
361 | ||
362 | static int omap_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm) | |
363 | { | |
55ba953a | 364 | struct omap_rtc *rtc = dev_get_drvdata(dev); |
ab7f580b | 365 | u8 reg, irqwake_reg = 0; |
db68b189 | 366 | |
db68b189 DB |
367 | if (tm2bcd(&alm->time) < 0) |
368 | return -EINVAL; | |
369 | ||
370 | local_irq_disable(); | |
55ba953a | 371 | rtc_wait_not_busy(rtc); |
db68b189 | 372 | |
9c28bd07 | 373 | rtc->type->unlock(rtc); |
55ba953a JH |
374 | rtc_write(rtc, OMAP_RTC_ALARM_YEARS_REG, alm->time.tm_year); |
375 | rtc_write(rtc, OMAP_RTC_ALARM_MONTHS_REG, alm->time.tm_mon); | |
376 | rtc_write(rtc, OMAP_RTC_ALARM_DAYS_REG, alm->time.tm_mday); | |
377 | rtc_write(rtc, OMAP_RTC_ALARM_HOURS_REG, alm->time.tm_hour); | |
378 | rtc_write(rtc, OMAP_RTC_ALARM_MINUTES_REG, alm->time.tm_min); | |
379 | rtc_write(rtc, OMAP_RTC_ALARM_SECONDS_REG, alm->time.tm_sec); | |
db68b189 | 380 | |
55ba953a | 381 | reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG); |
2153f949 | 382 | if (rtc->type->has_irqwakeen) |
55ba953a | 383 | irqwake_reg = rtc_read(rtc, OMAP_RTC_IRQWAKEEN); |
ab7f580b LV |
384 | |
385 | if (alm->enabled) { | |
db68b189 | 386 | reg |= OMAP_RTC_INTERRUPTS_IT_ALARM; |
ab7f580b LV |
387 | irqwake_reg |= OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN; |
388 | } else { | |
db68b189 | 389 | reg &= ~OMAP_RTC_INTERRUPTS_IT_ALARM; |
ab7f580b LV |
390 | irqwake_reg &= ~OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN; |
391 | } | |
55ba953a | 392 | rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, reg); |
2153f949 | 393 | if (rtc->type->has_irqwakeen) |
55ba953a | 394 | rtc_write(rtc, OMAP_RTC_IRQWAKEEN, irqwake_reg); |
9c28bd07 | 395 | rtc->type->lock(rtc); |
db68b189 DB |
396 | |
397 | local_irq_enable(); | |
398 | ||
399 | return 0; | |
400 | } | |
401 | ||
222a12fc JH |
402 | static struct omap_rtc *omap_rtc_power_off_rtc; |
403 | ||
404 | /* | |
405 | * omap_rtc_poweroff: RTC-controlled power off | |
406 | * | |
407 | * The RTC can be used to control an external PMIC via the pmic_power_en pin, | |
408 | * which can be configured to transition to OFF on ALARM2 events. | |
409 | * | |
410 | * Notes: | |
411 | * The two-second alarm offset is the shortest offset possible as the alarm | |
412 | * registers must be set before the next timer update and the offset | |
413 | * calculation is too heavy for everything to be done within a single access | |
414 | * period (~15 us). | |
415 | * | |
416 | * Called with local interrupts disabled. | |
417 | */ | |
418 | static void omap_rtc_power_off(void) | |
419 | { | |
420 | struct omap_rtc *rtc = omap_rtc_power_off_rtc; | |
421 | struct rtc_time tm; | |
422 | unsigned long now; | |
423 | u32 val; | |
424 | ||
9c28bd07 | 425 | rtc->type->unlock(rtc); |
222a12fc JH |
426 | /* enable pmic_power_en control */ |
427 | val = rtc_readl(rtc, OMAP_RTC_PMIC_REG); | |
428 | rtc_writel(rtc, OMAP_RTC_PMIC_REG, val | OMAP_RTC_PMIC_POWER_EN_EN); | |
429 | ||
430 | /* set alarm two seconds from now */ | |
431 | omap_rtc_read_time_raw(rtc, &tm); | |
432 | bcd2tm(&tm); | |
433 | rtc_tm_to_time(&tm, &now); | |
434 | rtc_time_to_tm(now + 2, &tm); | |
435 | ||
436 | if (tm2bcd(&tm) < 0) { | |
437 | dev_err(&rtc->rtc->dev, "power off failed\n"); | |
438 | return; | |
439 | } | |
440 | ||
441 | rtc_wait_not_busy(rtc); | |
442 | ||
443 | rtc_write(rtc, OMAP_RTC_ALARM2_SECONDS_REG, tm.tm_sec); | |
444 | rtc_write(rtc, OMAP_RTC_ALARM2_MINUTES_REG, tm.tm_min); | |
445 | rtc_write(rtc, OMAP_RTC_ALARM2_HOURS_REG, tm.tm_hour); | |
446 | rtc_write(rtc, OMAP_RTC_ALARM2_DAYS_REG, tm.tm_mday); | |
447 | rtc_write(rtc, OMAP_RTC_ALARM2_MONTHS_REG, tm.tm_mon); | |
448 | rtc_write(rtc, OMAP_RTC_ALARM2_YEARS_REG, tm.tm_year); | |
449 | ||
450 | /* | |
451 | * enable ALARM2 interrupt | |
452 | * | |
453 | * NOTE: this fails on AM3352 if rtc_write (writeb) is used | |
454 | */ | |
455 | val = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG); | |
456 | rtc_writel(rtc, OMAP_RTC_INTERRUPTS_REG, | |
457 | val | OMAP_RTC_INTERRUPTS_IT_ALARM2); | |
9c28bd07 | 458 | rtc->type->lock(rtc); |
222a12fc JH |
459 | |
460 | /* | |
461 | * Wait for alarm to trigger (within two seconds) and external PMIC to | |
462 | * power off the system. Add a 500 ms margin for external latencies | |
463 | * (e.g. debounce circuits). | |
464 | */ | |
465 | mdelay(2500); | |
466 | } | |
467 | ||
db68b189 | 468 | static struct rtc_class_ops omap_rtc_ops = { |
db68b189 DB |
469 | .read_time = omap_rtc_read_time, |
470 | .set_time = omap_rtc_set_time, | |
471 | .read_alarm = omap_rtc_read_alarm, | |
472 | .set_alarm = omap_rtc_set_alarm, | |
16380c15 | 473 | .alarm_irq_enable = omap_rtc_alarm_irq_enable, |
db68b189 DB |
474 | }; |
475 | ||
2153f949 | 476 | static const struct omap_rtc_device_type omap_rtc_default_type = { |
9291e340 | 477 | .has_power_up_reset = true, |
9c28bd07 LV |
478 | .lock = default_rtc_lock, |
479 | .unlock = default_rtc_unlock, | |
2153f949 JH |
480 | }; |
481 | ||
482 | static const struct omap_rtc_device_type omap_rtc_am3352_type = { | |
483 | .has_32kclk_en = true, | |
2153f949 | 484 | .has_irqwakeen = true, |
222a12fc | 485 | .has_pmic_mode = true, |
9c28bd07 LV |
486 | .lock = am3352_rtc_lock, |
487 | .unlock = am3352_rtc_unlock, | |
2153f949 JH |
488 | }; |
489 | ||
490 | static const struct omap_rtc_device_type omap_rtc_da830_type = { | |
9c28bd07 LV |
491 | .lock = am3352_rtc_lock, |
492 | .unlock = am3352_rtc_unlock, | |
2153f949 | 493 | }; |
9e0344dc | 494 | |
2153f949 | 495 | static const struct platform_device_id omap_rtc_id_table[] = { |
cab1458c | 496 | { |
a430ca22 | 497 | .name = "omap_rtc", |
2153f949 JH |
498 | .driver_data = (kernel_ulong_t)&omap_rtc_default_type, |
499 | }, { | |
8af750e3 | 500 | .name = "am3352-rtc", |
2153f949 JH |
501 | .driver_data = (kernel_ulong_t)&omap_rtc_am3352_type, |
502 | }, { | |
cab1458c | 503 | .name = "da830-rtc", |
2153f949 JH |
504 | .driver_data = (kernel_ulong_t)&omap_rtc_da830_type, |
505 | }, { | |
506 | /* sentinel */ | |
507 | } | |
cab1458c | 508 | }; |
2153f949 | 509 | MODULE_DEVICE_TABLE(platform, omap_rtc_id_table); |
cab1458c | 510 | |
9e0344dc | 511 | static const struct of_device_id omap_rtc_of_match[] = { |
2153f949 JH |
512 | { |
513 | .compatible = "ti,am3352-rtc", | |
514 | .data = &omap_rtc_am3352_type, | |
515 | }, { | |
516 | .compatible = "ti,da830-rtc", | |
517 | .data = &omap_rtc_da830_type, | |
518 | }, { | |
519 | /* sentinel */ | |
520 | } | |
9e0344dc AM |
521 | }; |
522 | MODULE_DEVICE_TABLE(of, omap_rtc_of_match); | |
523 | ||
5d9094b6 | 524 | static int omap_rtc_probe(struct platform_device *pdev) |
db68b189 | 525 | { |
10211ae3 JH |
526 | struct omap_rtc *rtc; |
527 | struct resource *res; | |
528 | u8 reg, mask, new_ctrl; | |
cab1458c | 529 | const struct platform_device_id *id_entry; |
9e0344dc | 530 | const struct of_device_id *of_id; |
437b37a6 | 531 | int ret; |
9e0344dc | 532 | |
55ba953a JH |
533 | rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL); |
534 | if (!rtc) | |
535 | return -ENOMEM; | |
536 | ||
9e0344dc | 537 | of_id = of_match_device(omap_rtc_of_match, &pdev->dev); |
2153f949 JH |
538 | if (of_id) { |
539 | rtc->type = of_id->data; | |
222a12fc JH |
540 | rtc->is_pmic_controller = rtc->type->has_pmic_mode && |
541 | of_property_read_bool(pdev->dev.of_node, | |
094d3ee3 | 542 | "system-power-controller"); |
2153f949 JH |
543 | } else { |
544 | id_entry = platform_get_device_id(pdev); | |
545 | rtc->type = (void *)id_entry->driver_data; | |
337b600f SN |
546 | } |
547 | ||
55ba953a JH |
548 | rtc->irq_timer = platform_get_irq(pdev, 0); |
549 | if (rtc->irq_timer <= 0) | |
db68b189 | 550 | return -ENOENT; |
db68b189 | 551 | |
55ba953a JH |
552 | rtc->irq_alarm = platform_get_irq(pdev, 1); |
553 | if (rtc->irq_alarm <= 0) | |
db68b189 | 554 | return -ENOENT; |
db68b189 | 555 | |
db68b189 | 556 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
55ba953a JH |
557 | rtc->base = devm_ioremap_resource(&pdev->dev, res); |
558 | if (IS_ERR(rtc->base)) | |
559 | return PTR_ERR(rtc->base); | |
560 | ||
561 | platform_set_drvdata(pdev, rtc); | |
8cfde8c1 | 562 | |
fc9bd902 VH |
563 | /* Enable the clock/module so that we can access the registers */ |
564 | pm_runtime_enable(&pdev->dev); | |
565 | pm_runtime_get_sync(&pdev->dev); | |
566 | ||
9c28bd07 | 567 | rtc->type->unlock(rtc); |
cab1458c | 568 | |
1ed8b5d2 JH |
569 | /* |
570 | * disable interrupts | |
571 | * | |
572 | * NOTE: ALARM2 is not cleared on AM3352 if rtc_write (writeb) is used | |
db68b189 | 573 | */ |
55ba953a | 574 | rtc_writel(rtc, OMAP_RTC_INTERRUPTS_REG, 0); |
db68b189 | 575 | |
cd914bba | 576 | /* enable RTC functional clock */ |
2153f949 | 577 | if (rtc->type->has_32kclk_en) { |
55ba953a JH |
578 | reg = rtc_read(rtc, OMAP_RTC_OSC_REG); |
579 | rtc_writel(rtc, OMAP_RTC_OSC_REG, | |
580 | reg | OMAP_RTC_OSC_32KCLK_EN); | |
44c63a57 | 581 | } |
cd914bba | 582 | |
db68b189 | 583 | /* clear old status */ |
55ba953a | 584 | reg = rtc_read(rtc, OMAP_RTC_STATUS_REG); |
9291e340 JH |
585 | |
586 | mask = OMAP_RTC_STATUS_ALARM; | |
587 | ||
222a12fc JH |
588 | if (rtc->type->has_pmic_mode) |
589 | mask |= OMAP_RTC_STATUS_ALARM2; | |
590 | ||
9291e340 JH |
591 | if (rtc->type->has_power_up_reset) { |
592 | mask |= OMAP_RTC_STATUS_POWER_UP; | |
593 | if (reg & OMAP_RTC_STATUS_POWER_UP) | |
594 | dev_info(&pdev->dev, "RTC power up reset detected\n"); | |
db68b189 | 595 | } |
9291e340 JH |
596 | |
597 | if (reg & mask) | |
598 | rtc_write(rtc, OMAP_RTC_STATUS_REG, reg & mask); | |
db68b189 | 599 | |
db68b189 | 600 | /* On boards with split power, RTC_ON_NOFF won't reset the RTC */ |
55ba953a | 601 | reg = rtc_read(rtc, OMAP_RTC_CTRL_REG); |
10211ae3 | 602 | if (reg & OMAP_RTC_CTRL_STOP) |
397b630a | 603 | dev_info(&pdev->dev, "already running\n"); |
db68b189 DB |
604 | |
605 | /* force to 24 hour mode */ | |
10211ae3 | 606 | new_ctrl = reg & (OMAP_RTC_CTRL_SPLIT | OMAP_RTC_CTRL_AUTO_COMP); |
db68b189 DB |
607 | new_ctrl |= OMAP_RTC_CTRL_STOP; |
608 | ||
10211ae3 JH |
609 | /* |
610 | * BOARD-SPECIFIC CUSTOMIZATION CAN GO HERE: | |
db68b189 | 611 | * |
fa5b0782 SN |
612 | * - Device wake-up capability setting should come through chip |
613 | * init logic. OMAP1 boards should initialize the "wakeup capable" | |
614 | * flag in the platform device if the board is wired right for | |
615 | * being woken up by RTC alarm. For OMAP-L138, this capability | |
616 | * is built into the SoC by the "Deep Sleep" capability. | |
db68b189 DB |
617 | * |
618 | * - Boards wired so RTC_ON_nOFF is used as the reset signal, | |
619 | * rather than nPWRON_RESET, should forcibly enable split | |
620 | * power mode. (Some chip errata report that RTC_CTRL_SPLIT | |
621 | * is write-only, and always reads as zero...) | |
622 | */ | |
db68b189 | 623 | |
10211ae3 | 624 | if (new_ctrl & OMAP_RTC_CTRL_SPLIT) |
397b630a | 625 | dev_info(&pdev->dev, "split power mode\n"); |
db68b189 DB |
626 | |
627 | if (reg != new_ctrl) | |
55ba953a | 628 | rtc_write(rtc, OMAP_RTC_CTRL_REG, new_ctrl); |
db68b189 | 629 | |
9c28bd07 LV |
630 | rtc->type->lock(rtc); |
631 | ||
4390ce00 JH |
632 | device_init_wakeup(&pdev->dev, true); |
633 | ||
55ba953a | 634 | rtc->rtc = devm_rtc_device_register(&pdev->dev, pdev->name, |
4390ce00 | 635 | &omap_rtc_ops, THIS_MODULE); |
55ba953a JH |
636 | if (IS_ERR(rtc->rtc)) { |
637 | ret = PTR_ERR(rtc->rtc); | |
4390ce00 JH |
638 | goto err; |
639 | } | |
4390ce00 JH |
640 | |
641 | /* handle periodic and alarm irqs */ | |
55ba953a JH |
642 | ret = devm_request_irq(&pdev->dev, rtc->irq_timer, rtc_irq, 0, |
643 | dev_name(&rtc->rtc->dev), rtc); | |
4390ce00 JH |
644 | if (ret) |
645 | goto err; | |
646 | ||
55ba953a JH |
647 | if (rtc->irq_timer != rtc->irq_alarm) { |
648 | ret = devm_request_irq(&pdev->dev, rtc->irq_alarm, rtc_irq, 0, | |
649 | dev_name(&rtc->rtc->dev), rtc); | |
4390ce00 JH |
650 | if (ret) |
651 | goto err; | |
652 | } | |
653 | ||
222a12fc JH |
654 | if (rtc->is_pmic_controller) { |
655 | if (!pm_power_off) { | |
656 | omap_rtc_power_off_rtc = rtc; | |
657 | pm_power_off = omap_rtc_power_off; | |
658 | } | |
659 | } | |
660 | ||
db68b189 DB |
661 | return 0; |
662 | ||
437b37a6 | 663 | err: |
7ecd9a3f | 664 | device_init_wakeup(&pdev->dev, false); |
9c28bd07 | 665 | rtc->type->lock(rtc); |
fc9bd902 VH |
666 | pm_runtime_put_sync(&pdev->dev); |
667 | pm_runtime_disable(&pdev->dev); | |
437b37a6 JH |
668 | |
669 | return ret; | |
db68b189 DB |
670 | } |
671 | ||
71fc8224 | 672 | static int __exit omap_rtc_remove(struct platform_device *pdev) |
db68b189 | 673 | { |
55ba953a | 674 | struct omap_rtc *rtc = platform_get_drvdata(pdev); |
db68b189 | 675 | |
222a12fc JH |
676 | if (pm_power_off == omap_rtc_power_off && |
677 | omap_rtc_power_off_rtc == rtc) { | |
678 | pm_power_off = NULL; | |
679 | omap_rtc_power_off_rtc = NULL; | |
680 | } | |
681 | ||
db68b189 DB |
682 | device_init_wakeup(&pdev->dev, 0); |
683 | ||
9c28bd07 | 684 | rtc->type->unlock(rtc); |
db68b189 | 685 | /* leave rtc running, but disable irqs */ |
55ba953a | 686 | rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, 0); |
db68b189 | 687 | |
9c28bd07 | 688 | rtc->type->lock(rtc); |
fc9bd902 VH |
689 | |
690 | /* Disable the clock/module */ | |
691 | pm_runtime_put_sync(&pdev->dev); | |
692 | pm_runtime_disable(&pdev->dev); | |
693 | ||
db68b189 DB |
694 | return 0; |
695 | } | |
696 | ||
04ebc359 | 697 | #ifdef CONFIG_PM_SLEEP |
04ebc359 | 698 | static int omap_rtc_suspend(struct device *dev) |
db68b189 | 699 | { |
55ba953a JH |
700 | struct omap_rtc *rtc = dev_get_drvdata(dev); |
701 | ||
702 | rtc->interrupts_reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG); | |
db68b189 | 703 | |
9c28bd07 | 704 | rtc->type->unlock(rtc); |
10211ae3 JH |
705 | /* |
706 | * FIXME: the RTC alarm is not currently acting as a wakeup event | |
8af750e3 HG |
707 | * source on some platforms, and in fact this enable() call is just |
708 | * saving a flag that's never used... | |
db68b189 | 709 | */ |
ab7f580b | 710 | if (device_may_wakeup(dev)) |
55ba953a | 711 | enable_irq_wake(rtc->irq_alarm); |
ab7f580b | 712 | else |
55ba953a | 713 | rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, 0); |
9c28bd07 | 714 | rtc->type->lock(rtc); |
db68b189 | 715 | |
fc9bd902 | 716 | /* Disable the clock/module */ |
04ebc359 | 717 | pm_runtime_put_sync(dev); |
fc9bd902 | 718 | |
db68b189 DB |
719 | return 0; |
720 | } | |
721 | ||
04ebc359 | 722 | static int omap_rtc_resume(struct device *dev) |
db68b189 | 723 | { |
55ba953a JH |
724 | struct omap_rtc *rtc = dev_get_drvdata(dev); |
725 | ||
fc9bd902 | 726 | /* Enable the clock/module so that we can access the registers */ |
04ebc359 | 727 | pm_runtime_get_sync(dev); |
fc9bd902 | 728 | |
9c28bd07 | 729 | rtc->type->unlock(rtc); |
ab7f580b | 730 | if (device_may_wakeup(dev)) |
55ba953a | 731 | disable_irq_wake(rtc->irq_alarm); |
ab7f580b | 732 | else |
55ba953a | 733 | rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, rtc->interrupts_reg); |
9c28bd07 | 734 | rtc->type->lock(rtc); |
ab7f580b | 735 | |
db68b189 DB |
736 | return 0; |
737 | } | |
db68b189 DB |
738 | #endif |
739 | ||
04ebc359 JH |
740 | static SIMPLE_DEV_PM_OPS(omap_rtc_pm_ops, omap_rtc_suspend, omap_rtc_resume); |
741 | ||
db68b189 DB |
742 | static void omap_rtc_shutdown(struct platform_device *pdev) |
743 | { | |
55ba953a | 744 | struct omap_rtc *rtc = platform_get_drvdata(pdev); |
8ad5c722 | 745 | u8 mask; |
55ba953a | 746 | |
8ad5c722 JH |
747 | /* |
748 | * Keep the ALARM interrupt enabled to allow the system to power up on | |
749 | * alarm events. | |
750 | */ | |
9c28bd07 | 751 | rtc->type->unlock(rtc); |
8ad5c722 JH |
752 | mask = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG); |
753 | mask &= OMAP_RTC_INTERRUPTS_IT_ALARM; | |
754 | rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, mask); | |
9c28bd07 | 755 | rtc->type->lock(rtc); |
db68b189 DB |
756 | } |
757 | ||
db68b189 | 758 | static struct platform_driver omap_rtc_driver = { |
5d9094b6 | 759 | .probe = omap_rtc_probe, |
71fc8224 | 760 | .remove = __exit_p(omap_rtc_remove), |
db68b189 DB |
761 | .shutdown = omap_rtc_shutdown, |
762 | .driver = { | |
a430ca22 | 763 | .name = "omap_rtc", |
04ebc359 | 764 | .pm = &omap_rtc_pm_ops, |
616b7341 | 765 | .of_match_table = omap_rtc_of_match, |
db68b189 | 766 | }, |
2153f949 | 767 | .id_table = omap_rtc_id_table, |
db68b189 DB |
768 | }; |
769 | ||
5d9094b6 | 770 | module_platform_driver(omap_rtc_driver); |
db68b189 | 771 | |
a430ca22 | 772 | MODULE_ALIAS("platform:omap_rtc"); |
db68b189 DB |
773 | MODULE_AUTHOR("George G. Davis (and others)"); |
774 | MODULE_LICENSE("GPL"); |