[deliverable/linux.git] / drivers / rtc / rtc-pcf2123.c

/*
 * An SPI driver for the Philips PCF2123 RTC
 * Copyright 2009 Cyber Switching, Inc.
 *
 * Author: Chris Verges <chrisv@cyberswitching.com>
 * Maintainers: http://www.cyberswitching.com
 *
 * based on the RS5C348 driver in this same directory.
 *
 * Thanks to Christian Pellegrin <chripell@fsfe.org> for
 * the sysfs contributions to this driver.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Please note that the CS is active high, so platform data
 * should look something like:
 *
 * static struct spi_board_info ek_spi_devices[] = {
 *	...
 *	{
 *		.modalias		= "rtc-pcf2123",
 *		.chip_select		= 1,
 *		.controller_data	= (void *)AT91_PIN_PA10,
 *		.max_speed_hz		= 1000 * 1000,
 *		.mode			= SPI_CS_HIGH,
 *		.bus_num		= 0,
 *	},
 *	...
 *};
 *
 */

#include <linux/bcd.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <linux/rtc.h>
#include <linux/spi/spi.h>
#include <linux/module.h>
#include <linux/sysfs.h>

#define DRV_VERSION "0.6"

/* REGISTERS */
#define PCF2123_REG_CTRL1	(0x00)	/* Control Register 1 */
#define PCF2123_REG_CTRL2	(0x01)	/* Control Register 2 */
#define PCF2123_REG_SC		(0x02)	/* datetime */
#define PCF2123_REG_MN		(0x03)
#define PCF2123_REG_HR		(0x04)
#define PCF2123_REG_DM		(0x05)
#define PCF2123_REG_DW		(0x06)
#define PCF2123_REG_MO		(0x07)
#define PCF2123_REG_YR		(0x08)
#define PCF2123_REG_ALRM_MN	(0x09)	/* Alarm Registers */
#define PCF2123_REG_ALRM_HR	(0x0a)
#define PCF2123_REG_ALRM_DM	(0x0b)
#define PCF2123_REG_ALRM_DW	(0x0c)
#define PCF2123_REG_OFFSET	(0x0d)	/* Clock Rate Offset Register */
#define PCF2123_REG_TMR_CLKOUT	(0x0e)	/* Timer Registers */
#define PCF2123_REG_CTDWN_TMR	(0x0f)

/* PCF2123_REG_CTRL1 BITS */
#define CTRL1_CLEAR		(0)	/* Clear */
#define CTRL1_CORR_INT		BIT(1)	/* Correction irq enable */
#define CTRL1_12_HOUR		BIT(2)	/* 12 hour time */
#define CTRL1_SW_RESET	(BIT(3) | BIT(4) | BIT(6))	/* Software reset */
#define CTRL1_STOP		BIT(5)	/* Stop the clock */
#define CTRL1_EXT_TEST		BIT(7)	/* External clock test mode */

/* PCF2123_REG_CTRL2 BITS */
#define CTRL2_TIE		BIT(0)	/* Countdown timer irq enable */
#define CTRL2_AIE		BIT(1)	/* Alarm irq enable */
#define CTRL2_TF		BIT(2)	/* Countdown timer flag */
#define CTRL2_AF		BIT(3)	/* Alarm flag */
#define CTRL2_TI_TP		BIT(4)	/* Irq pin generates pulse */
#define CTRL2_MSF		BIT(5)	/* Minute or second irq flag */
#define CTRL2_SI		BIT(6)	/* Second irq enable */
#define CTRL2_MI		BIT(7)	/* Minute irq enable */

/* PCF2123_REG_SC BITS */
#define OSC_HAS_STOPPED		BIT(7)	/* Clock has been stopped */

/* PCF2123_REG_ALRM_XX BITS */
#define ALRM_ENABLE		BIT(7)	/* MN, HR, DM, or DW alarm enable */

/* PCF2123_REG_TMR_CLKOUT BITS */
#define CD_TMR_4096KHZ		(0)	/* 4096 KHz countdown timer */
#define CD_TMR_64HZ		(1)	/* 64 Hz countdown timer */
#define CD_TMR_1HZ		(2)	/* 1 Hz countdown timer */
#define CD_TMR_60th_HZ		(3)	/* 60th Hz countdown timer */
#define CD_TMR_TE		BIT(3)	/* Countdown timer enable */

/* PCF2123_REG_OFFSET BITS */
#define OFFSET_SIGN_BIT		BIT(6)	/* 2's complement sign bit */
#define OFFSET_COARSE		BIT(7)	/* Coarse mode offset */

/* READ/WRITE ADDRESS BITS */
#define PCF2123_WRITE		BIT(4)
#define PCF2123_READ		(BIT(4) | BIT(7))


static struct spi_driver pcf2123_driver;

struct pcf2123_sysfs_reg {
	struct device_attribute attr;
	char name[2];
};

struct pcf2123_plat_data {
	struct rtc_device *rtc;
	struct pcf2123_sysfs_reg regs[16];
};

/*
 * Causes a 30 nanosecond delay to ensure that the PCF2123 chip select
 * is released properly after an SPI write.  This function should be
 * called after EVERY read/write call over SPI.
 */
static inline void pcf2123_delay_trec(void)
{
	ndelay(30);
}

static int pcf2123_read(struct device *dev, u8 reg, u8 *rxbuf, size_t size)
{
	struct spi_device *spi = to_spi_device(dev);
	int ret;

	reg |= PCF2123_READ;
	ret = spi_write_then_read(spi, &reg, 1, rxbuf, size);
	pcf2123_delay_trec();

	return ret;
}

static int pcf2123_write(struct device *dev, u8 *txbuf, size_t size)
{
	struct spi_device *spi = to_spi_device(dev);
	int ret;

	txbuf[0] |= PCF2123_WRITE;
	ret = spi_write(spi, txbuf, size);
	pcf2123_delay_trec();

	return ret;
}

static int pcf2123_write_reg(struct device *dev, u8 reg, u8 val)
{
	u8 txbuf[2];

	txbuf[0] = reg;
	txbuf[1] = val;
	return pcf2123_write(dev, txbuf, sizeof(txbuf));
}

static ssize_t pcf2123_show(struct device *dev, struct device_attribute *attr,
			    char *buffer)
{
	struct pcf2123_sysfs_reg *r;
	u8 rxbuf[1];
	unsigned long reg;
	int ret;

	r = container_of(attr, struct pcf2123_sysfs_reg, attr);

	ret = kstrtoul(r->name, 16, &reg);
	if (ret)
		return ret;

	ret = pcf2123_read(dev, reg, rxbuf, 1);
	if (ret < 0)
		return -EIO;

	return sprintf(buffer, "0x%x\n", rxbuf[0]);
}

static ssize_t pcf2123_store(struct device *dev, struct device_attribute *attr,
			     const char *buffer, size_t count) {
	struct pcf2123_sysfs_reg *r;
	unsigned long reg;
	unsigned long val;

	int ret;

	r = container_of(attr, struct pcf2123_sysfs_reg, attr);

	ret = kstrtoul(r->name, 16, &reg);
	if (ret)
		return ret;

	ret = kstrtoul(buffer, 10, &val);
	if (ret)
		return ret;

	pcf2123_write_reg(dev, reg, val);
	if (ret < 0)
		return -EIO;
	return count;
}

static int pcf2123_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
	u8 rxbuf[7];
	int ret;

	ret = pcf2123_read(dev, PCF2123_REG_SC, rxbuf, sizeof(rxbuf));
	if (ret < 0)
		return ret;

	if (rxbuf[0] & OSC_HAS_STOPPED) {
		dev_info(dev, "clock was stopped. Time is not valid\n");
		return -EINVAL;
	}

	tm->tm_sec = bcd2bin(rxbuf[0] & 0x7F);
	tm->tm_min = bcd2bin(rxbuf[1] & 0x7F);
	tm->tm_hour = bcd2bin(rxbuf[2] & 0x3F); /* rtc hr 0-23 */
	tm->tm_mday = bcd2bin(rxbuf[3] & 0x3F);
	tm->tm_wday = rxbuf[4] & 0x07;
	tm->tm_mon = bcd2bin(rxbuf[5] & 0x1F) - 1; /* rtc mn 1-12 */
	tm->tm_year = bcd2bin(rxbuf[6]);
	if (tm->tm_year < 70)
		tm->tm_year += 100;	/* assume we are in 1970...2069 */

	dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
			"mday=%d, mon=%d, year=%d, wday=%d\n",
			__func__,
			tm->tm_sec, tm->tm_min, tm->tm_hour,
			tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);

	return rtc_valid_tm(tm);
}

static int pcf2123_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
	u8 txbuf[8];
	int ret;

	dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
			"mday=%d, mon=%d, year=%d, wday=%d\n",
			__func__,
			tm->tm_sec, tm->tm_min, tm->tm_hour,
			tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);

	/* Stop the counter first */
	ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_STOP);
	if (ret < 0)
		return ret;

	/* Set the new time */
	txbuf[0] = PCF2123_REG_SC;
	txbuf[1] = bin2bcd(tm->tm_sec & 0x7F);
	txbuf[2] = bin2bcd(tm->tm_min & 0x7F);
	txbuf[3] = bin2bcd(tm->tm_hour & 0x3F);
	txbuf[4] = bin2bcd(tm->tm_mday & 0x3F);
	txbuf[5] = tm->tm_wday & 0x07;
	txbuf[6] = bin2bcd((tm->tm_mon + 1) & 0x1F); /* rtc mn 1-12 */
	txbuf[7] = bin2bcd(tm->tm_year < 100 ? tm->tm_year : tm->tm_year - 100);

	ret = pcf2123_write(dev, txbuf, sizeof(txbuf));
	if (ret < 0)
		return ret;

	/* Start the counter */
	ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_CLEAR);
	if (ret < 0)
		return ret;

	return 0;
}

static int pcf2123_reset(struct device *dev)
{
	int ret;
	u8  rxbuf[2];

	ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_SW_RESET);
	if (ret < 0)
		return ret;

	/* Stop the counter */
	dev_dbg(dev, "stopping RTC\n");
	ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_STOP);
	if (ret < 0)
		return ret;

	/* See if the counter was actually stopped */
	dev_dbg(dev, "checking for presence of RTC\n");
	ret = pcf2123_read(dev, PCF2123_REG_CTRL1, rxbuf, sizeof(rxbuf));
	if (ret < 0)
		return ret;

	dev_dbg(dev, "received data from RTC (0x%02X 0x%02X)\n",
		rxbuf[0], rxbuf[1]);
	if (!(rxbuf[0] & CTRL1_STOP))
		return -ENODEV;

	/* Start the counter */
	ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_CLEAR);
	if (ret < 0)
		return ret;

	return 0;
}

static const struct rtc_class_ops pcf2123_rtc_ops = {
	.read_time	= pcf2123_rtc_read_time,
	.set_time	= pcf2123_rtc_set_time,
};

static int pcf2123_probe(struct spi_device *spi)
{
	struct rtc_device *rtc;
	struct rtc_time tm;
	struct pcf2123_plat_data *pdata;
	int ret, i;

	pdata = devm_kzalloc(&spi->dev, sizeof(struct pcf2123_plat_data),
				GFP_KERNEL);
	if (!pdata)
		return -ENOMEM;
	spi->dev.platform_data = pdata;

	ret = pcf2123_rtc_read_time(&spi->dev, &tm);
	if (ret < 0) {
		ret = pcf2123_reset(&spi->dev);
		if (ret < 0) {
			dev_err(&spi->dev, "chip not found\n");
			goto kfree_exit;
		}
	}

	dev_info(&spi->dev, "chip found, driver version " DRV_VERSION "\n");
	dev_info(&spi->dev, "spiclk %u KHz.\n",
			(spi->max_speed_hz + 500) / 1000);

	/* Finalize the initialization */
	rtc = devm_rtc_device_register(&spi->dev, pcf2123_driver.driver.name,
			&pcf2123_rtc_ops, THIS_MODULE);

	if (IS_ERR(rtc)) {
		dev_err(&spi->dev, "failed to register.\n");
		ret = PTR_ERR(rtc);
		goto kfree_exit;
	}

	pdata->rtc = rtc;

	for (i = 0; i < 16; i++) {
		sysfs_attr_init(&pdata->regs[i].attr.attr);
		sprintf(pdata->regs[i].name, "%1x", i);
		pdata->regs[i].attr.attr.mode = S_IRUGO | S_IWUSR;
		pdata->regs[i].attr.attr.name = pdata->regs[i].name;
		pdata->regs[i].attr.show = pcf2123_show;
		pdata->regs[i].attr.store = pcf2123_store;
		ret = device_create_file(&spi->dev, &pdata->regs[i].attr);
		if (ret) {
			dev_err(&spi->dev, "Unable to create sysfs %s\n",
				pdata->regs[i].name);
			goto sysfs_exit;
		}
	}

	return 0;

sysfs_exit:
	for (i--; i >= 0; i--)
		device_remove_file(&spi->dev, &pdata->regs[i].attr);

kfree_exit:
	spi->dev.platform_data = NULL;
	return ret;
}

static int pcf2123_remove(struct spi_device *spi)
{
	struct pcf2123_plat_data *pdata = dev_get_platdata(&spi->dev);
	int i;

	if (pdata) {
		for (i = 0; i < 16; i++)
			if (pdata->regs[i].name[0])
				device_remove_file(&spi->dev,
						   &pdata->regs[i].attr);
	}

	return 0;
}

#ifdef CONFIG_OF
static const struct of_device_id pcf2123_dt_ids[] = {
	{ .compatible = "nxp,rtc-pcf2123", },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, pcf2123_dt_ids);
#endif

static struct spi_driver pcf2123_driver = {
	.driver	= {
			.name	= "rtc-pcf2123",
			.of_match_table = of_match_ptr(pcf2123_dt_ids),
	},
	.probe	= pcf2123_probe,
	.remove	= pcf2123_remove,
};

module_spi_driver(pcf2123_driver);

MODULE_AUTHOR("Chris Verges <chrisv@cyberswitching.com>");
MODULE_DESCRIPTION("NXP PCF2123 RTC driver");
MODULE_LICENSE("GPL");
MODULE_VERSION(DRV_VERSION);
Commit	Line	Data
7f3923a1 CV	1	/*
	2	* An SPI driver for the Philips PCF2123 RTC
	3	* Copyright 2009 Cyber Switching, Inc.
	4	*
	5	* Author: Chris Verges <chrisv@cyberswitching.com>
	6	* Maintainers: http://www.cyberswitching.com
	7	*
	8	* based on the RS5C348 driver in this same directory.
	9	*
	10	* Thanks to Christian Pellegrin <chripell@fsfe.org> for
	11	* the sysfs contributions to this driver.
	12	*
	13	* This program is free software; you can redistribute it and/or modify
	14	* it under the terms of the GNU General Public License version 2 as
	15	* published by the Free Software Foundation.
	16	*
	17	* Please note that the CS is active high, so platform data
	18	* should look something like:
	19	*
	20	* static struct spi_board_info ek_spi_devices[] = {
369015fb SK	21	* ...
	22	* {
	23	* .modalias = "rtc-pcf2123",
	24	* .chip_select = 1,
	25	* .controller_data = (void *)AT91_PIN_PA10,
7f3923a1 CV	26	* .max_speed_hz = 1000 * 1000,
	27	* .mode = SPI_CS_HIGH,
	28	* .bus_num = 0,
	29	* },
	30	* ...
	31	*};
	32	*
	33	*/
	34
	35	#include <linux/bcd.h>
	36	#include <linux/delay.h>
	37	#include <linux/device.h>
	38	#include <linux/errno.h>
	39	#include <linux/init.h>
	40	#include <linux/kernel.h>
3fc70077	41	#include <linux/of.h>
7f3923a1	42	#include <linux/string.h>
5a0e3ad6	43	#include <linux/slab.h>
7f3923a1 CV	44	#include <linux/rtc.h>
7f3923a1 CV	45	#include <linux/spi/spi.h>
2113852b	46	#include <linux/module.h>
5ed12f12	47	#include <linux/sysfs.h>
7f3923a1	48
f3d2570a	49	#define DRV_VERSION "0.6"
7f3923a1	50
245cb74b	51	/* REGISTERS */
7f3923a1 CV	52	#define PCF2123_REG_CTRL1 (0x00) /* Control Register 1 */
	53	#define PCF2123_REG_CTRL2 (0x01) /* Control Register 2 */
	54	#define PCF2123_REG_SC (0x02) /* datetime */
	55	#define PCF2123_REG_MN (0x03)
	56	#define PCF2123_REG_HR (0x04)
	57	#define PCF2123_REG_DM (0x05)
	58	#define PCF2123_REG_DW (0x06)
	59	#define PCF2123_REG_MO (0x07)
	60	#define PCF2123_REG_YR (0x08)
245cb74b JC	61	#define PCF2123_REG_ALRM_MN (0x09) /* Alarm Registers */
	62	#define PCF2123_REG_ALRM_HR (0x0a)
	63	#define PCF2123_REG_ALRM_DM (0x0b)
	64	#define PCF2123_REG_ALRM_DW (0x0c)
	65	#define PCF2123_REG_OFFSET (0x0d) /* Clock Rate Offset Register */
	66	#define PCF2123_REG_TMR_CLKOUT (0x0e) /* Timer Registers */
	67	#define PCF2123_REG_CTDWN_TMR (0x0f)
	68
	69	/* PCF2123_REG_CTRL1 BITS */
	70	#define CTRL1_CLEAR (0) /* Clear */
	71	#define CTRL1_CORR_INT BIT(1) /* Correction irq enable */
	72	#define CTRL1_12_HOUR BIT(2) /* 12 hour time */
	73	#define CTRL1_SW_RESET (BIT(3) \| BIT(4) \| BIT(6)) /* Software reset */
	74	#define CTRL1_STOP BIT(5) /* Stop the clock */
	75	#define CTRL1_EXT_TEST BIT(7) /* External clock test mode */
	76
	77	/* PCF2123_REG_CTRL2 BITS */
	78	#define CTRL2_TIE BIT(0) /* Countdown timer irq enable */
	79	#define CTRL2_AIE BIT(1) /* Alarm irq enable */
	80	#define CTRL2_TF BIT(2) /* Countdown timer flag */
	81	#define CTRL2_AF BIT(3) /* Alarm flag */
	82	#define CTRL2_TI_TP BIT(4) /* Irq pin generates pulse */
	83	#define CTRL2_MSF BIT(5) /* Minute or second irq flag */
	84	#define CTRL2_SI BIT(6) /* Second irq enable */
	85	#define CTRL2_MI BIT(7) /* Minute irq enable */
	86
	87	/* PCF2123_REG_SC BITS */
	88	#define OSC_HAS_STOPPED BIT(7) /* Clock has been stopped */
	89
	90	/* PCF2123_REG_ALRM_XX BITS */
	91	#define ALRM_ENABLE BIT(7) /* MN, HR, DM, or DW alarm enable */
	92
	93	/* PCF2123_REG_TMR_CLKOUT BITS */
	94	#define CD_TMR_4096KHZ (0) /* 4096 KHz countdown timer */
	95	#define CD_TMR_64HZ (1) /* 64 Hz countdown timer */
	96	#define CD_TMR_1HZ (2) /* 1 Hz countdown timer */
	97	#define CD_TMR_60th_HZ (3) /* 60th Hz countdown timer */
	98	#define CD_TMR_TE BIT(3) /* Countdown timer enable */
	99
	100	/* PCF2123_REG_OFFSET BITS */
	101	#define OFFSET_SIGN_BIT BIT(6) /* 2's complement sign bit */
	102	#define OFFSET_COARSE BIT(7) /* Coarse mode offset */
	103
	104	/* READ/WRITE ADDRESS BITS */
	105	#define PCF2123_WRITE BIT(4)
	106	#define PCF2123_READ (BIT(4) \| BIT(7))
7f3923a1	107
7f3923a1 CV	108
	109	static struct spi_driver pcf2123_driver;
	110
	111	struct pcf2123_sysfs_reg {
f3d2570a	112	struct device_attribute attr;
7f3923a1 CV	113	char name[2];
	114	};
	115
	116	struct pcf2123_plat_data {
	117	struct rtc_device *rtc;
	118	struct pcf2123_sysfs_reg regs[16];
	119	};
	120
	121	/*
	122	* Causes a 30 nanosecond delay to ensure that the PCF2123 chip select
	123	* is released properly after an SPI write. This function should be
	124	* called after EVERY read/write call over SPI.
	125	*/
	126	static inline void pcf2123_delay_trec(void)
	127	{
	128	ndelay(30);
	129	}
	130
66c056d6 JC	131	static int pcf2123_read(struct device dev, u8 reg, u8 rxbuf, size_t size)
	132	{
	133	struct spi_device *spi = to_spi_device(dev);
	134	int ret;
	135
	136	reg \|= PCF2123_READ;
	137	ret = spi_write_then_read(spi, &reg, 1, rxbuf, size);
	138	pcf2123_delay_trec();
	139
	140	return ret;
	141	}
	142
809b453b JC	143	static int pcf2123_write(struct device dev, u8 txbuf, size_t size)
	144	{
	145	struct spi_device *spi = to_spi_device(dev);
	146	int ret;
	147
	148	txbuf[0] \|= PCF2123_WRITE;
	149	ret = spi_write(spi, txbuf, size);
	150	pcf2123_delay_trec();
	151
	152	return ret;
	153	}
	154
	155	static int pcf2123_write_reg(struct device *dev, u8 reg, u8 val)
	156	{
	157	u8 txbuf[2];
	158
	159	txbuf[0] = reg;
	160	txbuf[1] = val;
	161	return pcf2123_write(dev, txbuf, sizeof(txbuf));
	162	}
	163
7f3923a1 CV	164	static ssize_t pcf2123_show(struct device dev, struct device_attribute attr,
	165	char *buffer)
	166	{
f3d2570a	167	struct pcf2123_sysfs_reg *r;
66c056d6	168	u8 rxbuf[1];
f3d2570a	169	unsigned long reg;
7f3923a1 CV	170	int ret;
7f3923a1 CV	171
f3d2570a CV	172	r = container_of(attr, struct pcf2123_sysfs_reg, attr);
f3d2570a CV	173
4c5591c1 JH	174	ret = kstrtoul(r->name, 16, &reg);
	175	if (ret)
	176	return ret;
f3d2570a	177
66c056d6	178	ret = pcf2123_read(dev, reg, rxbuf, 1);
7f3923a1	179	if (ret < 0)
f3d2570a	180	return -EIO;
66c056d6	181
f3d2570a	182	return sprintf(buffer, "0x%x\n", rxbuf[0]);
7f3923a1 CV	183	}
	184
	185	static ssize_t pcf2123_store(struct device dev, struct device_attribute attr,
	186	const char *buffer, size_t count) {
f3d2570a	187	struct pcf2123_sysfs_reg *r;
f3d2570a CV	188	unsigned long reg;
	189	unsigned long val;
	190
7f3923a1 CV	191	int ret;
7f3923a1 CV	192
f3d2570a CV	193	r = container_of(attr, struct pcf2123_sysfs_reg, attr);
f3d2570a CV	194
4c5591c1 JH	195	ret = kstrtoul(r->name, 16, &reg);
	196	if (ret)
	197	return ret;
	198
	199	ret = kstrtoul(buffer, 10, &val);
	200	if (ret)
	201	return ret;
f3d2570a	202
809b453b	203	pcf2123_write_reg(dev, reg, val);
7f3923a1 CV	204	if (ret < 0)
7f3923a1 CV	205	return -EIO;
7f3923a1 CV	206	return count;
	207	}
	208
	209	static int pcf2123_rtc_read_time(struct device dev, struct rtc_time tm)
	210	{
66c056d6	211	u8 rxbuf[7];
7f3923a1 CV	212	int ret;
7f3923a1 CV	213
66c056d6	214	ret = pcf2123_read(dev, PCF2123_REG_SC, rxbuf, sizeof(rxbuf));
7f3923a1 CV	215	if (ret < 0)
7f3923a1 CV	216	return ret;
7f3923a1	217
f07fa924 JC	218	if (rxbuf[0] & OSC_HAS_STOPPED) {
	219	dev_info(dev, "clock was stopped. Time is not valid\n");
	220	return -EINVAL;
	221	}
	222
7f3923a1 CV	223	tm->tm_sec = bcd2bin(rxbuf[0] & 0x7F);
	224	tm->tm_min = bcd2bin(rxbuf[1] & 0x7F);
	225	tm->tm_hour = bcd2bin(rxbuf[2] & 0x3F); /* rtc hr 0-23 */
	226	tm->tm_mday = bcd2bin(rxbuf[3] & 0x3F);
	227	tm->tm_wday = rxbuf[4] & 0x07;
	228	tm->tm_mon = bcd2bin(rxbuf[5] & 0x1F) - 1; /* rtc mn 1-12 */
	229	tm->tm_year = bcd2bin(rxbuf[6]);
	230	if (tm->tm_year < 70)
	231	tm->tm_year += 100; /* assume we are in 1970...2069 */
	232
	233	dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
	234	"mday=%d, mon=%d, year=%d, wday=%d\n",
	235	__func__,
	236	tm->tm_sec, tm->tm_min, tm->tm_hour,
	237	tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
	238
821f51c4	239	return rtc_valid_tm(tm);
7f3923a1 CV	240	}
	241
	242	static int pcf2123_rtc_set_time(struct device dev, struct rtc_time tm)
	243	{
7f3923a1 CV	244	u8 txbuf[8];
	245	int ret;
	246
	247	dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
	248	"mday=%d, mon=%d, year=%d, wday=%d\n",
	249	__func__,
	250	tm->tm_sec, tm->tm_min, tm->tm_hour,
	251	tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
	252
	253	/* Stop the counter first */
809b453b	254	ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_STOP);
7f3923a1 CV	255	if (ret < 0)
7f3923a1 CV	256	return ret;
7f3923a1 CV	257
7f3923a1 CV	258	/* Set the new time */
809b453b	259	txbuf[0] = PCF2123_REG_SC;
7f3923a1 CV	260	txbuf[1] = bin2bcd(tm->tm_sec & 0x7F);
	261	txbuf[2] = bin2bcd(tm->tm_min & 0x7F);
	262	txbuf[3] = bin2bcd(tm->tm_hour & 0x3F);
	263	txbuf[4] = bin2bcd(tm->tm_mday & 0x3F);
	264	txbuf[5] = tm->tm_wday & 0x07;
	265	txbuf[6] = bin2bcd((tm->tm_mon + 1) & 0x1F); /* rtc mn 1-12 */
	266	txbuf[7] = bin2bcd(tm->tm_year < 100 ? tm->tm_year : tm->tm_year - 100);
	267
809b453b	268	ret = pcf2123_write(dev, txbuf, sizeof(txbuf));
7f3923a1 CV	269	if (ret < 0)
7f3923a1 CV	270	return ret;
7f3923a1 CV	271
7f3923a1 CV	272	/* Start the counter */
809b453b	273	ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_CLEAR);
7f3923a1 CV	274	if (ret < 0)
7f3923a1 CV	275	return ret;
7f3923a1 CV	276
	277	return 0;
	278	}
	279
1e094b94 JC	280	static int pcf2123_reset(struct device *dev)
	281	{
	282	int ret;
	283	u8 rxbuf[2];
	284
	285	ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_SW_RESET);
	286	if (ret < 0)
	287	return ret;
	288
	289	/* Stop the counter */
	290	dev_dbg(dev, "stopping RTC\n");
	291	ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_STOP);
	292	if (ret < 0)
	293	return ret;
	294
	295	/* See if the counter was actually stopped */
	296	dev_dbg(dev, "checking for presence of RTC\n");
	297	ret = pcf2123_read(dev, PCF2123_REG_CTRL1, rxbuf, sizeof(rxbuf));
	298	if (ret < 0)
	299	return ret;
	300
	301	dev_dbg(dev, "received data from RTC (0x%02X 0x%02X)\n",
	302	rxbuf[0], rxbuf[1]);
	303	if (!(rxbuf[0] & CTRL1_STOP))
	304	return -ENODEV;
	305
	306	/* Start the counter */
	307	ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_CLEAR);
	308	if (ret < 0)
	309	return ret;
	310
	311	return 0;
	312	}
	313
7f3923a1 CV	314	static const struct rtc_class_ops pcf2123_rtc_ops = {
	315	.read_time = pcf2123_rtc_read_time,
	316	.set_time = pcf2123_rtc_set_time,
	317	};
	318
5a167f45	319	static int pcf2123_probe(struct spi_device *spi)
7f3923a1 CV	320	{
7f3923a1 CV	321	struct rtc_device *rtc;
f07fa924	322	struct rtc_time tm;
7f3923a1	323	struct pcf2123_plat_data *pdata;
7f3923a1 CV	324	int ret, i;
7f3923a1 CV	325
dd48ccc4 JH	326	pdata = devm_kzalloc(&spi->dev, sizeof(struct pcf2123_plat_data),
dd48ccc4 JH	327	GFP_KERNEL);
7f3923a1 CV	328	if (!pdata)
	329	return -ENOMEM;
	330	spi->dev.platform_data = pdata;
	331
f07fa924	332	ret = pcf2123_rtc_read_time(&spi->dev, &tm);
1e094b94	333	if (ret < 0) {
f07fa924 JC	334	ret = pcf2123_reset(&spi->dev);
	335	if (ret < 0) {
	336	dev_err(&spi->dev, "chip not found\n");
	337	goto kfree_exit;
	338	}
7f3923a1 CV	339	}
	340
	341	dev_info(&spi->dev, "chip found, driver version " DRV_VERSION "\n");
	342	dev_info(&spi->dev, "spiclk %u KHz.\n",
	343	(spi->max_speed_hz + 500) / 1000);
	344
7f3923a1	345	/* Finalize the initialization */
dd48ccc4	346	rtc = devm_rtc_device_register(&spi->dev, pcf2123_driver.driver.name,
7f3923a1 CV	347	&pcf2123_rtc_ops, THIS_MODULE);
	348
	349	if (IS_ERR(rtc)) {
	350	dev_err(&spi->dev, "failed to register.\n");
	351	ret = PTR_ERR(rtc);
	352	goto kfree_exit;
	353	}
	354
	355	pdata->rtc = rtc;
	356
	357	for (i = 0; i < 16; i++) {
5ed12f12	358	sysfs_attr_init(&pdata->regs[i].attr.attr);
7f3923a1 CV	359	sprintf(pdata->regs[i].name, "%1x", i);
	360	pdata->regs[i].attr.attr.mode = S_IRUGO \| S_IWUSR;
	361	pdata->regs[i].attr.attr.name = pdata->regs[i].name;
	362	pdata->regs[i].attr.show = pcf2123_show;
	363	pdata->regs[i].attr.store = pcf2123_store;
	364	ret = device_create_file(&spi->dev, &pdata->regs[i].attr);
	365	if (ret) {
	366	dev_err(&spi->dev, "Unable to create sysfs %s\n",
	367	pdata->regs[i].name);
f3d2570a	368	goto sysfs_exit;
7f3923a1 CV	369	}
	370	}
	371
	372	return 0;
f3d2570a CV	373
	374	sysfs_exit:
	375	for (i--; i >= 0; i--)
	376	device_remove_file(&spi->dev, &pdata->regs[i].attr);
	377
7f3923a1	378	kfree_exit:
7f3923a1 CV	379	spi->dev.platform_data = NULL;
	380	return ret;
	381	}
	382
5a167f45	383	static int pcf2123_remove(struct spi_device *spi)
7f3923a1	384	{
ffc75bb8	385	struct pcf2123_plat_data *pdata = dev_get_platdata(&spi->dev);
7f3923a1 CV	386	int i;
	387
	388	if (pdata) {
7f3923a1 CV	389	for (i = 0; i < 16; i++)
	390	if (pdata->regs[i].name[0])
	391	device_remove_file(&spi->dev,
	392	&pdata->regs[i].attr);
7f3923a1 CV	393	}
	394
	395	return 0;
	396	}
	397
3fc70077 JC	398	#ifdef CONFIG_OF
	399	static const struct of_device_id pcf2123_dt_ids[] = {
	400	{ .compatible = "nxp,rtc-pcf2123", },
	401	{ /* sentinel */ }
	402	};
	403	MODULE_DEVICE_TABLE(of, pcf2123_dt_ids);
	404	#endif
	405
7f3923a1 CV	406	static struct spi_driver pcf2123_driver = {
	407	.driver = {
	408	.name = "rtc-pcf2123",
3fc70077	409	.of_match_table = of_match_ptr(pcf2123_dt_ids),
7f3923a1 CV	410	},
7f3923a1 CV	411	.probe = pcf2123_probe,
5a167f45	412	.remove = pcf2123_remove,
7f3923a1 CV	413	};
7f3923a1 CV	414
109e9418	415	module_spi_driver(pcf2123_driver);
7f3923a1 CV	416
	417	MODULE_AUTHOR("Chris Verges <chrisv@cyberswitching.com>");
	418	MODULE_DESCRIPTION("NXP PCF2123 RTC driver");
	419	MODULE_LICENSE("GPL");
	420	MODULE_VERSION(DRV_VERSION);