Commit | Line | Data |
---|---|---|
1add6781 | 1 | /* drivers/rtc/rtc-s3c.c |
e48add8c AD |
2 | * |
3 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. | |
4 | * http://www.samsung.com/ | |
1add6781 BD |
5 | * |
6 | * Copyright (c) 2004,2006 Simtec Electronics | |
7 | * Ben Dooks, <ben@simtec.co.uk> | |
8 | * http://armlinux.simtec.co.uk/ | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * S3C2410/S3C2440/S3C24XX Internal RTC Driver | |
15 | */ | |
16 | ||
17 | #include <linux/module.h> | |
18 | #include <linux/fs.h> | |
19 | #include <linux/string.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/rtc.h> | |
24 | #include <linux/bcd.h> | |
25 | #include <linux/clk.h> | |
9974b6ea | 26 | #include <linux/log2.h> |
5a0e3ad6 | 27 | #include <linux/slab.h> |
39ce4084 | 28 | #include <linux/of.h> |
dbd9acbe SK |
29 | #include <linux/uaccess.h> |
30 | #include <linux/io.h> | |
1add6781 | 31 | |
1add6781 | 32 | #include <asm/irq.h> |
b9d7c5d3 | 33 | #include "rtc-s3c.h" |
1add6781 | 34 | |
9f4123b7 MC |
35 | enum s3c_cpu_type { |
36 | TYPE_S3C2410, | |
25c1a246 HS |
37 | TYPE_S3C2416, |
38 | TYPE_S3C2443, | |
9f4123b7 MC |
39 | TYPE_S3C64XX, |
40 | }; | |
41 | ||
c3cba928 TB |
42 | struct s3c_rtc_drv_data { |
43 | int cpu_type; | |
44 | }; | |
45 | ||
1add6781 BD |
46 | /* I have yet to find an S3C implementation with more than one |
47 | * of these rtc blocks in */ | |
48 | ||
e48add8c | 49 | static struct clk *rtc_clk; |
1add6781 | 50 | static void __iomem *s3c_rtc_base; |
ebe75335 PD |
51 | static int s3c_rtc_alarmno; |
52 | static int s3c_rtc_tickno; | |
9f4123b7 | 53 | static enum s3c_cpu_type s3c_rtc_cpu_type; |
1add6781 BD |
54 | |
55 | static DEFINE_SPINLOCK(s3c_rtc_pie_lock); | |
1add6781 | 56 | |
88cee8fd DK |
57 | static void s3c_rtc_alarm_clk_enable(bool enable) |
58 | { | |
59 | static DEFINE_SPINLOCK(s3c_rtc_alarm_clk_lock); | |
60 | static bool alarm_clk_enabled; | |
61 | unsigned long irq_flags; | |
62 | ||
63 | spin_lock_irqsave(&s3c_rtc_alarm_clk_lock, irq_flags); | |
64 | if (enable) { | |
65 | if (!alarm_clk_enabled) { | |
66 | clk_enable(rtc_clk); | |
67 | alarm_clk_enabled = true; | |
68 | } | |
69 | } else { | |
70 | if (alarm_clk_enabled) { | |
71 | clk_disable(rtc_clk); | |
72 | alarm_clk_enabled = false; | |
73 | } | |
74 | } | |
75 | spin_unlock_irqrestore(&s3c_rtc_alarm_clk_lock, irq_flags); | |
76 | } | |
77 | ||
1add6781 BD |
78 | /* IRQ Handlers */ |
79 | ||
7d12e780 | 80 | static irqreturn_t s3c_rtc_alarmirq(int irq, void *id) |
1add6781 BD |
81 | { |
82 | struct rtc_device *rdev = id; | |
83 | ||
cefe4fbb | 84 | clk_enable(rtc_clk); |
ab6a2d70 | 85 | rtc_update_irq(rdev, 1, RTC_AF | RTC_IRQF); |
2f3478f6 AD |
86 | |
87 | if (s3c_rtc_cpu_type == TYPE_S3C64XX) | |
88 | writeb(S3C2410_INTP_ALM, s3c_rtc_base + S3C2410_INTP); | |
89 | ||
cefe4fbb | 90 | clk_disable(rtc_clk); |
88cee8fd DK |
91 | |
92 | s3c_rtc_alarm_clk_enable(false); | |
93 | ||
1add6781 BD |
94 | return IRQ_HANDLED; |
95 | } | |
96 | ||
7d12e780 | 97 | static irqreturn_t s3c_rtc_tickirq(int irq, void *id) |
1add6781 BD |
98 | { |
99 | struct rtc_device *rdev = id; | |
100 | ||
cefe4fbb | 101 | clk_enable(rtc_clk); |
773be7ee | 102 | rtc_update_irq(rdev, 1, RTC_PF | RTC_IRQF); |
2f3478f6 AD |
103 | |
104 | if (s3c_rtc_cpu_type == TYPE_S3C64XX) | |
105 | writeb(S3C2410_INTP_TIC, s3c_rtc_base + S3C2410_INTP); | |
106 | ||
cefe4fbb | 107 | clk_disable(rtc_clk); |
1add6781 BD |
108 | return IRQ_HANDLED; |
109 | } | |
110 | ||
111 | /* Update control registers */ | |
2ec38a03 | 112 | static int s3c_rtc_setaie(struct device *dev, unsigned int enabled) |
1add6781 BD |
113 | { |
114 | unsigned int tmp; | |
115 | ||
d4a48c2a | 116 | dev_dbg(dev, "%s: aie=%d\n", __func__, enabled); |
1add6781 | 117 | |
cefe4fbb | 118 | clk_enable(rtc_clk); |
9a654518 | 119 | tmp = readb(s3c_rtc_base + S3C2410_RTCALM) & ~S3C2410_RTCALM_ALMEN; |
1add6781 | 120 | |
2ec38a03 | 121 | if (enabled) |
1add6781 BD |
122 | tmp |= S3C2410_RTCALM_ALMEN; |
123 | ||
9a654518 | 124 | writeb(tmp, s3c_rtc_base + S3C2410_RTCALM); |
cefe4fbb | 125 | clk_disable(rtc_clk); |
2ec38a03 | 126 | |
88cee8fd DK |
127 | s3c_rtc_alarm_clk_enable(enabled); |
128 | ||
2ec38a03 | 129 | return 0; |
1add6781 BD |
130 | } |
131 | ||
773be7ee | 132 | static int s3c_rtc_setfreq(struct device *dev, int freq) |
1add6781 | 133 | { |
9f4123b7 MC |
134 | struct platform_device *pdev = to_platform_device(dev); |
135 | struct rtc_device *rtc_dev = platform_get_drvdata(pdev); | |
136 | unsigned int tmp = 0; | |
25c1a246 | 137 | int val; |
1add6781 | 138 | |
5d2a5037 JC |
139 | if (!is_power_of_2(freq)) |
140 | return -EINVAL; | |
141 | ||
cefe4fbb | 142 | clk_enable(rtc_clk); |
1add6781 | 143 | spin_lock_irq(&s3c_rtc_pie_lock); |
1add6781 | 144 | |
25c1a246 | 145 | if (s3c_rtc_cpu_type != TYPE_S3C64XX) { |
9f4123b7 MC |
146 | tmp = readb(s3c_rtc_base + S3C2410_TICNT); |
147 | tmp &= S3C2410_TICNT_ENABLE; | |
148 | } | |
149 | ||
25c1a246 HS |
150 | val = (rtc_dev->max_user_freq / freq) - 1; |
151 | ||
152 | if (s3c_rtc_cpu_type == TYPE_S3C2416 || s3c_rtc_cpu_type == TYPE_S3C2443) { | |
153 | tmp |= S3C2443_TICNT_PART(val); | |
154 | writel(S3C2443_TICNT1_PART(val), s3c_rtc_base + S3C2443_TICNT1); | |
155 | ||
156 | if (s3c_rtc_cpu_type == TYPE_S3C2416) | |
157 | writel(S3C2416_TICNT2_PART(val), s3c_rtc_base + S3C2416_TICNT2); | |
158 | } else { | |
159 | tmp |= val; | |
160 | } | |
1add6781 | 161 | |
2f3478f6 | 162 | writel(tmp, s3c_rtc_base + S3C2410_TICNT); |
1add6781 | 163 | spin_unlock_irq(&s3c_rtc_pie_lock); |
cefe4fbb | 164 | clk_disable(rtc_clk); |
773be7ee BD |
165 | |
166 | return 0; | |
1add6781 BD |
167 | } |
168 | ||
169 | /* Time read/write */ | |
170 | ||
171 | static int s3c_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm) | |
172 | { | |
173 | unsigned int have_retried = 0; | |
9a654518 | 174 | void __iomem *base = s3c_rtc_base; |
1add6781 | 175 | |
cefe4fbb | 176 | clk_enable(rtc_clk); |
1add6781 | 177 | retry_get_time: |
9a654518 BD |
178 | rtc_tm->tm_min = readb(base + S3C2410_RTCMIN); |
179 | rtc_tm->tm_hour = readb(base + S3C2410_RTCHOUR); | |
180 | rtc_tm->tm_mday = readb(base + S3C2410_RTCDATE); | |
181 | rtc_tm->tm_mon = readb(base + S3C2410_RTCMON); | |
182 | rtc_tm->tm_year = readb(base + S3C2410_RTCYEAR); | |
183 | rtc_tm->tm_sec = readb(base + S3C2410_RTCSEC); | |
1add6781 | 184 | |
48fc7f7e | 185 | /* the only way to work out whether the system was mid-update |
1add6781 BD |
186 | * when we read it is to check the second counter, and if it |
187 | * is zero, then we re-try the entire read | |
188 | */ | |
189 | ||
190 | if (rtc_tm->tm_sec == 0 && !have_retried) { | |
191 | have_retried = 1; | |
192 | goto retry_get_time; | |
193 | } | |
194 | ||
fe20ba70 AB |
195 | rtc_tm->tm_sec = bcd2bin(rtc_tm->tm_sec); |
196 | rtc_tm->tm_min = bcd2bin(rtc_tm->tm_min); | |
197 | rtc_tm->tm_hour = bcd2bin(rtc_tm->tm_hour); | |
198 | rtc_tm->tm_mday = bcd2bin(rtc_tm->tm_mday); | |
199 | rtc_tm->tm_mon = bcd2bin(rtc_tm->tm_mon); | |
200 | rtc_tm->tm_year = bcd2bin(rtc_tm->tm_year); | |
1add6781 BD |
201 | |
202 | rtc_tm->tm_year += 100; | |
4e8896cd | 203 | |
d4a48c2a | 204 | dev_dbg(dev, "read time %04d.%02d.%02d %02d:%02d:%02d\n", |
4e8896cd MH |
205 | 1900 + rtc_tm->tm_year, rtc_tm->tm_mon, rtc_tm->tm_mday, |
206 | rtc_tm->tm_hour, rtc_tm->tm_min, rtc_tm->tm_sec); | |
207 | ||
1add6781 BD |
208 | rtc_tm->tm_mon -= 1; |
209 | ||
cefe4fbb | 210 | clk_disable(rtc_clk); |
5b3ffddd | 211 | return rtc_valid_tm(rtc_tm); |
1add6781 BD |
212 | } |
213 | ||
214 | static int s3c_rtc_settime(struct device *dev, struct rtc_time *tm) | |
215 | { | |
9a654518 | 216 | void __iomem *base = s3c_rtc_base; |
641741e0 | 217 | int year = tm->tm_year - 100; |
9a654518 | 218 | |
d4a48c2a | 219 | dev_dbg(dev, "set time %04d.%02d.%02d %02d:%02d:%02d\n", |
30ffc40c | 220 | 1900 + tm->tm_year, tm->tm_mon, tm->tm_mday, |
641741e0 BD |
221 | tm->tm_hour, tm->tm_min, tm->tm_sec); |
222 | ||
223 | /* we get around y2k by simply not supporting it */ | |
1add6781 | 224 | |
641741e0 | 225 | if (year < 0 || year >= 100) { |
9a654518 | 226 | dev_err(dev, "rtc only supports 100 years\n"); |
1add6781 | 227 | return -EINVAL; |
9a654518 BD |
228 | } |
229 | ||
2dbcd05f | 230 | clk_enable(rtc_clk); |
fe20ba70 AB |
231 | writeb(bin2bcd(tm->tm_sec), base + S3C2410_RTCSEC); |
232 | writeb(bin2bcd(tm->tm_min), base + S3C2410_RTCMIN); | |
233 | writeb(bin2bcd(tm->tm_hour), base + S3C2410_RTCHOUR); | |
234 | writeb(bin2bcd(tm->tm_mday), base + S3C2410_RTCDATE); | |
235 | writeb(bin2bcd(tm->tm_mon + 1), base + S3C2410_RTCMON); | |
236 | writeb(bin2bcd(year), base + S3C2410_RTCYEAR); | |
cefe4fbb | 237 | clk_disable(rtc_clk); |
1add6781 BD |
238 | |
239 | return 0; | |
240 | } | |
241 | ||
242 | static int s3c_rtc_getalarm(struct device *dev, struct rtc_wkalrm *alrm) | |
243 | { | |
244 | struct rtc_time *alm_tm = &alrm->time; | |
9a654518 | 245 | void __iomem *base = s3c_rtc_base; |
1add6781 BD |
246 | unsigned int alm_en; |
247 | ||
cefe4fbb | 248 | clk_enable(rtc_clk); |
9a654518 BD |
249 | alm_tm->tm_sec = readb(base + S3C2410_ALMSEC); |
250 | alm_tm->tm_min = readb(base + S3C2410_ALMMIN); | |
251 | alm_tm->tm_hour = readb(base + S3C2410_ALMHOUR); | |
252 | alm_tm->tm_mon = readb(base + S3C2410_ALMMON); | |
253 | alm_tm->tm_mday = readb(base + S3C2410_ALMDATE); | |
254 | alm_tm->tm_year = readb(base + S3C2410_ALMYEAR); | |
1add6781 | 255 | |
9a654518 | 256 | alm_en = readb(base + S3C2410_RTCALM); |
1add6781 | 257 | |
a2db8dfc DB |
258 | alrm->enabled = (alm_en & S3C2410_RTCALM_ALMEN) ? 1 : 0; |
259 | ||
d4a48c2a | 260 | dev_dbg(dev, "read alarm %d, %04d.%02d.%02d %02d:%02d:%02d\n", |
1add6781 | 261 | alm_en, |
30ffc40c | 262 | 1900 + alm_tm->tm_year, alm_tm->tm_mon, alm_tm->tm_mday, |
1add6781 BD |
263 | alm_tm->tm_hour, alm_tm->tm_min, alm_tm->tm_sec); |
264 | ||
265 | ||
266 | /* decode the alarm enable field */ | |
267 | ||
268 | if (alm_en & S3C2410_RTCALM_SECEN) | |
fe20ba70 | 269 | alm_tm->tm_sec = bcd2bin(alm_tm->tm_sec); |
1add6781 | 270 | else |
dd061d1a | 271 | alm_tm->tm_sec = -1; |
1add6781 BD |
272 | |
273 | if (alm_en & S3C2410_RTCALM_MINEN) | |
fe20ba70 | 274 | alm_tm->tm_min = bcd2bin(alm_tm->tm_min); |
1add6781 | 275 | else |
dd061d1a | 276 | alm_tm->tm_min = -1; |
1add6781 BD |
277 | |
278 | if (alm_en & S3C2410_RTCALM_HOUREN) | |
fe20ba70 | 279 | alm_tm->tm_hour = bcd2bin(alm_tm->tm_hour); |
1add6781 | 280 | else |
dd061d1a | 281 | alm_tm->tm_hour = -1; |
1add6781 BD |
282 | |
283 | if (alm_en & S3C2410_RTCALM_DAYEN) | |
fe20ba70 | 284 | alm_tm->tm_mday = bcd2bin(alm_tm->tm_mday); |
1add6781 | 285 | else |
dd061d1a | 286 | alm_tm->tm_mday = -1; |
1add6781 BD |
287 | |
288 | if (alm_en & S3C2410_RTCALM_MONEN) { | |
fe20ba70 | 289 | alm_tm->tm_mon = bcd2bin(alm_tm->tm_mon); |
1add6781 BD |
290 | alm_tm->tm_mon -= 1; |
291 | } else { | |
dd061d1a | 292 | alm_tm->tm_mon = -1; |
1add6781 BD |
293 | } |
294 | ||
295 | if (alm_en & S3C2410_RTCALM_YEAREN) | |
fe20ba70 | 296 | alm_tm->tm_year = bcd2bin(alm_tm->tm_year); |
1add6781 | 297 | else |
dd061d1a | 298 | alm_tm->tm_year = -1; |
1add6781 | 299 | |
cefe4fbb | 300 | clk_disable(rtc_clk); |
1add6781 BD |
301 | return 0; |
302 | } | |
303 | ||
304 | static int s3c_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm) | |
305 | { | |
306 | struct rtc_time *tm = &alrm->time; | |
9a654518 | 307 | void __iomem *base = s3c_rtc_base; |
1add6781 BD |
308 | unsigned int alrm_en; |
309 | ||
cefe4fbb | 310 | clk_enable(rtc_clk); |
d4a48c2a | 311 | dev_dbg(dev, "s3c_rtc_setalarm: %d, %04d.%02d.%02d %02d:%02d:%02d\n", |
1add6781 | 312 | alrm->enabled, |
4e8896cd | 313 | 1900 + tm->tm_year, tm->tm_mon + 1, tm->tm_mday, |
30ffc40c | 314 | tm->tm_hour, tm->tm_min, tm->tm_sec); |
1add6781 | 315 | |
9a654518 BD |
316 | alrm_en = readb(base + S3C2410_RTCALM) & S3C2410_RTCALM_ALMEN; |
317 | writeb(0x00, base + S3C2410_RTCALM); | |
1add6781 BD |
318 | |
319 | if (tm->tm_sec < 60 && tm->tm_sec >= 0) { | |
320 | alrm_en |= S3C2410_RTCALM_SECEN; | |
fe20ba70 | 321 | writeb(bin2bcd(tm->tm_sec), base + S3C2410_ALMSEC); |
1add6781 BD |
322 | } |
323 | ||
324 | if (tm->tm_min < 60 && tm->tm_min >= 0) { | |
325 | alrm_en |= S3C2410_RTCALM_MINEN; | |
fe20ba70 | 326 | writeb(bin2bcd(tm->tm_min), base + S3C2410_ALMMIN); |
1add6781 BD |
327 | } |
328 | ||
329 | if (tm->tm_hour < 24 && tm->tm_hour >= 0) { | |
330 | alrm_en |= S3C2410_RTCALM_HOUREN; | |
fe20ba70 | 331 | writeb(bin2bcd(tm->tm_hour), base + S3C2410_ALMHOUR); |
1add6781 BD |
332 | } |
333 | ||
d4a48c2a | 334 | dev_dbg(dev, "setting S3C2410_RTCALM to %08x\n", alrm_en); |
1add6781 | 335 | |
9a654518 | 336 | writeb(alrm_en, base + S3C2410_RTCALM); |
1add6781 | 337 | |
2ec38a03 | 338 | s3c_rtc_setaie(dev, alrm->enabled); |
1add6781 | 339 | |
cefe4fbb | 340 | clk_disable(rtc_clk); |
1add6781 BD |
341 | return 0; |
342 | } | |
343 | ||
1add6781 BD |
344 | static int s3c_rtc_proc(struct device *dev, struct seq_file *seq) |
345 | { | |
9f4123b7 | 346 | unsigned int ticnt; |
1add6781 | 347 | |
cefe4fbb | 348 | clk_enable(rtc_clk); |
9f4123b7 | 349 | if (s3c_rtc_cpu_type == TYPE_S3C64XX) { |
f61ae671 | 350 | ticnt = readw(s3c_rtc_base + S3C2410_RTCCON); |
9f4123b7 MC |
351 | ticnt &= S3C64XX_RTCCON_TICEN; |
352 | } else { | |
353 | ticnt = readb(s3c_rtc_base + S3C2410_TICNT); | |
354 | ticnt &= S3C2410_TICNT_ENABLE; | |
355 | } | |
356 | ||
357 | seq_printf(seq, "periodic_IRQ\t: %s\n", ticnt ? "yes" : "no"); | |
cefe4fbb | 358 | clk_disable(rtc_clk); |
1add6781 BD |
359 | return 0; |
360 | } | |
361 | ||
ff8371ac | 362 | static const struct rtc_class_ops s3c_rtcops = { |
1add6781 BD |
363 | .read_time = s3c_rtc_gettime, |
364 | .set_time = s3c_rtc_settime, | |
365 | .read_alarm = s3c_rtc_getalarm, | |
366 | .set_alarm = s3c_rtc_setalarm, | |
e6eb524e CY |
367 | .proc = s3c_rtc_proc, |
368 | .alarm_irq_enable = s3c_rtc_setaie, | |
1add6781 BD |
369 | }; |
370 | ||
371 | static void s3c_rtc_enable(struct platform_device *pdev, int en) | |
372 | { | |
9a654518 | 373 | void __iomem *base = s3c_rtc_base; |
1add6781 BD |
374 | unsigned int tmp; |
375 | ||
376 | if (s3c_rtc_base == NULL) | |
377 | return; | |
378 | ||
cefe4fbb | 379 | clk_enable(rtc_clk); |
1add6781 | 380 | if (!en) { |
f61ae671 | 381 | tmp = readw(base + S3C2410_RTCCON); |
9f4123b7 MC |
382 | if (s3c_rtc_cpu_type == TYPE_S3C64XX) |
383 | tmp &= ~S3C64XX_RTCCON_TICEN; | |
384 | tmp &= ~S3C2410_RTCCON_RTCEN; | |
f61ae671 | 385 | writew(tmp, base + S3C2410_RTCCON); |
9f4123b7 | 386 | |
25c1a246 | 387 | if (s3c_rtc_cpu_type != TYPE_S3C64XX) { |
9f4123b7 MC |
388 | tmp = readb(base + S3C2410_TICNT); |
389 | tmp &= ~S3C2410_TICNT_ENABLE; | |
390 | writeb(tmp, base + S3C2410_TICNT); | |
391 | } | |
1add6781 BD |
392 | } else { |
393 | /* re-enable the device, and check it is ok */ | |
394 | ||
f61ae671 | 395 | if ((readw(base+S3C2410_RTCCON) & S3C2410_RTCCON_RTCEN) == 0) { |
1add6781 BD |
396 | dev_info(&pdev->dev, "rtc disabled, re-enabling\n"); |
397 | ||
f61ae671 CY |
398 | tmp = readw(base + S3C2410_RTCCON); |
399 | writew(tmp | S3C2410_RTCCON_RTCEN, | |
400 | base + S3C2410_RTCCON); | |
1add6781 BD |
401 | } |
402 | ||
f61ae671 | 403 | if ((readw(base + S3C2410_RTCCON) & S3C2410_RTCCON_CNTSEL)) { |
1add6781 BD |
404 | dev_info(&pdev->dev, "removing RTCCON_CNTSEL\n"); |
405 | ||
f61ae671 CY |
406 | tmp = readw(base + S3C2410_RTCCON); |
407 | writew(tmp & ~S3C2410_RTCCON_CNTSEL, | |
408 | base + S3C2410_RTCCON); | |
1add6781 BD |
409 | } |
410 | ||
f61ae671 | 411 | if ((readw(base + S3C2410_RTCCON) & S3C2410_RTCCON_CLKRST)) { |
1add6781 BD |
412 | dev_info(&pdev->dev, "removing RTCCON_CLKRST\n"); |
413 | ||
f61ae671 CY |
414 | tmp = readw(base + S3C2410_RTCCON); |
415 | writew(tmp & ~S3C2410_RTCCON_CLKRST, | |
416 | base + S3C2410_RTCCON); | |
1add6781 BD |
417 | } |
418 | } | |
cefe4fbb | 419 | clk_disable(rtc_clk); |
1add6781 BD |
420 | } |
421 | ||
5a167f45 | 422 | static int s3c_rtc_remove(struct platform_device *dev) |
1add6781 | 423 | { |
2ec38a03 | 424 | s3c_rtc_setaie(&dev->dev, 0); |
1add6781 | 425 | |
1a3224f1 | 426 | clk_unprepare(rtc_clk); |
e48add8c AD |
427 | rtc_clk = NULL; |
428 | ||
1add6781 BD |
429 | return 0; |
430 | } | |
431 | ||
d2524caa HS |
432 | static const struct of_device_id s3c_rtc_dt_match[]; |
433 | ||
434 | static inline int s3c_rtc_get_driver_data(struct platform_device *pdev) | |
435 | { | |
436 | #ifdef CONFIG_OF | |
c3cba928 | 437 | struct s3c_rtc_drv_data *data; |
d2524caa HS |
438 | if (pdev->dev.of_node) { |
439 | const struct of_device_id *match; | |
440 | match = of_match_node(s3c_rtc_dt_match, pdev->dev.of_node); | |
c3cba928 TB |
441 | data = (struct s3c_rtc_drv_data *) match->data; |
442 | return data->cpu_type; | |
d2524caa HS |
443 | } |
444 | #endif | |
445 | return platform_get_device_id(pdev)->driver_data; | |
446 | } | |
447 | ||
5a167f45 | 448 | static int s3c_rtc_probe(struct platform_device *pdev) |
1add6781 BD |
449 | { |
450 | struct rtc_device *rtc; | |
e1df962e | 451 | struct rtc_time rtc_tm; |
1add6781 BD |
452 | struct resource *res; |
453 | int ret; | |
25c1a246 | 454 | int tmp; |
1add6781 | 455 | |
d4a48c2a | 456 | dev_dbg(&pdev->dev, "%s: probe=%p\n", __func__, pdev); |
1add6781 BD |
457 | |
458 | /* find the IRQs */ | |
459 | ||
460 | s3c_rtc_tickno = platform_get_irq(pdev, 1); | |
461 | if (s3c_rtc_tickno < 0) { | |
462 | dev_err(&pdev->dev, "no irq for rtc tick\n"); | |
1ee8c0ca | 463 | return s3c_rtc_tickno; |
1add6781 BD |
464 | } |
465 | ||
466 | s3c_rtc_alarmno = platform_get_irq(pdev, 0); | |
467 | if (s3c_rtc_alarmno < 0) { | |
468 | dev_err(&pdev->dev, "no irq for alarm\n"); | |
1ee8c0ca | 469 | return s3c_rtc_alarmno; |
1add6781 BD |
470 | } |
471 | ||
d4a48c2a | 472 | dev_dbg(&pdev->dev, "s3c2410_rtc: tick irq %d, alarm irq %d\n", |
1add6781 BD |
473 | s3c_rtc_tickno, s3c_rtc_alarmno); |
474 | ||
475 | /* get the memory region */ | |
476 | ||
477 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
8cbce1e5 TR |
478 | s3c_rtc_base = devm_ioremap_resource(&pdev->dev, res); |
479 | if (IS_ERR(s3c_rtc_base)) | |
480 | return PTR_ERR(s3c_rtc_base); | |
1add6781 | 481 | |
1b997329 | 482 | rtc_clk = devm_clk_get(&pdev->dev, "rtc"); |
e48add8c AD |
483 | if (IS_ERR(rtc_clk)) { |
484 | dev_err(&pdev->dev, "failed to find rtc clock source\n"); | |
485 | ret = PTR_ERR(rtc_clk); | |
486 | rtc_clk = NULL; | |
1b997329 | 487 | return ret; |
e48add8c AD |
488 | } |
489 | ||
1a3224f1 | 490 | clk_prepare_enable(rtc_clk); |
e48add8c | 491 | |
1add6781 BD |
492 | /* check to see if everything is setup correctly */ |
493 | ||
494 | s3c_rtc_enable(pdev, 1); | |
495 | ||
d4a48c2a | 496 | dev_dbg(&pdev->dev, "s3c2410_rtc: RTCCON=%02x\n", |
f61ae671 | 497 | readw(s3c_rtc_base + S3C2410_RTCCON)); |
1add6781 | 498 | |
51b7616e YK |
499 | device_init_wakeup(&pdev->dev, 1); |
500 | ||
1add6781 BD |
501 | /* register RTC and exit */ |
502 | ||
4c99c13a | 503 | rtc = devm_rtc_device_register(&pdev->dev, "s3c", &s3c_rtcops, |
1add6781 BD |
504 | THIS_MODULE); |
505 | ||
506 | if (IS_ERR(rtc)) { | |
507 | dev_err(&pdev->dev, "cannot attach rtc\n"); | |
508 | ret = PTR_ERR(rtc); | |
509 | goto err_nortc; | |
510 | } | |
511 | ||
d2524caa | 512 | s3c_rtc_cpu_type = s3c_rtc_get_driver_data(pdev); |
eaa6e4dd | 513 | |
051fe54e TK |
514 | /* Check RTC Time */ |
515 | ||
e1df962e | 516 | s3c_rtc_gettime(NULL, &rtc_tm); |
051fe54e | 517 | |
e1df962e CY |
518 | if (rtc_valid_tm(&rtc_tm)) { |
519 | rtc_tm.tm_year = 100; | |
520 | rtc_tm.tm_mon = 0; | |
521 | rtc_tm.tm_mday = 1; | |
522 | rtc_tm.tm_hour = 0; | |
523 | rtc_tm.tm_min = 0; | |
524 | rtc_tm.tm_sec = 0; | |
525 | ||
526 | s3c_rtc_settime(NULL, &rtc_tm); | |
527 | ||
528 | dev_warn(&pdev->dev, "warning: invalid RTC value so initializing it\n"); | |
051fe54e TK |
529 | } |
530 | ||
25c1a246 | 531 | if (s3c_rtc_cpu_type != TYPE_S3C2410) |
9f4123b7 MC |
532 | rtc->max_user_freq = 32768; |
533 | else | |
534 | rtc->max_user_freq = 128; | |
535 | ||
25c1a246 HS |
536 | if (s3c_rtc_cpu_type == TYPE_S3C2416 || s3c_rtc_cpu_type == TYPE_S3C2443) { |
537 | tmp = readw(s3c_rtc_base + S3C2410_RTCCON); | |
538 | tmp |= S3C2443_RTCCON_TICSEL; | |
539 | writew(tmp, s3c_rtc_base + S3C2410_RTCCON); | |
540 | } | |
541 | ||
1add6781 | 542 | platform_set_drvdata(pdev, rtc); |
e893de59 MC |
543 | |
544 | s3c_rtc_setfreq(&pdev->dev, 1); | |
545 | ||
1b997329 | 546 | ret = devm_request_irq(&pdev->dev, s3c_rtc_alarmno, s3c_rtc_alarmirq, |
2f6e5f94 | 547 | 0, "s3c2410-rtc alarm", rtc); |
62d17601 MH |
548 | if (ret) { |
549 | dev_err(&pdev->dev, "IRQ%d error %d\n", s3c_rtc_alarmno, ret); | |
fb9b525e | 550 | goto err_nortc; |
62d17601 MH |
551 | } |
552 | ||
1b997329 | 553 | ret = devm_request_irq(&pdev->dev, s3c_rtc_tickno, s3c_rtc_tickirq, |
2f6e5f94 | 554 | 0, "s3c2410-rtc tick", rtc); |
62d17601 MH |
555 | if (ret) { |
556 | dev_err(&pdev->dev, "IRQ%d error %d\n", s3c_rtc_tickno, ret); | |
fb9b525e | 557 | goto err_nortc; |
62d17601 MH |
558 | } |
559 | ||
cefe4fbb DK |
560 | clk_disable(rtc_clk); |
561 | ||
1add6781 BD |
562 | return 0; |
563 | ||
564 | err_nortc: | |
565 | s3c_rtc_enable(pdev, 0); | |
1a3224f1 | 566 | clk_disable_unprepare(rtc_clk); |
1add6781 | 567 | |
1add6781 BD |
568 | return ret; |
569 | } | |
570 | ||
32e445aa | 571 | #ifdef CONFIG_PM_SLEEP |
1add6781 BD |
572 | /* RTC Power management control */ |
573 | ||
9f4123b7 | 574 | static int ticnt_save, ticnt_en_save; |
32e445aa | 575 | static bool wake_en; |
1add6781 | 576 | |
32e445aa | 577 | static int s3c_rtc_suspend(struct device *dev) |
1add6781 | 578 | { |
32e445aa JH |
579 | struct platform_device *pdev = to_platform_device(dev); |
580 | ||
cefe4fbb | 581 | clk_enable(rtc_clk); |
1add6781 | 582 | /* save TICNT for anyone using periodic interrupts */ |
9f4123b7 | 583 | if (s3c_rtc_cpu_type == TYPE_S3C64XX) { |
f61ae671 | 584 | ticnt_en_save = readw(s3c_rtc_base + S3C2410_RTCCON); |
9f4123b7 | 585 | ticnt_en_save &= S3C64XX_RTCCON_TICEN; |
40d2d968 VS |
586 | ticnt_save = readl(s3c_rtc_base + S3C2410_TICNT); |
587 | } else { | |
588 | ticnt_save = readb(s3c_rtc_base + S3C2410_TICNT); | |
9f4123b7 | 589 | } |
1add6781 | 590 | s3c_rtc_enable(pdev, 0); |
f501ed52 | 591 | |
32e445aa | 592 | if (device_may_wakeup(dev) && !wake_en) { |
52cd4e5c BD |
593 | if (enable_irq_wake(s3c_rtc_alarmno) == 0) |
594 | wake_en = true; | |
595 | else | |
32e445aa | 596 | dev_err(dev, "enable_irq_wake failed\n"); |
52cd4e5c | 597 | } |
cefe4fbb | 598 | clk_disable(rtc_clk); |
f501ed52 | 599 | |
1add6781 BD |
600 | return 0; |
601 | } | |
602 | ||
32e445aa | 603 | static int s3c_rtc_resume(struct device *dev) |
1add6781 | 604 | { |
32e445aa | 605 | struct platform_device *pdev = to_platform_device(dev); |
9f4123b7 MC |
606 | unsigned int tmp; |
607 | ||
cefe4fbb | 608 | clk_enable(rtc_clk); |
1add6781 | 609 | s3c_rtc_enable(pdev, 1); |
40d2d968 VS |
610 | if (s3c_rtc_cpu_type == TYPE_S3C64XX) { |
611 | writel(ticnt_save, s3c_rtc_base + S3C2410_TICNT); | |
612 | if (ticnt_en_save) { | |
613 | tmp = readw(s3c_rtc_base + S3C2410_RTCCON); | |
614 | writew(tmp | ticnt_en_save, | |
615 | s3c_rtc_base + S3C2410_RTCCON); | |
616 | } | |
617 | } else { | |
618 | writeb(ticnt_save, s3c_rtc_base + S3C2410_TICNT); | |
9f4123b7 | 619 | } |
f501ed52 | 620 | |
32e445aa | 621 | if (device_may_wakeup(dev) && wake_en) { |
f501ed52 | 622 | disable_irq_wake(s3c_rtc_alarmno); |
52cd4e5c BD |
623 | wake_en = false; |
624 | } | |
cefe4fbb | 625 | clk_disable(rtc_clk); |
f501ed52 | 626 | |
1add6781 BD |
627 | return 0; |
628 | } | |
1add6781 BD |
629 | #endif |
630 | ||
32e445aa JH |
631 | static SIMPLE_DEV_PM_OPS(s3c_rtc_pm_ops, s3c_rtc_suspend, s3c_rtc_resume); |
632 | ||
ecb41a77 | 633 | #ifdef CONFIG_OF |
c3cba928 TB |
634 | static struct s3c_rtc_drv_data s3c_rtc_drv_data_array[] = { |
635 | [TYPE_S3C2410] = { TYPE_S3C2410 }, | |
636 | [TYPE_S3C2416] = { TYPE_S3C2416 }, | |
637 | [TYPE_S3C2443] = { TYPE_S3C2443 }, | |
638 | [TYPE_S3C64XX] = { TYPE_S3C64XX }, | |
639 | }; | |
640 | ||
39ce4084 | 641 | static const struct of_device_id s3c_rtc_dt_match[] = { |
d2524caa | 642 | { |
cd1e6f9e | 643 | .compatible = "samsung,s3c2410-rtc", |
c3cba928 | 644 | .data = &s3c_rtc_drv_data_array[TYPE_S3C2410], |
25c1a246 | 645 | }, { |
cd1e6f9e | 646 | .compatible = "samsung,s3c2416-rtc", |
c3cba928 | 647 | .data = &s3c_rtc_drv_data_array[TYPE_S3C2416], |
25c1a246 | 648 | }, { |
cd1e6f9e | 649 | .compatible = "samsung,s3c2443-rtc", |
c3cba928 | 650 | .data = &s3c_rtc_drv_data_array[TYPE_S3C2443], |
d2524caa | 651 | }, { |
cd1e6f9e | 652 | .compatible = "samsung,s3c6410-rtc", |
c3cba928 | 653 | .data = &s3c_rtc_drv_data_array[TYPE_S3C64XX], |
d2524caa | 654 | }, |
39ce4084 TA |
655 | {}, |
656 | }; | |
657 | MODULE_DEVICE_TABLE(of, s3c_rtc_dt_match); | |
39ce4084 TA |
658 | #endif |
659 | ||
9f4123b7 MC |
660 | static struct platform_device_id s3c_rtc_driver_ids[] = { |
661 | { | |
662 | .name = "s3c2410-rtc", | |
663 | .driver_data = TYPE_S3C2410, | |
25c1a246 HS |
664 | }, { |
665 | .name = "s3c2416-rtc", | |
666 | .driver_data = TYPE_S3C2416, | |
667 | }, { | |
668 | .name = "s3c2443-rtc", | |
669 | .driver_data = TYPE_S3C2443, | |
9f4123b7 MC |
670 | }, { |
671 | .name = "s3c64xx-rtc", | |
672 | .driver_data = TYPE_S3C64XX, | |
673 | }, | |
674 | { } | |
675 | }; | |
676 | ||
677 | MODULE_DEVICE_TABLE(platform, s3c_rtc_driver_ids); | |
678 | ||
679 | static struct platform_driver s3c_rtc_driver = { | |
1add6781 | 680 | .probe = s3c_rtc_probe, |
5a167f45 | 681 | .remove = s3c_rtc_remove, |
9f4123b7 | 682 | .id_table = s3c_rtc_driver_ids, |
1add6781 | 683 | .driver = { |
9f4123b7 | 684 | .name = "s3c-rtc", |
1add6781 | 685 | .owner = THIS_MODULE, |
32e445aa | 686 | .pm = &s3c_rtc_pm_ops, |
04a373fd | 687 | .of_match_table = of_match_ptr(s3c_rtc_dt_match), |
1add6781 BD |
688 | }, |
689 | }; | |
690 | ||
0c4eae66 | 691 | module_platform_driver(s3c_rtc_driver); |
1add6781 BD |
692 | |
693 | MODULE_DESCRIPTION("Samsung S3C RTC Driver"); | |
694 | MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>"); | |
695 | MODULE_LICENSE("GPL"); | |
ad28a07b | 696 | MODULE_ALIAS("platform:s3c2410-rtc"); |