Commit | Line | Data |
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e842f1c8 RP |
1 | /* |
2 | * Real Time Clock interface for StrongARM SA1x00 and XScale PXA2xx | |
3 | * | |
4 | * Copyright (c) 2000 Nils Faerber | |
5 | * | |
6 | * Based on rtc.c by Paul Gortmaker | |
7 | * | |
8 | * Original Driver by Nils Faerber <nils@kernelconcepts.de> | |
9 | * | |
10 | * Modifications from: | |
11 | * CIH <cih@coventive.com> | |
2f82af08 | 12 | * Nicolas Pitre <nico@fluxnic.net> |
e842f1c8 RP |
13 | * Andrew Christian <andrew.christian@hp.com> |
14 | * | |
15 | * Converted to the RTC subsystem and Driver Model | |
16 | * by Richard Purdie <rpurdie@rpsys.net> | |
17 | * | |
18 | * This program is free software; you can redistribute it and/or | |
19 | * modify it under the terms of the GNU General Public License | |
20 | * as published by the Free Software Foundation; either version | |
21 | * 2 of the License, or (at your option) any later version. | |
22 | */ | |
23 | ||
24 | #include <linux/platform_device.h> | |
25 | #include <linux/module.h> | |
26 | #include <linux/rtc.h> | |
27 | #include <linux/init.h> | |
28 | #include <linux/fs.h> | |
29 | #include <linux/interrupt.h> | |
a0164a57 | 30 | #include <linux/string.h> |
e842f1c8 | 31 | #include <linux/pm.h> |
a0164a57 | 32 | #include <linux/bitops.h> |
e842f1c8 | 33 | |
a09e64fb | 34 | #include <mach/hardware.h> |
e842f1c8 | 35 | #include <asm/irq.h> |
e842f1c8 | 36 | |
a0164a57 RK |
37 | #ifdef CONFIG_ARCH_PXA |
38 | #include <mach/regs-rtc.h> | |
39 | #endif | |
40 | ||
a404ad1f | 41 | #define RTC_DEF_DIVIDER (32768 - 1) |
e842f1c8 | 42 | #define RTC_DEF_TRIM 0 |
a0164a57 RK |
43 | |
44 | static const unsigned long RTC_FREQ = 1024; | |
45 | static struct rtc_time rtc_alarm; | |
46 | static DEFINE_SPINLOCK(sa1100_rtc_lock); | |
47 | ||
57270fcd RK |
48 | static inline int rtc_periodic_alarm(struct rtc_time *tm) |
49 | { | |
50 | return (tm->tm_year == -1) || | |
51 | ((unsigned)tm->tm_mon >= 12) || | |
52 | ((unsigned)(tm->tm_mday - 1) >= 31) || | |
53 | ((unsigned)tm->tm_hour > 23) || | |
54 | ((unsigned)tm->tm_min > 59) || | |
55 | ((unsigned)tm->tm_sec > 59); | |
56 | } | |
57 | ||
797276ec RK |
58 | /* |
59 | * Calculate the next alarm time given the requested alarm time mask | |
60 | * and the current time. | |
61 | */ | |
a404ad1f MRJ |
62 | static void rtc_next_alarm_time(struct rtc_time *next, struct rtc_time *now, |
63 | struct rtc_time *alrm) | |
797276ec RK |
64 | { |
65 | unsigned long next_time; | |
66 | unsigned long now_time; | |
67 | ||
68 | next->tm_year = now->tm_year; | |
69 | next->tm_mon = now->tm_mon; | |
70 | next->tm_mday = now->tm_mday; | |
71 | next->tm_hour = alrm->tm_hour; | |
72 | next->tm_min = alrm->tm_min; | |
73 | next->tm_sec = alrm->tm_sec; | |
74 | ||
75 | rtc_tm_to_time(now, &now_time); | |
76 | rtc_tm_to_time(next, &next_time); | |
77 | ||
78 | if (next_time < now_time) { | |
79 | /* Advance one day */ | |
80 | next_time += 60 * 60 * 24; | |
81 | rtc_time_to_tm(next_time, next); | |
82 | } | |
83 | } | |
84 | ||
57270fcd RK |
85 | static int rtc_update_alarm(struct rtc_time *alrm) |
86 | { | |
87 | struct rtc_time alarm_tm, now_tm; | |
88 | unsigned long now, time; | |
89 | int ret; | |
90 | ||
91 | do { | |
92 | now = RCNR; | |
93 | rtc_time_to_tm(now, &now_tm); | |
94 | rtc_next_alarm_time(&alarm_tm, &now_tm, alrm); | |
95 | ret = rtc_tm_to_time(&alarm_tm, &time); | |
96 | if (ret != 0) | |
97 | break; | |
98 | ||
99 | RTSR = RTSR & (RTSR_HZE|RTSR_ALE|RTSR_AL); | |
100 | RTAR = time; | |
101 | } while (now != RCNR); | |
102 | ||
103 | return ret; | |
104 | } | |
105 | ||
7d12e780 | 106 | static irqreturn_t sa1100_rtc_interrupt(int irq, void *dev_id) |
e842f1c8 RP |
107 | { |
108 | struct platform_device *pdev = to_platform_device(dev_id); | |
a0164a57 | 109 | struct rtc_device *rtc = platform_get_drvdata(pdev); |
e842f1c8 RP |
110 | unsigned int rtsr; |
111 | unsigned long events = 0; | |
112 | ||
a0164a57 | 113 | spin_lock(&sa1100_rtc_lock); |
e842f1c8 | 114 | |
a0164a57 | 115 | rtsr = RTSR; |
e842f1c8 | 116 | /* clear interrupt sources */ |
a0164a57 | 117 | RTSR = 0; |
7decaa55 MRJ |
118 | /* Fix for a nasty initialization problem the in SA11xx RTSR register. |
119 | * See also the comments in sa1100_rtc_probe(). */ | |
120 | if (rtsr & (RTSR_ALE | RTSR_HZE)) { | |
121 | /* This is the original code, before there was the if test | |
122 | * above. This code does not clear interrupts that were not | |
123 | * enabled. */ | |
a0164a57 | 124 | RTSR = (RTSR_AL | RTSR_HZ) & (rtsr >> 2); |
7decaa55 MRJ |
125 | } else { |
126 | /* For some reason, it is possible to enter this routine | |
127 | * without interruptions enabled, it has been tested with | |
128 | * several units (Bug in SA11xx chip?). | |
129 | * | |
130 | * This situation leads to an infinite "loop" of interrupt | |
131 | * routine calling and as a result the processor seems to | |
132 | * lock on its first call to open(). */ | |
a0164a57 | 133 | RTSR = RTSR_AL | RTSR_HZ; |
7decaa55 | 134 | } |
e842f1c8 RP |
135 | |
136 | /* clear alarm interrupt if it has occurred */ | |
137 | if (rtsr & RTSR_AL) | |
138 | rtsr &= ~RTSR_ALE; | |
a0164a57 | 139 | RTSR = rtsr & (RTSR_ALE | RTSR_HZE); |
e842f1c8 RP |
140 | |
141 | /* update irq data & counter */ | |
142 | if (rtsr & RTSR_AL) | |
143 | events |= RTC_AF | RTC_IRQF; | |
144 | if (rtsr & RTSR_HZ) | |
145 | events |= RTC_UF | RTC_IRQF; | |
146 | ||
a0164a57 | 147 | rtc_update_irq(rtc, 1, events); |
e842f1c8 | 148 | |
57270fcd RK |
149 | if (rtsr & RTSR_AL && rtc_periodic_alarm(&rtc_alarm)) |
150 | rtc_update_alarm(&rtc_alarm); | |
151 | ||
a0164a57 | 152 | spin_unlock(&sa1100_rtc_lock); |
e842f1c8 RP |
153 | |
154 | return IRQ_HANDLED; | |
155 | } | |
156 | ||
e842f1c8 RP |
157 | static int sa1100_rtc_open(struct device *dev) |
158 | { | |
159 | int ret; | |
a0164a57 RK |
160 | struct platform_device *plat_dev = to_platform_device(dev); |
161 | struct rtc_device *rtc = platform_get_drvdata(plat_dev); | |
e842f1c8 | 162 | |
a0164a57 RK |
163 | ret = request_irq(IRQ_RTC1Hz, sa1100_rtc_interrupt, IRQF_DISABLED, |
164 | "rtc 1Hz", dev); | |
e842f1c8 | 165 | if (ret) { |
a0164a57 | 166 | dev_err(dev, "IRQ %d already in use.\n", IRQ_RTC1Hz); |
e842f1c8 RP |
167 | goto fail_ui; |
168 | } | |
a0164a57 RK |
169 | ret = request_irq(IRQ_RTCAlrm, sa1100_rtc_interrupt, IRQF_DISABLED, |
170 | "rtc Alrm", dev); | |
e842f1c8 | 171 | if (ret) { |
a0164a57 | 172 | dev_err(dev, "IRQ %d already in use.\n", IRQ_RTCAlrm); |
e842f1c8 RP |
173 | goto fail_ai; |
174 | } | |
a0164a57 RK |
175 | rtc->max_user_freq = RTC_FREQ; |
176 | rtc_irq_set_freq(rtc, NULL, RTC_FREQ); | |
d2ccb52d | 177 | |
e842f1c8 RP |
178 | return 0; |
179 | ||
e842f1c8 | 180 | fail_ai: |
a0164a57 | 181 | free_irq(IRQ_RTC1Hz, dev); |
e842f1c8 RP |
182 | fail_ui: |
183 | return ret; | |
184 | } | |
185 | ||
186 | static void sa1100_rtc_release(struct device *dev) | |
187 | { | |
a0164a57 RK |
188 | spin_lock_irq(&sa1100_rtc_lock); |
189 | RTSR = 0; | |
190 | spin_unlock_irq(&sa1100_rtc_lock); | |
e842f1c8 | 191 | |
a0164a57 RK |
192 | free_irq(IRQ_RTCAlrm, dev); |
193 | free_irq(IRQ_RTC1Hz, dev); | |
e842f1c8 RP |
194 | } |
195 | ||
16380c15 JS |
196 | static int sa1100_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) |
197 | { | |
a0164a57 | 198 | spin_lock_irq(&sa1100_rtc_lock); |
16380c15 | 199 | if (enabled) |
a0164a57 | 200 | RTSR |= RTSR_ALE; |
16380c15 | 201 | else |
a0164a57 RK |
202 | RTSR &= ~RTSR_ALE; |
203 | spin_unlock_irq(&sa1100_rtc_lock); | |
16380c15 JS |
204 | return 0; |
205 | } | |
206 | ||
e842f1c8 RP |
207 | static int sa1100_rtc_read_time(struct device *dev, struct rtc_time *tm) |
208 | { | |
a0164a57 | 209 | rtc_time_to_tm(RCNR, tm); |
e842f1c8 RP |
210 | return 0; |
211 | } | |
212 | ||
213 | static int sa1100_rtc_set_time(struct device *dev, struct rtc_time *tm) | |
214 | { | |
215 | unsigned long time; | |
216 | int ret; | |
217 | ||
218 | ret = rtc_tm_to_time(tm, &time); | |
219 | if (ret == 0) | |
a0164a57 | 220 | RCNR = time; |
e842f1c8 RP |
221 | return ret; |
222 | } | |
223 | ||
224 | static int sa1100_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) | |
225 | { | |
a0164a57 | 226 | u32 rtsr; |
32b49da4 | 227 | |
a0164a57 RK |
228 | memcpy(&alrm->time, &rtc_alarm, sizeof(struct rtc_time)); |
229 | rtsr = RTSR; | |
32b49da4 DB |
230 | alrm->enabled = (rtsr & RTSR_ALE) ? 1 : 0; |
231 | alrm->pending = (rtsr & RTSR_AL) ? 1 : 0; | |
e842f1c8 RP |
232 | return 0; |
233 | } | |
234 | ||
235 | static int sa1100_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) | |
236 | { | |
a0164a57 | 237 | int ret; |
e842f1c8 | 238 | |
a0164a57 | 239 | spin_lock_irq(&sa1100_rtc_lock); |
57270fcd RK |
240 | ret = rtc_update_alarm(&alrm->time); |
241 | if (ret == 0) { | |
242 | if (alrm->enabled) | |
243 | RTSR |= RTSR_ALE; | |
244 | else | |
245 | RTSR &= ~RTSR_ALE; | |
246 | } | |
a0164a57 | 247 | spin_unlock_irq(&sa1100_rtc_lock); |
e842f1c8 | 248 | |
a0164a57 | 249 | return ret; |
e842f1c8 RP |
250 | } |
251 | ||
252 | static int sa1100_rtc_proc(struct device *dev, struct seq_file *seq) | |
253 | { | |
a0164a57 RK |
254 | seq_printf(seq, "trim/divider\t\t: 0x%08x\n", (u32) RTTR); |
255 | seq_printf(seq, "RTSR\t\t\t: 0x%08x\n", (u32)RTSR); | |
e842f1c8 RP |
256 | |
257 | return 0; | |
258 | } | |
259 | ||
ff8371ac | 260 | static const struct rtc_class_ops sa1100_rtc_ops = { |
e842f1c8 | 261 | .open = sa1100_rtc_open, |
e842f1c8 | 262 | .release = sa1100_rtc_release, |
e842f1c8 RP |
263 | .read_time = sa1100_rtc_read_time, |
264 | .set_time = sa1100_rtc_set_time, | |
265 | .read_alarm = sa1100_rtc_read_alarm, | |
266 | .set_alarm = sa1100_rtc_set_alarm, | |
267 | .proc = sa1100_rtc_proc, | |
16380c15 | 268 | .alarm_irq_enable = sa1100_rtc_alarm_irq_enable, |
e842f1c8 RP |
269 | }; |
270 | ||
271 | static int sa1100_rtc_probe(struct platform_device *pdev) | |
272 | { | |
a0164a57 | 273 | struct rtc_device *rtc; |
e842f1c8 RP |
274 | |
275 | /* | |
276 | * According to the manual we should be able to let RTTR be zero | |
277 | * and then a default diviser for a 32.768KHz clock is used. | |
278 | * Apparently this doesn't work, at least for my SA1110 rev 5. | |
279 | * If the clock divider is uninitialized then reset it to the | |
280 | * default value to get the 1Hz clock. | |
281 | */ | |
a0164a57 RK |
282 | if (RTTR == 0) { |
283 | RTTR = RTC_DEF_DIVIDER + (RTC_DEF_TRIM << 16); | |
284 | dev_warn(&pdev->dev, "warning: " | |
285 | "initializing default clock divider/trim value\n"); | |
e842f1c8 | 286 | /* The current RTC value probably doesn't make sense either */ |
a0164a57 | 287 | RCNR = 0; |
e842f1c8 RP |
288 | } |
289 | ||
e5a2c9cc UL |
290 | device_init_wakeup(&pdev->dev, 1); |
291 | ||
a0164a57 RK |
292 | rtc = rtc_device_register(pdev->name, &pdev->dev, &sa1100_rtc_ops, |
293 | THIS_MODULE); | |
294 | ||
295 | if (IS_ERR(rtc)) | |
296 | return PTR_ERR(rtc); | |
297 | ||
298 | platform_set_drvdata(pdev, rtc); | |
299 | ||
7decaa55 MRJ |
300 | /* Fix for a nasty initialization problem the in SA11xx RTSR register. |
301 | * See also the comments in sa1100_rtc_interrupt(). | |
302 | * | |
303 | * Sometimes bit 1 of the RTSR (RTSR_HZ) will wake up 1, which means an | |
304 | * interrupt pending, even though interrupts were never enabled. | |
305 | * In this case, this bit it must be reset before enabling | |
306 | * interruptions to avoid a nonexistent interrupt to occur. | |
307 | * | |
308 | * In principle, the same problem would apply to bit 0, although it has | |
309 | * never been observed to happen. | |
310 | * | |
311 | * This issue is addressed both here and in sa1100_rtc_interrupt(). | |
312 | * If the issue is not addressed here, in the times when the processor | |
313 | * wakes up with the bit set there will be one spurious interrupt. | |
314 | * | |
315 | * The issue is also dealt with in sa1100_rtc_interrupt() to be on the | |
316 | * safe side, once the condition that lead to this strange | |
317 | * initialization is unknown and could in principle happen during | |
318 | * normal processing. | |
319 | * | |
320 | * Notice that clearing bit 1 and 0 is accomplished by writting ONES to | |
321 | * the corresponding bits in RTSR. */ | |
a0164a57 | 322 | RTSR = RTSR_AL | RTSR_HZ; |
7decaa55 | 323 | |
e842f1c8 RP |
324 | return 0; |
325 | } | |
326 | ||
327 | static int sa1100_rtc_remove(struct platform_device *pdev) | |
328 | { | |
a0164a57 RK |
329 | struct rtc_device *rtc = platform_get_drvdata(pdev); |
330 | ||
331 | if (rtc) | |
332 | rtc_device_unregister(rtc); | |
e842f1c8 RP |
333 | |
334 | return 0; | |
335 | } | |
336 | ||
6bc54e69 | 337 | #ifdef CONFIG_PM |
5d027cd2 | 338 | static int sa1100_rtc_suspend(struct device *dev) |
6bc54e69 | 339 | { |
5d027cd2 | 340 | if (device_may_wakeup(dev)) |
a0164a57 | 341 | enable_irq_wake(IRQ_RTCAlrm); |
6bc54e69 RK |
342 | return 0; |
343 | } | |
344 | ||
5d027cd2 | 345 | static int sa1100_rtc_resume(struct device *dev) |
6bc54e69 | 346 | { |
5d027cd2 | 347 | if (device_may_wakeup(dev)) |
a0164a57 | 348 | disable_irq_wake(IRQ_RTCAlrm); |
6bc54e69 RK |
349 | return 0; |
350 | } | |
5d027cd2 | 351 | |
47145210 | 352 | static const struct dev_pm_ops sa1100_rtc_pm_ops = { |
5d027cd2 HZ |
353 | .suspend = sa1100_rtc_suspend, |
354 | .resume = sa1100_rtc_resume, | |
355 | }; | |
6bc54e69 RK |
356 | #endif |
357 | ||
e842f1c8 RP |
358 | static struct platform_driver sa1100_rtc_driver = { |
359 | .probe = sa1100_rtc_probe, | |
360 | .remove = sa1100_rtc_remove, | |
361 | .driver = { | |
5d027cd2 HZ |
362 | .name = "sa1100-rtc", |
363 | #ifdef CONFIG_PM | |
364 | .pm = &sa1100_rtc_pm_ops, | |
365 | #endif | |
e842f1c8 RP |
366 | }, |
367 | }; | |
368 | ||
0c4eae66 | 369 | module_platform_driver(sa1100_rtc_driver); |
e842f1c8 RP |
370 | |
371 | MODULE_AUTHOR("Richard Purdie <rpurdie@rpsys.net>"); | |
372 | MODULE_DESCRIPTION("SA11x0/PXA2xx Realtime Clock Driver (RTC)"); | |
373 | MODULE_LICENSE("GPL"); | |
ad28a07b | 374 | MODULE_ALIAS("platform:sa1100-rtc"); |