Merge remote branch 'jwb/next' into next
[deliverable/linux.git] / drivers / rtc / rtc-sh.c
CommitLineData
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1/*
2 * SuperH On-Chip RTC Support
3 *
063adc75 4 * Copyright (C) 2006 - 2009 Paul Mundt
1b73e6ae 5 * Copyright (C) 2006 Jamie Lenehan
b420b1a7 6 * Copyright (C) 2008 Angelo Castello
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7 *
8 * Based on the old arch/sh/kernel/cpu/rtc.c by:
9 *
10 * Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>
11 * Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka
12 *
13 * This file is subject to the terms and conditions of the GNU General Public
14 * License. See the file "COPYING" in the main directory of this archive
15 * for more details.
16 */
17#include <linux/module.h>
18#include <linux/kernel.h>
19#include <linux/bcd.h>
20#include <linux/rtc.h>
21#include <linux/init.h>
22#include <linux/platform_device.h>
23#include <linux/seq_file.h>
24#include <linux/interrupt.h>
25#include <linux/spinlock.h>
31ccb081 26#include <linux/io.h>
5d2a5037 27#include <linux/log2.h>
063adc75 28#include <linux/clk.h>
5a0e3ad6 29#include <linux/slab.h>
ad89f87a 30#include <asm/rtc.h>
317a6104 31
1b73e6ae 32#define DRV_NAME "sh-rtc"
5c9740a8 33#define DRV_VERSION "0.2.3"
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34
35#define RTC_REG(r) ((r) * rtc_reg_size)
36
31ccb081 37#define R64CNT RTC_REG(0)
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JL
38
39#define RSECCNT RTC_REG(1) /* RTC sec */
40#define RMINCNT RTC_REG(2) /* RTC min */
41#define RHRCNT RTC_REG(3) /* RTC hour */
42#define RWKCNT RTC_REG(4) /* RTC week */
43#define RDAYCNT RTC_REG(5) /* RTC day */
44#define RMONCNT RTC_REG(6) /* RTC month */
45#define RYRCNT RTC_REG(7) /* RTC year */
46#define RSECAR RTC_REG(8) /* ALARM sec */
47#define RMINAR RTC_REG(9) /* ALARM min */
48#define RHRAR RTC_REG(10) /* ALARM hour */
49#define RWKAR RTC_REG(11) /* ALARM week */
50#define RDAYAR RTC_REG(12) /* ALARM day */
51#define RMONAR RTC_REG(13) /* ALARM month */
52#define RCR1 RTC_REG(14) /* Control */
53#define RCR2 RTC_REG(15) /* Control */
54
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55/*
56 * Note on RYRAR and RCR3: Up until this point most of the register
57 * definitions are consistent across all of the available parts. However,
58 * the placement of the optional RYRAR and RCR3 (the RYRAR control
59 * register used to control RYRCNT/RYRAR compare) varies considerably
60 * across various parts, occasionally being mapped in to a completely
61 * unrelated address space. For proper RYRAR support a separate resource
62 * would have to be handed off, but as this is purely optional in
63 * practice, we simply opt not to support it, thereby keeping the code
64 * quite a bit more simplified.
65 */
66
1b73e6ae
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67/* ALARM Bits - or with BCD encoded value */
68#define AR_ENB 0x80 /* Enable for alarm cmp */
317a6104 69
b420b1a7
AC
70/* Period Bits */
71#define PF_HP 0x100 /* Enable Half Period to support 8,32,128Hz */
72#define PF_COUNT 0x200 /* Half periodic counter */
73#define PF_OXS 0x400 /* Periodic One x Second */
74#define PF_KOU 0x800 /* Kernel or User periodic request 1=kernel */
75#define PF_MASK 0xf00
76
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77/* RCR1 Bits */
78#define RCR1_CF 0x80 /* Carry Flag */
79#define RCR1_CIE 0x10 /* Carry Interrupt Enable */
80#define RCR1_AIE 0x08 /* Alarm Interrupt Enable */
81#define RCR1_AF 0x01 /* Alarm Flag */
82
83/* RCR2 Bits */
84#define RCR2_PEF 0x80 /* PEriodic interrupt Flag */
85#define RCR2_PESMASK 0x70 /* Periodic interrupt Set */
86#define RCR2_RTCEN 0x08 /* ENable RTC */
87#define RCR2_ADJ 0x04 /* ADJustment (30-second) */
88#define RCR2_RESET 0x02 /* Reset bit */
89#define RCR2_START 0x01 /* Start bit */
90
91struct sh_rtc {
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92 void __iomem *regbase;
93 unsigned long regsize;
94 struct resource *res;
95 int alarm_irq;
96 int periodic_irq;
97 int carry_irq;
98 struct clk *clk;
99 struct rtc_device *rtc_dev;
100 spinlock_t lock;
101 unsigned long capabilities; /* See asm/rtc.h for cap bits */
102 unsigned short periodic_freq;
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103};
104
5e084a15 105static int __sh_rtc_interrupt(struct sh_rtc *rtc)
317a6104 106{
5e084a15 107 unsigned int tmp, pending;
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108
109 tmp = readb(rtc->regbase + RCR1);
5e084a15 110 pending = tmp & RCR1_CF;
1b73e6ae 111 tmp &= ~RCR1_CF;
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112 writeb(tmp, rtc->regbase + RCR1);
113
b420b1a7 114 /* Users have requested One x Second IRQ */
5e084a15 115 if (pending && rtc->periodic_freq & PF_OXS)
b420b1a7 116 rtc_update_irq(rtc->rtc_dev, 1, RTC_UF | RTC_IRQF);
317a6104 117
5e084a15 118 return pending;
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119}
120
5e084a15 121static int __sh_rtc_alarm(struct sh_rtc *rtc)
1b73e6ae 122{
5e084a15 123 unsigned int tmp, pending;
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124
125 tmp = readb(rtc->regbase + RCR1);
5e084a15 126 pending = tmp & RCR1_AF;
b420b1a7 127 tmp &= ~(RCR1_AF | RCR1_AIE);
5e084a15 128 writeb(tmp, rtc->regbase + RCR1);
1b73e6ae 129
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130 if (pending)
131 rtc_update_irq(rtc->rtc_dev, 1, RTC_AF | RTC_IRQF);
b420b1a7 132
5e084a15 133 return pending;
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134}
135
5e084a15 136static int __sh_rtc_periodic(struct sh_rtc *rtc)
317a6104 137{
b420b1a7 138 struct rtc_device *rtc_dev = rtc->rtc_dev;
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MD
139 struct rtc_task *irq_task;
140 unsigned int tmp, pending;
317a6104 141
b420b1a7 142 tmp = readb(rtc->regbase + RCR2);
5e084a15 143 pending = tmp & RCR2_PEF;
b420b1a7
AC
144 tmp &= ~RCR2_PEF;
145 writeb(tmp, rtc->regbase + RCR2);
146
5e084a15
MD
147 if (!pending)
148 return 0;
149
b420b1a7
AC
150 /* Half period enabled than one skipped and the next notified */
151 if ((rtc->periodic_freq & PF_HP) && (rtc->periodic_freq & PF_COUNT))
152 rtc->periodic_freq &= ~PF_COUNT;
153 else {
154 if (rtc->periodic_freq & PF_HP)
155 rtc->periodic_freq |= PF_COUNT;
156 if (rtc->periodic_freq & PF_KOU) {
157 spin_lock(&rtc_dev->irq_task_lock);
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MD
158 irq_task = rtc_dev->irq_task;
159 if (irq_task)
160 irq_task->func(irq_task->private_data);
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161 spin_unlock(&rtc_dev->irq_task_lock);
162 } else
163 rtc_update_irq(rtc->rtc_dev, 1, RTC_PF | RTC_IRQF);
164 }
317a6104 165
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MD
166 return pending;
167}
168
169static irqreturn_t sh_rtc_interrupt(int irq, void *dev_id)
170{
171 struct sh_rtc *rtc = dev_id;
172 int ret;
173
174 spin_lock(&rtc->lock);
175 ret = __sh_rtc_interrupt(rtc);
176 spin_unlock(&rtc->lock);
177
178 return IRQ_RETVAL(ret);
179}
180
181static irqreturn_t sh_rtc_alarm(int irq, void *dev_id)
182{
183 struct sh_rtc *rtc = dev_id;
184 int ret;
185
186 spin_lock(&rtc->lock);
187 ret = __sh_rtc_alarm(rtc);
188 spin_unlock(&rtc->lock);
189
190 return IRQ_RETVAL(ret);
191}
192
193static irqreturn_t sh_rtc_periodic(int irq, void *dev_id)
194{
195 struct sh_rtc *rtc = dev_id;
196 int ret;
197
198 spin_lock(&rtc->lock);
199 ret = __sh_rtc_periodic(rtc);
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200 spin_unlock(&rtc->lock);
201
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202 return IRQ_RETVAL(ret);
203}
204
205static irqreturn_t sh_rtc_shared(int irq, void *dev_id)
206{
207 struct sh_rtc *rtc = dev_id;
208 int ret;
209
210 spin_lock(&rtc->lock);
211 ret = __sh_rtc_interrupt(rtc);
212 ret |= __sh_rtc_alarm(rtc);
213 ret |= __sh_rtc_periodic(rtc);
214 spin_unlock(&rtc->lock);
215
216 return IRQ_RETVAL(ret);
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217}
218
5c9740a8 219static int sh_rtc_irq_set_state(struct device *dev, int enable)
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220{
221 struct sh_rtc *rtc = dev_get_drvdata(dev);
222 unsigned int tmp;
223
224 spin_lock_irq(&rtc->lock);
225
226 tmp = readb(rtc->regbase + RCR2);
227
228 if (enable) {
5c9740a8 229 rtc->periodic_freq |= PF_KOU;
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230 tmp &= ~RCR2_PEF; /* Clear PES bit */
231 tmp |= (rtc->periodic_freq & ~PF_HP); /* Set PES2-0 */
5c9740a8
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232 } else {
233 rtc->periodic_freq &= ~PF_KOU;
317a6104 234 tmp &= ~(RCR2_PESMASK | RCR2_PEF);
5c9740a8 235 }
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236
237 writeb(tmp, rtc->regbase + RCR2);
238
239 spin_unlock_irq(&rtc->lock);
5c9740a8
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240
241 return 0;
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242}
243
5c9740a8 244static int sh_rtc_irq_set_freq(struct device *dev, int freq)
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245{
246 struct sh_rtc *rtc = dev_get_drvdata(dev);
b420b1a7 247 int tmp, ret = 0;
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248
249 spin_lock_irq(&rtc->lock);
b420b1a7 250 tmp = rtc->periodic_freq & PF_MASK;
317a6104 251
b420b1a7
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252 switch (freq) {
253 case 0:
254 rtc->periodic_freq = 0x00;
255 break;
256 case 1:
257 rtc->periodic_freq = 0x60;
258 break;
259 case 2:
260 rtc->periodic_freq = 0x50;
261 break;
262 case 4:
263 rtc->periodic_freq = 0x40;
264 break;
265 case 8:
266 rtc->periodic_freq = 0x30 | PF_HP;
267 break;
268 case 16:
269 rtc->periodic_freq = 0x30;
270 break;
271 case 32:
272 rtc->periodic_freq = 0x20 | PF_HP;
273 break;
274 case 64:
275 rtc->periodic_freq = 0x20;
276 break;
277 case 128:
278 rtc->periodic_freq = 0x10 | PF_HP;
279 break;
280 case 256:
281 rtc->periodic_freq = 0x10;
282 break;
283 default:
284 ret = -ENOTSUPP;
285 }
317a6104 286
1043bf5c 287 if (ret == 0)
b420b1a7 288 rtc->periodic_freq |= tmp;
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289
290 spin_unlock_irq(&rtc->lock);
b420b1a7 291 return ret;
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292}
293
b420b1a7 294static inline void sh_rtc_setaie(struct device *dev, unsigned int enable)
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295{
296 struct sh_rtc *rtc = dev_get_drvdata(dev);
297 unsigned int tmp;
317a6104 298
b420b1a7 299 spin_lock_irq(&rtc->lock);
317a6104 300
b420b1a7 301 tmp = readb(rtc->regbase + RCR1);
317a6104 302
063adc75 303 if (enable)
b420b1a7 304 tmp |= RCR1_AIE;
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305 else
306 tmp &= ~RCR1_AIE;
317a6104 307
b420b1a7 308 writeb(tmp, rtc->regbase + RCR1);
317a6104 309
b420b1a7 310 spin_unlock_irq(&rtc->lock);
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311}
312
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313static int sh_rtc_proc(struct device *dev, struct seq_file *seq)
314{
315 struct sh_rtc *rtc = dev_get_drvdata(dev);
316 unsigned int tmp;
317
318 tmp = readb(rtc->regbase + RCR1);
b420b1a7 319 seq_printf(seq, "carry_IRQ\t: %s\n", (tmp & RCR1_CIE) ? "yes" : "no");
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320
321 tmp = readb(rtc->regbase + RCR2);
322 seq_printf(seq, "periodic_IRQ\t: %s\n",
b420b1a7 323 (tmp & RCR2_PESMASK) ? "yes" : "no");
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324
325 return 0;
326}
327
9cd88b90
MD
328static inline void sh_rtc_setcie(struct device *dev, unsigned int enable)
329{
330 struct sh_rtc *rtc = dev_get_drvdata(dev);
331 unsigned int tmp;
332
333 spin_lock_irq(&rtc->lock);
334
335 tmp = readb(rtc->regbase + RCR1);
336
337 if (!enable)
338 tmp &= ~RCR1_CIE;
339 else
340 tmp |= RCR1_CIE;
341
342 writeb(tmp, rtc->regbase + RCR1);
343
344 spin_unlock_irq(&rtc->lock);
345}
346
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347static int sh_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
348{
b420b1a7
AC
349 struct sh_rtc *rtc = dev_get_drvdata(dev);
350 unsigned int ret = 0;
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351
352 switch (cmd) {
b420b1a7
AC
353 case RTC_UIE_OFF:
354 rtc->periodic_freq &= ~PF_OXS;
9cd88b90 355 sh_rtc_setcie(dev, 0);
b420b1a7
AC
356 break;
357 case RTC_UIE_ON:
358 rtc->periodic_freq |= PF_OXS;
9cd88b90 359 sh_rtc_setcie(dev, 1);
b420b1a7 360 break;
b420b1a7
AC
361 default:
362 ret = -ENOIOCTLCMD;
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363 }
364
365 return ret;
366}
367
16380c15
JS
368static int sh_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
369{
370 sh_rtc_setaie(dev, enabled);
371 return 0;
372}
373
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374static int sh_rtc_read_time(struct device *dev, struct rtc_time *tm)
375{
376 struct platform_device *pdev = to_platform_device(dev);
377 struct sh_rtc *rtc = platform_get_drvdata(pdev);
378 unsigned int sec128, sec2, yr, yr100, cf_bit;
379
380 do {
381 unsigned int tmp;
382
383 spin_lock_irq(&rtc->lock);
384
385 tmp = readb(rtc->regbase + RCR1);
386 tmp &= ~RCR1_CF; /* Clear CF-bit */
387 tmp |= RCR1_CIE;
388 writeb(tmp, rtc->regbase + RCR1);
389
390 sec128 = readb(rtc->regbase + R64CNT);
391
fe20ba70
AB
392 tm->tm_sec = bcd2bin(readb(rtc->regbase + RSECCNT));
393 tm->tm_min = bcd2bin(readb(rtc->regbase + RMINCNT));
394 tm->tm_hour = bcd2bin(readb(rtc->regbase + RHRCNT));
395 tm->tm_wday = bcd2bin(readb(rtc->regbase + RWKCNT));
396 tm->tm_mday = bcd2bin(readb(rtc->regbase + RDAYCNT));
397 tm->tm_mon = bcd2bin(readb(rtc->regbase + RMONCNT)) - 1;
317a6104 398
ad89f87a
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399 if (rtc->capabilities & RTC_CAP_4_DIGIT_YEAR) {
400 yr = readw(rtc->regbase + RYRCNT);
fe20ba70 401 yr100 = bcd2bin(yr >> 8);
ad89f87a
PM
402 yr &= 0xff;
403 } else {
404 yr = readb(rtc->regbase + RYRCNT);
fe20ba70 405 yr100 = bcd2bin((yr == 0x99) ? 0x19 : 0x20);
ad89f87a 406 }
317a6104 407
fe20ba70 408 tm->tm_year = (yr100 * 100 + bcd2bin(yr)) - 1900;
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409
410 sec2 = readb(rtc->regbase + R64CNT);
411 cf_bit = readb(rtc->regbase + RCR1) & RCR1_CF;
412
413 spin_unlock_irq(&rtc->lock);
414 } while (cf_bit != 0 || ((sec128 ^ sec2) & RTC_BIT_INVERTED) != 0);
415
416#if RTC_BIT_INVERTED != 0
417 if ((sec128 & RTC_BIT_INVERTED))
418 tm->tm_sec--;
419#endif
420
9cd88b90
MD
421 /* only keep the carry interrupt enabled if UIE is on */
422 if (!(rtc->periodic_freq & PF_OXS))
423 sh_rtc_setcie(dev, 0);
424
435c55d1 425 dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
317a6104 426 "mday=%d, mon=%d, year=%d, wday=%d\n",
2a4e2b87 427 __func__,
317a6104 428 tm->tm_sec, tm->tm_min, tm->tm_hour,
a1614796 429 tm->tm_mday, tm->tm_mon + 1, tm->tm_year, tm->tm_wday);
317a6104 430
edf22477 431 return rtc_valid_tm(tm);
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432}
433
434static int sh_rtc_set_time(struct device *dev, struct rtc_time *tm)
435{
436 struct platform_device *pdev = to_platform_device(dev);
437 struct sh_rtc *rtc = platform_get_drvdata(pdev);
438 unsigned int tmp;
439 int year;
440
441 spin_lock_irq(&rtc->lock);
442
443 /* Reset pre-scaler & stop RTC */
444 tmp = readb(rtc->regbase + RCR2);
445 tmp |= RCR2_RESET;
699bc661 446 tmp &= ~RCR2_START;
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447 writeb(tmp, rtc->regbase + RCR2);
448
fe20ba70
AB
449 writeb(bin2bcd(tm->tm_sec), rtc->regbase + RSECCNT);
450 writeb(bin2bcd(tm->tm_min), rtc->regbase + RMINCNT);
451 writeb(bin2bcd(tm->tm_hour), rtc->regbase + RHRCNT);
452 writeb(bin2bcd(tm->tm_wday), rtc->regbase + RWKCNT);
453 writeb(bin2bcd(tm->tm_mday), rtc->regbase + RDAYCNT);
454 writeb(bin2bcd(tm->tm_mon + 1), rtc->regbase + RMONCNT);
317a6104 455
ad89f87a 456 if (rtc->capabilities & RTC_CAP_4_DIGIT_YEAR) {
fe20ba70
AB
457 year = (bin2bcd((tm->tm_year + 1900) / 100) << 8) |
458 bin2bcd(tm->tm_year % 100);
ad89f87a
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459 writew(year, rtc->regbase + RYRCNT);
460 } else {
461 year = tm->tm_year % 100;
fe20ba70 462 writeb(bin2bcd(year), rtc->regbase + RYRCNT);
ad89f87a 463 }
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464
465 /* Start RTC */
466 tmp = readb(rtc->regbase + RCR2);
467 tmp &= ~RCR2_RESET;
468 tmp |= RCR2_RTCEN | RCR2_START;
469 writeb(tmp, rtc->regbase + RCR2);
470
471 spin_unlock_irq(&rtc->lock);
472
473 return 0;
474}
475
1b73e6ae
JL
476static inline int sh_rtc_read_alarm_value(struct sh_rtc *rtc, int reg_off)
477{
478 unsigned int byte;
479 int value = 0xff; /* return 0xff for ignored values */
480
481 byte = readb(rtc->regbase + reg_off);
482 if (byte & AR_ENB) {
483 byte &= ~AR_ENB; /* strip the enable bit */
fe20ba70 484 value = bcd2bin(byte);
1b73e6ae
JL
485 }
486
487 return value;
488}
489
490static int sh_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
491{
492 struct platform_device *pdev = to_platform_device(dev);
493 struct sh_rtc *rtc = platform_get_drvdata(pdev);
b420b1a7 494 struct rtc_time *tm = &wkalrm->time;
1b73e6ae
JL
495
496 spin_lock_irq(&rtc->lock);
497
498 tm->tm_sec = sh_rtc_read_alarm_value(rtc, RSECAR);
499 tm->tm_min = sh_rtc_read_alarm_value(rtc, RMINAR);
500 tm->tm_hour = sh_rtc_read_alarm_value(rtc, RHRAR);
501 tm->tm_wday = sh_rtc_read_alarm_value(rtc, RWKAR);
502 tm->tm_mday = sh_rtc_read_alarm_value(rtc, RDAYAR);
503 tm->tm_mon = sh_rtc_read_alarm_value(rtc, RMONAR);
504 if (tm->tm_mon > 0)
505 tm->tm_mon -= 1; /* RTC is 1-12, tm_mon is 0-11 */
506 tm->tm_year = 0xffff;
507
0d103e90
DB
508 wkalrm->enabled = (readb(rtc->regbase + RCR1) & RCR1_AIE) ? 1 : 0;
509
1b73e6ae
JL
510 spin_unlock_irq(&rtc->lock);
511
512 return 0;
513}
514
515static inline void sh_rtc_write_alarm_value(struct sh_rtc *rtc,
516 int value, int reg_off)
517{
518 /* < 0 for a value that is ignored */
519 if (value < 0)
520 writeb(0, rtc->regbase + reg_off);
521 else
fe20ba70 522 writeb(bin2bcd(value) | AR_ENB, rtc->regbase + reg_off);
1b73e6ae
JL
523}
524
b420b1a7 525static int sh_rtc_check_alarm(struct rtc_time *tm)
1b73e6ae
JL
526{
527 /*
528 * The original rtc says anything > 0xc0 is "don't care" or "match
529 * all" - most users use 0xff but rtc-dev uses -1 for the same thing.
530 * The original rtc doesn't support years - some things use -1 and
531 * some 0xffff. We use -1 to make out tests easier.
532 */
533 if (tm->tm_year == 0xffff)
534 tm->tm_year = -1;
535 if (tm->tm_mon >= 0xff)
536 tm->tm_mon = -1;
537 if (tm->tm_mday >= 0xff)
538 tm->tm_mday = -1;
539 if (tm->tm_wday >= 0xff)
540 tm->tm_wday = -1;
541 if (tm->tm_hour >= 0xff)
542 tm->tm_hour = -1;
543 if (tm->tm_min >= 0xff)
544 tm->tm_min = -1;
545 if (tm->tm_sec >= 0xff)
546 tm->tm_sec = -1;
547
548 if (tm->tm_year > 9999 ||
549 tm->tm_mon >= 12 ||
550 tm->tm_mday == 0 || tm->tm_mday >= 32 ||
551 tm->tm_wday >= 7 ||
552 tm->tm_hour >= 24 ||
553 tm->tm_min >= 60 ||
554 tm->tm_sec >= 60)
555 return -EINVAL;
556
557 return 0;
558}
559
560static int sh_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
561{
562 struct platform_device *pdev = to_platform_device(dev);
563 struct sh_rtc *rtc = platform_get_drvdata(pdev);
564 unsigned int rcr1;
565 struct rtc_time *tm = &wkalrm->time;
566 int mon, err;
567
568 err = sh_rtc_check_alarm(tm);
569 if (unlikely(err < 0))
570 return err;
571
572 spin_lock_irq(&rtc->lock);
573
15c945c3 574 /* disable alarm interrupt and clear the alarm flag */
1b73e6ae 575 rcr1 = readb(rtc->regbase + RCR1);
b420b1a7 576 rcr1 &= ~(RCR1_AF | RCR1_AIE);
15c945c3 577 writeb(rcr1, rtc->regbase + RCR1);
1b73e6ae 578
1b73e6ae
JL
579 /* set alarm time */
580 sh_rtc_write_alarm_value(rtc, tm->tm_sec, RSECAR);
581 sh_rtc_write_alarm_value(rtc, tm->tm_min, RMINAR);
582 sh_rtc_write_alarm_value(rtc, tm->tm_hour, RHRAR);
583 sh_rtc_write_alarm_value(rtc, tm->tm_wday, RWKAR);
584 sh_rtc_write_alarm_value(rtc, tm->tm_mday, RDAYAR);
585 mon = tm->tm_mon;
586 if (mon >= 0)
587 mon += 1;
588 sh_rtc_write_alarm_value(rtc, mon, RMONAR);
589
15c945c3
JL
590 if (wkalrm->enabled) {
591 rcr1 |= RCR1_AIE;
592 writeb(rcr1, rtc->regbase + RCR1);
593 }
1b73e6ae
JL
594
595 spin_unlock_irq(&rtc->lock);
596
597 return 0;
598}
599
317a6104 600static struct rtc_class_ops sh_rtc_ops = {
317a6104
PM
601 .ioctl = sh_rtc_ioctl,
602 .read_time = sh_rtc_read_time,
603 .set_time = sh_rtc_set_time,
1b73e6ae
JL
604 .read_alarm = sh_rtc_read_alarm,
605 .set_alarm = sh_rtc_set_alarm,
b420b1a7
AC
606 .irq_set_state = sh_rtc_irq_set_state,
607 .irq_set_freq = sh_rtc_irq_set_freq,
317a6104 608 .proc = sh_rtc_proc,
16380c15 609 .alarm_irq_enable = sh_rtc_alarm_irq_enable,
317a6104
PM
610};
611
5c9740a8 612static int __init sh_rtc_probe(struct platform_device *pdev)
317a6104
PM
613{
614 struct sh_rtc *rtc;
615 struct resource *res;
edf22477 616 struct rtc_time r;
063adc75
PM
617 char clk_name[6];
618 int clk_id, ret;
317a6104
PM
619
620 rtc = kzalloc(sizeof(struct sh_rtc), GFP_KERNEL);
621 if (unlikely(!rtc))
622 return -ENOMEM;
623
624 spin_lock_init(&rtc->lock);
625
b420b1a7 626 /* get periodic/carry/alarm irqs */
2641dc92 627 ret = platform_get_irq(pdev, 0);
2fac6674 628 if (unlikely(ret <= 0)) {
2641dc92 629 ret = -ENOENT;
5e084a15 630 dev_err(&pdev->dev, "No IRQ resource\n");
317a6104
PM
631 goto err_badres;
632 }
063adc75 633
2641dc92 634 rtc->periodic_irq = ret;
5e084a15
MD
635 rtc->carry_irq = platform_get_irq(pdev, 1);
636 rtc->alarm_irq = platform_get_irq(pdev, 2);
317a6104
PM
637
638 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
639 if (unlikely(res == NULL)) {
2641dc92 640 ret = -ENOENT;
317a6104
PM
641 dev_err(&pdev->dev, "No IO resource\n");
642 goto err_badres;
643 }
644
063adc75 645 rtc->regsize = resource_size(res);
317a6104
PM
646
647 rtc->res = request_mem_region(res->start, rtc->regsize, pdev->name);
648 if (unlikely(!rtc->res)) {
649 ret = -EBUSY;
650 goto err_badres;
651 }
652
0305794c 653 rtc->regbase = ioremap_nocache(rtc->res->start, rtc->regsize);
317a6104
PM
654 if (unlikely(!rtc->regbase)) {
655 ret = -EINVAL;
656 goto err_badmap;
657 }
658
063adc75
PM
659 clk_id = pdev->id;
660 /* With a single device, the clock id is still "rtc0" */
661 if (clk_id < 0)
662 clk_id = 0;
663
664 snprintf(clk_name, sizeof(clk_name), "rtc%d", clk_id);
665
666 rtc->clk = clk_get(&pdev->dev, clk_name);
667 if (IS_ERR(rtc->clk)) {
668 /*
669 * No error handling for rtc->clk intentionally, not all
670 * platforms will have a unique clock for the RTC, and
671 * the clk API can handle the struct clk pointer being
672 * NULL.
673 */
674 rtc->clk = NULL;
675 }
676
677 clk_enable(rtc->clk);
678
ad89f87a
PM
679 rtc->capabilities = RTC_DEF_CAPABILITIES;
680 if (pdev->dev.platform_data) {
681 struct sh_rtc_platform_info *pinfo = pdev->dev.platform_data;
682
683 /*
684 * Some CPUs have special capabilities in addition to the
685 * default set. Add those in here.
686 */
687 rtc->capabilities |= pinfo->capabilities;
688 }
689
5e084a15
MD
690 if (rtc->carry_irq <= 0) {
691 /* register shared periodic/carry/alarm irq */
692 ret = request_irq(rtc->periodic_irq, sh_rtc_shared,
693 IRQF_DISABLED, "sh-rtc", rtc);
694 if (unlikely(ret)) {
695 dev_err(&pdev->dev,
696 "request IRQ failed with %d, IRQ %d\n", ret,
697 rtc->periodic_irq);
698 goto err_unmap;
699 }
700 } else {
701 /* register periodic/carry/alarm irqs */
702 ret = request_irq(rtc->periodic_irq, sh_rtc_periodic,
703 IRQF_DISABLED, "sh-rtc period", rtc);
704 if (unlikely(ret)) {
705 dev_err(&pdev->dev,
706 "request period IRQ failed with %d, IRQ %d\n",
707 ret, rtc->periodic_irq);
708 goto err_unmap;
709 }
b420b1a7 710
5e084a15
MD
711 ret = request_irq(rtc->carry_irq, sh_rtc_interrupt,
712 IRQF_DISABLED, "sh-rtc carry", rtc);
713 if (unlikely(ret)) {
714 dev_err(&pdev->dev,
715 "request carry IRQ failed with %d, IRQ %d\n",
716 ret, rtc->carry_irq);
717 free_irq(rtc->periodic_irq, rtc);
718 goto err_unmap;
719 }
b420b1a7 720
5e084a15
MD
721 ret = request_irq(rtc->alarm_irq, sh_rtc_alarm,
722 IRQF_DISABLED, "sh-rtc alarm", rtc);
723 if (unlikely(ret)) {
724 dev_err(&pdev->dev,
725 "request alarm IRQ failed with %d, IRQ %d\n",
726 ret, rtc->alarm_irq);
727 free_irq(rtc->carry_irq, rtc);
728 free_irq(rtc->periodic_irq, rtc);
729 goto err_unmap;
730 }
b420b1a7
AC
731 }
732
5c9740a8
AZ
733 platform_set_drvdata(pdev, rtc);
734
9cd88b90 735 /* everything disabled by default */
5c9740a8
AZ
736 sh_rtc_irq_set_freq(&pdev->dev, 0);
737 sh_rtc_irq_set_state(&pdev->dev, 0);
9cd88b90
MD
738 sh_rtc_setaie(&pdev->dev, 0);
739 sh_rtc_setcie(&pdev->dev, 0);
edf22477 740
5c9740a8
AZ
741 rtc->rtc_dev = rtc_device_register("sh", &pdev->dev,
742 &sh_rtc_ops, THIS_MODULE);
743 if (IS_ERR(rtc->rtc_dev)) {
744 ret = PTR_ERR(rtc->rtc_dev);
745 free_irq(rtc->periodic_irq, rtc);
746 free_irq(rtc->carry_irq, rtc);
747 free_irq(rtc->alarm_irq, rtc);
748 goto err_unmap;
749 }
750
751 rtc->rtc_dev->max_user_freq = 256;
752
edf22477
MD
753 /* reset rtc to epoch 0 if time is invalid */
754 if (rtc_read_time(rtc->rtc_dev, &r) < 0) {
755 rtc_time_to_tm(0, &r);
756 rtc_set_time(rtc->rtc_dev, &r);
757 }
758
7a8fe8e3 759 device_init_wakeup(&pdev->dev, 1);
317a6104
PM
760 return 0;
761
0305794c 762err_unmap:
063adc75
PM
763 clk_disable(rtc->clk);
764 clk_put(rtc->clk);
0305794c 765 iounmap(rtc->regbase);
317a6104 766err_badmap:
899be96d 767 release_mem_region(rtc->res->start, rtc->regsize);
317a6104
PM
768err_badres:
769 kfree(rtc);
770
771 return ret;
772}
773
5c9740a8 774static int __exit sh_rtc_remove(struct platform_device *pdev)
317a6104
PM
775{
776 struct sh_rtc *rtc = platform_get_drvdata(pdev);
777
5c9740a8
AZ
778 rtc_device_unregister(rtc->rtc_dev);
779 sh_rtc_irq_set_state(&pdev->dev, 0);
317a6104 780
317a6104 781 sh_rtc_setaie(&pdev->dev, 0);
9cd88b90 782 sh_rtc_setcie(&pdev->dev, 0);
317a6104 783
b420b1a7 784 free_irq(rtc->periodic_irq, rtc);
063adc75 785
5e084a15
MD
786 if (rtc->carry_irq > 0) {
787 free_irq(rtc->carry_irq, rtc);
788 free_irq(rtc->alarm_irq, rtc);
789 }
b420b1a7 790
0305794c 791 iounmap(rtc->regbase);
899be96d 792 release_mem_region(rtc->res->start, rtc->regsize);
0305794c 793
063adc75
PM
794 clk_disable(rtc->clk);
795 clk_put(rtc->clk);
796
317a6104
PM
797 platform_set_drvdata(pdev, NULL);
798
799 kfree(rtc);
800
801 return 0;
802}
faa9fa8e
MD
803
804static void sh_rtc_set_irq_wake(struct device *dev, int enabled)
805{
806 struct platform_device *pdev = to_platform_device(dev);
807 struct sh_rtc *rtc = platform_get_drvdata(pdev);
808
809 set_irq_wake(rtc->periodic_irq, enabled);
063adc75 810
faa9fa8e
MD
811 if (rtc->carry_irq > 0) {
812 set_irq_wake(rtc->carry_irq, enabled);
813 set_irq_wake(rtc->alarm_irq, enabled);
814 }
faa9fa8e
MD
815}
816
817static int sh_rtc_suspend(struct device *dev)
818{
819 if (device_may_wakeup(dev))
820 sh_rtc_set_irq_wake(dev, 1);
821
822 return 0;
823}
824
825static int sh_rtc_resume(struct device *dev)
826{
827 if (device_may_wakeup(dev))
828 sh_rtc_set_irq_wake(dev, 0);
829
830 return 0;
831}
832
47145210 833static const struct dev_pm_ops sh_rtc_dev_pm_ops = {
faa9fa8e
MD
834 .suspend = sh_rtc_suspend,
835 .resume = sh_rtc_resume,
836};
837
317a6104
PM
838static struct platform_driver sh_rtc_platform_driver = {
839 .driver = {
1b73e6ae 840 .name = DRV_NAME,
317a6104 841 .owner = THIS_MODULE,
faa9fa8e 842 .pm = &sh_rtc_dev_pm_ops,
317a6104 843 },
5c9740a8 844 .remove = __exit_p(sh_rtc_remove),
317a6104
PM
845};
846
847static int __init sh_rtc_init(void)
848{
5c9740a8 849 return platform_driver_probe(&sh_rtc_platform_driver, sh_rtc_probe);
317a6104
PM
850}
851
852static void __exit sh_rtc_exit(void)
853{
854 platform_driver_unregister(&sh_rtc_platform_driver);
855}
856
857module_init(sh_rtc_init);
858module_exit(sh_rtc_exit);
859
860MODULE_DESCRIPTION("SuperH on-chip RTC driver");
1b73e6ae 861MODULE_VERSION(DRV_VERSION);
b420b1a7
AC
862MODULE_AUTHOR("Paul Mundt <lethal@linux-sh.org>, "
863 "Jamie Lenehan <lenehan@twibble.org>, "
864 "Angelo Castello <angelo.castello@st.com>");
317a6104 865MODULE_LICENSE("GPL");
ad28a07b 866MODULE_ALIAS("platform:" DRV_NAME);
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