Commit | Line | Data |
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317a6104 PM |
1 | /* |
2 | * SuperH On-Chip RTC Support | |
3 | * | |
063adc75 | 4 | * Copyright (C) 2006 - 2009 Paul Mundt |
1b73e6ae | 5 | * Copyright (C) 2006 Jamie Lenehan |
b420b1a7 | 6 | * Copyright (C) 2008 Angelo Castello |
317a6104 PM |
7 | * |
8 | * Based on the old arch/sh/kernel/cpu/rtc.c by: | |
9 | * | |
10 | * Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org> | |
11 | * Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka | |
12 | * | |
13 | * This file is subject to the terms and conditions of the GNU General Public | |
14 | * License. See the file "COPYING" in the main directory of this archive | |
15 | * for more details. | |
16 | */ | |
17 | #include <linux/module.h> | |
18 | #include <linux/kernel.h> | |
19 | #include <linux/bcd.h> | |
20 | #include <linux/rtc.h> | |
21 | #include <linux/init.h> | |
22 | #include <linux/platform_device.h> | |
23 | #include <linux/seq_file.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/spinlock.h> | |
31ccb081 | 26 | #include <linux/io.h> |
5d2a5037 | 27 | #include <linux/log2.h> |
063adc75 | 28 | #include <linux/clk.h> |
ad89f87a | 29 | #include <asm/rtc.h> |
317a6104 | 30 | |
1b73e6ae | 31 | #define DRV_NAME "sh-rtc" |
5c9740a8 | 32 | #define DRV_VERSION "0.2.3" |
317a6104 PM |
33 | |
34 | #define RTC_REG(r) ((r) * rtc_reg_size) | |
35 | ||
31ccb081 | 36 | #define R64CNT RTC_REG(0) |
1b73e6ae JL |
37 | |
38 | #define RSECCNT RTC_REG(1) /* RTC sec */ | |
39 | #define RMINCNT RTC_REG(2) /* RTC min */ | |
40 | #define RHRCNT RTC_REG(3) /* RTC hour */ | |
41 | #define RWKCNT RTC_REG(4) /* RTC week */ | |
42 | #define RDAYCNT RTC_REG(5) /* RTC day */ | |
43 | #define RMONCNT RTC_REG(6) /* RTC month */ | |
44 | #define RYRCNT RTC_REG(7) /* RTC year */ | |
45 | #define RSECAR RTC_REG(8) /* ALARM sec */ | |
46 | #define RMINAR RTC_REG(9) /* ALARM min */ | |
47 | #define RHRAR RTC_REG(10) /* ALARM hour */ | |
48 | #define RWKAR RTC_REG(11) /* ALARM week */ | |
49 | #define RDAYAR RTC_REG(12) /* ALARM day */ | |
50 | #define RMONAR RTC_REG(13) /* ALARM month */ | |
51 | #define RCR1 RTC_REG(14) /* Control */ | |
52 | #define RCR2 RTC_REG(15) /* Control */ | |
53 | ||
ff1b7506 PM |
54 | /* |
55 | * Note on RYRAR and RCR3: Up until this point most of the register | |
56 | * definitions are consistent across all of the available parts. However, | |
57 | * the placement of the optional RYRAR and RCR3 (the RYRAR control | |
58 | * register used to control RYRCNT/RYRAR compare) varies considerably | |
59 | * across various parts, occasionally being mapped in to a completely | |
60 | * unrelated address space. For proper RYRAR support a separate resource | |
61 | * would have to be handed off, but as this is purely optional in | |
62 | * practice, we simply opt not to support it, thereby keeping the code | |
63 | * quite a bit more simplified. | |
64 | */ | |
65 | ||
1b73e6ae JL |
66 | /* ALARM Bits - or with BCD encoded value */ |
67 | #define AR_ENB 0x80 /* Enable for alarm cmp */ | |
317a6104 | 68 | |
b420b1a7 AC |
69 | /* Period Bits */ |
70 | #define PF_HP 0x100 /* Enable Half Period to support 8,32,128Hz */ | |
71 | #define PF_COUNT 0x200 /* Half periodic counter */ | |
72 | #define PF_OXS 0x400 /* Periodic One x Second */ | |
73 | #define PF_KOU 0x800 /* Kernel or User periodic request 1=kernel */ | |
74 | #define PF_MASK 0xf00 | |
75 | ||
317a6104 PM |
76 | /* RCR1 Bits */ |
77 | #define RCR1_CF 0x80 /* Carry Flag */ | |
78 | #define RCR1_CIE 0x10 /* Carry Interrupt Enable */ | |
79 | #define RCR1_AIE 0x08 /* Alarm Interrupt Enable */ | |
80 | #define RCR1_AF 0x01 /* Alarm Flag */ | |
81 | ||
82 | /* RCR2 Bits */ | |
83 | #define RCR2_PEF 0x80 /* PEriodic interrupt Flag */ | |
84 | #define RCR2_PESMASK 0x70 /* Periodic interrupt Set */ | |
85 | #define RCR2_RTCEN 0x08 /* ENable RTC */ | |
86 | #define RCR2_ADJ 0x04 /* ADJustment (30-second) */ | |
87 | #define RCR2_RESET 0x02 /* Reset bit */ | |
88 | #define RCR2_START 0x01 /* Start bit */ | |
89 | ||
90 | struct sh_rtc { | |
063adc75 PM |
91 | void __iomem *regbase; |
92 | unsigned long regsize; | |
93 | struct resource *res; | |
94 | int alarm_irq; | |
95 | int periodic_irq; | |
96 | int carry_irq; | |
97 | struct clk *clk; | |
98 | struct rtc_device *rtc_dev; | |
99 | spinlock_t lock; | |
100 | unsigned long capabilities; /* See asm/rtc.h for cap bits */ | |
101 | unsigned short periodic_freq; | |
317a6104 PM |
102 | }; |
103 | ||
5e084a15 | 104 | static int __sh_rtc_interrupt(struct sh_rtc *rtc) |
317a6104 | 105 | { |
5e084a15 | 106 | unsigned int tmp, pending; |
317a6104 PM |
107 | |
108 | tmp = readb(rtc->regbase + RCR1); | |
5e084a15 | 109 | pending = tmp & RCR1_CF; |
1b73e6ae | 110 | tmp &= ~RCR1_CF; |
317a6104 PM |
111 | writeb(tmp, rtc->regbase + RCR1); |
112 | ||
b420b1a7 | 113 | /* Users have requested One x Second IRQ */ |
5e084a15 | 114 | if (pending && rtc->periodic_freq & PF_OXS) |
b420b1a7 | 115 | rtc_update_irq(rtc->rtc_dev, 1, RTC_UF | RTC_IRQF); |
317a6104 | 116 | |
5e084a15 | 117 | return pending; |
317a6104 PM |
118 | } |
119 | ||
5e084a15 | 120 | static int __sh_rtc_alarm(struct sh_rtc *rtc) |
1b73e6ae | 121 | { |
5e084a15 | 122 | unsigned int tmp, pending; |
1b73e6ae JL |
123 | |
124 | tmp = readb(rtc->regbase + RCR1); | |
5e084a15 | 125 | pending = tmp & RCR1_AF; |
b420b1a7 | 126 | tmp &= ~(RCR1_AF | RCR1_AIE); |
5e084a15 | 127 | writeb(tmp, rtc->regbase + RCR1); |
1b73e6ae | 128 | |
5e084a15 MD |
129 | if (pending) |
130 | rtc_update_irq(rtc->rtc_dev, 1, RTC_AF | RTC_IRQF); | |
b420b1a7 | 131 | |
5e084a15 | 132 | return pending; |
1b73e6ae JL |
133 | } |
134 | ||
5e084a15 | 135 | static int __sh_rtc_periodic(struct sh_rtc *rtc) |
317a6104 | 136 | { |
b420b1a7 | 137 | struct rtc_device *rtc_dev = rtc->rtc_dev; |
5e084a15 MD |
138 | struct rtc_task *irq_task; |
139 | unsigned int tmp, pending; | |
317a6104 | 140 | |
b420b1a7 | 141 | tmp = readb(rtc->regbase + RCR2); |
5e084a15 | 142 | pending = tmp & RCR2_PEF; |
b420b1a7 AC |
143 | tmp &= ~RCR2_PEF; |
144 | writeb(tmp, rtc->regbase + RCR2); | |
145 | ||
5e084a15 MD |
146 | if (!pending) |
147 | return 0; | |
148 | ||
b420b1a7 AC |
149 | /* Half period enabled than one skipped and the next notified */ |
150 | if ((rtc->periodic_freq & PF_HP) && (rtc->periodic_freq & PF_COUNT)) | |
151 | rtc->periodic_freq &= ~PF_COUNT; | |
152 | else { | |
153 | if (rtc->periodic_freq & PF_HP) | |
154 | rtc->periodic_freq |= PF_COUNT; | |
155 | if (rtc->periodic_freq & PF_KOU) { | |
156 | spin_lock(&rtc_dev->irq_task_lock); | |
5e084a15 MD |
157 | irq_task = rtc_dev->irq_task; |
158 | if (irq_task) | |
159 | irq_task->func(irq_task->private_data); | |
b420b1a7 AC |
160 | spin_unlock(&rtc_dev->irq_task_lock); |
161 | } else | |
162 | rtc_update_irq(rtc->rtc_dev, 1, RTC_PF | RTC_IRQF); | |
163 | } | |
317a6104 | 164 | |
5e084a15 MD |
165 | return pending; |
166 | } | |
167 | ||
168 | static irqreturn_t sh_rtc_interrupt(int irq, void *dev_id) | |
169 | { | |
170 | struct sh_rtc *rtc = dev_id; | |
171 | int ret; | |
172 | ||
173 | spin_lock(&rtc->lock); | |
174 | ret = __sh_rtc_interrupt(rtc); | |
175 | spin_unlock(&rtc->lock); | |
176 | ||
177 | return IRQ_RETVAL(ret); | |
178 | } | |
179 | ||
180 | static irqreturn_t sh_rtc_alarm(int irq, void *dev_id) | |
181 | { | |
182 | struct sh_rtc *rtc = dev_id; | |
183 | int ret; | |
184 | ||
185 | spin_lock(&rtc->lock); | |
186 | ret = __sh_rtc_alarm(rtc); | |
187 | spin_unlock(&rtc->lock); | |
188 | ||
189 | return IRQ_RETVAL(ret); | |
190 | } | |
191 | ||
192 | static irqreturn_t sh_rtc_periodic(int irq, void *dev_id) | |
193 | { | |
194 | struct sh_rtc *rtc = dev_id; | |
195 | int ret; | |
196 | ||
197 | spin_lock(&rtc->lock); | |
198 | ret = __sh_rtc_periodic(rtc); | |
317a6104 PM |
199 | spin_unlock(&rtc->lock); |
200 | ||
5e084a15 MD |
201 | return IRQ_RETVAL(ret); |
202 | } | |
203 | ||
204 | static irqreturn_t sh_rtc_shared(int irq, void *dev_id) | |
205 | { | |
206 | struct sh_rtc *rtc = dev_id; | |
207 | int ret; | |
208 | ||
209 | spin_lock(&rtc->lock); | |
210 | ret = __sh_rtc_interrupt(rtc); | |
211 | ret |= __sh_rtc_alarm(rtc); | |
212 | ret |= __sh_rtc_periodic(rtc); | |
213 | spin_unlock(&rtc->lock); | |
214 | ||
215 | return IRQ_RETVAL(ret); | |
317a6104 PM |
216 | } |
217 | ||
5c9740a8 | 218 | static int sh_rtc_irq_set_state(struct device *dev, int enable) |
317a6104 PM |
219 | { |
220 | struct sh_rtc *rtc = dev_get_drvdata(dev); | |
221 | unsigned int tmp; | |
222 | ||
223 | spin_lock_irq(&rtc->lock); | |
224 | ||
225 | tmp = readb(rtc->regbase + RCR2); | |
226 | ||
227 | if (enable) { | |
5c9740a8 | 228 | rtc->periodic_freq |= PF_KOU; |
b420b1a7 AC |
229 | tmp &= ~RCR2_PEF; /* Clear PES bit */ |
230 | tmp |= (rtc->periodic_freq & ~PF_HP); /* Set PES2-0 */ | |
5c9740a8 AZ |
231 | } else { |
232 | rtc->periodic_freq &= ~PF_KOU; | |
317a6104 | 233 | tmp &= ~(RCR2_PESMASK | RCR2_PEF); |
5c9740a8 | 234 | } |
317a6104 PM |
235 | |
236 | writeb(tmp, rtc->regbase + RCR2); | |
237 | ||
238 | spin_unlock_irq(&rtc->lock); | |
5c9740a8 AZ |
239 | |
240 | return 0; | |
317a6104 PM |
241 | } |
242 | ||
5c9740a8 | 243 | static int sh_rtc_irq_set_freq(struct device *dev, int freq) |
317a6104 PM |
244 | { |
245 | struct sh_rtc *rtc = dev_get_drvdata(dev); | |
b420b1a7 | 246 | int tmp, ret = 0; |
317a6104 PM |
247 | |
248 | spin_lock_irq(&rtc->lock); | |
b420b1a7 | 249 | tmp = rtc->periodic_freq & PF_MASK; |
317a6104 | 250 | |
b420b1a7 AC |
251 | switch (freq) { |
252 | case 0: | |
253 | rtc->periodic_freq = 0x00; | |
254 | break; | |
255 | case 1: | |
256 | rtc->periodic_freq = 0x60; | |
257 | break; | |
258 | case 2: | |
259 | rtc->periodic_freq = 0x50; | |
260 | break; | |
261 | case 4: | |
262 | rtc->periodic_freq = 0x40; | |
263 | break; | |
264 | case 8: | |
265 | rtc->periodic_freq = 0x30 | PF_HP; | |
266 | break; | |
267 | case 16: | |
268 | rtc->periodic_freq = 0x30; | |
269 | break; | |
270 | case 32: | |
271 | rtc->periodic_freq = 0x20 | PF_HP; | |
272 | break; | |
273 | case 64: | |
274 | rtc->periodic_freq = 0x20; | |
275 | break; | |
276 | case 128: | |
277 | rtc->periodic_freq = 0x10 | PF_HP; | |
278 | break; | |
279 | case 256: | |
280 | rtc->periodic_freq = 0x10; | |
281 | break; | |
282 | default: | |
283 | ret = -ENOTSUPP; | |
284 | } | |
317a6104 | 285 | |
1043bf5c | 286 | if (ret == 0) |
b420b1a7 | 287 | rtc->periodic_freq |= tmp; |
317a6104 PM |
288 | |
289 | spin_unlock_irq(&rtc->lock); | |
b420b1a7 | 290 | return ret; |
317a6104 PM |
291 | } |
292 | ||
b420b1a7 | 293 | static inline void sh_rtc_setaie(struct device *dev, unsigned int enable) |
317a6104 PM |
294 | { |
295 | struct sh_rtc *rtc = dev_get_drvdata(dev); | |
296 | unsigned int tmp; | |
317a6104 | 297 | |
b420b1a7 | 298 | spin_lock_irq(&rtc->lock); |
317a6104 | 299 | |
b420b1a7 | 300 | tmp = readb(rtc->regbase + RCR1); |
317a6104 | 301 | |
063adc75 | 302 | if (enable) |
b420b1a7 | 303 | tmp |= RCR1_AIE; |
063adc75 PM |
304 | else |
305 | tmp &= ~RCR1_AIE; | |
317a6104 | 306 | |
b420b1a7 | 307 | writeb(tmp, rtc->regbase + RCR1); |
317a6104 | 308 | |
b420b1a7 | 309 | spin_unlock_irq(&rtc->lock); |
317a6104 PM |
310 | } |
311 | ||
317a6104 PM |
312 | static int sh_rtc_proc(struct device *dev, struct seq_file *seq) |
313 | { | |
314 | struct sh_rtc *rtc = dev_get_drvdata(dev); | |
315 | unsigned int tmp; | |
316 | ||
317 | tmp = readb(rtc->regbase + RCR1); | |
b420b1a7 | 318 | seq_printf(seq, "carry_IRQ\t: %s\n", (tmp & RCR1_CIE) ? "yes" : "no"); |
317a6104 PM |
319 | |
320 | tmp = readb(rtc->regbase + RCR2); | |
321 | seq_printf(seq, "periodic_IRQ\t: %s\n", | |
b420b1a7 | 322 | (tmp & RCR2_PESMASK) ? "yes" : "no"); |
317a6104 PM |
323 | |
324 | return 0; | |
325 | } | |
326 | ||
9cd88b90 MD |
327 | static inline void sh_rtc_setcie(struct device *dev, unsigned int enable) |
328 | { | |
329 | struct sh_rtc *rtc = dev_get_drvdata(dev); | |
330 | unsigned int tmp; | |
331 | ||
332 | spin_lock_irq(&rtc->lock); | |
333 | ||
334 | tmp = readb(rtc->regbase + RCR1); | |
335 | ||
336 | if (!enable) | |
337 | tmp &= ~RCR1_CIE; | |
338 | else | |
339 | tmp |= RCR1_CIE; | |
340 | ||
341 | writeb(tmp, rtc->regbase + RCR1); | |
342 | ||
343 | spin_unlock_irq(&rtc->lock); | |
344 | } | |
345 | ||
317a6104 PM |
346 | static int sh_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg) |
347 | { | |
b420b1a7 AC |
348 | struct sh_rtc *rtc = dev_get_drvdata(dev); |
349 | unsigned int ret = 0; | |
317a6104 PM |
350 | |
351 | switch (cmd) { | |
317a6104 PM |
352 | case RTC_AIE_OFF: |
353 | case RTC_AIE_ON: | |
354 | sh_rtc_setaie(dev, cmd == RTC_AIE_ON); | |
317a6104 | 355 | break; |
b420b1a7 AC |
356 | case RTC_UIE_OFF: |
357 | rtc->periodic_freq &= ~PF_OXS; | |
9cd88b90 | 358 | sh_rtc_setcie(dev, 0); |
b420b1a7 AC |
359 | break; |
360 | case RTC_UIE_ON: | |
361 | rtc->periodic_freq |= PF_OXS; | |
9cd88b90 | 362 | sh_rtc_setcie(dev, 1); |
b420b1a7 | 363 | break; |
b420b1a7 AC |
364 | default: |
365 | ret = -ENOIOCTLCMD; | |
317a6104 PM |
366 | } |
367 | ||
368 | return ret; | |
369 | } | |
370 | ||
371 | static int sh_rtc_read_time(struct device *dev, struct rtc_time *tm) | |
372 | { | |
373 | struct platform_device *pdev = to_platform_device(dev); | |
374 | struct sh_rtc *rtc = platform_get_drvdata(pdev); | |
375 | unsigned int sec128, sec2, yr, yr100, cf_bit; | |
376 | ||
377 | do { | |
378 | unsigned int tmp; | |
379 | ||
380 | spin_lock_irq(&rtc->lock); | |
381 | ||
382 | tmp = readb(rtc->regbase + RCR1); | |
383 | tmp &= ~RCR1_CF; /* Clear CF-bit */ | |
384 | tmp |= RCR1_CIE; | |
385 | writeb(tmp, rtc->regbase + RCR1); | |
386 | ||
387 | sec128 = readb(rtc->regbase + R64CNT); | |
388 | ||
fe20ba70 AB |
389 | tm->tm_sec = bcd2bin(readb(rtc->regbase + RSECCNT)); |
390 | tm->tm_min = bcd2bin(readb(rtc->regbase + RMINCNT)); | |
391 | tm->tm_hour = bcd2bin(readb(rtc->regbase + RHRCNT)); | |
392 | tm->tm_wday = bcd2bin(readb(rtc->regbase + RWKCNT)); | |
393 | tm->tm_mday = bcd2bin(readb(rtc->regbase + RDAYCNT)); | |
394 | tm->tm_mon = bcd2bin(readb(rtc->regbase + RMONCNT)) - 1; | |
317a6104 | 395 | |
ad89f87a PM |
396 | if (rtc->capabilities & RTC_CAP_4_DIGIT_YEAR) { |
397 | yr = readw(rtc->regbase + RYRCNT); | |
fe20ba70 | 398 | yr100 = bcd2bin(yr >> 8); |
ad89f87a PM |
399 | yr &= 0xff; |
400 | } else { | |
401 | yr = readb(rtc->regbase + RYRCNT); | |
fe20ba70 | 402 | yr100 = bcd2bin((yr == 0x99) ? 0x19 : 0x20); |
ad89f87a | 403 | } |
317a6104 | 404 | |
fe20ba70 | 405 | tm->tm_year = (yr100 * 100 + bcd2bin(yr)) - 1900; |
317a6104 PM |
406 | |
407 | sec2 = readb(rtc->regbase + R64CNT); | |
408 | cf_bit = readb(rtc->regbase + RCR1) & RCR1_CF; | |
409 | ||
410 | spin_unlock_irq(&rtc->lock); | |
411 | } while (cf_bit != 0 || ((sec128 ^ sec2) & RTC_BIT_INVERTED) != 0); | |
412 | ||
413 | #if RTC_BIT_INVERTED != 0 | |
414 | if ((sec128 & RTC_BIT_INVERTED)) | |
415 | tm->tm_sec--; | |
416 | #endif | |
417 | ||
9cd88b90 MD |
418 | /* only keep the carry interrupt enabled if UIE is on */ |
419 | if (!(rtc->periodic_freq & PF_OXS)) | |
420 | sh_rtc_setcie(dev, 0); | |
421 | ||
435c55d1 | 422 | dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, " |
317a6104 | 423 | "mday=%d, mon=%d, year=%d, wday=%d\n", |
2a4e2b87 | 424 | __func__, |
317a6104 | 425 | tm->tm_sec, tm->tm_min, tm->tm_hour, |
a1614796 | 426 | tm->tm_mday, tm->tm_mon + 1, tm->tm_year, tm->tm_wday); |
317a6104 | 427 | |
edf22477 | 428 | return rtc_valid_tm(tm); |
317a6104 PM |
429 | } |
430 | ||
431 | static int sh_rtc_set_time(struct device *dev, struct rtc_time *tm) | |
432 | { | |
433 | struct platform_device *pdev = to_platform_device(dev); | |
434 | struct sh_rtc *rtc = platform_get_drvdata(pdev); | |
435 | unsigned int tmp; | |
436 | int year; | |
437 | ||
438 | spin_lock_irq(&rtc->lock); | |
439 | ||
440 | /* Reset pre-scaler & stop RTC */ | |
441 | tmp = readb(rtc->regbase + RCR2); | |
442 | tmp |= RCR2_RESET; | |
699bc661 | 443 | tmp &= ~RCR2_START; |
317a6104 PM |
444 | writeb(tmp, rtc->regbase + RCR2); |
445 | ||
fe20ba70 AB |
446 | writeb(bin2bcd(tm->tm_sec), rtc->regbase + RSECCNT); |
447 | writeb(bin2bcd(tm->tm_min), rtc->regbase + RMINCNT); | |
448 | writeb(bin2bcd(tm->tm_hour), rtc->regbase + RHRCNT); | |
449 | writeb(bin2bcd(tm->tm_wday), rtc->regbase + RWKCNT); | |
450 | writeb(bin2bcd(tm->tm_mday), rtc->regbase + RDAYCNT); | |
451 | writeb(bin2bcd(tm->tm_mon + 1), rtc->regbase + RMONCNT); | |
317a6104 | 452 | |
ad89f87a | 453 | if (rtc->capabilities & RTC_CAP_4_DIGIT_YEAR) { |
fe20ba70 AB |
454 | year = (bin2bcd((tm->tm_year + 1900) / 100) << 8) | |
455 | bin2bcd(tm->tm_year % 100); | |
ad89f87a PM |
456 | writew(year, rtc->regbase + RYRCNT); |
457 | } else { | |
458 | year = tm->tm_year % 100; | |
fe20ba70 | 459 | writeb(bin2bcd(year), rtc->regbase + RYRCNT); |
ad89f87a | 460 | } |
317a6104 PM |
461 | |
462 | /* Start RTC */ | |
463 | tmp = readb(rtc->regbase + RCR2); | |
464 | tmp &= ~RCR2_RESET; | |
465 | tmp |= RCR2_RTCEN | RCR2_START; | |
466 | writeb(tmp, rtc->regbase + RCR2); | |
467 | ||
468 | spin_unlock_irq(&rtc->lock); | |
469 | ||
470 | return 0; | |
471 | } | |
472 | ||
1b73e6ae JL |
473 | static inline int sh_rtc_read_alarm_value(struct sh_rtc *rtc, int reg_off) |
474 | { | |
475 | unsigned int byte; | |
476 | int value = 0xff; /* return 0xff for ignored values */ | |
477 | ||
478 | byte = readb(rtc->regbase + reg_off); | |
479 | if (byte & AR_ENB) { | |
480 | byte &= ~AR_ENB; /* strip the enable bit */ | |
fe20ba70 | 481 | value = bcd2bin(byte); |
1b73e6ae JL |
482 | } |
483 | ||
484 | return value; | |
485 | } | |
486 | ||
487 | static int sh_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *wkalrm) | |
488 | { | |
489 | struct platform_device *pdev = to_platform_device(dev); | |
490 | struct sh_rtc *rtc = platform_get_drvdata(pdev); | |
b420b1a7 | 491 | struct rtc_time *tm = &wkalrm->time; |
1b73e6ae JL |
492 | |
493 | spin_lock_irq(&rtc->lock); | |
494 | ||
495 | tm->tm_sec = sh_rtc_read_alarm_value(rtc, RSECAR); | |
496 | tm->tm_min = sh_rtc_read_alarm_value(rtc, RMINAR); | |
497 | tm->tm_hour = sh_rtc_read_alarm_value(rtc, RHRAR); | |
498 | tm->tm_wday = sh_rtc_read_alarm_value(rtc, RWKAR); | |
499 | tm->tm_mday = sh_rtc_read_alarm_value(rtc, RDAYAR); | |
500 | tm->tm_mon = sh_rtc_read_alarm_value(rtc, RMONAR); | |
501 | if (tm->tm_mon > 0) | |
502 | tm->tm_mon -= 1; /* RTC is 1-12, tm_mon is 0-11 */ | |
503 | tm->tm_year = 0xffff; | |
504 | ||
0d103e90 DB |
505 | wkalrm->enabled = (readb(rtc->regbase + RCR1) & RCR1_AIE) ? 1 : 0; |
506 | ||
1b73e6ae JL |
507 | spin_unlock_irq(&rtc->lock); |
508 | ||
509 | return 0; | |
510 | } | |
511 | ||
512 | static inline void sh_rtc_write_alarm_value(struct sh_rtc *rtc, | |
513 | int value, int reg_off) | |
514 | { | |
515 | /* < 0 for a value that is ignored */ | |
516 | if (value < 0) | |
517 | writeb(0, rtc->regbase + reg_off); | |
518 | else | |
fe20ba70 | 519 | writeb(bin2bcd(value) | AR_ENB, rtc->regbase + reg_off); |
1b73e6ae JL |
520 | } |
521 | ||
b420b1a7 | 522 | static int sh_rtc_check_alarm(struct rtc_time *tm) |
1b73e6ae JL |
523 | { |
524 | /* | |
525 | * The original rtc says anything > 0xc0 is "don't care" or "match | |
526 | * all" - most users use 0xff but rtc-dev uses -1 for the same thing. | |
527 | * The original rtc doesn't support years - some things use -1 and | |
528 | * some 0xffff. We use -1 to make out tests easier. | |
529 | */ | |
530 | if (tm->tm_year == 0xffff) | |
531 | tm->tm_year = -1; | |
532 | if (tm->tm_mon >= 0xff) | |
533 | tm->tm_mon = -1; | |
534 | if (tm->tm_mday >= 0xff) | |
535 | tm->tm_mday = -1; | |
536 | if (tm->tm_wday >= 0xff) | |
537 | tm->tm_wday = -1; | |
538 | if (tm->tm_hour >= 0xff) | |
539 | tm->tm_hour = -1; | |
540 | if (tm->tm_min >= 0xff) | |
541 | tm->tm_min = -1; | |
542 | if (tm->tm_sec >= 0xff) | |
543 | tm->tm_sec = -1; | |
544 | ||
545 | if (tm->tm_year > 9999 || | |
546 | tm->tm_mon >= 12 || | |
547 | tm->tm_mday == 0 || tm->tm_mday >= 32 || | |
548 | tm->tm_wday >= 7 || | |
549 | tm->tm_hour >= 24 || | |
550 | tm->tm_min >= 60 || | |
551 | tm->tm_sec >= 60) | |
552 | return -EINVAL; | |
553 | ||
554 | return 0; | |
555 | } | |
556 | ||
557 | static int sh_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *wkalrm) | |
558 | { | |
559 | struct platform_device *pdev = to_platform_device(dev); | |
560 | struct sh_rtc *rtc = platform_get_drvdata(pdev); | |
561 | unsigned int rcr1; | |
562 | struct rtc_time *tm = &wkalrm->time; | |
563 | int mon, err; | |
564 | ||
565 | err = sh_rtc_check_alarm(tm); | |
566 | if (unlikely(err < 0)) | |
567 | return err; | |
568 | ||
569 | spin_lock_irq(&rtc->lock); | |
570 | ||
15c945c3 | 571 | /* disable alarm interrupt and clear the alarm flag */ |
1b73e6ae | 572 | rcr1 = readb(rtc->regbase + RCR1); |
b420b1a7 | 573 | rcr1 &= ~(RCR1_AF | RCR1_AIE); |
15c945c3 | 574 | writeb(rcr1, rtc->regbase + RCR1); |
1b73e6ae | 575 | |
1b73e6ae JL |
576 | /* set alarm time */ |
577 | sh_rtc_write_alarm_value(rtc, tm->tm_sec, RSECAR); | |
578 | sh_rtc_write_alarm_value(rtc, tm->tm_min, RMINAR); | |
579 | sh_rtc_write_alarm_value(rtc, tm->tm_hour, RHRAR); | |
580 | sh_rtc_write_alarm_value(rtc, tm->tm_wday, RWKAR); | |
581 | sh_rtc_write_alarm_value(rtc, tm->tm_mday, RDAYAR); | |
582 | mon = tm->tm_mon; | |
583 | if (mon >= 0) | |
584 | mon += 1; | |
585 | sh_rtc_write_alarm_value(rtc, mon, RMONAR); | |
586 | ||
15c945c3 JL |
587 | if (wkalrm->enabled) { |
588 | rcr1 |= RCR1_AIE; | |
589 | writeb(rcr1, rtc->regbase + RCR1); | |
590 | } | |
1b73e6ae JL |
591 | |
592 | spin_unlock_irq(&rtc->lock); | |
593 | ||
594 | return 0; | |
595 | } | |
596 | ||
317a6104 | 597 | static struct rtc_class_ops sh_rtc_ops = { |
317a6104 PM |
598 | .ioctl = sh_rtc_ioctl, |
599 | .read_time = sh_rtc_read_time, | |
600 | .set_time = sh_rtc_set_time, | |
1b73e6ae JL |
601 | .read_alarm = sh_rtc_read_alarm, |
602 | .set_alarm = sh_rtc_set_alarm, | |
b420b1a7 AC |
603 | .irq_set_state = sh_rtc_irq_set_state, |
604 | .irq_set_freq = sh_rtc_irq_set_freq, | |
317a6104 PM |
605 | .proc = sh_rtc_proc, |
606 | }; | |
607 | ||
5c9740a8 | 608 | static int __init sh_rtc_probe(struct platform_device *pdev) |
317a6104 PM |
609 | { |
610 | struct sh_rtc *rtc; | |
611 | struct resource *res; | |
edf22477 | 612 | struct rtc_time r; |
063adc75 PM |
613 | char clk_name[6]; |
614 | int clk_id, ret; | |
317a6104 PM |
615 | |
616 | rtc = kzalloc(sizeof(struct sh_rtc), GFP_KERNEL); | |
617 | if (unlikely(!rtc)) | |
618 | return -ENOMEM; | |
619 | ||
620 | spin_lock_init(&rtc->lock); | |
621 | ||
b420b1a7 | 622 | /* get periodic/carry/alarm irqs */ |
2641dc92 | 623 | ret = platform_get_irq(pdev, 0); |
2fac6674 | 624 | if (unlikely(ret <= 0)) { |
2641dc92 | 625 | ret = -ENOENT; |
5e084a15 | 626 | dev_err(&pdev->dev, "No IRQ resource\n"); |
317a6104 PM |
627 | goto err_badres; |
628 | } | |
063adc75 | 629 | |
2641dc92 | 630 | rtc->periodic_irq = ret; |
5e084a15 MD |
631 | rtc->carry_irq = platform_get_irq(pdev, 1); |
632 | rtc->alarm_irq = platform_get_irq(pdev, 2); | |
317a6104 PM |
633 | |
634 | res = platform_get_resource(pdev, IORESOURCE_IO, 0); | |
635 | if (unlikely(res == NULL)) { | |
2641dc92 | 636 | ret = -ENOENT; |
317a6104 PM |
637 | dev_err(&pdev->dev, "No IO resource\n"); |
638 | goto err_badres; | |
639 | } | |
640 | ||
063adc75 | 641 | rtc->regsize = resource_size(res); |
317a6104 PM |
642 | |
643 | rtc->res = request_mem_region(res->start, rtc->regsize, pdev->name); | |
644 | if (unlikely(!rtc->res)) { | |
645 | ret = -EBUSY; | |
646 | goto err_badres; | |
647 | } | |
648 | ||
0305794c | 649 | rtc->regbase = ioremap_nocache(rtc->res->start, rtc->regsize); |
317a6104 PM |
650 | if (unlikely(!rtc->regbase)) { |
651 | ret = -EINVAL; | |
652 | goto err_badmap; | |
653 | } | |
654 | ||
063adc75 PM |
655 | clk_id = pdev->id; |
656 | /* With a single device, the clock id is still "rtc0" */ | |
657 | if (clk_id < 0) | |
658 | clk_id = 0; | |
659 | ||
660 | snprintf(clk_name, sizeof(clk_name), "rtc%d", clk_id); | |
661 | ||
662 | rtc->clk = clk_get(&pdev->dev, clk_name); | |
663 | if (IS_ERR(rtc->clk)) { | |
664 | /* | |
665 | * No error handling for rtc->clk intentionally, not all | |
666 | * platforms will have a unique clock for the RTC, and | |
667 | * the clk API can handle the struct clk pointer being | |
668 | * NULL. | |
669 | */ | |
670 | rtc->clk = NULL; | |
671 | } | |
672 | ||
673 | clk_enable(rtc->clk); | |
674 | ||
ad89f87a PM |
675 | rtc->capabilities = RTC_DEF_CAPABILITIES; |
676 | if (pdev->dev.platform_data) { | |
677 | struct sh_rtc_platform_info *pinfo = pdev->dev.platform_data; | |
678 | ||
679 | /* | |
680 | * Some CPUs have special capabilities in addition to the | |
681 | * default set. Add those in here. | |
682 | */ | |
683 | rtc->capabilities |= pinfo->capabilities; | |
684 | } | |
685 | ||
5e084a15 MD |
686 | if (rtc->carry_irq <= 0) { |
687 | /* register shared periodic/carry/alarm irq */ | |
688 | ret = request_irq(rtc->periodic_irq, sh_rtc_shared, | |
689 | IRQF_DISABLED, "sh-rtc", rtc); | |
690 | if (unlikely(ret)) { | |
691 | dev_err(&pdev->dev, | |
692 | "request IRQ failed with %d, IRQ %d\n", ret, | |
693 | rtc->periodic_irq); | |
694 | goto err_unmap; | |
695 | } | |
696 | } else { | |
697 | /* register periodic/carry/alarm irqs */ | |
698 | ret = request_irq(rtc->periodic_irq, sh_rtc_periodic, | |
699 | IRQF_DISABLED, "sh-rtc period", rtc); | |
700 | if (unlikely(ret)) { | |
701 | dev_err(&pdev->dev, | |
702 | "request period IRQ failed with %d, IRQ %d\n", | |
703 | ret, rtc->periodic_irq); | |
704 | goto err_unmap; | |
705 | } | |
b420b1a7 | 706 | |
5e084a15 MD |
707 | ret = request_irq(rtc->carry_irq, sh_rtc_interrupt, |
708 | IRQF_DISABLED, "sh-rtc carry", rtc); | |
709 | if (unlikely(ret)) { | |
710 | dev_err(&pdev->dev, | |
711 | "request carry IRQ failed with %d, IRQ %d\n", | |
712 | ret, rtc->carry_irq); | |
713 | free_irq(rtc->periodic_irq, rtc); | |
714 | goto err_unmap; | |
715 | } | |
b420b1a7 | 716 | |
5e084a15 MD |
717 | ret = request_irq(rtc->alarm_irq, sh_rtc_alarm, |
718 | IRQF_DISABLED, "sh-rtc alarm", rtc); | |
719 | if (unlikely(ret)) { | |
720 | dev_err(&pdev->dev, | |
721 | "request alarm IRQ failed with %d, IRQ %d\n", | |
722 | ret, rtc->alarm_irq); | |
723 | free_irq(rtc->carry_irq, rtc); | |
724 | free_irq(rtc->periodic_irq, rtc); | |
725 | goto err_unmap; | |
726 | } | |
b420b1a7 AC |
727 | } |
728 | ||
5c9740a8 AZ |
729 | platform_set_drvdata(pdev, rtc); |
730 | ||
9cd88b90 | 731 | /* everything disabled by default */ |
5c9740a8 AZ |
732 | sh_rtc_irq_set_freq(&pdev->dev, 0); |
733 | sh_rtc_irq_set_state(&pdev->dev, 0); | |
9cd88b90 MD |
734 | sh_rtc_setaie(&pdev->dev, 0); |
735 | sh_rtc_setcie(&pdev->dev, 0); | |
edf22477 | 736 | |
5c9740a8 AZ |
737 | rtc->rtc_dev = rtc_device_register("sh", &pdev->dev, |
738 | &sh_rtc_ops, THIS_MODULE); | |
739 | if (IS_ERR(rtc->rtc_dev)) { | |
740 | ret = PTR_ERR(rtc->rtc_dev); | |
741 | free_irq(rtc->periodic_irq, rtc); | |
742 | free_irq(rtc->carry_irq, rtc); | |
743 | free_irq(rtc->alarm_irq, rtc); | |
744 | goto err_unmap; | |
745 | } | |
746 | ||
747 | rtc->rtc_dev->max_user_freq = 256; | |
748 | ||
edf22477 MD |
749 | /* reset rtc to epoch 0 if time is invalid */ |
750 | if (rtc_read_time(rtc->rtc_dev, &r) < 0) { | |
751 | rtc_time_to_tm(0, &r); | |
752 | rtc_set_time(rtc->rtc_dev, &r); | |
753 | } | |
754 | ||
7a8fe8e3 | 755 | device_init_wakeup(&pdev->dev, 1); |
317a6104 PM |
756 | return 0; |
757 | ||
0305794c | 758 | err_unmap: |
063adc75 PM |
759 | clk_disable(rtc->clk); |
760 | clk_put(rtc->clk); | |
0305794c | 761 | iounmap(rtc->regbase); |
317a6104 PM |
762 | err_badmap: |
763 | release_resource(rtc->res); | |
764 | err_badres: | |
765 | kfree(rtc); | |
766 | ||
767 | return ret; | |
768 | } | |
769 | ||
5c9740a8 | 770 | static int __exit sh_rtc_remove(struct platform_device *pdev) |
317a6104 PM |
771 | { |
772 | struct sh_rtc *rtc = platform_get_drvdata(pdev); | |
773 | ||
5c9740a8 AZ |
774 | rtc_device_unregister(rtc->rtc_dev); |
775 | sh_rtc_irq_set_state(&pdev->dev, 0); | |
317a6104 | 776 | |
317a6104 | 777 | sh_rtc_setaie(&pdev->dev, 0); |
9cd88b90 | 778 | sh_rtc_setcie(&pdev->dev, 0); |
317a6104 | 779 | |
b420b1a7 | 780 | free_irq(rtc->periodic_irq, rtc); |
063adc75 | 781 | |
5e084a15 MD |
782 | if (rtc->carry_irq > 0) { |
783 | free_irq(rtc->carry_irq, rtc); | |
784 | free_irq(rtc->alarm_irq, rtc); | |
785 | } | |
b420b1a7 | 786 | |
0305794c | 787 | iounmap(rtc->regbase); |
5c9740a8 | 788 | release_resource(rtc->res); |
0305794c | 789 | |
063adc75 PM |
790 | clk_disable(rtc->clk); |
791 | clk_put(rtc->clk); | |
792 | ||
317a6104 PM |
793 | platform_set_drvdata(pdev, NULL); |
794 | ||
795 | kfree(rtc); | |
796 | ||
797 | return 0; | |
798 | } | |
faa9fa8e MD |
799 | |
800 | static void sh_rtc_set_irq_wake(struct device *dev, int enabled) | |
801 | { | |
802 | struct platform_device *pdev = to_platform_device(dev); | |
803 | struct sh_rtc *rtc = platform_get_drvdata(pdev); | |
804 | ||
805 | set_irq_wake(rtc->periodic_irq, enabled); | |
063adc75 | 806 | |
faa9fa8e MD |
807 | if (rtc->carry_irq > 0) { |
808 | set_irq_wake(rtc->carry_irq, enabled); | |
809 | set_irq_wake(rtc->alarm_irq, enabled); | |
810 | } | |
faa9fa8e MD |
811 | } |
812 | ||
813 | static int sh_rtc_suspend(struct device *dev) | |
814 | { | |
815 | if (device_may_wakeup(dev)) | |
816 | sh_rtc_set_irq_wake(dev, 1); | |
817 | ||
818 | return 0; | |
819 | } | |
820 | ||
821 | static int sh_rtc_resume(struct device *dev) | |
822 | { | |
823 | if (device_may_wakeup(dev)) | |
824 | sh_rtc_set_irq_wake(dev, 0); | |
825 | ||
826 | return 0; | |
827 | } | |
828 | ||
829 | static struct dev_pm_ops sh_rtc_dev_pm_ops = { | |
830 | .suspend = sh_rtc_suspend, | |
831 | .resume = sh_rtc_resume, | |
832 | }; | |
833 | ||
317a6104 PM |
834 | static struct platform_driver sh_rtc_platform_driver = { |
835 | .driver = { | |
1b73e6ae | 836 | .name = DRV_NAME, |
317a6104 | 837 | .owner = THIS_MODULE, |
faa9fa8e | 838 | .pm = &sh_rtc_dev_pm_ops, |
317a6104 | 839 | }, |
5c9740a8 | 840 | .remove = __exit_p(sh_rtc_remove), |
317a6104 PM |
841 | }; |
842 | ||
843 | static int __init sh_rtc_init(void) | |
844 | { | |
5c9740a8 | 845 | return platform_driver_probe(&sh_rtc_platform_driver, sh_rtc_probe); |
317a6104 PM |
846 | } |
847 | ||
848 | static void __exit sh_rtc_exit(void) | |
849 | { | |
850 | platform_driver_unregister(&sh_rtc_platform_driver); | |
851 | } | |
852 | ||
853 | module_init(sh_rtc_init); | |
854 | module_exit(sh_rtc_exit); | |
855 | ||
856 | MODULE_DESCRIPTION("SuperH on-chip RTC driver"); | |
1b73e6ae | 857 | MODULE_VERSION(DRV_VERSION); |
b420b1a7 AC |
858 | MODULE_AUTHOR("Paul Mundt <lethal@linux-sh.org>, " |
859 | "Jamie Lenehan <lenehan@twibble.org>, " | |
860 | "Angelo Castello <angelo.castello@st.com>"); | |
317a6104 | 861 | MODULE_LICENSE("GPL"); |
ad28a07b | 862 | MODULE_ALIAS("platform:" DRV_NAME); |