[deliverable/linux.git] / drivers / rtc / rtc-sirfsoc.c

/*
 * SiRFSoC Real Time Clock interface for Linux
 *
 * Copyright (c) 2013 Cambridge Silicon Radio Limited, a CSR plc group company.
 *
 * Licensed under GPLv2 or later.
 */

#include <linux/module.h>
#include <linux/err.h>
#include <linux/rtc.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/rtc/sirfsoc_rtciobrg.h>


#define RTC_CN			0x00
#define RTC_ALARM0		0x04
#define RTC_ALARM1		0x18
#define RTC_STATUS		0x08
#define RTC_SW_VALUE            0x40
#define SIRFSOC_RTC_AL1E	(1<<6)
#define SIRFSOC_RTC_AL1		(1<<4)
#define SIRFSOC_RTC_HZE		(1<<3)
#define SIRFSOC_RTC_AL0E	(1<<2)
#define SIRFSOC_RTC_HZ		(1<<1)
#define SIRFSOC_RTC_AL0		(1<<0)
#define RTC_DIV			0x0c
#define RTC_DEEP_CTRL		0x14
#define RTC_CLOCK_SWITCH	0x1c
#define SIRFSOC_RTC_CLK		0x03	/* others are reserved */

/* Refer to RTC DIV switch */
#define RTC_HZ			16

/* This macro is also defined in arch/arm/plat-sirfsoc/cpu.c */
#define RTC_SHIFT		4

#define INTR_SYSRTC_CN		0x48

struct sirfsoc_rtc_drv {
	struct rtc_device	*rtc;
	u32			rtc_base;
	u32			irq;
	unsigned		irq_wake;
	/* Overflow for every 8 years extra time */
	u32			overflow_rtc;
	spinlock_t		lock;
#ifdef CONFIG_PM
	u32		saved_counter;
	u32		saved_overflow_rtc;
#endif
};

static int sirfsoc_rtc_read_alarm(struct device *dev,
		struct rtc_wkalrm *alrm)
{
	unsigned long rtc_alarm, rtc_count;
	struct sirfsoc_rtc_drv *rtcdrv;

	rtcdrv = dev_get_drvdata(dev);

	spin_lock_irq(&rtcdrv->lock);

	rtc_count = sirfsoc_rtc_iobrg_readl(rtcdrv->rtc_base + RTC_CN);

	rtc_alarm = sirfsoc_rtc_iobrg_readl(rtcdrv->rtc_base + RTC_ALARM0);
	memset(alrm, 0, sizeof(struct rtc_wkalrm));

	/*
	 * assume alarm interval not beyond one round counter overflow_rtc:
	 * 0->0xffffffff
	 */
	/* if alarm is in next overflow cycle */
	if (rtc_count > rtc_alarm)
		rtc_time_to_tm((rtcdrv->overflow_rtc + 1)
				<< (BITS_PER_LONG - RTC_SHIFT)
				| rtc_alarm >> RTC_SHIFT, &(alrm->time));
	else
		rtc_time_to_tm(rtcdrv->overflow_rtc
				<< (BITS_PER_LONG - RTC_SHIFT)
				| rtc_alarm >> RTC_SHIFT, &(alrm->time));
	if (sirfsoc_rtc_iobrg_readl(
			rtcdrv->rtc_base + RTC_STATUS) & SIRFSOC_RTC_AL0E)
		alrm->enabled = 1;

	spin_unlock_irq(&rtcdrv->lock);

	return 0;
}

static int sirfsoc_rtc_set_alarm(struct device *dev,
		struct rtc_wkalrm *alrm)
{
	unsigned long rtc_status_reg, rtc_alarm;
	struct sirfsoc_rtc_drv *rtcdrv;
	rtcdrv = dev_get_drvdata(dev);

	if (alrm->enabled) {
		rtc_tm_to_time(&(alrm->time), &rtc_alarm);

		spin_lock_irq(&rtcdrv->lock);

		rtc_status_reg = sirfsoc_rtc_iobrg_readl(
				rtcdrv->rtc_base + RTC_STATUS);
		if (rtc_status_reg & SIRFSOC_RTC_AL0E) {
			/*
			 * An ongoing alarm in progress - ingore it and not
			 * to return EBUSY
			 */
			dev_info(dev, "An old alarm was set, will be replaced by a new one\n");
		}

		sirfsoc_rtc_iobrg_writel(
			rtc_alarm << RTC_SHIFT, rtcdrv->rtc_base + RTC_ALARM0);
		rtc_status_reg &= ~0x07; /* mask out the lower status bits */
		/*
		 * This bit RTC_AL sets it as a wake-up source for Sleep Mode
		 * Writing 1 into this bit will clear it
		 */
		rtc_status_reg |= SIRFSOC_RTC_AL0;
		/* enable the RTC alarm interrupt */
		rtc_status_reg |= SIRFSOC_RTC_AL0E;
		sirfsoc_rtc_iobrg_writel(
			rtc_status_reg, rtcdrv->rtc_base + RTC_STATUS);

		spin_unlock_irq(&rtcdrv->lock);
	} else {
		/*
		 * if this function was called with enabled=0
		 * then it could mean that the application is
		 * trying to cancel an ongoing alarm
		 */
		spin_lock_irq(&rtcdrv->lock);

		rtc_status_reg = sirfsoc_rtc_iobrg_readl(
				rtcdrv->rtc_base + RTC_STATUS);
		if (rtc_status_reg & SIRFSOC_RTC_AL0E) {
			/* clear the RTC status register's alarm bit */
			rtc_status_reg &= ~0x07;
			/* write 1 into SIRFSOC_RTC_AL0 to force a clear */
			rtc_status_reg |= (SIRFSOC_RTC_AL0);
			/* Clear the Alarm enable bit */
			rtc_status_reg &= ~(SIRFSOC_RTC_AL0E);

			sirfsoc_rtc_iobrg_writel(rtc_status_reg,
					rtcdrv->rtc_base + RTC_STATUS);
		}

		spin_unlock_irq(&rtcdrv->lock);
	}

	return 0;
}

static int sirfsoc_rtc_read_time(struct device *dev,
		struct rtc_time *tm)
{
	unsigned long tmp_rtc = 0;
	struct sirfsoc_rtc_drv *rtcdrv;
	rtcdrv = dev_get_drvdata(dev);
	/*
	 * This patch is taken from WinCE - Need to validate this for
	 * correctness. To work around sirfsoc RTC counter double sync logic
	 * fail, read several times to make sure get stable value.
	 */
	do {
		tmp_rtc = sirfsoc_rtc_iobrg_readl(rtcdrv->rtc_base + RTC_CN);
		cpu_relax();
	} while (tmp_rtc != sirfsoc_rtc_iobrg_readl(rtcdrv->rtc_base + RTC_CN));

	rtc_time_to_tm(rtcdrv->overflow_rtc << (BITS_PER_LONG - RTC_SHIFT) |
					tmp_rtc >> RTC_SHIFT, tm);
	return 0;
}

static int sirfsoc_rtc_set_time(struct device *dev,
		struct rtc_time *tm)
{
	unsigned long rtc_time;
	struct sirfsoc_rtc_drv *rtcdrv;
	rtcdrv = dev_get_drvdata(dev);

	rtc_tm_to_time(tm, &rtc_time);

	rtcdrv->overflow_rtc = rtc_time >> (BITS_PER_LONG - RTC_SHIFT);

	sirfsoc_rtc_iobrg_writel(rtcdrv->overflow_rtc,
			rtcdrv->rtc_base + RTC_SW_VALUE);
	sirfsoc_rtc_iobrg_writel(
			rtc_time << RTC_SHIFT, rtcdrv->rtc_base + RTC_CN);

	return 0;
}

static int sirfsoc_rtc_ioctl(struct device *dev, unsigned int cmd,
		unsigned long arg)
{
	switch (cmd) {
	case RTC_PIE_ON:
	case RTC_PIE_OFF:
	case RTC_UIE_ON:
	case RTC_UIE_OFF:
	case RTC_AIE_ON:
	case RTC_AIE_OFF:
		return 0;

	default:
		return -ENOIOCTLCMD;
	}
}

static int sirfsoc_rtc_alarm_irq_enable(struct device *dev,
		unsigned int enabled)
{
	unsigned long rtc_status_reg = 0x0;
	struct sirfsoc_rtc_drv *rtcdrv;

	rtcdrv = dev_get_drvdata(dev);

	spin_lock_irq(&rtcdrv->lock);

	rtc_status_reg = sirfsoc_rtc_iobrg_readl(
				rtcdrv->rtc_base + RTC_STATUS);
	if (enabled)
		rtc_status_reg |= SIRFSOC_RTC_AL0E;
	else
		rtc_status_reg &= ~SIRFSOC_RTC_AL0E;

	sirfsoc_rtc_iobrg_writel(rtc_status_reg, rtcdrv->rtc_base + RTC_STATUS);

	spin_unlock_irq(&rtcdrv->lock);

	return 0;

}

static const struct rtc_class_ops sirfsoc_rtc_ops = {
	.read_time = sirfsoc_rtc_read_time,
	.set_time = sirfsoc_rtc_set_time,
	.read_alarm = sirfsoc_rtc_read_alarm,
	.set_alarm = sirfsoc_rtc_set_alarm,
	.ioctl = sirfsoc_rtc_ioctl,
	.alarm_irq_enable = sirfsoc_rtc_alarm_irq_enable
};

static irqreturn_t sirfsoc_rtc_irq_handler(int irq, void *pdata)
{
	struct sirfsoc_rtc_drv *rtcdrv = pdata;
	unsigned long rtc_status_reg = 0x0;
	unsigned long events = 0x0;

	spin_lock(&rtcdrv->lock);

	rtc_status_reg = sirfsoc_rtc_iobrg_readl(rtcdrv->rtc_base + RTC_STATUS);
	/* this bit will be set ONLY if an alarm was active
	 * and it expired NOW
	 * So this is being used as an ASSERT
	 */
	if (rtc_status_reg & SIRFSOC_RTC_AL0) {
		/*
		 * clear the RTC status register's alarm bit
		 * mask out the lower status bits
		 */
		rtc_status_reg &= ~0x07;
		/* write 1 into SIRFSOC_RTC_AL0 to ACK the alarm interrupt */
		rtc_status_reg |= (SIRFSOC_RTC_AL0);
		/* Clear the Alarm enable bit */
		rtc_status_reg &= ~(SIRFSOC_RTC_AL0E);
	}
	sirfsoc_rtc_iobrg_writel(rtc_status_reg, rtcdrv->rtc_base + RTC_STATUS);

	spin_unlock(&rtcdrv->lock);

	/* this should wake up any apps polling/waiting on the read
	 * after setting the alarm
	 */
	events |= RTC_IRQF | RTC_AF;
	rtc_update_irq(rtcdrv->rtc, 1, events);

	return IRQ_HANDLED;
}

static const struct of_device_id sirfsoc_rtc_of_match[] = {
	{ .compatible = "sirf,prima2-sysrtc"},
	{},
};
MODULE_DEVICE_TABLE(of, sirfsoc_rtc_of_match);

static int sirfsoc_rtc_probe(struct platform_device *pdev)
{
	int err;
	unsigned long rtc_div;
	struct sirfsoc_rtc_drv *rtcdrv;
	struct device_node *np = pdev->dev.of_node;

	rtcdrv = devm_kzalloc(&pdev->dev,
		sizeof(struct sirfsoc_rtc_drv), GFP_KERNEL);
	if (rtcdrv == NULL)
		return -ENOMEM;

	spin_lock_init(&rtcdrv->lock);

	err = of_property_read_u32(np, "reg", &rtcdrv->rtc_base);
	if (err) {
		dev_err(&pdev->dev, "unable to find base address of rtc node in dtb\n");
		return err;
	}

	platform_set_drvdata(pdev, rtcdrv);

	/* Register rtc alarm as a wakeup source */
	device_init_wakeup(&pdev->dev, 1);

	/*
	 * Set SYS_RTC counter in RTC_HZ HZ Units
	 * We are using 32K RTC crystal (32768 / RTC_HZ / 2) -1
	 * If 16HZ, therefore RTC_DIV = 1023;
	 */
	rtc_div = ((32768 / RTC_HZ) / 2) - 1;
	sirfsoc_rtc_iobrg_writel(rtc_div, rtcdrv->rtc_base + RTC_DIV);

	/* 0x3 -> RTC_CLK */
	sirfsoc_rtc_iobrg_writel(SIRFSOC_RTC_CLK,
			rtcdrv->rtc_base + RTC_CLOCK_SWITCH);

	/* reset SYS RTC ALARM0 */
	sirfsoc_rtc_iobrg_writel(0x0, rtcdrv->rtc_base + RTC_ALARM0);

	/* reset SYS RTC ALARM1 */
	sirfsoc_rtc_iobrg_writel(0x0, rtcdrv->rtc_base + RTC_ALARM1);

	/* Restore RTC Overflow From Register After Command Reboot */
	rtcdrv->overflow_rtc =
		sirfsoc_rtc_iobrg_readl(rtcdrv->rtc_base + RTC_SW_VALUE);

	rtcdrv->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
			&sirfsoc_rtc_ops, THIS_MODULE);
	if (IS_ERR(rtcdrv->rtc)) {
		err = PTR_ERR(rtcdrv->rtc);
		dev_err(&pdev->dev, "can't register RTC device\n");
		return err;
	}

	rtcdrv->irq = platform_get_irq(pdev, 0);
	err = devm_request_irq(
			&pdev->dev,
			rtcdrv->irq,
			sirfsoc_rtc_irq_handler,
			IRQF_SHARED,
			pdev->name,
			rtcdrv);
	if (err) {
		dev_err(&pdev->dev, "Unable to register for the SiRF SOC RTC IRQ\n");
		return err;
	}

	return 0;
}

static int sirfsoc_rtc_remove(struct platform_device *pdev)
{
	device_init_wakeup(&pdev->dev, 0);

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int sirfsoc_rtc_suspend(struct device *dev)
{
	struct sirfsoc_rtc_drv *rtcdrv = dev_get_drvdata(dev);
	rtcdrv->overflow_rtc =
		sirfsoc_rtc_iobrg_readl(rtcdrv->rtc_base + RTC_SW_VALUE);

	rtcdrv->saved_counter =
		sirfsoc_rtc_iobrg_readl(rtcdrv->rtc_base + RTC_CN);
	rtcdrv->saved_overflow_rtc = rtcdrv->overflow_rtc;
	if (device_may_wakeup(dev) && !enable_irq_wake(rtcdrv->irq))
		rtcdrv->irq_wake = 1;

	return 0;
}

static int sirfsoc_rtc_resume(struct device *dev)
{
	u32 tmp;
	struct sirfsoc_rtc_drv *rtcdrv = dev_get_drvdata(dev);

	/*
	 * if resume from snapshot and the rtc power is lost,
	 * restroe the rtc settings
	 */
	if (SIRFSOC_RTC_CLK != sirfsoc_rtc_iobrg_readl(
			rtcdrv->rtc_base + RTC_CLOCK_SWITCH)) {
		u32 rtc_div;
		/* 0x3 -> RTC_CLK */
		sirfsoc_rtc_iobrg_writel(SIRFSOC_RTC_CLK,
			rtcdrv->rtc_base + RTC_CLOCK_SWITCH);
		/*
		 * Set SYS_RTC counter in RTC_HZ HZ Units
		 * We are using 32K RTC crystal (32768 / RTC_HZ / 2) -1
		 * If 16HZ, therefore RTC_DIV = 1023;
		 */
		rtc_div = ((32768 / RTC_HZ) / 2) - 1;

		sirfsoc_rtc_iobrg_writel(rtc_div, rtcdrv->rtc_base + RTC_DIV);

		/* reset SYS RTC ALARM0 */
		sirfsoc_rtc_iobrg_writel(0x0, rtcdrv->rtc_base + RTC_ALARM0);

		/* reset SYS RTC ALARM1 */
		sirfsoc_rtc_iobrg_writel(0x0, rtcdrv->rtc_base + RTC_ALARM1);
	}
	rtcdrv->overflow_rtc = rtcdrv->saved_overflow_rtc;

	/*
	 * if current counter is small than previous,
	 * it means overflow in sleep
	 */
	tmp = sirfsoc_rtc_iobrg_readl(rtcdrv->rtc_base + RTC_CN);
	if (tmp <= rtcdrv->saved_counter)
		rtcdrv->overflow_rtc++;
	/*
	 *PWRC Value Be Changed When Suspend, Restore Overflow
	 * In Memory To Register
	 */
	sirfsoc_rtc_iobrg_writel(rtcdrv->overflow_rtc,
			rtcdrv->rtc_base + RTC_SW_VALUE);

	if (device_may_wakeup(dev) && rtcdrv->irq_wake) {
		disable_irq_wake(rtcdrv->irq);
		rtcdrv->irq_wake = 0;
	}

	return 0;
}
#endif

static SIMPLE_DEV_PM_OPS(sirfsoc_rtc_pm_ops,
		sirfsoc_rtc_suspend, sirfsoc_rtc_resume);

static struct platform_driver sirfsoc_rtc_driver = {
	.driver = {
		.name = "sirfsoc-rtc",
		.pm = &sirfsoc_rtc_pm_ops,
		.of_match_table = sirfsoc_rtc_of_match,
	},
	.probe = sirfsoc_rtc_probe,
	.remove = sirfsoc_rtc_remove,
};
module_platform_driver(sirfsoc_rtc_driver);

MODULE_DESCRIPTION("SiRF SoC rtc driver");
MODULE_AUTHOR("Xianglong Du <Xianglong.Du@csr.com>");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:sirfsoc-rtc");
Commit	Line	Data
e88b815e XD	1	/*
	2	* SiRFSoC Real Time Clock interface for Linux
	3	*
	4	* Copyright (c) 2013 Cambridge Silicon Radio Limited, a CSR plc group company.
	5	*
	6	* Licensed under GPLv2 or later.
	7	*/
	8
	9	#include <linux/module.h>
	10	#include <linux/err.h>
	11	#include <linux/rtc.h>
	12	#include <linux/platform_device.h>
	13	#include <linux/slab.h>
	14	#include <linux/io.h>
	15	#include <linux/of.h>
	16	#include <linux/rtc/sirfsoc_rtciobrg.h>
	17
	18
	19	#define RTC_CN 0x00
	20	#define RTC_ALARM0 0x04
	21	#define RTC_ALARM1 0x18
	22	#define RTC_STATUS 0x08
	23	#define RTC_SW_VALUE 0x40
	24	#define SIRFSOC_RTC_AL1E (1<<6)
	25	#define SIRFSOC_RTC_AL1 (1<<4)
	26	#define SIRFSOC_RTC_HZE (1<<3)
	27	#define SIRFSOC_RTC_AL0E (1<<2)
	28	#define SIRFSOC_RTC_HZ (1<<1)
	29	#define SIRFSOC_RTC_AL0 (1<<0)
	30	#define RTC_DIV 0x0c
	31	#define RTC_DEEP_CTRL 0x14
	32	#define RTC_CLOCK_SWITCH 0x1c
	33	#define SIRFSOC_RTC_CLK 0x03 /* others are reserved */
	34
	35	/* Refer to RTC DIV switch */
	36	#define RTC_HZ 16
	37
	38	/* This macro is also defined in arch/arm/plat-sirfsoc/cpu.c */
	39	#define RTC_SHIFT 4
	40
	41	#define INTR_SYSRTC_CN 0x48
	42
	43	struct sirfsoc_rtc_drv {
	44	struct rtc_device *rtc;
	45	u32 rtc_base;
	46	u32 irq;
28984c7d	47	unsigned irq_wake;
e88b815e XD	48	/* Overflow for every 8 years extra time */
e88b815e XD	49	u32 overflow_rtc;
e9bc7363	50	spinlock_t lock;
e88b815e XD	51	#ifdef CONFIG_PM
	52	u32 saved_counter;
	53	u32 saved_overflow_rtc;
	54	#endif
	55	};
	56
	57	static int sirfsoc_rtc_read_alarm(struct device *dev,
	58	struct rtc_wkalrm *alrm)
	59	{
	60	unsigned long rtc_alarm, rtc_count;
	61	struct sirfsoc_rtc_drv *rtcdrv;
	62
b7efdf3b	63	rtcdrv = dev_get_drvdata(dev);
e88b815e	64
e9bc7363	65	spin_lock_irq(&rtcdrv->lock);
e88b815e XD	66
	67	rtc_count = sirfsoc_rtc_iobrg_readl(rtcdrv->rtc_base + RTC_CN);
	68
	69	rtc_alarm = sirfsoc_rtc_iobrg_readl(rtcdrv->rtc_base + RTC_ALARM0);
	70	memset(alrm, 0, sizeof(struct rtc_wkalrm));
	71
	72	/*
	73	* assume alarm interval not beyond one round counter overflow_rtc:
	74	* 0->0xffffffff
	75	*/
	76	/* if alarm is in next overflow cycle */
	77	if (rtc_count > rtc_alarm)
	78	rtc_time_to_tm((rtcdrv->overflow_rtc + 1)
	79	<< (BITS_PER_LONG - RTC_SHIFT)
	80	\| rtc_alarm >> RTC_SHIFT, &(alrm->time));
	81	else
	82	rtc_time_to_tm(rtcdrv->overflow_rtc
	83	<< (BITS_PER_LONG - RTC_SHIFT)
	84	\| rtc_alarm >> RTC_SHIFT, &(alrm->time));
	85	if (sirfsoc_rtc_iobrg_readl(
	86	rtcdrv->rtc_base + RTC_STATUS) & SIRFSOC_RTC_AL0E)
	87	alrm->enabled = 1;
e9bc7363 BS	88
e9bc7363 BS	89	spin_unlock_irq(&rtcdrv->lock);
e88b815e XD	90
	91	return 0;
	92	}
	93
	94	static int sirfsoc_rtc_set_alarm(struct device *dev,
	95	struct rtc_wkalrm *alrm)
	96	{
	97	unsigned long rtc_status_reg, rtc_alarm;
	98	struct sirfsoc_rtc_drv *rtcdrv;
b7efdf3b	99	rtcdrv = dev_get_drvdata(dev);
e88b815e XD	100
	101	if (alrm->enabled) {
	102	rtc_tm_to_time(&(alrm->time), &rtc_alarm);
	103
e9bc7363	104	spin_lock_irq(&rtcdrv->lock);
e88b815e XD	105
	106	rtc_status_reg = sirfsoc_rtc_iobrg_readl(
	107	rtcdrv->rtc_base + RTC_STATUS);
	108	if (rtc_status_reg & SIRFSOC_RTC_AL0E) {
	109	/*
	110	* An ongoing alarm in progress - ingore it and not
	111	* to return EBUSY
	112	*/
	113	dev_info(dev, "An old alarm was set, will be replaced by a new one\n");
	114	}
	115
	116	sirfsoc_rtc_iobrg_writel(
	117	rtc_alarm << RTC_SHIFT, rtcdrv->rtc_base + RTC_ALARM0);
	118	rtc_status_reg &= ~0x07; /* mask out the lower status bits */
	119	/*
	120	* This bit RTC_AL sets it as a wake-up source for Sleep Mode
	121	* Writing 1 into this bit will clear it
	122	*/
	123	rtc_status_reg \|= SIRFSOC_RTC_AL0;
	124	/* enable the RTC alarm interrupt */
	125	rtc_status_reg \|= SIRFSOC_RTC_AL0E;
	126	sirfsoc_rtc_iobrg_writel(
	127	rtc_status_reg, rtcdrv->rtc_base + RTC_STATUS);
e9bc7363 BS	128
e9bc7363 BS	129	spin_unlock_irq(&rtcdrv->lock);
e88b815e XD	130	} else {
	131	/*
	132	* if this function was called with enabled=0
	133	* then it could mean that the application is
	134	* trying to cancel an ongoing alarm
	135	*/
e9bc7363	136	spin_lock_irq(&rtcdrv->lock);
e88b815e XD	137
	138	rtc_status_reg = sirfsoc_rtc_iobrg_readl(
	139	rtcdrv->rtc_base + RTC_STATUS);
	140	if (rtc_status_reg & SIRFSOC_RTC_AL0E) {
	141	/* clear the RTC status register's alarm bit */
	142	rtc_status_reg &= ~0x07;
	143	/* write 1 into SIRFSOC_RTC_AL0 to force a clear */
	144	rtc_status_reg \|= (SIRFSOC_RTC_AL0);
	145	/* Clear the Alarm enable bit */
	146	rtc_status_reg &= ~(SIRFSOC_RTC_AL0E);
	147
	148	sirfsoc_rtc_iobrg_writel(rtc_status_reg,
	149	rtcdrv->rtc_base + RTC_STATUS);
	150	}
	151
e9bc7363	152	spin_unlock_irq(&rtcdrv->lock);
e88b815e XD	153	}
	154
	155	return 0;
	156	}
	157
	158	static int sirfsoc_rtc_read_time(struct device *dev,
	159	struct rtc_time *tm)
	160	{
	161	unsigned long tmp_rtc = 0;
	162	struct sirfsoc_rtc_drv *rtcdrv;
b7efdf3b	163	rtcdrv = dev_get_drvdata(dev);
e88b815e XD	164	/*
	165	* This patch is taken from WinCE - Need to validate this for
	166	* correctness. To work around sirfsoc RTC counter double sync logic
	167	* fail, read several times to make sure get stable value.
	168	*/
	169	do {
	170	tmp_rtc = sirfsoc_rtc_iobrg_readl(rtcdrv->rtc_base + RTC_CN);
	171	cpu_relax();
	172	} while (tmp_rtc != sirfsoc_rtc_iobrg_readl(rtcdrv->rtc_base + RTC_CN));
	173
	174	rtc_time_to_tm(rtcdrv->overflow_rtc << (BITS_PER_LONG - RTC_SHIFT) \|
	175	tmp_rtc >> RTC_SHIFT, tm);
	176	return 0;
	177	}
	178
	179	static int sirfsoc_rtc_set_time(struct device *dev,
	180	struct rtc_time *tm)
	181	{
	182	unsigned long rtc_time;
	183	struct sirfsoc_rtc_drv *rtcdrv;
b7efdf3b	184	rtcdrv = dev_get_drvdata(dev);
e88b815e XD	185
	186	rtc_tm_to_time(tm, &rtc_time);
	187
	188	rtcdrv->overflow_rtc = rtc_time >> (BITS_PER_LONG - RTC_SHIFT);
	189
	190	sirfsoc_rtc_iobrg_writel(rtcdrv->overflow_rtc,
	191	rtcdrv->rtc_base + RTC_SW_VALUE);
	192	sirfsoc_rtc_iobrg_writel(
	193	rtc_time << RTC_SHIFT, rtcdrv->rtc_base + RTC_CN);
	194
	195	return 0;
	196	}
	197
	198	static int sirfsoc_rtc_ioctl(struct device *dev, unsigned int cmd,
	199	unsigned long arg)
	200	{
	201	switch (cmd) {
	202	case RTC_PIE_ON:
	203	case RTC_PIE_OFF:
	204	case RTC_UIE_ON:
	205	case RTC_UIE_OFF:
	206	case RTC_AIE_ON:
	207	case RTC_AIE_OFF:
	208	return 0;
	209
	210	default:
	211	return -ENOIOCTLCMD;
	212	}
	213	}
	214
09e427f8	215	static int sirfsoc_rtc_alarm_irq_enable(struct device *dev,
	216	unsigned int enabled)
	217	{
	218	unsigned long rtc_status_reg = 0x0;
	219	struct sirfsoc_rtc_drv *rtcdrv;
	220
	221	rtcdrv = dev_get_drvdata(dev);
	222
e9bc7363	223	spin_lock_irq(&rtcdrv->lock);
09e427f8	224
	225	rtc_status_reg = sirfsoc_rtc_iobrg_readl(
	226	rtcdrv->rtc_base + RTC_STATUS);
	227	if (enabled)
	228	rtc_status_reg \|= SIRFSOC_RTC_AL0E;
	229	else
	230	rtc_status_reg &= ~SIRFSOC_RTC_AL0E;
	231
	232	sirfsoc_rtc_iobrg_writel(rtc_status_reg, rtcdrv->rtc_base + RTC_STATUS);
e9bc7363 BS	233
e9bc7363 BS	234	spin_unlock_irq(&rtcdrv->lock);
09e427f8	235
	236	return 0;
	237
	238	}
	239
e88b815e XD	240	static const struct rtc_class_ops sirfsoc_rtc_ops = {
	241	.read_time = sirfsoc_rtc_read_time,
	242	.set_time = sirfsoc_rtc_set_time,
	243	.read_alarm = sirfsoc_rtc_read_alarm,
	244	.set_alarm = sirfsoc_rtc_set_alarm,
09e427f8	245	.ioctl = sirfsoc_rtc_ioctl,
09e427f8	246	.alarm_irq_enable = sirfsoc_rtc_alarm_irq_enable
e88b815e XD	247	};
	248
	249	static irqreturn_t sirfsoc_rtc_irq_handler(int irq, void *pdata)
	250	{
	251	struct sirfsoc_rtc_drv *rtcdrv = pdata;
	252	unsigned long rtc_status_reg = 0x0;
	253	unsigned long events = 0x0;
	254
e9bc7363 BS	255	spin_lock(&rtcdrv->lock);
e9bc7363 BS	256
e88b815e XD	257	rtc_status_reg = sirfsoc_rtc_iobrg_readl(rtcdrv->rtc_base + RTC_STATUS);
	258	/* this bit will be set ONLY if an alarm was active
	259	* and it expired NOW
	260	* So this is being used as an ASSERT
	261	*/
	262	if (rtc_status_reg & SIRFSOC_RTC_AL0) {
	263	/*
	264	* clear the RTC status register's alarm bit
	265	* mask out the lower status bits
	266	*/
	267	rtc_status_reg &= ~0x07;
	268	/* write 1 into SIRFSOC_RTC_AL0 to ACK the alarm interrupt */
	269	rtc_status_reg \|= (SIRFSOC_RTC_AL0);
	270	/* Clear the Alarm enable bit */
	271	rtc_status_reg &= ~(SIRFSOC_RTC_AL0E);
	272	}
	273	sirfsoc_rtc_iobrg_writel(rtc_status_reg, rtcdrv->rtc_base + RTC_STATUS);
e9bc7363 BS	274
	275	spin_unlock(&rtcdrv->lock);
	276
e88b815e XD	277	/* this should wake up any apps polling/waiting on the read
	278	* after setting the alarm
	279	*/
	280	events \|= RTC_IRQF \| RTC_AF;
	281	rtc_update_irq(rtcdrv->rtc, 1, events);
	282
	283	return IRQ_HANDLED;
	284	}
	285
	286	static const struct of_device_id sirfsoc_rtc_of_match[] = {
	287	{ .compatible = "sirf,prima2-sysrtc"},
	288	{},
	289	};
	290	MODULE_DEVICE_TABLE(of, sirfsoc_rtc_of_match);
	291
	292	static int sirfsoc_rtc_probe(struct platform_device *pdev)
	293	{
	294	int err;
	295	unsigned long rtc_div;
	296	struct sirfsoc_rtc_drv *rtcdrv;
	297	struct device_node *np = pdev->dev.of_node;
	298
	299	rtcdrv = devm_kzalloc(&pdev->dev,
	300	sizeof(struct sirfsoc_rtc_drv), GFP_KERNEL);
98e2d21f	301	if (rtcdrv == NULL)
e88b815e	302	return -ENOMEM;
e88b815e	303
e9bc7363 BS	304	spin_lock_init(&rtcdrv->lock);
e9bc7363 BS	305
e88b815e XD	306	err = of_property_read_u32(np, "reg", &rtcdrv->rtc_base);
	307	if (err) {
	308	dev_err(&pdev->dev, "unable to find base address of rtc node in dtb\n");
3d09162e	309	return err;
e88b815e XD	310	}
	311
	312	platform_set_drvdata(pdev, rtcdrv);
	313
	314	/* Register rtc alarm as a wakeup source */
	315	device_init_wakeup(&pdev->dev, 1);
	316
	317	/*
	318	* Set SYS_RTC counter in RTC_HZ HZ Units
	319	* We are using 32K RTC crystal (32768 / RTC_HZ / 2) -1
	320	* If 16HZ, therefore RTC_DIV = 1023;
	321	*/
	322	rtc_div = ((32768 / RTC_HZ) / 2) - 1;
	323	sirfsoc_rtc_iobrg_writel(rtc_div, rtcdrv->rtc_base + RTC_DIV);
	324
e88b815e XD	325	/* 0x3 -> RTC_CLK */
	326	sirfsoc_rtc_iobrg_writel(SIRFSOC_RTC_CLK,
	327	rtcdrv->rtc_base + RTC_CLOCK_SWITCH);
	328
	329	/* reset SYS RTC ALARM0 */
	330	sirfsoc_rtc_iobrg_writel(0x0, rtcdrv->rtc_base + RTC_ALARM0);
	331
	332	/* reset SYS RTC ALARM1 */
	333	sirfsoc_rtc_iobrg_writel(0x0, rtcdrv->rtc_base + RTC_ALARM1);
	334
	335	/* Restore RTC Overflow From Register After Command Reboot */
	336	rtcdrv->overflow_rtc =
	337	sirfsoc_rtc_iobrg_readl(rtcdrv->rtc_base + RTC_SW_VALUE);
	338
0e953255 GZ	339	rtcdrv->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
	340	&sirfsoc_rtc_ops, THIS_MODULE);
	341	if (IS_ERR(rtcdrv->rtc)) {
	342	err = PTR_ERR(rtcdrv->rtc);
	343	dev_err(&pdev->dev, "can't register RTC device\n");
	344	return err;
	345	}
	346
e88b815e XD	347	rtcdrv->irq = platform_get_irq(pdev, 0);
	348	err = devm_request_irq(
	349	&pdev->dev,
	350	rtcdrv->irq,
	351	sirfsoc_rtc_irq_handler,
	352	IRQF_SHARED,
	353	pdev->name,
	354	rtcdrv);
	355	if (err) {
	356	dev_err(&pdev->dev, "Unable to register for the SiRF SOC RTC IRQ\n");
3d09162e	357	return err;
e88b815e XD	358	}
	359
	360	return 0;
e88b815e XD	361	}
	362
	363	static int sirfsoc_rtc_remove(struct platform_device *pdev)
	364	{
e88b815e	365	device_init_wakeup(&pdev->dev, 0);
e88b815e XD	366
	367	return 0;
	368	}
	369
3916b09e	370	#ifdef CONFIG_PM_SLEEP
e88b815e XD	371	static int sirfsoc_rtc_suspend(struct device *dev)
e88b815e XD	372	{
3916b09e	373	struct sirfsoc_rtc_drv *rtcdrv = dev_get_drvdata(dev);
e88b815e XD	374	rtcdrv->overflow_rtc =
	375	sirfsoc_rtc_iobrg_readl(rtcdrv->rtc_base + RTC_SW_VALUE);
	376
	377	rtcdrv->saved_counter =
	378	sirfsoc_rtc_iobrg_readl(rtcdrv->rtc_base + RTC_CN);
	379	rtcdrv->saved_overflow_rtc = rtcdrv->overflow_rtc;
3916b09e	380	if (device_may_wakeup(dev) && !enable_irq_wake(rtcdrv->irq))
28984c7d	381	rtcdrv->irq_wake = 1;
e88b815e XD	382
	383	return 0;
	384	}
	385
3916b09e	386	static int sirfsoc_rtc_resume(struct device *dev)
e88b815e XD	387	{
e88b815e XD	388	u32 tmp;
3916b09e	389	struct sirfsoc_rtc_drv *rtcdrv = dev_get_drvdata(dev);
e88b815e XD	390
e88b815e XD	391	/*
3916b09e	392	* if resume from snapshot and the rtc power is lost,
e88b815e XD	393	* restroe the rtc settings
	394	*/
	395	if (SIRFSOC_RTC_CLK != sirfsoc_rtc_iobrg_readl(
	396	rtcdrv->rtc_base + RTC_CLOCK_SWITCH)) {
	397	u32 rtc_div;
	398	/* 0x3 -> RTC_CLK */
	399	sirfsoc_rtc_iobrg_writel(SIRFSOC_RTC_CLK,
	400	rtcdrv->rtc_base + RTC_CLOCK_SWITCH);
	401	/*
	402	* Set SYS_RTC counter in RTC_HZ HZ Units
	403	* We are using 32K RTC crystal (32768 / RTC_HZ / 2) -1
	404	* If 16HZ, therefore RTC_DIV = 1023;
	405	*/
	406	rtc_div = ((32768 / RTC_HZ) / 2) - 1;
	407
	408	sirfsoc_rtc_iobrg_writel(rtc_div, rtcdrv->rtc_base + RTC_DIV);
	409
	410	/* reset SYS RTC ALARM0 */
	411	sirfsoc_rtc_iobrg_writel(0x0, rtcdrv->rtc_base + RTC_ALARM0);
	412
	413	/* reset SYS RTC ALARM1 */
	414	sirfsoc_rtc_iobrg_writel(0x0, rtcdrv->rtc_base + RTC_ALARM1);
	415	}
	416	rtcdrv->overflow_rtc = rtcdrv->saved_overflow_rtc;
	417
	418	/*
	419	* if current counter is small than previous,
	420	* it means overflow in sleep
	421	*/
	422	tmp = sirfsoc_rtc_iobrg_readl(rtcdrv->rtc_base + RTC_CN);
	423	if (tmp <= rtcdrv->saved_counter)
	424	rtcdrv->overflow_rtc++;
	425	/*
	426	*PWRC Value Be Changed When Suspend, Restore Overflow
	427	* In Memory To Register
	428	*/
	429	sirfsoc_rtc_iobrg_writel(rtcdrv->overflow_rtc,
	430	rtcdrv->rtc_base + RTC_SW_VALUE);
	431
3916b09e	432	if (device_may_wakeup(dev) && rtcdrv->irq_wake) {
e88b815e	433	disable_irq_wake(rtcdrv->irq);
28984c7d XD	434	rtcdrv->irq_wake = 0;
28984c7d XD	435	}
e88b815e XD	436
	437	return 0;
	438	}
e88b815e XD	439	#endif
e88b815e XD	440
3916b09e XD	441	static SIMPLE_DEV_PM_OPS(sirfsoc_rtc_pm_ops,
3916b09e XD	442	sirfsoc_rtc_suspend, sirfsoc_rtc_resume);
e88b815e XD	443
	444	static struct platform_driver sirfsoc_rtc_driver = {
	445	.driver = {
	446	.name = "sirfsoc-rtc",
e88b815e	447	.pm = &sirfsoc_rtc_pm_ops,
d149632e	448	.of_match_table = sirfsoc_rtc_of_match,
e88b815e XD	449	},
	450	.probe = sirfsoc_rtc_probe,
	451	.remove = sirfsoc_rtc_remove,
	452	};
	453	module_platform_driver(sirfsoc_rtc_driver);
	454
	455	MODULE_DESCRIPTION("SiRF SoC rtc driver");
	456	MODULE_AUTHOR("Xianglong Du <Xianglong.Du@csr.com>");
	457	MODULE_LICENSE("GPL v2");
	458	MODULE_ALIAS("platform:sirfsoc-rtc");