[deliverable/linux.git] / drivers / rtc / rtc-vr41xx.c

/*
 *  Driver for NEC VR4100 series Real Time Clock unit.
 *
 *  Copyright (C) 2003-2008  Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, write to the Free Software
 *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include <linux/err.h>
#include <linux/fs.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/rtc.h>
#include <linux/spinlock.h>
#include <linux/types.h>

#include <asm/div64.h>
#include <asm/io.h>
#include <asm/uaccess.h>

MODULE_AUTHOR("Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>");
MODULE_DESCRIPTION("NEC VR4100 series RTC driver");
MODULE_LICENSE("GPL v2");

/* RTC 1 registers */
#define ETIMELREG		0x00
#define ETIMEMREG		0x02
#define ETIMEHREG		0x04
/* RFU */
#define ECMPLREG		0x08
#define ECMPMREG		0x0a
#define ECMPHREG		0x0c
/* RFU */
#define RTCL1LREG		0x10
#define RTCL1HREG		0x12
#define RTCL1CNTLREG		0x14
#define RTCL1CNTHREG		0x16
#define RTCL2LREG		0x18
#define RTCL2HREG		0x1a
#define RTCL2CNTLREG		0x1c
#define RTCL2CNTHREG		0x1e

/* RTC 2 registers */
#define TCLKLREG		0x00
#define TCLKHREG		0x02
#define TCLKCNTLREG		0x04
#define TCLKCNTHREG		0x06
/* RFU */
#define RTCINTREG		0x1e
 #define TCLOCK_INT		0x08
 #define RTCLONG2_INT		0x04
 #define RTCLONG1_INT		0x02
 #define ELAPSEDTIME_INT	0x01

#define RTC_FREQUENCY		32768
#define MAX_PERIODIC_RATE	6553

static void __iomem *rtc1_base;
static void __iomem *rtc2_base;

#define rtc1_read(offset)		readw(rtc1_base + (offset))
#define rtc1_write(offset, value)	writew((value), rtc1_base + (offset))

#define rtc2_read(offset)		readw(rtc2_base + (offset))
#define rtc2_write(offset, value)	writew((value), rtc2_base + (offset))

static unsigned long epoch = 1970;	/* Jan 1 1970 00:00:00 */

static DEFINE_SPINLOCK(rtc_lock);
static char rtc_name[] = "RTC";
static unsigned long periodic_count;
static unsigned int alarm_enabled;
static int aie_irq = -1;
static int pie_irq = -1;

static inline unsigned long read_elapsed_second(void)
{

	unsigned long first_low, first_mid, first_high;

	unsigned long second_low, second_mid, second_high;

	do {
		first_low = rtc1_read(ETIMELREG);
		first_mid = rtc1_read(ETIMEMREG);
		first_high = rtc1_read(ETIMEHREG);
		second_low = rtc1_read(ETIMELREG);
		second_mid = rtc1_read(ETIMEMREG);
		second_high = rtc1_read(ETIMEHREG);
	} while (first_low != second_low || first_mid != second_mid ||
	         first_high != second_high);

	return (first_high << 17) | (first_mid << 1) | (first_low >> 15);
}

static inline void write_elapsed_second(unsigned long sec)
{
	spin_lock_irq(&rtc_lock);

	rtc1_write(ETIMELREG, (uint16_t)(sec << 15));
	rtc1_write(ETIMEMREG, (uint16_t)(sec >> 1));
	rtc1_write(ETIMEHREG, (uint16_t)(sec >> 17));

	spin_unlock_irq(&rtc_lock);
}

static void vr41xx_rtc_release(struct device *dev)
{

	spin_lock_irq(&rtc_lock);

	rtc1_write(ECMPLREG, 0);
	rtc1_write(ECMPMREG, 0);
	rtc1_write(ECMPHREG, 0);
	rtc1_write(RTCL1LREG, 0);
	rtc1_write(RTCL1HREG, 0);

	spin_unlock_irq(&rtc_lock);

	disable_irq(aie_irq);
	disable_irq(pie_irq);
}

static int vr41xx_rtc_read_time(struct device *dev, struct rtc_time *time)
{
	unsigned long epoch_sec, elapsed_sec;

	epoch_sec = mktime(epoch, 1, 1, 0, 0, 0);
	elapsed_sec = read_elapsed_second();

	rtc_time_to_tm(epoch_sec + elapsed_sec, time);

	return 0;
}

static int vr41xx_rtc_set_time(struct device *dev, struct rtc_time *time)
{
	unsigned long epoch_sec, current_sec;

	epoch_sec = mktime(epoch, 1, 1, 0, 0, 0);
	current_sec = mktime(time->tm_year + 1900, time->tm_mon + 1, time->tm_mday,
	                     time->tm_hour, time->tm_min, time->tm_sec);

	write_elapsed_second(current_sec - epoch_sec);

	return 0;
}

static int vr41xx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
{
	unsigned long low, mid, high;
	struct rtc_time *time = &wkalrm->time;

	spin_lock_irq(&rtc_lock);

	low = rtc1_read(ECMPLREG);
	mid = rtc1_read(ECMPMREG);
	high = rtc1_read(ECMPHREG);
	wkalrm->enabled = alarm_enabled;

	spin_unlock_irq(&rtc_lock);

	rtc_time_to_tm((high << 17) | (mid << 1) | (low >> 15), time);

	return 0;
}

static int vr41xx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
{
	unsigned long alarm_sec;
	struct rtc_time *time = &wkalrm->time;

	alarm_sec = mktime(time->tm_year + 1900, time->tm_mon + 1, time->tm_mday,
	                   time->tm_hour, time->tm_min, time->tm_sec);

	spin_lock_irq(&rtc_lock);

	if (alarm_enabled)
		disable_irq(aie_irq);

	rtc1_write(ECMPLREG, (uint16_t)(alarm_sec << 15));
	rtc1_write(ECMPMREG, (uint16_t)(alarm_sec >> 1));
	rtc1_write(ECMPHREG, (uint16_t)(alarm_sec >> 17));

	if (wkalrm->enabled)
		enable_irq(aie_irq);

	alarm_enabled = wkalrm->enabled;

	spin_unlock_irq(&rtc_lock);

	return 0;
}

static int vr41xx_rtc_irq_set_freq(struct device *dev, int freq)
{
	unsigned long count;

	count = RTC_FREQUENCY;
	do_div(count, freq);

	periodic_count = count;

	spin_lock_irq(&rtc_lock);

	rtc1_write(RTCL1LREG, count);
	rtc1_write(RTCL1HREG, count >> 16);

	spin_unlock_irq(&rtc_lock);

	return 0;
}

static int vr41xx_rtc_irq_set_state(struct device *dev, int enabled)
{
	if (enabled)
		enable_irq(pie_irq);
	else
		disable_irq(pie_irq);

	return 0;
}

static int vr41xx_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
{
	switch (cmd) {
	case RTC_AIE_ON:
		spin_lock_irq(&rtc_lock);

		if (!alarm_enabled) {
			enable_irq(aie_irq);
			alarm_enabled = 1;
		}

		spin_unlock_irq(&rtc_lock);
		break;
	case RTC_AIE_OFF:
		spin_lock_irq(&rtc_lock);

		if (alarm_enabled) {
			disable_irq(aie_irq);
			alarm_enabled = 0;
		}

		spin_unlock_irq(&rtc_lock);
		break;
	case RTC_EPOCH_READ:
		return put_user(epoch, (unsigned long __user *)arg);
	case RTC_EPOCH_SET:
		/* Doesn't support before 1900 */
		if (arg < 1900)
			return -EINVAL;
		epoch = arg;
		break;
	default:
		return -ENOIOCTLCMD;
	}

	return 0;
}

static irqreturn_t elapsedtime_interrupt(int irq, void *dev_id)
{
	struct platform_device *pdev = (struct platform_device *)dev_id;
	struct rtc_device *rtc = platform_get_drvdata(pdev);

	rtc2_write(RTCINTREG, ELAPSEDTIME_INT);

	rtc_update_irq(rtc, 1, RTC_AF);

	return IRQ_HANDLED;
}

static irqreturn_t rtclong1_interrupt(int irq, void *dev_id)
{
	struct platform_device *pdev = (struct platform_device *)dev_id;
	struct rtc_device *rtc = platform_get_drvdata(pdev);
	unsigned long count = periodic_count;

	rtc2_write(RTCINTREG, RTCLONG1_INT);

	rtc1_write(RTCL1LREG, count);
	rtc1_write(RTCL1HREG, count >> 16);

	rtc_update_irq(rtc, 1, RTC_PF);

	return IRQ_HANDLED;
}

static const struct rtc_class_ops vr41xx_rtc_ops = {
	.release	= vr41xx_rtc_release,
	.ioctl		= vr41xx_rtc_ioctl,
	.read_time	= vr41xx_rtc_read_time,
	.set_time	= vr41xx_rtc_set_time,
	.read_alarm	= vr41xx_rtc_read_alarm,
	.set_alarm	= vr41xx_rtc_set_alarm,
	.irq_set_freq	= vr41xx_rtc_irq_set_freq,
	.irq_set_state	= vr41xx_rtc_irq_set_state,
};

static int __devinit rtc_probe(struct platform_device *pdev)
{
	struct resource *res;
	struct rtc_device *rtc;
	int retval;

	if (pdev->num_resources != 4)
		return -EBUSY;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res)
		return -EBUSY;

	rtc1_base = ioremap(res->start, res->end - res->start + 1);
	if (!rtc1_base)
		return -EBUSY;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	if (!res) {
		retval = -EBUSY;
		goto err_rtc1_iounmap;
	}

	rtc2_base = ioremap(res->start, res->end - res->start + 1);
	if (!rtc2_base) {
		retval = -EBUSY;
		goto err_rtc1_iounmap;
	}

	rtc = rtc_device_register(rtc_name, &pdev->dev, &vr41xx_rtc_ops, THIS_MODULE);
	if (IS_ERR(rtc)) {
		retval = PTR_ERR(rtc);
		goto err_iounmap_all;
	}

	rtc->max_user_freq = MAX_PERIODIC_RATE;

	spin_lock_irq(&rtc_lock);

	rtc1_write(ECMPLREG, 0);
	rtc1_write(ECMPMREG, 0);
	rtc1_write(ECMPHREG, 0);
	rtc1_write(RTCL1LREG, 0);
	rtc1_write(RTCL1HREG, 0);

	spin_unlock_irq(&rtc_lock);

	aie_irq = platform_get_irq(pdev, 0);
	if (aie_irq < 0 || aie_irq >= nr_irqs) {
		retval = -EBUSY;
		goto err_device_unregister;
	}

	retval = request_irq(aie_irq, elapsedtime_interrupt, IRQF_DISABLED,
	                     "elapsed_time", pdev);
	if (retval < 0)
		goto err_device_unregister;

	pie_irq = platform_get_irq(pdev, 1);
	if (pie_irq < 0 || pie_irq >= nr_irqs)
		goto err_free_irq;

	retval = request_irq(pie_irq, rtclong1_interrupt, IRQF_DISABLED,
		             "rtclong1", pdev);
	if (retval < 0)
		goto err_free_irq;

	platform_set_drvdata(pdev, rtc);

	disable_irq(aie_irq);
	disable_irq(pie_irq);

	printk(KERN_INFO "rtc: Real Time Clock of NEC VR4100 series\n");

	return 0;

err_free_irq:
	free_irq(aie_irq, pdev);

err_device_unregister:
	rtc_device_unregister(rtc);

err_iounmap_all:
	iounmap(rtc2_base);
	rtc2_base = NULL;

err_rtc1_iounmap:
	iounmap(rtc1_base);
	rtc1_base = NULL;

	return retval;
}

static int __devexit rtc_remove(struct platform_device *pdev)
{
	struct rtc_device *rtc;

	rtc = platform_get_drvdata(pdev);
	if (rtc)
		rtc_device_unregister(rtc);

	platform_set_drvdata(pdev, NULL);

	free_irq(aie_irq, pdev);
	free_irq(pie_irq, pdev);
	if (rtc1_base)
		iounmap(rtc1_base);
	if (rtc2_base)
		iounmap(rtc2_base);

	return 0;
}

/* work with hotplug and coldplug */
MODULE_ALIAS("platform:RTC");

static struct platform_driver rtc_platform_driver = {
	.probe		= rtc_probe,
	.remove		= __devexit_p(rtc_remove),
	.driver		= {
		.name	= rtc_name,
		.owner	= THIS_MODULE,
	},
};

static int __init vr41xx_rtc_init(void)
{
	return platform_driver_register(&rtc_platform_driver);
}

static void __exit vr41xx_rtc_exit(void)
{
	platform_driver_unregister(&rtc_platform_driver);
}

module_init(vr41xx_rtc_init);
module_exit(vr41xx_rtc_exit);
Commit	Line	Data
1da177e4	1	/*
8417eb7a	2	* Driver for NEC VR4100 series Real Time Clock unit.
1da177e4	3	*
4cad4431	4	* Copyright (C) 2003-2008 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
1da177e4 LT	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
bd076509	20	#include <linux/err.h>
1da177e4 LT	21	#include <linux/fs.h>
	22	#include <linux/init.h>
	23	#include <linux/ioport.h>
bd076509	24	#include <linux/interrupt.h>
1da177e4	25	#include <linux/module.h>
8417eb7a	26	#include <linux/platform_device.h>
1da177e4 LT	27	#include <linux/rtc.h>
	28	#include <linux/spinlock.h>
	29	#include <linux/types.h>
1da177e4 LT	30
	31	#include <asm/div64.h>
	32	#include <asm/io.h>
1da177e4	33	#include <asm/uaccess.h>
1da177e4	34
29ce2c76	35	MODULE_AUTHOR("Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>");
1da177e4	36	MODULE_DESCRIPTION("NEC VR4100 series RTC driver");
4cad4431	37	MODULE_LICENSE("GPL v2");
1da177e4	38
1da177e4 LT	39	/* RTC 1 registers */
	40	#define ETIMELREG 0x00
	41	#define ETIMEMREG 0x02
	42	#define ETIMEHREG 0x04
	43	/* RFU */
	44	#define ECMPLREG 0x08
	45	#define ECMPMREG 0x0a
	46	#define ECMPHREG 0x0c
	47	/* RFU */
	48	#define RTCL1LREG 0x10
	49	#define RTCL1HREG 0x12
	50	#define RTCL1CNTLREG 0x14
	51	#define RTCL1CNTHREG 0x16
	52	#define RTCL2LREG 0x18
	53	#define RTCL2HREG 0x1a
	54	#define RTCL2CNTLREG 0x1c
	55	#define RTCL2CNTHREG 0x1e
	56
	57	/* RTC 2 registers */
	58	#define TCLKLREG 0x00
	59	#define TCLKHREG 0x02
	60	#define TCLKCNTLREG 0x04
	61	#define TCLKCNTHREG 0x06
	62	/* RFU */
	63	#define RTCINTREG 0x1e
	64	#define TCLOCK_INT 0x08
	65	#define RTCLONG2_INT 0x04
	66	#define RTCLONG1_INT 0x02
	67	#define ELAPSEDTIME_INT 0x01
	68
	69	#define RTC_FREQUENCY 32768
	70	#define MAX_PERIODIC_RATE 6553
1da177e4 LT	71
	72	static void __iomem *rtc1_base;
	73	static void __iomem *rtc2_base;
	74
	75	#define rtc1_read(offset) readw(rtc1_base + (offset))
	76	#define rtc1_write(offset, value) writew((value), rtc1_base + (offset))
	77
	78	#define rtc2_read(offset) readw(rtc2_base + (offset))
	79	#define rtc2_write(offset, value) writew((value), rtc2_base + (offset))
	80
	81	static unsigned long epoch = 1970; /* Jan 1 1970 00:00:00 */
	82
34af946a	83	static DEFINE_SPINLOCK(rtc_lock);
1da177e4	84	static char rtc_name[] = "RTC";
1da177e4	85	static unsigned long periodic_count;
9b5ef64a	86	static unsigned int alarm_enabled;
bd076509 YY	87	static int aie_irq = -1;
bd076509 YY	88	static int pie_irq = -1;
1da177e4	89
1da177e4 LT	90	static inline unsigned long read_elapsed_second(void)
1da177e4 LT	91	{
8417eb7a	92
1da177e4	93	unsigned long first_low, first_mid, first_high;
8417eb7a	94
1da177e4 LT	95	unsigned long second_low, second_mid, second_high;
	96
	97	do {
	98	first_low = rtc1_read(ETIMELREG);
	99	first_mid = rtc1_read(ETIMEMREG);
	100	first_high = rtc1_read(ETIMEHREG);
	101	second_low = rtc1_read(ETIMELREG);
	102	second_mid = rtc1_read(ETIMEMREG);
	103	second_high = rtc1_read(ETIMEHREG);
	104	} while (first_low != second_low \|\| first_mid != second_mid \|\|
	105	first_high != second_high);
	106
	107	return (first_high << 17) \| (first_mid << 1) \| (first_low >> 15);
	108	}
	109
	110	static inline void write_elapsed_second(unsigned long sec)
	111	{
	112	spin_lock_irq(&rtc_lock);
	113
	114	rtc1_write(ETIMELREG, (uint16_t)(sec << 15));
	115	rtc1_write(ETIMEMREG, (uint16_t)(sec >> 1));
	116	rtc1_write(ETIMEHREG, (uint16_t)(sec >> 17));
	117
	118	spin_unlock_irq(&rtc_lock);
	119	}
	120
8417eb7a	121	static void vr41xx_rtc_release(struct device *dev)
1da177e4	122	{
1da177e4 LT	123
	124	spin_lock_irq(&rtc_lock);
	125
8417eb7a YY	126	rtc1_write(ECMPLREG, 0);
	127	rtc1_write(ECMPMREG, 0);
	128	rtc1_write(ECMPHREG, 0);
	129	rtc1_write(RTCL1LREG, 0);
	130	rtc1_write(RTCL1HREG, 0);
1da177e4 LT	131
	132	spin_unlock_irq(&rtc_lock);
	133
bd076509 YY	134	disable_irq(aie_irq);
bd076509 YY	135	disable_irq(pie_irq);
1da177e4 LT	136	}
1da177e4 LT	137
8417eb7a	138	static int vr41xx_rtc_read_time(struct device dev, struct rtc_time time)
1da177e4 LT	139	{
	140	unsigned long epoch_sec, elapsed_sec;
	141
	142	epoch_sec = mktime(epoch, 1, 1, 0, 0, 0);
	143	elapsed_sec = read_elapsed_second();
	144
8417eb7a YY	145	rtc_time_to_tm(epoch_sec + elapsed_sec, time);
	146
	147	return 0;
1da177e4 LT	148	}
1da177e4 LT	149
8417eb7a	150	static int vr41xx_rtc_set_time(struct device dev, struct rtc_time time)
1da177e4 LT	151	{
	152	unsigned long epoch_sec, current_sec;
	153
	154	epoch_sec = mktime(epoch, 1, 1, 0, 0, 0);
	155	current_sec = mktime(time->tm_year + 1900, time->tm_mon + 1, time->tm_mday,
	156	time->tm_hour, time->tm_min, time->tm_sec);
	157
	158	write_elapsed_second(current_sec - epoch_sec);
8417eb7a YY	159
8417eb7a YY	160	return 0;
1da177e4 LT	161	}
1da177e4 LT	162
8417eb7a	163	static int vr41xx_rtc_read_alarm(struct device dev, struct rtc_wkalrm wkalrm)
1da177e4	164	{
8417eb7a YY	165	unsigned long low, mid, high;
8417eb7a YY	166	struct rtc_time *time = &wkalrm->time;
1da177e4	167
8417eb7a	168	spin_lock_irq(&rtc_lock);
1da177e4	169
8417eb7a YY	170	low = rtc1_read(ECMPLREG);
	171	mid = rtc1_read(ECMPMREG);
	172	high = rtc1_read(ECMPHREG);
9b5ef64a	173	wkalrm->enabled = alarm_enabled;
1da177e4	174
8417eb7a	175	spin_unlock_irq(&rtc_lock);
1da177e4	176
8417eb7a	177	rtc_time_to_tm((high << 17) \| (mid << 1) \| (low >> 15), time);
1da177e4	178
8417eb7a YY	179	return 0;
8417eb7a YY	180	}
1da177e4	181
8417eb7a YY	182	static int vr41xx_rtc_set_alarm(struct device dev, struct rtc_wkalrm wkalrm)
	183	{
	184	unsigned long alarm_sec;
	185	struct rtc_time *time = &wkalrm->time;
1da177e4	186
8417eb7a YY	187	alarm_sec = mktime(time->tm_year + 1900, time->tm_mon + 1, time->tm_mday,
8417eb7a YY	188	time->tm_hour, time->tm_min, time->tm_sec);
1da177e4	189
8417eb7a	190	spin_lock_irq(&rtc_lock);
1da177e4	191
9b5ef64a	192	if (alarm_enabled)
bd076509	193	disable_irq(aie_irq);
9b5ef64a	194
8417eb7a YY	195	rtc1_write(ECMPLREG, (uint16_t)(alarm_sec << 15));
	196	rtc1_write(ECMPMREG, (uint16_t)(alarm_sec >> 1));
	197	rtc1_write(ECMPHREG, (uint16_t)(alarm_sec >> 17));
1da177e4	198
9b5ef64a	199	if (wkalrm->enabled)
bd076509	200	enable_irq(aie_irq);
9b5ef64a YY	201
	202	alarm_enabled = wkalrm->enabled;
	203
8417eb7a	204	spin_unlock_irq(&rtc_lock);
1da177e4 LT	205
	206	return 0;
	207	}
	208
4cad4431	209	static int vr41xx_rtc_irq_set_freq(struct device *dev, int freq)
1da177e4	210	{
1da177e4 LT	211	unsigned long count;
1da177e4 LT	212
4cad4431 YY	213	count = RTC_FREQUENCY;
	214	do_div(count, freq);
	215
	216	periodic_count = count;
	217
	218	spin_lock_irq(&rtc_lock);
	219
	220	rtc1_write(RTCL1LREG, count);
	221	rtc1_write(RTCL1HREG, count >> 16);
	222
	223	spin_unlock_irq(&rtc_lock);
	224
	225	return 0;
	226	}
	227
	228	static int vr41xx_rtc_irq_set_state(struct device *dev, int enabled)
	229	{
	230	if (enabled)
	231	enable_irq(pie_irq);
	232	else
	233	disable_irq(pie_irq);
	234
	235	return 0;
	236	}
	237
	238	static int vr41xx_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
	239	{
1da177e4 LT	240	switch (cmd) {
1da177e4 LT	241	case RTC_AIE_ON:
9b5ef64a YY	242	spin_lock_irq(&rtc_lock);
	243
	244	if (!alarm_enabled) {
bd076509	245	enable_irq(aie_irq);
9b5ef64a YY	246	alarm_enabled = 1;
	247	}
	248
	249	spin_unlock_irq(&rtc_lock);
1da177e4 LT	250	break;
1da177e4 LT	251	case RTC_AIE_OFF:
9b5ef64a YY	252	spin_lock_irq(&rtc_lock);
	253
	254	if (alarm_enabled) {
bd076509	255	disable_irq(aie_irq);
9b5ef64a YY	256	alarm_enabled = 0;
	257	}
	258
1da177e4 LT	259	spin_unlock_irq(&rtc_lock);
	260	break;
	261	case RTC_EPOCH_READ:
	262	return put_user(epoch, (unsigned long __user *)arg);
	263	case RTC_EPOCH_SET:
	264	/* Doesn't support before 1900 */
	265	if (arg < 1900)
	266	return -EINVAL;
1da177e4 LT	267	epoch = arg;
	268	break;
	269	default:
b3969e58	270	return -ENOIOCTLCMD;
1da177e4 LT	271	}
	272
	273	return 0;
	274	}
	275
7d12e780	276	static irqreturn_t elapsedtime_interrupt(int irq, void *dev_id)
1da177e4	277	{
8417eb7a YY	278	struct platform_device pdev = (struct platform_device )dev_id;
8417eb7a YY	279	struct rtc_device *rtc = platform_get_drvdata(pdev);
1da177e4	280
8417eb7a	281	rtc2_write(RTCINTREG, ELAPSEDTIME_INT);
1da177e4	282
ab6a2d70	283	rtc_update_irq(rtc, 1, RTC_AF);
1da177e4 LT	284
	285	return IRQ_HANDLED;
	286	}
	287
7d12e780	288	static irqreturn_t rtclong1_interrupt(int irq, void *dev_id)
1da177e4	289	{
8417eb7a YY	290	struct platform_device pdev = (struct platform_device )dev_id;
8417eb7a YY	291	struct rtc_device *rtc = platform_get_drvdata(pdev);
1da177e4 LT	292	unsigned long count = periodic_count;
1da177e4 LT	293
1da177e4 LT	294	rtc2_write(RTCINTREG, RTCLONG1_INT);
	295
	296	rtc1_write(RTCL1LREG, count);
	297	rtc1_write(RTCL1HREG, count >> 16);
	298
ab6a2d70	299	rtc_update_irq(rtc, 1, RTC_PF);
1da177e4 LT	300
	301	return IRQ_HANDLED;
	302	}
	303
ff8371ac	304	static const struct rtc_class_ops vr41xx_rtc_ops = {
8417eb7a YY	305	.release = vr41xx_rtc_release,
	306	.ioctl = vr41xx_rtc_ioctl,
	307	.read_time = vr41xx_rtc_read_time,
	308	.set_time = vr41xx_rtc_set_time,
	309	.read_alarm = vr41xx_rtc_read_alarm,
	310	.set_alarm = vr41xx_rtc_set_alarm,
4cad4431 YY	311	.irq_set_freq = vr41xx_rtc_irq_set_freq,
4cad4431 YY	312	.irq_set_state = vr41xx_rtc_irq_set_state,
1da177e4 LT	313	};
1da177e4 LT	314
d39b6cfe	315	static int __devinit rtc_probe(struct platform_device *pdev)
1da177e4	316	{
bd076509	317	struct resource *res;
8417eb7a	318	struct rtc_device *rtc;
1da177e4 LT	319	int retval;
1da177e4 LT	320
bd076509	321	if (pdev->num_resources != 4)
1da177e4 LT	322	return -EBUSY;
1da177e4 LT	323
bd076509 YY	324	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
bd076509 YY	325	if (!res)
1da177e4 LT	326	return -EBUSY;
1da177e4 LT	327
bd076509 YY	328	rtc1_base = ioremap(res->start, res->end - res->start + 1);
bd076509 YY	329	if (!rtc1_base)
1da177e4	330	return -EBUSY;
bd076509 YY	331
	332	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	333	if (!res) {
	334	retval = -EBUSY;
	335	goto err_rtc1_iounmap;
	336	}
	337
	338	rtc2_base = ioremap(res->start, res->end - res->start + 1);
	339	if (!rtc2_base) {
	340	retval = -EBUSY;
	341	goto err_rtc1_iounmap;
1da177e4 LT	342	}
1da177e4 LT	343
8417eb7a YY	344	rtc = rtc_device_register(rtc_name, &pdev->dev, &vr41xx_rtc_ops, THIS_MODULE);
8417eb7a YY	345	if (IS_ERR(rtc)) {
bd076509 YY	346	retval = PTR_ERR(rtc);
bd076509 YY	347	goto err_iounmap_all;
1da177e4 LT	348	}
1da177e4 LT	349
4cad4431 YY	350	rtc->max_user_freq = MAX_PERIODIC_RATE;
4cad4431 YY	351
1da177e4 LT	352	spin_lock_irq(&rtc_lock);
	353
	354	rtc1_write(ECMPLREG, 0);
	355	rtc1_write(ECMPMREG, 0);
	356	rtc1_write(ECMPHREG, 0);
	357	rtc1_write(RTCL1LREG, 0);
	358	rtc1_write(RTCL1HREG, 0);
	359
1da177e4 LT	360	spin_unlock_irq(&rtc_lock);
1da177e4 LT	361
bd076509	362	aie_irq = platform_get_irq(pdev, 0);
c7576b5b	363	if (aie_irq < 0 \|\| aie_irq >= nr_irqs) {
bd076509 YY	364	retval = -EBUSY;
bd076509 YY	365	goto err_device_unregister;
1da177e4 LT	366	}
1da177e4 LT	367
bd076509 YY	368	retval = request_irq(aie_irq, elapsedtime_interrupt, IRQF_DISABLED,
	369	"elapsed_time", pdev);
	370	if (retval < 0)
	371	goto err_device_unregister;
	372
	373	pie_irq = platform_get_irq(pdev, 1);
c7576b5b	374	if (pie_irq < 0 \|\| pie_irq >= nr_irqs)
bd076509 YY	375	goto err_free_irq;
	376
	377	retval = request_irq(pie_irq, rtclong1_interrupt, IRQF_DISABLED,
	378	"rtclong1", pdev);
	379	if (retval < 0)
	380	goto err_free_irq;
1da177e4	381
8417eb7a YY	382	platform_set_drvdata(pdev, rtc);
8417eb7a YY	383
bd076509 YY	384	disable_irq(aie_irq);
bd076509 YY	385	disable_irq(pie_irq);
1da177e4	386
1da177e4 LT	387	printk(KERN_INFO "rtc: Real Time Clock of NEC VR4100 series\n");
	388
	389	return 0;
bd076509 YY	390
	391	err_free_irq:
	392	free_irq(aie_irq, pdev);
	393
	394	err_device_unregister:
	395	rtc_device_unregister(rtc);
	396
	397	err_iounmap_all:
	398	iounmap(rtc2_base);
	399	rtc2_base = NULL;
	400
	401	err_rtc1_iounmap:
	402	iounmap(rtc1_base);
	403	rtc1_base = NULL;
	404
	405	return retval;
1da177e4 LT	406	}
1da177e4 LT	407
8417eb7a	408	static int __devexit rtc_remove(struct platform_device *pdev)
1da177e4	409	{
8417eb7a	410	struct rtc_device *rtc;
1da177e4	411
8417eb7a	412	rtc = platform_get_drvdata(pdev);
bd076509	413	if (rtc)
8417eb7a YY	414	rtc_device_unregister(rtc);
	415
	416	platform_set_drvdata(pdev, NULL);
1da177e4	417
bd076509 YY	418	free_irq(aie_irq, pdev);
	419	free_irq(pie_irq, pdev);
	420	if (rtc1_base)
1da177e4	421	iounmap(rtc1_base);
bd076509	422	if (rtc2_base)
1da177e4 LT	423	iounmap(rtc2_base);
	424
	425	return 0;
	426	}
	427
ad28a07b KS	428	/* work with hotplug and coldplug */
	429	MODULE_ALIAS("platform:RTC");
	430
8417eb7a	431	static struct platform_driver rtc_platform_driver = {
1da177e4	432	.probe = rtc_probe,
d39b6cfe	433	.remove = __devexit_p(rtc_remove),
3ae5eaec RK	434	.driver = {
3ae5eaec RK	435	.name = rtc_name,
d39b6cfe	436	.owner = THIS_MODULE,
3ae5eaec	437	},
1da177e4 LT	438	};
1da177e4 LT	439
d39b6cfe	440	static int __init vr41xx_rtc_init(void)
1da177e4	441	{
bd076509	442	return platform_driver_register(&rtc_platform_driver);
1da177e4 LT	443	}
1da177e4 LT	444
d39b6cfe	445	static void __exit vr41xx_rtc_exit(void)
1da177e4	446	{
8417eb7a	447	platform_driver_unregister(&rtc_platform_driver);
1da177e4 LT	448	}
	449
	450	module_init(vr41xx_rtc_init);
	451	module_exit(vr41xx_rtc_exit);