Commit | Line | Data |
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1fec7c66 AZ |
1 | /* |
2 | * An i2c driver for the Xicor/Intersil X1205 RTC | |
3 | * Copyright 2004 Karen Spearel | |
4 | * Copyright 2005 Alessandro Zummo | |
5 | * | |
6 | * please send all reports to: | |
66e3f10c | 7 | * Karen Spearel <kas111 at gmail dot com> |
1fec7c66 AZ |
8 | * Alessandro Zummo <a.zummo@towertech.it> |
9 | * | |
10 | * based on a lot of other RTC drivers. | |
11 | * | |
890e0375 JD |
12 | * Information and datasheet: |
13 | * http://www.intersil.com/cda/deviceinfo/0,1477,X1205,00.html | |
14 | * | |
1fec7c66 AZ |
15 | * This program is free software; you can redistribute it and/or modify |
16 | * it under the terms of the GNU General Public License version 2 as | |
17 | * published by the Free Software Foundation. | |
18 | */ | |
19 | ||
20 | #include <linux/i2c.h> | |
21 | #include <linux/bcd.h> | |
22 | #include <linux/rtc.h> | |
23 | #include <linux/delay.h> | |
2113852b | 24 | #include <linux/module.h> |
1fec7c66 | 25 | |
4edac2b4 | 26 | #define DRV_VERSION "1.0.8" |
1fec7c66 AZ |
27 | |
28 | /* offsets into CCR area */ | |
29 | ||
30 | #define CCR_SEC 0 | |
31 | #define CCR_MIN 1 | |
32 | #define CCR_HOUR 2 | |
33 | #define CCR_MDAY 3 | |
34 | #define CCR_MONTH 4 | |
35 | #define CCR_YEAR 5 | |
36 | #define CCR_WDAY 6 | |
37 | #define CCR_Y2K 7 | |
38 | ||
39 | #define X1205_REG_SR 0x3F /* status register */ | |
40 | #define X1205_REG_Y2K 0x37 | |
41 | #define X1205_REG_DW 0x36 | |
42 | #define X1205_REG_YR 0x35 | |
43 | #define X1205_REG_MO 0x34 | |
44 | #define X1205_REG_DT 0x33 | |
45 | #define X1205_REG_HR 0x32 | |
46 | #define X1205_REG_MN 0x31 | |
47 | #define X1205_REG_SC 0x30 | |
48 | #define X1205_REG_DTR 0x13 | |
49 | #define X1205_REG_ATR 0x12 | |
50 | #define X1205_REG_INT 0x11 | |
51 | #define X1205_REG_0 0x10 | |
52 | #define X1205_REG_Y2K1 0x0F | |
53 | #define X1205_REG_DWA1 0x0E | |
54 | #define X1205_REG_YRA1 0x0D | |
55 | #define X1205_REG_MOA1 0x0C | |
56 | #define X1205_REG_DTA1 0x0B | |
57 | #define X1205_REG_HRA1 0x0A | |
58 | #define X1205_REG_MNA1 0x09 | |
59 | #define X1205_REG_SCA1 0x08 | |
60 | #define X1205_REG_Y2K0 0x07 | |
61 | #define X1205_REG_DWA0 0x06 | |
62 | #define X1205_REG_YRA0 0x05 | |
63 | #define X1205_REG_MOA0 0x04 | |
64 | #define X1205_REG_DTA0 0x03 | |
65 | #define X1205_REG_HRA0 0x02 | |
66 | #define X1205_REG_MNA0 0x01 | |
67 | #define X1205_REG_SCA0 0x00 | |
68 | ||
69 | #define X1205_CCR_BASE 0x30 /* Base address of CCR */ | |
70 | #define X1205_ALM0_BASE 0x00 /* Base address of ALARM0 */ | |
71 | ||
72 | #define X1205_SR_RTCF 0x01 /* Clock failure */ | |
73 | #define X1205_SR_WEL 0x02 /* Write Enable Latch */ | |
74 | #define X1205_SR_RWEL 0x04 /* Register Write Enable */ | |
471d47e3 | 75 | #define X1205_SR_AL0 0x20 /* Alarm 0 match */ |
1fec7c66 AZ |
76 | |
77 | #define X1205_DTR_DTR0 0x01 | |
78 | #define X1205_DTR_DTR1 0x02 | |
79 | #define X1205_DTR_DTR2 0x04 | |
80 | ||
81 | #define X1205_HR_MIL 0x80 /* Set in ccr.hour for 24 hr mode */ | |
82 | ||
471d47e3 MH |
83 | #define X1205_INT_AL0E 0x20 /* Alarm 0 enable */ |
84 | ||
4edac2b4 | 85 | static struct i2c_driver x1205_driver; |
1fec7c66 AZ |
86 | |
87 | /* | |
88 | * In the routines that deal directly with the x1205 hardware, we use | |
89 | * rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch | |
90 | * Epoch is initialized as 2000. Time is set to UTC. | |
91 | */ | |
92 | static int x1205_get_datetime(struct i2c_client *client, struct rtc_time *tm, | |
93 | unsigned char reg_base) | |
94 | { | |
95 | unsigned char dt_addr[2] = { 0, reg_base }; | |
1fec7c66 | 96 | unsigned char buf[8]; |
471d47e3 | 97 | int i; |
1fec7c66 AZ |
98 | |
99 | struct i2c_msg msgs[] = { | |
c3fe92b7 S |
100 | {/* setup read ptr */ |
101 | .addr = client->addr, | |
102 | .len = 2, | |
103 | .buf = dt_addr | |
104 | }, | |
105 | {/* read date */ | |
106 | .addr = client->addr, | |
107 | .flags = I2C_M_RD, | |
108 | .len = 8, | |
109 | .buf = buf | |
110 | }, | |
1fec7c66 AZ |
111 | }; |
112 | ||
113 | /* read date registers */ | |
471d47e3 | 114 | if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) { |
2a4e2b87 | 115 | dev_err(&client->dev, "%s: read error\n", __func__); |
1fec7c66 AZ |
116 | return -EIO; |
117 | } | |
118 | ||
119 | dev_dbg(&client->dev, | |
120 | "%s: raw read data - sec=%02x, min=%02x, hr=%02x, " | |
121 | "mday=%02x, mon=%02x, year=%02x, wday=%02x, y2k=%02x\n", | |
2a4e2b87 | 122 | __func__, |
1fec7c66 AZ |
123 | buf[0], buf[1], buf[2], buf[3], |
124 | buf[4], buf[5], buf[6], buf[7]); | |
125 | ||
471d47e3 MH |
126 | /* Mask out the enable bits if these are alarm registers */ |
127 | if (reg_base < X1205_CCR_BASE) | |
128 | for (i = 0; i <= 4; i++) | |
129 | buf[i] &= 0x7F; | |
130 | ||
fe20ba70 AB |
131 | tm->tm_sec = bcd2bin(buf[CCR_SEC]); |
132 | tm->tm_min = bcd2bin(buf[CCR_MIN]); | |
133 | tm->tm_hour = bcd2bin(buf[CCR_HOUR] & 0x3F); /* hr is 0-23 */ | |
134 | tm->tm_mday = bcd2bin(buf[CCR_MDAY]); | |
135 | tm->tm_mon = bcd2bin(buf[CCR_MONTH]) - 1; /* mon is 0-11 */ | |
136 | tm->tm_year = bcd2bin(buf[CCR_YEAR]) | |
137 | + (bcd2bin(buf[CCR_Y2K]) * 100) - 1900; | |
1fec7c66 AZ |
138 | tm->tm_wday = buf[CCR_WDAY]; |
139 | ||
140 | dev_dbg(&client->dev, "%s: tm is secs=%d, mins=%d, hours=%d, " | |
141 | "mday=%d, mon=%d, year=%d, wday=%d\n", | |
2a4e2b87 | 142 | __func__, |
1fec7c66 AZ |
143 | tm->tm_sec, tm->tm_min, tm->tm_hour, |
144 | tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday); | |
145 | ||
146 | return 0; | |
147 | } | |
148 | ||
149 | static int x1205_get_status(struct i2c_client *client, unsigned char *sr) | |
150 | { | |
151 | static unsigned char sr_addr[2] = { 0, X1205_REG_SR }; | |
152 | ||
153 | struct i2c_msg msgs[] = { | |
c3fe92b7 S |
154 | { /* setup read ptr */ |
155 | .addr = client->addr, | |
156 | .len = 2, | |
157 | .buf = sr_addr | |
158 | }, | |
159 | { /* read status */ | |
160 | .addr = client->addr, | |
161 | .flags = I2C_M_RD, | |
162 | .len = 1, | |
163 | .buf = sr | |
164 | }, | |
1fec7c66 AZ |
165 | }; |
166 | ||
167 | /* read status register */ | |
471d47e3 | 168 | if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) { |
2a4e2b87 | 169 | dev_err(&client->dev, "%s: read error\n", __func__); |
1fec7c66 AZ |
170 | return -EIO; |
171 | } | |
172 | ||
173 | return 0; | |
174 | } | |
175 | ||
176 | static int x1205_set_datetime(struct i2c_client *client, struct rtc_time *tm, | |
d973b632 | 177 | u8 reg_base, unsigned char alm_enable) |
1fec7c66 | 178 | { |
d973b632 | 179 | int i, xfer; |
471d47e3 | 180 | unsigned char rdata[10] = { 0, reg_base }; |
d973b632 | 181 | unsigned char *buf = rdata + 2; |
1fec7c66 AZ |
182 | |
183 | static const unsigned char wel[3] = { 0, X1205_REG_SR, | |
184 | X1205_SR_WEL }; | |
185 | ||
186 | static const unsigned char rwel[3] = { 0, X1205_REG_SR, | |
187 | X1205_SR_WEL | X1205_SR_RWEL }; | |
188 | ||
189 | static const unsigned char diswe[3] = { 0, X1205_REG_SR, 0 }; | |
190 | ||
191 | dev_dbg(&client->dev, | |
d973b632 JW |
192 | "%s: sec=%d min=%d hour=%d mday=%d mon=%d year=%d wday=%d\n", |
193 | __func__, tm->tm_sec, tm->tm_min, tm->tm_hour, tm->tm_mday, | |
194 | tm->tm_mon, tm->tm_year, tm->tm_wday); | |
1fec7c66 | 195 | |
fe20ba70 AB |
196 | buf[CCR_SEC] = bin2bcd(tm->tm_sec); |
197 | buf[CCR_MIN] = bin2bcd(tm->tm_min); | |
1fec7c66 AZ |
198 | |
199 | /* set hour and 24hr bit */ | |
fe20ba70 | 200 | buf[CCR_HOUR] = bin2bcd(tm->tm_hour) | X1205_HR_MIL; |
1fec7c66 | 201 | |
d973b632 | 202 | buf[CCR_MDAY] = bin2bcd(tm->tm_mday); |
1fec7c66 | 203 | |
d973b632 JW |
204 | /* month, 1 - 12 */ |
205 | buf[CCR_MONTH] = bin2bcd(tm->tm_mon + 1); | |
1fec7c66 | 206 | |
d973b632 JW |
207 | /* year, since the rtc epoch*/ |
208 | buf[CCR_YEAR] = bin2bcd(tm->tm_year % 100); | |
209 | buf[CCR_WDAY] = tm->tm_wday & 0x07; | |
210 | buf[CCR_Y2K] = bin2bcd((tm->tm_year + 1900) / 100); | |
1fec7c66 | 211 | |
471d47e3 MH |
212 | /* If writing alarm registers, set compare bits on registers 0-4 */ |
213 | if (reg_base < X1205_CCR_BASE) | |
214 | for (i = 0; i <= 4; i++) | |
215 | buf[i] |= 0x80; | |
216 | ||
1fec7c66 | 217 | /* this sequence is required to unlock the chip */ |
66e3f10c SK |
218 | xfer = i2c_master_send(client, wel, 3); |
219 | if (xfer != 3) { | |
2a4e2b87 | 220 | dev_err(&client->dev, "%s: wel - %d\n", __func__, xfer); |
1fec7c66 AZ |
221 | return -EIO; |
222 | } | |
223 | ||
66e3f10c SK |
224 | xfer = i2c_master_send(client, rwel, 3); |
225 | if (xfer != 3) { | |
2a4e2b87 | 226 | dev_err(&client->dev, "%s: rwel - %d\n", __func__, xfer); |
1fec7c66 AZ |
227 | return -EIO; |
228 | } | |
229 | ||
d973b632 JW |
230 | xfer = i2c_master_send(client, rdata, sizeof(rdata)); |
231 | if (xfer != sizeof(rdata)) { | |
471d47e3 MH |
232 | dev_err(&client->dev, |
233 | "%s: result=%d addr=%02x, data=%02x\n", | |
234 | __func__, | |
235 | xfer, rdata[1], rdata[2]); | |
236 | return -EIO; | |
237 | } | |
238 | ||
239 | /* If we wrote to the nonvolatile region, wait 10msec for write cycle*/ | |
240 | if (reg_base < X1205_CCR_BASE) { | |
241 | unsigned char al0e[3] = { 0, X1205_REG_INT, 0 }; | |
242 | ||
243 | msleep(10); | |
244 | ||
245 | /* ...and set or clear the AL0E bit in the INT register */ | |
1fec7c66 | 246 | |
471d47e3 MH |
247 | /* Need to set RWEL again as the write has cleared it */ |
248 | xfer = i2c_master_send(client, rwel, 3); | |
1fec7c66 AZ |
249 | if (xfer != 3) { |
250 | dev_err(&client->dev, | |
471d47e3 | 251 | "%s: aloe rwel - %d\n", |
2a4e2b87 | 252 | __func__, |
471d47e3 MH |
253 | xfer); |
254 | return -EIO; | |
255 | } | |
256 | ||
257 | if (alm_enable) | |
258 | al0e[2] = X1205_INT_AL0E; | |
259 | ||
260 | xfer = i2c_master_send(client, al0e, 3); | |
261 | if (xfer != 3) { | |
262 | dev_err(&client->dev, | |
263 | "%s: al0e - %d\n", | |
264 | __func__, | |
265 | xfer); | |
1fec7c66 AZ |
266 | return -EIO; |
267 | } | |
471d47e3 MH |
268 | |
269 | /* and wait 10msec again for this write to complete */ | |
270 | msleep(10); | |
271 | } | |
1fec7c66 AZ |
272 | |
273 | /* disable further writes */ | |
66e3f10c SK |
274 | xfer = i2c_master_send(client, diswe, 3); |
275 | if (xfer != 3) { | |
2a4e2b87 | 276 | dev_err(&client->dev, "%s: diswe - %d\n", __func__, xfer); |
1fec7c66 AZ |
277 | return -EIO; |
278 | } | |
279 | ||
280 | return 0; | |
281 | } | |
282 | ||
283 | static int x1205_fix_osc(struct i2c_client *client) | |
284 | { | |
285 | int err; | |
286 | struct rtc_time tm; | |
287 | ||
cb8799ee | 288 | memset(&tm, 0, sizeof(tm)); |
1fec7c66 | 289 | |
d973b632 | 290 | err = x1205_set_datetime(client, &tm, X1205_CCR_BASE, 0); |
471d47e3 MH |
291 | if (err < 0) |
292 | dev_err(&client->dev, "unable to restart the oscillator\n"); | |
1fec7c66 AZ |
293 | |
294 | return err; | |
295 | } | |
296 | ||
297 | static int x1205_get_dtrim(struct i2c_client *client, int *trim) | |
298 | { | |
299 | unsigned char dtr; | |
300 | static unsigned char dtr_addr[2] = { 0, X1205_REG_DTR }; | |
301 | ||
302 | struct i2c_msg msgs[] = { | |
c3fe92b7 S |
303 | { /* setup read ptr */ |
304 | .addr = client->addr, | |
305 | .len = 2, | |
306 | .buf = dtr_addr | |
307 | }, | |
308 | { /* read dtr */ | |
309 | .addr = client->addr, | |
310 | .flags = I2C_M_RD, | |
311 | .len = 1, | |
312 | .buf = &dtr | |
313 | }, | |
1fec7c66 AZ |
314 | }; |
315 | ||
316 | /* read dtr register */ | |
471d47e3 | 317 | if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) { |
2a4e2b87 | 318 | dev_err(&client->dev, "%s: read error\n", __func__); |
1fec7c66 AZ |
319 | return -EIO; |
320 | } | |
321 | ||
2a4e2b87 | 322 | dev_dbg(&client->dev, "%s: raw dtr=%x\n", __func__, dtr); |
1fec7c66 AZ |
323 | |
324 | *trim = 0; | |
325 | ||
326 | if (dtr & X1205_DTR_DTR0) | |
327 | *trim += 20; | |
328 | ||
329 | if (dtr & X1205_DTR_DTR1) | |
330 | *trim += 10; | |
331 | ||
332 | if (dtr & X1205_DTR_DTR2) | |
333 | *trim = -*trim; | |
334 | ||
335 | return 0; | |
336 | } | |
337 | ||
338 | static int x1205_get_atrim(struct i2c_client *client, int *trim) | |
339 | { | |
340 | s8 atr; | |
341 | static unsigned char atr_addr[2] = { 0, X1205_REG_ATR }; | |
342 | ||
343 | struct i2c_msg msgs[] = { | |
c3fe92b7 S |
344 | {/* setup read ptr */ |
345 | .addr = client->addr, | |
346 | .len = 2, | |
347 | .buf = atr_addr | |
348 | }, | |
349 | {/* read atr */ | |
350 | .addr = client->addr, | |
351 | .flags = I2C_M_RD, | |
352 | .len = 1, | |
353 | .buf = &atr | |
354 | }, | |
1fec7c66 AZ |
355 | }; |
356 | ||
357 | /* read atr register */ | |
471d47e3 | 358 | if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) { |
2a4e2b87 | 359 | dev_err(&client->dev, "%s: read error\n", __func__); |
1fec7c66 AZ |
360 | return -EIO; |
361 | } | |
362 | ||
2a4e2b87 | 363 | dev_dbg(&client->dev, "%s: raw atr=%x\n", __func__, atr); |
1fec7c66 AZ |
364 | |
365 | /* atr is a two's complement value on 6 bits, | |
366 | * perform sign extension. The formula is | |
367 | * Catr = (atr * 0.25pF) + 11.00pF. | |
368 | */ | |
369 | if (atr & 0x20) | |
370 | atr |= 0xC0; | |
371 | ||
2a4e2b87 | 372 | dev_dbg(&client->dev, "%s: raw atr=%x (%d)\n", __func__, atr, atr); |
1fec7c66 AZ |
373 | |
374 | *trim = (atr * 250) + 11000; | |
375 | ||
2a4e2b87 | 376 | dev_dbg(&client->dev, "%s: real=%d\n", __func__, *trim); |
1fec7c66 AZ |
377 | |
378 | return 0; | |
379 | } | |
380 | ||
66e3f10c | 381 | struct x1205_limit { |
1fec7c66 AZ |
382 | unsigned char reg, mask, min, max; |
383 | }; | |
384 | ||
385 | static int x1205_validate_client(struct i2c_client *client) | |
386 | { | |
387 | int i, xfer; | |
388 | ||
389 | /* Probe array. We will read the register at the specified | |
390 | * address and check if the given bits are zero. | |
391 | */ | |
392 | static const unsigned char probe_zero_pattern[] = { | |
393 | /* register, mask */ | |
394 | X1205_REG_SR, 0x18, | |
395 | X1205_REG_DTR, 0xF8, | |
396 | X1205_REG_ATR, 0xC0, | |
397 | X1205_REG_INT, 0x18, | |
398 | X1205_REG_0, 0xFF, | |
399 | }; | |
400 | ||
401 | static const struct x1205_limit probe_limits_pattern[] = { | |
402 | /* register, mask, min, max */ | |
403 | { X1205_REG_Y2K, 0xFF, 19, 20 }, | |
404 | { X1205_REG_DW, 0xFF, 0, 6 }, | |
405 | { X1205_REG_YR, 0xFF, 0, 99 }, | |
406 | { X1205_REG_MO, 0xFF, 0, 12 }, | |
407 | { X1205_REG_DT, 0xFF, 0, 31 }, | |
408 | { X1205_REG_HR, 0x7F, 0, 23 }, | |
409 | { X1205_REG_MN, 0xFF, 0, 59 }, | |
410 | { X1205_REG_SC, 0xFF, 0, 59 }, | |
411 | { X1205_REG_Y2K1, 0xFF, 19, 20 }, | |
412 | { X1205_REG_Y2K0, 0xFF, 19, 20 }, | |
413 | }; | |
414 | ||
415 | /* check that registers have bits a 0 where expected */ | |
416 | for (i = 0; i < ARRAY_SIZE(probe_zero_pattern); i += 2) { | |
417 | unsigned char buf; | |
418 | ||
419 | unsigned char addr[2] = { 0, probe_zero_pattern[i] }; | |
420 | ||
421 | struct i2c_msg msgs[2] = { | |
c3fe92b7 S |
422 | { |
423 | .addr = client->addr, | |
424 | .len = 2, | |
425 | .buf = addr | |
426 | }, | |
427 | { | |
428 | .addr = client->addr, | |
429 | .flags = I2C_M_RD, | |
430 | .len = 1, | |
431 | .buf = &buf | |
432 | }, | |
1fec7c66 AZ |
433 | }; |
434 | ||
66e3f10c SK |
435 | xfer = i2c_transfer(client->adapter, msgs, 2); |
436 | if (xfer != 2) { | |
a14e1893 | 437 | dev_err(&client->dev, |
1fec7c66 | 438 | "%s: could not read register %x\n", |
2a4e2b87 | 439 | __func__, probe_zero_pattern[i]); |
1fec7c66 AZ |
440 | |
441 | return -EIO; | |
442 | } | |
443 | ||
444 | if ((buf & probe_zero_pattern[i+1]) != 0) { | |
a14e1893 | 445 | dev_err(&client->dev, |
1fec7c66 | 446 | "%s: register=%02x, zero pattern=%d, value=%x\n", |
2a4e2b87 | 447 | __func__, probe_zero_pattern[i], i, buf); |
1fec7c66 AZ |
448 | |
449 | return -ENODEV; | |
450 | } | |
451 | } | |
452 | ||
453 | /* check limits (only registers with bcd values) */ | |
454 | for (i = 0; i < ARRAY_SIZE(probe_limits_pattern); i++) { | |
455 | unsigned char reg, value; | |
456 | ||
457 | unsigned char addr[2] = { 0, probe_limits_pattern[i].reg }; | |
458 | ||
459 | struct i2c_msg msgs[2] = { | |
c3fe92b7 S |
460 | { |
461 | .addr = client->addr, | |
462 | .len = 2, | |
463 | .buf = addr | |
464 | }, | |
465 | { | |
466 | .addr = client->addr, | |
467 | .flags = I2C_M_RD, | |
468 | .len = 1, | |
469 | .buf = ® | |
470 | }, | |
1fec7c66 AZ |
471 | }; |
472 | ||
66e3f10c SK |
473 | xfer = i2c_transfer(client->adapter, msgs, 2); |
474 | if (xfer != 2) { | |
a14e1893 | 475 | dev_err(&client->dev, |
1fec7c66 | 476 | "%s: could not read register %x\n", |
2a4e2b87 | 477 | __func__, probe_limits_pattern[i].reg); |
1fec7c66 AZ |
478 | |
479 | return -EIO; | |
480 | } | |
481 | ||
fe20ba70 | 482 | value = bcd2bin(reg & probe_limits_pattern[i].mask); |
1fec7c66 AZ |
483 | |
484 | if (value > probe_limits_pattern[i].max || | |
485 | value < probe_limits_pattern[i].min) { | |
a14e1893 | 486 | dev_dbg(&client->dev, |
1fec7c66 | 487 | "%s: register=%x, lim pattern=%d, value=%d\n", |
2a4e2b87 | 488 | __func__, probe_limits_pattern[i].reg, |
1fec7c66 AZ |
489 | i, value); |
490 | ||
491 | return -ENODEV; | |
492 | } | |
493 | } | |
494 | ||
495 | return 0; | |
496 | } | |
497 | ||
498 | static int x1205_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) | |
499 | { | |
471d47e3 MH |
500 | int err; |
501 | unsigned char intreg, status; | |
502 | static unsigned char int_addr[2] = { 0, X1205_REG_INT }; | |
503 | struct i2c_client *client = to_i2c_client(dev); | |
504 | struct i2c_msg msgs[] = { | |
c3fe92b7 S |
505 | { /* setup read ptr */ |
506 | .addr = client->addr, | |
507 | .len = 2, | |
508 | .buf = int_addr | |
509 | }, | |
510 | {/* read INT register */ | |
511 | ||
512 | .addr = client->addr, | |
513 | .flags = I2C_M_RD, | |
514 | .len = 1, | |
515 | .buf = &intreg | |
516 | }, | |
471d47e3 MH |
517 | }; |
518 | ||
519 | /* read interrupt register and status register */ | |
520 | if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) { | |
521 | dev_err(&client->dev, "%s: read error\n", __func__); | |
522 | return -EIO; | |
523 | } | |
524 | err = x1205_get_status(client, &status); | |
525 | if (err == 0) { | |
526 | alrm->pending = (status & X1205_SR_AL0) ? 1 : 0; | |
527 | alrm->enabled = (intreg & X1205_INT_AL0E) ? 1 : 0; | |
528 | err = x1205_get_datetime(client, &alrm->time, X1205_ALM0_BASE); | |
529 | } | |
530 | return err; | |
1fec7c66 AZ |
531 | } |
532 | ||
533 | static int x1205_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) | |
534 | { | |
535 | return x1205_set_datetime(to_i2c_client(dev), | |
d973b632 | 536 | &alrm->time, X1205_ALM0_BASE, alrm->enabled); |
1fec7c66 AZ |
537 | } |
538 | ||
539 | static int x1205_rtc_read_time(struct device *dev, struct rtc_time *tm) | |
540 | { | |
541 | return x1205_get_datetime(to_i2c_client(dev), | |
542 | tm, X1205_CCR_BASE); | |
543 | } | |
544 | ||
545 | static int x1205_rtc_set_time(struct device *dev, struct rtc_time *tm) | |
546 | { | |
547 | return x1205_set_datetime(to_i2c_client(dev), | |
d973b632 | 548 | tm, X1205_CCR_BASE, 0); |
1fec7c66 AZ |
549 | } |
550 | ||
551 | static int x1205_rtc_proc(struct device *dev, struct seq_file *seq) | |
552 | { | |
553 | int err, dtrim, atrim; | |
554 | ||
66e3f10c SK |
555 | err = x1205_get_dtrim(to_i2c_client(dev), &dtrim); |
556 | if (!err) | |
1fec7c66 AZ |
557 | seq_printf(seq, "digital_trim\t: %d ppm\n", dtrim); |
558 | ||
66e3f10c SK |
559 | err = x1205_get_atrim(to_i2c_client(dev), &atrim); |
560 | if (!err) | |
1fec7c66 AZ |
561 | seq_printf(seq, "analog_trim\t: %d.%02d pF\n", |
562 | atrim / 1000, atrim % 1000); | |
563 | return 0; | |
564 | } | |
565 | ||
ff8371ac | 566 | static const struct rtc_class_ops x1205_rtc_ops = { |
1fec7c66 AZ |
567 | .proc = x1205_rtc_proc, |
568 | .read_time = x1205_rtc_read_time, | |
569 | .set_time = x1205_rtc_set_time, | |
570 | .read_alarm = x1205_rtc_read_alarm, | |
571 | .set_alarm = x1205_rtc_set_alarm, | |
572 | }; | |
573 | ||
574 | static ssize_t x1205_sysfs_show_atrim(struct device *dev, | |
575 | struct device_attribute *attr, char *buf) | |
576 | { | |
015aefbb | 577 | int err, atrim; |
1fec7c66 | 578 | |
015aefbb AZ |
579 | err = x1205_get_atrim(to_i2c_client(dev), &atrim); |
580 | if (err) | |
581 | return err; | |
582 | ||
583 | return sprintf(buf, "%d.%02d pF\n", atrim / 1000, atrim % 1000); | |
1fec7c66 AZ |
584 | } |
585 | static DEVICE_ATTR(atrim, S_IRUGO, x1205_sysfs_show_atrim, NULL); | |
586 | ||
587 | static ssize_t x1205_sysfs_show_dtrim(struct device *dev, | |
588 | struct device_attribute *attr, char *buf) | |
589 | { | |
015aefbb | 590 | int err, dtrim; |
1fec7c66 | 591 | |
015aefbb AZ |
592 | err = x1205_get_dtrim(to_i2c_client(dev), &dtrim); |
593 | if (err) | |
594 | return err; | |
1fec7c66 | 595 | |
015aefbb | 596 | return sprintf(buf, "%d ppm\n", dtrim); |
1fec7c66 AZ |
597 | } |
598 | static DEVICE_ATTR(dtrim, S_IRUGO, x1205_sysfs_show_dtrim, NULL); | |
599 | ||
4edac2b4 AZ |
600 | static int x1205_sysfs_register(struct device *dev) |
601 | { | |
602 | int err; | |
603 | ||
604 | err = device_create_file(dev, &dev_attr_atrim); | |
605 | if (err) | |
606 | return err; | |
607 | ||
608 | err = device_create_file(dev, &dev_attr_dtrim); | |
609 | if (err) | |
610 | device_remove_file(dev, &dev_attr_atrim); | |
611 | ||
612 | return err; | |
613 | } | |
614 | ||
615 | static void x1205_sysfs_unregister(struct device *dev) | |
1fec7c66 | 616 | { |
4edac2b4 AZ |
617 | device_remove_file(dev, &dev_attr_atrim); |
618 | device_remove_file(dev, &dev_attr_dtrim); | |
1fec7c66 AZ |
619 | } |
620 | ||
4edac2b4 | 621 | |
d2653e92 JD |
622 | static int x1205_probe(struct i2c_client *client, |
623 | const struct i2c_device_id *id) | |
1fec7c66 AZ |
624 | { |
625 | int err = 0; | |
626 | unsigned char sr; | |
1fec7c66 AZ |
627 | struct rtc_device *rtc; |
628 | ||
4edac2b4 | 629 | dev_dbg(&client->dev, "%s\n", __func__); |
1fec7c66 | 630 | |
4edac2b4 AZ |
631 | if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) |
632 | return -ENODEV; | |
1fec7c66 | 633 | |
4edac2b4 AZ |
634 | if (x1205_validate_client(client) < 0) |
635 | return -ENODEV; | |
1fec7c66 AZ |
636 | |
637 | dev_info(&client->dev, "chip found, driver version " DRV_VERSION "\n"); | |
638 | ||
17581718 JH |
639 | rtc = devm_rtc_device_register(&client->dev, x1205_driver.driver.name, |
640 | &x1205_rtc_ops, THIS_MODULE); | |
1fec7c66 | 641 | |
4edac2b4 AZ |
642 | if (IS_ERR(rtc)) |
643 | return PTR_ERR(rtc); | |
1fec7c66 AZ |
644 | |
645 | i2c_set_clientdata(client, rtc); | |
646 | ||
25985edc | 647 | /* Check for power failures and eventually enable the osc */ |
66e3f10c SK |
648 | err = x1205_get_status(client, &sr); |
649 | if (!err) { | |
1fec7c66 AZ |
650 | if (sr & X1205_SR_RTCF) { |
651 | dev_err(&client->dev, | |
652 | "power failure detected, " | |
653 | "please set the clock\n"); | |
654 | udelay(50); | |
655 | x1205_fix_osc(client); | |
656 | } | |
66e3f10c | 657 | } else { |
1fec7c66 | 658 | dev_err(&client->dev, "couldn't read status\n"); |
66e3f10c | 659 | } |
1fec7c66 | 660 | |
4edac2b4 AZ |
661 | err = x1205_sysfs_register(&client->dev); |
662 | if (err) | |
17581718 | 663 | return err; |
1fec7c66 AZ |
664 | |
665 | return 0; | |
1fec7c66 AZ |
666 | } |
667 | ||
4edac2b4 | 668 | static int x1205_remove(struct i2c_client *client) |
1fec7c66 | 669 | { |
4edac2b4 | 670 | x1205_sysfs_unregister(&client->dev); |
1fec7c66 AZ |
671 | return 0; |
672 | } | |
673 | ||
3760f736 JD |
674 | static const struct i2c_device_id x1205_id[] = { |
675 | { "x1205", 0 }, | |
676 | { } | |
677 | }; | |
678 | MODULE_DEVICE_TABLE(i2c, x1205_id); | |
679 | ||
4edac2b4 AZ |
680 | static struct i2c_driver x1205_driver = { |
681 | .driver = { | |
682 | .name = "rtc-x1205", | |
683 | }, | |
684 | .probe = x1205_probe, | |
685 | .remove = x1205_remove, | |
3760f736 | 686 | .id_table = x1205_id, |
4edac2b4 AZ |
687 | }; |
688 | ||
0abc9201 | 689 | module_i2c_driver(x1205_driver); |
1fec7c66 AZ |
690 | |
691 | MODULE_AUTHOR( | |
692 | "Karen Spearel <kas111 at gmail dot com>, " | |
693 | "Alessandro Zummo <a.zummo@towertech.it>"); | |
694 | MODULE_DESCRIPTION("Xicor/Intersil X1205 RTC driver"); | |
695 | MODULE_LICENSE("GPL"); | |
696 | MODULE_VERSION(DRV_VERSION); |