[deliverable/linux.git] / drivers / rtc / rtc-x1205.c

/*
 * An i2c driver for the Xicor/Intersil X1205 RTC
 * Copyright 2004 Karen Spearel
 * Copyright 2005 Alessandro Zummo
 *
 * please send all reports to:
 * 	Karen Spearel <kas111 at gmail dot com>
 *	Alessandro Zummo <a.zummo@towertech.it>
 *
 * based on a lot of other RTC drivers.
 *
 * Information and datasheet:
 * http://www.intersil.com/cda/deviceinfo/0,1477,X1205,00.html
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/i2c.h>
#include <linux/bcd.h>
#include <linux/rtc.h>
#include <linux/delay.h>

#define DRV_VERSION "1.0.8"

/* offsets into CCR area */

#define CCR_SEC			0
#define CCR_MIN			1
#define CCR_HOUR		2
#define CCR_MDAY		3
#define CCR_MONTH		4
#define CCR_YEAR		5
#define CCR_WDAY		6
#define CCR_Y2K			7

#define X1205_REG_SR		0x3F	/* status register */
#define X1205_REG_Y2K		0x37
#define X1205_REG_DW		0x36
#define X1205_REG_YR		0x35
#define X1205_REG_MO		0x34
#define X1205_REG_DT		0x33
#define X1205_REG_HR		0x32
#define X1205_REG_MN		0x31
#define X1205_REG_SC		0x30
#define X1205_REG_DTR		0x13
#define X1205_REG_ATR		0x12
#define X1205_REG_INT		0x11
#define X1205_REG_0		0x10
#define X1205_REG_Y2K1		0x0F
#define X1205_REG_DWA1		0x0E
#define X1205_REG_YRA1		0x0D
#define X1205_REG_MOA1		0x0C
#define X1205_REG_DTA1		0x0B
#define X1205_REG_HRA1		0x0A
#define X1205_REG_MNA1		0x09
#define X1205_REG_SCA1		0x08
#define X1205_REG_Y2K0		0x07
#define X1205_REG_DWA0		0x06
#define X1205_REG_YRA0		0x05
#define X1205_REG_MOA0		0x04
#define X1205_REG_DTA0		0x03
#define X1205_REG_HRA0		0x02
#define X1205_REG_MNA0		0x01
#define X1205_REG_SCA0		0x00

#define X1205_CCR_BASE		0x30	/* Base address of CCR */
#define X1205_ALM0_BASE		0x00	/* Base address of ALARM0 */

#define X1205_SR_RTCF		0x01	/* Clock failure */
#define X1205_SR_WEL		0x02	/* Write Enable Latch */
#define X1205_SR_RWEL		0x04	/* Register Write Enable */
#define X1205_SR_AL0		0x20	/* Alarm 0 match */

#define X1205_DTR_DTR0		0x01
#define X1205_DTR_DTR1		0x02
#define X1205_DTR_DTR2		0x04

#define X1205_HR_MIL		0x80	/* Set in ccr.hour for 24 hr mode */

#define X1205_INT_AL0E		0x20	/* Alarm 0 enable */

static struct i2c_driver x1205_driver;

/*
 * In the routines that deal directly with the x1205 hardware, we use
 * rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch
 * Epoch is initialized as 2000. Time is set to UTC.
 */
static int x1205_get_datetime(struct i2c_client *client, struct rtc_time *tm,
				unsigned char reg_base)
{
	unsigned char dt_addr[2] = { 0, reg_base };
	unsigned char buf[8];
	int i;

	struct i2c_msg msgs[] = {
		{ client->addr, 0, 2, dt_addr },	/* setup read ptr */
		{ client->addr, I2C_M_RD, 8, buf },	/* read date */
	};

	/* read date registers */
	if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) {
		dev_err(&client->dev, "%s: read error\n", __func__);
		return -EIO;
	}

	dev_dbg(&client->dev,
		"%s: raw read data - sec=%02x, min=%02x, hr=%02x, "
		"mday=%02x, mon=%02x, year=%02x, wday=%02x, y2k=%02x\n",
		__func__,
		buf[0], buf[1], buf[2], buf[3],
		buf[4], buf[5], buf[6], buf[7]);

	/* Mask out the enable bits if these are alarm registers */
	if (reg_base < X1205_CCR_BASE)
		for (i = 0; i <= 4; i++)
			buf[i] &= 0x7F;

	tm->tm_sec = BCD2BIN(buf[CCR_SEC]);
	tm->tm_min = BCD2BIN(buf[CCR_MIN]);
	tm->tm_hour = BCD2BIN(buf[CCR_HOUR] & 0x3F); /* hr is 0-23 */
	tm->tm_mday = BCD2BIN(buf[CCR_MDAY]);
	tm->tm_mon = BCD2BIN(buf[CCR_MONTH]) - 1; /* mon is 0-11 */
	tm->tm_year = BCD2BIN(buf[CCR_YEAR])
			+ (BCD2BIN(buf[CCR_Y2K]) * 100) - 1900;
	tm->tm_wday = buf[CCR_WDAY];

	dev_dbg(&client->dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
		"mday=%d, mon=%d, year=%d, wday=%d\n",
		__func__,
		tm->tm_sec, tm->tm_min, tm->tm_hour,
		tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);

	return 0;
}

static int x1205_get_status(struct i2c_client *client, unsigned char *sr)
{
	static unsigned char sr_addr[2] = { 0, X1205_REG_SR };

	struct i2c_msg msgs[] = {
		{ client->addr, 0, 2, sr_addr },	/* setup read ptr */
		{ client->addr, I2C_M_RD, 1, sr },	/* read status */
	};

	/* read status register */
	if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) {
		dev_err(&client->dev, "%s: read error\n", __func__);
		return -EIO;
	}

	return 0;
}

static int x1205_set_datetime(struct i2c_client *client, struct rtc_time *tm,
			int datetoo, u8 reg_base, unsigned char alm_enable)
{
	int i, xfer, nbytes;
	unsigned char buf[8];
	unsigned char rdata[10] = { 0, reg_base };

	static const unsigned char wel[3] = { 0, X1205_REG_SR,
						X1205_SR_WEL };

	static const unsigned char rwel[3] = { 0, X1205_REG_SR,
						X1205_SR_WEL | X1205_SR_RWEL };

	static const unsigned char diswe[3] = { 0, X1205_REG_SR, 0 };

	dev_dbg(&client->dev,
		"%s: secs=%d, mins=%d, hours=%d\n",
		__func__,
		tm->tm_sec, tm->tm_min, tm->tm_hour);

	buf[CCR_SEC] = BIN2BCD(tm->tm_sec);
	buf[CCR_MIN] = BIN2BCD(tm->tm_min);

	/* set hour and 24hr bit */
	buf[CCR_HOUR] = BIN2BCD(tm->tm_hour) | X1205_HR_MIL;

	/* should we also set the date? */
	if (datetoo) {
		dev_dbg(&client->dev,
			"%s: mday=%d, mon=%d, year=%d, wday=%d\n",
			__func__,
			tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);

		buf[CCR_MDAY] = BIN2BCD(tm->tm_mday);

		/* month, 1 - 12 */
		buf[CCR_MONTH] = BIN2BCD(tm->tm_mon + 1);

		/* year, since the rtc epoch*/
		buf[CCR_YEAR] = BIN2BCD(tm->tm_year % 100);
		buf[CCR_WDAY] = tm->tm_wday & 0x07;
		buf[CCR_Y2K] = BIN2BCD(tm->tm_year / 100);
	}

	/* If writing alarm registers, set compare bits on registers 0-4 */
	if (reg_base < X1205_CCR_BASE)
		for (i = 0; i <= 4; i++)
			buf[i] |= 0x80;

	/* this sequence is required to unlock the chip */
	if ((xfer = i2c_master_send(client, wel, 3)) != 3) {
		dev_err(&client->dev, "%s: wel - %d\n", __func__, xfer);
		return -EIO;
	}

	if ((xfer = i2c_master_send(client, rwel, 3)) != 3) {
		dev_err(&client->dev, "%s: rwel - %d\n", __func__, xfer);
		return -EIO;
	}


	/* write register's data */
	if (datetoo)
		nbytes = 8;
	else
		nbytes = 3;
	for (i = 0; i < nbytes; i++)
		rdata[2+i] = buf[i];

	xfer = i2c_master_send(client, rdata, nbytes+2);
	if (xfer != nbytes+2) {
		dev_err(&client->dev,
			"%s: result=%d addr=%02x, data=%02x\n",
			__func__,
			 xfer, rdata[1], rdata[2]);
		return -EIO;
	}

	/* If we wrote to the nonvolatile region, wait 10msec for write cycle*/
	if (reg_base < X1205_CCR_BASE) {
		unsigned char al0e[3] = { 0, X1205_REG_INT, 0 };

		msleep(10);

		/* ...and set or clear the AL0E bit in the INT register */

		/* Need to set RWEL again as the write has cleared it */
		xfer = i2c_master_send(client, rwel, 3);
		if (xfer != 3) {
			dev_err(&client->dev,
				"%s: aloe rwel - %d\n",
				__func__,
				xfer);
			return -EIO;
		}

		if (alm_enable)
			al0e[2] = X1205_INT_AL0E;

		xfer = i2c_master_send(client, al0e, 3);
		if (xfer != 3) {
			dev_err(&client->dev,
				"%s: al0e - %d\n",
				__func__,
				xfer);
			return -EIO;
		}

		/* and wait 10msec again for this write to complete */
		msleep(10);
	}

	/* disable further writes */
	if ((xfer = i2c_master_send(client, diswe, 3)) != 3) {
		dev_err(&client->dev, "%s: diswe - %d\n", __func__, xfer);
		return -EIO;
	}

	return 0;
}

static int x1205_fix_osc(struct i2c_client *client)
{
	int err;
	struct rtc_time tm;

	tm.tm_hour = tm.tm_min = tm.tm_sec = 0;

	err = x1205_set_datetime(client, &tm, 0, X1205_CCR_BASE, 0);
	if (err < 0)
		dev_err(&client->dev, "unable to restart the oscillator\n");

	return err;
}

static int x1205_get_dtrim(struct i2c_client *client, int *trim)
{
	unsigned char dtr;
	static unsigned char dtr_addr[2] = { 0, X1205_REG_DTR };

	struct i2c_msg msgs[] = {
		{ client->addr, 0, 2, dtr_addr },	/* setup read ptr */
		{ client->addr, I2C_M_RD, 1, &dtr }, 	/* read dtr */
	};

	/* read dtr register */
	if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) {
		dev_err(&client->dev, "%s: read error\n", __func__);
		return -EIO;
	}

	dev_dbg(&client->dev, "%s: raw dtr=%x\n", __func__, dtr);

	*trim = 0;

	if (dtr & X1205_DTR_DTR0)
		*trim += 20;

	if (dtr & X1205_DTR_DTR1)
		*trim += 10;

	if (dtr & X1205_DTR_DTR2)
		*trim = -*trim;

	return 0;
}

static int x1205_get_atrim(struct i2c_client *client, int *trim)
{
	s8 atr;
	static unsigned char atr_addr[2] = { 0, X1205_REG_ATR };

	struct i2c_msg msgs[] = {
		{ client->addr, 0, 2, atr_addr },	/* setup read ptr */
		{ client->addr, I2C_M_RD, 1, &atr }, 	/* read atr */
	};

	/* read atr register */
	if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) {
		dev_err(&client->dev, "%s: read error\n", __func__);
		return -EIO;
	}

	dev_dbg(&client->dev, "%s: raw atr=%x\n", __func__, atr);

	/* atr is a two's complement value on 6 bits,
	 * perform sign extension. The formula is
	 * Catr = (atr * 0.25pF) + 11.00pF.
	 */
	if (atr & 0x20)
		atr |= 0xC0;

	dev_dbg(&client->dev, "%s: raw atr=%x (%d)\n", __func__, atr, atr);

	*trim = (atr * 250) + 11000;

	dev_dbg(&client->dev, "%s: real=%d\n", __func__, *trim);

	return 0;
}

struct x1205_limit
{
	unsigned char reg, mask, min, max;
};

static int x1205_validate_client(struct i2c_client *client)
{
	int i, xfer;

	/* Probe array. We will read the register at the specified
	 * address and check if the given bits are zero.
	 */
	static const unsigned char probe_zero_pattern[] = {
		/* register, mask */
		X1205_REG_SR,	0x18,
		X1205_REG_DTR,	0xF8,
		X1205_REG_ATR,	0xC0,
		X1205_REG_INT,	0x18,
		X1205_REG_0,	0xFF,
	};

	static const struct x1205_limit probe_limits_pattern[] = {
		/* register, mask, min, max */
		{ X1205_REG_Y2K,	0xFF,	19,	20	},
		{ X1205_REG_DW,		0xFF,	0,	6	},
		{ X1205_REG_YR,		0xFF,	0,	99	},
		{ X1205_REG_MO,		0xFF,	0,	12	},
		{ X1205_REG_DT,		0xFF,	0,	31	},
		{ X1205_REG_HR,		0x7F,	0,	23	},
		{ X1205_REG_MN,		0xFF,	0,	59	},
		{ X1205_REG_SC,		0xFF,	0,	59	},
		{ X1205_REG_Y2K1,	0xFF,	19,	20	},
		{ X1205_REG_Y2K0,	0xFF,	19,	20	},
	};

	/* check that registers have bits a 0 where expected */
	for (i = 0; i < ARRAY_SIZE(probe_zero_pattern); i += 2) {
		unsigned char buf;

		unsigned char addr[2] = { 0, probe_zero_pattern[i] };

		struct i2c_msg msgs[2] = {
			{ client->addr, 0, 2, addr },
			{ client->addr, I2C_M_RD, 1, &buf },
		};

		if ((xfer = i2c_transfer(client->adapter, msgs, 2)) != 2) {
			dev_err(&client->dev,
				"%s: could not read register %x\n",
				__func__, probe_zero_pattern[i]);

			return -EIO;
		}

		if ((buf & probe_zero_pattern[i+1]) != 0) {
			dev_err(&client->dev,
				"%s: register=%02x, zero pattern=%d, value=%x\n",
				__func__, probe_zero_pattern[i], i, buf);

			return -ENODEV;
		}
	}

	/* check limits (only registers with bcd values) */
	for (i = 0; i < ARRAY_SIZE(probe_limits_pattern); i++) {
		unsigned char reg, value;

		unsigned char addr[2] = { 0, probe_limits_pattern[i].reg };

		struct i2c_msg msgs[2] = {
			{ client->addr, 0, 2, addr },
			{ client->addr, I2C_M_RD, 1, &reg },
		};

		if ((xfer = i2c_transfer(client->adapter, msgs, 2)) != 2) {
			dev_err(&client->dev,
				"%s: could not read register %x\n",
				__func__, probe_limits_pattern[i].reg);

			return -EIO;
		}

		value = BCD2BIN(reg & probe_limits_pattern[i].mask);

		if (value > probe_limits_pattern[i].max ||
			value < probe_limits_pattern[i].min) {
			dev_dbg(&client->dev,
				"%s: register=%x, lim pattern=%d, value=%d\n",
				__func__, probe_limits_pattern[i].reg,
				i, value);

			return -ENODEV;
		}
	}

	return 0;
}

static int x1205_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	int err;
	unsigned char intreg, status;
	static unsigned char int_addr[2] = { 0, X1205_REG_INT };
	struct i2c_client *client = to_i2c_client(dev);
	struct i2c_msg msgs[] = {
		{ client->addr, 0, 2, int_addr },        /* setup read ptr */
		{ client->addr, I2C_M_RD, 1, &intreg },  /* read INT register */
	};

	/* read interrupt register and status register */
	if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) {
		dev_err(&client->dev, "%s: read error\n", __func__);
		return -EIO;
	}
	err = x1205_get_status(client, &status);
	if (err == 0) {
		alrm->pending = (status & X1205_SR_AL0) ? 1 : 0;
		alrm->enabled = (intreg & X1205_INT_AL0E) ? 1 : 0;
		err = x1205_get_datetime(client, &alrm->time, X1205_ALM0_BASE);
	}
	return err;
}

static int x1205_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	return x1205_set_datetime(to_i2c_client(dev),
		&alrm->time, 1, X1205_ALM0_BASE, alrm->enabled);
}

static int x1205_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
	return x1205_get_datetime(to_i2c_client(dev),
		tm, X1205_CCR_BASE);
}

static int x1205_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
	return x1205_set_datetime(to_i2c_client(dev),
		tm, 1, X1205_CCR_BASE, 0);
}

static int x1205_rtc_proc(struct device *dev, struct seq_file *seq)
{
	int err, dtrim, atrim;

	if ((err = x1205_get_dtrim(to_i2c_client(dev), &dtrim)) == 0)
		seq_printf(seq, "digital_trim\t: %d ppm\n", dtrim);

	if ((err = x1205_get_atrim(to_i2c_client(dev), &atrim)) == 0)
		seq_printf(seq, "analog_trim\t: %d.%02d pF\n",
			atrim / 1000, atrim % 1000);
	return 0;
}

static const struct rtc_class_ops x1205_rtc_ops = {
	.proc		= x1205_rtc_proc,
	.read_time	= x1205_rtc_read_time,
	.set_time	= x1205_rtc_set_time,
	.read_alarm	= x1205_rtc_read_alarm,
	.set_alarm	= x1205_rtc_set_alarm,
};

static ssize_t x1205_sysfs_show_atrim(struct device *dev,
				struct device_attribute *attr, char *buf)
{
	int err, atrim;

	err = x1205_get_atrim(to_i2c_client(dev), &atrim);
	if (err)
		return err;

	return sprintf(buf, "%d.%02d pF\n", atrim / 1000, atrim % 1000);
}
static DEVICE_ATTR(atrim, S_IRUGO, x1205_sysfs_show_atrim, NULL);

static ssize_t x1205_sysfs_show_dtrim(struct device *dev,
				struct device_attribute *attr, char *buf)
{
	int err, dtrim;

	err = x1205_get_dtrim(to_i2c_client(dev), &dtrim);
	if (err)
		return err;

	return sprintf(buf, "%d ppm\n", dtrim);
}
static DEVICE_ATTR(dtrim, S_IRUGO, x1205_sysfs_show_dtrim, NULL);

static int x1205_sysfs_register(struct device *dev)
{
	int err;

	err = device_create_file(dev, &dev_attr_atrim);
	if (err)
		return err;

	err = device_create_file(dev, &dev_attr_dtrim);
	if (err)
		device_remove_file(dev, &dev_attr_atrim);

	return err;
}

static void x1205_sysfs_unregister(struct device *dev)
{
	device_remove_file(dev, &dev_attr_atrim);
	device_remove_file(dev, &dev_attr_dtrim);
}


static int x1205_probe(struct i2c_client *client,
			const struct i2c_device_id *id)
{
	int err = 0;
	unsigned char sr;
	struct rtc_device *rtc;

	dev_dbg(&client->dev, "%s\n", __func__);

	if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
		return -ENODEV;

	if (x1205_validate_client(client) < 0)
		return -ENODEV;

	dev_info(&client->dev, "chip found, driver version " DRV_VERSION "\n");

	rtc = rtc_device_register(x1205_driver.driver.name, &client->dev,
				&x1205_rtc_ops, THIS_MODULE);

	if (IS_ERR(rtc))
		return PTR_ERR(rtc);

	i2c_set_clientdata(client, rtc);

	/* Check for power failures and eventualy enable the osc */
	if ((err = x1205_get_status(client, &sr)) == 0) {
		if (sr & X1205_SR_RTCF) {
			dev_err(&client->dev,
				"power failure detected, "
				"please set the clock\n");
			udelay(50);
			x1205_fix_osc(client);
		}
	}
	else
		dev_err(&client->dev, "couldn't read status\n");

	err = x1205_sysfs_register(&client->dev);
	if (err)
		goto exit_devreg;

	return 0;

exit_devreg:
	rtc_device_unregister(rtc);

	return err;
}

static int x1205_remove(struct i2c_client *client)
{
	struct rtc_device *rtc = i2c_get_clientdata(client);

	rtc_device_unregister(rtc);
	x1205_sysfs_unregister(&client->dev);
	return 0;
}

static const struct i2c_device_id x1205_id[] = {
	{ "x1205", 0 },
	{ }
};
MODULE_DEVICE_TABLE(i2c, x1205_id);

static struct i2c_driver x1205_driver = {
	.driver		= {
		.name	= "rtc-x1205",
	},
	.probe		= x1205_probe,
	.remove		= x1205_remove,
	.id_table	= x1205_id,
};

static int __init x1205_init(void)
{
	return i2c_add_driver(&x1205_driver);
}

static void __exit x1205_exit(void)
{
	i2c_del_driver(&x1205_driver);
}

MODULE_AUTHOR(
	"Karen Spearel <kas111 at gmail dot com>, "
	"Alessandro Zummo <a.zummo@towertech.it>");
MODULE_DESCRIPTION("Xicor/Intersil X1205 RTC driver");
MODULE_LICENSE("GPL");
MODULE_VERSION(DRV_VERSION);

module_init(x1205_init);
module_exit(x1205_exit);
Commit	Line	Data
1fec7c66 AZ	1	/*
	2	* An i2c driver for the Xicor/Intersil X1205 RTC
	3	* Copyright 2004 Karen Spearel
	4	* Copyright 2005 Alessandro Zummo
	5	*
	6	* please send all reports to:
	7	* Karen Spearel <kas111 at gmail dot com>
	8	* Alessandro Zummo <a.zummo@towertech.it>
	9	*
	10	* based on a lot of other RTC drivers.
	11	*
890e0375 JD	12	* Information and datasheet:
	13	* http://www.intersil.com/cda/deviceinfo/0,1477,X1205,00.html
	14	*
1fec7c66 AZ	15	* This program is free software; you can redistribute it and/or modify
	16	* it under the terms of the GNU General Public License version 2 as
	17	* published by the Free Software Foundation.
	18	*/
	19
	20	#include <linux/i2c.h>
	21	#include <linux/bcd.h>
	22	#include <linux/rtc.h>
	23	#include <linux/delay.h>
	24
4edac2b4	25	#define DRV_VERSION "1.0.8"
1fec7c66 AZ	26
	27	/* offsets into CCR area */
	28
	29	#define CCR_SEC 0
	30	#define CCR_MIN 1
	31	#define CCR_HOUR 2
	32	#define CCR_MDAY 3
	33	#define CCR_MONTH 4
	34	#define CCR_YEAR 5
	35	#define CCR_WDAY 6
	36	#define CCR_Y2K 7
	37
	38	#define X1205_REG_SR 0x3F /* status register */
	39	#define X1205_REG_Y2K 0x37
	40	#define X1205_REG_DW 0x36
	41	#define X1205_REG_YR 0x35
	42	#define X1205_REG_MO 0x34
	43	#define X1205_REG_DT 0x33
	44	#define X1205_REG_HR 0x32
	45	#define X1205_REG_MN 0x31
	46	#define X1205_REG_SC 0x30
	47	#define X1205_REG_DTR 0x13
	48	#define X1205_REG_ATR 0x12
	49	#define X1205_REG_INT 0x11
	50	#define X1205_REG_0 0x10
	51	#define X1205_REG_Y2K1 0x0F
	52	#define X1205_REG_DWA1 0x0E
	53	#define X1205_REG_YRA1 0x0D
	54	#define X1205_REG_MOA1 0x0C
	55	#define X1205_REG_DTA1 0x0B
	56	#define X1205_REG_HRA1 0x0A
	57	#define X1205_REG_MNA1 0x09
	58	#define X1205_REG_SCA1 0x08
	59	#define X1205_REG_Y2K0 0x07
	60	#define X1205_REG_DWA0 0x06
	61	#define X1205_REG_YRA0 0x05
	62	#define X1205_REG_MOA0 0x04
	63	#define X1205_REG_DTA0 0x03
	64	#define X1205_REG_HRA0 0x02
	65	#define X1205_REG_MNA0 0x01
	66	#define X1205_REG_SCA0 0x00
	67
	68	#define X1205_CCR_BASE 0x30 /* Base address of CCR */
	69	#define X1205_ALM0_BASE 0x00 /* Base address of ALARM0 */
	70
	71	#define X1205_SR_RTCF 0x01 /* Clock failure */
	72	#define X1205_SR_WEL 0x02 /* Write Enable Latch */
	73	#define X1205_SR_RWEL 0x04 /* Register Write Enable */
471d47e3	74	#define X1205_SR_AL0 0x20 /* Alarm 0 match */
1fec7c66 AZ	75
	76	#define X1205_DTR_DTR0 0x01
	77	#define X1205_DTR_DTR1 0x02
	78	#define X1205_DTR_DTR2 0x04
	79
	80	#define X1205_HR_MIL 0x80 /* Set in ccr.hour for 24 hr mode */
	81
471d47e3 MH	82	#define X1205_INT_AL0E 0x20 /* Alarm 0 enable */
471d47e3 MH	83
4edac2b4	84	static struct i2c_driver x1205_driver;
1fec7c66 AZ	85
	86	/*
	87	* In the routines that deal directly with the x1205 hardware, we use
	88	* rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch
	89	* Epoch is initialized as 2000. Time is set to UTC.
	90	*/
	91	static int x1205_get_datetime(struct i2c_client client, struct rtc_time tm,
	92	unsigned char reg_base)
	93	{
	94	unsigned char dt_addr[2] = { 0, reg_base };
1fec7c66	95	unsigned char buf[8];
471d47e3	96	int i;
1fec7c66 AZ	97
	98	struct i2c_msg msgs[] = {
	99	{ client->addr, 0, 2, dt_addr }, /* setup read ptr */
	100	{ client->addr, I2C_M_RD, 8, buf }, /* read date */
	101	};
	102
	103	/* read date registers */
471d47e3	104	if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) {
2a4e2b87	105	dev_err(&client->dev, "%s: read error\n", __func__);
1fec7c66 AZ	106	return -EIO;
	107	}
	108
	109	dev_dbg(&client->dev,
	110	"%s: raw read data - sec=%02x, min=%02x, hr=%02x, "
	111	"mday=%02x, mon=%02x, year=%02x, wday=%02x, y2k=%02x\n",
2a4e2b87	112	__func__,
1fec7c66 AZ	113	buf[0], buf[1], buf[2], buf[3],
	114	buf[4], buf[5], buf[6], buf[7]);
	115
471d47e3 MH	116	/* Mask out the enable bits if these are alarm registers */
	117	if (reg_base < X1205_CCR_BASE)
	118	for (i = 0; i <= 4; i++)
	119	buf[i] &= 0x7F;
	120
1fec7c66 AZ	121	tm->tm_sec = BCD2BIN(buf[CCR_SEC]);
	122	tm->tm_min = BCD2BIN(buf[CCR_MIN]);
	123	tm->tm_hour = BCD2BIN(buf[CCR_HOUR] & 0x3F); /* hr is 0-23 */
	124	tm->tm_mday = BCD2BIN(buf[CCR_MDAY]);
	125	tm->tm_mon = BCD2BIN(buf[CCR_MONTH]) - 1; /* mon is 0-11 */
	126	tm->tm_year = BCD2BIN(buf[CCR_YEAR])
	127	+ (BCD2BIN(buf[CCR_Y2K]) * 100) - 1900;
	128	tm->tm_wday = buf[CCR_WDAY];
	129
	130	dev_dbg(&client->dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
	131	"mday=%d, mon=%d, year=%d, wday=%d\n",
2a4e2b87	132	__func__,
1fec7c66 AZ	133	tm->tm_sec, tm->tm_min, tm->tm_hour,
	134	tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
	135
	136	return 0;
	137	}
	138
	139	static int x1205_get_status(struct i2c_client client, unsigned char sr)
	140	{
	141	static unsigned char sr_addr[2] = { 0, X1205_REG_SR };
	142
	143	struct i2c_msg msgs[] = {
	144	{ client->addr, 0, 2, sr_addr }, /* setup read ptr */
	145	{ client->addr, I2C_M_RD, 1, sr }, /* read status */
	146	};
	147
	148	/* read status register */
471d47e3	149	if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) {
2a4e2b87	150	dev_err(&client->dev, "%s: read error\n", __func__);
1fec7c66 AZ	151	return -EIO;
	152	}
	153
	154	return 0;
	155	}
	156
	157	static int x1205_set_datetime(struct i2c_client client, struct rtc_time tm,
471d47e3	158	int datetoo, u8 reg_base, unsigned char alm_enable)
1fec7c66	159	{
471d47e3	160	int i, xfer, nbytes;
1fec7c66	161	unsigned char buf[8];
471d47e3	162	unsigned char rdata[10] = { 0, reg_base };
1fec7c66 AZ	163
	164	static const unsigned char wel[3] = { 0, X1205_REG_SR,
	165	X1205_SR_WEL };
	166
	167	static const unsigned char rwel[3] = { 0, X1205_REG_SR,
	168	X1205_SR_WEL \| X1205_SR_RWEL };
	169
	170	static const unsigned char diswe[3] = { 0, X1205_REG_SR, 0 };
	171
	172	dev_dbg(&client->dev,
	173	"%s: secs=%d, mins=%d, hours=%d\n",
2a4e2b87	174	__func__,
1fec7c66 AZ	175	tm->tm_sec, tm->tm_min, tm->tm_hour);
	176
	177	buf[CCR_SEC] = BIN2BCD(tm->tm_sec);
	178	buf[CCR_MIN] = BIN2BCD(tm->tm_min);
	179
	180	/* set hour and 24hr bit */
	181	buf[CCR_HOUR] = BIN2BCD(tm->tm_hour) \| X1205_HR_MIL;
	182
	183	/* should we also set the date? */
	184	if (datetoo) {
	185	dev_dbg(&client->dev,
	186	"%s: mday=%d, mon=%d, year=%d, wday=%d\n",
2a4e2b87	187	__func__,
1fec7c66 AZ	188	tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
	189
	190	buf[CCR_MDAY] = BIN2BCD(tm->tm_mday);
	191
	192	/* month, 1 - 12 */
	193	buf[CCR_MONTH] = BIN2BCD(tm->tm_mon + 1);
	194
	195	/* year, since the rtc epoch*/
	196	buf[CCR_YEAR] = BIN2BCD(tm->tm_year % 100);
	197	buf[CCR_WDAY] = tm->tm_wday & 0x07;
	198	buf[CCR_Y2K] = BIN2BCD(tm->tm_year / 100);
	199	}
	200
471d47e3 MH	201	/* If writing alarm registers, set compare bits on registers 0-4 */
	202	if (reg_base < X1205_CCR_BASE)
	203	for (i = 0; i <= 4; i++)
	204	buf[i] \|= 0x80;
	205
1fec7c66 AZ	206	/* this sequence is required to unlock the chip */
1fec7c66 AZ	207	if ((xfer = i2c_master_send(client, wel, 3)) != 3) {
2a4e2b87	208	dev_err(&client->dev, "%s: wel - %d\n", __func__, xfer);
1fec7c66 AZ	209	return -EIO;
	210	}
	211
	212	if ((xfer = i2c_master_send(client, rwel, 3)) != 3) {
2a4e2b87	213	dev_err(&client->dev, "%s: rwel - %d\n", __func__, xfer);
1fec7c66 AZ	214	return -EIO;
	215	}
	216
471d47e3	217
1fec7c66	218	/* write register's data */
471d47e3 MH	219	if (datetoo)
	220	nbytes = 8;
	221	else
	222	nbytes = 3;
	223	for (i = 0; i < nbytes; i++)
	224	rdata[2+i] = buf[i];
	225
	226	xfer = i2c_master_send(client, rdata, nbytes+2);
	227	if (xfer != nbytes+2) {
	228	dev_err(&client->dev,
	229	"%s: result=%d addr=%02x, data=%02x\n",
	230	__func__,
	231	xfer, rdata[1], rdata[2]);
	232	return -EIO;
	233	}
	234
	235	/* If we wrote to the nonvolatile region, wait 10msec for write cycle*/
	236	if (reg_base < X1205_CCR_BASE) {
	237	unsigned char al0e[3] = { 0, X1205_REG_INT, 0 };
	238
	239	msleep(10);
	240
	241	/* ...and set or clear the AL0E bit in the INT register */
1fec7c66	242
471d47e3 MH	243	/* Need to set RWEL again as the write has cleared it */
471d47e3 MH	244	xfer = i2c_master_send(client, rwel, 3);
1fec7c66 AZ	245	if (xfer != 3) {
1fec7c66 AZ	246	dev_err(&client->dev,
471d47e3	247	"%s: aloe rwel - %d\n",
2a4e2b87	248	__func__,
471d47e3 MH	249	xfer);
	250	return -EIO;
	251	}
	252
	253	if (alm_enable)
	254	al0e[2] = X1205_INT_AL0E;
	255
	256	xfer = i2c_master_send(client, al0e, 3);
	257	if (xfer != 3) {
	258	dev_err(&client->dev,
	259	"%s: al0e - %d\n",
	260	__func__,
	261	xfer);
1fec7c66 AZ	262	return -EIO;
1fec7c66 AZ	263	}
471d47e3 MH	264
	265	/* and wait 10msec again for this write to complete */
	266	msleep(10);
	267	}
1fec7c66 AZ	268
	269	/* disable further writes */
	270	if ((xfer = i2c_master_send(client, diswe, 3)) != 3) {
2a4e2b87	271	dev_err(&client->dev, "%s: diswe - %d\n", __func__, xfer);
1fec7c66 AZ	272	return -EIO;
	273	}
	274
	275	return 0;
	276	}
	277
	278	static int x1205_fix_osc(struct i2c_client *client)
	279	{
	280	int err;
	281	struct rtc_time tm;
	282
	283	tm.tm_hour = tm.tm_min = tm.tm_sec = 0;
	284
471d47e3 MH	285	err = x1205_set_datetime(client, &tm, 0, X1205_CCR_BASE, 0);
	286	if (err < 0)
	287	dev_err(&client->dev, "unable to restart the oscillator\n");
1fec7c66 AZ	288
	289	return err;
	290	}
	291
	292	static int x1205_get_dtrim(struct i2c_client client, int trim)
	293	{
	294	unsigned char dtr;
	295	static unsigned char dtr_addr[2] = { 0, X1205_REG_DTR };
	296
	297	struct i2c_msg msgs[] = {
	298	{ client->addr, 0, 2, dtr_addr }, /* setup read ptr */
	299	{ client->addr, I2C_M_RD, 1, &dtr }, /* read dtr */
	300	};
	301
	302	/* read dtr register */
471d47e3	303	if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) {
2a4e2b87	304	dev_err(&client->dev, "%s: read error\n", __func__);
1fec7c66 AZ	305	return -EIO;
	306	}
	307
2a4e2b87	308	dev_dbg(&client->dev, "%s: raw dtr=%x\n", __func__, dtr);
1fec7c66 AZ	309
	310	*trim = 0;
	311
	312	if (dtr & X1205_DTR_DTR0)
	313	*trim += 20;
	314
	315	if (dtr & X1205_DTR_DTR1)
	316	*trim += 10;
	317
	318	if (dtr & X1205_DTR_DTR2)
	319	trim = -trim;
	320
	321	return 0;
	322	}
	323
	324	static int x1205_get_atrim(struct i2c_client client, int trim)
	325	{
	326	s8 atr;
	327	static unsigned char atr_addr[2] = { 0, X1205_REG_ATR };
	328
	329	struct i2c_msg msgs[] = {
	330	{ client->addr, 0, 2, atr_addr }, /* setup read ptr */
	331	{ client->addr, I2C_M_RD, 1, &atr }, /* read atr */
	332	};
	333
	334	/* read atr register */
471d47e3	335	if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) {
2a4e2b87	336	dev_err(&client->dev, "%s: read error\n", __func__);
1fec7c66 AZ	337	return -EIO;
	338	}
	339
2a4e2b87	340	dev_dbg(&client->dev, "%s: raw atr=%x\n", __func__, atr);
1fec7c66 AZ	341
	342	/* atr is a two's complement value on 6 bits,
	343	* perform sign extension. The formula is
	344	* Catr = (atr * 0.25pF) + 11.00pF.
	345	*/
	346	if (atr & 0x20)
	347	atr \|= 0xC0;
	348
2a4e2b87	349	dev_dbg(&client->dev, "%s: raw atr=%x (%d)\n", __func__, atr, atr);
1fec7c66 AZ	350
	351	trim = (atr 250) + 11000;
	352
2a4e2b87	353	dev_dbg(&client->dev, "%s: real=%d\n", __func__, *trim);
1fec7c66 AZ	354
	355	return 0;
	356	}
	357
	358	struct x1205_limit
	359	{
	360	unsigned char reg, mask, min, max;
	361	};
	362
	363	static int x1205_validate_client(struct i2c_client *client)
	364	{
	365	int i, xfer;
	366
	367	/* Probe array. We will read the register at the specified
	368	* address and check if the given bits are zero.
	369	*/
	370	static const unsigned char probe_zero_pattern[] = {
	371	/* register, mask */
	372	X1205_REG_SR, 0x18,
	373	X1205_REG_DTR, 0xF8,
	374	X1205_REG_ATR, 0xC0,
	375	X1205_REG_INT, 0x18,
	376	X1205_REG_0, 0xFF,
	377	};
	378
	379	static const struct x1205_limit probe_limits_pattern[] = {
	380	/* register, mask, min, max */
	381	{ X1205_REG_Y2K, 0xFF, 19, 20 },
	382	{ X1205_REG_DW, 0xFF, 0, 6 },
	383	{ X1205_REG_YR, 0xFF, 0, 99 },
	384	{ X1205_REG_MO, 0xFF, 0, 12 },
	385	{ X1205_REG_DT, 0xFF, 0, 31 },
	386	{ X1205_REG_HR, 0x7F, 0, 23 },
	387	{ X1205_REG_MN, 0xFF, 0, 59 },
	388	{ X1205_REG_SC, 0xFF, 0, 59 },
	389	{ X1205_REG_Y2K1, 0xFF, 19, 20 },
	390	{ X1205_REG_Y2K0, 0xFF, 19, 20 },
	391	};
	392
	393	/* check that registers have bits a 0 where expected */
	394	for (i = 0; i < ARRAY_SIZE(probe_zero_pattern); i += 2) {
	395	unsigned char buf;
	396
	397	unsigned char addr[2] = { 0, probe_zero_pattern[i] };
	398
	399	struct i2c_msg msgs[2] = {
	400	{ client->addr, 0, 2, addr },
	401	{ client->addr, I2C_M_RD, 1, &buf },
	402	};
	403
	404	if ((xfer = i2c_transfer(client->adapter, msgs, 2)) != 2) {
a14e1893	405	dev_err(&client->dev,
1fec7c66	406	"%s: could not read register %x\n",
2a4e2b87	407	__func__, probe_zero_pattern[i]);
1fec7c66 AZ	408
	409	return -EIO;
	410	}
	411
	412	if ((buf & probe_zero_pattern[i+1]) != 0) {
a14e1893	413	dev_err(&client->dev,
1fec7c66	414	"%s: register=%02x, zero pattern=%d, value=%x\n",
2a4e2b87	415	__func__, probe_zero_pattern[i], i, buf);
1fec7c66 AZ	416
	417	return -ENODEV;
	418	}
	419	}
	420
	421	/* check limits (only registers with bcd values) */
	422	for (i = 0; i < ARRAY_SIZE(probe_limits_pattern); i++) {
	423	unsigned char reg, value;
	424
	425	unsigned char addr[2] = { 0, probe_limits_pattern[i].reg };
	426
	427	struct i2c_msg msgs[2] = {
	428	{ client->addr, 0, 2, addr },
	429	{ client->addr, I2C_M_RD, 1, &reg },
	430	};
	431
	432	if ((xfer = i2c_transfer(client->adapter, msgs, 2)) != 2) {
a14e1893	433	dev_err(&client->dev,
1fec7c66	434	"%s: could not read register %x\n",
2a4e2b87	435	__func__, probe_limits_pattern[i].reg);
1fec7c66 AZ	436
	437	return -EIO;
	438	}
	439
	440	value = BCD2BIN(reg & probe_limits_pattern[i].mask);
	441
	442	if (value > probe_limits_pattern[i].max \|\|
	443	value < probe_limits_pattern[i].min) {
a14e1893	444	dev_dbg(&client->dev,
1fec7c66	445	"%s: register=%x, lim pattern=%d, value=%d\n",
2a4e2b87	446	__func__, probe_limits_pattern[i].reg,
1fec7c66 AZ	447	i, value);
	448
	449	return -ENODEV;
	450	}
	451	}
	452
	453	return 0;
	454	}
	455
	456	static int x1205_rtc_read_alarm(struct device dev, struct rtc_wkalrm alrm)
	457	{
471d47e3 MH	458	int err;
	459	unsigned char intreg, status;
	460	static unsigned char int_addr[2] = { 0, X1205_REG_INT };
	461	struct i2c_client *client = to_i2c_client(dev);
	462	struct i2c_msg msgs[] = {
	463	{ client->addr, 0, 2, int_addr }, /* setup read ptr */
	464	{ client->addr, I2C_M_RD, 1, &intreg }, /* read INT register */
	465	};
	466
	467	/* read interrupt register and status register */
	468	if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) {
	469	dev_err(&client->dev, "%s: read error\n", __func__);
	470	return -EIO;
	471	}
	472	err = x1205_get_status(client, &status);
	473	if (err == 0) {
	474	alrm->pending = (status & X1205_SR_AL0) ? 1 : 0;
	475	alrm->enabled = (intreg & X1205_INT_AL0E) ? 1 : 0;
	476	err = x1205_get_datetime(client, &alrm->time, X1205_ALM0_BASE);
	477	}
	478	return err;
1fec7c66 AZ	479	}
	480
	481	static int x1205_rtc_set_alarm(struct device dev, struct rtc_wkalrm alrm)
	482	{
	483	return x1205_set_datetime(to_i2c_client(dev),
471d47e3	484	&alrm->time, 1, X1205_ALM0_BASE, alrm->enabled);
1fec7c66 AZ	485	}
	486
	487	static int x1205_rtc_read_time(struct device dev, struct rtc_time tm)
	488	{
	489	return x1205_get_datetime(to_i2c_client(dev),
	490	tm, X1205_CCR_BASE);
	491	}
	492
	493	static int x1205_rtc_set_time(struct device dev, struct rtc_time tm)
	494	{
	495	return x1205_set_datetime(to_i2c_client(dev),
471d47e3	496	tm, 1, X1205_CCR_BASE, 0);
1fec7c66 AZ	497	}
	498
	499	static int x1205_rtc_proc(struct device dev, struct seq_file seq)
	500	{
	501	int err, dtrim, atrim;
	502
1fec7c66 AZ	503	if ((err = x1205_get_dtrim(to_i2c_client(dev), &dtrim)) == 0)
	504	seq_printf(seq, "digital_trim\t: %d ppm\n", dtrim);
	505
	506	if ((err = x1205_get_atrim(to_i2c_client(dev), &atrim)) == 0)
	507	seq_printf(seq, "analog_trim\t: %d.%02d pF\n",
	508	atrim / 1000, atrim % 1000);
	509	return 0;
	510	}
	511
ff8371ac	512	static const struct rtc_class_ops x1205_rtc_ops = {
1fec7c66 AZ	513	.proc = x1205_rtc_proc,
	514	.read_time = x1205_rtc_read_time,
	515	.set_time = x1205_rtc_set_time,
	516	.read_alarm = x1205_rtc_read_alarm,
	517	.set_alarm = x1205_rtc_set_alarm,
	518	};
	519
	520	static ssize_t x1205_sysfs_show_atrim(struct device *dev,
	521	struct device_attribute attr, char buf)
	522	{
015aefbb	523	int err, atrim;
1fec7c66	524
015aefbb AZ	525	err = x1205_get_atrim(to_i2c_client(dev), &atrim);
	526	if (err)
	527	return err;
	528
	529	return sprintf(buf, "%d.%02d pF\n", atrim / 1000, atrim % 1000);
1fec7c66 AZ	530	}
	531	static DEVICE_ATTR(atrim, S_IRUGO, x1205_sysfs_show_atrim, NULL);
	532
	533	static ssize_t x1205_sysfs_show_dtrim(struct device *dev,
	534	struct device_attribute attr, char buf)
	535	{
015aefbb	536	int err, dtrim;
1fec7c66	537
015aefbb AZ	538	err = x1205_get_dtrim(to_i2c_client(dev), &dtrim);
	539	if (err)
	540	return err;
1fec7c66	541
015aefbb	542	return sprintf(buf, "%d ppm\n", dtrim);
1fec7c66 AZ	543	}
	544	static DEVICE_ATTR(dtrim, S_IRUGO, x1205_sysfs_show_dtrim, NULL);
	545
4edac2b4 AZ	546	static int x1205_sysfs_register(struct device *dev)
	547	{
	548	int err;
	549
	550	err = device_create_file(dev, &dev_attr_atrim);
	551	if (err)
	552	return err;
	553
	554	err = device_create_file(dev, &dev_attr_dtrim);
	555	if (err)
	556	device_remove_file(dev, &dev_attr_atrim);
	557
	558	return err;
	559	}
	560
	561	static void x1205_sysfs_unregister(struct device *dev)
1fec7c66	562	{
4edac2b4 AZ	563	device_remove_file(dev, &dev_attr_atrim);
4edac2b4 AZ	564	device_remove_file(dev, &dev_attr_dtrim);
1fec7c66 AZ	565	}
1fec7c66 AZ	566
4edac2b4	567
d2653e92 JD	568	static int x1205_probe(struct i2c_client *client,
d2653e92 JD	569	const struct i2c_device_id *id)
1fec7c66 AZ	570	{
	571	int err = 0;
	572	unsigned char sr;
1fec7c66 AZ	573	struct rtc_device *rtc;
1fec7c66 AZ	574
4edac2b4	575	dev_dbg(&client->dev, "%s\n", __func__);
1fec7c66	576
4edac2b4 AZ	577	if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
4edac2b4 AZ	578	return -ENODEV;
1fec7c66	579
4edac2b4 AZ	580	if (x1205_validate_client(client) < 0)
4edac2b4 AZ	581	return -ENODEV;
1fec7c66 AZ	582
	583	dev_info(&client->dev, "chip found, driver version " DRV_VERSION "\n");
	584
	585	rtc = rtc_device_register(x1205_driver.driver.name, &client->dev,
	586	&x1205_rtc_ops, THIS_MODULE);
	587
4edac2b4 AZ	588	if (IS_ERR(rtc))
4edac2b4 AZ	589	return PTR_ERR(rtc);
1fec7c66 AZ	590
	591	i2c_set_clientdata(client, rtc);
	592
	593	/* Check for power failures and eventualy enable the osc */
	594	if ((err = x1205_get_status(client, &sr)) == 0) {
	595	if (sr & X1205_SR_RTCF) {
	596	dev_err(&client->dev,
	597	"power failure detected, "
	598	"please set the clock\n");
	599	udelay(50);
	600	x1205_fix_osc(client);
	601	}
	602	}
	603	else
	604	dev_err(&client->dev, "couldn't read status\n");
	605
4edac2b4 AZ	606	err = x1205_sysfs_register(&client->dev);
	607	if (err)
	608	goto exit_devreg;
1fec7c66 AZ	609
	610	return 0;
	611
91046a8a JG	612	exit_devreg:
	613	rtc_device_unregister(rtc);
	614
1fec7c66 AZ	615	return err;
	616	}
	617
4edac2b4	618	static int x1205_remove(struct i2c_client *client)
1fec7c66	619	{
1fec7c66 AZ	620	struct rtc_device *rtc = i2c_get_clientdata(client);
1fec7c66 AZ	621
4edac2b4 AZ	622	rtc_device_unregister(rtc);
4edac2b4 AZ	623	x1205_sysfs_unregister(&client->dev);
1fec7c66 AZ	624	return 0;
	625	}
	626
3760f736 JD	627	static const struct i2c_device_id x1205_id[] = {
	628	{ "x1205", 0 },
	629	{ }
	630	};
	631	MODULE_DEVICE_TABLE(i2c, x1205_id);
	632
4edac2b4 AZ	633	static struct i2c_driver x1205_driver = {
	634	.driver = {
	635	.name = "rtc-x1205",
	636	},
	637	.probe = x1205_probe,
	638	.remove = x1205_remove,
3760f736	639	.id_table = x1205_id,
4edac2b4 AZ	640	};
4edac2b4 AZ	641
1fec7c66 AZ	642	static int __init x1205_init(void)
	643	{
	644	return i2c_add_driver(&x1205_driver);
	645	}
	646
	647	static void __exit x1205_exit(void)
	648	{
	649	i2c_del_driver(&x1205_driver);
	650	}
	651
	652	MODULE_AUTHOR(
	653	"Karen Spearel <kas111 at gmail dot com>, "
	654	"Alessandro Zummo <a.zummo@towertech.it>");
	655	MODULE_DESCRIPTION("Xicor/Intersil X1205 RTC driver");
	656	MODULE_LICENSE("GPL");
	657	MODULE_VERSION(DRV_VERSION);
	658
	659	module_init(x1205_init);
	660	module_exit(x1205_exit);