[deliverable/linux.git] / drivers / s390 / cio / ioasm.h

#ifndef S390_CIO_IOASM_H
#define S390_CIO_IOASM_H

#include <asm/chpid.h>
#include <asm/schid.h>

/*
 * TPI info structure
 */
struct tpi_info {
	struct subchannel_id schid;
	__u32 intparm;		 /* interruption parameter */
	__u32 adapter_IO : 1;
	__u32 reserved2	 : 1;
	__u32 isc	 : 3;
	__u32 reserved3	 : 12;
	__u32 int_type	 : 3;
	__u32 reserved4	 : 12;
} __attribute__ ((packed));


/*
 * Some S390 specific IO instructions as inline
 */

static inline int stsch(struct subchannel_id schid, struct schib *addr)
{
	register struct subchannel_id reg1 asm ("1") = schid;
	int ccode;

	asm volatile(
		"	stsch	0(%3)\n"
		"	ipm	%0\n"
		"	srl	%0,28"
		: "=d" (ccode), "=m" (*addr)
		: "d" (reg1), "a" (addr)
		: "cc");
	return ccode;
}

static inline int stsch_err(struct subchannel_id schid, struct schib *addr)
{
	register struct subchannel_id reg1 asm ("1") = schid;
	int ccode = -EIO;

	asm volatile(
		"	stsch	0(%3)\n"
		"0:	ipm	%0\n"
		"	srl	%0,28\n"
		"1:\n"
		EX_TABLE(0b,1b)
		: "+d" (ccode), "=m" (*addr)
		: "d" (reg1), "a" (addr)
		: "cc");
	return ccode;
}

static inline int msch(struct subchannel_id schid, struct schib *addr)
{
	register struct subchannel_id reg1 asm ("1") = schid;
	int ccode;

	asm volatile(
		"	msch	0(%2)\n"
		"	ipm	%0\n"
		"	srl	%0,28"
		: "=d" (ccode)
		: "d" (reg1), "a" (addr), "m" (*addr)
		: "cc");
	return ccode;
}

static inline int msch_err(struct subchannel_id schid, struct schib *addr)
{
	register struct subchannel_id reg1 asm ("1") = schid;
	int ccode = -EIO;

	asm volatile(
		"	msch	0(%2)\n"
		"0:	ipm	%0\n"
		"	srl	%0,28\n"
		"1:\n"
		EX_TABLE(0b,1b)
		: "+d" (ccode)
		: "d" (reg1), "a" (addr), "m" (*addr)
		: "cc");
	return ccode;
}

static inline int tsch(struct subchannel_id schid, struct irb *addr)
{
	register struct subchannel_id reg1 asm ("1") = schid;
	int ccode;

	asm volatile(
		"	tsch	0(%3)\n"
		"	ipm	%0\n"
		"	srl	%0,28"
		: "=d" (ccode), "=m" (*addr)
		: "d" (reg1), "a" (addr)
		: "cc");
	return ccode;
}

static inline int tpi(struct tpi_info *addr)
{
	int ccode;

	asm volatile(
		"	tpi	0(%2)\n"
		"	ipm	%0\n"
		"	srl	%0,28"
		: "=d" (ccode), "=m" (*addr)
		: "a" (addr)
		: "cc");
	return ccode;
}

static inline int chsc(void *chsc_area)
{
	typedef struct { char _[4096]; } addr_type;
	int cc;

	asm volatile(
		"	.insn	rre,0xb25f0000,%2,0\n"
		"	ipm	%0\n"
		"	srl	%0,28\n"
		: "=d" (cc), "=m" (*(addr_type *) chsc_area)
		: "d" (chsc_area), "m" (*(addr_type *) chsc_area)
		: "cc");
	return cc;
}

static inline int rchp(struct chp_id chpid)
{
	register struct chp_id reg1 asm ("1") = chpid;
	int ccode;

	asm volatile(
		"	lr	1,%1\n"
		"	rchp\n"
		"	ipm	%0\n"
		"	srl	%0,28"
		: "=d" (ccode) : "d" (reg1) : "cc");
	return ccode;
}

#endif
Commit	Line	Data
1da177e4 LT	1	#ifndef S390_CIO_IOASM_H
	2	#define S390_CIO_IOASM_H
	3
e5854a58	4	#include <asm/chpid.h>
9d92a7e1	5	#include <asm/schid.h>
a8237fc4	6
1da177e4 LT	7	/*
	8	* TPI info structure
	9	*/
	10	struct tpi_info {
a8237fc4	11	struct subchannel_id schid;
1da177e4 LT	12	__u32 intparm; /* interruption parameter */
	13	__u32 adapter_IO : 1;
	14	__u32 reserved2 : 1;
	15	__u32 isc : 3;
	16	__u32 reserved3 : 12;
	17	__u32 int_type : 3;
	18	__u32 reserved4 : 12;
	19	} __attribute__ ((packed));
	20
	21
	22	/*
	23	* Some S390 specific IO instructions as inline
	24	*/
	25
f9c9fe3e	26	static inline int stsch(struct subchannel_id schid, struct schib *addr)
1da177e4	27	{
94c12cc7	28	register struct subchannel_id reg1 asm ("1") = schid;
1da177e4 LT	29	int ccode;
1da177e4 LT	30
94c12cc7	31	asm volatile(
f9c9fe3e	32	" stsch 0(%3)\n"
94c12cc7 MS	33	" ipm %0\n"
94c12cc7 MS	34	" srl %0,28"
f9c9fe3e PO	35	: "=d" (ccode), "=m" (*addr)
	36	: "d" (reg1), "a" (addr)
	37	: "cc");
1da177e4 LT	38	return ccode;
	39	}
	40
f9c9fe3e	41	static inline int stsch_err(struct subchannel_id schid, struct schib *addr)
fb6958a5	42	{
94c12cc7 MS	43	register struct subchannel_id reg1 asm ("1") = schid;
94c12cc7 MS	44	int ccode = -EIO;
fb6958a5	45
94c12cc7	46	asm volatile(
f9c9fe3e	47	" stsch 0(%3)\n"
94c12cc7 MS	48	"0: ipm %0\n"
94c12cc7 MS	49	" srl %0,28\n"
fb6958a5	50	"1:\n"
94c12cc7	51	EX_TABLE(0b,1b)
f9c9fe3e PO	52	: "+d" (ccode), "=m" (*addr)
	53	: "d" (reg1), "a" (addr)
	54	: "cc");
fb6958a5 CH	55	return ccode;
	56	}
	57
f9c9fe3e	58	static inline int msch(struct subchannel_id schid, struct schib *addr)
1da177e4	59	{
94c12cc7	60	register struct subchannel_id reg1 asm ("1") = schid;
1da177e4 LT	61	int ccode;
1da177e4 LT	62
94c12cc7 MS	63	asm volatile(
	64	" msch 0(%2)\n"
	65	" ipm %0\n"
	66	" srl %0,28"
f9c9fe3e PO	67	: "=d" (ccode)
	68	: "d" (reg1), "a" (addr), "m" (*addr)
	69	: "cc");
1da177e4 LT	70	return ccode;
	71	}
	72
f9c9fe3e	73	static inline int msch_err(struct subchannel_id schid, struct schib *addr)
1da177e4	74	{
94c12cc7 MS	75	register struct subchannel_id reg1 asm ("1") = schid;
94c12cc7 MS	76	int ccode = -EIO;
1da177e4	77
94c12cc7 MS	78	asm volatile(
	79	" msch 0(%2)\n"
	80	"0: ipm %0\n"
	81	" srl %0,28\n"
1da177e4	82	"1:\n"
94c12cc7	83	EX_TABLE(0b,1b)
f9c9fe3e PO	84	: "+d" (ccode)
	85	: "d" (reg1), "a" (addr), "m" (*addr)
	86	: "cc");
1da177e4 LT	87	return ccode;
	88	}
	89
f9c9fe3e	90	static inline int tsch(struct subchannel_id schid, struct irb *addr)
1da177e4	91	{
94c12cc7	92	register struct subchannel_id reg1 asm ("1") = schid;
1da177e4 LT	93	int ccode;
1da177e4 LT	94
94c12cc7	95	asm volatile(
f9c9fe3e	96	" tsch 0(%3)\n"
94c12cc7 MS	97	" ipm %0\n"
94c12cc7 MS	98	" srl %0,28"
f9c9fe3e PO	99	: "=d" (ccode), "=m" (*addr)
	100	: "d" (reg1), "a" (addr)
	101	: "cc");
1da177e4 LT	102	return ccode;
	103	}
	104
f9c9fe3e	105	static inline int tpi(struct tpi_info *addr)
1da177e4 LT	106	{
	107	int ccode;
	108
94c12cc7	109	asm volatile(
f9c9fe3e	110	" tpi 0(%2)\n"
94c12cc7 MS	111	" ipm %0\n"
94c12cc7 MS	112	" srl %0,28"
f9c9fe3e PO	113	: "=d" (ccode), "=m" (*addr)
	114	: "a" (addr)
	115	: "cc");
1da177e4 LT	116	return ccode;
	117	}
	118
4c24da79	119	static inline int chsc(void *chsc_area)
1da177e4	120	{
a8237fc4	121	typedef struct { char _[4096]; } addr_type;
1da177e4 LT	122	int cc;
1da177e4 LT	123
94c12cc7 MS	124	asm volatile(
	125	" .insn rre,0xb25f0000,%2,0\n"
	126	" ipm %0\n"
	127	" srl %0,28\n"
a8237fc4 CH	128	: "=d" (cc), "=m" ((addr_type ) chsc_area)
a8237fc4 CH	129	: "d" (chsc_area), "m" ((addr_type ) chsc_area)
94c12cc7	130	: "cc");
1da177e4 LT	131	return cc;
	132	}
	133
f86635fa	134	static inline int rchp(struct chp_id chpid)
1da177e4	135	{
f86635fa	136	register struct chp_id reg1 asm ("1") = chpid;
1da177e4 LT	137	int ccode;
1da177e4 LT	138
94c12cc7 MS	139	asm volatile(
	140	" lr 1,%1\n"
	141	" rchp\n"
	142	" ipm %0\n"
	143	" srl %0,28"
	144	: "=d" (ccode) : "d" (reg1) : "cc");
1da177e4 LT	145	return ccode;
	146	}
	147
	148	#endif