[deliverable/linux.git] / drivers / s390 / cio / qdio.h

/*
 * linux/drivers/s390/cio/qdio.h
 *
 * Copyright 2000,2009 IBM Corp.
 * Author(s): Utz Bacher <utz.bacher@de.ibm.com>
 *	      Jan Glauber <jang@linux.vnet.ibm.com>
 */
#ifndef _CIO_QDIO_H
#define _CIO_QDIO_H

#include <asm/page.h>
#include <asm/schid.h>
#include <asm/debug.h>
#include "chsc.h"

#define QDIO_BUSY_BIT_PATIENCE		(100 << 12)	/* 100 microseconds */
#define QDIO_BUSY_BIT_RETRY_DELAY	10		/* 10 milliseconds */
#define QDIO_BUSY_BIT_RETRIES		1000		/* = 10s retry time */
#define QDIO_INPUT_THRESHOLD		(500 << 12)	/* 500 microseconds */

/*
 * if an asynchronous HiperSockets queue runs full, the 10 seconds timer wait
 * till next initiative to give transmitted skbs back to the stack is too long.
 * Therefore polling is started in case of multicast queue is filled more
 * than 50 percent.
 */
#define QDIO_IQDIO_POLL_LVL		65	/* HS multicast queue */

enum qdio_irq_states {
	QDIO_IRQ_STATE_INACTIVE,
	QDIO_IRQ_STATE_ESTABLISHED,
	QDIO_IRQ_STATE_ACTIVE,
	QDIO_IRQ_STATE_STOPPED,
	QDIO_IRQ_STATE_CLEANUP,
	QDIO_IRQ_STATE_ERR,
	NR_QDIO_IRQ_STATES,
};

/* used as intparm in do_IO */
#define QDIO_DOING_ESTABLISH	1
#define QDIO_DOING_ACTIVATE	2
#define QDIO_DOING_CLEANUP	3

#define SLSB_STATE_NOT_INIT	0x0
#define SLSB_STATE_EMPTY	0x1
#define SLSB_STATE_PRIMED	0x2
#define SLSB_STATE_PENDING	0x3
#define SLSB_STATE_HALTED	0xe
#define SLSB_STATE_ERROR	0xf
#define SLSB_TYPE_INPUT		0x0
#define SLSB_TYPE_OUTPUT	0x20
#define SLSB_OWNER_PROG		0x80
#define SLSB_OWNER_CU		0x40

#define SLSB_P_INPUT_NOT_INIT	\
	(SLSB_OWNER_PROG | SLSB_TYPE_INPUT | SLSB_STATE_NOT_INIT)  /* 0x80 */
#define SLSB_P_INPUT_ACK	\
	(SLSB_OWNER_PROG | SLSB_TYPE_INPUT | SLSB_STATE_EMPTY)	   /* 0x81 */
#define SLSB_CU_INPUT_EMPTY	\
	(SLSB_OWNER_CU | SLSB_TYPE_INPUT | SLSB_STATE_EMPTY)	   /* 0x41 */
#define SLSB_P_INPUT_PRIMED	\
	(SLSB_OWNER_PROG | SLSB_TYPE_INPUT | SLSB_STATE_PRIMED)	   /* 0x82 */
#define SLSB_P_INPUT_HALTED	\
	(SLSB_OWNER_PROG | SLSB_TYPE_INPUT | SLSB_STATE_HALTED)	   /* 0x8e */
#define SLSB_P_INPUT_ERROR	\
	(SLSB_OWNER_PROG | SLSB_TYPE_INPUT | SLSB_STATE_ERROR)	   /* 0x8f */
#define SLSB_P_OUTPUT_NOT_INIT	\
	(SLSB_OWNER_PROG | SLSB_TYPE_OUTPUT | SLSB_STATE_NOT_INIT) /* 0xa0 */
#define SLSB_P_OUTPUT_EMPTY	\
	(SLSB_OWNER_PROG | SLSB_TYPE_OUTPUT | SLSB_STATE_EMPTY)	   /* 0xa1 */
#define SLSB_P_OUTPUT_PENDING \
	(SLSB_OWNER_PROG | SLSB_TYPE_OUTPUT | SLSB_STATE_PENDING)  /* 0xa3 */
#define SLSB_CU_OUTPUT_PRIMED	\
	(SLSB_OWNER_CU | SLSB_TYPE_OUTPUT | SLSB_STATE_PRIMED)	   /* 0x62 */
#define SLSB_P_OUTPUT_HALTED	\
	(SLSB_OWNER_PROG | SLSB_TYPE_OUTPUT | SLSB_STATE_HALTED)   /* 0xae */
#define SLSB_P_OUTPUT_ERROR	\
	(SLSB_OWNER_PROG | SLSB_TYPE_OUTPUT | SLSB_STATE_ERROR)	   /* 0xaf */

#define SLSB_ERROR_DURING_LOOKUP  0xff

/* additional CIWs returned by extended Sense-ID */
#define CIW_TYPE_EQUEUE			0x3 /* establish QDIO queues */
#define CIW_TYPE_AQUEUE			0x4 /* activate QDIO queues */

/* flags for st qdio sch data */
#define CHSC_FLAG_QDIO_CAPABILITY	0x80
#define CHSC_FLAG_VALIDITY		0x40

/* SIGA flags */
#define QDIO_SIGA_WRITE		0x00
#define QDIO_SIGA_READ		0x01
#define QDIO_SIGA_SYNC		0x02
#define QDIO_SIGA_WRITEQ	0x04
#define QDIO_SIGA_QEBSM_FLAG	0x80

#ifdef CONFIG_64BIT
static inline int do_sqbs(u64 token, unsigned char state, int queue,
			  int *start, int *count)
{
	register unsigned long _ccq asm ("0") = *count;
	register unsigned long _token asm ("1") = token;
	unsigned long _queuestart = ((unsigned long)queue << 32) | *start;

	asm volatile(
		"	.insn	rsy,0xeb000000008A,%1,0,0(%2)"
		: "+d" (_ccq), "+d" (_queuestart)
		: "d" ((unsigned long)state), "d" (_token)
		: "memory", "cc");
	*count = _ccq & 0xff;
	*start = _queuestart & 0xff;

	return (_ccq >> 32) & 0xff;
}

static inline int do_eqbs(u64 token, unsigned char *state, int queue,
			  int *start, int *count, int ack)
{
	register unsigned long _ccq asm ("0") = *count;
	register unsigned long _token asm ("1") = token;
	unsigned long _queuestart = ((unsigned long)queue << 32) | *start;
	unsigned long _state = (unsigned long)ack << 63;

	asm volatile(
		"	.insn	rrf,0xB99c0000,%1,%2,0,0"
		: "+d" (_ccq), "+d" (_queuestart), "+d" (_state)
		: "d" (_token)
		: "memory", "cc");
	*count = _ccq & 0xff;
	*start = _queuestart & 0xff;
	*state = _state & 0xff;

	return (_ccq >> 32) & 0xff;
}
#else
static inline int do_sqbs(u64 token, unsigned char state, int queue,
			  int *start, int *count) { return 0; }
static inline int do_eqbs(u64 token, unsigned char *state, int queue,
			  int *start, int *count, int ack) { return 0; }
#endif /* CONFIG_64BIT */

struct qdio_irq;

struct siga_flag {
	u8 input:1;
	u8 output:1;
	u8 sync:1;
	u8 sync_after_ai:1;
	u8 sync_out_after_pci:1;
	u8:3;
} __attribute__ ((packed));

struct chsc_ssqd_area {
	struct chsc_header request;
	u16:10;
	u8 ssid:2;
	u8 fmt:4;
	u16 first_sch;
	u16:16;
	u16 last_sch;
	u32:32;
	struct chsc_header response;
	u32:32;
	struct qdio_ssqd_desc qdio_ssqd;
} __attribute__ ((packed));

struct scssc_area {
	struct chsc_header request;
	u16 operation_code;
	u16:16;
	u32:32;
	u32:32;
	u64 summary_indicator_addr;
	u64 subchannel_indicator_addr;
	u32 ks:4;
	u32 kc:4;
	u32:21;
	u32 isc:3;
	u32 word_with_d_bit;
	u32:32;
	struct subchannel_id schid;
	u32 reserved[1004];
	struct chsc_header response;
	u32:32;
} __attribute__ ((packed));

struct qdio_dev_perf_stat {
	unsigned int adapter_int;
	unsigned int qdio_int;
	unsigned int pci_request_int;

	unsigned int tasklet_inbound;
	unsigned int tasklet_inbound_resched;
	unsigned int tasklet_inbound_resched2;
	unsigned int tasklet_outbound;

	unsigned int siga_read;
	unsigned int siga_write;
	unsigned int siga_sync;

	unsigned int inbound_call;
	unsigned int inbound_handler;
	unsigned int stop_polling;
	unsigned int inbound_queue_full;
	unsigned int outbound_call;
	unsigned int outbound_handler;
	unsigned int outbound_queue_full;
	unsigned int fast_requeue;
	unsigned int target_full;
	unsigned int eqbs;
	unsigned int eqbs_partial;
	unsigned int sqbs;
	unsigned int sqbs_partial;
	unsigned int int_discarded;
} ____cacheline_aligned;

struct qdio_queue_perf_stat {
	/*
	 * Sorted into order-2 buckets: 1, 2-3, 4-7, ... 64-127, 128.
	 * Since max. 127 SBALs are scanned reuse entry for 128 as queue full
	 * aka 127 SBALs found.
	 */
	unsigned int nr_sbals[8];
	unsigned int nr_sbal_error;
	unsigned int nr_sbal_nop;
	unsigned int nr_sbal_total;
};

enum qdio_queue_irq_states {
	QDIO_QUEUE_IRQS_DISABLED,
};

struct qdio_input_q {
	/* input buffer acknowledgement flag */
	int polling;
	/* first ACK'ed buffer */
	int ack_start;
	/* how much sbals are acknowledged with qebsm */
	int ack_count;
	/* last time of noticing incoming data */
	u64 timestamp;
	/* upper-layer polling flag */
	unsigned long queue_irq_state;
	/* callback to start upper-layer polling */
	void (*queue_start_poll) (struct ccw_device *, int, unsigned long);
};

struct qdio_output_q {
	/* PCIs are enabled for the queue */
	int pci_out_enabled;
	/* cq: use asynchronous output buffers */
	int use_cq;
	/* cq: aobs used for particual SBAL */
	struct qaob **aobs;
	/* cq: sbal state related to asynchronous operation */
	struct qdio_outbuf_state *sbal_state;
	/* timer to check for more outbound work */
	struct timer_list timer;
	/* used SBALs before tasklet schedule */
	int scan_threshold;
};

/*
 * Note on cache alignment: grouped slsb and write mostly data at the beginning
 * sbal[] is read-only and starts on a new cacheline followed by read mostly.
 */
struct qdio_q {
	struct slsb slsb;

	union {
		struct qdio_input_q in;
		struct qdio_output_q out;
	} u;

	/*
	 * inbound: next buffer the program should check for
	 * outbound: next buffer to check if adapter processed it
	 */
	int first_to_check;

	/* first_to_check of the last time */
	int last_move;

	/* beginning position for calling the program */
	int first_to_kick;

	/* number of buffers in use by the adapter */
	atomic_t nr_buf_used;

	/* error condition during a data transfer */
	unsigned int qdio_error;

	struct tasklet_struct tasklet;
	struct qdio_queue_perf_stat q_stats;

	struct qdio_buffer *sbal[QDIO_MAX_BUFFERS_PER_Q] ____cacheline_aligned;

	/* queue number */
	int nr;

	/* bitmask of queue number */
	int mask;

	/* input or output queue */
	int is_input_q;

	/* list of thinint input queues */
	struct list_head entry;

	/* upper-layer program handler */
	qdio_handler_t (*handler);

	struct dentry *debugfs_q;
	struct qdio_irq *irq_ptr;
	struct sl *sl;
	/*
	 * A page is allocated under this pointer and used for slib and sl.
	 * slib is 2048 bytes big and sl points to offset PAGE_SIZE / 2.
	 */
	struct slib *slib;
} __attribute__ ((aligned(256)));

struct qdio_irq {
	struct qib qib;
	u32 *dsci;		/* address of device state change indicator */
	struct ccw_device *cdev;
	struct dentry *debugfs_dev;
	struct dentry *debugfs_perf;

	unsigned long int_parm;
	struct subchannel_id schid;
	unsigned long sch_token;	/* QEBSM facility */

	enum qdio_irq_states state;

	struct siga_flag siga_flag;	/* siga sync information from qdioac */

	int nr_input_qs;
	int nr_output_qs;

	struct ccw1 ccw;
	struct ciw equeue;
	struct ciw aqueue;

	struct qdio_ssqd_desc ssqd_desc;
	void (*orig_handler) (struct ccw_device *, unsigned long, struct irb *);

	int perf_stat_enabled;

	struct qdr *qdr;
	unsigned long chsc_page;

	struct qdio_q *input_qs[QDIO_MAX_QUEUES_PER_IRQ];
	struct qdio_q *output_qs[QDIO_MAX_QUEUES_PER_IRQ];

	debug_info_t *debug_area;
	struct mutex setup_mutex;
	struct qdio_dev_perf_stat perf_stat;
};

/* helper functions */
#define queue_type(q)	q->irq_ptr->qib.qfmt
#define SCH_NO(q)	(q->irq_ptr->schid.sch_no)

#define is_thinint_irq(irq) \
	(irq->qib.qfmt == QDIO_IQDIO_QFMT || \
	 css_general_characteristics.aif_osa)

#define qperf(__qdev, __attr)	((__qdev)->perf_stat.(__attr))

#define qperf_inc(__q, __attr)						\
({									\
	struct qdio_irq *qdev = (__q)->irq_ptr;				\
	if (qdev->perf_stat_enabled)					\
		(qdev->perf_stat.__attr)++;				\
})

static inline void account_sbals_error(struct qdio_q *q, int count)
{
	q->q_stats.nr_sbal_error += count;
	q->q_stats.nr_sbal_total += count;
}

/* the highest iqdio queue is used for multicast */
static inline int multicast_outbound(struct qdio_q *q)
{
	return (q->irq_ptr->nr_output_qs > 1) &&
	       (q->nr == q->irq_ptr->nr_output_qs - 1);
}

#define pci_out_supported(q) \
	(q->irq_ptr->qib.ac & QIB_AC_OUTBOUND_PCI_SUPPORTED)
#define is_qebsm(q)			(q->irq_ptr->sch_token != 0)

#define need_siga_in(q)			(q->irq_ptr->siga_flag.input)
#define need_siga_out(q)		(q->irq_ptr->siga_flag.output)
#define need_siga_sync(q)		(unlikely(q->irq_ptr->siga_flag.sync))
#define need_siga_sync_after_ai(q)	\
	(unlikely(q->irq_ptr->siga_flag.sync_after_ai))
#define need_siga_sync_out_after_pci(q)	\
	(unlikely(q->irq_ptr->siga_flag.sync_out_after_pci))

#define for_each_input_queue(irq_ptr, q, i)	\
	for (i = 0, q = irq_ptr->input_qs[0];	\
		i < irq_ptr->nr_input_qs;	\
		q = irq_ptr->input_qs[++i])
#define for_each_output_queue(irq_ptr, q, i)	\
	for (i = 0, q = irq_ptr->output_qs[0];	\
		i < irq_ptr->nr_output_qs;	\
		q = irq_ptr->output_qs[++i])

#define prev_buf(bufnr)	\
	((bufnr + QDIO_MAX_BUFFERS_MASK) & QDIO_MAX_BUFFERS_MASK)
#define next_buf(bufnr)	\
	((bufnr + 1) & QDIO_MAX_BUFFERS_MASK)
#define add_buf(bufnr, inc) \
	((bufnr + inc) & QDIO_MAX_BUFFERS_MASK)
#define sub_buf(bufnr, dec) \
	((bufnr - dec) & QDIO_MAX_BUFFERS_MASK)

#define queue_irqs_enabled(q)			\
	(test_bit(QDIO_QUEUE_IRQS_DISABLED, &q->u.in.queue_irq_state) == 0)
#define queue_irqs_disabled(q)			\
	(test_bit(QDIO_QUEUE_IRQS_DISABLED, &q->u.in.queue_irq_state) != 0)

#define TIQDIO_SHARED_IND		63

/* device state change indicators */
struct indicator_t {
	u32 ind;	/* u32 because of compare-and-swap performance */
	atomic_t count; /* use count, 0 or 1 for non-shared indicators */
};

extern struct indicator_t *q_indicators;

static inline int has_multiple_inq_on_dsci(struct qdio_irq *irq)
{
	return irq->nr_input_qs > 1;
}

static inline int references_shared_dsci(struct qdio_irq *irq)
{
	return irq->dsci == &q_indicators[TIQDIO_SHARED_IND].ind;
}

static inline int shared_ind(struct qdio_q *q)
{
	struct qdio_irq *i = q->irq_ptr;
	return references_shared_dsci(i) || has_multiple_inq_on_dsci(i);
}

/* prototypes for thin interrupt */
void qdio_setup_thinint(struct qdio_irq *irq_ptr);
int qdio_establish_thinint(struct qdio_irq *irq_ptr);
void qdio_shutdown_thinint(struct qdio_irq *irq_ptr);
void tiqdio_add_input_queues(struct qdio_irq *irq_ptr);
void tiqdio_remove_input_queues(struct qdio_irq *irq_ptr);
void tiqdio_inbound_processing(unsigned long q);
int tiqdio_allocate_memory(void);
void tiqdio_free_memory(void);
int tiqdio_register_thinints(void);
void tiqdio_unregister_thinints(void);


/* prototypes for setup */
void qdio_inbound_processing(unsigned long data);
void qdio_outbound_processing(unsigned long data);
void qdio_outbound_timer(unsigned long data);
void qdio_int_handler(struct ccw_device *cdev, unsigned long intparm,
		      struct irb *irb);
int qdio_allocate_qs(struct qdio_irq *irq_ptr, int nr_input_qs,
		     int nr_output_qs);
void qdio_setup_ssqd_info(struct qdio_irq *irq_ptr);
int qdio_setup_get_ssqd(struct qdio_irq *irq_ptr,
			struct subchannel_id *schid,
			struct qdio_ssqd_desc *data);
int qdio_setup_irq(struct qdio_initialize *init_data);
void qdio_print_subchannel_info(struct qdio_irq *irq_ptr,
				struct ccw_device *cdev);
void qdio_release_memory(struct qdio_irq *irq_ptr);
int qdio_setup_create_sysfs(struct ccw_device *cdev);
void qdio_setup_destroy_sysfs(struct ccw_device *cdev);
int qdio_setup_init(void);
void qdio_setup_exit(void);
int qdio_enable_async_operation(struct qdio_output_q *q);
void qdio_disable_async_operation(struct qdio_output_q *q);
struct qaob *qdio_allocate_aob(void);

int debug_get_buf_state(struct qdio_q *q, unsigned int bufnr,
			unsigned char *state);
#endif /* _CIO_QDIO_H */
Commit	Line	Data
779e6e1c JG	1	/*
	2	* linux/drivers/s390/cio/qdio.h
	3	*
3f09bb89	4	* Copyright 2000,2009 IBM Corp.
779e6e1c JG	5	* Author(s): Utz Bacher <utz.bacher@de.ibm.com>
	6	* Jan Glauber <jang@linux.vnet.ibm.com>
	7	*/
1da177e4 LT	8	#ifndef _CIO_QDIO_H
	9	#define _CIO_QDIO_H
	10
0b642ede	11	#include <asm/page.h>
9d92a7e1	12	#include <asm/schid.h>
22f99347	13	#include <asm/debug.h>
779e6e1c	14	#include "chsc.h"
a8237fc4	15
3a601bfe	16	#define QDIO_BUSY_BIT_PATIENCE (100 << 12) /* 100 microseconds */
be8d97a5 JG	17	#define QDIO_BUSY_BIT_RETRY_DELAY 10 /* 10 milliseconds */
be8d97a5 JG	18	#define QDIO_BUSY_BIT_RETRIES 1000 /* = 10s retry time */
3a601bfe	19	#define QDIO_INPUT_THRESHOLD (500 << 12) /* 500 microseconds */
1da177e4	20
4bcb3a37 UB	21	/*
	22	* if an asynchronous HiperSockets queue runs full, the 10 seconds timer wait
	23	* till next initiative to give transmitted skbs back to the stack is too long.
	24	* Therefore polling is started in case of multicast queue is filled more
	25	* than 50 percent.
	26	*/
	27	#define QDIO_IQDIO_POLL_LVL 65 /* HS multicast queue */
	28
1da177e4 LT	29	enum qdio_irq_states {
	30	QDIO_IRQ_STATE_INACTIVE,
	31	QDIO_IRQ_STATE_ESTABLISHED,
	32	QDIO_IRQ_STATE_ACTIVE,
	33	QDIO_IRQ_STATE_STOPPED,
	34	QDIO_IRQ_STATE_CLEANUP,
	35	QDIO_IRQ_STATE_ERR,
	36	NR_QDIO_IRQ_STATES,
	37	};
	38
779e6e1c JG	39	/* used as intparm in do_IO */
	40	#define QDIO_DOING_ESTABLISH 1
	41	#define QDIO_DOING_ACTIVATE 2
	42	#define QDIO_DOING_CLEANUP 3
	43
	44	#define SLSB_STATE_NOT_INIT 0x0
	45	#define SLSB_STATE_EMPTY 0x1
	46	#define SLSB_STATE_PRIMED 0x2
104ea556	47	#define SLSB_STATE_PENDING 0x3
779e6e1c JG	48	#define SLSB_STATE_HALTED 0xe
	49	#define SLSB_STATE_ERROR 0xf
	50	#define SLSB_TYPE_INPUT 0x0
	51	#define SLSB_TYPE_OUTPUT 0x20
	52	#define SLSB_OWNER_PROG 0x80
	53	#define SLSB_OWNER_CU 0x40
	54
	55	#define SLSB_P_INPUT_NOT_INIT \
	56	(SLSB_OWNER_PROG \| SLSB_TYPE_INPUT \| SLSB_STATE_NOT_INIT) /* 0x80 */
	57	#define SLSB_P_INPUT_ACK \
	58	(SLSB_OWNER_PROG \| SLSB_TYPE_INPUT \| SLSB_STATE_EMPTY) /* 0x81 */
	59	#define SLSB_CU_INPUT_EMPTY \
	60	(SLSB_OWNER_CU \| SLSB_TYPE_INPUT \| SLSB_STATE_EMPTY) /* 0x41 */
	61	#define SLSB_P_INPUT_PRIMED \
	62	(SLSB_OWNER_PROG \| SLSB_TYPE_INPUT \| SLSB_STATE_PRIMED) /* 0x82 */
	63	#define SLSB_P_INPUT_HALTED \
	64	(SLSB_OWNER_PROG \| SLSB_TYPE_INPUT \| SLSB_STATE_HALTED) /* 0x8e */
	65	#define SLSB_P_INPUT_ERROR \
	66	(SLSB_OWNER_PROG \| SLSB_TYPE_INPUT \| SLSB_STATE_ERROR) /* 0x8f */
	67	#define SLSB_P_OUTPUT_NOT_INIT \
	68	(SLSB_OWNER_PROG \| SLSB_TYPE_OUTPUT \| SLSB_STATE_NOT_INIT) /* 0xa0 */
	69	#define SLSB_P_OUTPUT_EMPTY \
	70	(SLSB_OWNER_PROG \| SLSB_TYPE_OUTPUT \| SLSB_STATE_EMPTY) /* 0xa1 */
104ea556	71	#define SLSB_P_OUTPUT_PENDING \
104ea556	72	(SLSB_OWNER_PROG \| SLSB_TYPE_OUTPUT \| SLSB_STATE_PENDING) /* 0xa3 */
779e6e1c JG	73	#define SLSB_CU_OUTPUT_PRIMED \
	74	(SLSB_OWNER_CU \| SLSB_TYPE_OUTPUT \| SLSB_STATE_PRIMED) /* 0x62 */
	75	#define SLSB_P_OUTPUT_HALTED \
	76	(SLSB_OWNER_PROG \| SLSB_TYPE_OUTPUT \| SLSB_STATE_HALTED) /* 0xae */
	77	#define SLSB_P_OUTPUT_ERROR \
	78	(SLSB_OWNER_PROG \| SLSB_TYPE_OUTPUT \| SLSB_STATE_ERROR) /* 0xaf */
	79
	80	#define SLSB_ERROR_DURING_LOOKUP 0xff
	81
	82	/* additional CIWs returned by extended Sense-ID */
	83	#define CIW_TYPE_EQUEUE 0x3 /* establish QDIO queues */
	84	#define CIW_TYPE_AQUEUE 0x4 /* activate QDIO queues */
1da177e4	85
779e6e1c JG	86	/* flags for st qdio sch data */
	87	#define CHSC_FLAG_QDIO_CAPABILITY 0x80
	88	#define CHSC_FLAG_VALIDITY 0x40
	89
958c0ba4 JG	90	/* SIGA flags */
	91	#define QDIO_SIGA_WRITE 0x00
	92	#define QDIO_SIGA_READ 0x01
	93	#define QDIO_SIGA_SYNC 0x02
104ea556	94	#define QDIO_SIGA_WRITEQ 0x04
958c0ba4 JG	95	#define QDIO_SIGA_QEBSM_FLAG 0x80
958c0ba4 JG	96
779e6e1c JG	97	#ifdef CONFIG_64BIT
	98	static inline int do_sqbs(u64 token, unsigned char state, int queue,
	99	int start, int count)
	100	{
	101	register unsigned long _ccq asm ("0") = *count;
	102	register unsigned long _token asm ("1") = token;
	103	unsigned long _queuestart = ((unsigned long)queue << 32) \| *start;
1da177e4	104
779e6e1c JG	105	asm volatile(
	106	" .insn rsy,0xeb000000008A,%1,0,0(%2)"
	107	: "+d" (_ccq), "+d" (_queuestart)
	108	: "d" ((unsigned long)state), "d" (_token)
	109	: "memory", "cc");
	110	*count = _ccq & 0xff;
	111	*start = _queuestart & 0xff;
8129ee16	112
779e6e1c	113	return (_ccq >> 32) & 0xff;
8129ee16 FP	114	}
8129ee16 FP	115
779e6e1c	116	static inline int do_eqbs(u64 token, unsigned char *state, int queue,
50f769df	117	int start, int count, int ack)
8129ee16	118	{
8129ee16	119	register unsigned long _ccq asm ("0") = *count;
779e6e1c	120	register unsigned long _token asm ("1") = token;
8129ee16	121	unsigned long _queuestart = ((unsigned long)queue << 32) \| *start;
50f769df	122	unsigned long _state = (unsigned long)ack << 63;
8129ee16	123
94c12cc7 MS	124	asm volatile(
	125	" .insn rrf,0xB99c0000,%1,%2,0,0"
	126	: "+d" (_ccq), "+d" (_queuestart), "+d" (_state)
779e6e1c JG	127	: "d" (_token)
779e6e1c JG	128	: "memory", "cc");
8129ee16 FP	129	*count = _ccq & 0xff;
	130	*start = _queuestart & 0xff;
	131	*state = _state & 0xff;
	132
	133	return (_ccq >> 32) & 0xff;
1da177e4	134	}
779e6e1c JG	135	#else
	136	static inline int do_sqbs(u64 token, unsigned char state, int queue,
	137	int start, int count) { return 0; }
	138	static inline int do_eqbs(u64 token, unsigned char *state, int queue,
50f769df	139	int start, int count, int ack) { return 0; }
779e6e1c	140	#endif /* CONFIG_64BIT */
1da177e4	141
779e6e1c	142	struct qdio_irq;
1da177e4	143
779e6e1c JG	144	struct siga_flag {
	145	u8 input:1;
	146	u8 output:1;
	147	u8 sync:1;
90adac58 JG	148	u8 sync_after_ai:1;
	149	u8 sync_out_after_pci:1;
	150	u8:3;
779e6e1c	151	} __attribute__ ((packed));
1da177e4	152
779e6e1c	153	struct chsc_ssqd_area {
e1776856	154	struct chsc_header request;
779e6e1c JG	155	u16:10;
	156	u8 ssid:2;
	157	u8 fmt:4;
e1776856	158	u16 first_sch;
779e6e1c	159	u16:16;
e1776856	160	u16 last_sch;
779e6e1c	161	u32:32;
e1776856	162	struct chsc_header response;
779e6e1c JG	163	u32:32;
	164	struct qdio_ssqd_desc qdio_ssqd;
	165	} __attribute__ ((packed));
e1776856	166
779e6e1c JG	167	struct scssc_area {
	168	struct chsc_header request;
	169	u16 operation_code;
	170	u16:16;
	171	u32:32;
	172	u32:32;
	173	u64 summary_indicator_addr;
	174	u64 subchannel_indicator_addr;
	175	u32 ks:4;
	176	u32 kc:4;
	177	u32:21;
	178	u32 isc:3;
	179	u32 word_with_d_bit;
	180	u32:32;
	181	struct subchannel_id schid;
	182	u32 reserved[1004];
	183	struct chsc_header response;
	184	u32:32;
	185	} __attribute__ ((packed));
	186
6486cda6 JG	187	struct qdio_dev_perf_stat {
	188	unsigned int adapter_int;
	189	unsigned int qdio_int;
	190	unsigned int pci_request_int;
	191
	192	unsigned int tasklet_inbound;
	193	unsigned int tasklet_inbound_resched;
	194	unsigned int tasklet_inbound_resched2;
	195	unsigned int tasklet_outbound;
	196
	197	unsigned int siga_read;
	198	unsigned int siga_write;
	199	unsigned int siga_sync;
	200
	201	unsigned int inbound_call;
	202	unsigned int inbound_handler;
	203	unsigned int stop_polling;
	204	unsigned int inbound_queue_full;
	205	unsigned int outbound_call;
	206	unsigned int outbound_handler;
0195843b	207	unsigned int outbound_queue_full;
6486cda6 JG	208	unsigned int fast_requeue;
	209	unsigned int target_full;
	210	unsigned int eqbs;
	211	unsigned int eqbs_partial;
	212	unsigned int sqbs;
	213	unsigned int sqbs_partial;
d36deae7	214	unsigned int int_discarded;
432ac5e0	215	} ____cacheline_aligned;
6486cda6	216
d307297f JG	217	struct qdio_queue_perf_stat {
	218	/*
	219	* Sorted into order-2 buckets: 1, 2-3, 4-7, ... 64-127, 128.
	220	* Since max. 127 SBALs are scanned reuse entry for 128 as queue full
	221	* aka 127 SBALs found.
	222	*/
	223	unsigned int nr_sbals[8];
	224	unsigned int nr_sbal_error;
	225	unsigned int nr_sbal_nop;
	226	unsigned int nr_sbal_total;
	227	};
	228
d36deae7 JG	229	enum qdio_queue_irq_states {
	230	QDIO_QUEUE_IRQS_DISABLED,
	231	};
	232
779e6e1c JG	233	struct qdio_input_q {
	234	/* input buffer acknowledgement flag */
	235	int polling;
e85dea0e JG	236	/* first ACK'ed buffer */
e85dea0e JG	237	int ack_start;
50f769df JG	238	/* how much sbals are acknowledged with qebsm */
50f769df JG	239	int ack_count;
779e6e1c JG	240	/* last time of noticing incoming data */
779e6e1c JG	241	u64 timestamp;
d36deae7 JG	242	/* upper-layer polling flag */
	243	unsigned long queue_irq_state;
	244	/* callback to start upper-layer polling */
	245	void (queue_start_poll) (struct ccw_device , int, unsigned long);
1da177e4	246	};
1da177e4	247
779e6e1c	248	struct qdio_output_q {
779e6e1c JG	249	/* PCIs are enabled for the queue */
779e6e1c JG	250	int pci_out_enabled;
104ea556	251	/* cq: use asynchronous output buffers */
	252	int use_cq;
	253	/* cq: aobs used for particual SBAL */
	254	struct qaob **aobs;
	255	/* cq: sbal state related to asynchronous operation */
	256	struct qdio_outbuf_state *sbal_state;
779e6e1c JG	257	/* timer to check for more outbound work */
779e6e1c JG	258	struct timer_list timer;
3d6c76ff JG	259	/* used SBALs before tasklet schedule */
3d6c76ff JG	260	int scan_threshold;
779e6e1c	261	};
1da177e4	262
d307297f JG	263	/*
	264	* Note on cache alignment: grouped slsb and write mostly data at the beginning
	265	* sbal[] is read-only and starts on a new cacheline followed by read mostly.
	266	*/
1da177e4	267	struct qdio_q {
779e6e1c	268	struct slsb slsb;
d307297f	269
779e6e1c JG	270	union {
	271	struct qdio_input_q in;
	272	struct qdio_output_q out;
	273	} u;
1da177e4	274
779e6e1c JG	275	/*
779e6e1c JG	276	* inbound: next buffer the program should check for
d307297f	277	* outbound: next buffer to check if adapter processed it
779e6e1c JG	278	*/
779e6e1c JG	279	int first_to_check;
1da177e4	280
779e6e1c	281	/* first_to_check of the last time */
e85dea0e	282	int last_move;
1da177e4	283
779e6e1c JG	284	/* beginning position for calling the program */
779e6e1c JG	285	int first_to_kick;
1da177e4	286
779e6e1c JG	287	/* number of buffers in use by the adapter */
779e6e1c JG	288	atomic_t nr_buf_used;
1da177e4	289
779e6e1c	290	/* error condition during a data transfer */
1da177e4	291	unsigned int qdio_error;
1da177e4	292
d307297f JG	293	struct tasklet_struct tasklet;
	294	struct qdio_queue_perf_stat q_stats;
	295
	296	struct qdio_buffer *sbal[QDIO_MAX_BUFFERS_PER_Q] ____cacheline_aligned;
	297
	298	/* queue number */
	299	int nr;
	300
	301	/* bitmask of queue number */
	302	int mask;
	303
	304	/* input or output queue */
	305	int is_input_q;
	306
	307	/* list of thinint input queues */
	308	struct list_head entry;
	309
	310	/* upper-layer program handler */
	311	qdio_handler_t (*handler);
779e6e1c	312
d307297f JG	313	struct dentry *debugfs_q;
	314	struct qdio_irq *irq_ptr;
	315	struct sl *sl;
779e6e1c	316	/*
5382fe11 JG	317	* A page is allocated under this pointer and used for slib and sl.
5382fe11 JG	318	* slib is 2048 bytes big and sl points to offset PAGE_SIZE / 2.
779e6e1c JG	319	*/
779e6e1c JG	320	struct slib *slib;
1da177e4 LT	321	} __attribute__ ((aligned(256)));
	322
	323	struct qdio_irq {
779e6e1c JG	324	struct qib qib;
	325	u32 dsci; / address of device state change indicator */
	326	struct ccw_device *cdev;
3f09bb89	327	struct dentry *debugfs_dev;
6486cda6	328	struct dentry *debugfs_perf;
1da177e4 LT	329
1da177e4 LT	330	unsigned long int_parm;
a8237fc4	331	struct subchannel_id schid;
779e6e1c	332	unsigned long sch_token; /* QEBSM facility */
8129ee16	333
1da177e4 LT	334	enum qdio_irq_states state;
1da177e4 LT	335
779e6e1c	336	struct siga_flag siga_flag; /* siga sync information from qdioac */
1da177e4	337
779e6e1c JG	338	int nr_input_qs;
779e6e1c JG	339	int nr_output_qs;
1da177e4 LT	340
1da177e4 LT	341	struct ccw1 ccw;
1da177e4 LT	342	struct ciw equeue;
	343	struct ciw aqueue;
	344
779e6e1c	345	struct qdio_ssqd_desc ssqd_desc;
779e6e1c	346	void (orig_handler) (struct ccw_device , unsigned long, struct irb *);
1da177e4	347
6486cda6	348	int perf_stat_enabled;
432ac5e0	349
1da177e4	350	struct qdr *qdr;
779e6e1c JG	351	unsigned long chsc_page;
779e6e1c JG	352
1da177e4 LT	353	struct qdio_q *input_qs[QDIO_MAX_QUEUES_PER_IRQ];
1da177e4 LT	354	struct qdio_q *output_qs[QDIO_MAX_QUEUES_PER_IRQ];
779e6e1c	355
22f99347	356	debug_info_t *debug_area;
779e6e1c	357	struct mutex setup_mutex;
432ac5e0	358	struct qdio_dev_perf_stat perf_stat;
1da177e4	359	};
779e6e1c JG	360
	361	/* helper functions */
	362	#define queue_type(q) q->irq_ptr->qib.qfmt
22f99347	363	#define SCH_NO(q) (q->irq_ptr->schid.sch_no)
779e6e1c JG	364
	365	#define is_thinint_irq(irq) \
	366	(irq->qib.qfmt == QDIO_IQDIO_QFMT \|\| \
	367	css_general_characteristics.aif_osa)
	368
d307297f JG	369	#define qperf(__qdev, __attr) ((__qdev)->perf_stat.(__attr))
	370
	371	#define qperf_inc(__q, __attr) \
	372	({ \
	373	struct qdio_irq *qdev = (__q)->irq_ptr; \
	374	if (qdev->perf_stat_enabled) \
	375	(qdev->perf_stat.__attr)++; \
	376	})
	377
	378	static inline void account_sbals_error(struct qdio_q *q, int count)
	379	{
	380	q->q_stats.nr_sbal_error += count;
	381	q->q_stats.nr_sbal_total += count;
	382	}
6486cda6	383
779e6e1c JG	384	/* the highest iqdio queue is used for multicast */
	385	static inline int multicast_outbound(struct qdio_q *q)
	386	{
	387	return (q->irq_ptr->nr_output_qs > 1) &&
	388	(q->nr == q->irq_ptr->nr_output_qs - 1);
	389	}
	390
779e6e1c JG	391	#define pci_out_supported(q) \
	392	(q->irq_ptr->qib.ac & QIB_AC_OUTBOUND_PCI_SUPPORTED)
	393	#define is_qebsm(q) (q->irq_ptr->sch_token != 0)
	394
779e6e1c JG	395	#define need_siga_in(q) (q->irq_ptr->siga_flag.input)
779e6e1c JG	396	#define need_siga_out(q) (q->irq_ptr->siga_flag.output)
90adac58 JG	397	#define need_siga_sync(q) (unlikely(q->irq_ptr->siga_flag.sync))
	398	#define need_siga_sync_after_ai(q) \
	399	(unlikely(q->irq_ptr->siga_flag.sync_after_ai))
	400	#define need_siga_sync_out_after_pci(q) \
	401	(unlikely(q->irq_ptr->siga_flag.sync_out_after_pci))
779e6e1c JG	402
	403	#define for_each_input_queue(irq_ptr, q, i) \
	404	for (i = 0, q = irq_ptr->input_qs[0]; \
	405	i < irq_ptr->nr_input_qs; \
	406	q = irq_ptr->input_qs[++i])
	407	#define for_each_output_queue(irq_ptr, q, i) \
	408	for (i = 0, q = irq_ptr->output_qs[0]; \
	409	i < irq_ptr->nr_output_qs; \
	410	q = irq_ptr->output_qs[++i])
	411
	412	#define prev_buf(bufnr) \
	413	((bufnr + QDIO_MAX_BUFFERS_MASK) & QDIO_MAX_BUFFERS_MASK)
	414	#define next_buf(bufnr) \
	415	((bufnr + 1) & QDIO_MAX_BUFFERS_MASK)
	416	#define add_buf(bufnr, inc) \
	417	((bufnr + inc) & QDIO_MAX_BUFFERS_MASK)
50f769df JG	418	#define sub_buf(bufnr, dec) \
50f769df JG	419	((bufnr - dec) & QDIO_MAX_BUFFERS_MASK)
779e6e1c	420
d36deae7 JG	421	#define queue_irqs_enabled(q) \
	422	(test_bit(QDIO_QUEUE_IRQS_DISABLED, &q->u.in.queue_irq_state) == 0)
	423	#define queue_irqs_disabled(q) \
	424	(test_bit(QDIO_QUEUE_IRQS_DISABLED, &q->u.in.queue_irq_state) != 0)
	425
	426	#define TIQDIO_SHARED_IND 63
	427
	428	/* device state change indicators */
	429	struct indicator_t {
	430	u32 ind; /* u32 because of compare-and-swap performance */
	431	atomic_t count; /* use count, 0 or 1 for non-shared indicators */
	432	};
	433
	434	extern struct indicator_t *q_indicators;
	435
104ea556	436	static inline int has_multiple_inq_on_dsci(struct qdio_irq *irq)
d36deae7	437	{
104ea556	438	return irq->nr_input_qs > 1;
	439	}
	440
	441	static inline int references_shared_dsci(struct qdio_irq *irq)
	442	{
	443	return irq->dsci == &q_indicators[TIQDIO_SHARED_IND].ind;
	444	}
	445
	446	static inline int shared_ind(struct qdio_q *q)
	447	{
	448	struct qdio_irq *i = q->irq_ptr;
	449	return references_shared_dsci(i) \|\| has_multiple_inq_on_dsci(i);
d36deae7 JG	450	}
d36deae7 JG	451
779e6e1c	452	/* prototypes for thin interrupt */
779e6e1c JG	453	void qdio_setup_thinint(struct qdio_irq *irq_ptr);
	454	int qdio_establish_thinint(struct qdio_irq *irq_ptr);
	455	void qdio_shutdown_thinint(struct qdio_irq *irq_ptr);
	456	void tiqdio_add_input_queues(struct qdio_irq *irq_ptr);
	457	void tiqdio_remove_input_queues(struct qdio_irq *irq_ptr);
	458	void tiqdio_inbound_processing(unsigned long q);
	459	int tiqdio_allocate_memory(void);
	460	void tiqdio_free_memory(void);
	461	int tiqdio_register_thinints(void);
	462	void tiqdio_unregister_thinints(void);
	463
104ea556	464
779e6e1c JG	465	/* prototypes for setup */
	466	void qdio_inbound_processing(unsigned long data);
	467	void qdio_outbound_processing(unsigned long data);
	468	void qdio_outbound_timer(unsigned long data);
	469	void qdio_int_handler(struct ccw_device *cdev, unsigned long intparm,
	470	struct irb *irb);
	471	int qdio_allocate_qs(struct qdio_irq *irq_ptr, int nr_input_qs,
	472	int nr_output_qs);
	473	void qdio_setup_ssqd_info(struct qdio_irq *irq_ptr);
bbd50e17 JG	474	int qdio_setup_get_ssqd(struct qdio_irq *irq_ptr,
	475	struct subchannel_id *schid,
	476	struct qdio_ssqd_desc *data);
779e6e1c JG	477	int qdio_setup_irq(struct qdio_initialize *init_data);
	478	void qdio_print_subchannel_info(struct qdio_irq *irq_ptr,
	479	struct ccw_device *cdev);
	480	void qdio_release_memory(struct qdio_irq *irq_ptr);
50f769df JG	481	int qdio_setup_create_sysfs(struct ccw_device *cdev);
50f769df JG	482	void qdio_setup_destroy_sysfs(struct ccw_device *cdev);
779e6e1c JG	483	int qdio_setup_init(void);
779e6e1c JG	484	void qdio_setup_exit(void);
104ea556	485	int qdio_enable_async_operation(struct qdio_output_q *q);
	486	void qdio_disable_async_operation(struct qdio_output_q *q);
	487	struct qaob *qdio_allocate_aob(void);
779e6e1c	488
60b5df2f JG	489	int debug_get_buf_state(struct qdio_q *q, unsigned int bufnr,
60b5df2f JG	490	unsigned char *state);
779e6e1c	491	#endif /* _CIO_QDIO_H */