[deliverable/linux.git] / drivers / scsi / NCR5380.h

/* 
 * NCR 5380 defines
 *
 * Copyright 1993, Drew Eckhardt
 *	Visionary Computing
 *	(Unix consulting and custom programming)
 * 	drew@colorado.edu
 *      +1 (303) 666-5836
 *
 * For more information, please consult 
 *
 * NCR 5380 Family
 * SCSI Protocol Controller
 * Databook
 * NCR Microelectronics
 * 1635 Aeroplaza Drive
 * Colorado Springs, CO 80916
 * 1+ (719) 578-3400
 * 1+ (800) 334-5454
 */

#ifndef NCR5380_H
#define NCR5380_H

#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/workqueue.h>
#include <scsi/scsi_dbg.h>
#include <scsi/scsi_eh.h>
#include <scsi/scsi_transport_spi.h>

#define NDEBUG_ARBITRATION	0x1
#define NDEBUG_AUTOSENSE	0x2
#define NDEBUG_DMA		0x4
#define NDEBUG_HANDSHAKE	0x8
#define NDEBUG_INFORMATION	0x10
#define NDEBUG_INIT		0x20
#define NDEBUG_INTR		0x40
#define NDEBUG_LINKED		0x80
#define NDEBUG_MAIN		0x100
#define NDEBUG_NO_DATAOUT	0x200
#define NDEBUG_NO_WRITE		0x400
#define NDEBUG_PIO		0x800
#define NDEBUG_PSEUDO_DMA	0x1000
#define NDEBUG_QUEUES		0x2000
#define NDEBUG_RESELECTION	0x4000
#define NDEBUG_SELECTION	0x8000
#define NDEBUG_USLEEP		0x10000
#define NDEBUG_LAST_BYTE_SENT	0x20000
#define NDEBUG_RESTART_SELECT	0x40000
#define NDEBUG_EXTENDED		0x80000
#define NDEBUG_C400_PREAD	0x100000
#define NDEBUG_C400_PWRITE	0x200000
#define NDEBUG_LISTS		0x400000
#define NDEBUG_ABORT		0x800000
#define NDEBUG_TAGS		0x1000000
#define NDEBUG_MERGING		0x2000000

#define NDEBUG_ANY		0xFFFFFFFFUL

/* 
 * The contents of the OUTPUT DATA register are asserted on the bus when
 * either arbitration is occurring or the phase-indicating signals (
 * IO, CD, MSG) in the TARGET COMMAND register and the ASSERT DATA
 * bit in the INITIATOR COMMAND register is set.
 */

#define OUTPUT_DATA_REG         0	/* wo DATA lines on SCSI bus */
#define CURRENT_SCSI_DATA_REG   0	/* ro same */

#define INITIATOR_COMMAND_REG	1	/* rw */
#define ICR_ASSERT_RST		0x80	/* rw Set to assert RST  */
#define ICR_ARBITRATION_PROGRESS 0x40	/* ro Indicates arbitration complete */
#define ICR_TRI_STATE		0x40	/* wo Set to tri-state drivers */
#define ICR_ARBITRATION_LOST	0x20	/* ro Indicates arbitration lost */
#define ICR_DIFF_ENABLE		0x20	/* wo Set to enable diff. drivers */
#define ICR_ASSERT_ACK		0x10	/* rw ini Set to assert ACK */
#define ICR_ASSERT_BSY		0x08	/* rw Set to assert BSY */
#define ICR_ASSERT_SEL 		0x04	/* rw Set to assert SEL */
#define ICR_ASSERT_ATN		0x02	/* rw Set to assert ATN */
#define ICR_ASSERT_DATA		0x01	/* rw SCSI_DATA_REG is asserted */

#ifdef DIFFERENTIAL
#define ICR_BASE		ICR_DIFF_ENABLE
#else
#define ICR_BASE		0
#endif

#define MODE_REG		2
/*
 * Note : BLOCK_DMA code will keep DRQ asserted for the duration of the 
 * transfer, causing the chip to hog the bus.  You probably don't want 
 * this.
 */
#define MR_BLOCK_DMA_MODE	0x80	/* rw block mode DMA */
#define MR_TARGET		0x40	/* rw target mode */
#define MR_ENABLE_PAR_CHECK	0x20	/* rw enable parity checking */
#define MR_ENABLE_PAR_INTR	0x10	/* rw enable bad parity interrupt */
#define MR_ENABLE_EOP_INTR	0x08	/* rw enable eop interrupt */
#define MR_MONITOR_BSY		0x04	/* rw enable int on unexpected bsy fail */
#define MR_DMA_MODE		0x02	/* rw DMA / pseudo DMA mode */
#define MR_ARBITRATE		0x01	/* rw start arbitration */

#ifdef PARITY
#define MR_BASE			MR_ENABLE_PAR_CHECK
#else
#define MR_BASE			0
#endif

#define TARGET_COMMAND_REG	3
#define TCR_LAST_BYTE_SENT	0x80	/* ro DMA done */
#define TCR_ASSERT_REQ		0x08	/* tgt rw assert REQ */
#define TCR_ASSERT_MSG		0x04	/* tgt rw assert MSG */
#define TCR_ASSERT_CD		0x02	/* tgt rw assert CD */
#define TCR_ASSERT_IO		0x01	/* tgt rw assert IO */

#define STATUS_REG		4	/* ro */
/*
 * Note : a set bit indicates an active signal, driven by us or another 
 * device.
 */
#define SR_RST			0x80
#define SR_BSY			0x40
#define SR_REQ			0x20
#define SR_MSG			0x10
#define SR_CD			0x08
#define SR_IO			0x04
#define SR_SEL			0x02
#define SR_DBP			0x01

/*
 * Setting a bit in this register will cause an interrupt to be generated when 
 * BSY is false and SEL true and this bit is asserted  on the bus.
 */
#define SELECT_ENABLE_REG	4	/* wo */

#define BUS_AND_STATUS_REG	5	/* ro */
#define BASR_END_DMA_TRANSFER	0x80	/* ro set on end of transfer */
#define BASR_DRQ		0x40	/* ro mirror of DRQ pin */
#define BASR_PARITY_ERROR	0x20	/* ro parity error detected */
#define BASR_IRQ		0x10	/* ro mirror of IRQ pin */
#define BASR_PHASE_MATCH	0x08	/* ro Set when MSG CD IO match TCR */
#define BASR_BUSY_ERROR		0x04	/* ro Unexpected change to inactive state */
#define BASR_ATN 		0x02	/* ro BUS status */
#define BASR_ACK		0x01	/* ro BUS status */

/* Write any value to this register to start a DMA send */
#define START_DMA_SEND_REG	5	/* wo */

/* 
 * Used in DMA transfer mode, data is latched from the SCSI bus on
 * the falling edge of REQ (ini) or ACK (tgt)
 */
#define INPUT_DATA_REG			6	/* ro */

/* Write any value to this register to start a DMA receive */
#define START_DMA_TARGET_RECEIVE_REG	6	/* wo */

/* Read this register to clear interrupt conditions */
#define RESET_PARITY_INTERRUPT_REG	7	/* ro */

/* Write any value to this register to start an ini mode DMA receive */
#define START_DMA_INITIATOR_RECEIVE_REG 7	/* wo */

/* NCR 53C400(A) Control Status Register bits: */
#define CSR_RESET              0x80	/* wo  Resets 53c400 */
#define CSR_53C80_REG          0x80	/* ro  5380 registers busy */
#define CSR_TRANS_DIR          0x40	/* rw  Data transfer direction */
#define CSR_SCSI_BUFF_INTR     0x20	/* rw  Enable int on transfer ready */
#define CSR_53C80_INTR         0x10	/* rw  Enable 53c80 interrupts */
#define CSR_SHARED_INTR        0x08	/* rw  Interrupt sharing */
#define CSR_HOST_BUF_NOT_RDY   0x04	/* ro  Is Host buffer ready */
#define CSR_SCSI_BUF_RDY       0x02	/* ro  SCSI buffer read */
#define CSR_GATED_53C80_IRQ    0x01	/* ro  Last block xferred */

#if 0
#define CSR_BASE CSR_SCSI_BUFF_INTR | CSR_53C80_INTR
#else
#define CSR_BASE CSR_53C80_INTR
#endif

/* Note : PHASE_* macros are based on the values of the STATUS register */
#define PHASE_MASK 	(SR_MSG | SR_CD | SR_IO)

#define PHASE_DATAOUT		0
#define PHASE_DATAIN		SR_IO
#define PHASE_CMDOUT		SR_CD
#define PHASE_STATIN		(SR_CD | SR_IO)
#define PHASE_MSGOUT		(SR_MSG | SR_CD)
#define PHASE_MSGIN		(SR_MSG | SR_CD | SR_IO)
#define PHASE_UNKNOWN		0xff

/* 
 * Convert status register phase to something we can use to set phase in 
 * the target register so we can get phase mismatch interrupts on DMA 
 * transfers.
 */

#define PHASE_SR_TO_TCR(phase) ((phase) >> 2)

/*
 * These are "special" values for the irq and dma_channel fields of the 
 * Scsi_Host structure
 */

#define DMA_NONE	255
#define IRQ_AUTO	254
#define DMA_AUTO	254
#define PORT_AUTO	0xffff	/* autoprobe io port for 53c400a */

#ifndef NO_IRQ
#define NO_IRQ		0
#endif

#define FLAG_DMA_FIXUP			1	/* Use DMA errata workarounds */
#define FLAG_NO_PSEUDO_DMA		8	/* Inhibit DMA */
#define FLAG_LATE_DMA_SETUP		32	/* Setup NCR before DMA H/W */
#define FLAG_TOSHIBA_DELAY		128	/* Allow for borken CD-ROMs */

struct NCR5380_hostdata {
	NCR5380_implementation_fields;		/* implementation specific */
	struct Scsi_Host *host;			/* Host backpointer */
	unsigned char id_mask, id_higher_mask;	/* 1 << id, all bits greater */
	unsigned char busy[8];			/* index = target, bit = lun */
	int dma_len;				/* requested length of DMA */
	unsigned char last_message;		/* last message OUT */
	struct scsi_cmnd *connected;		/* currently connected cmnd */
	struct scsi_cmnd *selecting;		/* cmnd to be connected */
	struct list_head unissued;		/* waiting to be issued */
	struct list_head autosense;		/* priority issue queue */
	struct list_head disconnected;		/* waiting for reconnect */
	spinlock_t lock;			/* protects this struct */
	int flags;
	struct scsi_eh_save ses;
	struct scsi_cmnd *sensing;
	char info[256];
	int read_overruns;                /* number of bytes to cut from a
	                                   * transfer to handle chip overruns */
	struct work_struct main_task;
	struct workqueue_struct *work_q;
	unsigned long accesses_per_ms;	/* chip register accesses per ms */
};

#ifdef __KERNEL__

struct NCR5380_cmd {
	struct list_head list;
};

#define NCR5380_CMD_SIZE		(sizeof(struct NCR5380_cmd))

static inline struct scsi_cmnd *NCR5380_to_scmd(struct NCR5380_cmd *ncmd_ptr)
{
	return ((struct scsi_cmnd *)ncmd_ptr) - 1;
}

#ifndef NDEBUG
#define NDEBUG (0)
#endif

#define dprintk(flg, fmt, ...) \
	do { if ((NDEBUG) & (flg)) \
		printk(KERN_DEBUG fmt, ## __VA_ARGS__); } while (0)

#define dsprintk(flg, host, fmt, ...) \
	do { if ((NDEBUG) & (flg)) \
		shost_printk(KERN_DEBUG, host, fmt, ## __VA_ARGS__); \
	} while (0)

#if NDEBUG
#define NCR5380_dprint(flg, arg) \
	do { if ((NDEBUG) & (flg)) NCR5380_print(arg); } while (0)
#define NCR5380_dprint_phase(flg, arg) \
	do { if ((NDEBUG) & (flg)) NCR5380_print_phase(arg); } while (0)
static void NCR5380_print_phase(struct Scsi_Host *instance);
static void NCR5380_print(struct Scsi_Host *instance);
#else
#define NCR5380_dprint(flg, arg)       do {} while (0)
#define NCR5380_dprint_phase(flg, arg) do {} while (0)
#endif

static int NCR5380_probe_irq(struct Scsi_Host *instance, int possible);
static int NCR5380_init(struct Scsi_Host *instance, int flags);
static int NCR5380_maybe_reset_bus(struct Scsi_Host *);
static void NCR5380_exit(struct Scsi_Host *instance);
static void NCR5380_information_transfer(struct Scsi_Host *instance);
static irqreturn_t NCR5380_intr(int irq, void *dev_id);
static void NCR5380_main(struct work_struct *work);
static const char *NCR5380_info(struct Scsi_Host *instance);
static void NCR5380_reselect(struct Scsi_Host *instance);
static struct scsi_cmnd *NCR5380_select(struct Scsi_Host *, struct scsi_cmnd *);
static int NCR5380_transfer_dma(struct Scsi_Host *instance, unsigned char *phase, int *count, unsigned char **data);
static int NCR5380_transfer_pio(struct Scsi_Host *instance, unsigned char *phase, int *count, unsigned char **data);
static int NCR5380_poll_politely2(struct Scsi_Host *, int, int, int, int, int, int, int);

static inline int NCR5380_poll_politely(struct Scsi_Host *instance,
					int reg, int bit, int val, int wait)
{
	return NCR5380_poll_politely2(instance, reg, bit, val,
						reg, bit, val, wait);
}

#endif				/* __KERNEL__ */
#endif				/* NCR5380_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* NCR 5380 defines
	3	*
	4	* Copyright 1993, Drew Eckhardt
	5	* Visionary Computing
	6	* (Unix consulting and custom programming)
	7	* drew@colorado.edu
	8	* +1 (303) 666-5836
	9	*
1da177e4 LT	10	* For more information, please consult
	11	*
	12	* NCR 5380 Family
	13	* SCSI Protocol Controller
	14	* Databook
	15	* NCR Microelectronics
	16	* 1635 Aeroplaza Drive
	17	* Colorado Springs, CO 80916
	18	* 1+ (719) 578-3400
	19	* 1+ (800) 334-5454
	20	*/
	21
1da177e4 LT	22	#ifndef NCR5380_H
	23	#define NCR5380_H
	24
161c0059	25	#include <linux/delay.h>
1da177e4	26	#include <linux/interrupt.h>
32b26a10	27	#include <linux/list.h>
161c0059 FT	28	#include <linux/workqueue.h>
161c0059 FT	29	#include <scsi/scsi_dbg.h>
28424d3a	30	#include <scsi/scsi_eh.h>
161c0059	31	#include <scsi/scsi_transport_spi.h>
28424d3a	32
1da177e4 LT	33	#define NDEBUG_ARBITRATION 0x1
	34	#define NDEBUG_AUTOSENSE 0x2
	35	#define NDEBUG_DMA 0x4
	36	#define NDEBUG_HANDSHAKE 0x8
	37	#define NDEBUG_INFORMATION 0x10
	38	#define NDEBUG_INIT 0x20
	39	#define NDEBUG_INTR 0x40
	40	#define NDEBUG_LINKED 0x80
	41	#define NDEBUG_MAIN 0x100
	42	#define NDEBUG_NO_DATAOUT 0x200
	43	#define NDEBUG_NO_WRITE 0x400
	44	#define NDEBUG_PIO 0x800
	45	#define NDEBUG_PSEUDO_DMA 0x1000
	46	#define NDEBUG_QUEUES 0x2000
	47	#define NDEBUG_RESELECTION 0x4000
	48	#define NDEBUG_SELECTION 0x8000
	49	#define NDEBUG_USLEEP 0x10000
	50	#define NDEBUG_LAST_BYTE_SENT 0x20000
	51	#define NDEBUG_RESTART_SELECT 0x40000
	52	#define NDEBUG_EXTENDED 0x80000
	53	#define NDEBUG_C400_PREAD 0x100000
	54	#define NDEBUG_C400_PWRITE 0x200000
	55	#define NDEBUG_LISTS 0x400000
9829e528 FT	56	#define NDEBUG_ABORT 0x800000
	57	#define NDEBUG_TAGS 0x1000000
	58	#define NDEBUG_MERGING 0x2000000
1da177e4 LT	59
	60	#define NDEBUG_ANY 0xFFFFFFFFUL
	61
	62	/*
	63	* The contents of the OUTPUT DATA register are asserted on the bus when
	64	* either arbitration is occurring or the phase-indicating signals (
	65	* IO, CD, MSG) in the TARGET COMMAND register and the ASSERT DATA
	66	* bit in the INITIATOR COMMAND register is set.
	67	*/
	68
	69	#define OUTPUT_DATA_REG 0 /* wo DATA lines on SCSI bus */
	70	#define CURRENT_SCSI_DATA_REG 0 /* ro same */
	71
	72	#define INITIATOR_COMMAND_REG 1 /* rw */
	73	#define ICR_ASSERT_RST 0x80 /* rw Set to assert RST */
	74	#define ICR_ARBITRATION_PROGRESS 0x40 /* ro Indicates arbitration complete */
	75	#define ICR_TRI_STATE 0x40 /* wo Set to tri-state drivers */
	76	#define ICR_ARBITRATION_LOST 0x20 /* ro Indicates arbitration lost */
	77	#define ICR_DIFF_ENABLE 0x20 /* wo Set to enable diff. drivers */
	78	#define ICR_ASSERT_ACK 0x10 /* rw ini Set to assert ACK */
	79	#define ICR_ASSERT_BSY 0x08 /* rw Set to assert BSY */
	80	#define ICR_ASSERT_SEL 0x04 /* rw Set to assert SEL */
	81	#define ICR_ASSERT_ATN 0x02 /* rw Set to assert ATN */
	82	#define ICR_ASSERT_DATA 0x01 /* rw SCSI_DATA_REG is asserted */
	83
	84	#ifdef DIFFERENTIAL
	85	#define ICR_BASE ICR_DIFF_ENABLE
	86	#else
	87	#define ICR_BASE 0
	88	#endif
	89
	90	#define MODE_REG 2
	91	/*
	92	* Note : BLOCK_DMA code will keep DRQ asserted for the duration of the
	93	* transfer, causing the chip to hog the bus. You probably don't want
	94	* this.
	95	*/
	96	#define MR_BLOCK_DMA_MODE 0x80 /* rw block mode DMA */
	97	#define MR_TARGET 0x40 /* rw target mode */
	98	#define MR_ENABLE_PAR_CHECK 0x20 /* rw enable parity checking */
	99	#define MR_ENABLE_PAR_INTR 0x10 /* rw enable bad parity interrupt */
	100	#define MR_ENABLE_EOP_INTR 0x08 /* rw enable eop interrupt */
	101	#define MR_MONITOR_BSY 0x04 /* rw enable int on unexpected bsy fail */
	102	#define MR_DMA_MODE 0x02 /* rw DMA / pseudo DMA mode */
	103	#define MR_ARBITRATE 0x01 /* rw start arbitration */
	104
	105	#ifdef PARITY
	106	#define MR_BASE MR_ENABLE_PAR_CHECK
	107	#else
	108	#define MR_BASE 0
	109	#endif
	110
	111	#define TARGET_COMMAND_REG 3
	112	#define TCR_LAST_BYTE_SENT 0x80 /* ro DMA done */
	113	#define TCR_ASSERT_REQ 0x08 /* tgt rw assert REQ */
	114	#define TCR_ASSERT_MSG 0x04 /* tgt rw assert MSG */
	115	#define TCR_ASSERT_CD 0x02 /* tgt rw assert CD */
	116	#define TCR_ASSERT_IO 0x01 /* tgt rw assert IO */
	117
	118	#define STATUS_REG 4 /* ro */
	119	/*
	120	* Note : a set bit indicates an active signal, driven by us or another
	121	* device.
	122	*/
123	#define SR_RST 0x80
124	#define SR_BSY 0x40
125	#define SR_REQ 0x20
126	#define SR_MSG 0x10
127	#define SR_CD 0x08
128	#define SR_IO 0x04
129	#define SR_SEL 0x02
130	#define SR_DBP 0x01
131
132	/*
133	* Setting a bit in this register will cause an interrupt to be generated when
134	* BSY is false and SEL true and this bit is asserted on the bus.
135	*/
136	#define SELECT_ENABLE_REG 4 /* wo */
137
138	#define BUS_AND_STATUS_REG 5 /* ro */
139	#define BASR_END_DMA_TRANSFER 0x80 /* ro set on end of transfer */
140	#define BASR_DRQ 0x40 /* ro mirror of DRQ pin */
141	#define BASR_PARITY_ERROR 0x20 /* ro parity error detected */
142	#define BASR_IRQ 0x10 /* ro mirror of IRQ pin */
143	#define BASR_PHASE_MATCH 0x08 /* ro Set when MSG CD IO match TCR */
144	#define BASR_BUSY_ERROR 0x04 /* ro Unexpected change to inactive state */
145	#define BASR_ATN 0x02 /* ro BUS status */
146	#define BASR_ACK 0x01 /* ro BUS status */
147
148	/* Write any value to this register to start a DMA send */
149	#define START_DMA_SEND_REG 5 /* wo */
150
151	/*
152	* Used in DMA transfer mode, data is latched from the SCSI bus on
153	* the falling edge of REQ (ini) or ACK (tgt)
154	*/
155	#define INPUT_DATA_REG 6 /* ro */
156
157	/* Write any value to this register to start a DMA receive */
158	#define START_DMA_TARGET_RECEIVE_REG 6 /* wo */
159
160	/* Read this register to clear interrupt conditions */
161	#define RESET_PARITY_INTERRUPT_REG 7 /* ro */
162
163	/* Write any value to this register to start an ini mode DMA receive */
164	#define START_DMA_INITIATOR_RECEIVE_REG 7 /* wo */
165
12150797	166	/* NCR 53C400(A) Control Status Register bits: */
1da177e4 LT	167	#define CSR_RESET 0x80 /* wo Resets 53c400 */
	168	#define CSR_53C80_REG 0x80 /* ro 5380 registers busy */
	169	#define CSR_TRANS_DIR 0x40 /* rw Data transfer direction */
	170	#define CSR_SCSI_BUFF_INTR 0x20 /* rw Enable int on transfer ready */
	171	#define CSR_53C80_INTR 0x10 /* rw Enable 53c80 interrupts */
	172	#define CSR_SHARED_INTR 0x08 /* rw Interrupt sharing */
	173	#define CSR_HOST_BUF_NOT_RDY 0x04 /* ro Is Host buffer ready */
	174	#define CSR_SCSI_BUF_RDY 0x02 /* ro SCSI buffer read */
	175	#define CSR_GATED_53C80_IRQ 0x01 /* ro Last block xferred */
	176
	177	#if 0
	178	#define CSR_BASE CSR_SCSI_BUFF_INTR \| CSR_53C80_INTR
	179	#else
	180	#define CSR_BASE CSR_53C80_INTR
	181	#endif
	182
1da177e4 LT	183	/* Note : PHASE_* macros are based on the values of the STATUS register */
	184	#define PHASE_MASK (SR_MSG \| SR_CD \| SR_IO)
	185
	186	#define PHASE_DATAOUT 0
	187	#define PHASE_DATAIN SR_IO
	188	#define PHASE_CMDOUT SR_CD
	189	#define PHASE_STATIN (SR_CD \| SR_IO)
	190	#define PHASE_MSGOUT (SR_MSG \| SR_CD)
	191	#define PHASE_MSGIN (SR_MSG \| SR_CD \| SR_IO)
	192	#define PHASE_UNKNOWN 0xff
	193
	194	/*
	195	* Convert status register phase to something we can use to set phase in
	196	* the target register so we can get phase mismatch interrupts on DMA
	197	* transfers.
	198	*/
	199
	200	#define PHASE_SR_TO_TCR(phase) ((phase) >> 2)
	201
1da177e4 LT	202	/*
	203	* These are "special" values for the irq and dma_channel fields of the
	204	* Scsi_Host structure
	205	*/
	206
1da177e4 LT	207	#define DMA_NONE 255
	208	#define IRQ_AUTO 254
	209	#define DMA_AUTO 254
	210	#define PORT_AUTO 0xffff /* autoprobe io port for 53c400a */
	211
22f5f10d FT	212	#ifndef NO_IRQ
	213	#define NO_IRQ 0
	214	#endif
	215
1bb46002	216	#define FLAG_DMA_FIXUP 1 /* Use DMA errata workarounds */
1da177e4	217	#define FLAG_NO_PSEUDO_DMA 8 /* Inhibit DMA */
ef1081cb	218	#define FLAG_LATE_DMA_SETUP 32 /* Setup NCR before DMA H/W */
9c3f0e2b	219	#define FLAG_TOSHIBA_DELAY 128 /* Allow for borken CD-ROMs */
1da177e4	220
1da177e4 LT	221	struct NCR5380_hostdata {
	222	NCR5380_implementation_fields; /* implementation specific */
	223	struct Scsi_Host host; / Host backpointer */
	224	unsigned char id_mask, id_higher_mask; /* 1 << id, all bits greater */
5299b3ca	225	unsigned char busy[8]; /* index = target, bit = lun */
5299b3ca	226	int dma_len; /* requested length of DMA */
5299b3ca FT	227	unsigned char last_message; /* last message OUT */
5299b3ca FT	228	struct scsi_cmnd connected; / currently connected cmnd */
707d62b3	229	struct scsi_cmnd selecting; / cmnd to be connected */
32b26a10	230	struct list_head unissued; /* waiting to be issued */
f27db8eb	231	struct list_head autosense; /* priority issue queue */
32b26a10	232	struct list_head disconnected; /* waiting for reconnect */
11d2f63b	233	spinlock_t lock; /* protects this struct */
1da177e4	234	int flags;
28424d3a	235	struct scsi_eh_save ses;
f27db8eb	236	struct scsi_cmnd *sensing;
8c32513b	237	char info[256];
ef1081cb FT	238	int read_overruns; /* number of bytes to cut from a
ef1081cb FT	239	* transfer to handle chip overruns */
a53a21e4	240	struct work_struct main_task;
0ad0eff9	241	struct workqueue_struct *work_q;
2f854b82	242	unsigned long accesses_per_ms; /* chip register accesses per ms */
1da177e4 LT	243	};
	244
	245	#ifdef __KERNEL__
	246
32b26a10 FT	247	struct NCR5380_cmd {
	248	struct list_head list;
	249	};
	250
	251	#define NCR5380_CMD_SIZE (sizeof(struct NCR5380_cmd))
	252
	253	static inline struct scsi_cmnd NCR5380_to_scmd(struct NCR5380_cmd ncmd_ptr)
	254	{
	255	return ((struct scsi_cmnd *)ncmd_ptr) - 1;
	256	}
	257
9829e528 FT	258	#ifndef NDEBUG
	259	#define NDEBUG (0)
	260	#endif
	261
16b9d870	262	#define dprintk(flg, fmt, ...) \
d61c5427 FT	263	do { if ((NDEBUG) & (flg)) \
d61c5427 FT	264	printk(KERN_DEBUG fmt, ## __VA_ARGS__); } while (0)
16b9d870	265
dbb6b350 FT	266	#define dsprintk(flg, host, fmt, ...) \
	267	do { if ((NDEBUG) & (flg)) \
	268	shost_printk(KERN_DEBUG, host, fmt, ## __VA_ARGS__); \
	269	} while (0)
	270
9829e528	271	#if NDEBUG
9829e528 FT	272	#define NCR5380_dprint(flg, arg) \
	273	do { if ((NDEBUG) & (flg)) NCR5380_print(arg); } while (0)
	274	#define NCR5380_dprint_phase(flg, arg) \
	275	do { if ((NDEBUG) & (flg)) NCR5380_print_phase(arg); } while (0)
	276	static void NCR5380_print_phase(struct Scsi_Host *instance);
	277	static void NCR5380_print(struct Scsi_Host *instance);
	278	#else
52a6a1cb FT	279	#define NCR5380_dprint(flg, arg) do {} while (0)
52a6a1cb FT	280	#define NCR5380_dprint_phase(flg, arg) do {} while (0)
9829e528	281	#endif
1da177e4	282
1da177e4	283	static int NCR5380_probe_irq(struct Scsi_Host *instance, int possible);
1da177e4	284	static int NCR5380_init(struct Scsi_Host *instance, int flags);
b6488f97	285	static int NCR5380_maybe_reset_bus(struct Scsi_Host *);
1da177e4 LT	286	static void NCR5380_exit(struct Scsi_Host *instance);
1da177e4 LT	287	static void NCR5380_information_transfer(struct Scsi_Host *instance);
7d12e780	288	static irqreturn_t NCR5380_intr(int irq, void *dev_id);
c4028958	289	static void NCR5380_main(struct work_struct *work);
8c32513b	290	static const char NCR5380_info(struct Scsi_Host instance);
1da177e4	291	static void NCR5380_reselect(struct Scsi_Host *instance);
707d62b3	292	static struct scsi_cmnd NCR5380_select(struct Scsi_Host , struct scsi_cmnd *);
1da177e4	293	static int NCR5380_transfer_dma(struct Scsi_Host instance, unsigned char phase, int count, unsigned char *data);
1da177e4	294	static int NCR5380_transfer_pio(struct Scsi_Host instance, unsigned char phase, int count, unsigned char *data);
3a0f64bf	295	static int NCR5380_poll_politely2(struct Scsi_Host *, int, int, int, int, int, int, int);
1da177e4	296
01f17641 FT	297	static inline int NCR5380_poll_politely(struct Scsi_Host *instance,
	298	int reg, int bit, int val, int wait)
	299	{
	300	return NCR5380_poll_politely2(instance, reg, bit, val,
	301	reg, bit, val, wait);
	302	}
	303
1da177e4	304	#endif /* __KERNEL__ */
1da177e4	305	#endif /* NCR5380_H */