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a3667aae NKI |
1 | /* |
2 | * This file is part of the Chelsio FCoE driver for Linux. | |
3 | * | |
4 | * Copyright (c) 2008-2012 Chelsio Communications, Inc. All rights reserved. | |
5 | * | |
6 | * This software is available to you under a choice of one of two | |
7 | * licenses. You may choose to be licensed under the terms of the GNU | |
8 | * General Public License (GPL) Version 2, available from the file | |
9 | * COPYING in the main directory of this source tree, or the | |
10 | * OpenIB.org BSD license below: | |
11 | * | |
12 | * Redistribution and use in source and binary forms, with or | |
13 | * without modification, are permitted provided that the following | |
14 | * conditions are met: | |
15 | * | |
16 | * - Redistributions of source code must retain the above | |
17 | * copyright notice, this list of conditions and the following | |
18 | * disclaimer. | |
19 | * | |
20 | * - Redistributions in binary form must reproduce the above | |
21 | * copyright notice, this list of conditions and the following | |
22 | * disclaimer in the documentation and/or other materials | |
23 | * provided with the distribution. | |
24 | * | |
25 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
26 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
27 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
28 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
29 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
30 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
31 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
32 | * SOFTWARE. | |
33 | */ | |
34 | ||
35 | #include <linux/delay.h> | |
36 | #include <linux/jiffies.h> | |
37 | #include <linux/string.h> | |
38 | #include <scsi/scsi_device.h> | |
39 | #include <scsi/scsi_transport_fc.h> | |
40 | ||
41 | #include "csio_hw.h" | |
42 | #include "csio_lnode.h" | |
43 | #include "csio_rnode.h" | |
44 | #include "csio_mb.h" | |
45 | #include "csio_wr.h" | |
46 | ||
47 | #define csio_mb_is_host_owner(__owner) ((__owner) == CSIO_MBOWNER_PL) | |
48 | ||
49 | /* MB Command/Response Helpers */ | |
50 | /* | |
51 | * csio_mb_fw_retval - FW return value from a mailbox response. | |
52 | * @mbp: Mailbox structure | |
53 | * | |
54 | */ | |
55 | enum fw_retval | |
56 | csio_mb_fw_retval(struct csio_mb *mbp) | |
57 | { | |
58 | struct fw_cmd_hdr *hdr; | |
59 | ||
60 | hdr = (struct fw_cmd_hdr *)(mbp->mb); | |
61 | ||
e2ac9628 | 62 | return FW_CMD_RETVAL_G(ntohl(hdr->lo)); |
a3667aae NKI |
63 | } |
64 | ||
65 | /* | |
66 | * csio_mb_hello - FW HELLO command helper | |
67 | * @hw: The HW structure | |
68 | * @mbp: Mailbox structure | |
69 | * @m_mbox: Master mailbox number, if any. | |
70 | * @a_mbox: Mailbox number for asycn notifications. | |
71 | * @master: Device mastership. | |
72 | * @cbfn: Callback, if any. | |
73 | * | |
74 | */ | |
75 | void | |
76 | csio_mb_hello(struct csio_hw *hw, struct csio_mb *mbp, uint32_t tmo, | |
77 | uint32_t m_mbox, uint32_t a_mbox, enum csio_dev_master master, | |
78 | void (*cbfn) (struct csio_hw *, struct csio_mb *)) | |
79 | { | |
80 | struct fw_hello_cmd *cmdp = (struct fw_hello_cmd *)(mbp->mb); | |
81 | ||
82 | CSIO_INIT_MBP(mbp, cmdp, tmo, hw, cbfn, 1); | |
83 | ||
e2ac9628 HS |
84 | cmdp->op_to_write = htonl(FW_CMD_OP_V(FW_HELLO_CMD) | |
85 | FW_CMD_REQUEST_F | FW_CMD_WRITE_F); | |
86 | cmdp->retval_len16 = htonl(FW_CMD_LEN16_V(sizeof(*cmdp) / 16)); | |
a3667aae | 87 | cmdp->err_to_clearinit = htonl( |
5167865a HS |
88 | FW_HELLO_CMD_MASTERDIS_V(master == CSIO_MASTER_CANT) | |
89 | FW_HELLO_CMD_MASTERFORCE_V(master == CSIO_MASTER_MUST) | | |
90 | FW_HELLO_CMD_MBMASTER_V(master == CSIO_MASTER_MUST ? | |
91 | m_mbox : FW_HELLO_CMD_MBMASTER_M) | | |
92 | FW_HELLO_CMD_MBASYNCNOT_V(a_mbox) | | |
93 | FW_HELLO_CMD_STAGE_V(fw_hello_cmd_stage_os) | | |
94 | FW_HELLO_CMD_CLEARINIT_F); | |
a3667aae NKI |
95 | |
96 | } | |
97 | ||
98 | /* | |
99 | * csio_mb_process_hello_rsp - FW HELLO response processing helper | |
100 | * @hw: The HW structure | |
101 | * @mbp: Mailbox structure | |
102 | * @retval: Mailbox return value from Firmware | |
103 | * @state: State that the function is in. | |
104 | * @mpfn: Master pfn | |
105 | * | |
106 | */ | |
107 | void | |
108 | csio_mb_process_hello_rsp(struct csio_hw *hw, struct csio_mb *mbp, | |
109 | enum fw_retval *retval, enum csio_dev_state *state, | |
110 | uint8_t *mpfn) | |
111 | { | |
112 | struct fw_hello_cmd *rsp = (struct fw_hello_cmd *)(mbp->mb); | |
113 | uint32_t value; | |
114 | ||
e2ac9628 | 115 | *retval = FW_CMD_RETVAL_G(ntohl(rsp->retval_len16)); |
a3667aae NKI |
116 | |
117 | if (*retval == FW_SUCCESS) { | |
118 | hw->fwrev = ntohl(rsp->fwrev); | |
119 | ||
120 | value = ntohl(rsp->err_to_clearinit); | |
5167865a | 121 | *mpfn = FW_HELLO_CMD_MBMASTER_G(value); |
a3667aae | 122 | |
5167865a | 123 | if (value & FW_HELLO_CMD_INIT_F) |
a3667aae | 124 | *state = CSIO_DEV_STATE_INIT; |
5167865a | 125 | else if (value & FW_HELLO_CMD_ERR_F) |
a3667aae NKI |
126 | *state = CSIO_DEV_STATE_ERR; |
127 | else | |
128 | *state = CSIO_DEV_STATE_UNINIT; | |
129 | } | |
130 | } | |
131 | ||
132 | /* | |
133 | * csio_mb_bye - FW BYE command helper | |
134 | * @hw: The HW structure | |
135 | * @mbp: Mailbox structure | |
136 | * @cbfn: Callback, if any. | |
137 | * | |
138 | */ | |
139 | void | |
140 | csio_mb_bye(struct csio_hw *hw, struct csio_mb *mbp, uint32_t tmo, | |
141 | void (*cbfn) (struct csio_hw *, struct csio_mb *)) | |
142 | { | |
143 | struct fw_bye_cmd *cmdp = (struct fw_bye_cmd *)(mbp->mb); | |
144 | ||
145 | CSIO_INIT_MBP(mbp, cmdp, tmo, hw, cbfn, 1); | |
146 | ||
e2ac9628 HS |
147 | cmdp->op_to_write = htonl(FW_CMD_OP_V(FW_BYE_CMD) | |
148 | FW_CMD_REQUEST_F | FW_CMD_WRITE_F); | |
149 | cmdp->retval_len16 = htonl(FW_CMD_LEN16_V(sizeof(*cmdp) / 16)); | |
a3667aae NKI |
150 | |
151 | } | |
152 | ||
153 | /* | |
154 | * csio_mb_reset - FW RESET command helper | |
155 | * @hw: The HW structure | |
156 | * @mbp: Mailbox structure | |
157 | * @reset: Type of reset. | |
158 | * @cbfn: Callback, if any. | |
159 | * | |
160 | */ | |
161 | void | |
162 | csio_mb_reset(struct csio_hw *hw, struct csio_mb *mbp, uint32_t tmo, | |
163 | int reset, int halt, | |
164 | void (*cbfn) (struct csio_hw *, struct csio_mb *)) | |
165 | { | |
166 | struct fw_reset_cmd *cmdp = (struct fw_reset_cmd *)(mbp->mb); | |
167 | ||
168 | CSIO_INIT_MBP(mbp, cmdp, tmo, hw, cbfn, 1); | |
169 | ||
e2ac9628 HS |
170 | cmdp->op_to_write = htonl(FW_CMD_OP_V(FW_RESET_CMD) | |
171 | FW_CMD_REQUEST_F | FW_CMD_WRITE_F); | |
172 | cmdp->retval_len16 = htonl(FW_CMD_LEN16_V(sizeof(*cmdp) / 16)); | |
a3667aae NKI |
173 | cmdp->val = htonl(reset); |
174 | cmdp->halt_pkd = htonl(halt); | |
175 | ||
176 | } | |
177 | ||
178 | /* | |
179 | * csio_mb_params - FW PARAMS command helper | |
180 | * @hw: The HW structure | |
181 | * @mbp: Mailbox structure | |
182 | * @tmo: Command timeout. | |
183 | * @pf: PF number. | |
184 | * @vf: VF number. | |
b23f7a09 | 185 | * @nparams: Number of parameters |
a3667aae NKI |
186 | * @params: Parameter mnemonic array. |
187 | * @val: Parameter value array. | |
188 | * @wr: Write/Read PARAMS. | |
189 | * @cbfn: Callback, if any. | |
190 | * | |
191 | */ | |
192 | void | |
193 | csio_mb_params(struct csio_hw *hw, struct csio_mb *mbp, uint32_t tmo, | |
194 | unsigned int pf, unsigned int vf, unsigned int nparams, | |
195 | const u32 *params, u32 *val, bool wr, | |
196 | void (*cbfn)(struct csio_hw *, struct csio_mb *)) | |
197 | { | |
198 | uint32_t i; | |
199 | uint32_t temp_params = 0, temp_val = 0; | |
200 | struct fw_params_cmd *cmdp = (struct fw_params_cmd *)(mbp->mb); | |
201 | __be32 *p = &cmdp->param[0].mnem; | |
202 | ||
203 | CSIO_INIT_MBP(mbp, cmdp, tmo, hw, cbfn, 1); | |
204 | ||
e2ac9628 HS |
205 | cmdp->op_to_vfn = htonl(FW_CMD_OP_V(FW_PARAMS_CMD) | |
206 | FW_CMD_REQUEST_F | | |
207 | (wr ? FW_CMD_WRITE_F : FW_CMD_READ_F) | | |
5167865a HS |
208 | FW_PARAMS_CMD_PFN_V(pf) | |
209 | FW_PARAMS_CMD_VFN_V(vf)); | |
e2ac9628 | 210 | cmdp->retval_len16 = htonl(FW_CMD_LEN16_V(sizeof(*cmdp) / 16)); |
a3667aae NKI |
211 | |
212 | /* Write Params */ | |
213 | if (wr) { | |
214 | while (nparams--) { | |
215 | temp_params = *params++; | |
216 | temp_val = *val++; | |
217 | ||
218 | *p++ = htonl(temp_params); | |
219 | *p++ = htonl(temp_val); | |
220 | } | |
221 | } else { | |
222 | for (i = 0; i < nparams; i++, p += 2) { | |
223 | temp_params = *params++; | |
224 | *p = htonl(temp_params); | |
225 | } | |
226 | } | |
227 | ||
228 | } | |
229 | ||
230 | /* | |
231 | * csio_mb_process_read_params_rsp - FW PARAMS response processing helper | |
232 | * @hw: The HW structure | |
233 | * @mbp: Mailbox structure | |
234 | * @retval: Mailbox return value from Firmware | |
235 | * @nparams: Number of parameters | |
236 | * @val: Parameter value array. | |
237 | * | |
238 | */ | |
239 | void | |
240 | csio_mb_process_read_params_rsp(struct csio_hw *hw, struct csio_mb *mbp, | |
241 | enum fw_retval *retval, unsigned int nparams, | |
242 | u32 *val) | |
243 | { | |
244 | struct fw_params_cmd *rsp = (struct fw_params_cmd *)(mbp->mb); | |
245 | uint32_t i; | |
246 | __be32 *p = &rsp->param[0].val; | |
247 | ||
e2ac9628 | 248 | *retval = FW_CMD_RETVAL_G(ntohl(rsp->retval_len16)); |
a3667aae NKI |
249 | |
250 | if (*retval == FW_SUCCESS) | |
251 | for (i = 0; i < nparams; i++, p += 2) | |
252 | *val++ = ntohl(*p); | |
253 | } | |
254 | ||
255 | /* | |
256 | * csio_mb_ldst - FW LDST command | |
257 | * @hw: The HW structure | |
258 | * @mbp: Mailbox structure | |
259 | * @tmo: timeout | |
260 | * @reg: register | |
261 | * | |
262 | */ | |
263 | void | |
264 | csio_mb_ldst(struct csio_hw *hw, struct csio_mb *mbp, uint32_t tmo, int reg) | |
265 | { | |
266 | struct fw_ldst_cmd *ldst_cmd = (struct fw_ldst_cmd *)(mbp->mb); | |
267 | CSIO_INIT_MBP(mbp, ldst_cmd, tmo, hw, NULL, 1); | |
268 | ||
269 | /* | |
270 | * Construct and send the Firmware LDST Command to retrieve the | |
271 | * specified PCI-E Configuration Space register. | |
272 | */ | |
273 | ldst_cmd->op_to_addrspace = | |
e2ac9628 HS |
274 | htonl(FW_CMD_OP_V(FW_LDST_CMD) | |
275 | FW_CMD_REQUEST_F | | |
276 | FW_CMD_READ_F | | |
5167865a | 277 | FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FUNC_PCIE)); |
a3667aae | 278 | ldst_cmd->cycles_to_len16 = htonl(FW_LEN16(struct fw_ldst_cmd)); |
5167865a | 279 | ldst_cmd->u.pcie.select_naccess = FW_LDST_CMD_NACCESS_V(1); |
a3667aae | 280 | ldst_cmd->u.pcie.ctrl_to_fn = |
5167865a | 281 | (FW_LDST_CMD_LC_F | FW_LDST_CMD_FN_V(hw->pfn)); |
a3667aae NKI |
282 | ldst_cmd->u.pcie.r = (uint8_t)reg; |
283 | } | |
284 | ||
285 | /* | |
286 | * | |
287 | * csio_mb_caps_config - FW Read/Write Capabilities command helper | |
288 | * @hw: The HW structure | |
289 | * @mbp: Mailbox structure | |
290 | * @wr: Write if 1, Read if 0 | |
291 | * @init: Turn on initiator mode. | |
292 | * @tgt: Turn on target mode. | |
293 | * @cofld: If 1, Control Offload for FCoE | |
294 | * @cbfn: Callback, if any. | |
295 | * | |
296 | * This helper assumes that cmdp has MB payload from a previous CAPS | |
297 | * read command. | |
298 | */ | |
299 | void | |
300 | csio_mb_caps_config(struct csio_hw *hw, struct csio_mb *mbp, uint32_t tmo, | |
301 | bool wr, bool init, bool tgt, bool cofld, | |
302 | void (*cbfn) (struct csio_hw *, struct csio_mb *)) | |
303 | { | |
304 | struct fw_caps_config_cmd *cmdp = | |
305 | (struct fw_caps_config_cmd *)(mbp->mb); | |
306 | ||
307 | CSIO_INIT_MBP(mbp, cmdp, tmo, hw, cbfn, wr ? 0 : 1); | |
308 | ||
e2ac9628 HS |
309 | cmdp->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | |
310 | FW_CMD_REQUEST_F | | |
311 | (wr ? FW_CMD_WRITE_F : FW_CMD_READ_F)); | |
312 | cmdp->cfvalid_to_len16 = htonl(FW_CMD_LEN16_V(sizeof(*cmdp) / 16)); | |
a3667aae NKI |
313 | |
314 | /* Read config */ | |
315 | if (!wr) | |
316 | return; | |
317 | ||
318 | /* Write config */ | |
319 | cmdp->fcoecaps = 0; | |
320 | ||
321 | if (cofld) | |
322 | cmdp->fcoecaps |= htons(FW_CAPS_CONFIG_FCOE_CTRL_OFLD); | |
323 | if (init) | |
324 | cmdp->fcoecaps |= htons(FW_CAPS_CONFIG_FCOE_INITIATOR); | |
325 | if (tgt) | |
326 | cmdp->fcoecaps |= htons(FW_CAPS_CONFIG_FCOE_TARGET); | |
327 | } | |
328 | ||
a3667aae NKI |
329 | #define CSIO_ADVERT_MASK (FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G |\ |
330 | FW_PORT_CAP_SPEED_10G | FW_PORT_CAP_ANEG) | |
331 | ||
332 | /* | |
333 | * csio_mb_port- FW PORT command helper | |
334 | * @hw: The HW structure | |
335 | * @mbp: Mailbox structure | |
336 | * @tmo: COmmand timeout | |
337 | * @portid: Port ID to get/set info | |
338 | * @wr: Write/Read PORT information. | |
339 | * @fc: Flow control | |
340 | * @caps: Port capabilites to set. | |
341 | * @cbfn: Callback, if any. | |
342 | * | |
343 | */ | |
344 | void | |
345 | csio_mb_port(struct csio_hw *hw, struct csio_mb *mbp, uint32_t tmo, | |
346 | uint8_t portid, bool wr, uint32_t fc, uint16_t caps, | |
347 | void (*cbfn) (struct csio_hw *, struct csio_mb *)) | |
348 | { | |
349 | struct fw_port_cmd *cmdp = (struct fw_port_cmd *)(mbp->mb); | |
2b5fb1f2 | 350 | unsigned int lfc = 0, mdi = FW_PORT_CAP_MDI_V(FW_PORT_CAP_MDI_AUTO); |
a3667aae NKI |
351 | |
352 | CSIO_INIT_MBP(mbp, cmdp, tmo, hw, cbfn, 1); | |
353 | ||
e2ac9628 HS |
354 | cmdp->op_to_portid = htonl(FW_CMD_OP_V(FW_PORT_CMD) | |
355 | FW_CMD_REQUEST_F | | |
356 | (wr ? FW_CMD_EXEC_F : FW_CMD_READ_F) | | |
2b5fb1f2 | 357 | FW_PORT_CMD_PORTID_V(portid)); |
a3667aae NKI |
358 | if (!wr) { |
359 | cmdp->action_to_len16 = htonl( | |
2b5fb1f2 | 360 | FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_GET_PORT_INFO) | |
e2ac9628 | 361 | FW_CMD_LEN16_V(sizeof(*cmdp) / 16)); |
a3667aae NKI |
362 | return; |
363 | } | |
364 | ||
365 | /* Set port */ | |
366 | cmdp->action_to_len16 = htonl( | |
2b5fb1f2 | 367 | FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_L1_CFG) | |
e2ac9628 | 368 | FW_CMD_LEN16_V(sizeof(*cmdp) / 16)); |
a3667aae NKI |
369 | |
370 | if (fc & PAUSE_RX) | |
371 | lfc |= FW_PORT_CAP_FC_RX; | |
372 | if (fc & PAUSE_TX) | |
373 | lfc |= FW_PORT_CAP_FC_TX; | |
374 | ||
375 | if (!(caps & FW_PORT_CAP_ANEG)) | |
376 | cmdp->u.l1cfg.rcap = htonl((caps & CSIO_ADVERT_MASK) | lfc); | |
377 | else | |
378 | cmdp->u.l1cfg.rcap = htonl((caps & CSIO_ADVERT_MASK) | | |
379 | lfc | mdi); | |
380 | } | |
381 | ||
382 | /* | |
383 | * csio_mb_process_read_port_rsp - FW PORT command response processing helper | |
384 | * @hw: The HW structure | |
385 | * @mbp: Mailbox structure | |
386 | * @retval: Mailbox return value from Firmware | |
387 | * @caps: port capabilities | |
388 | * | |
389 | */ | |
390 | void | |
391 | csio_mb_process_read_port_rsp(struct csio_hw *hw, struct csio_mb *mbp, | |
392 | enum fw_retval *retval, uint16_t *caps) | |
393 | { | |
394 | struct fw_port_cmd *rsp = (struct fw_port_cmd *)(mbp->mb); | |
395 | ||
e2ac9628 | 396 | *retval = FW_CMD_RETVAL_G(ntohl(rsp->action_to_len16)); |
a3667aae NKI |
397 | |
398 | if (*retval == FW_SUCCESS) | |
399 | *caps = ntohs(rsp->u.info.pcap); | |
400 | } | |
401 | ||
402 | /* | |
403 | * csio_mb_initialize - FW INITIALIZE command helper | |
404 | * @hw: The HW structure | |
405 | * @mbp: Mailbox structure | |
406 | * @tmo: COmmand timeout | |
407 | * @cbfn: Callback, if any. | |
408 | * | |
409 | */ | |
410 | void | |
411 | csio_mb_initialize(struct csio_hw *hw, struct csio_mb *mbp, uint32_t tmo, | |
412 | void (*cbfn) (struct csio_hw *, struct csio_mb *)) | |
413 | { | |
414 | struct fw_initialize_cmd *cmdp = (struct fw_initialize_cmd *)(mbp->mb); | |
415 | ||
416 | CSIO_INIT_MBP(mbp, cmdp, tmo, hw, cbfn, 1); | |
417 | ||
e2ac9628 HS |
418 | cmdp->op_to_write = htonl(FW_CMD_OP_V(FW_INITIALIZE_CMD) | |
419 | FW_CMD_REQUEST_F | FW_CMD_WRITE_F); | |
420 | cmdp->retval_len16 = htonl(FW_CMD_LEN16_V(sizeof(*cmdp) / 16)); | |
a3667aae NKI |
421 | |
422 | } | |
423 | ||
424 | /* | |
425 | * csio_mb_iq_alloc - Initializes the mailbox to allocate an | |
426 | * Ingress DMA queue in the firmware. | |
427 | * | |
428 | * @hw: The hw structure | |
429 | * @mbp: Mailbox structure to initialize | |
430 | * @priv: Private object | |
431 | * @mb_tmo: Mailbox time-out period (in ms). | |
432 | * @iq_params: Ingress queue params needed for allocation. | |
433 | * @cbfn: The call-back function | |
434 | * | |
435 | * | |
436 | */ | |
437 | static void | |
438 | csio_mb_iq_alloc(struct csio_hw *hw, struct csio_mb *mbp, void *priv, | |
439 | uint32_t mb_tmo, struct csio_iq_params *iq_params, | |
440 | void (*cbfn) (struct csio_hw *, struct csio_mb *)) | |
441 | { | |
442 | struct fw_iq_cmd *cmdp = (struct fw_iq_cmd *)(mbp->mb); | |
443 | ||
444 | CSIO_INIT_MBP(mbp, cmdp, mb_tmo, priv, cbfn, 1); | |
445 | ||
e2ac9628 HS |
446 | cmdp->op_to_vfn = htonl(FW_CMD_OP_V(FW_IQ_CMD) | |
447 | FW_CMD_REQUEST_F | FW_CMD_EXEC_F | | |
6e4b51a6 HS |
448 | FW_IQ_CMD_PFN_V(iq_params->pfn) | |
449 | FW_IQ_CMD_VFN_V(iq_params->vfn)); | |
a3667aae | 450 | |
6e4b51a6 | 451 | cmdp->alloc_to_len16 = htonl(FW_IQ_CMD_ALLOC_F | |
e2ac9628 | 452 | FW_CMD_LEN16_V(sizeof(*cmdp) / 16)); |
a3667aae NKI |
453 | |
454 | cmdp->type_to_iqandstindex = htonl( | |
6e4b51a6 HS |
455 | FW_IQ_CMD_VIID_V(iq_params->viid) | |
456 | FW_IQ_CMD_TYPE_V(iq_params->type) | | |
457 | FW_IQ_CMD_IQASYNCH_V(iq_params->iqasynch)); | |
a3667aae NKI |
458 | |
459 | cmdp->fl0size = htons(iq_params->fl0size); | |
460 | cmdp->fl0size = htons(iq_params->fl1size); | |
461 | ||
462 | } /* csio_mb_iq_alloc */ | |
463 | ||
464 | /* | |
465 | * csio_mb_iq_write - Initializes the mailbox for writing into an | |
466 | * Ingress DMA Queue. | |
467 | * | |
468 | * @hw: The HW structure | |
469 | * @mbp: Mailbox structure to initialize | |
470 | * @priv: Private object | |
471 | * @mb_tmo: Mailbox time-out period (in ms). | |
472 | * @cascaded_req: TRUE - if this request is cascased with iq-alloc request. | |
473 | * @iq_params: Ingress queue params needed for writing. | |
474 | * @cbfn: The call-back function | |
475 | * | |
476 | * NOTE: We OR relevant bits with cmdp->XXX, instead of just equating, | |
477 | * because this IQ write request can be cascaded with a previous | |
478 | * IQ alloc request, and we dont want to over-write the bits set by | |
479 | * that request. This logic will work even in a non-cascaded case, since the | |
480 | * cmdp structure is zeroed out by CSIO_INIT_MBP. | |
481 | */ | |
482 | static void | |
483 | csio_mb_iq_write(struct csio_hw *hw, struct csio_mb *mbp, void *priv, | |
484 | uint32_t mb_tmo, bool cascaded_req, | |
485 | struct csio_iq_params *iq_params, | |
486 | void (*cbfn) (struct csio_hw *, struct csio_mb *)) | |
487 | { | |
488 | struct fw_iq_cmd *cmdp = (struct fw_iq_cmd *)(mbp->mb); | |
489 | ||
490 | uint32_t iq_start_stop = (iq_params->iq_start) ? | |
6e4b51a6 HS |
491 | FW_IQ_CMD_IQSTART_F : |
492 | FW_IQ_CMD_IQSTOP_F; | |
a3667aae NKI |
493 | |
494 | /* | |
495 | * If this IQ write is cascaded with IQ alloc request, do not | |
496 | * re-initialize with 0's. | |
497 | * | |
498 | */ | |
499 | if (!cascaded_req) | |
500 | CSIO_INIT_MBP(mbp, cmdp, mb_tmo, priv, cbfn, 1); | |
501 | ||
e2ac9628 HS |
502 | cmdp->op_to_vfn |= htonl(FW_CMD_OP_V(FW_IQ_CMD) | |
503 | FW_CMD_REQUEST_F | FW_CMD_WRITE_F | | |
6e4b51a6 HS |
504 | FW_IQ_CMD_PFN_V(iq_params->pfn) | |
505 | FW_IQ_CMD_VFN_V(iq_params->vfn)); | |
a3667aae | 506 | cmdp->alloc_to_len16 |= htonl(iq_start_stop | |
e2ac9628 | 507 | FW_CMD_LEN16_V(sizeof(*cmdp) / 16)); |
a3667aae NKI |
508 | cmdp->iqid |= htons(iq_params->iqid); |
509 | cmdp->fl0id |= htons(iq_params->fl0id); | |
510 | cmdp->fl1id |= htons(iq_params->fl1id); | |
511 | cmdp->type_to_iqandstindex |= htonl( | |
6e4b51a6 HS |
512 | FW_IQ_CMD_IQANDST_V(iq_params->iqandst) | |
513 | FW_IQ_CMD_IQANUS_V(iq_params->iqanus) | | |
514 | FW_IQ_CMD_IQANUD_V(iq_params->iqanud) | | |
515 | FW_IQ_CMD_IQANDSTINDEX_V(iq_params->iqandstindex)); | |
a3667aae | 516 | cmdp->iqdroprss_to_iqesize |= htons( |
6e4b51a6 HS |
517 | FW_IQ_CMD_IQPCIECH_V(iq_params->iqpciech) | |
518 | FW_IQ_CMD_IQDCAEN_V(iq_params->iqdcaen) | | |
519 | FW_IQ_CMD_IQDCACPU_V(iq_params->iqdcacpu) | | |
520 | FW_IQ_CMD_IQINTCNTTHRESH_V(iq_params->iqintcntthresh) | | |
521 | FW_IQ_CMD_IQCPRIO_V(iq_params->iqcprio) | | |
522 | FW_IQ_CMD_IQESIZE_V(iq_params->iqesize)); | |
a3667aae NKI |
523 | |
524 | cmdp->iqsize |= htons(iq_params->iqsize); | |
525 | cmdp->iqaddr |= cpu_to_be64(iq_params->iqaddr); | |
526 | ||
527 | if (iq_params->type == 0) { | |
528 | cmdp->iqns_to_fl0congen |= htonl( | |
6e4b51a6 HS |
529 | FW_IQ_CMD_IQFLINTIQHSEN_V(iq_params->iqflintiqhsen)| |
530 | FW_IQ_CMD_IQFLINTCONGEN_V(iq_params->iqflintcongen)); | |
a3667aae NKI |
531 | } |
532 | ||
533 | if (iq_params->fl0size && iq_params->fl0addr && | |
534 | (iq_params->fl0id != 0xFFFF)) { | |
535 | ||
536 | cmdp->iqns_to_fl0congen |= htonl( | |
6e4b51a6 HS |
537 | FW_IQ_CMD_FL0HOSTFCMODE_V(iq_params->fl0hostfcmode)| |
538 | FW_IQ_CMD_FL0CPRIO_V(iq_params->fl0cprio) | | |
539 | FW_IQ_CMD_FL0PADEN_V(iq_params->fl0paden) | | |
540 | FW_IQ_CMD_FL0PACKEN_V(iq_params->fl0packen)); | |
a3667aae | 541 | cmdp->fl0dcaen_to_fl0cidxfthresh |= htons( |
6e4b51a6 HS |
542 | FW_IQ_CMD_FL0DCAEN_V(iq_params->fl0dcaen) | |
543 | FW_IQ_CMD_FL0DCACPU_V(iq_params->fl0dcacpu) | | |
544 | FW_IQ_CMD_FL0FBMIN_V(iq_params->fl0fbmin) | | |
545 | FW_IQ_CMD_FL0FBMAX_V(iq_params->fl0fbmax) | | |
546 | FW_IQ_CMD_FL0CIDXFTHRESH_V(iq_params->fl0cidxfthresh)); | |
a3667aae NKI |
547 | cmdp->fl0size |= htons(iq_params->fl0size); |
548 | cmdp->fl0addr |= cpu_to_be64(iq_params->fl0addr); | |
549 | } | |
550 | } /* csio_mb_iq_write */ | |
551 | ||
552 | /* | |
553 | * csio_mb_iq_alloc_write - Initializes the mailbox for allocating an | |
554 | * Ingress DMA Queue. | |
555 | * | |
556 | * @hw: The HW structure | |
557 | * @mbp: Mailbox structure to initialize | |
558 | * @priv: Private data. | |
559 | * @mb_tmo: Mailbox time-out period (in ms). | |
560 | * @iq_params: Ingress queue params needed for allocation & writing. | |
561 | * @cbfn: The call-back function | |
562 | * | |
563 | * | |
564 | */ | |
565 | void | |
566 | csio_mb_iq_alloc_write(struct csio_hw *hw, struct csio_mb *mbp, void *priv, | |
567 | uint32_t mb_tmo, struct csio_iq_params *iq_params, | |
568 | void (*cbfn) (struct csio_hw *, struct csio_mb *)) | |
569 | { | |
570 | csio_mb_iq_alloc(hw, mbp, priv, mb_tmo, iq_params, cbfn); | |
571 | csio_mb_iq_write(hw, mbp, priv, mb_tmo, true, iq_params, cbfn); | |
572 | } /* csio_mb_iq_alloc_write */ | |
573 | ||
574 | /* | |
575 | * csio_mb_iq_alloc_write_rsp - Process the allocation & writing | |
576 | * of ingress DMA queue mailbox's response. | |
577 | * | |
578 | * @hw: The HW structure. | |
579 | * @mbp: Mailbox structure to initialize. | |
580 | * @retval: Firmware return value. | |
581 | * @iq_params: Ingress queue parameters, after allocation and write. | |
582 | * | |
583 | */ | |
584 | void | |
585 | csio_mb_iq_alloc_write_rsp(struct csio_hw *hw, struct csio_mb *mbp, | |
586 | enum fw_retval *ret_val, | |
587 | struct csio_iq_params *iq_params) | |
588 | { | |
589 | struct fw_iq_cmd *rsp = (struct fw_iq_cmd *)(mbp->mb); | |
590 | ||
e2ac9628 | 591 | *ret_val = FW_CMD_RETVAL_G(ntohl(rsp->alloc_to_len16)); |
a3667aae NKI |
592 | if (*ret_val == FW_SUCCESS) { |
593 | iq_params->physiqid = ntohs(rsp->physiqid); | |
594 | iq_params->iqid = ntohs(rsp->iqid); | |
595 | iq_params->fl0id = ntohs(rsp->fl0id); | |
596 | iq_params->fl1id = ntohs(rsp->fl1id); | |
597 | } else { | |
598 | iq_params->physiqid = iq_params->iqid = | |
599 | iq_params->fl0id = iq_params->fl1id = 0; | |
600 | } | |
601 | } /* csio_mb_iq_alloc_write_rsp */ | |
602 | ||
603 | /* | |
604 | * csio_mb_iq_free - Initializes the mailbox for freeing a | |
605 | * specified Ingress DMA Queue. | |
606 | * | |
607 | * @hw: The HW structure | |
608 | * @mbp: Mailbox structure to initialize | |
609 | * @priv: Private data | |
610 | * @mb_tmo: Mailbox time-out period (in ms). | |
611 | * @iq_params: Parameters of ingress queue, that is to be freed. | |
612 | * @cbfn: The call-back function | |
613 | * | |
614 | * | |
615 | */ | |
616 | void | |
617 | csio_mb_iq_free(struct csio_hw *hw, struct csio_mb *mbp, void *priv, | |
618 | uint32_t mb_tmo, struct csio_iq_params *iq_params, | |
619 | void (*cbfn) (struct csio_hw *, struct csio_mb *)) | |
620 | { | |
621 | struct fw_iq_cmd *cmdp = (struct fw_iq_cmd *)(mbp->mb); | |
622 | ||
623 | CSIO_INIT_MBP(mbp, cmdp, mb_tmo, priv, cbfn, 1); | |
624 | ||
e2ac9628 HS |
625 | cmdp->op_to_vfn = htonl(FW_CMD_OP_V(FW_IQ_CMD) | |
626 | FW_CMD_REQUEST_F | FW_CMD_EXEC_F | | |
6e4b51a6 HS |
627 | FW_IQ_CMD_PFN_V(iq_params->pfn) | |
628 | FW_IQ_CMD_VFN_V(iq_params->vfn)); | |
629 | cmdp->alloc_to_len16 = htonl(FW_IQ_CMD_FREE_F | | |
e2ac9628 | 630 | FW_CMD_LEN16_V(sizeof(*cmdp) / 16)); |
6e4b51a6 | 631 | cmdp->type_to_iqandstindex = htonl(FW_IQ_CMD_TYPE_V(iq_params->type)); |
a3667aae NKI |
632 | |
633 | cmdp->iqid = htons(iq_params->iqid); | |
634 | cmdp->fl0id = htons(iq_params->fl0id); | |
635 | cmdp->fl1id = htons(iq_params->fl1id); | |
636 | ||
637 | } /* csio_mb_iq_free */ | |
638 | ||
639 | /* | |
640 | * csio_mb_eq_ofld_alloc - Initializes the mailbox for allocating | |
641 | * an offload-egress queue. | |
642 | * | |
643 | * @hw: The HW structure | |
644 | * @mbp: Mailbox structure to initialize | |
645 | * @priv: Private data | |
646 | * @mb_tmo: Mailbox time-out period (in ms). | |
b23f7a09 | 647 | * @eq_ofld_params: (Offload) Egress queue parameters. |
a3667aae NKI |
648 | * @cbfn: The call-back function |
649 | * | |
650 | * | |
651 | */ | |
652 | static void | |
653 | csio_mb_eq_ofld_alloc(struct csio_hw *hw, struct csio_mb *mbp, void *priv, | |
654 | uint32_t mb_tmo, struct csio_eq_params *eq_ofld_params, | |
655 | void (*cbfn) (struct csio_hw *, struct csio_mb *)) | |
656 | { | |
657 | struct fw_eq_ofld_cmd *cmdp = (struct fw_eq_ofld_cmd *)(mbp->mb); | |
658 | ||
659 | CSIO_INIT_MBP(mbp, cmdp, mb_tmo, priv, cbfn, 1); | |
e2ac9628 HS |
660 | cmdp->op_to_vfn = htonl(FW_CMD_OP_V(FW_EQ_OFLD_CMD) | |
661 | FW_CMD_REQUEST_F | FW_CMD_EXEC_F | | |
6e4b51a6 HS |
662 | FW_EQ_OFLD_CMD_PFN_V(eq_ofld_params->pfn) | |
663 | FW_EQ_OFLD_CMD_VFN_V(eq_ofld_params->vfn)); | |
664 | cmdp->alloc_to_len16 = htonl(FW_EQ_OFLD_CMD_ALLOC_F | | |
e2ac9628 | 665 | FW_CMD_LEN16_V(sizeof(*cmdp) / 16)); |
a3667aae NKI |
666 | |
667 | } /* csio_mb_eq_ofld_alloc */ | |
668 | ||
669 | /* | |
670 | * csio_mb_eq_ofld_write - Initializes the mailbox for writing | |
671 | * an alloacted offload-egress queue. | |
672 | * | |
673 | * @hw: The HW structure | |
674 | * @mbp: Mailbox structure to initialize | |
675 | * @priv: Private data | |
676 | * @mb_tmo: Mailbox time-out period (in ms). | |
677 | * @cascaded_req: TRUE - if this request is cascased with Eq-alloc request. | |
b23f7a09 | 678 | * @eq_ofld_params: (Offload) Egress queue parameters. |
a3667aae NKI |
679 | * @cbfn: The call-back function |
680 | * | |
681 | * | |
682 | * NOTE: We OR relevant bits with cmdp->XXX, instead of just equating, | |
683 | * because this EQ write request can be cascaded with a previous | |
684 | * EQ alloc request, and we dont want to over-write the bits set by | |
685 | * that request. This logic will work even in a non-cascaded case, since the | |
686 | * cmdp structure is zeroed out by CSIO_INIT_MBP. | |
687 | */ | |
688 | static void | |
689 | csio_mb_eq_ofld_write(struct csio_hw *hw, struct csio_mb *mbp, void *priv, | |
690 | uint32_t mb_tmo, bool cascaded_req, | |
691 | struct csio_eq_params *eq_ofld_params, | |
692 | void (*cbfn) (struct csio_hw *, struct csio_mb *)) | |
693 | { | |
694 | struct fw_eq_ofld_cmd *cmdp = (struct fw_eq_ofld_cmd *)(mbp->mb); | |
695 | ||
696 | uint32_t eq_start_stop = (eq_ofld_params->eqstart) ? | |
6e4b51a6 HS |
697 | FW_EQ_OFLD_CMD_EQSTART_F : |
698 | FW_EQ_OFLD_CMD_EQSTOP_F; | |
a3667aae NKI |
699 | |
700 | /* | |
701 | * If this EQ write is cascaded with EQ alloc request, do not | |
702 | * re-initialize with 0's. | |
703 | * | |
704 | */ | |
705 | if (!cascaded_req) | |
706 | CSIO_INIT_MBP(mbp, cmdp, mb_tmo, priv, cbfn, 1); | |
707 | ||
e2ac9628 HS |
708 | cmdp->op_to_vfn |= htonl(FW_CMD_OP_V(FW_EQ_OFLD_CMD) | |
709 | FW_CMD_REQUEST_F | FW_CMD_WRITE_F | | |
6e4b51a6 HS |
710 | FW_EQ_OFLD_CMD_PFN_V(eq_ofld_params->pfn) | |
711 | FW_EQ_OFLD_CMD_VFN_V(eq_ofld_params->vfn)); | |
a3667aae | 712 | cmdp->alloc_to_len16 |= htonl(eq_start_stop | |
e2ac9628 | 713 | FW_CMD_LEN16_V(sizeof(*cmdp) / 16)); |
a3667aae | 714 | |
6e4b51a6 | 715 | cmdp->eqid_pkd |= htonl(FW_EQ_OFLD_CMD_EQID_V(eq_ofld_params->eqid)); |
a3667aae NKI |
716 | |
717 | cmdp->fetchszm_to_iqid |= htonl( | |
6e4b51a6 HS |
718 | FW_EQ_OFLD_CMD_HOSTFCMODE_V(eq_ofld_params->hostfcmode) | |
719 | FW_EQ_OFLD_CMD_CPRIO_V(eq_ofld_params->cprio) | | |
720 | FW_EQ_OFLD_CMD_PCIECHN_V(eq_ofld_params->pciechn) | | |
721 | FW_EQ_OFLD_CMD_IQID_V(eq_ofld_params->iqid)); | |
a3667aae NKI |
722 | |
723 | cmdp->dcaen_to_eqsize |= htonl( | |
6e4b51a6 HS |
724 | FW_EQ_OFLD_CMD_DCAEN_V(eq_ofld_params->dcaen) | |
725 | FW_EQ_OFLD_CMD_DCACPU_V(eq_ofld_params->dcacpu) | | |
726 | FW_EQ_OFLD_CMD_FBMIN_V(eq_ofld_params->fbmin) | | |
727 | FW_EQ_OFLD_CMD_FBMAX_V(eq_ofld_params->fbmax) | | |
728 | FW_EQ_OFLD_CMD_CIDXFTHRESHO_V(eq_ofld_params->cidxfthresho) | | |
729 | FW_EQ_OFLD_CMD_CIDXFTHRESH_V(eq_ofld_params->cidxfthresh) | | |
730 | FW_EQ_OFLD_CMD_EQSIZE_V(eq_ofld_params->eqsize)); | |
a3667aae NKI |
731 | |
732 | cmdp->eqaddr |= cpu_to_be64(eq_ofld_params->eqaddr); | |
733 | ||
734 | } /* csio_mb_eq_ofld_write */ | |
735 | ||
736 | /* | |
737 | * csio_mb_eq_ofld_alloc_write - Initializes the mailbox for allocation | |
738 | * writing into an Engress DMA Queue. | |
739 | * | |
740 | * @hw: The HW structure | |
741 | * @mbp: Mailbox structure to initialize | |
742 | * @priv: Private data. | |
743 | * @mb_tmo: Mailbox time-out period (in ms). | |
b23f7a09 | 744 | * @eq_ofld_params: (Offload) Egress queue parameters. |
a3667aae NKI |
745 | * @cbfn: The call-back function |
746 | * | |
747 | * | |
748 | */ | |
749 | void | |
750 | csio_mb_eq_ofld_alloc_write(struct csio_hw *hw, struct csio_mb *mbp, | |
751 | void *priv, uint32_t mb_tmo, | |
752 | struct csio_eq_params *eq_ofld_params, | |
753 | void (*cbfn) (struct csio_hw *, struct csio_mb *)) | |
754 | { | |
755 | csio_mb_eq_ofld_alloc(hw, mbp, priv, mb_tmo, eq_ofld_params, cbfn); | |
756 | csio_mb_eq_ofld_write(hw, mbp, priv, mb_tmo, true, | |
757 | eq_ofld_params, cbfn); | |
758 | } /* csio_mb_eq_ofld_alloc_write */ | |
759 | ||
760 | /* | |
761 | * csio_mb_eq_ofld_alloc_write_rsp - Process the allocation | |
762 | * & write egress DMA queue mailbox's response. | |
763 | * | |
764 | * @hw: The HW structure. | |
765 | * @mbp: Mailbox structure to initialize. | |
766 | * @retval: Firmware return value. | |
b23f7a09 | 767 | * @eq_ofld_params: (Offload) Egress queue parameters. |
a3667aae NKI |
768 | * |
769 | */ | |
770 | void | |
771 | csio_mb_eq_ofld_alloc_write_rsp(struct csio_hw *hw, | |
772 | struct csio_mb *mbp, enum fw_retval *ret_val, | |
773 | struct csio_eq_params *eq_ofld_params) | |
774 | { | |
775 | struct fw_eq_ofld_cmd *rsp = (struct fw_eq_ofld_cmd *)(mbp->mb); | |
776 | ||
e2ac9628 | 777 | *ret_val = FW_CMD_RETVAL_G(ntohl(rsp->alloc_to_len16)); |
a3667aae NKI |
778 | |
779 | if (*ret_val == FW_SUCCESS) { | |
6e4b51a6 | 780 | eq_ofld_params->eqid = FW_EQ_OFLD_CMD_EQID_G( |
a3667aae | 781 | ntohl(rsp->eqid_pkd)); |
6e4b51a6 | 782 | eq_ofld_params->physeqid = FW_EQ_OFLD_CMD_PHYSEQID_G( |
a3667aae NKI |
783 | ntohl(rsp->physeqid_pkd)); |
784 | } else | |
785 | eq_ofld_params->eqid = 0; | |
786 | ||
787 | } /* csio_mb_eq_ofld_alloc_write_rsp */ | |
788 | ||
789 | /* | |
790 | * csio_mb_eq_ofld_free - Initializes the mailbox for freeing a | |
791 | * specified Engress DMA Queue. | |
792 | * | |
793 | * @hw: The HW structure | |
794 | * @mbp: Mailbox structure to initialize | |
795 | * @priv: Private data area. | |
796 | * @mb_tmo: Mailbox time-out period (in ms). | |
b23f7a09 | 797 | * @eq_ofld_params: (Offload) Egress queue parameters, that is to be freed. |
a3667aae NKI |
798 | * @cbfn: The call-back function |
799 | * | |
800 | * | |
801 | */ | |
802 | void | |
803 | csio_mb_eq_ofld_free(struct csio_hw *hw, struct csio_mb *mbp, void *priv, | |
804 | uint32_t mb_tmo, struct csio_eq_params *eq_ofld_params, | |
805 | void (*cbfn) (struct csio_hw *, struct csio_mb *)) | |
806 | { | |
807 | struct fw_eq_ofld_cmd *cmdp = (struct fw_eq_ofld_cmd *)(mbp->mb); | |
808 | ||
809 | CSIO_INIT_MBP(mbp, cmdp, mb_tmo, priv, cbfn, 1); | |
810 | ||
e2ac9628 HS |
811 | cmdp->op_to_vfn = htonl(FW_CMD_OP_V(FW_EQ_OFLD_CMD) | |
812 | FW_CMD_REQUEST_F | FW_CMD_EXEC_F | | |
6e4b51a6 HS |
813 | FW_EQ_OFLD_CMD_PFN_V(eq_ofld_params->pfn) | |
814 | FW_EQ_OFLD_CMD_VFN_V(eq_ofld_params->vfn)); | |
815 | cmdp->alloc_to_len16 = htonl(FW_EQ_OFLD_CMD_FREE_F | | |
e2ac9628 | 816 | FW_CMD_LEN16_V(sizeof(*cmdp) / 16)); |
6e4b51a6 | 817 | cmdp->eqid_pkd = htonl(FW_EQ_OFLD_CMD_EQID_V(eq_ofld_params->eqid)); |
a3667aae NKI |
818 | |
819 | } /* csio_mb_eq_ofld_free */ | |
820 | ||
821 | /* | |
822 | * csio_write_fcoe_link_cond_init_mb - Initialize Mailbox to write FCoE link | |
823 | * condition. | |
824 | * | |
825 | * @ln: The Lnode structure | |
826 | * @mbp: Mailbox structure to initialize | |
827 | * @mb_tmo: Mailbox time-out period (in ms). | |
828 | * @cbfn: The call back function. | |
829 | * | |
830 | * | |
831 | */ | |
832 | void | |
833 | csio_write_fcoe_link_cond_init_mb(struct csio_lnode *ln, struct csio_mb *mbp, | |
834 | uint32_t mb_tmo, uint8_t port_id, uint32_t sub_opcode, | |
835 | uint8_t cos, bool link_status, uint32_t fcfi, | |
836 | void (*cbfn) (struct csio_hw *, struct csio_mb *)) | |
837 | { | |
838 | struct fw_fcoe_link_cmd *cmdp = | |
839 | (struct fw_fcoe_link_cmd *)(mbp->mb); | |
840 | ||
841 | CSIO_INIT_MBP(mbp, cmdp, mb_tmo, ln, cbfn, 1); | |
842 | ||
843 | cmdp->op_to_portid = htonl(( | |
e2ac9628 HS |
844 | FW_CMD_OP_V(FW_FCOE_LINK_CMD) | |
845 | FW_CMD_REQUEST_F | | |
846 | FW_CMD_WRITE_F | | |
a3667aae NKI |
847 | FW_FCOE_LINK_CMD_PORTID(port_id))); |
848 | cmdp->sub_opcode_fcfi = htonl( | |
849 | FW_FCOE_LINK_CMD_SUB_OPCODE(sub_opcode) | | |
850 | FW_FCOE_LINK_CMD_FCFI(fcfi)); | |
851 | cmdp->lstatus = link_status; | |
e2ac9628 | 852 | cmdp->retval_len16 = htonl(FW_CMD_LEN16_V(sizeof(*cmdp) / 16)); |
a3667aae NKI |
853 | |
854 | } /* csio_write_fcoe_link_cond_init_mb */ | |
855 | ||
856 | /* | |
857 | * csio_fcoe_read_res_info_init_mb - Initializes the mailbox for reading FCoE | |
858 | * resource information(FW_GET_RES_INFO_CMD). | |
859 | * | |
860 | * @hw: The HW structure | |
861 | * @mbp: Mailbox structure to initialize | |
862 | * @mb_tmo: Mailbox time-out period (in ms). | |
863 | * @cbfn: The call-back function | |
864 | * | |
865 | * | |
866 | */ | |
867 | void | |
868 | csio_fcoe_read_res_info_init_mb(struct csio_hw *hw, struct csio_mb *mbp, | |
869 | uint32_t mb_tmo, | |
870 | void (*cbfn) (struct csio_hw *, struct csio_mb *)) | |
871 | { | |
872 | struct fw_fcoe_res_info_cmd *cmdp = | |
873 | (struct fw_fcoe_res_info_cmd *)(mbp->mb); | |
874 | ||
875 | CSIO_INIT_MBP(mbp, cmdp, mb_tmo, hw, cbfn, 1); | |
876 | ||
e2ac9628 HS |
877 | cmdp->op_to_read = htonl((FW_CMD_OP_V(FW_FCOE_RES_INFO_CMD) | |
878 | FW_CMD_REQUEST_F | | |
879 | FW_CMD_READ_F)); | |
a3667aae | 880 | |
e2ac9628 | 881 | cmdp->retval_len16 = htonl(FW_CMD_LEN16_V(sizeof(*cmdp) / 16)); |
a3667aae NKI |
882 | |
883 | } /* csio_fcoe_read_res_info_init_mb */ | |
884 | ||
885 | /* | |
886 | * csio_fcoe_vnp_alloc_init_mb - Initializes the mailbox for allocating VNP | |
887 | * in the firmware (FW_FCOE_VNP_CMD). | |
888 | * | |
889 | * @ln: The Lnode structure. | |
890 | * @mbp: Mailbox structure to initialize. | |
891 | * @mb_tmo: Mailbox time-out period (in ms). | |
892 | * @fcfi: FCF Index. | |
893 | * @vnpi: vnpi | |
894 | * @iqid: iqid | |
895 | * @vnport_wwnn: vnport WWNN | |
896 | * @vnport_wwpn: vnport WWPN | |
897 | * @cbfn: The call-back function. | |
898 | * | |
899 | * | |
900 | */ | |
901 | void | |
902 | csio_fcoe_vnp_alloc_init_mb(struct csio_lnode *ln, struct csio_mb *mbp, | |
903 | uint32_t mb_tmo, uint32_t fcfi, uint32_t vnpi, uint16_t iqid, | |
904 | uint8_t vnport_wwnn[8], uint8_t vnport_wwpn[8], | |
905 | void (*cbfn) (struct csio_hw *, struct csio_mb *)) | |
906 | { | |
907 | struct fw_fcoe_vnp_cmd *cmdp = | |
908 | (struct fw_fcoe_vnp_cmd *)(mbp->mb); | |
909 | ||
910 | CSIO_INIT_MBP(mbp, cmdp, mb_tmo, ln, cbfn, 1); | |
911 | ||
e2ac9628 HS |
912 | cmdp->op_to_fcfi = htonl((FW_CMD_OP_V(FW_FCOE_VNP_CMD) | |
913 | FW_CMD_REQUEST_F | | |
914 | FW_CMD_EXEC_F | | |
a3667aae NKI |
915 | FW_FCOE_VNP_CMD_FCFI(fcfi))); |
916 | ||
917 | cmdp->alloc_to_len16 = htonl(FW_FCOE_VNP_CMD_ALLOC | | |
e2ac9628 | 918 | FW_CMD_LEN16_V(sizeof(*cmdp) / 16)); |
a3667aae NKI |
919 | |
920 | cmdp->gen_wwn_to_vnpi = htonl(FW_FCOE_VNP_CMD_VNPI(vnpi)); | |
921 | ||
922 | cmdp->iqid = htons(iqid); | |
923 | ||
924 | if (!wwn_to_u64(vnport_wwnn) && !wwn_to_u64(vnport_wwpn)) | |
925 | cmdp->gen_wwn_to_vnpi |= htonl(FW_FCOE_VNP_CMD_GEN_WWN); | |
926 | ||
927 | if (vnport_wwnn) | |
928 | memcpy(cmdp->vnport_wwnn, vnport_wwnn, 8); | |
929 | if (vnport_wwpn) | |
930 | memcpy(cmdp->vnport_wwpn, vnport_wwpn, 8); | |
931 | ||
932 | } /* csio_fcoe_vnp_alloc_init_mb */ | |
933 | ||
934 | /* | |
935 | * csio_fcoe_vnp_read_init_mb - Prepares VNP read cmd. | |
936 | * @ln: The Lnode structure. | |
937 | * @mbp: Mailbox structure to initialize. | |
938 | * @mb_tmo: Mailbox time-out period (in ms). | |
939 | * @fcfi: FCF Index. | |
940 | * @vnpi: vnpi | |
941 | * @cbfn: The call-back handler. | |
942 | */ | |
943 | void | |
944 | csio_fcoe_vnp_read_init_mb(struct csio_lnode *ln, struct csio_mb *mbp, | |
945 | uint32_t mb_tmo, uint32_t fcfi, uint32_t vnpi, | |
946 | void (*cbfn) (struct csio_hw *, struct csio_mb *)) | |
947 | { | |
948 | struct fw_fcoe_vnp_cmd *cmdp = | |
949 | (struct fw_fcoe_vnp_cmd *)(mbp->mb); | |
950 | ||
951 | CSIO_INIT_MBP(mbp, cmdp, mb_tmo, ln, cbfn, 1); | |
e2ac9628 HS |
952 | cmdp->op_to_fcfi = htonl(FW_CMD_OP_V(FW_FCOE_VNP_CMD) | |
953 | FW_CMD_REQUEST_F | | |
954 | FW_CMD_READ_F | | |
a3667aae | 955 | FW_FCOE_VNP_CMD_FCFI(fcfi)); |
e2ac9628 | 956 | cmdp->alloc_to_len16 = htonl(FW_CMD_LEN16_V(sizeof(*cmdp) / 16)); |
a3667aae NKI |
957 | cmdp->gen_wwn_to_vnpi = htonl(FW_FCOE_VNP_CMD_VNPI(vnpi)); |
958 | } | |
959 | ||
960 | /* | |
961 | * csio_fcoe_vnp_free_init_mb - Initializes the mailbox for freeing an | |
962 | * alloacted VNP in the firmware (FW_FCOE_VNP_CMD). | |
963 | * | |
964 | * @ln: The Lnode structure. | |
965 | * @mbp: Mailbox structure to initialize. | |
966 | * @mb_tmo: Mailbox time-out period (in ms). | |
967 | * @fcfi: FCF flow id | |
968 | * @vnpi: VNP flow id | |
969 | * @cbfn: The call-back function. | |
970 | * Return: None | |
971 | */ | |
972 | void | |
973 | csio_fcoe_vnp_free_init_mb(struct csio_lnode *ln, struct csio_mb *mbp, | |
974 | uint32_t mb_tmo, uint32_t fcfi, uint32_t vnpi, | |
975 | void (*cbfn) (struct csio_hw *, struct csio_mb *)) | |
976 | { | |
977 | struct fw_fcoe_vnp_cmd *cmdp = | |
978 | (struct fw_fcoe_vnp_cmd *)(mbp->mb); | |
979 | ||
980 | CSIO_INIT_MBP(mbp, cmdp, mb_tmo, ln, cbfn, 1); | |
981 | ||
e2ac9628 HS |
982 | cmdp->op_to_fcfi = htonl(FW_CMD_OP_V(FW_FCOE_VNP_CMD) | |
983 | FW_CMD_REQUEST_F | | |
984 | FW_CMD_EXEC_F | | |
a3667aae NKI |
985 | FW_FCOE_VNP_CMD_FCFI(fcfi)); |
986 | cmdp->alloc_to_len16 = htonl(FW_FCOE_VNP_CMD_FREE | | |
e2ac9628 | 987 | FW_CMD_LEN16_V(sizeof(*cmdp) / 16)); |
a3667aae NKI |
988 | cmdp->gen_wwn_to_vnpi = htonl(FW_FCOE_VNP_CMD_VNPI(vnpi)); |
989 | } | |
990 | ||
991 | /* | |
992 | * csio_fcoe_read_fcf_init_mb - Initializes the mailbox to read the | |
993 | * FCF records. | |
994 | * | |
995 | * @ln: The Lnode structure | |
996 | * @mbp: Mailbox structure to initialize | |
997 | * @mb_tmo: Mailbox time-out period (in ms). | |
998 | * @fcf_params: FC-Forwarder parameters. | |
999 | * @cbfn: The call-back function | |
1000 | * | |
1001 | * | |
1002 | */ | |
1003 | void | |
1004 | csio_fcoe_read_fcf_init_mb(struct csio_lnode *ln, struct csio_mb *mbp, | |
1005 | uint32_t mb_tmo, uint32_t portid, uint32_t fcfi, | |
1006 | void (*cbfn) (struct csio_hw *, struct csio_mb *)) | |
1007 | { | |
1008 | struct fw_fcoe_fcf_cmd *cmdp = | |
1009 | (struct fw_fcoe_fcf_cmd *)(mbp->mb); | |
1010 | ||
1011 | CSIO_INIT_MBP(mbp, cmdp, mb_tmo, ln, cbfn, 1); | |
1012 | ||
e2ac9628 HS |
1013 | cmdp->op_to_fcfi = htonl(FW_CMD_OP_V(FW_FCOE_FCF_CMD) | |
1014 | FW_CMD_REQUEST_F | | |
1015 | FW_CMD_READ_F | | |
a3667aae | 1016 | FW_FCOE_FCF_CMD_FCFI(fcfi)); |
e2ac9628 | 1017 | cmdp->retval_len16 = htonl(FW_CMD_LEN16_V(sizeof(*cmdp) / 16)); |
a3667aae NKI |
1018 | |
1019 | } /* csio_fcoe_read_fcf_init_mb */ | |
1020 | ||
1021 | void | |
1022 | csio_fcoe_read_portparams_init_mb(struct csio_hw *hw, struct csio_mb *mbp, | |
1023 | uint32_t mb_tmo, | |
1024 | struct fw_fcoe_port_cmd_params *portparams, | |
1025 | void (*cbfn)(struct csio_hw *, | |
1026 | struct csio_mb *)) | |
1027 | { | |
1028 | struct fw_fcoe_stats_cmd *cmdp = (struct fw_fcoe_stats_cmd *)(mbp->mb); | |
1029 | ||
1030 | CSIO_INIT_MBP(mbp, cmdp, mb_tmo, hw, cbfn, 1); | |
1031 | mbp->mb_size = 64; | |
1032 | ||
e2ac9628 HS |
1033 | cmdp->op_to_flowid = htonl(FW_CMD_OP_V(FW_FCOE_STATS_CMD) | |
1034 | FW_CMD_REQUEST_F | FW_CMD_READ_F); | |
1035 | cmdp->free_to_len16 = htonl(FW_CMD_LEN16_V(CSIO_MAX_MB_SIZE/16)); | |
a3667aae NKI |
1036 | |
1037 | cmdp->u.ctl.nstats_port = FW_FCOE_STATS_CMD_NSTATS(portparams->nstats) | | |
1038 | FW_FCOE_STATS_CMD_PORT(portparams->portid); | |
1039 | ||
1040 | cmdp->u.ctl.port_valid_ix = FW_FCOE_STATS_CMD_IX(portparams->idx) | | |
1041 | FW_FCOE_STATS_CMD_PORT_VALID; | |
1042 | ||
1043 | } /* csio_fcoe_read_portparams_init_mb */ | |
1044 | ||
1045 | void | |
5036f0a0 | 1046 | csio_mb_process_portparams_rsp(struct csio_hw *hw, |
a3667aae NKI |
1047 | struct csio_mb *mbp, |
1048 | enum fw_retval *retval, | |
1049 | struct fw_fcoe_port_cmd_params *portparams, | |
5036f0a0 | 1050 | struct fw_fcoe_port_stats *portstats) |
a3667aae NKI |
1051 | { |
1052 | struct fw_fcoe_stats_cmd *rsp = (struct fw_fcoe_stats_cmd *)(mbp->mb); | |
1053 | struct fw_fcoe_port_stats stats; | |
1054 | uint8_t *src; | |
1055 | uint8_t *dst; | |
1056 | ||
e2ac9628 | 1057 | *retval = FW_CMD_RETVAL_G(ntohl(rsp->free_to_len16)); |
a3667aae NKI |
1058 | |
1059 | memset(&stats, 0, sizeof(struct fw_fcoe_port_stats)); | |
1060 | ||
1061 | if (*retval == FW_SUCCESS) { | |
1062 | dst = (uint8_t *)(&stats) + ((portparams->idx - 1) * 8); | |
1063 | src = (uint8_t *)rsp + (CSIO_STATS_OFFSET * 8); | |
1064 | memcpy(dst, src, (portparams->nstats * 8)); | |
1065 | if (portparams->idx == 1) { | |
1066 | /* Get the first 6 flits from the Mailbox */ | |
5036f0a0 NKI |
1067 | portstats->tx_bcast_bytes = stats.tx_bcast_bytes; |
1068 | portstats->tx_bcast_frames = stats.tx_bcast_frames; | |
1069 | portstats->tx_mcast_bytes = stats.tx_mcast_bytes; | |
1070 | portstats->tx_mcast_frames = stats.tx_mcast_frames; | |
1071 | portstats->tx_ucast_bytes = stats.tx_ucast_bytes; | |
1072 | portstats->tx_ucast_frames = stats.tx_ucast_frames; | |
a3667aae NKI |
1073 | } |
1074 | if (portparams->idx == 7) { | |
1075 | /* Get the second 6 flits from the Mailbox */ | |
5036f0a0 NKI |
1076 | portstats->tx_drop_frames = stats.tx_drop_frames; |
1077 | portstats->tx_offload_bytes = stats.tx_offload_bytes; | |
1078 | portstats->tx_offload_frames = stats.tx_offload_frames; | |
a3667aae | 1079 | #if 0 |
5036f0a0 NKI |
1080 | portstats->rx_pf_bytes = stats.rx_pf_bytes; |
1081 | portstats->rx_pf_frames = stats.rx_pf_frames; | |
a3667aae | 1082 | #endif |
5036f0a0 NKI |
1083 | portstats->rx_bcast_bytes = stats.rx_bcast_bytes; |
1084 | portstats->rx_bcast_frames = stats.rx_bcast_frames; | |
1085 | portstats->rx_mcast_bytes = stats.rx_mcast_bytes; | |
a3667aae NKI |
1086 | } |
1087 | if (portparams->idx == 13) { | |
1088 | /* Get the last 4 flits from the Mailbox */ | |
5036f0a0 NKI |
1089 | portstats->rx_mcast_frames = stats.rx_mcast_frames; |
1090 | portstats->rx_ucast_bytes = stats.rx_ucast_bytes; | |
1091 | portstats->rx_ucast_frames = stats.rx_ucast_frames; | |
1092 | portstats->rx_err_frames = stats.rx_err_frames; | |
a3667aae NKI |
1093 | } |
1094 | } | |
1095 | } | |
1096 | ||
1097 | /* Entry points/APIs for MB module */ | |
1098 | /* | |
1099 | * csio_mb_intr_enable - Enable Interrupts from mailboxes. | |
1100 | * @hw: The HW structure | |
1101 | * | |
1102 | * Enables CIM interrupt bit in appropriate INT_ENABLE registers. | |
1103 | */ | |
1104 | void | |
1105 | csio_mb_intr_enable(struct csio_hw *hw) | |
1106 | { | |
89c3a86c HS |
1107 | csio_wr_reg32(hw, MBMSGRDYINTEN_F, MYPF_REG(CIM_PF_HOST_INT_ENABLE_A)); |
1108 | csio_rd_reg32(hw, MYPF_REG(CIM_PF_HOST_INT_ENABLE_A)); | |
a3667aae NKI |
1109 | } |
1110 | ||
1111 | /* | |
1112 | * csio_mb_intr_disable - Disable Interrupts from mailboxes. | |
1113 | * @hw: The HW structure | |
1114 | * | |
1115 | * Disable bit in HostInterruptEnable CIM register. | |
1116 | */ | |
1117 | void | |
1118 | csio_mb_intr_disable(struct csio_hw *hw) | |
1119 | { | |
89c3a86c HS |
1120 | csio_wr_reg32(hw, MBMSGRDYINTEN_V(0), |
1121 | MYPF_REG(CIM_PF_HOST_INT_ENABLE_A)); | |
1122 | csio_rd_reg32(hw, MYPF_REG(CIM_PF_HOST_INT_ENABLE_A)); | |
a3667aae NKI |
1123 | } |
1124 | ||
1125 | static void | |
1126 | csio_mb_dump_fw_dbg(struct csio_hw *hw, __be64 *cmd) | |
1127 | { | |
1128 | struct fw_debug_cmd *dbg = (struct fw_debug_cmd *)cmd; | |
1129 | ||
b2e1a3f0 | 1130 | if ((FW_DEBUG_CMD_TYPE_G(ntohl(dbg->op_type))) == 1) { |
a3667aae NKI |
1131 | csio_info(hw, "FW print message:\n"); |
1132 | csio_info(hw, "\tdebug->dprtstridx = %d\n", | |
1133 | ntohs(dbg->u.prt.dprtstridx)); | |
1134 | csio_info(hw, "\tdebug->dprtstrparam0 = 0x%x\n", | |
1135 | ntohl(dbg->u.prt.dprtstrparam0)); | |
1136 | csio_info(hw, "\tdebug->dprtstrparam1 = 0x%x\n", | |
1137 | ntohl(dbg->u.prt.dprtstrparam1)); | |
1138 | csio_info(hw, "\tdebug->dprtstrparam2 = 0x%x\n", | |
1139 | ntohl(dbg->u.prt.dprtstrparam2)); | |
1140 | csio_info(hw, "\tdebug->dprtstrparam3 = 0x%x\n", | |
1141 | ntohl(dbg->u.prt.dprtstrparam3)); | |
1142 | } else { | |
1143 | /* This is a FW assertion */ | |
1144 | csio_fatal(hw, "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n", | |
1145 | dbg->u.assert.filename_0_7, | |
1146 | ntohl(dbg->u.assert.line), | |
1147 | ntohl(dbg->u.assert.x), | |
1148 | ntohl(dbg->u.assert.y)); | |
1149 | } | |
1150 | } | |
1151 | ||
1152 | static void | |
1153 | csio_mb_debug_cmd_handler(struct csio_hw *hw) | |
1154 | { | |
1155 | int i; | |
1156 | __be64 cmd[CSIO_MB_MAX_REGS]; | |
89c3a86c HS |
1157 | uint32_t ctl_reg = PF_REG(hw->pfn, CIM_PF_MAILBOX_CTRL_A); |
1158 | uint32_t data_reg = PF_REG(hw->pfn, CIM_PF_MAILBOX_DATA_A); | |
a3667aae NKI |
1159 | int size = sizeof(struct fw_debug_cmd); |
1160 | ||
1161 | /* Copy mailbox data */ | |
1162 | for (i = 0; i < size; i += 8) | |
1163 | cmd[i / 8] = cpu_to_be64(csio_rd_reg64(hw, data_reg + i)); | |
1164 | ||
1165 | csio_mb_dump_fw_dbg(hw, cmd); | |
1166 | ||
1167 | /* Notify FW of mailbox by setting owner as UP */ | |
89c3a86c HS |
1168 | csio_wr_reg32(hw, MBMSGVALID_F | MBINTREQ_F | |
1169 | MBOWNER_V(CSIO_MBOWNER_FW), ctl_reg); | |
a3667aae NKI |
1170 | |
1171 | csio_rd_reg32(hw, ctl_reg); | |
1172 | wmb(); | |
1173 | } | |
1174 | ||
1175 | /* | |
1176 | * csio_mb_issue - generic routine for issuing Mailbox commands. | |
1177 | * @hw: The HW structure | |
1178 | * @mbp: Mailbox command to issue | |
1179 | * | |
1180 | * Caller should hold hw lock across this call. | |
1181 | */ | |
1182 | int | |
1183 | csio_mb_issue(struct csio_hw *hw, struct csio_mb *mbp) | |
1184 | { | |
1185 | uint32_t owner, ctl; | |
1186 | int i; | |
1187 | uint32_t ii; | |
1188 | __be64 *cmd = mbp->mb; | |
1189 | __be64 hdr; | |
1190 | struct csio_mbm *mbm = &hw->mbm; | |
89c3a86c HS |
1191 | uint32_t ctl_reg = PF_REG(hw->pfn, CIM_PF_MAILBOX_CTRL_A); |
1192 | uint32_t data_reg = PF_REG(hw->pfn, CIM_PF_MAILBOX_DATA_A); | |
a3667aae NKI |
1193 | int size = mbp->mb_size; |
1194 | int rv = -EINVAL; | |
1195 | struct fw_cmd_hdr *fw_hdr; | |
1196 | ||
1197 | /* Determine mode */ | |
1198 | if (mbp->mb_cbfn == NULL) { | |
1199 | /* Need to issue/get results in the same context */ | |
1200 | if (mbp->tmo < CSIO_MB_POLL_FREQ) { | |
1201 | csio_err(hw, "Invalid tmo: 0x%x\n", mbp->tmo); | |
1202 | goto error_out; | |
1203 | } | |
1204 | } else if (!csio_is_host_intr_enabled(hw) || | |
1205 | !csio_is_hw_intr_enabled(hw)) { | |
1206 | csio_err(hw, "Cannot issue mailbox in interrupt mode 0x%x\n", | |
1207 | *((uint8_t *)mbp->mb)); | |
1208 | goto error_out; | |
1209 | } | |
1210 | ||
1211 | if (mbm->mcurrent != NULL) { | |
1212 | /* Queue mbox cmd, if another mbox cmd is active */ | |
1213 | if (mbp->mb_cbfn == NULL) { | |
1214 | rv = -EBUSY; | |
1215 | csio_dbg(hw, "Couldnt own Mailbox %x op:0x%x\n", | |
1216 | hw->pfn, *((uint8_t *)mbp->mb)); | |
1217 | ||
1218 | goto error_out; | |
1219 | } else { | |
1220 | list_add_tail(&mbp->list, &mbm->req_q); | |
1221 | CSIO_INC_STATS(mbm, n_activeq); | |
1222 | ||
1223 | return 0; | |
1224 | } | |
1225 | } | |
1226 | ||
1227 | /* Now get ownership of mailbox */ | |
89c3a86c | 1228 | owner = MBOWNER_G(csio_rd_reg32(hw, ctl_reg)); |
a3667aae NKI |
1229 | |
1230 | if (!csio_mb_is_host_owner(owner)) { | |
1231 | ||
1232 | for (i = 0; (owner == CSIO_MBOWNER_NONE) && (i < 3); i++) | |
89c3a86c | 1233 | owner = MBOWNER_G(csio_rd_reg32(hw, ctl_reg)); |
a3667aae NKI |
1234 | /* |
1235 | * Mailbox unavailable. In immediate mode, fail the command. | |
1236 | * In other modes, enqueue the request. | |
1237 | */ | |
1238 | if (!csio_mb_is_host_owner(owner)) { | |
1239 | if (mbp->mb_cbfn == NULL) { | |
1240 | rv = owner ? -EBUSY : -ETIMEDOUT; | |
1241 | ||
1242 | csio_dbg(hw, | |
1243 | "Couldnt own Mailbox %x op:0x%x " | |
1244 | "owner:%x\n", | |
1245 | hw->pfn, *((uint8_t *)mbp->mb), owner); | |
1246 | goto error_out; | |
1247 | } else { | |
1248 | if (mbm->mcurrent == NULL) { | |
1249 | csio_err(hw, | |
1250 | "Couldnt own Mailbox %x " | |
1251 | "op:0x%x owner:%x\n", | |
1252 | hw->pfn, *((uint8_t *)mbp->mb), | |
1253 | owner); | |
1254 | csio_err(hw, | |
1255 | "No outstanding driver" | |
1256 | " mailbox as well\n"); | |
1257 | goto error_out; | |
1258 | } | |
1259 | } | |
1260 | } | |
1261 | } | |
1262 | ||
1263 | /* Mailbox is available, copy mailbox data into it */ | |
1264 | for (i = 0; i < size; i += 8) { | |
1265 | csio_wr_reg64(hw, be64_to_cpu(*cmd), data_reg + i); | |
1266 | cmd++; | |
1267 | } | |
1268 | ||
1269 | CSIO_DUMP_MB(hw, hw->pfn, data_reg); | |
1270 | ||
1271 | /* Start completion timers in non-immediate modes and notify FW */ | |
1272 | if (mbp->mb_cbfn != NULL) { | |
1273 | mbm->mcurrent = mbp; | |
1274 | mod_timer(&mbm->timer, jiffies + msecs_to_jiffies(mbp->tmo)); | |
89c3a86c HS |
1275 | csio_wr_reg32(hw, MBMSGVALID_F | MBINTREQ_F | |
1276 | MBOWNER_V(CSIO_MBOWNER_FW), ctl_reg); | |
a3667aae | 1277 | } else |
89c3a86c | 1278 | csio_wr_reg32(hw, MBMSGVALID_F | MBOWNER_V(CSIO_MBOWNER_FW), |
a3667aae NKI |
1279 | ctl_reg); |
1280 | ||
1281 | /* Flush posted writes */ | |
1282 | csio_rd_reg32(hw, ctl_reg); | |
1283 | wmb(); | |
1284 | ||
1285 | CSIO_INC_STATS(mbm, n_req); | |
1286 | ||
1287 | if (mbp->mb_cbfn) | |
1288 | return 0; | |
1289 | ||
1290 | /* Poll for completion in immediate mode */ | |
1291 | cmd = mbp->mb; | |
1292 | ||
1293 | for (ii = 0; ii < mbp->tmo; ii += CSIO_MB_POLL_FREQ) { | |
1294 | mdelay(CSIO_MB_POLL_FREQ); | |
1295 | ||
1296 | /* Check for response */ | |
1297 | ctl = csio_rd_reg32(hw, ctl_reg); | |
89c3a86c | 1298 | if (csio_mb_is_host_owner(MBOWNER_G(ctl))) { |
a3667aae | 1299 | |
89c3a86c | 1300 | if (!(ctl & MBMSGVALID_F)) { |
a3667aae NKI |
1301 | csio_wr_reg32(hw, 0, ctl_reg); |
1302 | continue; | |
1303 | } | |
1304 | ||
1305 | CSIO_DUMP_MB(hw, hw->pfn, data_reg); | |
1306 | ||
1307 | hdr = cpu_to_be64(csio_rd_reg64(hw, data_reg)); | |
1308 | fw_hdr = (struct fw_cmd_hdr *)&hdr; | |
1309 | ||
e2ac9628 | 1310 | switch (FW_CMD_OP_G(ntohl(fw_hdr->hi))) { |
a3667aae NKI |
1311 | case FW_DEBUG_CMD: |
1312 | csio_mb_debug_cmd_handler(hw); | |
1313 | continue; | |
1314 | } | |
1315 | ||
1316 | /* Copy response */ | |
1317 | for (i = 0; i < size; i += 8) | |
1318 | *cmd++ = cpu_to_be64(csio_rd_reg64 | |
1319 | (hw, data_reg + i)); | |
1320 | csio_wr_reg32(hw, 0, ctl_reg); | |
1321 | ||
5036f0a0 | 1322 | if (csio_mb_fw_retval(mbp) != FW_SUCCESS) |
a3667aae NKI |
1323 | CSIO_INC_STATS(mbm, n_err); |
1324 | ||
1325 | CSIO_INC_STATS(mbm, n_rsp); | |
1326 | return 0; | |
1327 | } | |
1328 | } | |
1329 | ||
1330 | CSIO_INC_STATS(mbm, n_tmo); | |
1331 | ||
1332 | csio_err(hw, "Mailbox %x op:0x%x timed out!\n", | |
1333 | hw->pfn, *((uint8_t *)cmd)); | |
1334 | ||
1335 | return -ETIMEDOUT; | |
1336 | ||
1337 | error_out: | |
1338 | CSIO_INC_STATS(mbm, n_err); | |
1339 | return rv; | |
1340 | } | |
1341 | ||
1342 | /* | |
1343 | * csio_mb_completions - Completion handler for Mailbox commands | |
1344 | * @hw: The HW structure | |
1345 | * @cbfn_q: Completion queue. | |
1346 | * | |
1347 | */ | |
1348 | void | |
1349 | csio_mb_completions(struct csio_hw *hw, struct list_head *cbfn_q) | |
1350 | { | |
1351 | struct csio_mb *mbp; | |
1352 | struct csio_mbm *mbm = &hw->mbm; | |
1353 | enum fw_retval rv; | |
1354 | ||
1355 | while (!list_empty(cbfn_q)) { | |
1356 | mbp = list_first_entry(cbfn_q, struct csio_mb, list); | |
1357 | list_del_init(&mbp->list); | |
1358 | ||
1359 | rv = csio_mb_fw_retval(mbp); | |
1360 | if ((rv != FW_SUCCESS) && (rv != FW_HOSTERROR)) | |
1361 | CSIO_INC_STATS(mbm, n_err); | |
1362 | else if (rv != FW_HOSTERROR) | |
1363 | CSIO_INC_STATS(mbm, n_rsp); | |
1364 | ||
1365 | if (mbp->mb_cbfn) | |
1366 | mbp->mb_cbfn(hw, mbp); | |
1367 | } | |
1368 | } | |
1369 | ||
1370 | static void | |
1371 | csio_mb_portmod_changed(struct csio_hw *hw, uint8_t port_id) | |
1372 | { | |
1373 | static char *mod_str[] = { | |
1374 | NULL, "LR", "SR", "ER", "TWINAX", "active TWINAX", "LRM" | |
1375 | }; | |
1376 | ||
1377 | struct csio_pport *port = &hw->pport[port_id]; | |
1378 | ||
1379 | if (port->mod_type == FW_PORT_MOD_TYPE_NONE) | |
1380 | csio_info(hw, "Port:%d - port module unplugged\n", port_id); | |
1381 | else if (port->mod_type < ARRAY_SIZE(mod_str)) | |
1382 | csio_info(hw, "Port:%d - %s port module inserted\n", port_id, | |
1383 | mod_str[port->mod_type]); | |
1384 | else if (port->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED) | |
1385 | csio_info(hw, | |
1386 | "Port:%d - unsupported optical port module " | |
1387 | "inserted\n", port_id); | |
1388 | else if (port->mod_type == FW_PORT_MOD_TYPE_UNKNOWN) | |
1389 | csio_info(hw, | |
1390 | "Port:%d - unknown port module inserted, forcing " | |
1391 | "TWINAX\n", port_id); | |
1392 | else if (port->mod_type == FW_PORT_MOD_TYPE_ERROR) | |
1393 | csio_info(hw, "Port:%d - transceiver module error\n", port_id); | |
1394 | else | |
1395 | csio_info(hw, "Port:%d - unknown module type %d inserted\n", | |
1396 | port_id, port->mod_type); | |
1397 | } | |
1398 | ||
1399 | int | |
1400 | csio_mb_fwevt_handler(struct csio_hw *hw, __be64 *cmd) | |
1401 | { | |
1402 | uint8_t opcode = *(uint8_t *)cmd; | |
1403 | struct fw_port_cmd *pcmd; | |
1404 | uint8_t port_id; | |
1405 | uint32_t link_status; | |
1406 | uint16_t action; | |
1407 | uint8_t mod_type; | |
1408 | ||
1409 | if (opcode == FW_PORT_CMD) { | |
1410 | pcmd = (struct fw_port_cmd *)cmd; | |
2b5fb1f2 | 1411 | port_id = FW_PORT_CMD_PORTID_G( |
a3667aae | 1412 | ntohl(pcmd->op_to_portid)); |
2b5fb1f2 | 1413 | action = FW_PORT_CMD_ACTION_G( |
a3667aae NKI |
1414 | ntohl(pcmd->action_to_len16)); |
1415 | if (action != FW_PORT_ACTION_GET_PORT_INFO) { | |
1416 | csio_err(hw, "Unhandled FW_PORT_CMD action: %u\n", | |
1417 | action); | |
1418 | return -EINVAL; | |
1419 | } | |
1420 | ||
1421 | link_status = ntohl(pcmd->u.info.lstatus_to_modtype); | |
2b5fb1f2 | 1422 | mod_type = FW_PORT_CMD_MODTYPE_G(link_status); |
a3667aae NKI |
1423 | |
1424 | hw->pport[port_id].link_status = | |
2b5fb1f2 | 1425 | FW_PORT_CMD_LSTATUS_G(link_status); |
a3667aae | 1426 | hw->pport[port_id].link_speed = |
2b5fb1f2 | 1427 | FW_PORT_CMD_LSPEED_G(link_status); |
a3667aae NKI |
1428 | |
1429 | csio_info(hw, "Port:%x - LINK %s\n", port_id, | |
2b5fb1f2 | 1430 | FW_PORT_CMD_LSTATUS_G(link_status) ? "UP" : "DOWN"); |
a3667aae NKI |
1431 | |
1432 | if (mod_type != hw->pport[port_id].mod_type) { | |
1433 | hw->pport[port_id].mod_type = mod_type; | |
1434 | csio_mb_portmod_changed(hw, port_id); | |
1435 | } | |
1436 | } else if (opcode == FW_DEBUG_CMD) { | |
1437 | csio_mb_dump_fw_dbg(hw, cmd); | |
1438 | } else { | |
1439 | csio_dbg(hw, "Gen MB can't handle op:0x%x on evtq.\n", opcode); | |
1440 | return -EINVAL; | |
1441 | } | |
1442 | ||
1443 | return 0; | |
1444 | } | |
1445 | ||
1446 | /* | |
1447 | * csio_mb_isr_handler - Handle mailboxes related interrupts. | |
1448 | * @hw: The HW structure | |
1449 | * | |
1450 | * Called from the ISR to handle Mailbox related interrupts. | |
1451 | * HW Lock should be held across this call. | |
1452 | */ | |
1453 | int | |
1454 | csio_mb_isr_handler(struct csio_hw *hw) | |
1455 | { | |
1456 | struct csio_mbm *mbm = &hw->mbm; | |
1457 | struct csio_mb *mbp = mbm->mcurrent; | |
1458 | __be64 *cmd; | |
1459 | uint32_t ctl, cim_cause, pl_cause; | |
1460 | int i; | |
89c3a86c HS |
1461 | uint32_t ctl_reg = PF_REG(hw->pfn, CIM_PF_MAILBOX_CTRL_A); |
1462 | uint32_t data_reg = PF_REG(hw->pfn, CIM_PF_MAILBOX_DATA_A); | |
a3667aae NKI |
1463 | int size; |
1464 | __be64 hdr; | |
1465 | struct fw_cmd_hdr *fw_hdr; | |
1466 | ||
0d804338 | 1467 | pl_cause = csio_rd_reg32(hw, MYPF_REG(PL_PF_INT_CAUSE_A)); |
89c3a86c | 1468 | cim_cause = csio_rd_reg32(hw, MYPF_REG(CIM_PF_HOST_INT_CAUSE_A)); |
a3667aae | 1469 | |
0d804338 | 1470 | if (!(pl_cause & PFCIM_F) || !(cim_cause & MBMSGRDYINT_F)) { |
a3667aae NKI |
1471 | CSIO_INC_STATS(hw, n_mbint_unexp); |
1472 | return -EINVAL; | |
1473 | } | |
1474 | ||
1475 | /* | |
1476 | * The cause registers below HAVE to be cleared in the SAME | |
1477 | * order as below: The low level cause register followed by | |
1478 | * the upper level cause register. In other words, CIM-cause | |
1479 | * first followed by PL-Cause next. | |
1480 | */ | |
89c3a86c | 1481 | csio_wr_reg32(hw, MBMSGRDYINT_F, MYPF_REG(CIM_PF_HOST_INT_CAUSE_A)); |
0d804338 | 1482 | csio_wr_reg32(hw, PFCIM_F, MYPF_REG(PL_PF_INT_CAUSE_A)); |
a3667aae NKI |
1483 | |
1484 | ctl = csio_rd_reg32(hw, ctl_reg); | |
1485 | ||
89c3a86c | 1486 | if (csio_mb_is_host_owner(MBOWNER_G(ctl))) { |
a3667aae NKI |
1487 | |
1488 | CSIO_DUMP_MB(hw, hw->pfn, data_reg); | |
1489 | ||
89c3a86c | 1490 | if (!(ctl & MBMSGVALID_F)) { |
a3667aae NKI |
1491 | csio_warn(hw, |
1492 | "Stray mailbox interrupt recvd," | |
1493 | " mailbox data not valid\n"); | |
1494 | csio_wr_reg32(hw, 0, ctl_reg); | |
1495 | /* Flush */ | |
1496 | csio_rd_reg32(hw, ctl_reg); | |
1497 | return -EINVAL; | |
1498 | } | |
1499 | ||
1500 | hdr = cpu_to_be64(csio_rd_reg64(hw, data_reg)); | |
1501 | fw_hdr = (struct fw_cmd_hdr *)&hdr; | |
1502 | ||
e2ac9628 | 1503 | switch (FW_CMD_OP_G(ntohl(fw_hdr->hi))) { |
a3667aae NKI |
1504 | case FW_DEBUG_CMD: |
1505 | csio_mb_debug_cmd_handler(hw); | |
1506 | return -EINVAL; | |
1507 | #if 0 | |
1508 | case FW_ERROR_CMD: | |
1509 | case FW_INITIALIZE_CMD: /* When we are not master */ | |
1510 | #endif | |
1511 | } | |
1512 | ||
1513 | CSIO_ASSERT(mbp != NULL); | |
1514 | ||
1515 | cmd = mbp->mb; | |
1516 | size = mbp->mb_size; | |
1517 | /* Get response */ | |
1518 | for (i = 0; i < size; i += 8) | |
1519 | *cmd++ = cpu_to_be64(csio_rd_reg64 | |
1520 | (hw, data_reg + i)); | |
1521 | ||
1522 | csio_wr_reg32(hw, 0, ctl_reg); | |
1523 | /* Flush */ | |
1524 | csio_rd_reg32(hw, ctl_reg); | |
1525 | ||
1526 | mbm->mcurrent = NULL; | |
1527 | ||
1528 | /* Add completion to tail of cbfn queue */ | |
1529 | list_add_tail(&mbp->list, &mbm->cbfn_q); | |
1530 | CSIO_INC_STATS(mbm, n_cbfnq); | |
1531 | ||
1532 | /* | |
1533 | * Enqueue event to EventQ. Events processing happens | |
1534 | * in Event worker thread context | |
1535 | */ | |
1536 | if (csio_enqueue_evt(hw, CSIO_EVT_MBX, mbp, sizeof(mbp))) | |
1537 | CSIO_INC_STATS(hw, n_evt_drop); | |
1538 | ||
1539 | return 0; | |
1540 | ||
1541 | } else { | |
1542 | /* | |
1543 | * We can get here if mailbox MSIX vector is shared, | |
1544 | * or in INTx case. Or a stray interrupt. | |
1545 | */ | |
1546 | csio_dbg(hw, "Host not owner, no mailbox interrupt\n"); | |
1547 | CSIO_INC_STATS(hw, n_int_stray); | |
1548 | return -EINVAL; | |
1549 | } | |
1550 | } | |
1551 | ||
1552 | /* | |
1553 | * csio_mb_tmo_handler - Timeout handler | |
1554 | * @hw: The HW structure | |
1555 | * | |
1556 | */ | |
1557 | struct csio_mb * | |
1558 | csio_mb_tmo_handler(struct csio_hw *hw) | |
1559 | { | |
1560 | struct csio_mbm *mbm = &hw->mbm; | |
1561 | struct csio_mb *mbp = mbm->mcurrent; | |
1562 | struct fw_cmd_hdr *fw_hdr; | |
1563 | ||
1564 | /* | |
1565 | * Could be a race b/w the completion handler and the timer | |
1566 | * and the completion handler won that race. | |
1567 | */ | |
1568 | if (mbp == NULL) { | |
1569 | CSIO_DB_ASSERT(0); | |
1570 | return NULL; | |
1571 | } | |
1572 | ||
1573 | fw_hdr = (struct fw_cmd_hdr *)(mbp->mb); | |
1574 | ||
1575 | csio_dbg(hw, "Mailbox num:%x op:0x%x timed out\n", hw->pfn, | |
e2ac9628 | 1576 | FW_CMD_OP_G(ntohl(fw_hdr->hi))); |
a3667aae NKI |
1577 | |
1578 | mbm->mcurrent = NULL; | |
1579 | CSIO_INC_STATS(mbm, n_tmo); | |
e2ac9628 | 1580 | fw_hdr->lo = htonl(FW_CMD_RETVAL_V(FW_ETIMEDOUT)); |
a3667aae NKI |
1581 | |
1582 | return mbp; | |
1583 | } | |
1584 | ||
1585 | /* | |
1586 | * csio_mb_cancel_all - Cancel all waiting commands. | |
1587 | * @hw: The HW structure | |
1588 | * @cbfn_q: The callback queue. | |
1589 | * | |
1590 | * Caller should hold hw lock across this call. | |
1591 | */ | |
1592 | void | |
1593 | csio_mb_cancel_all(struct csio_hw *hw, struct list_head *cbfn_q) | |
1594 | { | |
1595 | struct csio_mb *mbp; | |
1596 | struct csio_mbm *mbm = &hw->mbm; | |
1597 | struct fw_cmd_hdr *hdr; | |
1598 | struct list_head *tmp; | |
1599 | ||
1600 | if (mbm->mcurrent) { | |
1601 | mbp = mbm->mcurrent; | |
1602 | ||
1603 | /* Stop mailbox completion timer */ | |
1604 | del_timer_sync(&mbm->timer); | |
1605 | ||
1606 | /* Add completion to tail of cbfn queue */ | |
1607 | list_add_tail(&mbp->list, cbfn_q); | |
1608 | mbm->mcurrent = NULL; | |
1609 | } | |
1610 | ||
1611 | if (!list_empty(&mbm->req_q)) { | |
1612 | list_splice_tail_init(&mbm->req_q, cbfn_q); | |
1613 | mbm->stats.n_activeq = 0; | |
1614 | } | |
1615 | ||
1616 | if (!list_empty(&mbm->cbfn_q)) { | |
1617 | list_splice_tail_init(&mbm->cbfn_q, cbfn_q); | |
1618 | mbm->stats.n_cbfnq = 0; | |
1619 | } | |
1620 | ||
1621 | if (list_empty(cbfn_q)) | |
1622 | return; | |
1623 | ||
1624 | list_for_each(tmp, cbfn_q) { | |
1625 | mbp = (struct csio_mb *)tmp; | |
1626 | hdr = (struct fw_cmd_hdr *)(mbp->mb); | |
1627 | ||
1628 | csio_dbg(hw, "Cancelling pending mailbox num %x op:%x\n", | |
e2ac9628 | 1629 | hw->pfn, FW_CMD_OP_G(ntohl(hdr->hi))); |
a3667aae NKI |
1630 | |
1631 | CSIO_INC_STATS(mbm, n_cancel); | |
e2ac9628 | 1632 | hdr->lo = htonl(FW_CMD_RETVAL_V(FW_HOSTERROR)); |
a3667aae NKI |
1633 | } |
1634 | } | |
1635 | ||
1636 | /* | |
1637 | * csio_mbm_init - Initialize Mailbox module | |
1638 | * @mbm: Mailbox module | |
1639 | * @hw: The HW structure | |
1640 | * @timer: Timing function for interrupting mailboxes | |
1641 | * | |
1642 | * Initialize timer and the request/response queues. | |
1643 | */ | |
1644 | int | |
1645 | csio_mbm_init(struct csio_mbm *mbm, struct csio_hw *hw, | |
1646 | void (*timer_fn)(uintptr_t)) | |
1647 | { | |
1648 | struct timer_list *timer = &mbm->timer; | |
1649 | ||
1650 | init_timer(timer); | |
1651 | timer->function = timer_fn; | |
1652 | timer->data = (unsigned long)hw; | |
1653 | ||
1654 | INIT_LIST_HEAD(&mbm->req_q); | |
1655 | INIT_LIST_HEAD(&mbm->cbfn_q); | |
1656 | csio_set_mb_intr_idx(mbm, -1); | |
1657 | ||
1658 | return 0; | |
1659 | } | |
1660 | ||
1661 | /* | |
1662 | * csio_mbm_exit - Uninitialize mailbox module | |
1663 | * @mbm: Mailbox module | |
1664 | * | |
1665 | * Stop timer. | |
1666 | */ | |
1667 | void | |
1668 | csio_mbm_exit(struct csio_mbm *mbm) | |
1669 | { | |
1670 | del_timer_sync(&mbm->timer); | |
1671 | ||
1672 | CSIO_DB_ASSERT(mbm->mcurrent == NULL); | |
1673 | CSIO_DB_ASSERT(list_empty(&mbm->req_q)); | |
1674 | CSIO_DB_ASSERT(list_empty(&mbm->cbfn_q)); | |
1675 | } |