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edd16368 SC |
1 | /* |
2 | * Disk Array driver for HP Smart Array SAS controllers | |
1358f6dc DB |
3 | * Copyright 2014-2015 PMC-Sierra, Inc. |
4 | * Copyright 2000,2009-2015 Hewlett-Packard Development Company, L.P. | |
edd16368 SC |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; version 2 of the License. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
13 | * NON INFRINGEMENT. See the GNU General Public License for more details. | |
14 | * | |
1358f6dc | 15 | * Questions/Comments/Bugfixes to storagedev@pmcs.com |
edd16368 SC |
16 | * |
17 | */ | |
18 | ||
19 | #include <linux/module.h> | |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/types.h> | |
22 | #include <linux/pci.h> | |
e5a44df8 | 23 | #include <linux/pci-aspm.h> |
edd16368 SC |
24 | #include <linux/kernel.h> |
25 | #include <linux/slab.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/fs.h> | |
28 | #include <linux/timer.h> | |
edd16368 SC |
29 | #include <linux/init.h> |
30 | #include <linux/spinlock.h> | |
edd16368 SC |
31 | #include <linux/compat.h> |
32 | #include <linux/blktrace_api.h> | |
33 | #include <linux/uaccess.h> | |
34 | #include <linux/io.h> | |
35 | #include <linux/dma-mapping.h> | |
36 | #include <linux/completion.h> | |
37 | #include <linux/moduleparam.h> | |
38 | #include <scsi/scsi.h> | |
39 | #include <scsi/scsi_cmnd.h> | |
40 | #include <scsi/scsi_device.h> | |
41 | #include <scsi/scsi_host.h> | |
667e23d4 | 42 | #include <scsi/scsi_tcq.h> |
9437ac43 | 43 | #include <scsi/scsi_eh.h> |
d04e62b9 | 44 | #include <scsi/scsi_transport_sas.h> |
73153fe5 | 45 | #include <scsi/scsi_dbg.h> |
edd16368 SC |
46 | #include <linux/cciss_ioctl.h> |
47 | #include <linux/string.h> | |
48 | #include <linux/bitmap.h> | |
60063497 | 49 | #include <linux/atomic.h> |
a0c12413 | 50 | #include <linux/jiffies.h> |
42a91641 | 51 | #include <linux/percpu-defs.h> |
094963da | 52 | #include <linux/percpu.h> |
2b08b3e9 | 53 | #include <asm/unaligned.h> |
283b4a9b | 54 | #include <asm/div64.h> |
edd16368 SC |
55 | #include "hpsa_cmd.h" |
56 | #include "hpsa.h" | |
57 | ||
ec2c3aa9 DB |
58 | /* |
59 | * HPSA_DRIVER_VERSION must be 3 byte values (0-255) separated by '.' | |
60 | * with an optional trailing '-' followed by a byte value (0-255). | |
61 | */ | |
62 | #define HPSA_DRIVER_VERSION "3.4.14-0" | |
edd16368 | 63 | #define DRIVER_NAME "HP HPSA Driver (v " HPSA_DRIVER_VERSION ")" |
f79cfec6 | 64 | #define HPSA "hpsa" |
edd16368 | 65 | |
007e7aa9 RE |
66 | /* How long to wait for CISS doorbell communication */ |
67 | #define CLEAR_EVENT_WAIT_INTERVAL 20 /* ms for each msleep() call */ | |
68 | #define MODE_CHANGE_WAIT_INTERVAL 10 /* ms for each msleep() call */ | |
69 | #define MAX_CLEAR_EVENT_WAIT 30000 /* times 20 ms = 600 s */ | |
70 | #define MAX_MODE_CHANGE_WAIT 2000 /* times 10 ms = 20 s */ | |
edd16368 SC |
71 | #define MAX_IOCTL_CONFIG_WAIT 1000 |
72 | ||
73 | /*define how many times we will try a command because of bus resets */ | |
74 | #define MAX_CMD_RETRIES 3 | |
75 | ||
76 | /* Embedded module documentation macros - see modules.h */ | |
77 | MODULE_AUTHOR("Hewlett-Packard Company"); | |
78 | MODULE_DESCRIPTION("Driver for HP Smart Array Controller version " \ | |
79 | HPSA_DRIVER_VERSION); | |
80 | MODULE_SUPPORTED_DEVICE("HP Smart Array Controllers"); | |
81 | MODULE_VERSION(HPSA_DRIVER_VERSION); | |
82 | MODULE_LICENSE("GPL"); | |
83 | ||
84 | static int hpsa_allow_any; | |
85 | module_param(hpsa_allow_any, int, S_IRUGO|S_IWUSR); | |
86 | MODULE_PARM_DESC(hpsa_allow_any, | |
87 | "Allow hpsa driver to access unknown HP Smart Array hardware"); | |
02ec19c8 SC |
88 | static int hpsa_simple_mode; |
89 | module_param(hpsa_simple_mode, int, S_IRUGO|S_IWUSR); | |
90 | MODULE_PARM_DESC(hpsa_simple_mode, | |
91 | "Use 'simple mode' rather than 'performant mode'"); | |
edd16368 SC |
92 | |
93 | /* define the PCI info for the cards we can control */ | |
94 | static const struct pci_device_id hpsa_pci_device_id[] = { | |
edd16368 SC |
95 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3241}, |
96 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3243}, | |
97 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3245}, | |
98 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3247}, | |
99 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3249}, | |
163dbcd8 MM |
100 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324A}, |
101 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324B}, | |
f8b01eb9 | 102 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3233}, |
9143a961 | 103 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3350}, |
104 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3351}, | |
105 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3352}, | |
106 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3353}, | |
107 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3354}, | |
108 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3355}, | |
109 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3356}, | |
fe0c9610 MM |
110 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1921}, |
111 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1922}, | |
112 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1923}, | |
113 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1924}, | |
fe0c9610 MM |
114 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1926}, |
115 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1928}, | |
97b9f53d MM |
116 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1929}, |
117 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BD}, | |
118 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BE}, | |
119 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BF}, | |
120 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C0}, | |
121 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C1}, | |
122 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C2}, | |
123 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C3}, | |
124 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C4}, | |
125 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C5}, | |
3b7a45e5 | 126 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C6}, |
97b9f53d MM |
127 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C7}, |
128 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C8}, | |
129 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C9}, | |
3b7a45e5 JH |
130 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CA}, |
131 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CB}, | |
132 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CC}, | |
133 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CD}, | |
134 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CE}, | |
fdfa4b6d | 135 | {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0580}, |
cbb47dcb DB |
136 | {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0581}, |
137 | {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0582}, | |
138 | {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0583}, | |
139 | {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0584}, | |
140 | {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0585}, | |
8e616a5e SC |
141 | {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0076}, |
142 | {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0087}, | |
143 | {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x007D}, | |
144 | {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0088}, | |
145 | {PCI_VENDOR_ID_HP, 0x333f, 0x103c, 0x333f}, | |
7c03b870 | 146 | {PCI_VENDOR_ID_HP, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, |
6798cc0a | 147 | PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0}, |
edd16368 SC |
148 | {0,} |
149 | }; | |
150 | ||
151 | MODULE_DEVICE_TABLE(pci, hpsa_pci_device_id); | |
152 | ||
153 | /* board_id = Subsystem Device ID & Vendor ID | |
154 | * product = Marketing Name for the board | |
155 | * access = Address of the struct of function pointers | |
156 | */ | |
157 | static struct board_type products[] = { | |
edd16368 SC |
158 | {0x3241103C, "Smart Array P212", &SA5_access}, |
159 | {0x3243103C, "Smart Array P410", &SA5_access}, | |
160 | {0x3245103C, "Smart Array P410i", &SA5_access}, | |
161 | {0x3247103C, "Smart Array P411", &SA5_access}, | |
162 | {0x3249103C, "Smart Array P812", &SA5_access}, | |
163dbcd8 MM |
163 | {0x324A103C, "Smart Array P712m", &SA5_access}, |
164 | {0x324B103C, "Smart Array P711m", &SA5_access}, | |
7d2cce58 | 165 | {0x3233103C, "HP StorageWorks 1210m", &SA5_access}, /* alias of 333f */ |
fe0c9610 MM |
166 | {0x3350103C, "Smart Array P222", &SA5_access}, |
167 | {0x3351103C, "Smart Array P420", &SA5_access}, | |
168 | {0x3352103C, "Smart Array P421", &SA5_access}, | |
169 | {0x3353103C, "Smart Array P822", &SA5_access}, | |
170 | {0x3354103C, "Smart Array P420i", &SA5_access}, | |
171 | {0x3355103C, "Smart Array P220i", &SA5_access}, | |
172 | {0x3356103C, "Smart Array P721m", &SA5_access}, | |
1fd6c8e3 MM |
173 | {0x1921103C, "Smart Array P830i", &SA5_access}, |
174 | {0x1922103C, "Smart Array P430", &SA5_access}, | |
175 | {0x1923103C, "Smart Array P431", &SA5_access}, | |
176 | {0x1924103C, "Smart Array P830", &SA5_access}, | |
177 | {0x1926103C, "Smart Array P731m", &SA5_access}, | |
178 | {0x1928103C, "Smart Array P230i", &SA5_access}, | |
179 | {0x1929103C, "Smart Array P530", &SA5_access}, | |
27fb8137 DB |
180 | {0x21BD103C, "Smart Array P244br", &SA5_access}, |
181 | {0x21BE103C, "Smart Array P741m", &SA5_access}, | |
182 | {0x21BF103C, "Smart HBA H240ar", &SA5_access}, | |
183 | {0x21C0103C, "Smart Array P440ar", &SA5_access}, | |
c8ae0ab1 | 184 | {0x21C1103C, "Smart Array P840ar", &SA5_access}, |
27fb8137 DB |
185 | {0x21C2103C, "Smart Array P440", &SA5_access}, |
186 | {0x21C3103C, "Smart Array P441", &SA5_access}, | |
97b9f53d | 187 | {0x21C4103C, "Smart Array", &SA5_access}, |
27fb8137 DB |
188 | {0x21C5103C, "Smart Array P841", &SA5_access}, |
189 | {0x21C6103C, "Smart HBA H244br", &SA5_access}, | |
190 | {0x21C7103C, "Smart HBA H240", &SA5_access}, | |
191 | {0x21C8103C, "Smart HBA H241", &SA5_access}, | |
97b9f53d | 192 | {0x21C9103C, "Smart Array", &SA5_access}, |
27fb8137 DB |
193 | {0x21CA103C, "Smart Array P246br", &SA5_access}, |
194 | {0x21CB103C, "Smart Array P840", &SA5_access}, | |
3b7a45e5 JH |
195 | {0x21CC103C, "Smart Array", &SA5_access}, |
196 | {0x21CD103C, "Smart Array", &SA5_access}, | |
27fb8137 | 197 | {0x21CE103C, "Smart HBA", &SA5_access}, |
fdfa4b6d | 198 | {0x05809005, "SmartHBA-SA", &SA5_access}, |
cbb47dcb DB |
199 | {0x05819005, "SmartHBA-SA 8i", &SA5_access}, |
200 | {0x05829005, "SmartHBA-SA 8i8e", &SA5_access}, | |
201 | {0x05839005, "SmartHBA-SA 8e", &SA5_access}, | |
202 | {0x05849005, "SmartHBA-SA 16i", &SA5_access}, | |
203 | {0x05859005, "SmartHBA-SA 4i4e", &SA5_access}, | |
8e616a5e SC |
204 | {0x00761590, "HP Storage P1224 Array Controller", &SA5_access}, |
205 | {0x00871590, "HP Storage P1224e Array Controller", &SA5_access}, | |
206 | {0x007D1590, "HP Storage P1228 Array Controller", &SA5_access}, | |
207 | {0x00881590, "HP Storage P1228e Array Controller", &SA5_access}, | |
208 | {0x333f103c, "HP StorageWorks 1210m Array Controller", &SA5_access}, | |
edd16368 SC |
209 | {0xFFFF103C, "Unknown Smart Array", &SA5_access}, |
210 | }; | |
211 | ||
d04e62b9 KB |
212 | static struct scsi_transport_template *hpsa_sas_transport_template; |
213 | static int hpsa_add_sas_host(struct ctlr_info *h); | |
214 | static void hpsa_delete_sas_host(struct ctlr_info *h); | |
215 | static int hpsa_add_sas_device(struct hpsa_sas_node *hpsa_sas_node, | |
216 | struct hpsa_scsi_dev_t *device); | |
217 | static void hpsa_remove_sas_device(struct hpsa_scsi_dev_t *device); | |
218 | static struct hpsa_scsi_dev_t | |
219 | *hpsa_find_device_by_sas_rphy(struct ctlr_info *h, | |
220 | struct sas_rphy *rphy); | |
221 | ||
a58e7e53 WS |
222 | #define SCSI_CMD_BUSY ((struct scsi_cmnd *)&hpsa_cmd_busy) |
223 | static const struct scsi_cmnd hpsa_cmd_busy; | |
224 | #define SCSI_CMD_IDLE ((struct scsi_cmnd *)&hpsa_cmd_idle) | |
225 | static const struct scsi_cmnd hpsa_cmd_idle; | |
edd16368 SC |
226 | static int number_of_controllers; |
227 | ||
10f66018 SC |
228 | static irqreturn_t do_hpsa_intr_intx(int irq, void *dev_id); |
229 | static irqreturn_t do_hpsa_intr_msi(int irq, void *dev_id); | |
42a91641 | 230 | static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg); |
edd16368 SC |
231 | |
232 | #ifdef CONFIG_COMPAT | |
42a91641 DB |
233 | static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, |
234 | void __user *arg); | |
edd16368 SC |
235 | #endif |
236 | ||
237 | static void cmd_free(struct ctlr_info *h, struct CommandList *c); | |
edd16368 | 238 | static struct CommandList *cmd_alloc(struct ctlr_info *h); |
73153fe5 WS |
239 | static void cmd_tagged_free(struct ctlr_info *h, struct CommandList *c); |
240 | static struct CommandList *cmd_tagged_alloc(struct ctlr_info *h, | |
241 | struct scsi_cmnd *scmd); | |
a2dac136 | 242 | static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h, |
b7bb24eb | 243 | void *buff, size_t size, u16 page_code, unsigned char *scsi3addr, |
edd16368 | 244 | int cmd_type); |
2c143342 | 245 | static void hpsa_free_cmd_pool(struct ctlr_info *h); |
b7bb24eb | 246 | #define VPD_PAGE (1 << 8) |
b48d9804 | 247 | #define HPSA_SIMPLE_ERROR_BITS 0x03 |
edd16368 | 248 | |
f281233d | 249 | static int hpsa_scsi_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd); |
a08a8471 SC |
250 | static void hpsa_scan_start(struct Scsi_Host *); |
251 | static int hpsa_scan_finished(struct Scsi_Host *sh, | |
252 | unsigned long elapsed_time); | |
7c0a0229 | 253 | static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth); |
edd16368 SC |
254 | |
255 | static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd); | |
75167d2c | 256 | static int hpsa_eh_abort_handler(struct scsi_cmnd *scsicmd); |
edd16368 | 257 | static int hpsa_slave_alloc(struct scsi_device *sdev); |
41ce4c35 | 258 | static int hpsa_slave_configure(struct scsi_device *sdev); |
edd16368 SC |
259 | static void hpsa_slave_destroy(struct scsi_device *sdev); |
260 | ||
8aa60681 | 261 | static void hpsa_update_scsi_devices(struct ctlr_info *h); |
edd16368 SC |
262 | static int check_for_unit_attention(struct ctlr_info *h, |
263 | struct CommandList *c); | |
264 | static void check_ioctl_unit_attention(struct ctlr_info *h, | |
265 | struct CommandList *c); | |
303932fd DB |
266 | /* performant mode helper functions */ |
267 | static void calc_bucket_map(int *bucket, int num_buckets, | |
2b08b3e9 | 268 | int nsgs, int min_blocks, u32 *bucket_map); |
105a3dbc RE |
269 | static void hpsa_free_performant_mode(struct ctlr_info *h); |
270 | static int hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h); | |
254f796b | 271 | static inline u32 next_command(struct ctlr_info *h, u8 q); |
6f039790 GKH |
272 | static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr, |
273 | u32 *cfg_base_addr, u64 *cfg_base_addr_index, | |
274 | u64 *cfg_offset); | |
275 | static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev, | |
276 | unsigned long *memory_bar); | |
277 | static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id); | |
278 | static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr, | |
279 | int wait_for_ready); | |
75167d2c | 280 | static inline void finish_cmd(struct CommandList *c); |
c706a795 | 281 | static int hpsa_wait_for_mode_change_ack(struct ctlr_info *h); |
fe5389c8 SC |
282 | #define BOARD_NOT_READY 0 |
283 | #define BOARD_READY 1 | |
23100dd9 | 284 | static void hpsa_drain_accel_commands(struct ctlr_info *h); |
76438d08 | 285 | static void hpsa_flush_cache(struct ctlr_info *h); |
c349775e ST |
286 | static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h, |
287 | struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len, | |
03383736 | 288 | u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk); |
080ef1cc | 289 | static void hpsa_command_resubmit_worker(struct work_struct *work); |
25163bd5 WS |
290 | static u32 lockup_detected(struct ctlr_info *h); |
291 | static int detect_controller_lockup(struct ctlr_info *h); | |
c2adae44 | 292 | static void hpsa_disable_rld_caching(struct ctlr_info *h); |
d04e62b9 KB |
293 | static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h, |
294 | struct ReportExtendedLUNdata *buf, int bufsize); | |
34592254 | 295 | static int hpsa_luns_changed(struct ctlr_info *h); |
edd16368 | 296 | |
edd16368 SC |
297 | static inline struct ctlr_info *sdev_to_hba(struct scsi_device *sdev) |
298 | { | |
299 | unsigned long *priv = shost_priv(sdev->host); | |
300 | return (struct ctlr_info *) *priv; | |
301 | } | |
302 | ||
a23513e8 SC |
303 | static inline struct ctlr_info *shost_to_hba(struct Scsi_Host *sh) |
304 | { | |
305 | unsigned long *priv = shost_priv(sh); | |
306 | return (struct ctlr_info *) *priv; | |
307 | } | |
308 | ||
a58e7e53 WS |
309 | static inline bool hpsa_is_cmd_idle(struct CommandList *c) |
310 | { | |
311 | return c->scsi_cmd == SCSI_CMD_IDLE; | |
312 | } | |
313 | ||
d604f533 WS |
314 | static inline bool hpsa_is_pending_event(struct CommandList *c) |
315 | { | |
316 | return c->abort_pending || c->reset_pending; | |
317 | } | |
318 | ||
9437ac43 SC |
319 | /* extract sense key, asc, and ascq from sense data. -1 means invalid. */ |
320 | static void decode_sense_data(const u8 *sense_data, int sense_data_len, | |
321 | u8 *sense_key, u8 *asc, u8 *ascq) | |
322 | { | |
323 | struct scsi_sense_hdr sshdr; | |
324 | bool rc; | |
325 | ||
326 | *sense_key = -1; | |
327 | *asc = -1; | |
328 | *ascq = -1; | |
329 | ||
330 | if (sense_data_len < 1) | |
331 | return; | |
332 | ||
333 | rc = scsi_normalize_sense(sense_data, sense_data_len, &sshdr); | |
334 | if (rc) { | |
335 | *sense_key = sshdr.sense_key; | |
336 | *asc = sshdr.asc; | |
337 | *ascq = sshdr.ascq; | |
338 | } | |
339 | } | |
340 | ||
edd16368 SC |
341 | static int check_for_unit_attention(struct ctlr_info *h, |
342 | struct CommandList *c) | |
343 | { | |
9437ac43 SC |
344 | u8 sense_key, asc, ascq; |
345 | int sense_len; | |
346 | ||
347 | if (c->err_info->SenseLen > sizeof(c->err_info->SenseInfo)) | |
348 | sense_len = sizeof(c->err_info->SenseInfo); | |
349 | else | |
350 | sense_len = c->err_info->SenseLen; | |
351 | ||
352 | decode_sense_data(c->err_info->SenseInfo, sense_len, | |
353 | &sense_key, &asc, &ascq); | |
81c27557 | 354 | if (sense_key != UNIT_ATTENTION || asc == 0xff) |
edd16368 SC |
355 | return 0; |
356 | ||
9437ac43 | 357 | switch (asc) { |
edd16368 | 358 | case STATE_CHANGED: |
9437ac43 | 359 | dev_warn(&h->pdev->dev, |
2946e82b RE |
360 | "%s: a state change detected, command retried\n", |
361 | h->devname); | |
edd16368 SC |
362 | break; |
363 | case LUN_FAILED: | |
7f73695a | 364 | dev_warn(&h->pdev->dev, |
2946e82b | 365 | "%s: LUN failure detected\n", h->devname); |
edd16368 SC |
366 | break; |
367 | case REPORT_LUNS_CHANGED: | |
7f73695a | 368 | dev_warn(&h->pdev->dev, |
2946e82b | 369 | "%s: report LUN data changed\n", h->devname); |
edd16368 | 370 | /* |
4f4eb9f1 ST |
371 | * Note: this REPORT_LUNS_CHANGED condition only occurs on the external |
372 | * target (array) devices. | |
edd16368 SC |
373 | */ |
374 | break; | |
375 | case POWER_OR_RESET: | |
2946e82b RE |
376 | dev_warn(&h->pdev->dev, |
377 | "%s: a power on or device reset detected\n", | |
378 | h->devname); | |
edd16368 SC |
379 | break; |
380 | case UNIT_ATTENTION_CLEARED: | |
2946e82b RE |
381 | dev_warn(&h->pdev->dev, |
382 | "%s: unit attention cleared by another initiator\n", | |
383 | h->devname); | |
edd16368 SC |
384 | break; |
385 | default: | |
2946e82b RE |
386 | dev_warn(&h->pdev->dev, |
387 | "%s: unknown unit attention detected\n", | |
388 | h->devname); | |
edd16368 SC |
389 | break; |
390 | } | |
391 | return 1; | |
392 | } | |
393 | ||
852af20a MB |
394 | static int check_for_busy(struct ctlr_info *h, struct CommandList *c) |
395 | { | |
396 | if (c->err_info->CommandStatus != CMD_TARGET_STATUS || | |
397 | (c->err_info->ScsiStatus != SAM_STAT_BUSY && | |
398 | c->err_info->ScsiStatus != SAM_STAT_TASK_SET_FULL)) | |
399 | return 0; | |
400 | dev_warn(&h->pdev->dev, HPSA "device busy"); | |
401 | return 1; | |
402 | } | |
403 | ||
e985c58f SC |
404 | static u32 lockup_detected(struct ctlr_info *h); |
405 | static ssize_t host_show_lockup_detected(struct device *dev, | |
406 | struct device_attribute *attr, char *buf) | |
407 | { | |
408 | int ld; | |
409 | struct ctlr_info *h; | |
410 | struct Scsi_Host *shost = class_to_shost(dev); | |
411 | ||
412 | h = shost_to_hba(shost); | |
413 | ld = lockup_detected(h); | |
414 | ||
415 | return sprintf(buf, "ld=%d\n", ld); | |
416 | } | |
417 | ||
da0697bd ST |
418 | static ssize_t host_store_hp_ssd_smart_path_status(struct device *dev, |
419 | struct device_attribute *attr, | |
420 | const char *buf, size_t count) | |
421 | { | |
422 | int status, len; | |
423 | struct ctlr_info *h; | |
424 | struct Scsi_Host *shost = class_to_shost(dev); | |
425 | char tmpbuf[10]; | |
426 | ||
427 | if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO)) | |
428 | return -EACCES; | |
429 | len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count; | |
430 | strncpy(tmpbuf, buf, len); | |
431 | tmpbuf[len] = '\0'; | |
432 | if (sscanf(tmpbuf, "%d", &status) != 1) | |
433 | return -EINVAL; | |
434 | h = shost_to_hba(shost); | |
435 | h->acciopath_status = !!status; | |
436 | dev_warn(&h->pdev->dev, | |
437 | "hpsa: HP SSD Smart Path %s via sysfs update.\n", | |
438 | h->acciopath_status ? "enabled" : "disabled"); | |
439 | return count; | |
440 | } | |
441 | ||
2ba8bfc8 SC |
442 | static ssize_t host_store_raid_offload_debug(struct device *dev, |
443 | struct device_attribute *attr, | |
444 | const char *buf, size_t count) | |
445 | { | |
446 | int debug_level, len; | |
447 | struct ctlr_info *h; | |
448 | struct Scsi_Host *shost = class_to_shost(dev); | |
449 | char tmpbuf[10]; | |
450 | ||
451 | if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO)) | |
452 | return -EACCES; | |
453 | len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count; | |
454 | strncpy(tmpbuf, buf, len); | |
455 | tmpbuf[len] = '\0'; | |
456 | if (sscanf(tmpbuf, "%d", &debug_level) != 1) | |
457 | return -EINVAL; | |
458 | if (debug_level < 0) | |
459 | debug_level = 0; | |
460 | h = shost_to_hba(shost); | |
461 | h->raid_offload_debug = debug_level; | |
462 | dev_warn(&h->pdev->dev, "hpsa: Set raid_offload_debug level = %d\n", | |
463 | h->raid_offload_debug); | |
464 | return count; | |
465 | } | |
466 | ||
edd16368 SC |
467 | static ssize_t host_store_rescan(struct device *dev, |
468 | struct device_attribute *attr, | |
469 | const char *buf, size_t count) | |
470 | { | |
471 | struct ctlr_info *h; | |
472 | struct Scsi_Host *shost = class_to_shost(dev); | |
a23513e8 | 473 | h = shost_to_hba(shost); |
31468401 | 474 | hpsa_scan_start(h->scsi_host); |
edd16368 SC |
475 | return count; |
476 | } | |
477 | ||
d28ce020 SC |
478 | static ssize_t host_show_firmware_revision(struct device *dev, |
479 | struct device_attribute *attr, char *buf) | |
480 | { | |
481 | struct ctlr_info *h; | |
482 | struct Scsi_Host *shost = class_to_shost(dev); | |
483 | unsigned char *fwrev; | |
484 | ||
485 | h = shost_to_hba(shost); | |
486 | if (!h->hba_inquiry_data) | |
487 | return 0; | |
488 | fwrev = &h->hba_inquiry_data[32]; | |
489 | return snprintf(buf, 20, "%c%c%c%c\n", | |
490 | fwrev[0], fwrev[1], fwrev[2], fwrev[3]); | |
491 | } | |
492 | ||
94a13649 SC |
493 | static ssize_t host_show_commands_outstanding(struct device *dev, |
494 | struct device_attribute *attr, char *buf) | |
495 | { | |
496 | struct Scsi_Host *shost = class_to_shost(dev); | |
497 | struct ctlr_info *h = shost_to_hba(shost); | |
498 | ||
0cbf768e SC |
499 | return snprintf(buf, 20, "%d\n", |
500 | atomic_read(&h->commands_outstanding)); | |
94a13649 SC |
501 | } |
502 | ||
745a7a25 SC |
503 | static ssize_t host_show_transport_mode(struct device *dev, |
504 | struct device_attribute *attr, char *buf) | |
505 | { | |
506 | struct ctlr_info *h; | |
507 | struct Scsi_Host *shost = class_to_shost(dev); | |
508 | ||
509 | h = shost_to_hba(shost); | |
510 | return snprintf(buf, 20, "%s\n", | |
960a30e7 | 511 | h->transMethod & CFGTBL_Trans_Performant ? |
745a7a25 SC |
512 | "performant" : "simple"); |
513 | } | |
514 | ||
da0697bd ST |
515 | static ssize_t host_show_hp_ssd_smart_path_status(struct device *dev, |
516 | struct device_attribute *attr, char *buf) | |
517 | { | |
518 | struct ctlr_info *h; | |
519 | struct Scsi_Host *shost = class_to_shost(dev); | |
520 | ||
521 | h = shost_to_hba(shost); | |
522 | return snprintf(buf, 30, "HP SSD Smart Path %s\n", | |
523 | (h->acciopath_status == 1) ? "enabled" : "disabled"); | |
524 | } | |
525 | ||
46380786 | 526 | /* List of controllers which cannot be hard reset on kexec with reset_devices */ |
941b1cda SC |
527 | static u32 unresettable_controller[] = { |
528 | 0x324a103C, /* Smart Array P712m */ | |
9b5c48c2 | 529 | 0x324b103C, /* Smart Array P711m */ |
941b1cda SC |
530 | 0x3223103C, /* Smart Array P800 */ |
531 | 0x3234103C, /* Smart Array P400 */ | |
532 | 0x3235103C, /* Smart Array P400i */ | |
533 | 0x3211103C, /* Smart Array E200i */ | |
534 | 0x3212103C, /* Smart Array E200 */ | |
535 | 0x3213103C, /* Smart Array E200i */ | |
536 | 0x3214103C, /* Smart Array E200i */ | |
537 | 0x3215103C, /* Smart Array E200i */ | |
538 | 0x3237103C, /* Smart Array E500 */ | |
539 | 0x323D103C, /* Smart Array P700m */ | |
7af0abbc | 540 | 0x40800E11, /* Smart Array 5i */ |
941b1cda SC |
541 | 0x409C0E11, /* Smart Array 6400 */ |
542 | 0x409D0E11, /* Smart Array 6400 EM */ | |
5a4f934e TH |
543 | 0x40700E11, /* Smart Array 5300 */ |
544 | 0x40820E11, /* Smart Array 532 */ | |
545 | 0x40830E11, /* Smart Array 5312 */ | |
546 | 0x409A0E11, /* Smart Array 641 */ | |
547 | 0x409B0E11, /* Smart Array 642 */ | |
548 | 0x40910E11, /* Smart Array 6i */ | |
941b1cda SC |
549 | }; |
550 | ||
46380786 SC |
551 | /* List of controllers which cannot even be soft reset */ |
552 | static u32 soft_unresettable_controller[] = { | |
7af0abbc | 553 | 0x40800E11, /* Smart Array 5i */ |
5a4f934e TH |
554 | 0x40700E11, /* Smart Array 5300 */ |
555 | 0x40820E11, /* Smart Array 532 */ | |
556 | 0x40830E11, /* Smart Array 5312 */ | |
557 | 0x409A0E11, /* Smart Array 641 */ | |
558 | 0x409B0E11, /* Smart Array 642 */ | |
559 | 0x40910E11, /* Smart Array 6i */ | |
46380786 SC |
560 | /* Exclude 640x boards. These are two pci devices in one slot |
561 | * which share a battery backed cache module. One controls the | |
562 | * cache, the other accesses the cache through the one that controls | |
563 | * it. If we reset the one controlling the cache, the other will | |
564 | * likely not be happy. Just forbid resetting this conjoined mess. | |
565 | * The 640x isn't really supported by hpsa anyway. | |
566 | */ | |
567 | 0x409C0E11, /* Smart Array 6400 */ | |
568 | 0x409D0E11, /* Smart Array 6400 EM */ | |
569 | }; | |
570 | ||
9b5c48c2 SC |
571 | static u32 needs_abort_tags_swizzled[] = { |
572 | 0x323D103C, /* Smart Array P700m */ | |
573 | 0x324a103C, /* Smart Array P712m */ | |
574 | 0x324b103C, /* SmartArray P711m */ | |
575 | }; | |
576 | ||
577 | static int board_id_in_array(u32 a[], int nelems, u32 board_id) | |
941b1cda SC |
578 | { |
579 | int i; | |
580 | ||
9b5c48c2 SC |
581 | for (i = 0; i < nelems; i++) |
582 | if (a[i] == board_id) | |
583 | return 1; | |
584 | return 0; | |
46380786 SC |
585 | } |
586 | ||
9b5c48c2 | 587 | static int ctlr_is_hard_resettable(u32 board_id) |
46380786 | 588 | { |
9b5c48c2 SC |
589 | return !board_id_in_array(unresettable_controller, |
590 | ARRAY_SIZE(unresettable_controller), board_id); | |
591 | } | |
46380786 | 592 | |
9b5c48c2 SC |
593 | static int ctlr_is_soft_resettable(u32 board_id) |
594 | { | |
595 | return !board_id_in_array(soft_unresettable_controller, | |
596 | ARRAY_SIZE(soft_unresettable_controller), board_id); | |
941b1cda SC |
597 | } |
598 | ||
46380786 SC |
599 | static int ctlr_is_resettable(u32 board_id) |
600 | { | |
601 | return ctlr_is_hard_resettable(board_id) || | |
602 | ctlr_is_soft_resettable(board_id); | |
603 | } | |
604 | ||
9b5c48c2 SC |
605 | static int ctlr_needs_abort_tags_swizzled(u32 board_id) |
606 | { | |
607 | return board_id_in_array(needs_abort_tags_swizzled, | |
608 | ARRAY_SIZE(needs_abort_tags_swizzled), board_id); | |
609 | } | |
610 | ||
941b1cda SC |
611 | static ssize_t host_show_resettable(struct device *dev, |
612 | struct device_attribute *attr, char *buf) | |
613 | { | |
614 | struct ctlr_info *h; | |
615 | struct Scsi_Host *shost = class_to_shost(dev); | |
616 | ||
617 | h = shost_to_hba(shost); | |
46380786 | 618 | return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h->board_id)); |
941b1cda SC |
619 | } |
620 | ||
edd16368 SC |
621 | static inline int is_logical_dev_addr_mode(unsigned char scsi3addr[]) |
622 | { | |
623 | return (scsi3addr[3] & 0xC0) == 0x40; | |
624 | } | |
625 | ||
f2ef0ce7 | 626 | static const char * const raid_label[] = { "0", "4", "1(+0)", "5", "5+1", "6", |
7c59a0d4 | 627 | "1(+0)ADM", "UNKNOWN", "PHYS DRV" |
edd16368 | 628 | }; |
6b80b18f ST |
629 | #define HPSA_RAID_0 0 |
630 | #define HPSA_RAID_4 1 | |
631 | #define HPSA_RAID_1 2 /* also used for RAID 10 */ | |
632 | #define HPSA_RAID_5 3 /* also used for RAID 50 */ | |
633 | #define HPSA_RAID_51 4 | |
634 | #define HPSA_RAID_6 5 /* also used for RAID 60 */ | |
635 | #define HPSA_RAID_ADM 6 /* also used for RAID 1+0 ADM */ | |
7c59a0d4 DB |
636 | #define RAID_UNKNOWN (ARRAY_SIZE(raid_label) - 2) |
637 | #define PHYSICAL_DRIVE (ARRAY_SIZE(raid_label) - 1) | |
edd16368 | 638 | |
f3f01730 KB |
639 | static inline bool is_logical_device(struct hpsa_scsi_dev_t *device) |
640 | { | |
641 | return !device->physical_device; | |
642 | } | |
edd16368 SC |
643 | |
644 | static ssize_t raid_level_show(struct device *dev, | |
645 | struct device_attribute *attr, char *buf) | |
646 | { | |
647 | ssize_t l = 0; | |
82a72c0a | 648 | unsigned char rlevel; |
edd16368 SC |
649 | struct ctlr_info *h; |
650 | struct scsi_device *sdev; | |
651 | struct hpsa_scsi_dev_t *hdev; | |
652 | unsigned long flags; | |
653 | ||
654 | sdev = to_scsi_device(dev); | |
655 | h = sdev_to_hba(sdev); | |
656 | spin_lock_irqsave(&h->lock, flags); | |
657 | hdev = sdev->hostdata; | |
658 | if (!hdev) { | |
659 | spin_unlock_irqrestore(&h->lock, flags); | |
660 | return -ENODEV; | |
661 | } | |
662 | ||
663 | /* Is this even a logical drive? */ | |
f3f01730 | 664 | if (!is_logical_device(hdev)) { |
edd16368 SC |
665 | spin_unlock_irqrestore(&h->lock, flags); |
666 | l = snprintf(buf, PAGE_SIZE, "N/A\n"); | |
667 | return l; | |
668 | } | |
669 | ||
670 | rlevel = hdev->raid_level; | |
671 | spin_unlock_irqrestore(&h->lock, flags); | |
82a72c0a | 672 | if (rlevel > RAID_UNKNOWN) |
edd16368 SC |
673 | rlevel = RAID_UNKNOWN; |
674 | l = snprintf(buf, PAGE_SIZE, "RAID %s\n", raid_label[rlevel]); | |
675 | return l; | |
676 | } | |
677 | ||
678 | static ssize_t lunid_show(struct device *dev, | |
679 | struct device_attribute *attr, char *buf) | |
680 | { | |
681 | struct ctlr_info *h; | |
682 | struct scsi_device *sdev; | |
683 | struct hpsa_scsi_dev_t *hdev; | |
684 | unsigned long flags; | |
685 | unsigned char lunid[8]; | |
686 | ||
687 | sdev = to_scsi_device(dev); | |
688 | h = sdev_to_hba(sdev); | |
689 | spin_lock_irqsave(&h->lock, flags); | |
690 | hdev = sdev->hostdata; | |
691 | if (!hdev) { | |
692 | spin_unlock_irqrestore(&h->lock, flags); | |
693 | return -ENODEV; | |
694 | } | |
695 | memcpy(lunid, hdev->scsi3addr, sizeof(lunid)); | |
696 | spin_unlock_irqrestore(&h->lock, flags); | |
697 | return snprintf(buf, 20, "0x%02x%02x%02x%02x%02x%02x%02x%02x\n", | |
698 | lunid[0], lunid[1], lunid[2], lunid[3], | |
699 | lunid[4], lunid[5], lunid[6], lunid[7]); | |
700 | } | |
701 | ||
702 | static ssize_t unique_id_show(struct device *dev, | |
703 | struct device_attribute *attr, char *buf) | |
704 | { | |
705 | struct ctlr_info *h; | |
706 | struct scsi_device *sdev; | |
707 | struct hpsa_scsi_dev_t *hdev; | |
708 | unsigned long flags; | |
709 | unsigned char sn[16]; | |
710 | ||
711 | sdev = to_scsi_device(dev); | |
712 | h = sdev_to_hba(sdev); | |
713 | spin_lock_irqsave(&h->lock, flags); | |
714 | hdev = sdev->hostdata; | |
715 | if (!hdev) { | |
716 | spin_unlock_irqrestore(&h->lock, flags); | |
717 | return -ENODEV; | |
718 | } | |
719 | memcpy(sn, hdev->device_id, sizeof(sn)); | |
720 | spin_unlock_irqrestore(&h->lock, flags); | |
721 | return snprintf(buf, 16 * 2 + 2, | |
722 | "%02X%02X%02X%02X%02X%02X%02X%02X" | |
723 | "%02X%02X%02X%02X%02X%02X%02X%02X\n", | |
724 | sn[0], sn[1], sn[2], sn[3], | |
725 | sn[4], sn[5], sn[6], sn[7], | |
726 | sn[8], sn[9], sn[10], sn[11], | |
727 | sn[12], sn[13], sn[14], sn[15]); | |
728 | } | |
729 | ||
c1988684 ST |
730 | static ssize_t host_show_hp_ssd_smart_path_enabled(struct device *dev, |
731 | struct device_attribute *attr, char *buf) | |
732 | { | |
733 | struct ctlr_info *h; | |
734 | struct scsi_device *sdev; | |
735 | struct hpsa_scsi_dev_t *hdev; | |
736 | unsigned long flags; | |
737 | int offload_enabled; | |
738 | ||
739 | sdev = to_scsi_device(dev); | |
740 | h = sdev_to_hba(sdev); | |
741 | spin_lock_irqsave(&h->lock, flags); | |
742 | hdev = sdev->hostdata; | |
743 | if (!hdev) { | |
744 | spin_unlock_irqrestore(&h->lock, flags); | |
745 | return -ENODEV; | |
746 | } | |
747 | offload_enabled = hdev->offload_enabled; | |
748 | spin_unlock_irqrestore(&h->lock, flags); | |
749 | return snprintf(buf, 20, "%d\n", offload_enabled); | |
750 | } | |
751 | ||
8270b862 | 752 | #define MAX_PATHS 8 |
8270b862 JH |
753 | |
754 | static ssize_t path_info_show(struct device *dev, | |
755 | struct device_attribute *attr, char *buf) | |
756 | { | |
757 | struct ctlr_info *h; | |
758 | struct scsi_device *sdev; | |
759 | struct hpsa_scsi_dev_t *hdev; | |
760 | unsigned long flags; | |
761 | int i; | |
762 | int output_len = 0; | |
763 | u8 box; | |
764 | u8 bay; | |
765 | u8 path_map_index = 0; | |
766 | char *active; | |
767 | unsigned char phys_connector[2]; | |
8270b862 | 768 | |
8270b862 JH |
769 | sdev = to_scsi_device(dev); |
770 | h = sdev_to_hba(sdev); | |
771 | spin_lock_irqsave(&h->devlock, flags); | |
772 | hdev = sdev->hostdata; | |
773 | if (!hdev) { | |
774 | spin_unlock_irqrestore(&h->devlock, flags); | |
775 | return -ENODEV; | |
776 | } | |
777 | ||
778 | bay = hdev->bay; | |
779 | for (i = 0; i < MAX_PATHS; i++) { | |
780 | path_map_index = 1<<i; | |
781 | if (i == hdev->active_path_index) | |
782 | active = "Active"; | |
783 | else if (hdev->path_map & path_map_index) | |
784 | active = "Inactive"; | |
785 | else | |
786 | continue; | |
787 | ||
1faf072c RV |
788 | output_len += scnprintf(buf + output_len, |
789 | PAGE_SIZE - output_len, | |
790 | "[%d:%d:%d:%d] %20.20s ", | |
8270b862 JH |
791 | h->scsi_host->host_no, |
792 | hdev->bus, hdev->target, hdev->lun, | |
793 | scsi_device_type(hdev->devtype)); | |
794 | ||
66749d0d | 795 | if (hdev->external || |
f3f01730 KB |
796 | hdev->devtype == TYPE_RAID || |
797 | is_logical_device(hdev)) { | |
1faf072c RV |
798 | output_len += snprintf(buf + output_len, |
799 | PAGE_SIZE - output_len, | |
800 | "%s\n", active); | |
8270b862 JH |
801 | continue; |
802 | } | |
803 | ||
804 | box = hdev->box[i]; | |
805 | memcpy(&phys_connector, &hdev->phys_connector[i], | |
806 | sizeof(phys_connector)); | |
807 | if (phys_connector[0] < '0') | |
808 | phys_connector[0] = '0'; | |
809 | if (phys_connector[1] < '0') | |
810 | phys_connector[1] = '0'; | |
811 | if (hdev->phys_connector[i] > 0) | |
1faf072c RV |
812 | output_len += snprintf(buf + output_len, |
813 | PAGE_SIZE - output_len, | |
8270b862 JH |
814 | "PORT: %.2s ", |
815 | phys_connector); | |
2a168208 | 816 | if (hdev->devtype == TYPE_DISK && hdev->expose_device) { |
8270b862 | 817 | if (box == 0 || box == 0xFF) { |
1faf072c RV |
818 | output_len += snprintf(buf + output_len, |
819 | PAGE_SIZE - output_len, | |
8270b862 JH |
820 | "BAY: %hhu %s\n", |
821 | bay, active); | |
822 | } else { | |
1faf072c RV |
823 | output_len += snprintf(buf + output_len, |
824 | PAGE_SIZE - output_len, | |
8270b862 JH |
825 | "BOX: %hhu BAY: %hhu %s\n", |
826 | box, bay, active); | |
827 | } | |
828 | } else if (box != 0 && box != 0xFF) { | |
1faf072c RV |
829 | output_len += snprintf(buf + output_len, |
830 | PAGE_SIZE - output_len, "BOX: %hhu %s\n", | |
8270b862 JH |
831 | box, active); |
832 | } else | |
1faf072c RV |
833 | output_len += snprintf(buf + output_len, |
834 | PAGE_SIZE - output_len, "%s\n", active); | |
8270b862 JH |
835 | } |
836 | ||
837 | spin_unlock_irqrestore(&h->devlock, flags); | |
1faf072c | 838 | return output_len; |
8270b862 JH |
839 | } |
840 | ||
3f5eac3a SC |
841 | static DEVICE_ATTR(raid_level, S_IRUGO, raid_level_show, NULL); |
842 | static DEVICE_ATTR(lunid, S_IRUGO, lunid_show, NULL); | |
843 | static DEVICE_ATTR(unique_id, S_IRUGO, unique_id_show, NULL); | |
844 | static DEVICE_ATTR(rescan, S_IWUSR, NULL, host_store_rescan); | |
c1988684 ST |
845 | static DEVICE_ATTR(hp_ssd_smart_path_enabled, S_IRUGO, |
846 | host_show_hp_ssd_smart_path_enabled, NULL); | |
8270b862 | 847 | static DEVICE_ATTR(path_info, S_IRUGO, path_info_show, NULL); |
da0697bd ST |
848 | static DEVICE_ATTR(hp_ssd_smart_path_status, S_IWUSR|S_IRUGO|S_IROTH, |
849 | host_show_hp_ssd_smart_path_status, | |
850 | host_store_hp_ssd_smart_path_status); | |
2ba8bfc8 SC |
851 | static DEVICE_ATTR(raid_offload_debug, S_IWUSR, NULL, |
852 | host_store_raid_offload_debug); | |
3f5eac3a SC |
853 | static DEVICE_ATTR(firmware_revision, S_IRUGO, |
854 | host_show_firmware_revision, NULL); | |
855 | static DEVICE_ATTR(commands_outstanding, S_IRUGO, | |
856 | host_show_commands_outstanding, NULL); | |
857 | static DEVICE_ATTR(transport_mode, S_IRUGO, | |
858 | host_show_transport_mode, NULL); | |
941b1cda SC |
859 | static DEVICE_ATTR(resettable, S_IRUGO, |
860 | host_show_resettable, NULL); | |
e985c58f SC |
861 | static DEVICE_ATTR(lockup_detected, S_IRUGO, |
862 | host_show_lockup_detected, NULL); | |
3f5eac3a SC |
863 | |
864 | static struct device_attribute *hpsa_sdev_attrs[] = { | |
865 | &dev_attr_raid_level, | |
866 | &dev_attr_lunid, | |
867 | &dev_attr_unique_id, | |
c1988684 | 868 | &dev_attr_hp_ssd_smart_path_enabled, |
8270b862 | 869 | &dev_attr_path_info, |
3f5eac3a SC |
870 | NULL, |
871 | }; | |
872 | ||
873 | static struct device_attribute *hpsa_shost_attrs[] = { | |
874 | &dev_attr_rescan, | |
875 | &dev_attr_firmware_revision, | |
876 | &dev_attr_commands_outstanding, | |
877 | &dev_attr_transport_mode, | |
941b1cda | 878 | &dev_attr_resettable, |
da0697bd | 879 | &dev_attr_hp_ssd_smart_path_status, |
2ba8bfc8 | 880 | &dev_attr_raid_offload_debug, |
fb53c439 | 881 | &dev_attr_lockup_detected, |
3f5eac3a SC |
882 | NULL, |
883 | }; | |
884 | ||
41ce4c35 SC |
885 | #define HPSA_NRESERVED_CMDS (HPSA_CMDS_RESERVED_FOR_ABORTS + \ |
886 | HPSA_CMDS_RESERVED_FOR_DRIVER + HPSA_MAX_CONCURRENT_PASSTHRUS) | |
887 | ||
3f5eac3a SC |
888 | static struct scsi_host_template hpsa_driver_template = { |
889 | .module = THIS_MODULE, | |
f79cfec6 SC |
890 | .name = HPSA, |
891 | .proc_name = HPSA, | |
3f5eac3a SC |
892 | .queuecommand = hpsa_scsi_queue_command, |
893 | .scan_start = hpsa_scan_start, | |
894 | .scan_finished = hpsa_scan_finished, | |
7c0a0229 | 895 | .change_queue_depth = hpsa_change_queue_depth, |
3f5eac3a SC |
896 | .this_id = -1, |
897 | .use_clustering = ENABLE_CLUSTERING, | |
75167d2c | 898 | .eh_abort_handler = hpsa_eh_abort_handler, |
3f5eac3a SC |
899 | .eh_device_reset_handler = hpsa_eh_device_reset_handler, |
900 | .ioctl = hpsa_ioctl, | |
901 | .slave_alloc = hpsa_slave_alloc, | |
41ce4c35 | 902 | .slave_configure = hpsa_slave_configure, |
3f5eac3a SC |
903 | .slave_destroy = hpsa_slave_destroy, |
904 | #ifdef CONFIG_COMPAT | |
905 | .compat_ioctl = hpsa_compat_ioctl, | |
906 | #endif | |
907 | .sdev_attrs = hpsa_sdev_attrs, | |
908 | .shost_attrs = hpsa_shost_attrs, | |
c0d6a4d1 | 909 | .max_sectors = 8192, |
54b2b50c | 910 | .no_write_same = 1, |
3f5eac3a SC |
911 | }; |
912 | ||
254f796b | 913 | static inline u32 next_command(struct ctlr_info *h, u8 q) |
3f5eac3a SC |
914 | { |
915 | u32 a; | |
072b0518 | 916 | struct reply_queue_buffer *rq = &h->reply_queue[q]; |
3f5eac3a | 917 | |
e1f7de0c MG |
918 | if (h->transMethod & CFGTBL_Trans_io_accel1) |
919 | return h->access.command_completed(h, q); | |
920 | ||
3f5eac3a | 921 | if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant))) |
254f796b | 922 | return h->access.command_completed(h, q); |
3f5eac3a | 923 | |
254f796b MG |
924 | if ((rq->head[rq->current_entry] & 1) == rq->wraparound) { |
925 | a = rq->head[rq->current_entry]; | |
926 | rq->current_entry++; | |
0cbf768e | 927 | atomic_dec(&h->commands_outstanding); |
3f5eac3a SC |
928 | } else { |
929 | a = FIFO_EMPTY; | |
930 | } | |
931 | /* Check for wraparound */ | |
254f796b MG |
932 | if (rq->current_entry == h->max_commands) { |
933 | rq->current_entry = 0; | |
934 | rq->wraparound ^= 1; | |
3f5eac3a SC |
935 | } |
936 | return a; | |
937 | } | |
938 | ||
c349775e ST |
939 | /* |
940 | * There are some special bits in the bus address of the | |
941 | * command that we have to set for the controller to know | |
942 | * how to process the command: | |
943 | * | |
944 | * Normal performant mode: | |
945 | * bit 0: 1 means performant mode, 0 means simple mode. | |
946 | * bits 1-3 = block fetch table entry | |
947 | * bits 4-6 = command type (== 0) | |
948 | * | |
949 | * ioaccel1 mode: | |
950 | * bit 0 = "performant mode" bit. | |
951 | * bits 1-3 = block fetch table entry | |
952 | * bits 4-6 = command type (== 110) | |
953 | * (command type is needed because ioaccel1 mode | |
954 | * commands are submitted through the same register as normal | |
955 | * mode commands, so this is how the controller knows whether | |
956 | * the command is normal mode or ioaccel1 mode.) | |
957 | * | |
958 | * ioaccel2 mode: | |
959 | * bit 0 = "performant mode" bit. | |
960 | * bits 1-4 = block fetch table entry (note extra bit) | |
961 | * bits 4-6 = not needed, because ioaccel2 mode has | |
962 | * a separate special register for submitting commands. | |
963 | */ | |
964 | ||
25163bd5 WS |
965 | /* |
966 | * set_performant_mode: Modify the tag for cciss performant | |
3f5eac3a SC |
967 | * set bit 0 for pull model, bits 3-1 for block fetch |
968 | * register number | |
969 | */ | |
25163bd5 WS |
970 | #define DEFAULT_REPLY_QUEUE (-1) |
971 | static void set_performant_mode(struct ctlr_info *h, struct CommandList *c, | |
972 | int reply_queue) | |
3f5eac3a | 973 | { |
254f796b | 974 | if (likely(h->transMethod & CFGTBL_Trans_Performant)) { |
3f5eac3a | 975 | c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1); |
25163bd5 WS |
976 | if (unlikely(!h->msix_vector)) |
977 | return; | |
978 | if (likely(reply_queue == DEFAULT_REPLY_QUEUE)) | |
254f796b | 979 | c->Header.ReplyQueue = |
804a5cb5 | 980 | raw_smp_processor_id() % h->nreply_queues; |
25163bd5 WS |
981 | else |
982 | c->Header.ReplyQueue = reply_queue % h->nreply_queues; | |
254f796b | 983 | } |
3f5eac3a SC |
984 | } |
985 | ||
c349775e | 986 | static void set_ioaccel1_performant_mode(struct ctlr_info *h, |
25163bd5 WS |
987 | struct CommandList *c, |
988 | int reply_queue) | |
c349775e ST |
989 | { |
990 | struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex]; | |
991 | ||
25163bd5 WS |
992 | /* |
993 | * Tell the controller to post the reply to the queue for this | |
c349775e ST |
994 | * processor. This seems to give the best I/O throughput. |
995 | */ | |
25163bd5 WS |
996 | if (likely(reply_queue == DEFAULT_REPLY_QUEUE)) |
997 | cp->ReplyQueue = smp_processor_id() % h->nreply_queues; | |
998 | else | |
999 | cp->ReplyQueue = reply_queue % h->nreply_queues; | |
1000 | /* | |
1001 | * Set the bits in the address sent down to include: | |
c349775e ST |
1002 | * - performant mode bit (bit 0) |
1003 | * - pull count (bits 1-3) | |
1004 | * - command type (bits 4-6) | |
1005 | */ | |
1006 | c->busaddr |= 1 | (h->ioaccel1_blockFetchTable[c->Header.SGList] << 1) | | |
1007 | IOACCEL1_BUSADDR_CMDTYPE; | |
1008 | } | |
1009 | ||
8be986cc SC |
1010 | static void set_ioaccel2_tmf_performant_mode(struct ctlr_info *h, |
1011 | struct CommandList *c, | |
1012 | int reply_queue) | |
1013 | { | |
1014 | struct hpsa_tmf_struct *cp = (struct hpsa_tmf_struct *) | |
1015 | &h->ioaccel2_cmd_pool[c->cmdindex]; | |
1016 | ||
1017 | /* Tell the controller to post the reply to the queue for this | |
1018 | * processor. This seems to give the best I/O throughput. | |
1019 | */ | |
1020 | if (likely(reply_queue == DEFAULT_REPLY_QUEUE)) | |
1021 | cp->reply_queue = smp_processor_id() % h->nreply_queues; | |
1022 | else | |
1023 | cp->reply_queue = reply_queue % h->nreply_queues; | |
1024 | /* Set the bits in the address sent down to include: | |
1025 | * - performant mode bit not used in ioaccel mode 2 | |
1026 | * - pull count (bits 0-3) | |
1027 | * - command type isn't needed for ioaccel2 | |
1028 | */ | |
1029 | c->busaddr |= h->ioaccel2_blockFetchTable[0]; | |
1030 | } | |
1031 | ||
c349775e | 1032 | static void set_ioaccel2_performant_mode(struct ctlr_info *h, |
25163bd5 WS |
1033 | struct CommandList *c, |
1034 | int reply_queue) | |
c349775e ST |
1035 | { |
1036 | struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex]; | |
1037 | ||
25163bd5 WS |
1038 | /* |
1039 | * Tell the controller to post the reply to the queue for this | |
c349775e ST |
1040 | * processor. This seems to give the best I/O throughput. |
1041 | */ | |
25163bd5 WS |
1042 | if (likely(reply_queue == DEFAULT_REPLY_QUEUE)) |
1043 | cp->reply_queue = smp_processor_id() % h->nreply_queues; | |
1044 | else | |
1045 | cp->reply_queue = reply_queue % h->nreply_queues; | |
1046 | /* | |
1047 | * Set the bits in the address sent down to include: | |
c349775e ST |
1048 | * - performant mode bit not used in ioaccel mode 2 |
1049 | * - pull count (bits 0-3) | |
1050 | * - command type isn't needed for ioaccel2 | |
1051 | */ | |
1052 | c->busaddr |= (h->ioaccel2_blockFetchTable[cp->sg_count]); | |
1053 | } | |
1054 | ||
e85c5974 SC |
1055 | static int is_firmware_flash_cmd(u8 *cdb) |
1056 | { | |
1057 | return cdb[0] == BMIC_WRITE && cdb[6] == BMIC_FLASH_FIRMWARE; | |
1058 | } | |
1059 | ||
1060 | /* | |
1061 | * During firmware flash, the heartbeat register may not update as frequently | |
1062 | * as it should. So we dial down lockup detection during firmware flash. and | |
1063 | * dial it back up when firmware flash completes. | |
1064 | */ | |
1065 | #define HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH (240 * HZ) | |
1066 | #define HEARTBEAT_SAMPLE_INTERVAL (30 * HZ) | |
1067 | static void dial_down_lockup_detection_during_fw_flash(struct ctlr_info *h, | |
1068 | struct CommandList *c) | |
1069 | { | |
1070 | if (!is_firmware_flash_cmd(c->Request.CDB)) | |
1071 | return; | |
1072 | atomic_inc(&h->firmware_flash_in_progress); | |
1073 | h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH; | |
1074 | } | |
1075 | ||
1076 | static void dial_up_lockup_detection_on_fw_flash_complete(struct ctlr_info *h, | |
1077 | struct CommandList *c) | |
1078 | { | |
1079 | if (is_firmware_flash_cmd(c->Request.CDB) && | |
1080 | atomic_dec_and_test(&h->firmware_flash_in_progress)) | |
1081 | h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL; | |
1082 | } | |
1083 | ||
25163bd5 WS |
1084 | static void __enqueue_cmd_and_start_io(struct ctlr_info *h, |
1085 | struct CommandList *c, int reply_queue) | |
3f5eac3a | 1086 | { |
c05e8866 SC |
1087 | dial_down_lockup_detection_during_fw_flash(h, c); |
1088 | atomic_inc(&h->commands_outstanding); | |
c349775e ST |
1089 | switch (c->cmd_type) { |
1090 | case CMD_IOACCEL1: | |
25163bd5 | 1091 | set_ioaccel1_performant_mode(h, c, reply_queue); |
c05e8866 | 1092 | writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET); |
c349775e ST |
1093 | break; |
1094 | case CMD_IOACCEL2: | |
25163bd5 | 1095 | set_ioaccel2_performant_mode(h, c, reply_queue); |
c05e8866 | 1096 | writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32); |
c349775e | 1097 | break; |
8be986cc SC |
1098 | case IOACCEL2_TMF: |
1099 | set_ioaccel2_tmf_performant_mode(h, c, reply_queue); | |
1100 | writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32); | |
1101 | break; | |
c349775e | 1102 | default: |
25163bd5 | 1103 | set_performant_mode(h, c, reply_queue); |
c05e8866 | 1104 | h->access.submit_command(h, c); |
c349775e | 1105 | } |
3f5eac3a SC |
1106 | } |
1107 | ||
a58e7e53 | 1108 | static void enqueue_cmd_and_start_io(struct ctlr_info *h, struct CommandList *c) |
25163bd5 | 1109 | { |
d604f533 | 1110 | if (unlikely(hpsa_is_pending_event(c))) |
a58e7e53 WS |
1111 | return finish_cmd(c); |
1112 | ||
25163bd5 WS |
1113 | __enqueue_cmd_and_start_io(h, c, DEFAULT_REPLY_QUEUE); |
1114 | } | |
1115 | ||
3f5eac3a SC |
1116 | static inline int is_hba_lunid(unsigned char scsi3addr[]) |
1117 | { | |
1118 | return memcmp(scsi3addr, RAID_CTLR_LUNID, 8) == 0; | |
1119 | } | |
1120 | ||
1121 | static inline int is_scsi_rev_5(struct ctlr_info *h) | |
1122 | { | |
1123 | if (!h->hba_inquiry_data) | |
1124 | return 0; | |
1125 | if ((h->hba_inquiry_data[2] & 0x07) == 5) | |
1126 | return 1; | |
1127 | return 0; | |
1128 | } | |
1129 | ||
edd16368 SC |
1130 | static int hpsa_find_target_lun(struct ctlr_info *h, |
1131 | unsigned char scsi3addr[], int bus, int *target, int *lun) | |
1132 | { | |
1133 | /* finds an unused bus, target, lun for a new physical device | |
1134 | * assumes h->devlock is held | |
1135 | */ | |
1136 | int i, found = 0; | |
cfe5badc | 1137 | DECLARE_BITMAP(lun_taken, HPSA_MAX_DEVICES); |
edd16368 | 1138 | |
263d9401 | 1139 | bitmap_zero(lun_taken, HPSA_MAX_DEVICES); |
edd16368 SC |
1140 | |
1141 | for (i = 0; i < h->ndevices; i++) { | |
1142 | if (h->dev[i]->bus == bus && h->dev[i]->target != -1) | |
263d9401 | 1143 | __set_bit(h->dev[i]->target, lun_taken); |
edd16368 SC |
1144 | } |
1145 | ||
263d9401 AM |
1146 | i = find_first_zero_bit(lun_taken, HPSA_MAX_DEVICES); |
1147 | if (i < HPSA_MAX_DEVICES) { | |
1148 | /* *bus = 1; */ | |
1149 | *target = i; | |
1150 | *lun = 0; | |
1151 | found = 1; | |
edd16368 SC |
1152 | } |
1153 | return !found; | |
1154 | } | |
1155 | ||
1d33d85d | 1156 | static void hpsa_show_dev_msg(const char *level, struct ctlr_info *h, |
0d96ef5f WS |
1157 | struct hpsa_scsi_dev_t *dev, char *description) |
1158 | { | |
7c59a0d4 DB |
1159 | #define LABEL_SIZE 25 |
1160 | char label[LABEL_SIZE]; | |
1161 | ||
9975ec9d DB |
1162 | if (h == NULL || h->pdev == NULL || h->scsi_host == NULL) |
1163 | return; | |
1164 | ||
7c59a0d4 DB |
1165 | switch (dev->devtype) { |
1166 | case TYPE_RAID: | |
1167 | snprintf(label, LABEL_SIZE, "controller"); | |
1168 | break; | |
1169 | case TYPE_ENCLOSURE: | |
1170 | snprintf(label, LABEL_SIZE, "enclosure"); | |
1171 | break; | |
1172 | case TYPE_DISK: | |
1173 | if (dev->external) | |
1174 | snprintf(label, LABEL_SIZE, "external"); | |
1175 | else if (!is_logical_dev_addr_mode(dev->scsi3addr)) | |
1176 | snprintf(label, LABEL_SIZE, "%s", | |
1177 | raid_label[PHYSICAL_DRIVE]); | |
1178 | else | |
1179 | snprintf(label, LABEL_SIZE, "RAID-%s", | |
1180 | dev->raid_level > RAID_UNKNOWN ? "?" : | |
1181 | raid_label[dev->raid_level]); | |
1182 | break; | |
1183 | case TYPE_ROM: | |
1184 | snprintf(label, LABEL_SIZE, "rom"); | |
1185 | break; | |
1186 | case TYPE_TAPE: | |
1187 | snprintf(label, LABEL_SIZE, "tape"); | |
1188 | break; | |
1189 | case TYPE_MEDIUM_CHANGER: | |
1190 | snprintf(label, LABEL_SIZE, "changer"); | |
1191 | break; | |
1192 | default: | |
1193 | snprintf(label, LABEL_SIZE, "UNKNOWN"); | |
1194 | break; | |
1195 | } | |
1196 | ||
0d96ef5f | 1197 | dev_printk(level, &h->pdev->dev, |
7c59a0d4 | 1198 | "scsi %d:%d:%d:%d: %s %s %.8s %.16s %s SSDSmartPathCap%c En%c Exp=%d\n", |
0d96ef5f WS |
1199 | h->scsi_host->host_no, dev->bus, dev->target, dev->lun, |
1200 | description, | |
1201 | scsi_device_type(dev->devtype), | |
1202 | dev->vendor, | |
1203 | dev->model, | |
7c59a0d4 | 1204 | label, |
0d96ef5f WS |
1205 | dev->offload_config ? '+' : '-', |
1206 | dev->offload_enabled ? '+' : '-', | |
2a168208 | 1207 | dev->expose_device); |
0d96ef5f WS |
1208 | } |
1209 | ||
edd16368 | 1210 | /* Add an entry into h->dev[] array. */ |
8aa60681 | 1211 | static int hpsa_scsi_add_entry(struct ctlr_info *h, |
edd16368 SC |
1212 | struct hpsa_scsi_dev_t *device, |
1213 | struct hpsa_scsi_dev_t *added[], int *nadded) | |
1214 | { | |
1215 | /* assumes h->devlock is held */ | |
1216 | int n = h->ndevices; | |
1217 | int i; | |
1218 | unsigned char addr1[8], addr2[8]; | |
1219 | struct hpsa_scsi_dev_t *sd; | |
1220 | ||
cfe5badc | 1221 | if (n >= HPSA_MAX_DEVICES) { |
edd16368 SC |
1222 | dev_err(&h->pdev->dev, "too many devices, some will be " |
1223 | "inaccessible.\n"); | |
1224 | return -1; | |
1225 | } | |
1226 | ||
1227 | /* physical devices do not have lun or target assigned until now. */ | |
1228 | if (device->lun != -1) | |
1229 | /* Logical device, lun is already assigned. */ | |
1230 | goto lun_assigned; | |
1231 | ||
1232 | /* If this device a non-zero lun of a multi-lun device | |
1233 | * byte 4 of the 8-byte LUN addr will contain the logical | |
2b08b3e9 | 1234 | * unit no, zero otherwise. |
edd16368 SC |
1235 | */ |
1236 | if (device->scsi3addr[4] == 0) { | |
1237 | /* This is not a non-zero lun of a multi-lun device */ | |
1238 | if (hpsa_find_target_lun(h, device->scsi3addr, | |
1239 | device->bus, &device->target, &device->lun) != 0) | |
1240 | return -1; | |
1241 | goto lun_assigned; | |
1242 | } | |
1243 | ||
1244 | /* This is a non-zero lun of a multi-lun device. | |
1245 | * Search through our list and find the device which | |
9a4178b7 | 1246 | * has the same 8 byte LUN address, excepting byte 4 and 5. |
edd16368 SC |
1247 | * Assign the same bus and target for this new LUN. |
1248 | * Use the logical unit number from the firmware. | |
1249 | */ | |
1250 | memcpy(addr1, device->scsi3addr, 8); | |
1251 | addr1[4] = 0; | |
9a4178b7 | 1252 | addr1[5] = 0; |
edd16368 SC |
1253 | for (i = 0; i < n; i++) { |
1254 | sd = h->dev[i]; | |
1255 | memcpy(addr2, sd->scsi3addr, 8); | |
1256 | addr2[4] = 0; | |
9a4178b7 | 1257 | addr2[5] = 0; |
1258 | /* differ only in byte 4 and 5? */ | |
edd16368 SC |
1259 | if (memcmp(addr1, addr2, 8) == 0) { |
1260 | device->bus = sd->bus; | |
1261 | device->target = sd->target; | |
1262 | device->lun = device->scsi3addr[4]; | |
1263 | break; | |
1264 | } | |
1265 | } | |
1266 | if (device->lun == -1) { | |
1267 | dev_warn(&h->pdev->dev, "physical device with no LUN=0," | |
1268 | " suspect firmware bug or unsupported hardware " | |
1269 | "configuration.\n"); | |
1270 | return -1; | |
1271 | } | |
1272 | ||
1273 | lun_assigned: | |
1274 | ||
1275 | h->dev[n] = device; | |
1276 | h->ndevices++; | |
1277 | added[*nadded] = device; | |
1278 | (*nadded)++; | |
0d96ef5f | 1279 | hpsa_show_dev_msg(KERN_INFO, h, device, |
2a168208 | 1280 | device->expose_device ? "added" : "masked"); |
a473d86c RE |
1281 | device->offload_to_be_enabled = device->offload_enabled; |
1282 | device->offload_enabled = 0; | |
edd16368 SC |
1283 | return 0; |
1284 | } | |
1285 | ||
bd9244f7 | 1286 | /* Update an entry in h->dev[] array. */ |
8aa60681 | 1287 | static void hpsa_scsi_update_entry(struct ctlr_info *h, |
bd9244f7 ST |
1288 | int entry, struct hpsa_scsi_dev_t *new_entry) |
1289 | { | |
a473d86c | 1290 | int offload_enabled; |
bd9244f7 ST |
1291 | /* assumes h->devlock is held */ |
1292 | BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES); | |
1293 | ||
1294 | /* Raid level changed. */ | |
1295 | h->dev[entry]->raid_level = new_entry->raid_level; | |
250fb125 | 1296 | |
03383736 DB |
1297 | /* Raid offload parameters changed. Careful about the ordering. */ |
1298 | if (new_entry->offload_config && new_entry->offload_enabled) { | |
1299 | /* | |
1300 | * if drive is newly offload_enabled, we want to copy the | |
1301 | * raid map data first. If previously offload_enabled and | |
1302 | * offload_config were set, raid map data had better be | |
1303 | * the same as it was before. if raid map data is changed | |
1304 | * then it had better be the case that | |
1305 | * h->dev[entry]->offload_enabled is currently 0. | |
1306 | */ | |
1307 | h->dev[entry]->raid_map = new_entry->raid_map; | |
1308 | h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle; | |
03383736 | 1309 | } |
a3144e0b JH |
1310 | if (new_entry->hba_ioaccel_enabled) { |
1311 | h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle; | |
1312 | wmb(); /* set ioaccel_handle *before* hba_ioaccel_enabled */ | |
1313 | } | |
1314 | h->dev[entry]->hba_ioaccel_enabled = new_entry->hba_ioaccel_enabled; | |
250fb125 | 1315 | h->dev[entry]->offload_config = new_entry->offload_config; |
9fb0de2d | 1316 | h->dev[entry]->offload_to_mirror = new_entry->offload_to_mirror; |
03383736 | 1317 | h->dev[entry]->queue_depth = new_entry->queue_depth; |
250fb125 | 1318 | |
41ce4c35 SC |
1319 | /* |
1320 | * We can turn off ioaccel offload now, but need to delay turning | |
1321 | * it on until we can update h->dev[entry]->phys_disk[], but we | |
1322 | * can't do that until all the devices are updated. | |
1323 | */ | |
1324 | h->dev[entry]->offload_to_be_enabled = new_entry->offload_enabled; | |
1325 | if (!new_entry->offload_enabled) | |
1326 | h->dev[entry]->offload_enabled = 0; | |
1327 | ||
a473d86c RE |
1328 | offload_enabled = h->dev[entry]->offload_enabled; |
1329 | h->dev[entry]->offload_enabled = h->dev[entry]->offload_to_be_enabled; | |
0d96ef5f | 1330 | hpsa_show_dev_msg(KERN_INFO, h, h->dev[entry], "updated"); |
a473d86c | 1331 | h->dev[entry]->offload_enabled = offload_enabled; |
bd9244f7 ST |
1332 | } |
1333 | ||
2a8ccf31 | 1334 | /* Replace an entry from h->dev[] array. */ |
8aa60681 | 1335 | static void hpsa_scsi_replace_entry(struct ctlr_info *h, |
2a8ccf31 SC |
1336 | int entry, struct hpsa_scsi_dev_t *new_entry, |
1337 | struct hpsa_scsi_dev_t *added[], int *nadded, | |
1338 | struct hpsa_scsi_dev_t *removed[], int *nremoved) | |
1339 | { | |
1340 | /* assumes h->devlock is held */ | |
cfe5badc | 1341 | BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES); |
2a8ccf31 SC |
1342 | removed[*nremoved] = h->dev[entry]; |
1343 | (*nremoved)++; | |
01350d05 SC |
1344 | |
1345 | /* | |
1346 | * New physical devices won't have target/lun assigned yet | |
1347 | * so we need to preserve the values in the slot we are replacing. | |
1348 | */ | |
1349 | if (new_entry->target == -1) { | |
1350 | new_entry->target = h->dev[entry]->target; | |
1351 | new_entry->lun = h->dev[entry]->lun; | |
1352 | } | |
1353 | ||
2a8ccf31 SC |
1354 | h->dev[entry] = new_entry; |
1355 | added[*nadded] = new_entry; | |
1356 | (*nadded)++; | |
0d96ef5f | 1357 | hpsa_show_dev_msg(KERN_INFO, h, new_entry, "replaced"); |
a473d86c RE |
1358 | new_entry->offload_to_be_enabled = new_entry->offload_enabled; |
1359 | new_entry->offload_enabled = 0; | |
2a8ccf31 SC |
1360 | } |
1361 | ||
edd16368 | 1362 | /* Remove an entry from h->dev[] array. */ |
8aa60681 | 1363 | static void hpsa_scsi_remove_entry(struct ctlr_info *h, int entry, |
edd16368 SC |
1364 | struct hpsa_scsi_dev_t *removed[], int *nremoved) |
1365 | { | |
1366 | /* assumes h->devlock is held */ | |
1367 | int i; | |
1368 | struct hpsa_scsi_dev_t *sd; | |
1369 | ||
cfe5badc | 1370 | BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES); |
edd16368 SC |
1371 | |
1372 | sd = h->dev[entry]; | |
1373 | removed[*nremoved] = h->dev[entry]; | |
1374 | (*nremoved)++; | |
1375 | ||
1376 | for (i = entry; i < h->ndevices-1; i++) | |
1377 | h->dev[i] = h->dev[i+1]; | |
1378 | h->ndevices--; | |
0d96ef5f | 1379 | hpsa_show_dev_msg(KERN_INFO, h, sd, "removed"); |
edd16368 SC |
1380 | } |
1381 | ||
1382 | #define SCSI3ADDR_EQ(a, b) ( \ | |
1383 | (a)[7] == (b)[7] && \ | |
1384 | (a)[6] == (b)[6] && \ | |
1385 | (a)[5] == (b)[5] && \ | |
1386 | (a)[4] == (b)[4] && \ | |
1387 | (a)[3] == (b)[3] && \ | |
1388 | (a)[2] == (b)[2] && \ | |
1389 | (a)[1] == (b)[1] && \ | |
1390 | (a)[0] == (b)[0]) | |
1391 | ||
1392 | static void fixup_botched_add(struct ctlr_info *h, | |
1393 | struct hpsa_scsi_dev_t *added) | |
1394 | { | |
1395 | /* called when scsi_add_device fails in order to re-adjust | |
1396 | * h->dev[] to match the mid layer's view. | |
1397 | */ | |
1398 | unsigned long flags; | |
1399 | int i, j; | |
1400 | ||
1401 | spin_lock_irqsave(&h->lock, flags); | |
1402 | for (i = 0; i < h->ndevices; i++) { | |
1403 | if (h->dev[i] == added) { | |
1404 | for (j = i; j < h->ndevices-1; j++) | |
1405 | h->dev[j] = h->dev[j+1]; | |
1406 | h->ndevices--; | |
1407 | break; | |
1408 | } | |
1409 | } | |
1410 | spin_unlock_irqrestore(&h->lock, flags); | |
1411 | kfree(added); | |
1412 | } | |
1413 | ||
1414 | static inline int device_is_the_same(struct hpsa_scsi_dev_t *dev1, | |
1415 | struct hpsa_scsi_dev_t *dev2) | |
1416 | { | |
edd16368 SC |
1417 | /* we compare everything except lun and target as these |
1418 | * are not yet assigned. Compare parts likely | |
1419 | * to differ first | |
1420 | */ | |
1421 | if (memcmp(dev1->scsi3addr, dev2->scsi3addr, | |
1422 | sizeof(dev1->scsi3addr)) != 0) | |
1423 | return 0; | |
1424 | if (memcmp(dev1->device_id, dev2->device_id, | |
1425 | sizeof(dev1->device_id)) != 0) | |
1426 | return 0; | |
1427 | if (memcmp(dev1->model, dev2->model, sizeof(dev1->model)) != 0) | |
1428 | return 0; | |
1429 | if (memcmp(dev1->vendor, dev2->vendor, sizeof(dev1->vendor)) != 0) | |
1430 | return 0; | |
edd16368 SC |
1431 | if (dev1->devtype != dev2->devtype) |
1432 | return 0; | |
edd16368 SC |
1433 | if (dev1->bus != dev2->bus) |
1434 | return 0; | |
1435 | return 1; | |
1436 | } | |
1437 | ||
bd9244f7 ST |
1438 | static inline int device_updated(struct hpsa_scsi_dev_t *dev1, |
1439 | struct hpsa_scsi_dev_t *dev2) | |
1440 | { | |
1441 | /* Device attributes that can change, but don't mean | |
1442 | * that the device is a different device, nor that the OS | |
1443 | * needs to be told anything about the change. | |
1444 | */ | |
1445 | if (dev1->raid_level != dev2->raid_level) | |
1446 | return 1; | |
250fb125 SC |
1447 | if (dev1->offload_config != dev2->offload_config) |
1448 | return 1; | |
1449 | if (dev1->offload_enabled != dev2->offload_enabled) | |
1450 | return 1; | |
93849508 DB |
1451 | if (!is_logical_dev_addr_mode(dev1->scsi3addr)) |
1452 | if (dev1->queue_depth != dev2->queue_depth) | |
1453 | return 1; | |
bd9244f7 ST |
1454 | return 0; |
1455 | } | |
1456 | ||
edd16368 SC |
1457 | /* Find needle in haystack. If exact match found, return DEVICE_SAME, |
1458 | * and return needle location in *index. If scsi3addr matches, but not | |
1459 | * vendor, model, serial num, etc. return DEVICE_CHANGED, and return needle | |
bd9244f7 ST |
1460 | * location in *index. |
1461 | * In the case of a minor device attribute change, such as RAID level, just | |
1462 | * return DEVICE_UPDATED, along with the updated device's location in index. | |
1463 | * If needle not found, return DEVICE_NOT_FOUND. | |
edd16368 SC |
1464 | */ |
1465 | static int hpsa_scsi_find_entry(struct hpsa_scsi_dev_t *needle, | |
1466 | struct hpsa_scsi_dev_t *haystack[], int haystack_size, | |
1467 | int *index) | |
1468 | { | |
1469 | int i; | |
1470 | #define DEVICE_NOT_FOUND 0 | |
1471 | #define DEVICE_CHANGED 1 | |
1472 | #define DEVICE_SAME 2 | |
bd9244f7 | 1473 | #define DEVICE_UPDATED 3 |
1d33d85d DB |
1474 | if (needle == NULL) |
1475 | return DEVICE_NOT_FOUND; | |
1476 | ||
edd16368 | 1477 | for (i = 0; i < haystack_size; i++) { |
23231048 SC |
1478 | if (haystack[i] == NULL) /* previously removed. */ |
1479 | continue; | |
edd16368 SC |
1480 | if (SCSI3ADDR_EQ(needle->scsi3addr, haystack[i]->scsi3addr)) { |
1481 | *index = i; | |
bd9244f7 ST |
1482 | if (device_is_the_same(needle, haystack[i])) { |
1483 | if (device_updated(needle, haystack[i])) | |
1484 | return DEVICE_UPDATED; | |
edd16368 | 1485 | return DEVICE_SAME; |
bd9244f7 | 1486 | } else { |
9846590e SC |
1487 | /* Keep offline devices offline */ |
1488 | if (needle->volume_offline) | |
1489 | return DEVICE_NOT_FOUND; | |
edd16368 | 1490 | return DEVICE_CHANGED; |
bd9244f7 | 1491 | } |
edd16368 SC |
1492 | } |
1493 | } | |
1494 | *index = -1; | |
1495 | return DEVICE_NOT_FOUND; | |
1496 | } | |
1497 | ||
9846590e SC |
1498 | static void hpsa_monitor_offline_device(struct ctlr_info *h, |
1499 | unsigned char scsi3addr[]) | |
1500 | { | |
1501 | struct offline_device_entry *device; | |
1502 | unsigned long flags; | |
1503 | ||
1504 | /* Check to see if device is already on the list */ | |
1505 | spin_lock_irqsave(&h->offline_device_lock, flags); | |
1506 | list_for_each_entry(device, &h->offline_device_list, offline_list) { | |
1507 | if (memcmp(device->scsi3addr, scsi3addr, | |
1508 | sizeof(device->scsi3addr)) == 0) { | |
1509 | spin_unlock_irqrestore(&h->offline_device_lock, flags); | |
1510 | return; | |
1511 | } | |
1512 | } | |
1513 | spin_unlock_irqrestore(&h->offline_device_lock, flags); | |
1514 | ||
1515 | /* Device is not on the list, add it. */ | |
1516 | device = kmalloc(sizeof(*device), GFP_KERNEL); | |
1517 | if (!device) { | |
1518 | dev_warn(&h->pdev->dev, "out of memory in %s\n", __func__); | |
1519 | return; | |
1520 | } | |
1521 | memcpy(device->scsi3addr, scsi3addr, sizeof(device->scsi3addr)); | |
1522 | spin_lock_irqsave(&h->offline_device_lock, flags); | |
1523 | list_add_tail(&device->offline_list, &h->offline_device_list); | |
1524 | spin_unlock_irqrestore(&h->offline_device_lock, flags); | |
1525 | } | |
1526 | ||
1527 | /* Print a message explaining various offline volume states */ | |
1528 | static void hpsa_show_volume_status(struct ctlr_info *h, | |
1529 | struct hpsa_scsi_dev_t *sd) | |
1530 | { | |
1531 | if (sd->volume_offline == HPSA_VPD_LV_STATUS_UNSUPPORTED) | |
1532 | dev_info(&h->pdev->dev, | |
1533 | "C%d:B%d:T%d:L%d Volume status is not available through vital product data pages.\n", | |
1534 | h->scsi_host->host_no, | |
1535 | sd->bus, sd->target, sd->lun); | |
1536 | switch (sd->volume_offline) { | |
1537 | case HPSA_LV_OK: | |
1538 | break; | |
1539 | case HPSA_LV_UNDERGOING_ERASE: | |
1540 | dev_info(&h->pdev->dev, | |
1541 | "C%d:B%d:T%d:L%d Volume is undergoing background erase process.\n", | |
1542 | h->scsi_host->host_no, | |
1543 | sd->bus, sd->target, sd->lun); | |
1544 | break; | |
5ca01204 SB |
1545 | case HPSA_LV_NOT_AVAILABLE: |
1546 | dev_info(&h->pdev->dev, | |
1547 | "C%d:B%d:T%d:L%d Volume is waiting for transforming volume.\n", | |
1548 | h->scsi_host->host_no, | |
1549 | sd->bus, sd->target, sd->lun); | |
1550 | break; | |
9846590e SC |
1551 | case HPSA_LV_UNDERGOING_RPI: |
1552 | dev_info(&h->pdev->dev, | |
5ca01204 | 1553 | "C%d:B%d:T%d:L%d Volume is undergoing rapid parity init.\n", |
9846590e SC |
1554 | h->scsi_host->host_no, |
1555 | sd->bus, sd->target, sd->lun); | |
1556 | break; | |
1557 | case HPSA_LV_PENDING_RPI: | |
1558 | dev_info(&h->pdev->dev, | |
5ca01204 SB |
1559 | "C%d:B%d:T%d:L%d Volume is queued for rapid parity initialization process.\n", |
1560 | h->scsi_host->host_no, | |
1561 | sd->bus, sd->target, sd->lun); | |
9846590e SC |
1562 | break; |
1563 | case HPSA_LV_ENCRYPTED_NO_KEY: | |
1564 | dev_info(&h->pdev->dev, | |
1565 | "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because key is not present.\n", | |
1566 | h->scsi_host->host_no, | |
1567 | sd->bus, sd->target, sd->lun); | |
1568 | break; | |
1569 | case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER: | |
1570 | dev_info(&h->pdev->dev, | |
1571 | "C%d:B%d:T%d:L%d Volume is not encrypted and cannot be accessed because controller is in encryption-only mode.\n", | |
1572 | h->scsi_host->host_no, | |
1573 | sd->bus, sd->target, sd->lun); | |
1574 | break; | |
1575 | case HPSA_LV_UNDERGOING_ENCRYPTION: | |
1576 | dev_info(&h->pdev->dev, | |
1577 | "C%d:B%d:T%d:L%d Volume is undergoing encryption process.\n", | |
1578 | h->scsi_host->host_no, | |
1579 | sd->bus, sd->target, sd->lun); | |
1580 | break; | |
1581 | case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING: | |
1582 | dev_info(&h->pdev->dev, | |
1583 | "C%d:B%d:T%d:L%d Volume is undergoing encryption re-keying process.\n", | |
1584 | h->scsi_host->host_no, | |
1585 | sd->bus, sd->target, sd->lun); | |
1586 | break; | |
1587 | case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER: | |
1588 | dev_info(&h->pdev->dev, | |
1589 | "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because controller does not have encryption enabled.\n", | |
1590 | h->scsi_host->host_no, | |
1591 | sd->bus, sd->target, sd->lun); | |
1592 | break; | |
1593 | case HPSA_LV_PENDING_ENCRYPTION: | |
1594 | dev_info(&h->pdev->dev, | |
1595 | "C%d:B%d:T%d:L%d Volume is pending migration to encrypted state, but process has not started.\n", | |
1596 | h->scsi_host->host_no, | |
1597 | sd->bus, sd->target, sd->lun); | |
1598 | break; | |
1599 | case HPSA_LV_PENDING_ENCRYPTION_REKEYING: | |
1600 | dev_info(&h->pdev->dev, | |
1601 | "C%d:B%d:T%d:L%d Volume is encrypted and is pending encryption rekeying.\n", | |
1602 | h->scsi_host->host_no, | |
1603 | sd->bus, sd->target, sd->lun); | |
1604 | break; | |
1605 | } | |
1606 | } | |
1607 | ||
03383736 DB |
1608 | /* |
1609 | * Figure the list of physical drive pointers for a logical drive with | |
1610 | * raid offload configured. | |
1611 | */ | |
1612 | static void hpsa_figure_phys_disk_ptrs(struct ctlr_info *h, | |
1613 | struct hpsa_scsi_dev_t *dev[], int ndevices, | |
1614 | struct hpsa_scsi_dev_t *logical_drive) | |
1615 | { | |
1616 | struct raid_map_data *map = &logical_drive->raid_map; | |
1617 | struct raid_map_disk_data *dd = &map->data[0]; | |
1618 | int i, j; | |
1619 | int total_disks_per_row = le16_to_cpu(map->data_disks_per_row) + | |
1620 | le16_to_cpu(map->metadata_disks_per_row); | |
1621 | int nraid_map_entries = le16_to_cpu(map->row_cnt) * | |
1622 | le16_to_cpu(map->layout_map_count) * | |
1623 | total_disks_per_row; | |
1624 | int nphys_disk = le16_to_cpu(map->layout_map_count) * | |
1625 | total_disks_per_row; | |
1626 | int qdepth; | |
1627 | ||
1628 | if (nraid_map_entries > RAID_MAP_MAX_ENTRIES) | |
1629 | nraid_map_entries = RAID_MAP_MAX_ENTRIES; | |
1630 | ||
d604f533 WS |
1631 | logical_drive->nphysical_disks = nraid_map_entries; |
1632 | ||
03383736 DB |
1633 | qdepth = 0; |
1634 | for (i = 0; i < nraid_map_entries; i++) { | |
1635 | logical_drive->phys_disk[i] = NULL; | |
1636 | if (!logical_drive->offload_config) | |
1637 | continue; | |
1638 | for (j = 0; j < ndevices; j++) { | |
1d33d85d DB |
1639 | if (dev[j] == NULL) |
1640 | continue; | |
03383736 DB |
1641 | if (dev[j]->devtype != TYPE_DISK) |
1642 | continue; | |
f3f01730 | 1643 | if (is_logical_device(dev[j])) |
03383736 DB |
1644 | continue; |
1645 | if (dev[j]->ioaccel_handle != dd[i].ioaccel_handle) | |
1646 | continue; | |
1647 | ||
1648 | logical_drive->phys_disk[i] = dev[j]; | |
1649 | if (i < nphys_disk) | |
1650 | qdepth = min(h->nr_cmds, qdepth + | |
1651 | logical_drive->phys_disk[i]->queue_depth); | |
1652 | break; | |
1653 | } | |
1654 | ||
1655 | /* | |
1656 | * This can happen if a physical drive is removed and | |
1657 | * the logical drive is degraded. In that case, the RAID | |
1658 | * map data will refer to a physical disk which isn't actually | |
1659 | * present. And in that case offload_enabled should already | |
1660 | * be 0, but we'll turn it off here just in case | |
1661 | */ | |
1662 | if (!logical_drive->phys_disk[i]) { | |
1663 | logical_drive->offload_enabled = 0; | |
41ce4c35 SC |
1664 | logical_drive->offload_to_be_enabled = 0; |
1665 | logical_drive->queue_depth = 8; | |
03383736 DB |
1666 | } |
1667 | } | |
1668 | if (nraid_map_entries) | |
1669 | /* | |
1670 | * This is correct for reads, too high for full stripe writes, | |
1671 | * way too high for partial stripe writes | |
1672 | */ | |
1673 | logical_drive->queue_depth = qdepth; | |
1674 | else | |
1675 | logical_drive->queue_depth = h->nr_cmds; | |
1676 | } | |
1677 | ||
1678 | static void hpsa_update_log_drive_phys_drive_ptrs(struct ctlr_info *h, | |
1679 | struct hpsa_scsi_dev_t *dev[], int ndevices) | |
1680 | { | |
1681 | int i; | |
1682 | ||
1683 | for (i = 0; i < ndevices; i++) { | |
1d33d85d DB |
1684 | if (dev[i] == NULL) |
1685 | continue; | |
03383736 DB |
1686 | if (dev[i]->devtype != TYPE_DISK) |
1687 | continue; | |
f3f01730 | 1688 | if (!is_logical_device(dev[i])) |
03383736 | 1689 | continue; |
41ce4c35 SC |
1690 | |
1691 | /* | |
1692 | * If offload is currently enabled, the RAID map and | |
1693 | * phys_disk[] assignment *better* not be changing | |
1694 | * and since it isn't changing, we do not need to | |
1695 | * update it. | |
1696 | */ | |
1697 | if (dev[i]->offload_enabled) | |
1698 | continue; | |
1699 | ||
03383736 DB |
1700 | hpsa_figure_phys_disk_ptrs(h, dev, ndevices, dev[i]); |
1701 | } | |
1702 | } | |
1703 | ||
096ccff4 KB |
1704 | static int hpsa_add_device(struct ctlr_info *h, struct hpsa_scsi_dev_t *device) |
1705 | { | |
1706 | int rc = 0; | |
1707 | ||
1708 | if (!h->scsi_host) | |
1709 | return 1; | |
1710 | ||
d04e62b9 KB |
1711 | if (is_logical_device(device)) /* RAID */ |
1712 | rc = scsi_add_device(h->scsi_host, device->bus, | |
096ccff4 | 1713 | device->target, device->lun); |
d04e62b9 KB |
1714 | else /* HBA */ |
1715 | rc = hpsa_add_sas_device(h->sas_host, device); | |
1716 | ||
096ccff4 KB |
1717 | return rc; |
1718 | } | |
1719 | ||
1720 | static void hpsa_remove_device(struct ctlr_info *h, | |
1721 | struct hpsa_scsi_dev_t *device) | |
1722 | { | |
1723 | struct scsi_device *sdev = NULL; | |
1724 | ||
1725 | if (!h->scsi_host) | |
1726 | return; | |
1727 | ||
d04e62b9 KB |
1728 | if (is_logical_device(device)) { /* RAID */ |
1729 | sdev = scsi_device_lookup(h->scsi_host, device->bus, | |
096ccff4 | 1730 | device->target, device->lun); |
d04e62b9 KB |
1731 | if (sdev) { |
1732 | scsi_remove_device(sdev); | |
1733 | scsi_device_put(sdev); | |
1734 | } else { | |
1735 | /* | |
1736 | * We don't expect to get here. Future commands | |
1737 | * to this device will get a selection timeout as | |
1738 | * if the device were gone. | |
1739 | */ | |
1740 | hpsa_show_dev_msg(KERN_WARNING, h, device, | |
096ccff4 | 1741 | "didn't find device for removal."); |
d04e62b9 KB |
1742 | } |
1743 | } else /* HBA */ | |
1744 | hpsa_remove_sas_device(device); | |
096ccff4 KB |
1745 | } |
1746 | ||
8aa60681 | 1747 | static void adjust_hpsa_scsi_table(struct ctlr_info *h, |
edd16368 SC |
1748 | struct hpsa_scsi_dev_t *sd[], int nsds) |
1749 | { | |
1750 | /* sd contains scsi3 addresses and devtypes, and inquiry | |
1751 | * data. This function takes what's in sd to be the current | |
1752 | * reality and updates h->dev[] to reflect that reality. | |
1753 | */ | |
1754 | int i, entry, device_change, changes = 0; | |
1755 | struct hpsa_scsi_dev_t *csd; | |
1756 | unsigned long flags; | |
1757 | struct hpsa_scsi_dev_t **added, **removed; | |
1758 | int nadded, nremoved; | |
edd16368 | 1759 | |
da03ded0 DB |
1760 | /* |
1761 | * A reset can cause a device status to change | |
1762 | * re-schedule the scan to see what happened. | |
1763 | */ | |
1764 | if (h->reset_in_progress) { | |
1765 | h->drv_req_rescan = 1; | |
1766 | return; | |
1767 | } | |
edd16368 | 1768 | |
cfe5badc ST |
1769 | added = kzalloc(sizeof(*added) * HPSA_MAX_DEVICES, GFP_KERNEL); |
1770 | removed = kzalloc(sizeof(*removed) * HPSA_MAX_DEVICES, GFP_KERNEL); | |
edd16368 SC |
1771 | |
1772 | if (!added || !removed) { | |
1773 | dev_warn(&h->pdev->dev, "out of memory in " | |
1774 | "adjust_hpsa_scsi_table\n"); | |
1775 | goto free_and_out; | |
1776 | } | |
1777 | ||
1778 | spin_lock_irqsave(&h->devlock, flags); | |
1779 | ||
1780 | /* find any devices in h->dev[] that are not in | |
1781 | * sd[] and remove them from h->dev[], and for any | |
1782 | * devices which have changed, remove the old device | |
1783 | * info and add the new device info. | |
bd9244f7 ST |
1784 | * If minor device attributes change, just update |
1785 | * the existing device structure. | |
edd16368 SC |
1786 | */ |
1787 | i = 0; | |
1788 | nremoved = 0; | |
1789 | nadded = 0; | |
1790 | while (i < h->ndevices) { | |
1791 | csd = h->dev[i]; | |
1792 | device_change = hpsa_scsi_find_entry(csd, sd, nsds, &entry); | |
1793 | if (device_change == DEVICE_NOT_FOUND) { | |
1794 | changes++; | |
8aa60681 | 1795 | hpsa_scsi_remove_entry(h, i, removed, &nremoved); |
edd16368 SC |
1796 | continue; /* remove ^^^, hence i not incremented */ |
1797 | } else if (device_change == DEVICE_CHANGED) { | |
1798 | changes++; | |
8aa60681 | 1799 | hpsa_scsi_replace_entry(h, i, sd[entry], |
2a8ccf31 | 1800 | added, &nadded, removed, &nremoved); |
c7f172dc SC |
1801 | /* Set it to NULL to prevent it from being freed |
1802 | * at the bottom of hpsa_update_scsi_devices() | |
1803 | */ | |
1804 | sd[entry] = NULL; | |
bd9244f7 | 1805 | } else if (device_change == DEVICE_UPDATED) { |
8aa60681 | 1806 | hpsa_scsi_update_entry(h, i, sd[entry]); |
edd16368 SC |
1807 | } |
1808 | i++; | |
1809 | } | |
1810 | ||
1811 | /* Now, make sure every device listed in sd[] is also | |
1812 | * listed in h->dev[], adding them if they aren't found | |
1813 | */ | |
1814 | ||
1815 | for (i = 0; i < nsds; i++) { | |
1816 | if (!sd[i]) /* if already added above. */ | |
1817 | continue; | |
9846590e SC |
1818 | |
1819 | /* Don't add devices which are NOT READY, FORMAT IN PROGRESS | |
1820 | * as the SCSI mid-layer does not handle such devices well. | |
1821 | * It relentlessly loops sending TUR at 3Hz, then READ(10) | |
1822 | * at 160Hz, and prevents the system from coming up. | |
1823 | */ | |
1824 | if (sd[i]->volume_offline) { | |
1825 | hpsa_show_volume_status(h, sd[i]); | |
0d96ef5f | 1826 | hpsa_show_dev_msg(KERN_INFO, h, sd[i], "offline"); |
9846590e SC |
1827 | continue; |
1828 | } | |
1829 | ||
edd16368 SC |
1830 | device_change = hpsa_scsi_find_entry(sd[i], h->dev, |
1831 | h->ndevices, &entry); | |
1832 | if (device_change == DEVICE_NOT_FOUND) { | |
1833 | changes++; | |
8aa60681 | 1834 | if (hpsa_scsi_add_entry(h, sd[i], added, &nadded) != 0) |
edd16368 SC |
1835 | break; |
1836 | sd[i] = NULL; /* prevent from being freed later. */ | |
1837 | } else if (device_change == DEVICE_CHANGED) { | |
1838 | /* should never happen... */ | |
1839 | changes++; | |
1840 | dev_warn(&h->pdev->dev, | |
1841 | "device unexpectedly changed.\n"); | |
1842 | /* but if it does happen, we just ignore that device */ | |
1843 | } | |
1844 | } | |
41ce4c35 SC |
1845 | hpsa_update_log_drive_phys_drive_ptrs(h, h->dev, h->ndevices); |
1846 | ||
1847 | /* Now that h->dev[]->phys_disk[] is coherent, we can enable | |
1848 | * any logical drives that need it enabled. | |
1849 | */ | |
1d33d85d DB |
1850 | for (i = 0; i < h->ndevices; i++) { |
1851 | if (h->dev[i] == NULL) | |
1852 | continue; | |
41ce4c35 | 1853 | h->dev[i]->offload_enabled = h->dev[i]->offload_to_be_enabled; |
1d33d85d | 1854 | } |
41ce4c35 | 1855 | |
edd16368 SC |
1856 | spin_unlock_irqrestore(&h->devlock, flags); |
1857 | ||
9846590e SC |
1858 | /* Monitor devices which are in one of several NOT READY states to be |
1859 | * brought online later. This must be done without holding h->devlock, | |
1860 | * so don't touch h->dev[] | |
1861 | */ | |
1862 | for (i = 0; i < nsds; i++) { | |
1863 | if (!sd[i]) /* if already added above. */ | |
1864 | continue; | |
1865 | if (sd[i]->volume_offline) | |
1866 | hpsa_monitor_offline_device(h, sd[i]->scsi3addr); | |
1867 | } | |
1868 | ||
edd16368 SC |
1869 | /* Don't notify scsi mid layer of any changes the first time through |
1870 | * (or if there are no changes) scsi_scan_host will do it later the | |
1871 | * first time through. | |
1872 | */ | |
8aa60681 | 1873 | if (!changes) |
edd16368 SC |
1874 | goto free_and_out; |
1875 | ||
edd16368 SC |
1876 | /* Notify scsi mid layer of any removed devices */ |
1877 | for (i = 0; i < nremoved; i++) { | |
1d33d85d DB |
1878 | if (removed[i] == NULL) |
1879 | continue; | |
096ccff4 KB |
1880 | if (removed[i]->expose_device) |
1881 | hpsa_remove_device(h, removed[i]); | |
edd16368 SC |
1882 | kfree(removed[i]); |
1883 | removed[i] = NULL; | |
1884 | } | |
1885 | ||
1886 | /* Notify scsi mid layer of any added devices */ | |
1887 | for (i = 0; i < nadded; i++) { | |
096ccff4 KB |
1888 | int rc = 0; |
1889 | ||
1d33d85d DB |
1890 | if (added[i] == NULL) |
1891 | continue; | |
2a168208 | 1892 | if (!(added[i]->expose_device)) |
41ce4c35 | 1893 | continue; |
096ccff4 KB |
1894 | rc = hpsa_add_device(h, added[i]); |
1895 | if (!rc) | |
edd16368 | 1896 | continue; |
096ccff4 KB |
1897 | dev_warn(&h->pdev->dev, |
1898 | "addition failed %d, device not added.", rc); | |
edd16368 SC |
1899 | /* now we have to remove it from h->dev, |
1900 | * since it didn't get added to scsi mid layer | |
1901 | */ | |
1902 | fixup_botched_add(h, added[i]); | |
853633e8 | 1903 | h->drv_req_rescan = 1; |
edd16368 SC |
1904 | } |
1905 | ||
1906 | free_and_out: | |
1907 | kfree(added); | |
1908 | kfree(removed); | |
edd16368 SC |
1909 | } |
1910 | ||
1911 | /* | |
9e03aa2f | 1912 | * Lookup bus/target/lun and return corresponding struct hpsa_scsi_dev_t * |
edd16368 SC |
1913 | * Assume's h->devlock is held. |
1914 | */ | |
1915 | static struct hpsa_scsi_dev_t *lookup_hpsa_scsi_dev(struct ctlr_info *h, | |
1916 | int bus, int target, int lun) | |
1917 | { | |
1918 | int i; | |
1919 | struct hpsa_scsi_dev_t *sd; | |
1920 | ||
1921 | for (i = 0; i < h->ndevices; i++) { | |
1922 | sd = h->dev[i]; | |
1923 | if (sd->bus == bus && sd->target == target && sd->lun == lun) | |
1924 | return sd; | |
1925 | } | |
1926 | return NULL; | |
1927 | } | |
1928 | ||
edd16368 SC |
1929 | static int hpsa_slave_alloc(struct scsi_device *sdev) |
1930 | { | |
1931 | struct hpsa_scsi_dev_t *sd; | |
1932 | unsigned long flags; | |
1933 | struct ctlr_info *h; | |
1934 | ||
1935 | h = sdev_to_hba(sdev); | |
1936 | spin_lock_irqsave(&h->devlock, flags); | |
d04e62b9 KB |
1937 | if (sdev_channel(sdev) == HPSA_PHYSICAL_DEVICE_BUS) { |
1938 | struct scsi_target *starget; | |
1939 | struct sas_rphy *rphy; | |
1940 | ||
1941 | starget = scsi_target(sdev); | |
1942 | rphy = target_to_rphy(starget); | |
1943 | sd = hpsa_find_device_by_sas_rphy(h, rphy); | |
1944 | if (sd) { | |
1945 | sd->target = sdev_id(sdev); | |
1946 | sd->lun = sdev->lun; | |
1947 | } | |
1948 | } else | |
1949 | sd = lookup_hpsa_scsi_dev(h, sdev_channel(sdev), | |
1950 | sdev_id(sdev), sdev->lun); | |
1951 | ||
1952 | if (sd && sd->expose_device) { | |
03383736 | 1953 | atomic_set(&sd->ioaccel_cmds_out, 0); |
d04e62b9 | 1954 | sdev->hostdata = sd; |
41ce4c35 SC |
1955 | } else |
1956 | sdev->hostdata = NULL; | |
edd16368 SC |
1957 | spin_unlock_irqrestore(&h->devlock, flags); |
1958 | return 0; | |
1959 | } | |
1960 | ||
41ce4c35 SC |
1961 | /* configure scsi device based on internal per-device structure */ |
1962 | static int hpsa_slave_configure(struct scsi_device *sdev) | |
1963 | { | |
1964 | struct hpsa_scsi_dev_t *sd; | |
1965 | int queue_depth; | |
1966 | ||
1967 | sd = sdev->hostdata; | |
2a168208 | 1968 | sdev->no_uld_attach = !sd || !sd->expose_device; |
41ce4c35 SC |
1969 | |
1970 | if (sd) | |
1971 | queue_depth = sd->queue_depth != 0 ? | |
1972 | sd->queue_depth : sdev->host->can_queue; | |
1973 | else | |
1974 | queue_depth = sdev->host->can_queue; | |
1975 | ||
1976 | scsi_change_queue_depth(sdev, queue_depth); | |
1977 | ||
1978 | return 0; | |
1979 | } | |
1980 | ||
edd16368 SC |
1981 | static void hpsa_slave_destroy(struct scsi_device *sdev) |
1982 | { | |
bcc44255 | 1983 | /* nothing to do. */ |
edd16368 SC |
1984 | } |
1985 | ||
d9a729f3 WS |
1986 | static void hpsa_free_ioaccel2_sg_chain_blocks(struct ctlr_info *h) |
1987 | { | |
1988 | int i; | |
1989 | ||
1990 | if (!h->ioaccel2_cmd_sg_list) | |
1991 | return; | |
1992 | for (i = 0; i < h->nr_cmds; i++) { | |
1993 | kfree(h->ioaccel2_cmd_sg_list[i]); | |
1994 | h->ioaccel2_cmd_sg_list[i] = NULL; | |
1995 | } | |
1996 | kfree(h->ioaccel2_cmd_sg_list); | |
1997 | h->ioaccel2_cmd_sg_list = NULL; | |
1998 | } | |
1999 | ||
2000 | static int hpsa_allocate_ioaccel2_sg_chain_blocks(struct ctlr_info *h) | |
2001 | { | |
2002 | int i; | |
2003 | ||
2004 | if (h->chainsize <= 0) | |
2005 | return 0; | |
2006 | ||
2007 | h->ioaccel2_cmd_sg_list = | |
2008 | kzalloc(sizeof(*h->ioaccel2_cmd_sg_list) * h->nr_cmds, | |
2009 | GFP_KERNEL); | |
2010 | if (!h->ioaccel2_cmd_sg_list) | |
2011 | return -ENOMEM; | |
2012 | for (i = 0; i < h->nr_cmds; i++) { | |
2013 | h->ioaccel2_cmd_sg_list[i] = | |
2014 | kmalloc(sizeof(*h->ioaccel2_cmd_sg_list[i]) * | |
2015 | h->maxsgentries, GFP_KERNEL); | |
2016 | if (!h->ioaccel2_cmd_sg_list[i]) | |
2017 | goto clean; | |
2018 | } | |
2019 | return 0; | |
2020 | ||
2021 | clean: | |
2022 | hpsa_free_ioaccel2_sg_chain_blocks(h); | |
2023 | return -ENOMEM; | |
2024 | } | |
2025 | ||
33a2ffce SC |
2026 | static void hpsa_free_sg_chain_blocks(struct ctlr_info *h) |
2027 | { | |
2028 | int i; | |
2029 | ||
2030 | if (!h->cmd_sg_list) | |
2031 | return; | |
2032 | for (i = 0; i < h->nr_cmds; i++) { | |
2033 | kfree(h->cmd_sg_list[i]); | |
2034 | h->cmd_sg_list[i] = NULL; | |
2035 | } | |
2036 | kfree(h->cmd_sg_list); | |
2037 | h->cmd_sg_list = NULL; | |
2038 | } | |
2039 | ||
105a3dbc | 2040 | static int hpsa_alloc_sg_chain_blocks(struct ctlr_info *h) |
33a2ffce SC |
2041 | { |
2042 | int i; | |
2043 | ||
2044 | if (h->chainsize <= 0) | |
2045 | return 0; | |
2046 | ||
2047 | h->cmd_sg_list = kzalloc(sizeof(*h->cmd_sg_list) * h->nr_cmds, | |
2048 | GFP_KERNEL); | |
3d4e6af8 RE |
2049 | if (!h->cmd_sg_list) { |
2050 | dev_err(&h->pdev->dev, "Failed to allocate SG list\n"); | |
33a2ffce | 2051 | return -ENOMEM; |
3d4e6af8 | 2052 | } |
33a2ffce SC |
2053 | for (i = 0; i < h->nr_cmds; i++) { |
2054 | h->cmd_sg_list[i] = kmalloc(sizeof(*h->cmd_sg_list[i]) * | |
2055 | h->chainsize, GFP_KERNEL); | |
3d4e6af8 RE |
2056 | if (!h->cmd_sg_list[i]) { |
2057 | dev_err(&h->pdev->dev, "Failed to allocate cmd SG\n"); | |
33a2ffce | 2058 | goto clean; |
3d4e6af8 | 2059 | } |
33a2ffce SC |
2060 | } |
2061 | return 0; | |
2062 | ||
2063 | clean: | |
2064 | hpsa_free_sg_chain_blocks(h); | |
2065 | return -ENOMEM; | |
2066 | } | |
2067 | ||
d9a729f3 WS |
2068 | static int hpsa_map_ioaccel2_sg_chain_block(struct ctlr_info *h, |
2069 | struct io_accel2_cmd *cp, struct CommandList *c) | |
2070 | { | |
2071 | struct ioaccel2_sg_element *chain_block; | |
2072 | u64 temp64; | |
2073 | u32 chain_size; | |
2074 | ||
2075 | chain_block = h->ioaccel2_cmd_sg_list[c->cmdindex]; | |
a736e9b6 | 2076 | chain_size = le32_to_cpu(cp->sg[0].length); |
d9a729f3 WS |
2077 | temp64 = pci_map_single(h->pdev, chain_block, chain_size, |
2078 | PCI_DMA_TODEVICE); | |
2079 | if (dma_mapping_error(&h->pdev->dev, temp64)) { | |
2080 | /* prevent subsequent unmapping */ | |
2081 | cp->sg->address = 0; | |
2082 | return -1; | |
2083 | } | |
2084 | cp->sg->address = cpu_to_le64(temp64); | |
2085 | return 0; | |
2086 | } | |
2087 | ||
2088 | static void hpsa_unmap_ioaccel2_sg_chain_block(struct ctlr_info *h, | |
2089 | struct io_accel2_cmd *cp) | |
2090 | { | |
2091 | struct ioaccel2_sg_element *chain_sg; | |
2092 | u64 temp64; | |
2093 | u32 chain_size; | |
2094 | ||
2095 | chain_sg = cp->sg; | |
2096 | temp64 = le64_to_cpu(chain_sg->address); | |
a736e9b6 | 2097 | chain_size = le32_to_cpu(cp->sg[0].length); |
d9a729f3 WS |
2098 | pci_unmap_single(h->pdev, temp64, chain_size, PCI_DMA_TODEVICE); |
2099 | } | |
2100 | ||
e2bea6df | 2101 | static int hpsa_map_sg_chain_block(struct ctlr_info *h, |
33a2ffce SC |
2102 | struct CommandList *c) |
2103 | { | |
2104 | struct SGDescriptor *chain_sg, *chain_block; | |
2105 | u64 temp64; | |
50a0decf | 2106 | u32 chain_len; |
33a2ffce SC |
2107 | |
2108 | chain_sg = &c->SG[h->max_cmd_sg_entries - 1]; | |
2109 | chain_block = h->cmd_sg_list[c->cmdindex]; | |
50a0decf SC |
2110 | chain_sg->Ext = cpu_to_le32(HPSA_SG_CHAIN); |
2111 | chain_len = sizeof(*chain_sg) * | |
2b08b3e9 | 2112 | (le16_to_cpu(c->Header.SGTotal) - h->max_cmd_sg_entries); |
50a0decf SC |
2113 | chain_sg->Len = cpu_to_le32(chain_len); |
2114 | temp64 = pci_map_single(h->pdev, chain_block, chain_len, | |
33a2ffce | 2115 | PCI_DMA_TODEVICE); |
e2bea6df SC |
2116 | if (dma_mapping_error(&h->pdev->dev, temp64)) { |
2117 | /* prevent subsequent unmapping */ | |
50a0decf | 2118 | chain_sg->Addr = cpu_to_le64(0); |
e2bea6df SC |
2119 | return -1; |
2120 | } | |
50a0decf | 2121 | chain_sg->Addr = cpu_to_le64(temp64); |
e2bea6df | 2122 | return 0; |
33a2ffce SC |
2123 | } |
2124 | ||
2125 | static void hpsa_unmap_sg_chain_block(struct ctlr_info *h, | |
2126 | struct CommandList *c) | |
2127 | { | |
2128 | struct SGDescriptor *chain_sg; | |
33a2ffce | 2129 | |
50a0decf | 2130 | if (le16_to_cpu(c->Header.SGTotal) <= h->max_cmd_sg_entries) |
33a2ffce SC |
2131 | return; |
2132 | ||
2133 | chain_sg = &c->SG[h->max_cmd_sg_entries - 1]; | |
50a0decf SC |
2134 | pci_unmap_single(h->pdev, le64_to_cpu(chain_sg->Addr), |
2135 | le32_to_cpu(chain_sg->Len), PCI_DMA_TODEVICE); | |
33a2ffce SC |
2136 | } |
2137 | ||
a09c1441 ST |
2138 | |
2139 | /* Decode the various types of errors on ioaccel2 path. | |
2140 | * Return 1 for any error that should generate a RAID path retry. | |
2141 | * Return 0 for errors that don't require a RAID path retry. | |
2142 | */ | |
2143 | static int handle_ioaccel_mode2_error(struct ctlr_info *h, | |
c349775e ST |
2144 | struct CommandList *c, |
2145 | struct scsi_cmnd *cmd, | |
2146 | struct io_accel2_cmd *c2) | |
2147 | { | |
2148 | int data_len; | |
a09c1441 | 2149 | int retry = 0; |
c40820d5 | 2150 | u32 ioaccel2_resid = 0; |
c349775e ST |
2151 | |
2152 | switch (c2->error_data.serv_response) { | |
2153 | case IOACCEL2_SERV_RESPONSE_COMPLETE: | |
2154 | switch (c2->error_data.status) { | |
2155 | case IOACCEL2_STATUS_SR_TASK_COMP_GOOD: | |
2156 | break; | |
2157 | case IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND: | |
ee6b1889 | 2158 | cmd->result |= SAM_STAT_CHECK_CONDITION; |
c349775e | 2159 | if (c2->error_data.data_present != |
ee6b1889 SC |
2160 | IOACCEL2_SENSE_DATA_PRESENT) { |
2161 | memset(cmd->sense_buffer, 0, | |
2162 | SCSI_SENSE_BUFFERSIZE); | |
c349775e | 2163 | break; |
ee6b1889 | 2164 | } |
c349775e ST |
2165 | /* copy the sense data */ |
2166 | data_len = c2->error_data.sense_data_len; | |
2167 | if (data_len > SCSI_SENSE_BUFFERSIZE) | |
2168 | data_len = SCSI_SENSE_BUFFERSIZE; | |
2169 | if (data_len > sizeof(c2->error_data.sense_data_buff)) | |
2170 | data_len = | |
2171 | sizeof(c2->error_data.sense_data_buff); | |
2172 | memcpy(cmd->sense_buffer, | |
2173 | c2->error_data.sense_data_buff, data_len); | |
a09c1441 | 2174 | retry = 1; |
c349775e ST |
2175 | break; |
2176 | case IOACCEL2_STATUS_SR_TASK_COMP_BUSY: | |
a09c1441 | 2177 | retry = 1; |
c349775e ST |
2178 | break; |
2179 | case IOACCEL2_STATUS_SR_TASK_COMP_RES_CON: | |
a09c1441 | 2180 | retry = 1; |
c349775e ST |
2181 | break; |
2182 | case IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL: | |
4a8da22b | 2183 | retry = 1; |
c349775e ST |
2184 | break; |
2185 | case IOACCEL2_STATUS_SR_TASK_COMP_ABORTED: | |
a09c1441 | 2186 | retry = 1; |
c349775e ST |
2187 | break; |
2188 | default: | |
a09c1441 | 2189 | retry = 1; |
c349775e ST |
2190 | break; |
2191 | } | |
2192 | break; | |
2193 | case IOACCEL2_SERV_RESPONSE_FAILURE: | |
c40820d5 JH |
2194 | switch (c2->error_data.status) { |
2195 | case IOACCEL2_STATUS_SR_IO_ERROR: | |
2196 | case IOACCEL2_STATUS_SR_IO_ABORTED: | |
2197 | case IOACCEL2_STATUS_SR_OVERRUN: | |
2198 | retry = 1; | |
2199 | break; | |
2200 | case IOACCEL2_STATUS_SR_UNDERRUN: | |
2201 | cmd->result = (DID_OK << 16); /* host byte */ | |
2202 | cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */ | |
2203 | ioaccel2_resid = get_unaligned_le32( | |
2204 | &c2->error_data.resid_cnt[0]); | |
2205 | scsi_set_resid(cmd, ioaccel2_resid); | |
2206 | break; | |
2207 | case IOACCEL2_STATUS_SR_NO_PATH_TO_DEVICE: | |
2208 | case IOACCEL2_STATUS_SR_INVALID_DEVICE: | |
2209 | case IOACCEL2_STATUS_SR_IOACCEL_DISABLED: | |
2210 | /* We will get an event from ctlr to trigger rescan */ | |
2211 | retry = 1; | |
2212 | break; | |
2213 | default: | |
2214 | retry = 1; | |
c40820d5 | 2215 | } |
c349775e ST |
2216 | break; |
2217 | case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE: | |
2218 | break; | |
2219 | case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS: | |
2220 | break; | |
2221 | case IOACCEL2_SERV_RESPONSE_TMF_REJECTED: | |
a09c1441 | 2222 | retry = 1; |
c349775e ST |
2223 | break; |
2224 | case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN: | |
c349775e ST |
2225 | break; |
2226 | default: | |
a09c1441 | 2227 | retry = 1; |
c349775e ST |
2228 | break; |
2229 | } | |
a09c1441 ST |
2230 | |
2231 | return retry; /* retry on raid path? */ | |
c349775e ST |
2232 | } |
2233 | ||
a58e7e53 WS |
2234 | static void hpsa_cmd_resolve_events(struct ctlr_info *h, |
2235 | struct CommandList *c) | |
2236 | { | |
d604f533 WS |
2237 | bool do_wake = false; |
2238 | ||
a58e7e53 WS |
2239 | /* |
2240 | * Prevent the following race in the abort handler: | |
2241 | * | |
2242 | * 1. LLD is requested to abort a SCSI command | |
2243 | * 2. The SCSI command completes | |
2244 | * 3. The struct CommandList associated with step 2 is made available | |
2245 | * 4. New I/O request to LLD to another LUN re-uses struct CommandList | |
2246 | * 5. Abort handler follows scsi_cmnd->host_scribble and | |
2247 | * finds struct CommandList and tries to aborts it | |
2248 | * Now we have aborted the wrong command. | |
2249 | * | |
d604f533 WS |
2250 | * Reset c->scsi_cmd here so that the abort or reset handler will know |
2251 | * this command has completed. Then, check to see if the handler is | |
a58e7e53 WS |
2252 | * waiting for this command, and, if so, wake it. |
2253 | */ | |
2254 | c->scsi_cmd = SCSI_CMD_IDLE; | |
d604f533 | 2255 | mb(); /* Declare command idle before checking for pending events. */ |
a58e7e53 | 2256 | if (c->abort_pending) { |
d604f533 | 2257 | do_wake = true; |
a58e7e53 | 2258 | c->abort_pending = false; |
a58e7e53 | 2259 | } |
d604f533 WS |
2260 | if (c->reset_pending) { |
2261 | unsigned long flags; | |
2262 | struct hpsa_scsi_dev_t *dev; | |
2263 | ||
2264 | /* | |
2265 | * There appears to be a reset pending; lock the lock and | |
2266 | * reconfirm. If so, then decrement the count of outstanding | |
2267 | * commands and wake the reset command if this is the last one. | |
2268 | */ | |
2269 | spin_lock_irqsave(&h->lock, flags); | |
2270 | dev = c->reset_pending; /* Re-fetch under the lock. */ | |
2271 | if (dev && atomic_dec_and_test(&dev->reset_cmds_out)) | |
2272 | do_wake = true; | |
2273 | c->reset_pending = NULL; | |
2274 | spin_unlock_irqrestore(&h->lock, flags); | |
2275 | } | |
2276 | ||
2277 | if (do_wake) | |
2278 | wake_up_all(&h->event_sync_wait_queue); | |
a58e7e53 WS |
2279 | } |
2280 | ||
73153fe5 WS |
2281 | static void hpsa_cmd_resolve_and_free(struct ctlr_info *h, |
2282 | struct CommandList *c) | |
2283 | { | |
2284 | hpsa_cmd_resolve_events(h, c); | |
2285 | cmd_tagged_free(h, c); | |
2286 | } | |
2287 | ||
8a0ff92c WS |
2288 | static void hpsa_cmd_free_and_done(struct ctlr_info *h, |
2289 | struct CommandList *c, struct scsi_cmnd *cmd) | |
2290 | { | |
73153fe5 | 2291 | hpsa_cmd_resolve_and_free(h, c); |
8a0ff92c WS |
2292 | cmd->scsi_done(cmd); |
2293 | } | |
2294 | ||
2295 | static void hpsa_retry_cmd(struct ctlr_info *h, struct CommandList *c) | |
2296 | { | |
2297 | INIT_WORK(&c->work, hpsa_command_resubmit_worker); | |
2298 | queue_work_on(raw_smp_processor_id(), h->resubmit_wq, &c->work); | |
2299 | } | |
2300 | ||
a58e7e53 WS |
2301 | static void hpsa_set_scsi_cmd_aborted(struct scsi_cmnd *cmd) |
2302 | { | |
2303 | cmd->result = DID_ABORT << 16; | |
2304 | } | |
2305 | ||
2306 | static void hpsa_cmd_abort_and_free(struct ctlr_info *h, struct CommandList *c, | |
2307 | struct scsi_cmnd *cmd) | |
2308 | { | |
2309 | hpsa_set_scsi_cmd_aborted(cmd); | |
2310 | dev_warn(&h->pdev->dev, "CDB %16phN was aborted with status 0x%x\n", | |
2311 | c->Request.CDB, c->err_info->ScsiStatus); | |
73153fe5 | 2312 | hpsa_cmd_resolve_and_free(h, c); |
a58e7e53 WS |
2313 | } |
2314 | ||
c349775e ST |
2315 | static void process_ioaccel2_completion(struct ctlr_info *h, |
2316 | struct CommandList *c, struct scsi_cmnd *cmd, | |
2317 | struct hpsa_scsi_dev_t *dev) | |
2318 | { | |
2319 | struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex]; | |
2320 | ||
2321 | /* check for good status */ | |
2322 | if (likely(c2->error_data.serv_response == 0 && | |
8a0ff92c WS |
2323 | c2->error_data.status == 0)) |
2324 | return hpsa_cmd_free_and_done(h, c, cmd); | |
c349775e | 2325 | |
8a0ff92c WS |
2326 | /* |
2327 | * Any RAID offload error results in retry which will use | |
c349775e ST |
2328 | * the normal I/O path so the controller can handle whatever's |
2329 | * wrong. | |
2330 | */ | |
f3f01730 | 2331 | if (is_logical_device(dev) && |
c349775e ST |
2332 | c2->error_data.serv_response == |
2333 | IOACCEL2_SERV_RESPONSE_FAILURE) { | |
080ef1cc DB |
2334 | if (c2->error_data.status == |
2335 | IOACCEL2_STATUS_SR_IOACCEL_DISABLED) | |
2336 | dev->offload_enabled = 0; | |
8a0ff92c WS |
2337 | |
2338 | return hpsa_retry_cmd(h, c); | |
a09c1441 | 2339 | } |
080ef1cc DB |
2340 | |
2341 | if (handle_ioaccel_mode2_error(h, c, cmd, c2)) | |
8a0ff92c | 2342 | return hpsa_retry_cmd(h, c); |
080ef1cc | 2343 | |
8a0ff92c | 2344 | return hpsa_cmd_free_and_done(h, c, cmd); |
c349775e ST |
2345 | } |
2346 | ||
9437ac43 SC |
2347 | /* Returns 0 on success, < 0 otherwise. */ |
2348 | static int hpsa_evaluate_tmf_status(struct ctlr_info *h, | |
2349 | struct CommandList *cp) | |
2350 | { | |
2351 | u8 tmf_status = cp->err_info->ScsiStatus; | |
2352 | ||
2353 | switch (tmf_status) { | |
2354 | case CISS_TMF_COMPLETE: | |
2355 | /* | |
2356 | * CISS_TMF_COMPLETE never happens, instead, | |
2357 | * ei->CommandStatus == 0 for this case. | |
2358 | */ | |
2359 | case CISS_TMF_SUCCESS: | |
2360 | return 0; | |
2361 | case CISS_TMF_INVALID_FRAME: | |
2362 | case CISS_TMF_NOT_SUPPORTED: | |
2363 | case CISS_TMF_FAILED: | |
2364 | case CISS_TMF_WRONG_LUN: | |
2365 | case CISS_TMF_OVERLAPPED_TAG: | |
2366 | break; | |
2367 | default: | |
2368 | dev_warn(&h->pdev->dev, "Unknown TMF status: 0x%02x\n", | |
2369 | tmf_status); | |
2370 | break; | |
2371 | } | |
2372 | return -tmf_status; | |
2373 | } | |
2374 | ||
1fb011fb | 2375 | static void complete_scsi_command(struct CommandList *cp) |
edd16368 SC |
2376 | { |
2377 | struct scsi_cmnd *cmd; | |
2378 | struct ctlr_info *h; | |
2379 | struct ErrorInfo *ei; | |
283b4a9b | 2380 | struct hpsa_scsi_dev_t *dev; |
d9a729f3 | 2381 | struct io_accel2_cmd *c2; |
edd16368 | 2382 | |
9437ac43 SC |
2383 | u8 sense_key; |
2384 | u8 asc; /* additional sense code */ | |
2385 | u8 ascq; /* additional sense code qualifier */ | |
db111e18 | 2386 | unsigned long sense_data_size; |
edd16368 SC |
2387 | |
2388 | ei = cp->err_info; | |
7fa3030c | 2389 | cmd = cp->scsi_cmd; |
edd16368 | 2390 | h = cp->h; |
283b4a9b | 2391 | dev = cmd->device->hostdata; |
d9a729f3 | 2392 | c2 = &h->ioaccel2_cmd_pool[cp->cmdindex]; |
edd16368 SC |
2393 | |
2394 | scsi_dma_unmap(cmd); /* undo the DMA mappings */ | |
e1f7de0c | 2395 | if ((cp->cmd_type == CMD_SCSI) && |
2b08b3e9 | 2396 | (le16_to_cpu(cp->Header.SGTotal) > h->max_cmd_sg_entries)) |
33a2ffce | 2397 | hpsa_unmap_sg_chain_block(h, cp); |
edd16368 | 2398 | |
d9a729f3 WS |
2399 | if ((cp->cmd_type == CMD_IOACCEL2) && |
2400 | (c2->sg[0].chain_indicator == IOACCEL2_CHAIN)) | |
2401 | hpsa_unmap_ioaccel2_sg_chain_block(h, c2); | |
2402 | ||
edd16368 SC |
2403 | cmd->result = (DID_OK << 16); /* host byte */ |
2404 | cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */ | |
c349775e | 2405 | |
03383736 DB |
2406 | if (cp->cmd_type == CMD_IOACCEL2 || cp->cmd_type == CMD_IOACCEL1) |
2407 | atomic_dec(&cp->phys_disk->ioaccel_cmds_out); | |
2408 | ||
25163bd5 WS |
2409 | /* |
2410 | * We check for lockup status here as it may be set for | |
2411 | * CMD_SCSI, CMD_IOACCEL1 and CMD_IOACCEL2 commands by | |
2412 | * fail_all_oustanding_cmds() | |
2413 | */ | |
2414 | if (unlikely(ei->CommandStatus == CMD_CTLR_LOCKUP)) { | |
2415 | /* DID_NO_CONNECT will prevent a retry */ | |
2416 | cmd->result = DID_NO_CONNECT << 16; | |
8a0ff92c | 2417 | return hpsa_cmd_free_and_done(h, cp, cmd); |
25163bd5 WS |
2418 | } |
2419 | ||
d604f533 WS |
2420 | if ((unlikely(hpsa_is_pending_event(cp)))) { |
2421 | if (cp->reset_pending) | |
2422 | return hpsa_cmd_resolve_and_free(h, cp); | |
2423 | if (cp->abort_pending) | |
2424 | return hpsa_cmd_abort_and_free(h, cp, cmd); | |
2425 | } | |
2426 | ||
c349775e ST |
2427 | if (cp->cmd_type == CMD_IOACCEL2) |
2428 | return process_ioaccel2_completion(h, cp, cmd, dev); | |
2429 | ||
6aa4c361 | 2430 | scsi_set_resid(cmd, ei->ResidualCnt); |
8a0ff92c WS |
2431 | if (ei->CommandStatus == 0) |
2432 | return hpsa_cmd_free_and_done(h, cp, cmd); | |
6aa4c361 | 2433 | |
e1f7de0c MG |
2434 | /* For I/O accelerator commands, copy over some fields to the normal |
2435 | * CISS header used below for error handling. | |
2436 | */ | |
2437 | if (cp->cmd_type == CMD_IOACCEL1) { | |
2438 | struct io_accel1_cmd *c = &h->ioaccel_cmd_pool[cp->cmdindex]; | |
2b08b3e9 DB |
2439 | cp->Header.SGList = scsi_sg_count(cmd); |
2440 | cp->Header.SGTotal = cpu_to_le16(cp->Header.SGList); | |
2441 | cp->Request.CDBLen = le16_to_cpu(c->io_flags) & | |
2442 | IOACCEL1_IOFLAGS_CDBLEN_MASK; | |
50a0decf | 2443 | cp->Header.tag = c->tag; |
e1f7de0c MG |
2444 | memcpy(cp->Header.LUN.LunAddrBytes, c->CISS_LUN, 8); |
2445 | memcpy(cp->Request.CDB, c->CDB, cp->Request.CDBLen); | |
283b4a9b SC |
2446 | |
2447 | /* Any RAID offload error results in retry which will use | |
2448 | * the normal I/O path so the controller can handle whatever's | |
2449 | * wrong. | |
2450 | */ | |
f3f01730 | 2451 | if (is_logical_device(dev)) { |
283b4a9b SC |
2452 | if (ei->CommandStatus == CMD_IOACCEL_DISABLED) |
2453 | dev->offload_enabled = 0; | |
d604f533 | 2454 | return hpsa_retry_cmd(h, cp); |
283b4a9b | 2455 | } |
e1f7de0c MG |
2456 | } |
2457 | ||
edd16368 SC |
2458 | /* an error has occurred */ |
2459 | switch (ei->CommandStatus) { | |
2460 | ||
2461 | case CMD_TARGET_STATUS: | |
9437ac43 SC |
2462 | cmd->result |= ei->ScsiStatus; |
2463 | /* copy the sense data */ | |
2464 | if (SCSI_SENSE_BUFFERSIZE < sizeof(ei->SenseInfo)) | |
2465 | sense_data_size = SCSI_SENSE_BUFFERSIZE; | |
2466 | else | |
2467 | sense_data_size = sizeof(ei->SenseInfo); | |
2468 | if (ei->SenseLen < sense_data_size) | |
2469 | sense_data_size = ei->SenseLen; | |
2470 | memcpy(cmd->sense_buffer, ei->SenseInfo, sense_data_size); | |
2471 | if (ei->ScsiStatus) | |
2472 | decode_sense_data(ei->SenseInfo, sense_data_size, | |
2473 | &sense_key, &asc, &ascq); | |
edd16368 | 2474 | if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION) { |
1d3b3609 | 2475 | if (sense_key == ABORTED_COMMAND) { |
2e311fba | 2476 | cmd->result |= DID_SOFT_ERROR << 16; |
1d3b3609 MG |
2477 | break; |
2478 | } | |
edd16368 SC |
2479 | break; |
2480 | } | |
edd16368 SC |
2481 | /* Problem was not a check condition |
2482 | * Pass it up to the upper layers... | |
2483 | */ | |
2484 | if (ei->ScsiStatus) { | |
2485 | dev_warn(&h->pdev->dev, "cp %p has status 0x%x " | |
2486 | "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, " | |
2487 | "Returning result: 0x%x\n", | |
2488 | cp, ei->ScsiStatus, | |
2489 | sense_key, asc, ascq, | |
2490 | cmd->result); | |
2491 | } else { /* scsi status is zero??? How??? */ | |
2492 | dev_warn(&h->pdev->dev, "cp %p SCSI status was 0. " | |
2493 | "Returning no connection.\n", cp), | |
2494 | ||
2495 | /* Ordinarily, this case should never happen, | |
2496 | * but there is a bug in some released firmware | |
2497 | * revisions that allows it to happen if, for | |
2498 | * example, a 4100 backplane loses power and | |
2499 | * the tape drive is in it. We assume that | |
2500 | * it's a fatal error of some kind because we | |
2501 | * can't show that it wasn't. We will make it | |
2502 | * look like selection timeout since that is | |
2503 | * the most common reason for this to occur, | |
2504 | * and it's severe enough. | |
2505 | */ | |
2506 | ||
2507 | cmd->result = DID_NO_CONNECT << 16; | |
2508 | } | |
2509 | break; | |
2510 | ||
2511 | case CMD_DATA_UNDERRUN: /* let mid layer handle it. */ | |
2512 | break; | |
2513 | case CMD_DATA_OVERRUN: | |
f42e81e1 SC |
2514 | dev_warn(&h->pdev->dev, |
2515 | "CDB %16phN data overrun\n", cp->Request.CDB); | |
edd16368 SC |
2516 | break; |
2517 | case CMD_INVALID: { | |
2518 | /* print_bytes(cp, sizeof(*cp), 1, 0); | |
2519 | print_cmd(cp); */ | |
2520 | /* We get CMD_INVALID if you address a non-existent device | |
2521 | * instead of a selection timeout (no response). You will | |
2522 | * see this if you yank out a drive, then try to access it. | |
2523 | * This is kind of a shame because it means that any other | |
2524 | * CMD_INVALID (e.g. driver bug) will get interpreted as a | |
2525 | * missing target. */ | |
2526 | cmd->result = DID_NO_CONNECT << 16; | |
2527 | } | |
2528 | break; | |
2529 | case CMD_PROTOCOL_ERR: | |
256d0eaa | 2530 | cmd->result = DID_ERROR << 16; |
f42e81e1 SC |
2531 | dev_warn(&h->pdev->dev, "CDB %16phN : protocol error\n", |
2532 | cp->Request.CDB); | |
edd16368 SC |
2533 | break; |
2534 | case CMD_HARDWARE_ERR: | |
2535 | cmd->result = DID_ERROR << 16; | |
f42e81e1 SC |
2536 | dev_warn(&h->pdev->dev, "CDB %16phN : hardware error\n", |
2537 | cp->Request.CDB); | |
edd16368 SC |
2538 | break; |
2539 | case CMD_CONNECTION_LOST: | |
2540 | cmd->result = DID_ERROR << 16; | |
f42e81e1 SC |
2541 | dev_warn(&h->pdev->dev, "CDB %16phN : connection lost\n", |
2542 | cp->Request.CDB); | |
edd16368 SC |
2543 | break; |
2544 | case CMD_ABORTED: | |
a58e7e53 WS |
2545 | /* Return now to avoid calling scsi_done(). */ |
2546 | return hpsa_cmd_abort_and_free(h, cp, cmd); | |
edd16368 SC |
2547 | case CMD_ABORT_FAILED: |
2548 | cmd->result = DID_ERROR << 16; | |
f42e81e1 SC |
2549 | dev_warn(&h->pdev->dev, "CDB %16phN : abort failed\n", |
2550 | cp->Request.CDB); | |
edd16368 SC |
2551 | break; |
2552 | case CMD_UNSOLICITED_ABORT: | |
f6e76055 | 2553 | cmd->result = DID_SOFT_ERROR << 16; /* retry the command */ |
f42e81e1 SC |
2554 | dev_warn(&h->pdev->dev, "CDB %16phN : unsolicited abort\n", |
2555 | cp->Request.CDB); | |
edd16368 SC |
2556 | break; |
2557 | case CMD_TIMEOUT: | |
2558 | cmd->result = DID_TIME_OUT << 16; | |
f42e81e1 SC |
2559 | dev_warn(&h->pdev->dev, "CDB %16phN timed out\n", |
2560 | cp->Request.CDB); | |
edd16368 | 2561 | break; |
1d5e2ed0 SC |
2562 | case CMD_UNABORTABLE: |
2563 | cmd->result = DID_ERROR << 16; | |
2564 | dev_warn(&h->pdev->dev, "Command unabortable\n"); | |
2565 | break; | |
9437ac43 SC |
2566 | case CMD_TMF_STATUS: |
2567 | if (hpsa_evaluate_tmf_status(h, cp)) /* TMF failed? */ | |
2568 | cmd->result = DID_ERROR << 16; | |
2569 | break; | |
283b4a9b SC |
2570 | case CMD_IOACCEL_DISABLED: |
2571 | /* This only handles the direct pass-through case since RAID | |
2572 | * offload is handled above. Just attempt a retry. | |
2573 | */ | |
2574 | cmd->result = DID_SOFT_ERROR << 16; | |
2575 | dev_warn(&h->pdev->dev, | |
2576 | "cp %p had HP SSD Smart Path error\n", cp); | |
2577 | break; | |
edd16368 SC |
2578 | default: |
2579 | cmd->result = DID_ERROR << 16; | |
2580 | dev_warn(&h->pdev->dev, "cp %p returned unknown status %x\n", | |
2581 | cp, ei->CommandStatus); | |
2582 | } | |
8a0ff92c WS |
2583 | |
2584 | return hpsa_cmd_free_and_done(h, cp, cmd); | |
edd16368 SC |
2585 | } |
2586 | ||
edd16368 SC |
2587 | static void hpsa_pci_unmap(struct pci_dev *pdev, |
2588 | struct CommandList *c, int sg_used, int data_direction) | |
2589 | { | |
2590 | int i; | |
edd16368 | 2591 | |
50a0decf SC |
2592 | for (i = 0; i < sg_used; i++) |
2593 | pci_unmap_single(pdev, (dma_addr_t) le64_to_cpu(c->SG[i].Addr), | |
2594 | le32_to_cpu(c->SG[i].Len), | |
2595 | data_direction); | |
edd16368 SC |
2596 | } |
2597 | ||
a2dac136 | 2598 | static int hpsa_map_one(struct pci_dev *pdev, |
edd16368 SC |
2599 | struct CommandList *cp, |
2600 | unsigned char *buf, | |
2601 | size_t buflen, | |
2602 | int data_direction) | |
2603 | { | |
01a02ffc | 2604 | u64 addr64; |
edd16368 SC |
2605 | |
2606 | if (buflen == 0 || data_direction == PCI_DMA_NONE) { | |
2607 | cp->Header.SGList = 0; | |
50a0decf | 2608 | cp->Header.SGTotal = cpu_to_le16(0); |
a2dac136 | 2609 | return 0; |
edd16368 SC |
2610 | } |
2611 | ||
50a0decf | 2612 | addr64 = pci_map_single(pdev, buf, buflen, data_direction); |
eceaae18 | 2613 | if (dma_mapping_error(&pdev->dev, addr64)) { |
a2dac136 | 2614 | /* Prevent subsequent unmap of something never mapped */ |
eceaae18 | 2615 | cp->Header.SGList = 0; |
50a0decf | 2616 | cp->Header.SGTotal = cpu_to_le16(0); |
a2dac136 | 2617 | return -1; |
eceaae18 | 2618 | } |
50a0decf SC |
2619 | cp->SG[0].Addr = cpu_to_le64(addr64); |
2620 | cp->SG[0].Len = cpu_to_le32(buflen); | |
2621 | cp->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* we are not chaining */ | |
2622 | cp->Header.SGList = 1; /* no. SGs contig in this cmd */ | |
2623 | cp->Header.SGTotal = cpu_to_le16(1); /* total sgs in cmd list */ | |
a2dac136 | 2624 | return 0; |
edd16368 SC |
2625 | } |
2626 | ||
25163bd5 WS |
2627 | #define NO_TIMEOUT ((unsigned long) -1) |
2628 | #define DEFAULT_TIMEOUT 30000 /* milliseconds */ | |
2629 | static int hpsa_scsi_do_simple_cmd_core(struct ctlr_info *h, | |
2630 | struct CommandList *c, int reply_queue, unsigned long timeout_msecs) | |
edd16368 SC |
2631 | { |
2632 | DECLARE_COMPLETION_ONSTACK(wait); | |
2633 | ||
2634 | c->waiting = &wait; | |
25163bd5 WS |
2635 | __enqueue_cmd_and_start_io(h, c, reply_queue); |
2636 | if (timeout_msecs == NO_TIMEOUT) { | |
2637 | /* TODO: get rid of this no-timeout thing */ | |
2638 | wait_for_completion_io(&wait); | |
2639 | return IO_OK; | |
2640 | } | |
2641 | if (!wait_for_completion_io_timeout(&wait, | |
2642 | msecs_to_jiffies(timeout_msecs))) { | |
2643 | dev_warn(&h->pdev->dev, "Command timed out.\n"); | |
2644 | return -ETIMEDOUT; | |
2645 | } | |
2646 | return IO_OK; | |
2647 | } | |
2648 | ||
2649 | static int hpsa_scsi_do_simple_cmd(struct ctlr_info *h, struct CommandList *c, | |
2650 | int reply_queue, unsigned long timeout_msecs) | |
2651 | { | |
2652 | if (unlikely(lockup_detected(h))) { | |
2653 | c->err_info->CommandStatus = CMD_CTLR_LOCKUP; | |
2654 | return IO_OK; | |
2655 | } | |
2656 | return hpsa_scsi_do_simple_cmd_core(h, c, reply_queue, timeout_msecs); | |
edd16368 SC |
2657 | } |
2658 | ||
094963da SC |
2659 | static u32 lockup_detected(struct ctlr_info *h) |
2660 | { | |
2661 | int cpu; | |
2662 | u32 rc, *lockup_detected; | |
2663 | ||
2664 | cpu = get_cpu(); | |
2665 | lockup_detected = per_cpu_ptr(h->lockup_detected, cpu); | |
2666 | rc = *lockup_detected; | |
2667 | put_cpu(); | |
2668 | return rc; | |
2669 | } | |
2670 | ||
9c2fc160 | 2671 | #define MAX_DRIVER_CMD_RETRIES 25 |
25163bd5 WS |
2672 | static int hpsa_scsi_do_simple_cmd_with_retry(struct ctlr_info *h, |
2673 | struct CommandList *c, int data_direction, unsigned long timeout_msecs) | |
edd16368 | 2674 | { |
9c2fc160 | 2675 | int backoff_time = 10, retry_count = 0; |
25163bd5 | 2676 | int rc; |
edd16368 SC |
2677 | |
2678 | do { | |
7630abd0 | 2679 | memset(c->err_info, 0, sizeof(*c->err_info)); |
25163bd5 WS |
2680 | rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, |
2681 | timeout_msecs); | |
2682 | if (rc) | |
2683 | break; | |
edd16368 | 2684 | retry_count++; |
9c2fc160 SC |
2685 | if (retry_count > 3) { |
2686 | msleep(backoff_time); | |
2687 | if (backoff_time < 1000) | |
2688 | backoff_time *= 2; | |
2689 | } | |
852af20a | 2690 | } while ((check_for_unit_attention(h, c) || |
9c2fc160 SC |
2691 | check_for_busy(h, c)) && |
2692 | retry_count <= MAX_DRIVER_CMD_RETRIES); | |
edd16368 | 2693 | hpsa_pci_unmap(h->pdev, c, 1, data_direction); |
25163bd5 WS |
2694 | if (retry_count > MAX_DRIVER_CMD_RETRIES) |
2695 | rc = -EIO; | |
2696 | return rc; | |
edd16368 SC |
2697 | } |
2698 | ||
d1e8beac SC |
2699 | static void hpsa_print_cmd(struct ctlr_info *h, char *txt, |
2700 | struct CommandList *c) | |
edd16368 | 2701 | { |
d1e8beac SC |
2702 | const u8 *cdb = c->Request.CDB; |
2703 | const u8 *lun = c->Header.LUN.LunAddrBytes; | |
2704 | ||
2705 | dev_warn(&h->pdev->dev, "%s: LUN:%02x%02x%02x%02x%02x%02x%02x%02x" | |
2706 | " CDB:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\n", | |
2707 | txt, lun[0], lun[1], lun[2], lun[3], | |
2708 | lun[4], lun[5], lun[6], lun[7], | |
2709 | cdb[0], cdb[1], cdb[2], cdb[3], | |
2710 | cdb[4], cdb[5], cdb[6], cdb[7], | |
2711 | cdb[8], cdb[9], cdb[10], cdb[11], | |
2712 | cdb[12], cdb[13], cdb[14], cdb[15]); | |
2713 | } | |
2714 | ||
2715 | static void hpsa_scsi_interpret_error(struct ctlr_info *h, | |
2716 | struct CommandList *cp) | |
2717 | { | |
2718 | const struct ErrorInfo *ei = cp->err_info; | |
edd16368 | 2719 | struct device *d = &cp->h->pdev->dev; |
9437ac43 SC |
2720 | u8 sense_key, asc, ascq; |
2721 | int sense_len; | |
edd16368 | 2722 | |
edd16368 SC |
2723 | switch (ei->CommandStatus) { |
2724 | case CMD_TARGET_STATUS: | |
9437ac43 SC |
2725 | if (ei->SenseLen > sizeof(ei->SenseInfo)) |
2726 | sense_len = sizeof(ei->SenseInfo); | |
2727 | else | |
2728 | sense_len = ei->SenseLen; | |
2729 | decode_sense_data(ei->SenseInfo, sense_len, | |
2730 | &sense_key, &asc, &ascq); | |
d1e8beac SC |
2731 | hpsa_print_cmd(h, "SCSI status", cp); |
2732 | if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION) | |
9437ac43 SC |
2733 | dev_warn(d, "SCSI Status = 02, Sense key = 0x%02x, ASC = 0x%02x, ASCQ = 0x%02x\n", |
2734 | sense_key, asc, ascq); | |
d1e8beac | 2735 | else |
9437ac43 | 2736 | dev_warn(d, "SCSI Status = 0x%02x\n", ei->ScsiStatus); |
edd16368 SC |
2737 | if (ei->ScsiStatus == 0) |
2738 | dev_warn(d, "SCSI status is abnormally zero. " | |
2739 | "(probably indicates selection timeout " | |
2740 | "reported incorrectly due to a known " | |
2741 | "firmware bug, circa July, 2001.)\n"); | |
2742 | break; | |
2743 | case CMD_DATA_UNDERRUN: /* let mid layer handle it. */ | |
edd16368 SC |
2744 | break; |
2745 | case CMD_DATA_OVERRUN: | |
d1e8beac | 2746 | hpsa_print_cmd(h, "overrun condition", cp); |
edd16368 SC |
2747 | break; |
2748 | case CMD_INVALID: { | |
2749 | /* controller unfortunately reports SCSI passthru's | |
2750 | * to non-existent targets as invalid commands. | |
2751 | */ | |
d1e8beac SC |
2752 | hpsa_print_cmd(h, "invalid command", cp); |
2753 | dev_warn(d, "probably means device no longer present\n"); | |
edd16368 SC |
2754 | } |
2755 | break; | |
2756 | case CMD_PROTOCOL_ERR: | |
d1e8beac | 2757 | hpsa_print_cmd(h, "protocol error", cp); |
edd16368 SC |
2758 | break; |
2759 | case CMD_HARDWARE_ERR: | |
d1e8beac | 2760 | hpsa_print_cmd(h, "hardware error", cp); |
edd16368 SC |
2761 | break; |
2762 | case CMD_CONNECTION_LOST: | |
d1e8beac | 2763 | hpsa_print_cmd(h, "connection lost", cp); |
edd16368 SC |
2764 | break; |
2765 | case CMD_ABORTED: | |
d1e8beac | 2766 | hpsa_print_cmd(h, "aborted", cp); |
edd16368 SC |
2767 | break; |
2768 | case CMD_ABORT_FAILED: | |
d1e8beac | 2769 | hpsa_print_cmd(h, "abort failed", cp); |
edd16368 SC |
2770 | break; |
2771 | case CMD_UNSOLICITED_ABORT: | |
d1e8beac | 2772 | hpsa_print_cmd(h, "unsolicited abort", cp); |
edd16368 SC |
2773 | break; |
2774 | case CMD_TIMEOUT: | |
d1e8beac | 2775 | hpsa_print_cmd(h, "timed out", cp); |
edd16368 | 2776 | break; |
1d5e2ed0 | 2777 | case CMD_UNABORTABLE: |
d1e8beac | 2778 | hpsa_print_cmd(h, "unabortable", cp); |
1d5e2ed0 | 2779 | break; |
25163bd5 WS |
2780 | case CMD_CTLR_LOCKUP: |
2781 | hpsa_print_cmd(h, "controller lockup detected", cp); | |
2782 | break; | |
edd16368 | 2783 | default: |
d1e8beac SC |
2784 | hpsa_print_cmd(h, "unknown status", cp); |
2785 | dev_warn(d, "Unknown command status %x\n", | |
edd16368 SC |
2786 | ei->CommandStatus); |
2787 | } | |
2788 | } | |
2789 | ||
2790 | static int hpsa_scsi_do_inquiry(struct ctlr_info *h, unsigned char *scsi3addr, | |
b7bb24eb | 2791 | u16 page, unsigned char *buf, |
edd16368 SC |
2792 | unsigned char bufsize) |
2793 | { | |
2794 | int rc = IO_OK; | |
2795 | struct CommandList *c; | |
2796 | struct ErrorInfo *ei; | |
2797 | ||
45fcb86e | 2798 | c = cmd_alloc(h); |
edd16368 | 2799 | |
a2dac136 SC |
2800 | if (fill_cmd(c, HPSA_INQUIRY, h, buf, bufsize, |
2801 | page, scsi3addr, TYPE_CMD)) { | |
2802 | rc = -1; | |
2803 | goto out; | |
2804 | } | |
25163bd5 WS |
2805 | rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, |
2806 | PCI_DMA_FROMDEVICE, NO_TIMEOUT); | |
2807 | if (rc) | |
2808 | goto out; | |
edd16368 SC |
2809 | ei = c->err_info; |
2810 | if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) { | |
d1e8beac | 2811 | hpsa_scsi_interpret_error(h, c); |
edd16368 SC |
2812 | rc = -1; |
2813 | } | |
a2dac136 | 2814 | out: |
45fcb86e | 2815 | cmd_free(h, c); |
edd16368 SC |
2816 | return rc; |
2817 | } | |
2818 | ||
bf711ac6 | 2819 | static int hpsa_send_reset(struct ctlr_info *h, unsigned char *scsi3addr, |
25163bd5 | 2820 | u8 reset_type, int reply_queue) |
edd16368 SC |
2821 | { |
2822 | int rc = IO_OK; | |
2823 | struct CommandList *c; | |
2824 | struct ErrorInfo *ei; | |
2825 | ||
45fcb86e | 2826 | c = cmd_alloc(h); |
edd16368 | 2827 | |
edd16368 | 2828 | |
a2dac136 | 2829 | /* fill_cmd can't fail here, no data buffer to map. */ |
0b9b7b6e | 2830 | (void) fill_cmd(c, reset_type, h, NULL, 0, 0, |
bf711ac6 | 2831 | scsi3addr, TYPE_MSG); |
25163bd5 WS |
2832 | rc = hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT); |
2833 | if (rc) { | |
2834 | dev_warn(&h->pdev->dev, "Failed to send reset command\n"); | |
2835 | goto out; | |
2836 | } | |
edd16368 SC |
2837 | /* no unmap needed here because no data xfer. */ |
2838 | ||
2839 | ei = c->err_info; | |
2840 | if (ei->CommandStatus != 0) { | |
d1e8beac | 2841 | hpsa_scsi_interpret_error(h, c); |
edd16368 SC |
2842 | rc = -1; |
2843 | } | |
25163bd5 | 2844 | out: |
45fcb86e | 2845 | cmd_free(h, c); |
edd16368 SC |
2846 | return rc; |
2847 | } | |
2848 | ||
d604f533 WS |
2849 | static bool hpsa_cmd_dev_match(struct ctlr_info *h, struct CommandList *c, |
2850 | struct hpsa_scsi_dev_t *dev, | |
2851 | unsigned char *scsi3addr) | |
2852 | { | |
2853 | int i; | |
2854 | bool match = false; | |
2855 | struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex]; | |
2856 | struct hpsa_tmf_struct *ac = (struct hpsa_tmf_struct *) c2; | |
2857 | ||
2858 | if (hpsa_is_cmd_idle(c)) | |
2859 | return false; | |
2860 | ||
2861 | switch (c->cmd_type) { | |
2862 | case CMD_SCSI: | |
2863 | case CMD_IOCTL_PEND: | |
2864 | match = !memcmp(scsi3addr, &c->Header.LUN.LunAddrBytes, | |
2865 | sizeof(c->Header.LUN.LunAddrBytes)); | |
2866 | break; | |
2867 | ||
2868 | case CMD_IOACCEL1: | |
2869 | case CMD_IOACCEL2: | |
2870 | if (c->phys_disk == dev) { | |
2871 | /* HBA mode match */ | |
2872 | match = true; | |
2873 | } else { | |
2874 | /* Possible RAID mode -- check each phys dev. */ | |
2875 | /* FIXME: Do we need to take out a lock here? If | |
2876 | * so, we could just call hpsa_get_pdisk_of_ioaccel2() | |
2877 | * instead. */ | |
2878 | for (i = 0; i < dev->nphysical_disks && !match; i++) { | |
2879 | /* FIXME: an alternate test might be | |
2880 | * | |
2881 | * match = dev->phys_disk[i]->ioaccel_handle | |
2882 | * == c2->scsi_nexus; */ | |
2883 | match = dev->phys_disk[i] == c->phys_disk; | |
2884 | } | |
2885 | } | |
2886 | break; | |
2887 | ||
2888 | case IOACCEL2_TMF: | |
2889 | for (i = 0; i < dev->nphysical_disks && !match; i++) { | |
2890 | match = dev->phys_disk[i]->ioaccel_handle == | |
2891 | le32_to_cpu(ac->it_nexus); | |
2892 | } | |
2893 | break; | |
2894 | ||
2895 | case 0: /* The command is in the middle of being initialized. */ | |
2896 | match = false; | |
2897 | break; | |
2898 | ||
2899 | default: | |
2900 | dev_err(&h->pdev->dev, "unexpected cmd_type: %d\n", | |
2901 | c->cmd_type); | |
2902 | BUG(); | |
2903 | } | |
2904 | ||
2905 | return match; | |
2906 | } | |
2907 | ||
2908 | static int hpsa_do_reset(struct ctlr_info *h, struct hpsa_scsi_dev_t *dev, | |
2909 | unsigned char *scsi3addr, u8 reset_type, int reply_queue) | |
2910 | { | |
2911 | int i; | |
2912 | int rc = 0; | |
2913 | ||
2914 | /* We can really only handle one reset at a time */ | |
2915 | if (mutex_lock_interruptible(&h->reset_mutex) == -EINTR) { | |
2916 | dev_warn(&h->pdev->dev, "concurrent reset wait interrupted.\n"); | |
2917 | return -EINTR; | |
2918 | } | |
2919 | ||
2920 | BUG_ON(atomic_read(&dev->reset_cmds_out) != 0); | |
2921 | ||
2922 | for (i = 0; i < h->nr_cmds; i++) { | |
2923 | struct CommandList *c = h->cmd_pool + i; | |
2924 | int refcount = atomic_inc_return(&c->refcount); | |
2925 | ||
2926 | if (refcount > 1 && hpsa_cmd_dev_match(h, c, dev, scsi3addr)) { | |
2927 | unsigned long flags; | |
2928 | ||
2929 | /* | |
2930 | * Mark the target command as having a reset pending, | |
2931 | * then lock a lock so that the command cannot complete | |
2932 | * while we're considering it. If the command is not | |
2933 | * idle then count it; otherwise revoke the event. | |
2934 | */ | |
2935 | c->reset_pending = dev; | |
2936 | spin_lock_irqsave(&h->lock, flags); /* Implied MB */ | |
2937 | if (!hpsa_is_cmd_idle(c)) | |
2938 | atomic_inc(&dev->reset_cmds_out); | |
2939 | else | |
2940 | c->reset_pending = NULL; | |
2941 | spin_unlock_irqrestore(&h->lock, flags); | |
2942 | } | |
2943 | ||
2944 | cmd_free(h, c); | |
2945 | } | |
2946 | ||
2947 | rc = hpsa_send_reset(h, scsi3addr, reset_type, reply_queue); | |
2948 | if (!rc) | |
2949 | wait_event(h->event_sync_wait_queue, | |
2950 | atomic_read(&dev->reset_cmds_out) == 0 || | |
2951 | lockup_detected(h)); | |
2952 | ||
2953 | if (unlikely(lockup_detected(h))) { | |
77678d3a DB |
2954 | dev_warn(&h->pdev->dev, |
2955 | "Controller lockup detected during reset wait\n"); | |
2956 | rc = -ENODEV; | |
2957 | } | |
d604f533 WS |
2958 | |
2959 | if (unlikely(rc)) | |
2960 | atomic_set(&dev->reset_cmds_out, 0); | |
2961 | ||
2962 | mutex_unlock(&h->reset_mutex); | |
2963 | return rc; | |
2964 | } | |
2965 | ||
edd16368 SC |
2966 | static void hpsa_get_raid_level(struct ctlr_info *h, |
2967 | unsigned char *scsi3addr, unsigned char *raid_level) | |
2968 | { | |
2969 | int rc; | |
2970 | unsigned char *buf; | |
2971 | ||
2972 | *raid_level = RAID_UNKNOWN; | |
2973 | buf = kzalloc(64, GFP_KERNEL); | |
2974 | if (!buf) | |
2975 | return; | |
b7bb24eb | 2976 | rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0xC1, buf, 64); |
edd16368 SC |
2977 | if (rc == 0) |
2978 | *raid_level = buf[8]; | |
2979 | if (*raid_level > RAID_UNKNOWN) | |
2980 | *raid_level = RAID_UNKNOWN; | |
2981 | kfree(buf); | |
2982 | return; | |
2983 | } | |
2984 | ||
283b4a9b SC |
2985 | #define HPSA_MAP_DEBUG |
2986 | #ifdef HPSA_MAP_DEBUG | |
2987 | static void hpsa_debug_map_buff(struct ctlr_info *h, int rc, | |
2988 | struct raid_map_data *map_buff) | |
2989 | { | |
2990 | struct raid_map_disk_data *dd = &map_buff->data[0]; | |
2991 | int map, row, col; | |
2992 | u16 map_cnt, row_cnt, disks_per_row; | |
2993 | ||
2994 | if (rc != 0) | |
2995 | return; | |
2996 | ||
2ba8bfc8 SC |
2997 | /* Show details only if debugging has been activated. */ |
2998 | if (h->raid_offload_debug < 2) | |
2999 | return; | |
3000 | ||
283b4a9b SC |
3001 | dev_info(&h->pdev->dev, "structure_size = %u\n", |
3002 | le32_to_cpu(map_buff->structure_size)); | |
3003 | dev_info(&h->pdev->dev, "volume_blk_size = %u\n", | |
3004 | le32_to_cpu(map_buff->volume_blk_size)); | |
3005 | dev_info(&h->pdev->dev, "volume_blk_cnt = 0x%llx\n", | |
3006 | le64_to_cpu(map_buff->volume_blk_cnt)); | |
3007 | dev_info(&h->pdev->dev, "physicalBlockShift = %u\n", | |
3008 | map_buff->phys_blk_shift); | |
3009 | dev_info(&h->pdev->dev, "parity_rotation_shift = %u\n", | |
3010 | map_buff->parity_rotation_shift); | |
3011 | dev_info(&h->pdev->dev, "strip_size = %u\n", | |
3012 | le16_to_cpu(map_buff->strip_size)); | |
3013 | dev_info(&h->pdev->dev, "disk_starting_blk = 0x%llx\n", | |
3014 | le64_to_cpu(map_buff->disk_starting_blk)); | |
3015 | dev_info(&h->pdev->dev, "disk_blk_cnt = 0x%llx\n", | |
3016 | le64_to_cpu(map_buff->disk_blk_cnt)); | |
3017 | dev_info(&h->pdev->dev, "data_disks_per_row = %u\n", | |
3018 | le16_to_cpu(map_buff->data_disks_per_row)); | |
3019 | dev_info(&h->pdev->dev, "metadata_disks_per_row = %u\n", | |
3020 | le16_to_cpu(map_buff->metadata_disks_per_row)); | |
3021 | dev_info(&h->pdev->dev, "row_cnt = %u\n", | |
3022 | le16_to_cpu(map_buff->row_cnt)); | |
3023 | dev_info(&h->pdev->dev, "layout_map_count = %u\n", | |
3024 | le16_to_cpu(map_buff->layout_map_count)); | |
2b08b3e9 | 3025 | dev_info(&h->pdev->dev, "flags = 0x%x\n", |
dd0e19f3 | 3026 | le16_to_cpu(map_buff->flags)); |
2b08b3e9 DB |
3027 | dev_info(&h->pdev->dev, "encrypytion = %s\n", |
3028 | le16_to_cpu(map_buff->flags) & | |
3029 | RAID_MAP_FLAG_ENCRYPT_ON ? "ON" : "OFF"); | |
dd0e19f3 ST |
3030 | dev_info(&h->pdev->dev, "dekindex = %u\n", |
3031 | le16_to_cpu(map_buff->dekindex)); | |
283b4a9b SC |
3032 | map_cnt = le16_to_cpu(map_buff->layout_map_count); |
3033 | for (map = 0; map < map_cnt; map++) { | |
3034 | dev_info(&h->pdev->dev, "Map%u:\n", map); | |
3035 | row_cnt = le16_to_cpu(map_buff->row_cnt); | |
3036 | for (row = 0; row < row_cnt; row++) { | |
3037 | dev_info(&h->pdev->dev, " Row%u:\n", row); | |
3038 | disks_per_row = | |
3039 | le16_to_cpu(map_buff->data_disks_per_row); | |
3040 | for (col = 0; col < disks_per_row; col++, dd++) | |
3041 | dev_info(&h->pdev->dev, | |
3042 | " D%02u: h=0x%04x xor=%u,%u\n", | |
3043 | col, dd->ioaccel_handle, | |
3044 | dd->xor_mult[0], dd->xor_mult[1]); | |
3045 | disks_per_row = | |
3046 | le16_to_cpu(map_buff->metadata_disks_per_row); | |
3047 | for (col = 0; col < disks_per_row; col++, dd++) | |
3048 | dev_info(&h->pdev->dev, | |
3049 | " M%02u: h=0x%04x xor=%u,%u\n", | |
3050 | col, dd->ioaccel_handle, | |
3051 | dd->xor_mult[0], dd->xor_mult[1]); | |
3052 | } | |
3053 | } | |
3054 | } | |
3055 | #else | |
3056 | static void hpsa_debug_map_buff(__attribute__((unused)) struct ctlr_info *h, | |
3057 | __attribute__((unused)) int rc, | |
3058 | __attribute__((unused)) struct raid_map_data *map_buff) | |
3059 | { | |
3060 | } | |
3061 | #endif | |
3062 | ||
3063 | static int hpsa_get_raid_map(struct ctlr_info *h, | |
3064 | unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device) | |
3065 | { | |
3066 | int rc = 0; | |
3067 | struct CommandList *c; | |
3068 | struct ErrorInfo *ei; | |
3069 | ||
45fcb86e | 3070 | c = cmd_alloc(h); |
bf43caf3 | 3071 | |
283b4a9b SC |
3072 | if (fill_cmd(c, HPSA_GET_RAID_MAP, h, &this_device->raid_map, |
3073 | sizeof(this_device->raid_map), 0, | |
3074 | scsi3addr, TYPE_CMD)) { | |
2dd02d74 RE |
3075 | dev_warn(&h->pdev->dev, "hpsa_get_raid_map fill_cmd failed\n"); |
3076 | cmd_free(h, c); | |
3077 | return -1; | |
283b4a9b | 3078 | } |
25163bd5 WS |
3079 | rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, |
3080 | PCI_DMA_FROMDEVICE, NO_TIMEOUT); | |
3081 | if (rc) | |
3082 | goto out; | |
283b4a9b SC |
3083 | ei = c->err_info; |
3084 | if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) { | |
d1e8beac | 3085 | hpsa_scsi_interpret_error(h, c); |
25163bd5 WS |
3086 | rc = -1; |
3087 | goto out; | |
283b4a9b | 3088 | } |
45fcb86e | 3089 | cmd_free(h, c); |
283b4a9b SC |
3090 | |
3091 | /* @todo in the future, dynamically allocate RAID map memory */ | |
3092 | if (le32_to_cpu(this_device->raid_map.structure_size) > | |
3093 | sizeof(this_device->raid_map)) { | |
3094 | dev_warn(&h->pdev->dev, "RAID map size is too large!\n"); | |
3095 | rc = -1; | |
3096 | } | |
3097 | hpsa_debug_map_buff(h, rc, &this_device->raid_map); | |
3098 | return rc; | |
25163bd5 WS |
3099 | out: |
3100 | cmd_free(h, c); | |
3101 | return rc; | |
283b4a9b SC |
3102 | } |
3103 | ||
d04e62b9 KB |
3104 | static int hpsa_bmic_sense_subsystem_information(struct ctlr_info *h, |
3105 | unsigned char scsi3addr[], u16 bmic_device_index, | |
3106 | struct bmic_sense_subsystem_info *buf, size_t bufsize) | |
3107 | { | |
3108 | int rc = IO_OK; | |
3109 | struct CommandList *c; | |
3110 | struct ErrorInfo *ei; | |
3111 | ||
3112 | c = cmd_alloc(h); | |
3113 | ||
3114 | rc = fill_cmd(c, BMIC_SENSE_SUBSYSTEM_INFORMATION, h, buf, bufsize, | |
3115 | 0, RAID_CTLR_LUNID, TYPE_CMD); | |
3116 | if (rc) | |
3117 | goto out; | |
3118 | ||
3119 | c->Request.CDB[2] = bmic_device_index & 0xff; | |
3120 | c->Request.CDB[9] = (bmic_device_index >> 8) & 0xff; | |
3121 | ||
3122 | rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, | |
3123 | PCI_DMA_FROMDEVICE, NO_TIMEOUT); | |
3124 | if (rc) | |
3125 | goto out; | |
3126 | ei = c->err_info; | |
3127 | if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) { | |
3128 | hpsa_scsi_interpret_error(h, c); | |
3129 | rc = -1; | |
3130 | } | |
3131 | out: | |
3132 | cmd_free(h, c); | |
3133 | return rc; | |
3134 | } | |
3135 | ||
66749d0d ST |
3136 | static int hpsa_bmic_id_controller(struct ctlr_info *h, |
3137 | struct bmic_identify_controller *buf, size_t bufsize) | |
3138 | { | |
3139 | int rc = IO_OK; | |
3140 | struct CommandList *c; | |
3141 | struct ErrorInfo *ei; | |
3142 | ||
3143 | c = cmd_alloc(h); | |
3144 | ||
3145 | rc = fill_cmd(c, BMIC_IDENTIFY_CONTROLLER, h, buf, bufsize, | |
3146 | 0, RAID_CTLR_LUNID, TYPE_CMD); | |
3147 | if (rc) | |
3148 | goto out; | |
3149 | ||
3150 | rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, | |
3151 | PCI_DMA_FROMDEVICE, NO_TIMEOUT); | |
3152 | if (rc) | |
3153 | goto out; | |
3154 | ei = c->err_info; | |
3155 | if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) { | |
3156 | hpsa_scsi_interpret_error(h, c); | |
3157 | rc = -1; | |
3158 | } | |
3159 | out: | |
3160 | cmd_free(h, c); | |
3161 | return rc; | |
3162 | } | |
3163 | ||
03383736 DB |
3164 | static int hpsa_bmic_id_physical_device(struct ctlr_info *h, |
3165 | unsigned char scsi3addr[], u16 bmic_device_index, | |
3166 | struct bmic_identify_physical_device *buf, size_t bufsize) | |
3167 | { | |
3168 | int rc = IO_OK; | |
3169 | struct CommandList *c; | |
3170 | struct ErrorInfo *ei; | |
3171 | ||
3172 | c = cmd_alloc(h); | |
3173 | rc = fill_cmd(c, BMIC_IDENTIFY_PHYSICAL_DEVICE, h, buf, bufsize, | |
3174 | 0, RAID_CTLR_LUNID, TYPE_CMD); | |
3175 | if (rc) | |
3176 | goto out; | |
3177 | ||
3178 | c->Request.CDB[2] = bmic_device_index & 0xff; | |
3179 | c->Request.CDB[9] = (bmic_device_index >> 8) & 0xff; | |
3180 | ||
25163bd5 WS |
3181 | hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE, |
3182 | NO_TIMEOUT); | |
03383736 DB |
3183 | ei = c->err_info; |
3184 | if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) { | |
3185 | hpsa_scsi_interpret_error(h, c); | |
3186 | rc = -1; | |
3187 | } | |
3188 | out: | |
3189 | cmd_free(h, c); | |
d04e62b9 | 3190 | |
03383736 DB |
3191 | return rc; |
3192 | } | |
3193 | ||
d04e62b9 KB |
3194 | static u64 hpsa_get_sas_address_from_report_physical(struct ctlr_info *h, |
3195 | unsigned char *scsi3addr) | |
3196 | { | |
3197 | struct ReportExtendedLUNdata *physdev; | |
3198 | u32 nphysicals; | |
3199 | u64 sa = 0; | |
3200 | int i; | |
3201 | ||
3202 | physdev = kzalloc(sizeof(*physdev), GFP_KERNEL); | |
3203 | if (!physdev) | |
3204 | return 0; | |
3205 | ||
3206 | if (hpsa_scsi_do_report_phys_luns(h, physdev, sizeof(*physdev))) { | |
3207 | dev_err(&h->pdev->dev, "report physical LUNs failed.\n"); | |
3208 | kfree(physdev); | |
3209 | return 0; | |
3210 | } | |
3211 | nphysicals = get_unaligned_be32(physdev->LUNListLength) / 24; | |
3212 | ||
3213 | for (i = 0; i < nphysicals; i++) | |
3214 | if (!memcmp(&physdev->LUN[i].lunid[0], scsi3addr, 8)) { | |
3215 | sa = get_unaligned_be64(&physdev->LUN[i].wwid[0]); | |
3216 | break; | |
3217 | } | |
3218 | ||
3219 | kfree(physdev); | |
3220 | ||
3221 | return sa; | |
3222 | } | |
3223 | ||
3224 | static void hpsa_get_sas_address(struct ctlr_info *h, unsigned char *scsi3addr, | |
3225 | struct hpsa_scsi_dev_t *dev) | |
3226 | { | |
3227 | int rc; | |
3228 | u64 sa = 0; | |
3229 | ||
3230 | if (is_hba_lunid(scsi3addr)) { | |
3231 | struct bmic_sense_subsystem_info *ssi; | |
3232 | ||
3233 | ssi = kzalloc(sizeof(*ssi), GFP_KERNEL); | |
3234 | if (ssi == NULL) { | |
3235 | dev_warn(&h->pdev->dev, | |
3236 | "%s: out of memory\n", __func__); | |
3237 | return; | |
3238 | } | |
3239 | ||
3240 | rc = hpsa_bmic_sense_subsystem_information(h, | |
3241 | scsi3addr, 0, ssi, sizeof(*ssi)); | |
3242 | if (rc == 0) { | |
3243 | sa = get_unaligned_be64(ssi->primary_world_wide_id); | |
3244 | h->sas_address = sa; | |
3245 | } | |
3246 | ||
3247 | kfree(ssi); | |
3248 | } else | |
3249 | sa = hpsa_get_sas_address_from_report_physical(h, scsi3addr); | |
3250 | ||
3251 | dev->sas_address = sa; | |
3252 | } | |
3253 | ||
3254 | /* Get a device id from inquiry page 0x83 */ | |
1b70150a SC |
3255 | static int hpsa_vpd_page_supported(struct ctlr_info *h, |
3256 | unsigned char scsi3addr[], u8 page) | |
3257 | { | |
3258 | int rc; | |
3259 | int i; | |
3260 | int pages; | |
3261 | unsigned char *buf, bufsize; | |
3262 | ||
3263 | buf = kzalloc(256, GFP_KERNEL); | |
3264 | if (!buf) | |
3265 | return 0; | |
3266 | ||
3267 | /* Get the size of the page list first */ | |
3268 | rc = hpsa_scsi_do_inquiry(h, scsi3addr, | |
3269 | VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES, | |
3270 | buf, HPSA_VPD_HEADER_SZ); | |
3271 | if (rc != 0) | |
3272 | goto exit_unsupported; | |
3273 | pages = buf[3]; | |
3274 | if ((pages + HPSA_VPD_HEADER_SZ) <= 255) | |
3275 | bufsize = pages + HPSA_VPD_HEADER_SZ; | |
3276 | else | |
3277 | bufsize = 255; | |
3278 | ||
3279 | /* Get the whole VPD page list */ | |
3280 | rc = hpsa_scsi_do_inquiry(h, scsi3addr, | |
3281 | VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES, | |
3282 | buf, bufsize); | |
3283 | if (rc != 0) | |
3284 | goto exit_unsupported; | |
3285 | ||
3286 | pages = buf[3]; | |
3287 | for (i = 1; i <= pages; i++) | |
3288 | if (buf[3 + i] == page) | |
3289 | goto exit_supported; | |
3290 | exit_unsupported: | |
3291 | kfree(buf); | |
3292 | return 0; | |
3293 | exit_supported: | |
3294 | kfree(buf); | |
3295 | return 1; | |
3296 | } | |
3297 | ||
283b4a9b SC |
3298 | static void hpsa_get_ioaccel_status(struct ctlr_info *h, |
3299 | unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device) | |
3300 | { | |
3301 | int rc; | |
3302 | unsigned char *buf; | |
3303 | u8 ioaccel_status; | |
3304 | ||
3305 | this_device->offload_config = 0; | |
3306 | this_device->offload_enabled = 0; | |
41ce4c35 | 3307 | this_device->offload_to_be_enabled = 0; |
283b4a9b SC |
3308 | |
3309 | buf = kzalloc(64, GFP_KERNEL); | |
3310 | if (!buf) | |
3311 | return; | |
1b70150a SC |
3312 | if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_IOACCEL_STATUS)) |
3313 | goto out; | |
283b4a9b | 3314 | rc = hpsa_scsi_do_inquiry(h, scsi3addr, |
b7bb24eb | 3315 | VPD_PAGE | HPSA_VPD_LV_IOACCEL_STATUS, buf, 64); |
283b4a9b SC |
3316 | if (rc != 0) |
3317 | goto out; | |
3318 | ||
3319 | #define IOACCEL_STATUS_BYTE 4 | |
3320 | #define OFFLOAD_CONFIGURED_BIT 0x01 | |
3321 | #define OFFLOAD_ENABLED_BIT 0x02 | |
3322 | ioaccel_status = buf[IOACCEL_STATUS_BYTE]; | |
3323 | this_device->offload_config = | |
3324 | !!(ioaccel_status & OFFLOAD_CONFIGURED_BIT); | |
3325 | if (this_device->offload_config) { | |
3326 | this_device->offload_enabled = | |
3327 | !!(ioaccel_status & OFFLOAD_ENABLED_BIT); | |
3328 | if (hpsa_get_raid_map(h, scsi3addr, this_device)) | |
3329 | this_device->offload_enabled = 0; | |
3330 | } | |
41ce4c35 | 3331 | this_device->offload_to_be_enabled = this_device->offload_enabled; |
283b4a9b SC |
3332 | out: |
3333 | kfree(buf); | |
3334 | return; | |
3335 | } | |
3336 | ||
edd16368 SC |
3337 | /* Get the device id from inquiry page 0x83 */ |
3338 | static int hpsa_get_device_id(struct ctlr_info *h, unsigned char *scsi3addr, | |
75d23d89 | 3339 | unsigned char *device_id, int index, int buflen) |
edd16368 SC |
3340 | { |
3341 | int rc; | |
3342 | unsigned char *buf; | |
3343 | ||
3344 | if (buflen > 16) | |
3345 | buflen = 16; | |
3346 | buf = kzalloc(64, GFP_KERNEL); | |
3347 | if (!buf) | |
a84d794d | 3348 | return -ENOMEM; |
b7bb24eb | 3349 | rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0x83, buf, 64); |
edd16368 | 3350 | if (rc == 0) |
75d23d89 DB |
3351 | memcpy(device_id, &buf[index], buflen); |
3352 | ||
edd16368 | 3353 | kfree(buf); |
75d23d89 | 3354 | |
edd16368 SC |
3355 | return rc != 0; |
3356 | } | |
3357 | ||
3358 | static int hpsa_scsi_do_report_luns(struct ctlr_info *h, int logical, | |
03383736 | 3359 | void *buf, int bufsize, |
edd16368 SC |
3360 | int extended_response) |
3361 | { | |
3362 | int rc = IO_OK; | |
3363 | struct CommandList *c; | |
3364 | unsigned char scsi3addr[8]; | |
3365 | struct ErrorInfo *ei; | |
3366 | ||
45fcb86e | 3367 | c = cmd_alloc(h); |
bf43caf3 | 3368 | |
e89c0ae7 SC |
3369 | /* address the controller */ |
3370 | memset(scsi3addr, 0, sizeof(scsi3addr)); | |
a2dac136 SC |
3371 | if (fill_cmd(c, logical ? HPSA_REPORT_LOG : HPSA_REPORT_PHYS, h, |
3372 | buf, bufsize, 0, scsi3addr, TYPE_CMD)) { | |
3373 | rc = -1; | |
3374 | goto out; | |
3375 | } | |
edd16368 SC |
3376 | if (extended_response) |
3377 | c->Request.CDB[1] = extended_response; | |
25163bd5 WS |
3378 | rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, |
3379 | PCI_DMA_FROMDEVICE, NO_TIMEOUT); | |
3380 | if (rc) | |
3381 | goto out; | |
edd16368 SC |
3382 | ei = c->err_info; |
3383 | if (ei->CommandStatus != 0 && | |
3384 | ei->CommandStatus != CMD_DATA_UNDERRUN) { | |
d1e8beac | 3385 | hpsa_scsi_interpret_error(h, c); |
edd16368 | 3386 | rc = -1; |
283b4a9b | 3387 | } else { |
03383736 DB |
3388 | struct ReportLUNdata *rld = buf; |
3389 | ||
3390 | if (rld->extended_response_flag != extended_response) { | |
283b4a9b SC |
3391 | dev_err(&h->pdev->dev, |
3392 | "report luns requested format %u, got %u\n", | |
3393 | extended_response, | |
03383736 | 3394 | rld->extended_response_flag); |
283b4a9b SC |
3395 | rc = -1; |
3396 | } | |
edd16368 | 3397 | } |
a2dac136 | 3398 | out: |
45fcb86e | 3399 | cmd_free(h, c); |
edd16368 SC |
3400 | return rc; |
3401 | } | |
3402 | ||
3403 | static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h, | |
03383736 | 3404 | struct ReportExtendedLUNdata *buf, int bufsize) |
edd16368 | 3405 | { |
03383736 DB |
3406 | return hpsa_scsi_do_report_luns(h, 0, buf, bufsize, |
3407 | HPSA_REPORT_PHYS_EXTENDED); | |
edd16368 SC |
3408 | } |
3409 | ||
3410 | static inline int hpsa_scsi_do_report_log_luns(struct ctlr_info *h, | |
3411 | struct ReportLUNdata *buf, int bufsize) | |
3412 | { | |
3413 | return hpsa_scsi_do_report_luns(h, 1, buf, bufsize, 0); | |
3414 | } | |
3415 | ||
3416 | static inline void hpsa_set_bus_target_lun(struct hpsa_scsi_dev_t *device, | |
3417 | int bus, int target, int lun) | |
3418 | { | |
3419 | device->bus = bus; | |
3420 | device->target = target; | |
3421 | device->lun = lun; | |
3422 | } | |
3423 | ||
9846590e SC |
3424 | /* Use VPD inquiry to get details of volume status */ |
3425 | static int hpsa_get_volume_status(struct ctlr_info *h, | |
3426 | unsigned char scsi3addr[]) | |
3427 | { | |
3428 | int rc; | |
3429 | int status; | |
3430 | int size; | |
3431 | unsigned char *buf; | |
3432 | ||
3433 | buf = kzalloc(64, GFP_KERNEL); | |
3434 | if (!buf) | |
3435 | return HPSA_VPD_LV_STATUS_UNSUPPORTED; | |
3436 | ||
3437 | /* Does controller have VPD for logical volume status? */ | |
24a4b078 | 3438 | if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_STATUS)) |
9846590e | 3439 | goto exit_failed; |
9846590e SC |
3440 | |
3441 | /* Get the size of the VPD return buffer */ | |
3442 | rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS, | |
3443 | buf, HPSA_VPD_HEADER_SZ); | |
24a4b078 | 3444 | if (rc != 0) |
9846590e | 3445 | goto exit_failed; |
9846590e SC |
3446 | size = buf[3]; |
3447 | ||
3448 | /* Now get the whole VPD buffer */ | |
3449 | rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS, | |
3450 | buf, size + HPSA_VPD_HEADER_SZ); | |
24a4b078 | 3451 | if (rc != 0) |
9846590e | 3452 | goto exit_failed; |
9846590e SC |
3453 | status = buf[4]; /* status byte */ |
3454 | ||
3455 | kfree(buf); | |
3456 | return status; | |
3457 | exit_failed: | |
3458 | kfree(buf); | |
3459 | return HPSA_VPD_LV_STATUS_UNSUPPORTED; | |
3460 | } | |
3461 | ||
3462 | /* Determine offline status of a volume. | |
3463 | * Return either: | |
3464 | * 0 (not offline) | |
67955ba3 | 3465 | * 0xff (offline for unknown reasons) |
9846590e SC |
3466 | * # (integer code indicating one of several NOT READY states |
3467 | * describing why a volume is to be kept offline) | |
3468 | */ | |
67955ba3 | 3469 | static int hpsa_volume_offline(struct ctlr_info *h, |
9846590e SC |
3470 | unsigned char scsi3addr[]) |
3471 | { | |
3472 | struct CommandList *c; | |
9437ac43 SC |
3473 | unsigned char *sense; |
3474 | u8 sense_key, asc, ascq; | |
3475 | int sense_len; | |
25163bd5 | 3476 | int rc, ldstat = 0; |
9846590e SC |
3477 | u16 cmd_status; |
3478 | u8 scsi_status; | |
3479 | #define ASC_LUN_NOT_READY 0x04 | |
3480 | #define ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS 0x04 | |
3481 | #define ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ 0x02 | |
3482 | ||
3483 | c = cmd_alloc(h); | |
bf43caf3 | 3484 | |
9846590e | 3485 | (void) fill_cmd(c, TEST_UNIT_READY, h, NULL, 0, 0, scsi3addr, TYPE_CMD); |
25163bd5 WS |
3486 | rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT); |
3487 | if (rc) { | |
3488 | cmd_free(h, c); | |
3489 | return 0; | |
3490 | } | |
9846590e | 3491 | sense = c->err_info->SenseInfo; |
9437ac43 SC |
3492 | if (c->err_info->SenseLen > sizeof(c->err_info->SenseInfo)) |
3493 | sense_len = sizeof(c->err_info->SenseInfo); | |
3494 | else | |
3495 | sense_len = c->err_info->SenseLen; | |
3496 | decode_sense_data(sense, sense_len, &sense_key, &asc, &ascq); | |
9846590e SC |
3497 | cmd_status = c->err_info->CommandStatus; |
3498 | scsi_status = c->err_info->ScsiStatus; | |
3499 | cmd_free(h, c); | |
3500 | /* Is the volume 'not ready'? */ | |
3501 | if (cmd_status != CMD_TARGET_STATUS || | |
3502 | scsi_status != SAM_STAT_CHECK_CONDITION || | |
3503 | sense_key != NOT_READY || | |
3504 | asc != ASC_LUN_NOT_READY) { | |
3505 | return 0; | |
3506 | } | |
3507 | ||
3508 | /* Determine the reason for not ready state */ | |
3509 | ldstat = hpsa_get_volume_status(h, scsi3addr); | |
3510 | ||
3511 | /* Keep volume offline in certain cases: */ | |
3512 | switch (ldstat) { | |
3513 | case HPSA_LV_UNDERGOING_ERASE: | |
5ca01204 | 3514 | case HPSA_LV_NOT_AVAILABLE: |
9846590e SC |
3515 | case HPSA_LV_UNDERGOING_RPI: |
3516 | case HPSA_LV_PENDING_RPI: | |
3517 | case HPSA_LV_ENCRYPTED_NO_KEY: | |
3518 | case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER: | |
3519 | case HPSA_LV_UNDERGOING_ENCRYPTION: | |
3520 | case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING: | |
3521 | case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER: | |
3522 | return ldstat; | |
3523 | case HPSA_VPD_LV_STATUS_UNSUPPORTED: | |
3524 | /* If VPD status page isn't available, | |
3525 | * use ASC/ASCQ to determine state | |
3526 | */ | |
3527 | if ((ascq == ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS) || | |
3528 | (ascq == ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ)) | |
3529 | return ldstat; | |
3530 | break; | |
3531 | default: | |
3532 | break; | |
3533 | } | |
3534 | return 0; | |
3535 | } | |
3536 | ||
9b5c48c2 SC |
3537 | /* |
3538 | * Find out if a logical device supports aborts by simply trying one. | |
3539 | * Smart Array may claim not to support aborts on logical drives, but | |
3540 | * if a MSA2000 * is connected, the drives on that will be presented | |
3541 | * by the Smart Array as logical drives, and aborts may be sent to | |
3542 | * those devices successfully. So the simplest way to find out is | |
3543 | * to simply try an abort and see how the device responds. | |
3544 | */ | |
3545 | static int hpsa_device_supports_aborts(struct ctlr_info *h, | |
3546 | unsigned char *scsi3addr) | |
3547 | { | |
3548 | struct CommandList *c; | |
3549 | struct ErrorInfo *ei; | |
3550 | int rc = 0; | |
3551 | ||
3552 | u64 tag = (u64) -1; /* bogus tag */ | |
3553 | ||
3554 | /* Assume that physical devices support aborts */ | |
3555 | if (!is_logical_dev_addr_mode(scsi3addr)) | |
3556 | return 1; | |
3557 | ||
3558 | c = cmd_alloc(h); | |
bf43caf3 | 3559 | |
9b5c48c2 SC |
3560 | (void) fill_cmd(c, HPSA_ABORT_MSG, h, &tag, 0, 0, scsi3addr, TYPE_MSG); |
3561 | (void) hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT); | |
3562 | /* no unmap needed here because no data xfer. */ | |
3563 | ei = c->err_info; | |
3564 | switch (ei->CommandStatus) { | |
3565 | case CMD_INVALID: | |
3566 | rc = 0; | |
3567 | break; | |
3568 | case CMD_UNABORTABLE: | |
3569 | case CMD_ABORT_FAILED: | |
3570 | rc = 1; | |
3571 | break; | |
9437ac43 SC |
3572 | case CMD_TMF_STATUS: |
3573 | rc = hpsa_evaluate_tmf_status(h, c); | |
3574 | break; | |
9b5c48c2 SC |
3575 | default: |
3576 | rc = 0; | |
3577 | break; | |
3578 | } | |
3579 | cmd_free(h, c); | |
3580 | return rc; | |
3581 | } | |
3582 | ||
75d23d89 DB |
3583 | static void sanitize_inquiry_string(unsigned char *s, int len) |
3584 | { | |
3585 | bool terminated = false; | |
3586 | ||
3587 | for (; len > 0; (--len, ++s)) { | |
3588 | if (*s == 0) | |
3589 | terminated = true; | |
3590 | if (terminated || *s < 0x20 || *s > 0x7e) | |
3591 | *s = ' '; | |
3592 | } | |
3593 | } | |
3594 | ||
edd16368 | 3595 | static int hpsa_update_device_info(struct ctlr_info *h, |
0b0e1d6c SC |
3596 | unsigned char scsi3addr[], struct hpsa_scsi_dev_t *this_device, |
3597 | unsigned char *is_OBDR_device) | |
edd16368 | 3598 | { |
0b0e1d6c SC |
3599 | |
3600 | #define OBDR_SIG_OFFSET 43 | |
3601 | #define OBDR_TAPE_SIG "$DR-10" | |
3602 | #define OBDR_SIG_LEN (sizeof(OBDR_TAPE_SIG) - 1) | |
3603 | #define OBDR_TAPE_INQ_SIZE (OBDR_SIG_OFFSET + OBDR_SIG_LEN) | |
3604 | ||
ea6d3bc3 | 3605 | unsigned char *inq_buff; |
0b0e1d6c | 3606 | unsigned char *obdr_sig; |
683fc444 | 3607 | int rc = 0; |
edd16368 | 3608 | |
ea6d3bc3 | 3609 | inq_buff = kzalloc(OBDR_TAPE_INQ_SIZE, GFP_KERNEL); |
683fc444 DB |
3610 | if (!inq_buff) { |
3611 | rc = -ENOMEM; | |
edd16368 | 3612 | goto bail_out; |
683fc444 | 3613 | } |
edd16368 | 3614 | |
edd16368 SC |
3615 | /* Do an inquiry to the device to see what it is. */ |
3616 | if (hpsa_scsi_do_inquiry(h, scsi3addr, 0, inq_buff, | |
3617 | (unsigned char) OBDR_TAPE_INQ_SIZE) != 0) { | |
3618 | /* Inquiry failed (msg printed already) */ | |
3619 | dev_err(&h->pdev->dev, | |
3620 | "hpsa_update_device_info: inquiry failed\n"); | |
683fc444 | 3621 | rc = -EIO; |
edd16368 SC |
3622 | goto bail_out; |
3623 | } | |
3624 | ||
75d23d89 DB |
3625 | sanitize_inquiry_string(&inq_buff[8], 8); |
3626 | sanitize_inquiry_string(&inq_buff[16], 16); | |
3627 | ||
edd16368 SC |
3628 | this_device->devtype = (inq_buff[0] & 0x1f); |
3629 | memcpy(this_device->scsi3addr, scsi3addr, 8); | |
3630 | memcpy(this_device->vendor, &inq_buff[8], | |
3631 | sizeof(this_device->vendor)); | |
3632 | memcpy(this_device->model, &inq_buff[16], | |
3633 | sizeof(this_device->model)); | |
edd16368 SC |
3634 | memset(this_device->device_id, 0, |
3635 | sizeof(this_device->device_id)); | |
75d23d89 | 3636 | hpsa_get_device_id(h, scsi3addr, this_device->device_id, 8, |
edd16368 SC |
3637 | sizeof(this_device->device_id)); |
3638 | ||
3639 | if (this_device->devtype == TYPE_DISK && | |
283b4a9b | 3640 | is_logical_dev_addr_mode(scsi3addr)) { |
67955ba3 SC |
3641 | int volume_offline; |
3642 | ||
edd16368 | 3643 | hpsa_get_raid_level(h, scsi3addr, &this_device->raid_level); |
283b4a9b SC |
3644 | if (h->fw_support & MISC_FW_RAID_OFFLOAD_BASIC) |
3645 | hpsa_get_ioaccel_status(h, scsi3addr, this_device); | |
67955ba3 SC |
3646 | volume_offline = hpsa_volume_offline(h, scsi3addr); |
3647 | if (volume_offline < 0 || volume_offline > 0xff) | |
3648 | volume_offline = HPSA_VPD_LV_STATUS_UNSUPPORTED; | |
3649 | this_device->volume_offline = volume_offline & 0xff; | |
283b4a9b | 3650 | } else { |
edd16368 | 3651 | this_device->raid_level = RAID_UNKNOWN; |
283b4a9b SC |
3652 | this_device->offload_config = 0; |
3653 | this_device->offload_enabled = 0; | |
41ce4c35 | 3654 | this_device->offload_to_be_enabled = 0; |
a3144e0b | 3655 | this_device->hba_ioaccel_enabled = 0; |
9846590e | 3656 | this_device->volume_offline = 0; |
03383736 | 3657 | this_device->queue_depth = h->nr_cmds; |
283b4a9b | 3658 | } |
edd16368 | 3659 | |
0b0e1d6c SC |
3660 | if (is_OBDR_device) { |
3661 | /* See if this is a One-Button-Disaster-Recovery device | |
3662 | * by looking for "$DR-10" at offset 43 in inquiry data. | |
3663 | */ | |
3664 | obdr_sig = &inq_buff[OBDR_SIG_OFFSET]; | |
3665 | *is_OBDR_device = (this_device->devtype == TYPE_ROM && | |
3666 | strncmp(obdr_sig, OBDR_TAPE_SIG, | |
3667 | OBDR_SIG_LEN) == 0); | |
3668 | } | |
edd16368 SC |
3669 | kfree(inq_buff); |
3670 | return 0; | |
3671 | ||
3672 | bail_out: | |
3673 | kfree(inq_buff); | |
683fc444 | 3674 | return rc; |
edd16368 SC |
3675 | } |
3676 | ||
9b5c48c2 SC |
3677 | static void hpsa_update_device_supports_aborts(struct ctlr_info *h, |
3678 | struct hpsa_scsi_dev_t *dev, u8 *scsi3addr) | |
3679 | { | |
3680 | unsigned long flags; | |
3681 | int rc, entry; | |
3682 | /* | |
3683 | * See if this device supports aborts. If we already know | |
3684 | * the device, we already know if it supports aborts, otherwise | |
3685 | * we have to find out if it supports aborts by trying one. | |
3686 | */ | |
3687 | spin_lock_irqsave(&h->devlock, flags); | |
3688 | rc = hpsa_scsi_find_entry(dev, h->dev, h->ndevices, &entry); | |
3689 | if ((rc == DEVICE_SAME || rc == DEVICE_UPDATED) && | |
3690 | entry >= 0 && entry < h->ndevices) { | |
3691 | dev->supports_aborts = h->dev[entry]->supports_aborts; | |
3692 | spin_unlock_irqrestore(&h->devlock, flags); | |
3693 | } else { | |
3694 | spin_unlock_irqrestore(&h->devlock, flags); | |
3695 | dev->supports_aborts = | |
3696 | hpsa_device_supports_aborts(h, scsi3addr); | |
3697 | if (dev->supports_aborts < 0) | |
3698 | dev->supports_aborts = 0; | |
3699 | } | |
3700 | } | |
3701 | ||
c795505a KB |
3702 | /* |
3703 | * Helper function to assign bus, target, lun mapping of devices. | |
edd16368 SC |
3704 | * Logical drive target and lun are assigned at this time, but |
3705 | * physical device lun and target assignment are deferred (assigned | |
3706 | * in hpsa_find_target_lun, called by hpsa_scsi_add_entry.) | |
c795505a | 3707 | */ |
edd16368 | 3708 | static void figure_bus_target_lun(struct ctlr_info *h, |
1f310bde | 3709 | u8 *lunaddrbytes, struct hpsa_scsi_dev_t *device) |
edd16368 | 3710 | { |
c795505a | 3711 | u32 lunid = get_unaligned_le32(lunaddrbytes); |
1f310bde SC |
3712 | |
3713 | if (!is_logical_dev_addr_mode(lunaddrbytes)) { | |
3714 | /* physical device, target and lun filled in later */ | |
edd16368 | 3715 | if (is_hba_lunid(lunaddrbytes)) |
c795505a KB |
3716 | hpsa_set_bus_target_lun(device, |
3717 | HPSA_HBA_BUS, 0, lunid & 0x3fff); | |
edd16368 | 3718 | else |
1f310bde | 3719 | /* defer target, lun assignment for physical devices */ |
c795505a KB |
3720 | hpsa_set_bus_target_lun(device, |
3721 | HPSA_PHYSICAL_DEVICE_BUS, -1, -1); | |
1f310bde SC |
3722 | return; |
3723 | } | |
3724 | /* It's a logical device */ | |
66749d0d | 3725 | if (device->external) { |
1f310bde | 3726 | hpsa_set_bus_target_lun(device, |
c795505a KB |
3727 | HPSA_EXTERNAL_RAID_VOLUME_BUS, (lunid >> 16) & 0x3fff, |
3728 | lunid & 0x00ff); | |
1f310bde | 3729 | return; |
edd16368 | 3730 | } |
c795505a KB |
3731 | hpsa_set_bus_target_lun(device, HPSA_RAID_VOLUME_BUS, |
3732 | 0, lunid & 0x3fff); | |
edd16368 SC |
3733 | } |
3734 | ||
edd16368 | 3735 | |
54b6e9e9 ST |
3736 | /* |
3737 | * Get address of physical disk used for an ioaccel2 mode command: | |
3738 | * 1. Extract ioaccel2 handle from the command. | |
3739 | * 2. Find a matching ioaccel2 handle from list of physical disks. | |
3740 | * 3. Return: | |
3741 | * 1 and set scsi3addr to address of matching physical | |
3742 | * 0 if no matching physical disk was found. | |
3743 | */ | |
3744 | static int hpsa_get_pdisk_of_ioaccel2(struct ctlr_info *h, | |
3745 | struct CommandList *ioaccel2_cmd_to_abort, unsigned char *scsi3addr) | |
3746 | { | |
41ce4c35 SC |
3747 | struct io_accel2_cmd *c2 = |
3748 | &h->ioaccel2_cmd_pool[ioaccel2_cmd_to_abort->cmdindex]; | |
3749 | unsigned long flags; | |
54b6e9e9 | 3750 | int i; |
54b6e9e9 | 3751 | |
41ce4c35 SC |
3752 | spin_lock_irqsave(&h->devlock, flags); |
3753 | for (i = 0; i < h->ndevices; i++) | |
3754 | if (h->dev[i]->ioaccel_handle == le32_to_cpu(c2->scsi_nexus)) { | |
3755 | memcpy(scsi3addr, h->dev[i]->scsi3addr, | |
3756 | sizeof(h->dev[i]->scsi3addr)); | |
3757 | spin_unlock_irqrestore(&h->devlock, flags); | |
3758 | return 1; | |
3759 | } | |
3760 | spin_unlock_irqrestore(&h->devlock, flags); | |
3761 | return 0; | |
54b6e9e9 | 3762 | } |
41ce4c35 | 3763 | |
66749d0d ST |
3764 | static int figure_external_status(struct ctlr_info *h, int raid_ctlr_position, |
3765 | int i, int nphysicals, int nlocal_logicals) | |
3766 | { | |
3767 | /* In report logicals, local logicals are listed first, | |
3768 | * then any externals. | |
3769 | */ | |
3770 | int logicals_start = nphysicals + (raid_ctlr_position == 0); | |
3771 | ||
3772 | if (i == raid_ctlr_position) | |
3773 | return 0; | |
3774 | ||
3775 | if (i < logicals_start) | |
3776 | return 0; | |
3777 | ||
3778 | /* i is in logicals range, but still within local logicals */ | |
3779 | if ((i - nphysicals - (raid_ctlr_position == 0)) < nlocal_logicals) | |
3780 | return 0; | |
3781 | ||
3782 | return 1; /* it's an external lun */ | |
3783 | } | |
3784 | ||
edd16368 SC |
3785 | /* |
3786 | * Do CISS_REPORT_PHYS and CISS_REPORT_LOG. Data is returned in physdev, | |
3787 | * logdev. The number of luns in physdev and logdev are returned in | |
3788 | * *nphysicals and *nlogicals, respectively. | |
3789 | * Returns 0 on success, -1 otherwise. | |
3790 | */ | |
3791 | static int hpsa_gather_lun_info(struct ctlr_info *h, | |
03383736 | 3792 | struct ReportExtendedLUNdata *physdev, u32 *nphysicals, |
01a02ffc | 3793 | struct ReportLUNdata *logdev, u32 *nlogicals) |
edd16368 | 3794 | { |
03383736 | 3795 | if (hpsa_scsi_do_report_phys_luns(h, physdev, sizeof(*physdev))) { |
edd16368 SC |
3796 | dev_err(&h->pdev->dev, "report physical LUNs failed.\n"); |
3797 | return -1; | |
3798 | } | |
03383736 | 3799 | *nphysicals = be32_to_cpu(*((__be32 *)physdev->LUNListLength)) / 24; |
edd16368 | 3800 | if (*nphysicals > HPSA_MAX_PHYS_LUN) { |
03383736 DB |
3801 | dev_warn(&h->pdev->dev, "maximum physical LUNs (%d) exceeded. %d LUNs ignored.\n", |
3802 | HPSA_MAX_PHYS_LUN, *nphysicals - HPSA_MAX_PHYS_LUN); | |
edd16368 SC |
3803 | *nphysicals = HPSA_MAX_PHYS_LUN; |
3804 | } | |
03383736 | 3805 | if (hpsa_scsi_do_report_log_luns(h, logdev, sizeof(*logdev))) { |
edd16368 SC |
3806 | dev_err(&h->pdev->dev, "report logical LUNs failed.\n"); |
3807 | return -1; | |
3808 | } | |
6df1e954 | 3809 | *nlogicals = be32_to_cpu(*((__be32 *) logdev->LUNListLength)) / 8; |
edd16368 SC |
3810 | /* Reject Logicals in excess of our max capability. */ |
3811 | if (*nlogicals > HPSA_MAX_LUN) { | |
3812 | dev_warn(&h->pdev->dev, | |
3813 | "maximum logical LUNs (%d) exceeded. " | |
3814 | "%d LUNs ignored.\n", HPSA_MAX_LUN, | |
3815 | *nlogicals - HPSA_MAX_LUN); | |
3816 | *nlogicals = HPSA_MAX_LUN; | |
3817 | } | |
3818 | if (*nlogicals + *nphysicals > HPSA_MAX_PHYS_LUN) { | |
3819 | dev_warn(&h->pdev->dev, | |
3820 | "maximum logical + physical LUNs (%d) exceeded. " | |
3821 | "%d LUNs ignored.\n", HPSA_MAX_PHYS_LUN, | |
3822 | *nphysicals + *nlogicals - HPSA_MAX_PHYS_LUN); | |
3823 | *nlogicals = HPSA_MAX_PHYS_LUN - *nphysicals; | |
3824 | } | |
3825 | return 0; | |
3826 | } | |
3827 | ||
42a91641 DB |
3828 | static u8 *figure_lunaddrbytes(struct ctlr_info *h, int raid_ctlr_position, |
3829 | int i, int nphysicals, int nlogicals, | |
a93aa1fe | 3830 | struct ReportExtendedLUNdata *physdev_list, |
339b2b14 SC |
3831 | struct ReportLUNdata *logdev_list) |
3832 | { | |
3833 | /* Helper function, figure out where the LUN ID info is coming from | |
3834 | * given index i, lists of physical and logical devices, where in | |
3835 | * the list the raid controller is supposed to appear (first or last) | |
3836 | */ | |
3837 | ||
3838 | int logicals_start = nphysicals + (raid_ctlr_position == 0); | |
3839 | int last_device = nphysicals + nlogicals + (raid_ctlr_position == 0); | |
3840 | ||
3841 | if (i == raid_ctlr_position) | |
3842 | return RAID_CTLR_LUNID; | |
3843 | ||
3844 | if (i < logicals_start) | |
d5b5d964 SC |
3845 | return &physdev_list->LUN[i - |
3846 | (raid_ctlr_position == 0)].lunid[0]; | |
339b2b14 SC |
3847 | |
3848 | if (i < last_device) | |
3849 | return &logdev_list->LUN[i - nphysicals - | |
3850 | (raid_ctlr_position == 0)][0]; | |
3851 | BUG(); | |
3852 | return NULL; | |
3853 | } | |
3854 | ||
03383736 DB |
3855 | /* get physical drive ioaccel handle and queue depth */ |
3856 | static void hpsa_get_ioaccel_drive_info(struct ctlr_info *h, | |
3857 | struct hpsa_scsi_dev_t *dev, | |
f2039b03 | 3858 | struct ReportExtendedLUNdata *rlep, int rle_index, |
03383736 DB |
3859 | struct bmic_identify_physical_device *id_phys) |
3860 | { | |
3861 | int rc; | |
f2039b03 | 3862 | struct ext_report_lun_entry *rle = &rlep->LUN[rle_index]; |
03383736 DB |
3863 | |
3864 | dev->ioaccel_handle = rle->ioaccel_handle; | |
f2039b03 | 3865 | if ((rle->device_flags & 0x08) && dev->ioaccel_handle) |
a3144e0b | 3866 | dev->hba_ioaccel_enabled = 1; |
03383736 | 3867 | memset(id_phys, 0, sizeof(*id_phys)); |
f2039b03 DB |
3868 | rc = hpsa_bmic_id_physical_device(h, &rle->lunid[0], |
3869 | GET_BMIC_DRIVE_NUMBER(&rle->lunid[0]), id_phys, | |
03383736 DB |
3870 | sizeof(*id_phys)); |
3871 | if (!rc) | |
3872 | /* Reserve space for FW operations */ | |
3873 | #define DRIVE_CMDS_RESERVED_FOR_FW 2 | |
3874 | #define DRIVE_QUEUE_DEPTH 7 | |
3875 | dev->queue_depth = | |
3876 | le16_to_cpu(id_phys->current_queue_depth_limit) - | |
3877 | DRIVE_CMDS_RESERVED_FOR_FW; | |
3878 | else | |
3879 | dev->queue_depth = DRIVE_QUEUE_DEPTH; /* conservative */ | |
03383736 DB |
3880 | } |
3881 | ||
8270b862 | 3882 | static void hpsa_get_path_info(struct hpsa_scsi_dev_t *this_device, |
f2039b03 | 3883 | struct ReportExtendedLUNdata *rlep, int rle_index, |
8270b862 JH |
3884 | struct bmic_identify_physical_device *id_phys) |
3885 | { | |
f2039b03 DB |
3886 | struct ext_report_lun_entry *rle = &rlep->LUN[rle_index]; |
3887 | ||
3888 | if ((rle->device_flags & 0x08) && this_device->ioaccel_handle) | |
8270b862 JH |
3889 | this_device->hba_ioaccel_enabled = 1; |
3890 | ||
3891 | memcpy(&this_device->active_path_index, | |
3892 | &id_phys->active_path_number, | |
3893 | sizeof(this_device->active_path_index)); | |
3894 | memcpy(&this_device->path_map, | |
3895 | &id_phys->redundant_path_present_map, | |
3896 | sizeof(this_device->path_map)); | |
3897 | memcpy(&this_device->box, | |
3898 | &id_phys->alternate_paths_phys_box_on_port, | |
3899 | sizeof(this_device->box)); | |
3900 | memcpy(&this_device->phys_connector, | |
3901 | &id_phys->alternate_paths_phys_connector, | |
3902 | sizeof(this_device->phys_connector)); | |
3903 | memcpy(&this_device->bay, | |
3904 | &id_phys->phys_bay_in_box, | |
3905 | sizeof(this_device->bay)); | |
3906 | } | |
3907 | ||
66749d0d ST |
3908 | /* get number of local logical disks. */ |
3909 | static int hpsa_set_local_logical_count(struct ctlr_info *h, | |
3910 | struct bmic_identify_controller *id_ctlr, | |
3911 | u32 *nlocals) | |
3912 | { | |
3913 | int rc; | |
3914 | ||
3915 | if (!id_ctlr) { | |
3916 | dev_warn(&h->pdev->dev, "%s: id_ctlr buffer is NULL.\n", | |
3917 | __func__); | |
3918 | return -ENOMEM; | |
3919 | } | |
3920 | memset(id_ctlr, 0, sizeof(*id_ctlr)); | |
3921 | rc = hpsa_bmic_id_controller(h, id_ctlr, sizeof(*id_ctlr)); | |
3922 | if (!rc) | |
3923 | if (id_ctlr->configured_logical_drive_count < 256) | |
3924 | *nlocals = id_ctlr->configured_logical_drive_count; | |
3925 | else | |
3926 | *nlocals = le16_to_cpu( | |
3927 | id_ctlr->extended_logical_unit_count); | |
3928 | else | |
3929 | *nlocals = -1; | |
3930 | return rc; | |
3931 | } | |
3932 | ||
3933 | ||
8aa60681 | 3934 | static void hpsa_update_scsi_devices(struct ctlr_info *h) |
edd16368 SC |
3935 | { |
3936 | /* the idea here is we could get notified | |
3937 | * that some devices have changed, so we do a report | |
3938 | * physical luns and report logical luns cmd, and adjust | |
3939 | * our list of devices accordingly. | |
3940 | * | |
3941 | * The scsi3addr's of devices won't change so long as the | |
3942 | * adapter is not reset. That means we can rescan and | |
3943 | * tell which devices we already know about, vs. new | |
3944 | * devices, vs. disappearing devices. | |
3945 | */ | |
a93aa1fe | 3946 | struct ReportExtendedLUNdata *physdev_list = NULL; |
edd16368 | 3947 | struct ReportLUNdata *logdev_list = NULL; |
03383736 | 3948 | struct bmic_identify_physical_device *id_phys = NULL; |
66749d0d | 3949 | struct bmic_identify_controller *id_ctlr = NULL; |
01a02ffc SC |
3950 | u32 nphysicals = 0; |
3951 | u32 nlogicals = 0; | |
66749d0d | 3952 | u32 nlocal_logicals = 0; |
01a02ffc | 3953 | u32 ndev_allocated = 0; |
edd16368 SC |
3954 | struct hpsa_scsi_dev_t **currentsd, *this_device, *tmpdevice; |
3955 | int ncurrent = 0; | |
4f4eb9f1 | 3956 | int i, n_ext_target_devs, ndevs_to_allocate; |
339b2b14 | 3957 | int raid_ctlr_position; |
04fa2f44 | 3958 | bool physical_device; |
aca4a520 | 3959 | DECLARE_BITMAP(lunzerobits, MAX_EXT_TARGETS); |
edd16368 | 3960 | |
cfe5badc | 3961 | currentsd = kzalloc(sizeof(*currentsd) * HPSA_MAX_DEVICES, GFP_KERNEL); |
92084715 SC |
3962 | physdev_list = kzalloc(sizeof(*physdev_list), GFP_KERNEL); |
3963 | logdev_list = kzalloc(sizeof(*logdev_list), GFP_KERNEL); | |
edd16368 | 3964 | tmpdevice = kzalloc(sizeof(*tmpdevice), GFP_KERNEL); |
03383736 | 3965 | id_phys = kzalloc(sizeof(*id_phys), GFP_KERNEL); |
66749d0d | 3966 | id_ctlr = kzalloc(sizeof(*id_ctlr), GFP_KERNEL); |
edd16368 | 3967 | |
03383736 | 3968 | if (!currentsd || !physdev_list || !logdev_list || |
66749d0d | 3969 | !tmpdevice || !id_phys || !id_ctlr) { |
edd16368 SC |
3970 | dev_err(&h->pdev->dev, "out of memory\n"); |
3971 | goto out; | |
3972 | } | |
3973 | memset(lunzerobits, 0, sizeof(lunzerobits)); | |
3974 | ||
853633e8 DB |
3975 | h->drv_req_rescan = 0; /* cancel scheduled rescan - we're doing it. */ |
3976 | ||
03383736 | 3977 | if (hpsa_gather_lun_info(h, physdev_list, &nphysicals, |
853633e8 DB |
3978 | logdev_list, &nlogicals)) { |
3979 | h->drv_req_rescan = 1; | |
edd16368 | 3980 | goto out; |
853633e8 | 3981 | } |
edd16368 | 3982 | |
66749d0d ST |
3983 | /* Set number of local logicals (non PTRAID) */ |
3984 | if (hpsa_set_local_logical_count(h, id_ctlr, &nlocal_logicals)) { | |
3985 | dev_warn(&h->pdev->dev, | |
3986 | "%s: Can't determine number of local logical devices.\n", | |
3987 | __func__); | |
3988 | } | |
edd16368 | 3989 | |
aca4a520 ST |
3990 | /* We might see up to the maximum number of logical and physical disks |
3991 | * plus external target devices, and a device for the local RAID | |
3992 | * controller. | |
edd16368 | 3993 | */ |
aca4a520 | 3994 | ndevs_to_allocate = nphysicals + nlogicals + MAX_EXT_TARGETS + 1; |
edd16368 SC |
3995 | |
3996 | /* Allocate the per device structures */ | |
3997 | for (i = 0; i < ndevs_to_allocate; i++) { | |
b7ec021f ST |
3998 | if (i >= HPSA_MAX_DEVICES) { |
3999 | dev_warn(&h->pdev->dev, "maximum devices (%d) exceeded." | |
4000 | " %d devices ignored.\n", HPSA_MAX_DEVICES, | |
4001 | ndevs_to_allocate - HPSA_MAX_DEVICES); | |
4002 | break; | |
4003 | } | |
4004 | ||
edd16368 SC |
4005 | currentsd[i] = kzalloc(sizeof(*currentsd[i]), GFP_KERNEL); |
4006 | if (!currentsd[i]) { | |
4007 | dev_warn(&h->pdev->dev, "out of memory at %s:%d\n", | |
4008 | __FILE__, __LINE__); | |
853633e8 | 4009 | h->drv_req_rescan = 1; |
edd16368 SC |
4010 | goto out; |
4011 | } | |
4012 | ndev_allocated++; | |
4013 | } | |
4014 | ||
8645291b | 4015 | if (is_scsi_rev_5(h)) |
339b2b14 SC |
4016 | raid_ctlr_position = 0; |
4017 | else | |
4018 | raid_ctlr_position = nphysicals + nlogicals; | |
4019 | ||
edd16368 | 4020 | /* adjust our table of devices */ |
4f4eb9f1 | 4021 | n_ext_target_devs = 0; |
edd16368 | 4022 | for (i = 0; i < nphysicals + nlogicals + 1; i++) { |
0b0e1d6c | 4023 | u8 *lunaddrbytes, is_OBDR = 0; |
683fc444 | 4024 | int rc = 0; |
f2039b03 | 4025 | int phys_dev_index = i - (raid_ctlr_position == 0); |
edd16368 | 4026 | |
04fa2f44 | 4027 | physical_device = i < nphysicals + (raid_ctlr_position == 0); |
edd16368 SC |
4028 | |
4029 | /* Figure out where the LUN ID info is coming from */ | |
339b2b14 SC |
4030 | lunaddrbytes = figure_lunaddrbytes(h, raid_ctlr_position, |
4031 | i, nphysicals, nlogicals, physdev_list, logdev_list); | |
41ce4c35 SC |
4032 | |
4033 | /* skip masked non-disk devices */ | |
04fa2f44 KB |
4034 | if (MASKED_DEVICE(lunaddrbytes) && physical_device && |
4035 | (physdev_list->LUN[phys_dev_index].device_flags & 0x01)) | |
4036 | continue; | |
edd16368 SC |
4037 | |
4038 | /* Get device type, vendor, model, device id */ | |
683fc444 DB |
4039 | rc = hpsa_update_device_info(h, lunaddrbytes, tmpdevice, |
4040 | &is_OBDR); | |
4041 | if (rc == -ENOMEM) { | |
4042 | dev_warn(&h->pdev->dev, | |
4043 | "Out of memory, rescan deferred.\n"); | |
853633e8 | 4044 | h->drv_req_rescan = 1; |
683fc444 | 4045 | goto out; |
853633e8 | 4046 | } |
683fc444 DB |
4047 | if (rc) { |
4048 | dev_warn(&h->pdev->dev, | |
4049 | "Inquiry failed, skipping device.\n"); | |
4050 | continue; | |
4051 | } | |
4052 | ||
66749d0d ST |
4053 | /* Determine if this is a lun from an external target array */ |
4054 | tmpdevice->external = | |
4055 | figure_external_status(h, raid_ctlr_position, i, | |
4056 | nphysicals, nlocal_logicals); | |
4057 | ||
1f310bde | 4058 | figure_bus_target_lun(h, lunaddrbytes, tmpdevice); |
9b5c48c2 | 4059 | hpsa_update_device_supports_aborts(h, tmpdevice, lunaddrbytes); |
edd16368 SC |
4060 | this_device = currentsd[ncurrent]; |
4061 | ||
34592254 ST |
4062 | /* Turn on discovery_polling if there are ext target devices. |
4063 | * Event-based change notification is unreliable for those. | |
edd16368 | 4064 | */ |
34592254 ST |
4065 | if (!h->discovery_polling) { |
4066 | if (tmpdevice->external) { | |
4067 | h->discovery_polling = 1; | |
4068 | dev_info(&h->pdev->dev, | |
4069 | "External target, activate discovery polling.\n"); | |
4070 | } | |
edd16368 SC |
4071 | } |
4072 | ||
34592254 | 4073 | |
edd16368 | 4074 | *this_device = *tmpdevice; |
04fa2f44 | 4075 | this_device->physical_device = physical_device; |
edd16368 | 4076 | |
04fa2f44 KB |
4077 | /* |
4078 | * Expose all devices except for physical devices that | |
4079 | * are masked. | |
4080 | */ | |
4081 | if (MASKED_DEVICE(lunaddrbytes) && this_device->physical_device) | |
2a168208 KB |
4082 | this_device->expose_device = 0; |
4083 | else | |
4084 | this_device->expose_device = 1; | |
41ce4c35 | 4085 | |
d04e62b9 KB |
4086 | |
4087 | /* | |
4088 | * Get the SAS address for physical devices that are exposed. | |
4089 | */ | |
4090 | if (this_device->physical_device && this_device->expose_device) | |
4091 | hpsa_get_sas_address(h, lunaddrbytes, this_device); | |
41ce4c35 | 4092 | |
edd16368 | 4093 | switch (this_device->devtype) { |
0b0e1d6c | 4094 | case TYPE_ROM: |
edd16368 SC |
4095 | /* We don't *really* support actual CD-ROM devices, |
4096 | * just "One Button Disaster Recovery" tape drive | |
4097 | * which temporarily pretends to be a CD-ROM drive. | |
4098 | * So we check that the device is really an OBDR tape | |
4099 | * device by checking for "$DR-10" in bytes 43-48 of | |
4100 | * the inquiry data. | |
4101 | */ | |
0b0e1d6c SC |
4102 | if (is_OBDR) |
4103 | ncurrent++; | |
edd16368 SC |
4104 | break; |
4105 | case TYPE_DISK: | |
04fa2f44 | 4106 | if (this_device->physical_device) { |
b9092b79 KB |
4107 | /* The disk is in HBA mode. */ |
4108 | /* Never use RAID mapper in HBA mode. */ | |
ecf418d1 | 4109 | this_device->offload_enabled = 0; |
b9092b79 | 4110 | hpsa_get_ioaccel_drive_info(h, this_device, |
f2039b03 DB |
4111 | physdev_list, phys_dev_index, id_phys); |
4112 | hpsa_get_path_info(this_device, | |
4113 | physdev_list, phys_dev_index, id_phys); | |
b9092b79 | 4114 | } |
ecf418d1 | 4115 | ncurrent++; |
edd16368 SC |
4116 | break; |
4117 | case TYPE_TAPE: | |
4118 | case TYPE_MEDIUM_CHANGER: | |
41ce4c35 | 4119 | case TYPE_ENCLOSURE: |
b9092b79 | 4120 | ncurrent++; |
41ce4c35 | 4121 | break; |
edd16368 SC |
4122 | case TYPE_RAID: |
4123 | /* Only present the Smartarray HBA as a RAID controller. | |
4124 | * If it's a RAID controller other than the HBA itself | |
4125 | * (an external RAID controller, MSA500 or similar) | |
4126 | * don't present it. | |
4127 | */ | |
4128 | if (!is_hba_lunid(lunaddrbytes)) | |
4129 | break; | |
4130 | ncurrent++; | |
4131 | break; | |
4132 | default: | |
4133 | break; | |
4134 | } | |
cfe5badc | 4135 | if (ncurrent >= HPSA_MAX_DEVICES) |
edd16368 SC |
4136 | break; |
4137 | } | |
d04e62b9 KB |
4138 | |
4139 | if (h->sas_host == NULL) { | |
4140 | int rc = 0; | |
4141 | ||
4142 | rc = hpsa_add_sas_host(h); | |
4143 | if (rc) { | |
4144 | dev_warn(&h->pdev->dev, | |
4145 | "Could not add sas host %d\n", rc); | |
4146 | goto out; | |
4147 | } | |
4148 | } | |
4149 | ||
8aa60681 | 4150 | adjust_hpsa_scsi_table(h, currentsd, ncurrent); |
edd16368 SC |
4151 | out: |
4152 | kfree(tmpdevice); | |
4153 | for (i = 0; i < ndev_allocated; i++) | |
4154 | kfree(currentsd[i]); | |
4155 | kfree(currentsd); | |
edd16368 SC |
4156 | kfree(physdev_list); |
4157 | kfree(logdev_list); | |
66749d0d | 4158 | kfree(id_ctlr); |
03383736 | 4159 | kfree(id_phys); |
edd16368 SC |
4160 | } |
4161 | ||
ec5cbf04 WS |
4162 | static void hpsa_set_sg_descriptor(struct SGDescriptor *desc, |
4163 | struct scatterlist *sg) | |
4164 | { | |
4165 | u64 addr64 = (u64) sg_dma_address(sg); | |
4166 | unsigned int len = sg_dma_len(sg); | |
4167 | ||
4168 | desc->Addr = cpu_to_le64(addr64); | |
4169 | desc->Len = cpu_to_le32(len); | |
4170 | desc->Ext = 0; | |
4171 | } | |
4172 | ||
c7ee65b3 WS |
4173 | /* |
4174 | * hpsa_scatter_gather takes a struct scsi_cmnd, (cmd), and does the pci | |
edd16368 SC |
4175 | * dma mapping and fills in the scatter gather entries of the |
4176 | * hpsa command, cp. | |
4177 | */ | |
33a2ffce | 4178 | static int hpsa_scatter_gather(struct ctlr_info *h, |
edd16368 SC |
4179 | struct CommandList *cp, |
4180 | struct scsi_cmnd *cmd) | |
4181 | { | |
edd16368 | 4182 | struct scatterlist *sg; |
b3a7ba7c | 4183 | int use_sg, i, sg_limit, chained, last_sg; |
33a2ffce | 4184 | struct SGDescriptor *curr_sg; |
edd16368 | 4185 | |
33a2ffce | 4186 | BUG_ON(scsi_sg_count(cmd) > h->maxsgentries); |
edd16368 SC |
4187 | |
4188 | use_sg = scsi_dma_map(cmd); | |
4189 | if (use_sg < 0) | |
4190 | return use_sg; | |
4191 | ||
4192 | if (!use_sg) | |
4193 | goto sglist_finished; | |
4194 | ||
b3a7ba7c WS |
4195 | /* |
4196 | * If the number of entries is greater than the max for a single list, | |
4197 | * then we have a chained list; we will set up all but one entry in the | |
4198 | * first list (the last entry is saved for link information); | |
4199 | * otherwise, we don't have a chained list and we'll set up at each of | |
4200 | * the entries in the one list. | |
4201 | */ | |
33a2ffce | 4202 | curr_sg = cp->SG; |
b3a7ba7c WS |
4203 | chained = use_sg > h->max_cmd_sg_entries; |
4204 | sg_limit = chained ? h->max_cmd_sg_entries - 1 : use_sg; | |
4205 | last_sg = scsi_sg_count(cmd) - 1; | |
4206 | scsi_for_each_sg(cmd, sg, sg_limit, i) { | |
ec5cbf04 | 4207 | hpsa_set_sg_descriptor(curr_sg, sg); |
33a2ffce SC |
4208 | curr_sg++; |
4209 | } | |
ec5cbf04 | 4210 | |
b3a7ba7c WS |
4211 | if (chained) { |
4212 | /* | |
4213 | * Continue with the chained list. Set curr_sg to the chained | |
4214 | * list. Modify the limit to the total count less the entries | |
4215 | * we've already set up. Resume the scan at the list entry | |
4216 | * where the previous loop left off. | |
4217 | */ | |
4218 | curr_sg = h->cmd_sg_list[cp->cmdindex]; | |
4219 | sg_limit = use_sg - sg_limit; | |
4220 | for_each_sg(sg, sg, sg_limit, i) { | |
4221 | hpsa_set_sg_descriptor(curr_sg, sg); | |
4222 | curr_sg++; | |
4223 | } | |
4224 | } | |
4225 | ||
ec5cbf04 | 4226 | /* Back the pointer up to the last entry and mark it as "last". */ |
b3a7ba7c | 4227 | (curr_sg - 1)->Ext = cpu_to_le32(HPSA_SG_LAST); |
33a2ffce SC |
4228 | |
4229 | if (use_sg + chained > h->maxSG) | |
4230 | h->maxSG = use_sg + chained; | |
4231 | ||
4232 | if (chained) { | |
4233 | cp->Header.SGList = h->max_cmd_sg_entries; | |
50a0decf | 4234 | cp->Header.SGTotal = cpu_to_le16(use_sg + 1); |
e2bea6df SC |
4235 | if (hpsa_map_sg_chain_block(h, cp)) { |
4236 | scsi_dma_unmap(cmd); | |
4237 | return -1; | |
4238 | } | |
33a2ffce | 4239 | return 0; |
edd16368 SC |
4240 | } |
4241 | ||
4242 | sglist_finished: | |
4243 | ||
01a02ffc | 4244 | cp->Header.SGList = (u8) use_sg; /* no. SGs contig in this cmd */ |
c7ee65b3 | 4245 | cp->Header.SGTotal = cpu_to_le16(use_sg); /* total sgs in cmd list */ |
edd16368 SC |
4246 | return 0; |
4247 | } | |
4248 | ||
283b4a9b SC |
4249 | #define IO_ACCEL_INELIGIBLE (1) |
4250 | static int fixup_ioaccel_cdb(u8 *cdb, int *cdb_len) | |
4251 | { | |
4252 | int is_write = 0; | |
4253 | u32 block; | |
4254 | u32 block_cnt; | |
4255 | ||
4256 | /* Perform some CDB fixups if needed using 10 byte reads/writes only */ | |
4257 | switch (cdb[0]) { | |
4258 | case WRITE_6: | |
4259 | case WRITE_12: | |
4260 | is_write = 1; | |
4261 | case READ_6: | |
4262 | case READ_12: | |
4263 | if (*cdb_len == 6) { | |
c8a6c9a6 | 4264 | block = get_unaligned_be16(&cdb[2]); |
283b4a9b | 4265 | block_cnt = cdb[4]; |
c8a6c9a6 DB |
4266 | if (block_cnt == 0) |
4267 | block_cnt = 256; | |
283b4a9b SC |
4268 | } else { |
4269 | BUG_ON(*cdb_len != 12); | |
c8a6c9a6 DB |
4270 | block = get_unaligned_be32(&cdb[2]); |
4271 | block_cnt = get_unaligned_be32(&cdb[6]); | |
283b4a9b SC |
4272 | } |
4273 | if (block_cnt > 0xffff) | |
4274 | return IO_ACCEL_INELIGIBLE; | |
4275 | ||
4276 | cdb[0] = is_write ? WRITE_10 : READ_10; | |
4277 | cdb[1] = 0; | |
4278 | cdb[2] = (u8) (block >> 24); | |
4279 | cdb[3] = (u8) (block >> 16); | |
4280 | cdb[4] = (u8) (block >> 8); | |
4281 | cdb[5] = (u8) (block); | |
4282 | cdb[6] = 0; | |
4283 | cdb[7] = (u8) (block_cnt >> 8); | |
4284 | cdb[8] = (u8) (block_cnt); | |
4285 | cdb[9] = 0; | |
4286 | *cdb_len = 10; | |
4287 | break; | |
4288 | } | |
4289 | return 0; | |
4290 | } | |
4291 | ||
c349775e | 4292 | static int hpsa_scsi_ioaccel1_queue_command(struct ctlr_info *h, |
283b4a9b | 4293 | struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len, |
03383736 | 4294 | u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk) |
e1f7de0c MG |
4295 | { |
4296 | struct scsi_cmnd *cmd = c->scsi_cmd; | |
e1f7de0c MG |
4297 | struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex]; |
4298 | unsigned int len; | |
4299 | unsigned int total_len = 0; | |
4300 | struct scatterlist *sg; | |
4301 | u64 addr64; | |
4302 | int use_sg, i; | |
4303 | struct SGDescriptor *curr_sg; | |
4304 | u32 control = IOACCEL1_CONTROL_SIMPLEQUEUE; | |
4305 | ||
283b4a9b | 4306 | /* TODO: implement chaining support */ |
03383736 DB |
4307 | if (scsi_sg_count(cmd) > h->ioaccel_maxsg) { |
4308 | atomic_dec(&phys_disk->ioaccel_cmds_out); | |
283b4a9b | 4309 | return IO_ACCEL_INELIGIBLE; |
03383736 | 4310 | } |
283b4a9b | 4311 | |
e1f7de0c MG |
4312 | BUG_ON(cmd->cmd_len > IOACCEL1_IOFLAGS_CDBLEN_MAX); |
4313 | ||
03383736 DB |
4314 | if (fixup_ioaccel_cdb(cdb, &cdb_len)) { |
4315 | atomic_dec(&phys_disk->ioaccel_cmds_out); | |
283b4a9b | 4316 | return IO_ACCEL_INELIGIBLE; |
03383736 | 4317 | } |
283b4a9b | 4318 | |
e1f7de0c MG |
4319 | c->cmd_type = CMD_IOACCEL1; |
4320 | ||
4321 | /* Adjust the DMA address to point to the accelerated command buffer */ | |
4322 | c->busaddr = (u32) h->ioaccel_cmd_pool_dhandle + | |
4323 | (c->cmdindex * sizeof(*cp)); | |
4324 | BUG_ON(c->busaddr & 0x0000007F); | |
4325 | ||
4326 | use_sg = scsi_dma_map(cmd); | |
03383736 DB |
4327 | if (use_sg < 0) { |
4328 | atomic_dec(&phys_disk->ioaccel_cmds_out); | |
e1f7de0c | 4329 | return use_sg; |
03383736 | 4330 | } |
e1f7de0c MG |
4331 | |
4332 | if (use_sg) { | |
4333 | curr_sg = cp->SG; | |
4334 | scsi_for_each_sg(cmd, sg, use_sg, i) { | |
4335 | addr64 = (u64) sg_dma_address(sg); | |
4336 | len = sg_dma_len(sg); | |
4337 | total_len += len; | |
50a0decf SC |
4338 | curr_sg->Addr = cpu_to_le64(addr64); |
4339 | curr_sg->Len = cpu_to_le32(len); | |
4340 | curr_sg->Ext = cpu_to_le32(0); | |
e1f7de0c MG |
4341 | curr_sg++; |
4342 | } | |
50a0decf | 4343 | (--curr_sg)->Ext = cpu_to_le32(HPSA_SG_LAST); |
e1f7de0c MG |
4344 | |
4345 | switch (cmd->sc_data_direction) { | |
4346 | case DMA_TO_DEVICE: | |
4347 | control |= IOACCEL1_CONTROL_DATA_OUT; | |
4348 | break; | |
4349 | case DMA_FROM_DEVICE: | |
4350 | control |= IOACCEL1_CONTROL_DATA_IN; | |
4351 | break; | |
4352 | case DMA_NONE: | |
4353 | control |= IOACCEL1_CONTROL_NODATAXFER; | |
4354 | break; | |
4355 | default: | |
4356 | dev_err(&h->pdev->dev, "unknown data direction: %d\n", | |
4357 | cmd->sc_data_direction); | |
4358 | BUG(); | |
4359 | break; | |
4360 | } | |
4361 | } else { | |
4362 | control |= IOACCEL1_CONTROL_NODATAXFER; | |
4363 | } | |
4364 | ||
c349775e | 4365 | c->Header.SGList = use_sg; |
e1f7de0c | 4366 | /* Fill out the command structure to submit */ |
2b08b3e9 DB |
4367 | cp->dev_handle = cpu_to_le16(ioaccel_handle & 0xFFFF); |
4368 | cp->transfer_len = cpu_to_le32(total_len); | |
4369 | cp->io_flags = cpu_to_le16(IOACCEL1_IOFLAGS_IO_REQ | | |
4370 | (cdb_len & IOACCEL1_IOFLAGS_CDBLEN_MASK)); | |
4371 | cp->control = cpu_to_le32(control); | |
283b4a9b SC |
4372 | memcpy(cp->CDB, cdb, cdb_len); |
4373 | memcpy(cp->CISS_LUN, scsi3addr, 8); | |
c349775e | 4374 | /* Tag was already set at init time. */ |
283b4a9b | 4375 | enqueue_cmd_and_start_io(h, c); |
e1f7de0c MG |
4376 | return 0; |
4377 | } | |
edd16368 | 4378 | |
283b4a9b SC |
4379 | /* |
4380 | * Queue a command directly to a device behind the controller using the | |
4381 | * I/O accelerator path. | |
4382 | */ | |
4383 | static int hpsa_scsi_ioaccel_direct_map(struct ctlr_info *h, | |
4384 | struct CommandList *c) | |
4385 | { | |
4386 | struct scsi_cmnd *cmd = c->scsi_cmd; | |
4387 | struct hpsa_scsi_dev_t *dev = cmd->device->hostdata; | |
4388 | ||
03383736 DB |
4389 | c->phys_disk = dev; |
4390 | ||
283b4a9b | 4391 | return hpsa_scsi_ioaccel_queue_command(h, c, dev->ioaccel_handle, |
03383736 | 4392 | cmd->cmnd, cmd->cmd_len, dev->scsi3addr, dev); |
283b4a9b SC |
4393 | } |
4394 | ||
dd0e19f3 ST |
4395 | /* |
4396 | * Set encryption parameters for the ioaccel2 request | |
4397 | */ | |
4398 | static void set_encrypt_ioaccel2(struct ctlr_info *h, | |
4399 | struct CommandList *c, struct io_accel2_cmd *cp) | |
4400 | { | |
4401 | struct scsi_cmnd *cmd = c->scsi_cmd; | |
4402 | struct hpsa_scsi_dev_t *dev = cmd->device->hostdata; | |
4403 | struct raid_map_data *map = &dev->raid_map; | |
4404 | u64 first_block; | |
4405 | ||
dd0e19f3 | 4406 | /* Are we doing encryption on this device */ |
2b08b3e9 | 4407 | if (!(le16_to_cpu(map->flags) & RAID_MAP_FLAG_ENCRYPT_ON)) |
dd0e19f3 ST |
4408 | return; |
4409 | /* Set the data encryption key index. */ | |
4410 | cp->dekindex = map->dekindex; | |
4411 | ||
4412 | /* Set the encryption enable flag, encoded into direction field. */ | |
4413 | cp->direction |= IOACCEL2_DIRECTION_ENCRYPT_MASK; | |
4414 | ||
4415 | /* Set encryption tweak values based on logical block address | |
4416 | * If block size is 512, tweak value is LBA. | |
4417 | * For other block sizes, tweak is (LBA * block size)/ 512) | |
4418 | */ | |
4419 | switch (cmd->cmnd[0]) { | |
4420 | /* Required? 6-byte cdbs eliminated by fixup_ioaccel_cdb */ | |
4421 | case WRITE_6: | |
4422 | case READ_6: | |
2b08b3e9 | 4423 | first_block = get_unaligned_be16(&cmd->cmnd[2]); |
dd0e19f3 ST |
4424 | break; |
4425 | case WRITE_10: | |
4426 | case READ_10: | |
dd0e19f3 ST |
4427 | /* Required? 12-byte cdbs eliminated by fixup_ioaccel_cdb */ |
4428 | case WRITE_12: | |
4429 | case READ_12: | |
2b08b3e9 | 4430 | first_block = get_unaligned_be32(&cmd->cmnd[2]); |
dd0e19f3 ST |
4431 | break; |
4432 | case WRITE_16: | |
4433 | case READ_16: | |
2b08b3e9 | 4434 | first_block = get_unaligned_be64(&cmd->cmnd[2]); |
dd0e19f3 ST |
4435 | break; |
4436 | default: | |
4437 | dev_err(&h->pdev->dev, | |
2b08b3e9 DB |
4438 | "ERROR: %s: size (0x%x) not supported for encryption\n", |
4439 | __func__, cmd->cmnd[0]); | |
dd0e19f3 ST |
4440 | BUG(); |
4441 | break; | |
4442 | } | |
2b08b3e9 DB |
4443 | |
4444 | if (le32_to_cpu(map->volume_blk_size) != 512) | |
4445 | first_block = first_block * | |
4446 | le32_to_cpu(map->volume_blk_size)/512; | |
4447 | ||
4448 | cp->tweak_lower = cpu_to_le32(first_block); | |
4449 | cp->tweak_upper = cpu_to_le32(first_block >> 32); | |
dd0e19f3 ST |
4450 | } |
4451 | ||
c349775e ST |
4452 | static int hpsa_scsi_ioaccel2_queue_command(struct ctlr_info *h, |
4453 | struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len, | |
03383736 | 4454 | u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk) |
c349775e ST |
4455 | { |
4456 | struct scsi_cmnd *cmd = c->scsi_cmd; | |
4457 | struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex]; | |
4458 | struct ioaccel2_sg_element *curr_sg; | |
4459 | int use_sg, i; | |
4460 | struct scatterlist *sg; | |
4461 | u64 addr64; | |
4462 | u32 len; | |
4463 | u32 total_len = 0; | |
4464 | ||
d9a729f3 | 4465 | BUG_ON(scsi_sg_count(cmd) > h->maxsgentries); |
c349775e | 4466 | |
03383736 DB |
4467 | if (fixup_ioaccel_cdb(cdb, &cdb_len)) { |
4468 | atomic_dec(&phys_disk->ioaccel_cmds_out); | |
c349775e | 4469 | return IO_ACCEL_INELIGIBLE; |
03383736 DB |
4470 | } |
4471 | ||
c349775e ST |
4472 | c->cmd_type = CMD_IOACCEL2; |
4473 | /* Adjust the DMA address to point to the accelerated command buffer */ | |
4474 | c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle + | |
4475 | (c->cmdindex * sizeof(*cp)); | |
4476 | BUG_ON(c->busaddr & 0x0000007F); | |
4477 | ||
4478 | memset(cp, 0, sizeof(*cp)); | |
4479 | cp->IU_type = IOACCEL2_IU_TYPE; | |
4480 | ||
4481 | use_sg = scsi_dma_map(cmd); | |
03383736 DB |
4482 | if (use_sg < 0) { |
4483 | atomic_dec(&phys_disk->ioaccel_cmds_out); | |
c349775e | 4484 | return use_sg; |
03383736 | 4485 | } |
c349775e ST |
4486 | |
4487 | if (use_sg) { | |
c349775e | 4488 | curr_sg = cp->sg; |
d9a729f3 WS |
4489 | if (use_sg > h->ioaccel_maxsg) { |
4490 | addr64 = le64_to_cpu( | |
4491 | h->ioaccel2_cmd_sg_list[c->cmdindex]->address); | |
4492 | curr_sg->address = cpu_to_le64(addr64); | |
4493 | curr_sg->length = 0; | |
4494 | curr_sg->reserved[0] = 0; | |
4495 | curr_sg->reserved[1] = 0; | |
4496 | curr_sg->reserved[2] = 0; | |
4497 | curr_sg->chain_indicator = 0x80; | |
4498 | ||
4499 | curr_sg = h->ioaccel2_cmd_sg_list[c->cmdindex]; | |
4500 | } | |
c349775e ST |
4501 | scsi_for_each_sg(cmd, sg, use_sg, i) { |
4502 | addr64 = (u64) sg_dma_address(sg); | |
4503 | len = sg_dma_len(sg); | |
4504 | total_len += len; | |
4505 | curr_sg->address = cpu_to_le64(addr64); | |
4506 | curr_sg->length = cpu_to_le32(len); | |
4507 | curr_sg->reserved[0] = 0; | |
4508 | curr_sg->reserved[1] = 0; | |
4509 | curr_sg->reserved[2] = 0; | |
4510 | curr_sg->chain_indicator = 0; | |
4511 | curr_sg++; | |
4512 | } | |
4513 | ||
4514 | switch (cmd->sc_data_direction) { | |
4515 | case DMA_TO_DEVICE: | |
dd0e19f3 ST |
4516 | cp->direction &= ~IOACCEL2_DIRECTION_MASK; |
4517 | cp->direction |= IOACCEL2_DIR_DATA_OUT; | |
c349775e ST |
4518 | break; |
4519 | case DMA_FROM_DEVICE: | |
dd0e19f3 ST |
4520 | cp->direction &= ~IOACCEL2_DIRECTION_MASK; |
4521 | cp->direction |= IOACCEL2_DIR_DATA_IN; | |
c349775e ST |
4522 | break; |
4523 | case DMA_NONE: | |
dd0e19f3 ST |
4524 | cp->direction &= ~IOACCEL2_DIRECTION_MASK; |
4525 | cp->direction |= IOACCEL2_DIR_NO_DATA; | |
c349775e ST |
4526 | break; |
4527 | default: | |
4528 | dev_err(&h->pdev->dev, "unknown data direction: %d\n", | |
4529 | cmd->sc_data_direction); | |
4530 | BUG(); | |
4531 | break; | |
4532 | } | |
4533 | } else { | |
dd0e19f3 ST |
4534 | cp->direction &= ~IOACCEL2_DIRECTION_MASK; |
4535 | cp->direction |= IOACCEL2_DIR_NO_DATA; | |
c349775e | 4536 | } |
dd0e19f3 ST |
4537 | |
4538 | /* Set encryption parameters, if necessary */ | |
4539 | set_encrypt_ioaccel2(h, c, cp); | |
4540 | ||
2b08b3e9 | 4541 | cp->scsi_nexus = cpu_to_le32(ioaccel_handle); |
f2405db8 | 4542 | cp->Tag = cpu_to_le32(c->cmdindex << DIRECT_LOOKUP_SHIFT); |
c349775e | 4543 | memcpy(cp->cdb, cdb, sizeof(cp->cdb)); |
c349775e | 4544 | |
c349775e ST |
4545 | cp->data_len = cpu_to_le32(total_len); |
4546 | cp->err_ptr = cpu_to_le64(c->busaddr + | |
4547 | offsetof(struct io_accel2_cmd, error_data)); | |
50a0decf | 4548 | cp->err_len = cpu_to_le32(sizeof(cp->error_data)); |
c349775e | 4549 | |
d9a729f3 WS |
4550 | /* fill in sg elements */ |
4551 | if (use_sg > h->ioaccel_maxsg) { | |
4552 | cp->sg_count = 1; | |
a736e9b6 | 4553 | cp->sg[0].length = cpu_to_le32(use_sg * sizeof(cp->sg[0])); |
d9a729f3 WS |
4554 | if (hpsa_map_ioaccel2_sg_chain_block(h, cp, c)) { |
4555 | atomic_dec(&phys_disk->ioaccel_cmds_out); | |
4556 | scsi_dma_unmap(cmd); | |
4557 | return -1; | |
4558 | } | |
4559 | } else | |
4560 | cp->sg_count = (u8) use_sg; | |
4561 | ||
c349775e ST |
4562 | enqueue_cmd_and_start_io(h, c); |
4563 | return 0; | |
4564 | } | |
4565 | ||
4566 | /* | |
4567 | * Queue a command to the correct I/O accelerator path. | |
4568 | */ | |
4569 | static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h, | |
4570 | struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len, | |
03383736 | 4571 | u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk) |
c349775e | 4572 | { |
03383736 DB |
4573 | /* Try to honor the device's queue depth */ |
4574 | if (atomic_inc_return(&phys_disk->ioaccel_cmds_out) > | |
4575 | phys_disk->queue_depth) { | |
4576 | atomic_dec(&phys_disk->ioaccel_cmds_out); | |
4577 | return IO_ACCEL_INELIGIBLE; | |
4578 | } | |
c349775e ST |
4579 | if (h->transMethod & CFGTBL_Trans_io_accel1) |
4580 | return hpsa_scsi_ioaccel1_queue_command(h, c, ioaccel_handle, | |
03383736 DB |
4581 | cdb, cdb_len, scsi3addr, |
4582 | phys_disk); | |
c349775e ST |
4583 | else |
4584 | return hpsa_scsi_ioaccel2_queue_command(h, c, ioaccel_handle, | |
03383736 DB |
4585 | cdb, cdb_len, scsi3addr, |
4586 | phys_disk); | |
c349775e ST |
4587 | } |
4588 | ||
6b80b18f ST |
4589 | static void raid_map_helper(struct raid_map_data *map, |
4590 | int offload_to_mirror, u32 *map_index, u32 *current_group) | |
4591 | { | |
4592 | if (offload_to_mirror == 0) { | |
4593 | /* use physical disk in the first mirrored group. */ | |
2b08b3e9 | 4594 | *map_index %= le16_to_cpu(map->data_disks_per_row); |
6b80b18f ST |
4595 | return; |
4596 | } | |
4597 | do { | |
4598 | /* determine mirror group that *map_index indicates */ | |
2b08b3e9 DB |
4599 | *current_group = *map_index / |
4600 | le16_to_cpu(map->data_disks_per_row); | |
6b80b18f ST |
4601 | if (offload_to_mirror == *current_group) |
4602 | continue; | |
2b08b3e9 | 4603 | if (*current_group < le16_to_cpu(map->layout_map_count) - 1) { |
6b80b18f | 4604 | /* select map index from next group */ |
2b08b3e9 | 4605 | *map_index += le16_to_cpu(map->data_disks_per_row); |
6b80b18f ST |
4606 | (*current_group)++; |
4607 | } else { | |
4608 | /* select map index from first group */ | |
2b08b3e9 | 4609 | *map_index %= le16_to_cpu(map->data_disks_per_row); |
6b80b18f ST |
4610 | *current_group = 0; |
4611 | } | |
4612 | } while (offload_to_mirror != *current_group); | |
4613 | } | |
4614 | ||
283b4a9b SC |
4615 | /* |
4616 | * Attempt to perform offload RAID mapping for a logical volume I/O. | |
4617 | */ | |
4618 | static int hpsa_scsi_ioaccel_raid_map(struct ctlr_info *h, | |
4619 | struct CommandList *c) | |
4620 | { | |
4621 | struct scsi_cmnd *cmd = c->scsi_cmd; | |
4622 | struct hpsa_scsi_dev_t *dev = cmd->device->hostdata; | |
4623 | struct raid_map_data *map = &dev->raid_map; | |
4624 | struct raid_map_disk_data *dd = &map->data[0]; | |
4625 | int is_write = 0; | |
4626 | u32 map_index; | |
4627 | u64 first_block, last_block; | |
4628 | u32 block_cnt; | |
4629 | u32 blocks_per_row; | |
4630 | u64 first_row, last_row; | |
4631 | u32 first_row_offset, last_row_offset; | |
4632 | u32 first_column, last_column; | |
6b80b18f ST |
4633 | u64 r0_first_row, r0_last_row; |
4634 | u32 r5or6_blocks_per_row; | |
4635 | u64 r5or6_first_row, r5or6_last_row; | |
4636 | u32 r5or6_first_row_offset, r5or6_last_row_offset; | |
4637 | u32 r5or6_first_column, r5or6_last_column; | |
4638 | u32 total_disks_per_row; | |
4639 | u32 stripesize; | |
4640 | u32 first_group, last_group, current_group; | |
283b4a9b SC |
4641 | u32 map_row; |
4642 | u32 disk_handle; | |
4643 | u64 disk_block; | |
4644 | u32 disk_block_cnt; | |
4645 | u8 cdb[16]; | |
4646 | u8 cdb_len; | |
2b08b3e9 | 4647 | u16 strip_size; |
283b4a9b SC |
4648 | #if BITS_PER_LONG == 32 |
4649 | u64 tmpdiv; | |
4650 | #endif | |
6b80b18f | 4651 | int offload_to_mirror; |
283b4a9b | 4652 | |
283b4a9b SC |
4653 | /* check for valid opcode, get LBA and block count */ |
4654 | switch (cmd->cmnd[0]) { | |
4655 | case WRITE_6: | |
4656 | is_write = 1; | |
4657 | case READ_6: | |
c8a6c9a6 | 4658 | first_block = get_unaligned_be16(&cmd->cmnd[2]); |
283b4a9b | 4659 | block_cnt = cmd->cmnd[4]; |
3fa89a04 SC |
4660 | if (block_cnt == 0) |
4661 | block_cnt = 256; | |
283b4a9b SC |
4662 | break; |
4663 | case WRITE_10: | |
4664 | is_write = 1; | |
4665 | case READ_10: | |
4666 | first_block = | |
4667 | (((u64) cmd->cmnd[2]) << 24) | | |
4668 | (((u64) cmd->cmnd[3]) << 16) | | |
4669 | (((u64) cmd->cmnd[4]) << 8) | | |
4670 | cmd->cmnd[5]; | |
4671 | block_cnt = | |
4672 | (((u32) cmd->cmnd[7]) << 8) | | |
4673 | cmd->cmnd[8]; | |
4674 | break; | |
4675 | case WRITE_12: | |
4676 | is_write = 1; | |
4677 | case READ_12: | |
4678 | first_block = | |
4679 | (((u64) cmd->cmnd[2]) << 24) | | |
4680 | (((u64) cmd->cmnd[3]) << 16) | | |
4681 | (((u64) cmd->cmnd[4]) << 8) | | |
4682 | cmd->cmnd[5]; | |
4683 | block_cnt = | |
4684 | (((u32) cmd->cmnd[6]) << 24) | | |
4685 | (((u32) cmd->cmnd[7]) << 16) | | |
4686 | (((u32) cmd->cmnd[8]) << 8) | | |
4687 | cmd->cmnd[9]; | |
4688 | break; | |
4689 | case WRITE_16: | |
4690 | is_write = 1; | |
4691 | case READ_16: | |
4692 | first_block = | |
4693 | (((u64) cmd->cmnd[2]) << 56) | | |
4694 | (((u64) cmd->cmnd[3]) << 48) | | |
4695 | (((u64) cmd->cmnd[4]) << 40) | | |
4696 | (((u64) cmd->cmnd[5]) << 32) | | |
4697 | (((u64) cmd->cmnd[6]) << 24) | | |
4698 | (((u64) cmd->cmnd[7]) << 16) | | |
4699 | (((u64) cmd->cmnd[8]) << 8) | | |
4700 | cmd->cmnd[9]; | |
4701 | block_cnt = | |
4702 | (((u32) cmd->cmnd[10]) << 24) | | |
4703 | (((u32) cmd->cmnd[11]) << 16) | | |
4704 | (((u32) cmd->cmnd[12]) << 8) | | |
4705 | cmd->cmnd[13]; | |
4706 | break; | |
4707 | default: | |
4708 | return IO_ACCEL_INELIGIBLE; /* process via normal I/O path */ | |
4709 | } | |
283b4a9b SC |
4710 | last_block = first_block + block_cnt - 1; |
4711 | ||
4712 | /* check for write to non-RAID-0 */ | |
4713 | if (is_write && dev->raid_level != 0) | |
4714 | return IO_ACCEL_INELIGIBLE; | |
4715 | ||
4716 | /* check for invalid block or wraparound */ | |
2b08b3e9 DB |
4717 | if (last_block >= le64_to_cpu(map->volume_blk_cnt) || |
4718 | last_block < first_block) | |
283b4a9b SC |
4719 | return IO_ACCEL_INELIGIBLE; |
4720 | ||
4721 | /* calculate stripe information for the request */ | |
2b08b3e9 DB |
4722 | blocks_per_row = le16_to_cpu(map->data_disks_per_row) * |
4723 | le16_to_cpu(map->strip_size); | |
4724 | strip_size = le16_to_cpu(map->strip_size); | |
283b4a9b SC |
4725 | #if BITS_PER_LONG == 32 |
4726 | tmpdiv = first_block; | |
4727 | (void) do_div(tmpdiv, blocks_per_row); | |
4728 | first_row = tmpdiv; | |
4729 | tmpdiv = last_block; | |
4730 | (void) do_div(tmpdiv, blocks_per_row); | |
4731 | last_row = tmpdiv; | |
4732 | first_row_offset = (u32) (first_block - (first_row * blocks_per_row)); | |
4733 | last_row_offset = (u32) (last_block - (last_row * blocks_per_row)); | |
4734 | tmpdiv = first_row_offset; | |
2b08b3e9 | 4735 | (void) do_div(tmpdiv, strip_size); |
283b4a9b SC |
4736 | first_column = tmpdiv; |
4737 | tmpdiv = last_row_offset; | |
2b08b3e9 | 4738 | (void) do_div(tmpdiv, strip_size); |
283b4a9b SC |
4739 | last_column = tmpdiv; |
4740 | #else | |
4741 | first_row = first_block / blocks_per_row; | |
4742 | last_row = last_block / blocks_per_row; | |
4743 | first_row_offset = (u32) (first_block - (first_row * blocks_per_row)); | |
4744 | last_row_offset = (u32) (last_block - (last_row * blocks_per_row)); | |
2b08b3e9 DB |
4745 | first_column = first_row_offset / strip_size; |
4746 | last_column = last_row_offset / strip_size; | |
283b4a9b SC |
4747 | #endif |
4748 | ||
4749 | /* if this isn't a single row/column then give to the controller */ | |
4750 | if ((first_row != last_row) || (first_column != last_column)) | |
4751 | return IO_ACCEL_INELIGIBLE; | |
4752 | ||
4753 | /* proceeding with driver mapping */ | |
2b08b3e9 DB |
4754 | total_disks_per_row = le16_to_cpu(map->data_disks_per_row) + |
4755 | le16_to_cpu(map->metadata_disks_per_row); | |
283b4a9b | 4756 | map_row = ((u32)(first_row >> map->parity_rotation_shift)) % |
2b08b3e9 | 4757 | le16_to_cpu(map->row_cnt); |
6b80b18f ST |
4758 | map_index = (map_row * total_disks_per_row) + first_column; |
4759 | ||
4760 | switch (dev->raid_level) { | |
4761 | case HPSA_RAID_0: | |
4762 | break; /* nothing special to do */ | |
4763 | case HPSA_RAID_1: | |
4764 | /* Handles load balance across RAID 1 members. | |
4765 | * (2-drive R1 and R10 with even # of drives.) | |
4766 | * Appropriate for SSDs, not optimal for HDDs | |
283b4a9b | 4767 | */ |
2b08b3e9 | 4768 | BUG_ON(le16_to_cpu(map->layout_map_count) != 2); |
283b4a9b | 4769 | if (dev->offload_to_mirror) |
2b08b3e9 | 4770 | map_index += le16_to_cpu(map->data_disks_per_row); |
283b4a9b | 4771 | dev->offload_to_mirror = !dev->offload_to_mirror; |
6b80b18f ST |
4772 | break; |
4773 | case HPSA_RAID_ADM: | |
4774 | /* Handles N-way mirrors (R1-ADM) | |
4775 | * and R10 with # of drives divisible by 3.) | |
4776 | */ | |
2b08b3e9 | 4777 | BUG_ON(le16_to_cpu(map->layout_map_count) != 3); |
6b80b18f ST |
4778 | |
4779 | offload_to_mirror = dev->offload_to_mirror; | |
4780 | raid_map_helper(map, offload_to_mirror, | |
4781 | &map_index, ¤t_group); | |
4782 | /* set mirror group to use next time */ | |
4783 | offload_to_mirror = | |
2b08b3e9 DB |
4784 | (offload_to_mirror >= |
4785 | le16_to_cpu(map->layout_map_count) - 1) | |
6b80b18f | 4786 | ? 0 : offload_to_mirror + 1; |
6b80b18f ST |
4787 | dev->offload_to_mirror = offload_to_mirror; |
4788 | /* Avoid direct use of dev->offload_to_mirror within this | |
4789 | * function since multiple threads might simultaneously | |
4790 | * increment it beyond the range of dev->layout_map_count -1. | |
4791 | */ | |
4792 | break; | |
4793 | case HPSA_RAID_5: | |
4794 | case HPSA_RAID_6: | |
2b08b3e9 | 4795 | if (le16_to_cpu(map->layout_map_count) <= 1) |
6b80b18f ST |
4796 | break; |
4797 | ||
4798 | /* Verify first and last block are in same RAID group */ | |
4799 | r5or6_blocks_per_row = | |
2b08b3e9 DB |
4800 | le16_to_cpu(map->strip_size) * |
4801 | le16_to_cpu(map->data_disks_per_row); | |
6b80b18f | 4802 | BUG_ON(r5or6_blocks_per_row == 0); |
2b08b3e9 DB |
4803 | stripesize = r5or6_blocks_per_row * |
4804 | le16_to_cpu(map->layout_map_count); | |
6b80b18f ST |
4805 | #if BITS_PER_LONG == 32 |
4806 | tmpdiv = first_block; | |
4807 | first_group = do_div(tmpdiv, stripesize); | |
4808 | tmpdiv = first_group; | |
4809 | (void) do_div(tmpdiv, r5or6_blocks_per_row); | |
4810 | first_group = tmpdiv; | |
4811 | tmpdiv = last_block; | |
4812 | last_group = do_div(tmpdiv, stripesize); | |
4813 | tmpdiv = last_group; | |
4814 | (void) do_div(tmpdiv, r5or6_blocks_per_row); | |
4815 | last_group = tmpdiv; | |
4816 | #else | |
4817 | first_group = (first_block % stripesize) / r5or6_blocks_per_row; | |
4818 | last_group = (last_block % stripesize) / r5or6_blocks_per_row; | |
6b80b18f | 4819 | #endif |
000ff7c2 | 4820 | if (first_group != last_group) |
6b80b18f ST |
4821 | return IO_ACCEL_INELIGIBLE; |
4822 | ||
4823 | /* Verify request is in a single row of RAID 5/6 */ | |
4824 | #if BITS_PER_LONG == 32 | |
4825 | tmpdiv = first_block; | |
4826 | (void) do_div(tmpdiv, stripesize); | |
4827 | first_row = r5or6_first_row = r0_first_row = tmpdiv; | |
4828 | tmpdiv = last_block; | |
4829 | (void) do_div(tmpdiv, stripesize); | |
4830 | r5or6_last_row = r0_last_row = tmpdiv; | |
4831 | #else | |
4832 | first_row = r5or6_first_row = r0_first_row = | |
4833 | first_block / stripesize; | |
4834 | r5or6_last_row = r0_last_row = last_block / stripesize; | |
4835 | #endif | |
4836 | if (r5or6_first_row != r5or6_last_row) | |
4837 | return IO_ACCEL_INELIGIBLE; | |
4838 | ||
4839 | ||
4840 | /* Verify request is in a single column */ | |
4841 | #if BITS_PER_LONG == 32 | |
4842 | tmpdiv = first_block; | |
4843 | first_row_offset = do_div(tmpdiv, stripesize); | |
4844 | tmpdiv = first_row_offset; | |
4845 | first_row_offset = (u32) do_div(tmpdiv, r5or6_blocks_per_row); | |
4846 | r5or6_first_row_offset = first_row_offset; | |
4847 | tmpdiv = last_block; | |
4848 | r5or6_last_row_offset = do_div(tmpdiv, stripesize); | |
4849 | tmpdiv = r5or6_last_row_offset; | |
4850 | r5or6_last_row_offset = do_div(tmpdiv, r5or6_blocks_per_row); | |
4851 | tmpdiv = r5or6_first_row_offset; | |
4852 | (void) do_div(tmpdiv, map->strip_size); | |
4853 | first_column = r5or6_first_column = tmpdiv; | |
4854 | tmpdiv = r5or6_last_row_offset; | |
4855 | (void) do_div(tmpdiv, map->strip_size); | |
4856 | r5or6_last_column = tmpdiv; | |
4857 | #else | |
4858 | first_row_offset = r5or6_first_row_offset = | |
4859 | (u32)((first_block % stripesize) % | |
4860 | r5or6_blocks_per_row); | |
4861 | ||
4862 | r5or6_last_row_offset = | |
4863 | (u32)((last_block % stripesize) % | |
4864 | r5or6_blocks_per_row); | |
4865 | ||
4866 | first_column = r5or6_first_column = | |
2b08b3e9 | 4867 | r5or6_first_row_offset / le16_to_cpu(map->strip_size); |
6b80b18f | 4868 | r5or6_last_column = |
2b08b3e9 | 4869 | r5or6_last_row_offset / le16_to_cpu(map->strip_size); |
6b80b18f ST |
4870 | #endif |
4871 | if (r5or6_first_column != r5or6_last_column) | |
4872 | return IO_ACCEL_INELIGIBLE; | |
4873 | ||
4874 | /* Request is eligible */ | |
4875 | map_row = ((u32)(first_row >> map->parity_rotation_shift)) % | |
2b08b3e9 | 4876 | le16_to_cpu(map->row_cnt); |
6b80b18f ST |
4877 | |
4878 | map_index = (first_group * | |
2b08b3e9 | 4879 | (le16_to_cpu(map->row_cnt) * total_disks_per_row)) + |
6b80b18f ST |
4880 | (map_row * total_disks_per_row) + first_column; |
4881 | break; | |
4882 | default: | |
4883 | return IO_ACCEL_INELIGIBLE; | |
283b4a9b | 4884 | } |
6b80b18f | 4885 | |
07543e0c SC |
4886 | if (unlikely(map_index >= RAID_MAP_MAX_ENTRIES)) |
4887 | return IO_ACCEL_INELIGIBLE; | |
4888 | ||
03383736 DB |
4889 | c->phys_disk = dev->phys_disk[map_index]; |
4890 | ||
283b4a9b | 4891 | disk_handle = dd[map_index].ioaccel_handle; |
2b08b3e9 DB |
4892 | disk_block = le64_to_cpu(map->disk_starting_blk) + |
4893 | first_row * le16_to_cpu(map->strip_size) + | |
4894 | (first_row_offset - first_column * | |
4895 | le16_to_cpu(map->strip_size)); | |
283b4a9b SC |
4896 | disk_block_cnt = block_cnt; |
4897 | ||
4898 | /* handle differing logical/physical block sizes */ | |
4899 | if (map->phys_blk_shift) { | |
4900 | disk_block <<= map->phys_blk_shift; | |
4901 | disk_block_cnt <<= map->phys_blk_shift; | |
4902 | } | |
4903 | BUG_ON(disk_block_cnt > 0xffff); | |
4904 | ||
4905 | /* build the new CDB for the physical disk I/O */ | |
4906 | if (disk_block > 0xffffffff) { | |
4907 | cdb[0] = is_write ? WRITE_16 : READ_16; | |
4908 | cdb[1] = 0; | |
4909 | cdb[2] = (u8) (disk_block >> 56); | |
4910 | cdb[3] = (u8) (disk_block >> 48); | |
4911 | cdb[4] = (u8) (disk_block >> 40); | |
4912 | cdb[5] = (u8) (disk_block >> 32); | |
4913 | cdb[6] = (u8) (disk_block >> 24); | |
4914 | cdb[7] = (u8) (disk_block >> 16); | |
4915 | cdb[8] = (u8) (disk_block >> 8); | |
4916 | cdb[9] = (u8) (disk_block); | |
4917 | cdb[10] = (u8) (disk_block_cnt >> 24); | |
4918 | cdb[11] = (u8) (disk_block_cnt >> 16); | |
4919 | cdb[12] = (u8) (disk_block_cnt >> 8); | |
4920 | cdb[13] = (u8) (disk_block_cnt); | |
4921 | cdb[14] = 0; | |
4922 | cdb[15] = 0; | |
4923 | cdb_len = 16; | |
4924 | } else { | |
4925 | cdb[0] = is_write ? WRITE_10 : READ_10; | |
4926 | cdb[1] = 0; | |
4927 | cdb[2] = (u8) (disk_block >> 24); | |
4928 | cdb[3] = (u8) (disk_block >> 16); | |
4929 | cdb[4] = (u8) (disk_block >> 8); | |
4930 | cdb[5] = (u8) (disk_block); | |
4931 | cdb[6] = 0; | |
4932 | cdb[7] = (u8) (disk_block_cnt >> 8); | |
4933 | cdb[8] = (u8) (disk_block_cnt); | |
4934 | cdb[9] = 0; | |
4935 | cdb_len = 10; | |
4936 | } | |
4937 | return hpsa_scsi_ioaccel_queue_command(h, c, disk_handle, cdb, cdb_len, | |
03383736 DB |
4938 | dev->scsi3addr, |
4939 | dev->phys_disk[map_index]); | |
283b4a9b SC |
4940 | } |
4941 | ||
25163bd5 WS |
4942 | /* |
4943 | * Submit commands down the "normal" RAID stack path | |
4944 | * All callers to hpsa_ciss_submit must check lockup_detected | |
4945 | * beforehand, before (opt.) and after calling cmd_alloc | |
4946 | */ | |
574f05d3 SC |
4947 | static int hpsa_ciss_submit(struct ctlr_info *h, |
4948 | struct CommandList *c, struct scsi_cmnd *cmd, | |
4949 | unsigned char scsi3addr[]) | |
edd16368 | 4950 | { |
edd16368 | 4951 | cmd->host_scribble = (unsigned char *) c; |
edd16368 SC |
4952 | c->cmd_type = CMD_SCSI; |
4953 | c->scsi_cmd = cmd; | |
4954 | c->Header.ReplyQueue = 0; /* unused in simple mode */ | |
4955 | memcpy(&c->Header.LUN.LunAddrBytes[0], &scsi3addr[0], 8); | |
f2405db8 | 4956 | c->Header.tag = cpu_to_le64((c->cmdindex << DIRECT_LOOKUP_SHIFT)); |
edd16368 SC |
4957 | |
4958 | /* Fill in the request block... */ | |
4959 | ||
4960 | c->Request.Timeout = 0; | |
edd16368 SC |
4961 | BUG_ON(cmd->cmd_len > sizeof(c->Request.CDB)); |
4962 | c->Request.CDBLen = cmd->cmd_len; | |
4963 | memcpy(c->Request.CDB, cmd->cmnd, cmd->cmd_len); | |
edd16368 SC |
4964 | switch (cmd->sc_data_direction) { |
4965 | case DMA_TO_DEVICE: | |
a505b86f SC |
4966 | c->Request.type_attr_dir = |
4967 | TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_WRITE); | |
edd16368 SC |
4968 | break; |
4969 | case DMA_FROM_DEVICE: | |
a505b86f SC |
4970 | c->Request.type_attr_dir = |
4971 | TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_READ); | |
edd16368 SC |
4972 | break; |
4973 | case DMA_NONE: | |
a505b86f SC |
4974 | c->Request.type_attr_dir = |
4975 | TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_NONE); | |
edd16368 SC |
4976 | break; |
4977 | case DMA_BIDIRECTIONAL: | |
4978 | /* This can happen if a buggy application does a scsi passthru | |
4979 | * and sets both inlen and outlen to non-zero. ( see | |
4980 | * ../scsi/scsi_ioctl.c:scsi_ioctl_send_command() ) | |
4981 | */ | |
4982 | ||
a505b86f SC |
4983 | c->Request.type_attr_dir = |
4984 | TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_RSVD); | |
edd16368 SC |
4985 | /* This is technically wrong, and hpsa controllers should |
4986 | * reject it with CMD_INVALID, which is the most correct | |
4987 | * response, but non-fibre backends appear to let it | |
4988 | * slide by, and give the same results as if this field | |
4989 | * were set correctly. Either way is acceptable for | |
4990 | * our purposes here. | |
4991 | */ | |
4992 | ||
4993 | break; | |
4994 | ||
4995 | default: | |
4996 | dev_err(&h->pdev->dev, "unknown data direction: %d\n", | |
4997 | cmd->sc_data_direction); | |
4998 | BUG(); | |
4999 | break; | |
5000 | } | |
5001 | ||
33a2ffce | 5002 | if (hpsa_scatter_gather(h, c, cmd) < 0) { /* Fill SG list */ |
73153fe5 | 5003 | hpsa_cmd_resolve_and_free(h, c); |
edd16368 SC |
5004 | return SCSI_MLQUEUE_HOST_BUSY; |
5005 | } | |
5006 | enqueue_cmd_and_start_io(h, c); | |
5007 | /* the cmd'll come back via intr handler in complete_scsi_command() */ | |
5008 | return 0; | |
5009 | } | |
5010 | ||
360c73bd SC |
5011 | static void hpsa_cmd_init(struct ctlr_info *h, int index, |
5012 | struct CommandList *c) | |
5013 | { | |
5014 | dma_addr_t cmd_dma_handle, err_dma_handle; | |
5015 | ||
5016 | /* Zero out all of commandlist except the last field, refcount */ | |
5017 | memset(c, 0, offsetof(struct CommandList, refcount)); | |
5018 | c->Header.tag = cpu_to_le64((u64) (index << DIRECT_LOOKUP_SHIFT)); | |
5019 | cmd_dma_handle = h->cmd_pool_dhandle + index * sizeof(*c); | |
5020 | c->err_info = h->errinfo_pool + index; | |
5021 | memset(c->err_info, 0, sizeof(*c->err_info)); | |
5022 | err_dma_handle = h->errinfo_pool_dhandle | |
5023 | + index * sizeof(*c->err_info); | |
5024 | c->cmdindex = index; | |
5025 | c->busaddr = (u32) cmd_dma_handle; | |
5026 | c->ErrDesc.Addr = cpu_to_le64((u64) err_dma_handle); | |
5027 | c->ErrDesc.Len = cpu_to_le32((u32) sizeof(*c->err_info)); | |
5028 | c->h = h; | |
a58e7e53 | 5029 | c->scsi_cmd = SCSI_CMD_IDLE; |
360c73bd SC |
5030 | } |
5031 | ||
5032 | static void hpsa_preinitialize_commands(struct ctlr_info *h) | |
5033 | { | |
5034 | int i; | |
5035 | ||
5036 | for (i = 0; i < h->nr_cmds; i++) { | |
5037 | struct CommandList *c = h->cmd_pool + i; | |
5038 | ||
5039 | hpsa_cmd_init(h, i, c); | |
5040 | atomic_set(&c->refcount, 0); | |
5041 | } | |
5042 | } | |
5043 | ||
5044 | static inline void hpsa_cmd_partial_init(struct ctlr_info *h, int index, | |
5045 | struct CommandList *c) | |
5046 | { | |
5047 | dma_addr_t cmd_dma_handle = h->cmd_pool_dhandle + index * sizeof(*c); | |
5048 | ||
73153fe5 WS |
5049 | BUG_ON(c->cmdindex != index); |
5050 | ||
360c73bd SC |
5051 | memset(c->Request.CDB, 0, sizeof(c->Request.CDB)); |
5052 | memset(c->err_info, 0, sizeof(*c->err_info)); | |
5053 | c->busaddr = (u32) cmd_dma_handle; | |
5054 | } | |
5055 | ||
592a0ad5 WS |
5056 | static int hpsa_ioaccel_submit(struct ctlr_info *h, |
5057 | struct CommandList *c, struct scsi_cmnd *cmd, | |
5058 | unsigned char *scsi3addr) | |
5059 | { | |
5060 | struct hpsa_scsi_dev_t *dev = cmd->device->hostdata; | |
5061 | int rc = IO_ACCEL_INELIGIBLE; | |
5062 | ||
5063 | cmd->host_scribble = (unsigned char *) c; | |
5064 | ||
5065 | if (dev->offload_enabled) { | |
5066 | hpsa_cmd_init(h, c->cmdindex, c); | |
5067 | c->cmd_type = CMD_SCSI; | |
5068 | c->scsi_cmd = cmd; | |
5069 | rc = hpsa_scsi_ioaccel_raid_map(h, c); | |
5070 | if (rc < 0) /* scsi_dma_map failed. */ | |
5071 | rc = SCSI_MLQUEUE_HOST_BUSY; | |
a3144e0b | 5072 | } else if (dev->hba_ioaccel_enabled) { |
592a0ad5 WS |
5073 | hpsa_cmd_init(h, c->cmdindex, c); |
5074 | c->cmd_type = CMD_SCSI; | |
5075 | c->scsi_cmd = cmd; | |
5076 | rc = hpsa_scsi_ioaccel_direct_map(h, c); | |
5077 | if (rc < 0) /* scsi_dma_map failed. */ | |
5078 | rc = SCSI_MLQUEUE_HOST_BUSY; | |
5079 | } | |
5080 | return rc; | |
5081 | } | |
5082 | ||
080ef1cc DB |
5083 | static void hpsa_command_resubmit_worker(struct work_struct *work) |
5084 | { | |
5085 | struct scsi_cmnd *cmd; | |
5086 | struct hpsa_scsi_dev_t *dev; | |
8a0ff92c | 5087 | struct CommandList *c = container_of(work, struct CommandList, work); |
080ef1cc DB |
5088 | |
5089 | cmd = c->scsi_cmd; | |
5090 | dev = cmd->device->hostdata; | |
5091 | if (!dev) { | |
5092 | cmd->result = DID_NO_CONNECT << 16; | |
8a0ff92c | 5093 | return hpsa_cmd_free_and_done(c->h, c, cmd); |
080ef1cc | 5094 | } |
d604f533 WS |
5095 | if (c->reset_pending) |
5096 | return hpsa_cmd_resolve_and_free(c->h, c); | |
a58e7e53 WS |
5097 | if (c->abort_pending) |
5098 | return hpsa_cmd_abort_and_free(c->h, c, cmd); | |
592a0ad5 WS |
5099 | if (c->cmd_type == CMD_IOACCEL2) { |
5100 | struct ctlr_info *h = c->h; | |
5101 | struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex]; | |
5102 | int rc; | |
5103 | ||
5104 | if (c2->error_data.serv_response == | |
5105 | IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL) { | |
5106 | rc = hpsa_ioaccel_submit(h, c, cmd, dev->scsi3addr); | |
5107 | if (rc == 0) | |
5108 | return; | |
5109 | if (rc == SCSI_MLQUEUE_HOST_BUSY) { | |
5110 | /* | |
5111 | * If we get here, it means dma mapping failed. | |
5112 | * Try again via scsi mid layer, which will | |
5113 | * then get SCSI_MLQUEUE_HOST_BUSY. | |
5114 | */ | |
5115 | cmd->result = DID_IMM_RETRY << 16; | |
8a0ff92c | 5116 | return hpsa_cmd_free_and_done(h, c, cmd); |
592a0ad5 WS |
5117 | } |
5118 | /* else, fall thru and resubmit down CISS path */ | |
5119 | } | |
5120 | } | |
360c73bd | 5121 | hpsa_cmd_partial_init(c->h, c->cmdindex, c); |
080ef1cc DB |
5122 | if (hpsa_ciss_submit(c->h, c, cmd, dev->scsi3addr)) { |
5123 | /* | |
5124 | * If we get here, it means dma mapping failed. Try | |
5125 | * again via scsi mid layer, which will then get | |
5126 | * SCSI_MLQUEUE_HOST_BUSY. | |
592a0ad5 WS |
5127 | * |
5128 | * hpsa_ciss_submit will have already freed c | |
5129 | * if it encountered a dma mapping failure. | |
080ef1cc DB |
5130 | */ |
5131 | cmd->result = DID_IMM_RETRY << 16; | |
5132 | cmd->scsi_done(cmd); | |
5133 | } | |
5134 | } | |
5135 | ||
574f05d3 SC |
5136 | /* Running in struct Scsi_Host->host_lock less mode */ |
5137 | static int hpsa_scsi_queue_command(struct Scsi_Host *sh, struct scsi_cmnd *cmd) | |
5138 | { | |
5139 | struct ctlr_info *h; | |
5140 | struct hpsa_scsi_dev_t *dev; | |
5141 | unsigned char scsi3addr[8]; | |
5142 | struct CommandList *c; | |
5143 | int rc = 0; | |
5144 | ||
5145 | /* Get the ptr to our adapter structure out of cmd->host. */ | |
5146 | h = sdev_to_hba(cmd->device); | |
73153fe5 WS |
5147 | |
5148 | BUG_ON(cmd->request->tag < 0); | |
5149 | ||
574f05d3 SC |
5150 | dev = cmd->device->hostdata; |
5151 | if (!dev) { | |
5152 | cmd->result = DID_NO_CONNECT << 16; | |
5153 | cmd->scsi_done(cmd); | |
5154 | return 0; | |
5155 | } | |
574f05d3 | 5156 | |
73153fe5 | 5157 | memcpy(scsi3addr, dev->scsi3addr, sizeof(scsi3addr)); |
bf43caf3 | 5158 | |
407863cb | 5159 | if (unlikely(lockup_detected(h))) { |
25163bd5 | 5160 | cmd->result = DID_NO_CONNECT << 16; |
407863cb SC |
5161 | cmd->scsi_done(cmd); |
5162 | return 0; | |
5163 | } | |
73153fe5 | 5164 | c = cmd_tagged_alloc(h, cmd); |
574f05d3 | 5165 | |
407863cb SC |
5166 | /* |
5167 | * Call alternate submit routine for I/O accelerated commands. | |
574f05d3 SC |
5168 | * Retries always go down the normal I/O path. |
5169 | */ | |
5170 | if (likely(cmd->retries == 0 && | |
5171 | cmd->request->cmd_type == REQ_TYPE_FS && | |
5172 | h->acciopath_status)) { | |
592a0ad5 WS |
5173 | rc = hpsa_ioaccel_submit(h, c, cmd, scsi3addr); |
5174 | if (rc == 0) | |
5175 | return 0; | |
5176 | if (rc == SCSI_MLQUEUE_HOST_BUSY) { | |
73153fe5 | 5177 | hpsa_cmd_resolve_and_free(h, c); |
592a0ad5 | 5178 | return SCSI_MLQUEUE_HOST_BUSY; |
574f05d3 SC |
5179 | } |
5180 | } | |
5181 | return hpsa_ciss_submit(h, c, cmd, scsi3addr); | |
5182 | } | |
5183 | ||
8ebc9248 | 5184 | static void hpsa_scan_complete(struct ctlr_info *h) |
5f389360 SC |
5185 | { |
5186 | unsigned long flags; | |
5187 | ||
8ebc9248 WS |
5188 | spin_lock_irqsave(&h->scan_lock, flags); |
5189 | h->scan_finished = 1; | |
5190 | wake_up_all(&h->scan_wait_queue); | |
5191 | spin_unlock_irqrestore(&h->scan_lock, flags); | |
5f389360 SC |
5192 | } |
5193 | ||
a08a8471 SC |
5194 | static void hpsa_scan_start(struct Scsi_Host *sh) |
5195 | { | |
5196 | struct ctlr_info *h = shost_to_hba(sh); | |
5197 | unsigned long flags; | |
5198 | ||
8ebc9248 WS |
5199 | /* |
5200 | * Don't let rescans be initiated on a controller known to be locked | |
5201 | * up. If the controller locks up *during* a rescan, that thread is | |
5202 | * probably hosed, but at least we can prevent new rescan threads from | |
5203 | * piling up on a locked up controller. | |
5204 | */ | |
5205 | if (unlikely(lockup_detected(h))) | |
5206 | return hpsa_scan_complete(h); | |
5f389360 | 5207 | |
a08a8471 SC |
5208 | /* wait until any scan already in progress is finished. */ |
5209 | while (1) { | |
5210 | spin_lock_irqsave(&h->scan_lock, flags); | |
5211 | if (h->scan_finished) | |
5212 | break; | |
5213 | spin_unlock_irqrestore(&h->scan_lock, flags); | |
5214 | wait_event(h->scan_wait_queue, h->scan_finished); | |
5215 | /* Note: We don't need to worry about a race between this | |
5216 | * thread and driver unload because the midlayer will | |
5217 | * have incremented the reference count, so unload won't | |
5218 | * happen if we're in here. | |
5219 | */ | |
5220 | } | |
5221 | h->scan_finished = 0; /* mark scan as in progress */ | |
5222 | spin_unlock_irqrestore(&h->scan_lock, flags); | |
5223 | ||
8ebc9248 WS |
5224 | if (unlikely(lockup_detected(h))) |
5225 | return hpsa_scan_complete(h); | |
5f389360 | 5226 | |
8aa60681 | 5227 | hpsa_update_scsi_devices(h); |
a08a8471 | 5228 | |
8ebc9248 | 5229 | hpsa_scan_complete(h); |
a08a8471 SC |
5230 | } |
5231 | ||
7c0a0229 DB |
5232 | static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth) |
5233 | { | |
03383736 DB |
5234 | struct hpsa_scsi_dev_t *logical_drive = sdev->hostdata; |
5235 | ||
5236 | if (!logical_drive) | |
5237 | return -ENODEV; | |
7c0a0229 DB |
5238 | |
5239 | if (qdepth < 1) | |
5240 | qdepth = 1; | |
03383736 DB |
5241 | else if (qdepth > logical_drive->queue_depth) |
5242 | qdepth = logical_drive->queue_depth; | |
5243 | ||
5244 | return scsi_change_queue_depth(sdev, qdepth); | |
7c0a0229 DB |
5245 | } |
5246 | ||
a08a8471 SC |
5247 | static int hpsa_scan_finished(struct Scsi_Host *sh, |
5248 | unsigned long elapsed_time) | |
5249 | { | |
5250 | struct ctlr_info *h = shost_to_hba(sh); | |
5251 | unsigned long flags; | |
5252 | int finished; | |
5253 | ||
5254 | spin_lock_irqsave(&h->scan_lock, flags); | |
5255 | finished = h->scan_finished; | |
5256 | spin_unlock_irqrestore(&h->scan_lock, flags); | |
5257 | return finished; | |
5258 | } | |
5259 | ||
2946e82b | 5260 | static int hpsa_scsi_host_alloc(struct ctlr_info *h) |
edd16368 | 5261 | { |
b705690d | 5262 | struct Scsi_Host *sh; |
edd16368 | 5263 | |
b705690d | 5264 | sh = scsi_host_alloc(&hpsa_driver_template, sizeof(h)); |
2946e82b RE |
5265 | if (sh == NULL) { |
5266 | dev_err(&h->pdev->dev, "scsi_host_alloc failed\n"); | |
5267 | return -ENOMEM; | |
5268 | } | |
b705690d SC |
5269 | |
5270 | sh->io_port = 0; | |
5271 | sh->n_io_port = 0; | |
5272 | sh->this_id = -1; | |
5273 | sh->max_channel = 3; | |
5274 | sh->max_cmd_len = MAX_COMMAND_SIZE; | |
5275 | sh->max_lun = HPSA_MAX_LUN; | |
5276 | sh->max_id = HPSA_MAX_LUN; | |
41ce4c35 | 5277 | sh->can_queue = h->nr_cmds - HPSA_NRESERVED_CMDS; |
03383736 | 5278 | sh->cmd_per_lun = sh->can_queue; |
b705690d | 5279 | sh->sg_tablesize = h->maxsgentries; |
d04e62b9 | 5280 | sh->transportt = hpsa_sas_transport_template; |
b705690d SC |
5281 | sh->hostdata[0] = (unsigned long) h; |
5282 | sh->irq = h->intr[h->intr_mode]; | |
5283 | sh->unique_id = sh->irq; | |
64d513ac | 5284 | |
2946e82b | 5285 | h->scsi_host = sh; |
b705690d | 5286 | return 0; |
2946e82b | 5287 | } |
b705690d | 5288 | |
2946e82b RE |
5289 | static int hpsa_scsi_add_host(struct ctlr_info *h) |
5290 | { | |
5291 | int rv; | |
5292 | ||
5293 | rv = scsi_add_host(h->scsi_host, &h->pdev->dev); | |
5294 | if (rv) { | |
5295 | dev_err(&h->pdev->dev, "scsi_add_host failed\n"); | |
5296 | return rv; | |
5297 | } | |
5298 | scsi_scan_host(h->scsi_host); | |
5299 | return 0; | |
edd16368 SC |
5300 | } |
5301 | ||
73153fe5 WS |
5302 | /* |
5303 | * The block layer has already gone to the trouble of picking out a unique, | |
5304 | * small-integer tag for this request. We use an offset from that value as | |
5305 | * an index to select our command block. (The offset allows us to reserve the | |
5306 | * low-numbered entries for our own uses.) | |
5307 | */ | |
5308 | static int hpsa_get_cmd_index(struct scsi_cmnd *scmd) | |
5309 | { | |
5310 | int idx = scmd->request->tag; | |
5311 | ||
5312 | if (idx < 0) | |
5313 | return idx; | |
5314 | ||
5315 | /* Offset to leave space for internal cmds. */ | |
5316 | return idx += HPSA_NRESERVED_CMDS; | |
5317 | } | |
5318 | ||
b69324ff WS |
5319 | /* |
5320 | * Send a TEST_UNIT_READY command to the specified LUN using the specified | |
5321 | * reply queue; returns zero if the unit is ready, and non-zero otherwise. | |
5322 | */ | |
5323 | static int hpsa_send_test_unit_ready(struct ctlr_info *h, | |
5324 | struct CommandList *c, unsigned char lunaddr[], | |
5325 | int reply_queue) | |
5326 | { | |
5327 | int rc; | |
5328 | ||
5329 | /* Send the Test Unit Ready, fill_cmd can't fail, no mapping */ | |
5330 | (void) fill_cmd(c, TEST_UNIT_READY, h, | |
5331 | NULL, 0, 0, lunaddr, TYPE_CMD); | |
5332 | rc = hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT); | |
5333 | if (rc) | |
5334 | return rc; | |
5335 | /* no unmap needed here because no data xfer. */ | |
5336 | ||
5337 | /* Check if the unit is already ready. */ | |
5338 | if (c->err_info->CommandStatus == CMD_SUCCESS) | |
5339 | return 0; | |
5340 | ||
5341 | /* | |
5342 | * The first command sent after reset will receive "unit attention" to | |
5343 | * indicate that the LUN has been reset...this is actually what we're | |
5344 | * looking for (but, success is good too). | |
5345 | */ | |
5346 | if (c->err_info->CommandStatus == CMD_TARGET_STATUS && | |
5347 | c->err_info->ScsiStatus == SAM_STAT_CHECK_CONDITION && | |
5348 | (c->err_info->SenseInfo[2] == NO_SENSE || | |
5349 | c->err_info->SenseInfo[2] == UNIT_ATTENTION)) | |
5350 | return 0; | |
5351 | ||
5352 | return 1; | |
5353 | } | |
5354 | ||
5355 | /* | |
5356 | * Wait for a TEST_UNIT_READY command to complete, retrying as necessary; | |
5357 | * returns zero when the unit is ready, and non-zero when giving up. | |
5358 | */ | |
5359 | static int hpsa_wait_for_test_unit_ready(struct ctlr_info *h, | |
5360 | struct CommandList *c, | |
5361 | unsigned char lunaddr[], int reply_queue) | |
edd16368 | 5362 | { |
8919358e | 5363 | int rc; |
edd16368 SC |
5364 | int count = 0; |
5365 | int waittime = 1; /* seconds */ | |
edd16368 SC |
5366 | |
5367 | /* Send test unit ready until device ready, or give up. */ | |
b69324ff | 5368 | for (count = 0; count < HPSA_TUR_RETRY_LIMIT; count++) { |
edd16368 | 5369 | |
b69324ff WS |
5370 | /* |
5371 | * Wait for a bit. do this first, because if we send | |
edd16368 SC |
5372 | * the TUR right away, the reset will just abort it. |
5373 | */ | |
5374 | msleep(1000 * waittime); | |
b69324ff WS |
5375 | |
5376 | rc = hpsa_send_test_unit_ready(h, c, lunaddr, reply_queue); | |
5377 | if (!rc) | |
5378 | break; | |
edd16368 SC |
5379 | |
5380 | /* Increase wait time with each try, up to a point. */ | |
5381 | if (waittime < HPSA_MAX_WAIT_INTERVAL_SECS) | |
b69324ff | 5382 | waittime *= 2; |
edd16368 | 5383 | |
b69324ff WS |
5384 | dev_warn(&h->pdev->dev, |
5385 | "waiting %d secs for device to become ready.\n", | |
5386 | waittime); | |
5387 | } | |
edd16368 | 5388 | |
b69324ff WS |
5389 | return rc; |
5390 | } | |
edd16368 | 5391 | |
b69324ff WS |
5392 | static int wait_for_device_to_become_ready(struct ctlr_info *h, |
5393 | unsigned char lunaddr[], | |
5394 | int reply_queue) | |
5395 | { | |
5396 | int first_queue; | |
5397 | int last_queue; | |
5398 | int rq; | |
5399 | int rc = 0; | |
5400 | struct CommandList *c; | |
5401 | ||
5402 | c = cmd_alloc(h); | |
5403 | ||
5404 | /* | |
5405 | * If no specific reply queue was requested, then send the TUR | |
5406 | * repeatedly, requesting a reply on each reply queue; otherwise execute | |
5407 | * the loop exactly once using only the specified queue. | |
5408 | */ | |
5409 | if (reply_queue == DEFAULT_REPLY_QUEUE) { | |
5410 | first_queue = 0; | |
5411 | last_queue = h->nreply_queues - 1; | |
5412 | } else { | |
5413 | first_queue = reply_queue; | |
5414 | last_queue = reply_queue; | |
5415 | } | |
5416 | ||
5417 | for (rq = first_queue; rq <= last_queue; rq++) { | |
5418 | rc = hpsa_wait_for_test_unit_ready(h, c, lunaddr, rq); | |
5419 | if (rc) | |
edd16368 | 5420 | break; |
edd16368 SC |
5421 | } |
5422 | ||
5423 | if (rc) | |
5424 | dev_warn(&h->pdev->dev, "giving up on device.\n"); | |
5425 | else | |
5426 | dev_warn(&h->pdev->dev, "device is ready.\n"); | |
5427 | ||
45fcb86e | 5428 | cmd_free(h, c); |
edd16368 SC |
5429 | return rc; |
5430 | } | |
5431 | ||
5432 | /* Need at least one of these error handlers to keep ../scsi/hosts.c from | |
5433 | * complaining. Doing a host- or bus-reset can't do anything good here. | |
5434 | */ | |
5435 | static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd) | |
5436 | { | |
5437 | int rc; | |
5438 | struct ctlr_info *h; | |
5439 | struct hpsa_scsi_dev_t *dev; | |
0b9b7b6e | 5440 | u8 reset_type; |
2dc127bb | 5441 | char msg[48]; |
edd16368 SC |
5442 | |
5443 | /* find the controller to which the command to be aborted was sent */ | |
5444 | h = sdev_to_hba(scsicmd->device); | |
5445 | if (h == NULL) /* paranoia */ | |
5446 | return FAILED; | |
e345893b DB |
5447 | |
5448 | if (lockup_detected(h)) | |
5449 | return FAILED; | |
5450 | ||
edd16368 SC |
5451 | dev = scsicmd->device->hostdata; |
5452 | if (!dev) { | |
d604f533 | 5453 | dev_err(&h->pdev->dev, "%s: device lookup failed\n", __func__); |
edd16368 SC |
5454 | return FAILED; |
5455 | } | |
25163bd5 WS |
5456 | |
5457 | /* if controller locked up, we can guarantee command won't complete */ | |
5458 | if (lockup_detected(h)) { | |
2dc127bb DC |
5459 | snprintf(msg, sizeof(msg), |
5460 | "cmd %d RESET FAILED, lockup detected", | |
5461 | hpsa_get_cmd_index(scsicmd)); | |
73153fe5 | 5462 | hpsa_show_dev_msg(KERN_WARNING, h, dev, msg); |
25163bd5 WS |
5463 | return FAILED; |
5464 | } | |
5465 | ||
5466 | /* this reset request might be the result of a lockup; check */ | |
5467 | if (detect_controller_lockup(h)) { | |
2dc127bb DC |
5468 | snprintf(msg, sizeof(msg), |
5469 | "cmd %d RESET FAILED, new lockup detected", | |
5470 | hpsa_get_cmd_index(scsicmd)); | |
73153fe5 | 5471 | hpsa_show_dev_msg(KERN_WARNING, h, dev, msg); |
25163bd5 WS |
5472 | return FAILED; |
5473 | } | |
5474 | ||
d604f533 WS |
5475 | /* Do not attempt on controller */ |
5476 | if (is_hba_lunid(dev->scsi3addr)) | |
5477 | return SUCCESS; | |
5478 | ||
0b9b7b6e ST |
5479 | if (is_logical_dev_addr_mode(dev->scsi3addr)) |
5480 | reset_type = HPSA_DEVICE_RESET_MSG; | |
5481 | else | |
5482 | reset_type = HPSA_PHYS_TARGET_RESET; | |
5483 | ||
5484 | sprintf(msg, "resetting %s", | |
5485 | reset_type == HPSA_DEVICE_RESET_MSG ? "logical " : "physical "); | |
5486 | hpsa_show_dev_msg(KERN_WARNING, h, dev, msg); | |
25163bd5 | 5487 | |
da03ded0 | 5488 | h->reset_in_progress = 1; |
25163bd5 | 5489 | |
edd16368 | 5490 | /* send a reset to the SCSI LUN which the command was sent to */ |
0b9b7b6e | 5491 | rc = hpsa_do_reset(h, dev, dev->scsi3addr, reset_type, |
d604f533 | 5492 | DEFAULT_REPLY_QUEUE); |
0b9b7b6e ST |
5493 | sprintf(msg, "reset %s %s", |
5494 | reset_type == HPSA_DEVICE_RESET_MSG ? "logical " : "physical ", | |
5495 | rc == 0 ? "completed successfully" : "failed"); | |
d604f533 | 5496 | hpsa_show_dev_msg(KERN_WARNING, h, dev, msg); |
da03ded0 | 5497 | h->reset_in_progress = 0; |
d604f533 | 5498 | return rc == 0 ? SUCCESS : FAILED; |
edd16368 SC |
5499 | } |
5500 | ||
6cba3f19 SC |
5501 | static void swizzle_abort_tag(u8 *tag) |
5502 | { | |
5503 | u8 original_tag[8]; | |
5504 | ||
5505 | memcpy(original_tag, tag, 8); | |
5506 | tag[0] = original_tag[3]; | |
5507 | tag[1] = original_tag[2]; | |
5508 | tag[2] = original_tag[1]; | |
5509 | tag[3] = original_tag[0]; | |
5510 | tag[4] = original_tag[7]; | |
5511 | tag[5] = original_tag[6]; | |
5512 | tag[6] = original_tag[5]; | |
5513 | tag[7] = original_tag[4]; | |
5514 | } | |
5515 | ||
17eb87d2 | 5516 | static void hpsa_get_tag(struct ctlr_info *h, |
2b08b3e9 | 5517 | struct CommandList *c, __le32 *taglower, __le32 *tagupper) |
17eb87d2 | 5518 | { |
2b08b3e9 | 5519 | u64 tag; |
17eb87d2 ST |
5520 | if (c->cmd_type == CMD_IOACCEL1) { |
5521 | struct io_accel1_cmd *cm1 = (struct io_accel1_cmd *) | |
5522 | &h->ioaccel_cmd_pool[c->cmdindex]; | |
2b08b3e9 DB |
5523 | tag = le64_to_cpu(cm1->tag); |
5524 | *tagupper = cpu_to_le32(tag >> 32); | |
5525 | *taglower = cpu_to_le32(tag); | |
54b6e9e9 ST |
5526 | return; |
5527 | } | |
5528 | if (c->cmd_type == CMD_IOACCEL2) { | |
5529 | struct io_accel2_cmd *cm2 = (struct io_accel2_cmd *) | |
5530 | &h->ioaccel2_cmd_pool[c->cmdindex]; | |
dd0e19f3 ST |
5531 | /* upper tag not used in ioaccel2 mode */ |
5532 | memset(tagupper, 0, sizeof(*tagupper)); | |
5533 | *taglower = cm2->Tag; | |
54b6e9e9 | 5534 | return; |
17eb87d2 | 5535 | } |
2b08b3e9 DB |
5536 | tag = le64_to_cpu(c->Header.tag); |
5537 | *tagupper = cpu_to_le32(tag >> 32); | |
5538 | *taglower = cpu_to_le32(tag); | |
17eb87d2 ST |
5539 | } |
5540 | ||
75167d2c | 5541 | static int hpsa_send_abort(struct ctlr_info *h, unsigned char *scsi3addr, |
9b5c48c2 | 5542 | struct CommandList *abort, int reply_queue) |
75167d2c SC |
5543 | { |
5544 | int rc = IO_OK; | |
5545 | struct CommandList *c; | |
5546 | struct ErrorInfo *ei; | |
2b08b3e9 | 5547 | __le32 tagupper, taglower; |
75167d2c | 5548 | |
45fcb86e | 5549 | c = cmd_alloc(h); |
75167d2c | 5550 | |
a2dac136 | 5551 | /* fill_cmd can't fail here, no buffer to map */ |
9b5c48c2 | 5552 | (void) fill_cmd(c, HPSA_ABORT_MSG, h, &abort->Header.tag, |
a2dac136 | 5553 | 0, 0, scsi3addr, TYPE_MSG); |
9b5c48c2 | 5554 | if (h->needs_abort_tags_swizzled) |
6cba3f19 | 5555 | swizzle_abort_tag(&c->Request.CDB[4]); |
25163bd5 | 5556 | (void) hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT); |
17eb87d2 | 5557 | hpsa_get_tag(h, abort, &taglower, &tagupper); |
25163bd5 | 5558 | dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: do_simple_cmd(abort) completed.\n", |
17eb87d2 | 5559 | __func__, tagupper, taglower); |
75167d2c SC |
5560 | /* no unmap needed here because no data xfer. */ |
5561 | ||
5562 | ei = c->err_info; | |
5563 | switch (ei->CommandStatus) { | |
5564 | case CMD_SUCCESS: | |
5565 | break; | |
9437ac43 SC |
5566 | case CMD_TMF_STATUS: |
5567 | rc = hpsa_evaluate_tmf_status(h, c); | |
5568 | break; | |
75167d2c SC |
5569 | case CMD_UNABORTABLE: /* Very common, don't make noise. */ |
5570 | rc = -1; | |
5571 | break; | |
5572 | default: | |
5573 | dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: interpreting error.\n", | |
17eb87d2 | 5574 | __func__, tagupper, taglower); |
d1e8beac | 5575 | hpsa_scsi_interpret_error(h, c); |
75167d2c SC |
5576 | rc = -1; |
5577 | break; | |
5578 | } | |
45fcb86e | 5579 | cmd_free(h, c); |
dd0e19f3 ST |
5580 | dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n", |
5581 | __func__, tagupper, taglower); | |
75167d2c SC |
5582 | return rc; |
5583 | } | |
5584 | ||
8be986cc SC |
5585 | static void setup_ioaccel2_abort_cmd(struct CommandList *c, struct ctlr_info *h, |
5586 | struct CommandList *command_to_abort, int reply_queue) | |
5587 | { | |
5588 | struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex]; | |
5589 | struct hpsa_tmf_struct *ac = (struct hpsa_tmf_struct *) c2; | |
5590 | struct io_accel2_cmd *c2a = | |
5591 | &h->ioaccel2_cmd_pool[command_to_abort->cmdindex]; | |
a58e7e53 | 5592 | struct scsi_cmnd *scmd = command_to_abort->scsi_cmd; |
8be986cc SC |
5593 | struct hpsa_scsi_dev_t *dev = scmd->device->hostdata; |
5594 | ||
5595 | /* | |
5596 | * We're overlaying struct hpsa_tmf_struct on top of something which | |
5597 | * was allocated as a struct io_accel2_cmd, so we better be sure it | |
5598 | * actually fits, and doesn't overrun the error info space. | |
5599 | */ | |
5600 | BUILD_BUG_ON(sizeof(struct hpsa_tmf_struct) > | |
5601 | sizeof(struct io_accel2_cmd)); | |
5602 | BUG_ON(offsetof(struct io_accel2_cmd, error_data) < | |
5603 | offsetof(struct hpsa_tmf_struct, error_len) + | |
5604 | sizeof(ac->error_len)); | |
5605 | ||
5606 | c->cmd_type = IOACCEL2_TMF; | |
a58e7e53 WS |
5607 | c->scsi_cmd = SCSI_CMD_BUSY; |
5608 | ||
8be986cc SC |
5609 | /* Adjust the DMA address to point to the accelerated command buffer */ |
5610 | c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle + | |
5611 | (c->cmdindex * sizeof(struct io_accel2_cmd)); | |
5612 | BUG_ON(c->busaddr & 0x0000007F); | |
5613 | ||
5614 | memset(ac, 0, sizeof(*c2)); /* yes this is correct */ | |
5615 | ac->iu_type = IOACCEL2_IU_TMF_TYPE; | |
5616 | ac->reply_queue = reply_queue; | |
5617 | ac->tmf = IOACCEL2_TMF_ABORT; | |
5618 | ac->it_nexus = cpu_to_le32(dev->ioaccel_handle); | |
5619 | memset(ac->lun_id, 0, sizeof(ac->lun_id)); | |
5620 | ac->tag = cpu_to_le64(c->cmdindex << DIRECT_LOOKUP_SHIFT); | |
5621 | ac->abort_tag = cpu_to_le64(le32_to_cpu(c2a->Tag)); | |
5622 | ac->error_ptr = cpu_to_le64(c->busaddr + | |
5623 | offsetof(struct io_accel2_cmd, error_data)); | |
5624 | ac->error_len = cpu_to_le32(sizeof(c2->error_data)); | |
5625 | } | |
5626 | ||
54b6e9e9 ST |
5627 | /* ioaccel2 path firmware cannot handle abort task requests. |
5628 | * Change abort requests to physical target reset, and send to the | |
5629 | * address of the physical disk used for the ioaccel 2 command. | |
5630 | * Return 0 on success (IO_OK) | |
5631 | * -1 on failure | |
5632 | */ | |
5633 | ||
5634 | static int hpsa_send_reset_as_abort_ioaccel2(struct ctlr_info *h, | |
25163bd5 | 5635 | unsigned char *scsi3addr, struct CommandList *abort, int reply_queue) |
54b6e9e9 ST |
5636 | { |
5637 | int rc = IO_OK; | |
5638 | struct scsi_cmnd *scmd; /* scsi command within request being aborted */ | |
5639 | struct hpsa_scsi_dev_t *dev; /* device to which scsi cmd was sent */ | |
5640 | unsigned char phys_scsi3addr[8]; /* addr of phys disk with volume */ | |
5641 | unsigned char *psa = &phys_scsi3addr[0]; | |
5642 | ||
5643 | /* Get a pointer to the hpsa logical device. */ | |
7fa3030c | 5644 | scmd = abort->scsi_cmd; |
54b6e9e9 ST |
5645 | dev = (struct hpsa_scsi_dev_t *)(scmd->device->hostdata); |
5646 | if (dev == NULL) { | |
5647 | dev_warn(&h->pdev->dev, | |
5648 | "Cannot abort: no device pointer for command.\n"); | |
5649 | return -1; /* not abortable */ | |
5650 | } | |
5651 | ||
2ba8bfc8 SC |
5652 | if (h->raid_offload_debug > 0) |
5653 | dev_info(&h->pdev->dev, | |
0d96ef5f | 5654 | "scsi %d:%d:%d:%d %s scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n", |
2ba8bfc8 | 5655 | h->scsi_host->host_no, dev->bus, dev->target, dev->lun, |
0d96ef5f | 5656 | "Reset as abort", |
2ba8bfc8 SC |
5657 | scsi3addr[0], scsi3addr[1], scsi3addr[2], scsi3addr[3], |
5658 | scsi3addr[4], scsi3addr[5], scsi3addr[6], scsi3addr[7]); | |
5659 | ||
54b6e9e9 ST |
5660 | if (!dev->offload_enabled) { |
5661 | dev_warn(&h->pdev->dev, | |
5662 | "Can't abort: device is not operating in HP SSD Smart Path mode.\n"); | |
5663 | return -1; /* not abortable */ | |
5664 | } | |
5665 | ||
5666 | /* Incoming scsi3addr is logical addr. We need physical disk addr. */ | |
5667 | if (!hpsa_get_pdisk_of_ioaccel2(h, abort, psa)) { | |
5668 | dev_warn(&h->pdev->dev, "Can't abort: Failed lookup of physical address.\n"); | |
5669 | return -1; /* not abortable */ | |
5670 | } | |
5671 | ||
5672 | /* send the reset */ | |
2ba8bfc8 SC |
5673 | if (h->raid_offload_debug > 0) |
5674 | dev_info(&h->pdev->dev, | |
5675 | "Reset as abort: Resetting physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n", | |
5676 | psa[0], psa[1], psa[2], psa[3], | |
5677 | psa[4], psa[5], psa[6], psa[7]); | |
d604f533 | 5678 | rc = hpsa_do_reset(h, dev, psa, HPSA_RESET_TYPE_TARGET, reply_queue); |
54b6e9e9 ST |
5679 | if (rc != 0) { |
5680 | dev_warn(&h->pdev->dev, | |
5681 | "Reset as abort: Failed on physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n", | |
5682 | psa[0], psa[1], psa[2], psa[3], | |
5683 | psa[4], psa[5], psa[6], psa[7]); | |
5684 | return rc; /* failed to reset */ | |
5685 | } | |
5686 | ||
5687 | /* wait for device to recover */ | |
b69324ff | 5688 | if (wait_for_device_to_become_ready(h, psa, reply_queue) != 0) { |
54b6e9e9 ST |
5689 | dev_warn(&h->pdev->dev, |
5690 | "Reset as abort: Failed: Device never recovered from reset: 0x%02x%02x%02x%02x%02x%02x%02x%02x\n", | |
5691 | psa[0], psa[1], psa[2], psa[3], | |
5692 | psa[4], psa[5], psa[6], psa[7]); | |
5693 | return -1; /* failed to recover */ | |
5694 | } | |
5695 | ||
5696 | /* device recovered */ | |
5697 | dev_info(&h->pdev->dev, | |
5698 | "Reset as abort: Device recovered from reset: scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n", | |
5699 | psa[0], psa[1], psa[2], psa[3], | |
5700 | psa[4], psa[5], psa[6], psa[7]); | |
5701 | ||
5702 | return rc; /* success */ | |
5703 | } | |
5704 | ||
8be986cc SC |
5705 | static int hpsa_send_abort_ioaccel2(struct ctlr_info *h, |
5706 | struct CommandList *abort, int reply_queue) | |
5707 | { | |
5708 | int rc = IO_OK; | |
5709 | struct CommandList *c; | |
5710 | __le32 taglower, tagupper; | |
5711 | struct hpsa_scsi_dev_t *dev; | |
5712 | struct io_accel2_cmd *c2; | |
5713 | ||
5714 | dev = abort->scsi_cmd->device->hostdata; | |
5715 | if (!dev->offload_enabled && !dev->hba_ioaccel_enabled) | |
5716 | return -1; | |
5717 | ||
5718 | c = cmd_alloc(h); | |
5719 | setup_ioaccel2_abort_cmd(c, h, abort, reply_queue); | |
5720 | c2 = &h->ioaccel2_cmd_pool[c->cmdindex]; | |
5721 | (void) hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT); | |
5722 | hpsa_get_tag(h, abort, &taglower, &tagupper); | |
5723 | dev_dbg(&h->pdev->dev, | |
5724 | "%s: Tag:0x%08x:%08x: do_simple_cmd(ioaccel2 abort) completed.\n", | |
5725 | __func__, tagupper, taglower); | |
5726 | /* no unmap needed here because no data xfer. */ | |
5727 | ||
5728 | dev_dbg(&h->pdev->dev, | |
5729 | "%s: Tag:0x%08x:%08x: abort service response = 0x%02x.\n", | |
5730 | __func__, tagupper, taglower, c2->error_data.serv_response); | |
5731 | switch (c2->error_data.serv_response) { | |
5732 | case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE: | |
5733 | case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS: | |
5734 | rc = 0; | |
5735 | break; | |
5736 | case IOACCEL2_SERV_RESPONSE_TMF_REJECTED: | |
5737 | case IOACCEL2_SERV_RESPONSE_FAILURE: | |
5738 | case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN: | |
5739 | rc = -1; | |
5740 | break; | |
5741 | default: | |
5742 | dev_warn(&h->pdev->dev, | |
5743 | "%s: Tag:0x%08x:%08x: unknown abort service response 0x%02x\n", | |
5744 | __func__, tagupper, taglower, | |
5745 | c2->error_data.serv_response); | |
5746 | rc = -1; | |
5747 | } | |
5748 | cmd_free(h, c); | |
5749 | dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n", __func__, | |
5750 | tagupper, taglower); | |
5751 | return rc; | |
5752 | } | |
5753 | ||
6cba3f19 | 5754 | static int hpsa_send_abort_both_ways(struct ctlr_info *h, |
25163bd5 | 5755 | unsigned char *scsi3addr, struct CommandList *abort, int reply_queue) |
6cba3f19 | 5756 | { |
8be986cc SC |
5757 | /* |
5758 | * ioccelerator mode 2 commands should be aborted via the | |
54b6e9e9 | 5759 | * accelerated path, since RAID path is unaware of these commands, |
8be986cc SC |
5760 | * but not all underlying firmware can handle abort TMF. |
5761 | * Change abort to physical device reset when abort TMF is unsupported. | |
54b6e9e9 | 5762 | */ |
8be986cc SC |
5763 | if (abort->cmd_type == CMD_IOACCEL2) { |
5764 | if (HPSATMF_IOACCEL_ENABLED & h->TMFSupportFlags) | |
5765 | return hpsa_send_abort_ioaccel2(h, abort, | |
5766 | reply_queue); | |
5767 | else | |
5768 | return hpsa_send_reset_as_abort_ioaccel2(h, scsi3addr, | |
25163bd5 | 5769 | abort, reply_queue); |
8be986cc | 5770 | } |
9b5c48c2 | 5771 | return hpsa_send_abort(h, scsi3addr, abort, reply_queue); |
25163bd5 | 5772 | } |
54b6e9e9 | 5773 | |
25163bd5 WS |
5774 | /* Find out which reply queue a command was meant to return on */ |
5775 | static int hpsa_extract_reply_queue(struct ctlr_info *h, | |
5776 | struct CommandList *c) | |
5777 | { | |
5778 | if (c->cmd_type == CMD_IOACCEL2) | |
5779 | return h->ioaccel2_cmd_pool[c->cmdindex].reply_queue; | |
5780 | return c->Header.ReplyQueue; | |
6cba3f19 SC |
5781 | } |
5782 | ||
9b5c48c2 SC |
5783 | /* |
5784 | * Limit concurrency of abort commands to prevent | |
5785 | * over-subscription of commands | |
5786 | */ | |
5787 | static inline int wait_for_available_abort_cmd(struct ctlr_info *h) | |
5788 | { | |
5789 | #define ABORT_CMD_WAIT_MSECS 5000 | |
5790 | return !wait_event_timeout(h->abort_cmd_wait_queue, | |
5791 | atomic_dec_if_positive(&h->abort_cmds_available) >= 0, | |
5792 | msecs_to_jiffies(ABORT_CMD_WAIT_MSECS)); | |
5793 | } | |
5794 | ||
75167d2c SC |
5795 | /* Send an abort for the specified command. |
5796 | * If the device and controller support it, | |
5797 | * send a task abort request. | |
5798 | */ | |
5799 | static int hpsa_eh_abort_handler(struct scsi_cmnd *sc) | |
5800 | { | |
5801 | ||
a58e7e53 | 5802 | int rc; |
75167d2c SC |
5803 | struct ctlr_info *h; |
5804 | struct hpsa_scsi_dev_t *dev; | |
5805 | struct CommandList *abort; /* pointer to command to be aborted */ | |
75167d2c SC |
5806 | struct scsi_cmnd *as; /* ptr to scsi cmd inside aborted command. */ |
5807 | char msg[256]; /* For debug messaging. */ | |
5808 | int ml = 0; | |
2b08b3e9 | 5809 | __le32 tagupper, taglower; |
25163bd5 WS |
5810 | int refcount, reply_queue; |
5811 | ||
5812 | if (sc == NULL) | |
5813 | return FAILED; | |
75167d2c | 5814 | |
9b5c48c2 SC |
5815 | if (sc->device == NULL) |
5816 | return FAILED; | |
5817 | ||
75167d2c SC |
5818 | /* Find the controller of the command to be aborted */ |
5819 | h = sdev_to_hba(sc->device); | |
9b5c48c2 | 5820 | if (h == NULL) |
75167d2c SC |
5821 | return FAILED; |
5822 | ||
25163bd5 WS |
5823 | /* Find the device of the command to be aborted */ |
5824 | dev = sc->device->hostdata; | |
5825 | if (!dev) { | |
5826 | dev_err(&h->pdev->dev, "%s FAILED, Device lookup failed.\n", | |
5827 | msg); | |
e345893b | 5828 | return FAILED; |
25163bd5 WS |
5829 | } |
5830 | ||
5831 | /* If controller locked up, we can guarantee command won't complete */ | |
5832 | if (lockup_detected(h)) { | |
5833 | hpsa_show_dev_msg(KERN_WARNING, h, dev, | |
5834 | "ABORT FAILED, lockup detected"); | |
5835 | return FAILED; | |
5836 | } | |
5837 | ||
5838 | /* This is a good time to check if controller lockup has occurred */ | |
5839 | if (detect_controller_lockup(h)) { | |
5840 | hpsa_show_dev_msg(KERN_WARNING, h, dev, | |
5841 | "ABORT FAILED, new lockup detected"); | |
5842 | return FAILED; | |
5843 | } | |
e345893b | 5844 | |
75167d2c SC |
5845 | /* Check that controller supports some kind of task abort */ |
5846 | if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags) && | |
5847 | !(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags)) | |
5848 | return FAILED; | |
5849 | ||
5850 | memset(msg, 0, sizeof(msg)); | |
4b761557 | 5851 | ml += sprintf(msg+ml, "scsi %d:%d:%d:%llu %s %p", |
75167d2c | 5852 | h->scsi_host->host_no, sc->device->channel, |
0d96ef5f | 5853 | sc->device->id, sc->device->lun, |
4b761557 | 5854 | "Aborting command", sc); |
75167d2c | 5855 | |
75167d2c SC |
5856 | /* Get SCSI command to be aborted */ |
5857 | abort = (struct CommandList *) sc->host_scribble; | |
5858 | if (abort == NULL) { | |
281a7fd0 WS |
5859 | /* This can happen if the command already completed. */ |
5860 | return SUCCESS; | |
5861 | } | |
5862 | refcount = atomic_inc_return(&abort->refcount); | |
5863 | if (refcount == 1) { /* Command is done already. */ | |
5864 | cmd_free(h, abort); | |
5865 | return SUCCESS; | |
75167d2c | 5866 | } |
9b5c48c2 SC |
5867 | |
5868 | /* Don't bother trying the abort if we know it won't work. */ | |
5869 | if (abort->cmd_type != CMD_IOACCEL2 && | |
5870 | abort->cmd_type != CMD_IOACCEL1 && !dev->supports_aborts) { | |
5871 | cmd_free(h, abort); | |
5872 | return FAILED; | |
5873 | } | |
5874 | ||
a58e7e53 WS |
5875 | /* |
5876 | * Check that we're aborting the right command. | |
5877 | * It's possible the CommandList already completed and got re-used. | |
5878 | */ | |
5879 | if (abort->scsi_cmd != sc) { | |
5880 | cmd_free(h, abort); | |
5881 | return SUCCESS; | |
5882 | } | |
5883 | ||
5884 | abort->abort_pending = true; | |
17eb87d2 | 5885 | hpsa_get_tag(h, abort, &taglower, &tagupper); |
25163bd5 | 5886 | reply_queue = hpsa_extract_reply_queue(h, abort); |
17eb87d2 | 5887 | ml += sprintf(msg+ml, "Tag:0x%08x:%08x ", tagupper, taglower); |
7fa3030c | 5888 | as = abort->scsi_cmd; |
75167d2c | 5889 | if (as != NULL) |
4b761557 RE |
5890 | ml += sprintf(msg+ml, |
5891 | "CDBLen: %d CDB: 0x%02x%02x... SN: 0x%lx ", | |
5892 | as->cmd_len, as->cmnd[0], as->cmnd[1], | |
5893 | as->serial_number); | |
5894 | dev_warn(&h->pdev->dev, "%s BEING SENT\n", msg); | |
0d96ef5f | 5895 | hpsa_show_dev_msg(KERN_WARNING, h, dev, "Aborting command"); |
4b761557 | 5896 | |
75167d2c SC |
5897 | /* |
5898 | * Command is in flight, or possibly already completed | |
5899 | * by the firmware (but not to the scsi mid layer) but we can't | |
5900 | * distinguish which. Send the abort down. | |
5901 | */ | |
9b5c48c2 SC |
5902 | if (wait_for_available_abort_cmd(h)) { |
5903 | dev_warn(&h->pdev->dev, | |
4b761557 RE |
5904 | "%s FAILED, timeout waiting for an abort command to become available.\n", |
5905 | msg); | |
9b5c48c2 SC |
5906 | cmd_free(h, abort); |
5907 | return FAILED; | |
5908 | } | |
25163bd5 | 5909 | rc = hpsa_send_abort_both_ways(h, dev->scsi3addr, abort, reply_queue); |
9b5c48c2 SC |
5910 | atomic_inc(&h->abort_cmds_available); |
5911 | wake_up_all(&h->abort_cmd_wait_queue); | |
75167d2c | 5912 | if (rc != 0) { |
4b761557 | 5913 | dev_warn(&h->pdev->dev, "%s SENT, FAILED\n", msg); |
0d96ef5f | 5914 | hpsa_show_dev_msg(KERN_WARNING, h, dev, |
4b761557 | 5915 | "FAILED to abort command"); |
281a7fd0 | 5916 | cmd_free(h, abort); |
75167d2c SC |
5917 | return FAILED; |
5918 | } | |
4b761557 | 5919 | dev_info(&h->pdev->dev, "%s SENT, SUCCESS\n", msg); |
d604f533 | 5920 | wait_event(h->event_sync_wait_queue, |
a58e7e53 | 5921 | abort->scsi_cmd != sc || lockup_detected(h)); |
281a7fd0 | 5922 | cmd_free(h, abort); |
a58e7e53 | 5923 | return !lockup_detected(h) ? SUCCESS : FAILED; |
75167d2c SC |
5924 | } |
5925 | ||
73153fe5 WS |
5926 | /* |
5927 | * For operations with an associated SCSI command, a command block is allocated | |
5928 | * at init, and managed by cmd_tagged_alloc() and cmd_tagged_free() using the | |
5929 | * block request tag as an index into a table of entries. cmd_tagged_free() is | |
5930 | * the complement, although cmd_free() may be called instead. | |
5931 | */ | |
5932 | static struct CommandList *cmd_tagged_alloc(struct ctlr_info *h, | |
5933 | struct scsi_cmnd *scmd) | |
5934 | { | |
5935 | int idx = hpsa_get_cmd_index(scmd); | |
5936 | struct CommandList *c = h->cmd_pool + idx; | |
5937 | ||
5938 | if (idx < HPSA_NRESERVED_CMDS || idx >= h->nr_cmds) { | |
5939 | dev_err(&h->pdev->dev, "Bad block tag: %d not in [%d..%d]\n", | |
5940 | idx, HPSA_NRESERVED_CMDS, h->nr_cmds - 1); | |
5941 | /* The index value comes from the block layer, so if it's out of | |
5942 | * bounds, it's probably not our bug. | |
5943 | */ | |
5944 | BUG(); | |
5945 | } | |
5946 | ||
5947 | atomic_inc(&c->refcount); | |
5948 | if (unlikely(!hpsa_is_cmd_idle(c))) { | |
5949 | /* | |
5950 | * We expect that the SCSI layer will hand us a unique tag | |
5951 | * value. Thus, there should never be a collision here between | |
5952 | * two requests...because if the selected command isn't idle | |
5953 | * then someone is going to be very disappointed. | |
5954 | */ | |
5955 | dev_err(&h->pdev->dev, | |
5956 | "tag collision (tag=%d) in cmd_tagged_alloc().\n", | |
5957 | idx); | |
5958 | if (c->scsi_cmd != NULL) | |
5959 | scsi_print_command(c->scsi_cmd); | |
5960 | scsi_print_command(scmd); | |
5961 | } | |
5962 | ||
5963 | hpsa_cmd_partial_init(h, idx, c); | |
5964 | return c; | |
5965 | } | |
5966 | ||
5967 | static void cmd_tagged_free(struct ctlr_info *h, struct CommandList *c) | |
5968 | { | |
5969 | /* | |
5970 | * Release our reference to the block. We don't need to do anything | |
5971 | * else to free it, because it is accessed by index. (There's no point | |
5972 | * in checking the result of the decrement, since we cannot guarantee | |
5973 | * that there isn't a concurrent abort which is also accessing it.) | |
5974 | */ | |
5975 | (void)atomic_dec(&c->refcount); | |
5976 | } | |
5977 | ||
edd16368 SC |
5978 | /* |
5979 | * For operations that cannot sleep, a command block is allocated at init, | |
5980 | * and managed by cmd_alloc() and cmd_free() using a simple bitmap to track | |
5981 | * which ones are free or in use. Lock must be held when calling this. | |
5982 | * cmd_free() is the complement. | |
bf43caf3 RE |
5983 | * This function never gives up and returns NULL. If it hangs, |
5984 | * another thread must call cmd_free() to free some tags. | |
edd16368 | 5985 | */ |
281a7fd0 | 5986 | |
edd16368 SC |
5987 | static struct CommandList *cmd_alloc(struct ctlr_info *h) |
5988 | { | |
5989 | struct CommandList *c; | |
360c73bd | 5990 | int refcount, i; |
73153fe5 | 5991 | int offset = 0; |
4c413128 | 5992 | |
33811026 RE |
5993 | /* |
5994 | * There is some *extremely* small but non-zero chance that that | |
4c413128 SC |
5995 | * multiple threads could get in here, and one thread could |
5996 | * be scanning through the list of bits looking for a free | |
5997 | * one, but the free ones are always behind him, and other | |
5998 | * threads sneak in behind him and eat them before he can | |
5999 | * get to them, so that while there is always a free one, a | |
6000 | * very unlucky thread might be starved anyway, never able to | |
6001 | * beat the other threads. In reality, this happens so | |
6002 | * infrequently as to be indistinguishable from never. | |
73153fe5 WS |
6003 | * |
6004 | * Note that we start allocating commands before the SCSI host structure | |
6005 | * is initialized. Since the search starts at bit zero, this | |
6006 | * all works, since we have at least one command structure available; | |
6007 | * however, it means that the structures with the low indexes have to be | |
6008 | * reserved for driver-initiated requests, while requests from the block | |
6009 | * layer will use the higher indexes. | |
4c413128 | 6010 | */ |
edd16368 | 6011 | |
281a7fd0 | 6012 | for (;;) { |
73153fe5 WS |
6013 | i = find_next_zero_bit(h->cmd_pool_bits, |
6014 | HPSA_NRESERVED_CMDS, | |
6015 | offset); | |
6016 | if (unlikely(i >= HPSA_NRESERVED_CMDS)) { | |
281a7fd0 WS |
6017 | offset = 0; |
6018 | continue; | |
6019 | } | |
6020 | c = h->cmd_pool + i; | |
6021 | refcount = atomic_inc_return(&c->refcount); | |
6022 | if (unlikely(refcount > 1)) { | |
6023 | cmd_free(h, c); /* already in use */ | |
73153fe5 | 6024 | offset = (i + 1) % HPSA_NRESERVED_CMDS; |
281a7fd0 WS |
6025 | continue; |
6026 | } | |
6027 | set_bit(i & (BITS_PER_LONG - 1), | |
6028 | h->cmd_pool_bits + (i / BITS_PER_LONG)); | |
6029 | break; /* it's ours now. */ | |
6030 | } | |
360c73bd | 6031 | hpsa_cmd_partial_init(h, i, c); |
edd16368 SC |
6032 | return c; |
6033 | } | |
6034 | ||
73153fe5 WS |
6035 | /* |
6036 | * This is the complementary operation to cmd_alloc(). Note, however, in some | |
6037 | * corner cases it may also be used to free blocks allocated by | |
6038 | * cmd_tagged_alloc() in which case the ref-count decrement does the trick and | |
6039 | * the clear-bit is harmless. | |
6040 | */ | |
edd16368 SC |
6041 | static void cmd_free(struct ctlr_info *h, struct CommandList *c) |
6042 | { | |
281a7fd0 WS |
6043 | if (atomic_dec_and_test(&c->refcount)) { |
6044 | int i; | |
edd16368 | 6045 | |
281a7fd0 WS |
6046 | i = c - h->cmd_pool; |
6047 | clear_bit(i & (BITS_PER_LONG - 1), | |
6048 | h->cmd_pool_bits + (i / BITS_PER_LONG)); | |
6049 | } | |
edd16368 SC |
6050 | } |
6051 | ||
edd16368 SC |
6052 | #ifdef CONFIG_COMPAT |
6053 | ||
42a91641 DB |
6054 | static int hpsa_ioctl32_passthru(struct scsi_device *dev, int cmd, |
6055 | void __user *arg) | |
edd16368 SC |
6056 | { |
6057 | IOCTL32_Command_struct __user *arg32 = | |
6058 | (IOCTL32_Command_struct __user *) arg; | |
6059 | IOCTL_Command_struct arg64; | |
6060 | IOCTL_Command_struct __user *p = compat_alloc_user_space(sizeof(arg64)); | |
6061 | int err; | |
6062 | u32 cp; | |
6063 | ||
938abd84 | 6064 | memset(&arg64, 0, sizeof(arg64)); |
edd16368 SC |
6065 | err = 0; |
6066 | err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info, | |
6067 | sizeof(arg64.LUN_info)); | |
6068 | err |= copy_from_user(&arg64.Request, &arg32->Request, | |
6069 | sizeof(arg64.Request)); | |
6070 | err |= copy_from_user(&arg64.error_info, &arg32->error_info, | |
6071 | sizeof(arg64.error_info)); | |
6072 | err |= get_user(arg64.buf_size, &arg32->buf_size); | |
6073 | err |= get_user(cp, &arg32->buf); | |
6074 | arg64.buf = compat_ptr(cp); | |
6075 | err |= copy_to_user(p, &arg64, sizeof(arg64)); | |
6076 | ||
6077 | if (err) | |
6078 | return -EFAULT; | |
6079 | ||
42a91641 | 6080 | err = hpsa_ioctl(dev, CCISS_PASSTHRU, p); |
edd16368 SC |
6081 | if (err) |
6082 | return err; | |
6083 | err |= copy_in_user(&arg32->error_info, &p->error_info, | |
6084 | sizeof(arg32->error_info)); | |
6085 | if (err) | |
6086 | return -EFAULT; | |
6087 | return err; | |
6088 | } | |
6089 | ||
6090 | static int hpsa_ioctl32_big_passthru(struct scsi_device *dev, | |
42a91641 | 6091 | int cmd, void __user *arg) |
edd16368 SC |
6092 | { |
6093 | BIG_IOCTL32_Command_struct __user *arg32 = | |
6094 | (BIG_IOCTL32_Command_struct __user *) arg; | |
6095 | BIG_IOCTL_Command_struct arg64; | |
6096 | BIG_IOCTL_Command_struct __user *p = | |
6097 | compat_alloc_user_space(sizeof(arg64)); | |
6098 | int err; | |
6099 | u32 cp; | |
6100 | ||
938abd84 | 6101 | memset(&arg64, 0, sizeof(arg64)); |
edd16368 SC |
6102 | err = 0; |
6103 | err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info, | |
6104 | sizeof(arg64.LUN_info)); | |
6105 | err |= copy_from_user(&arg64.Request, &arg32->Request, | |
6106 | sizeof(arg64.Request)); | |
6107 | err |= copy_from_user(&arg64.error_info, &arg32->error_info, | |
6108 | sizeof(arg64.error_info)); | |
6109 | err |= get_user(arg64.buf_size, &arg32->buf_size); | |
6110 | err |= get_user(arg64.malloc_size, &arg32->malloc_size); | |
6111 | err |= get_user(cp, &arg32->buf); | |
6112 | arg64.buf = compat_ptr(cp); | |
6113 | err |= copy_to_user(p, &arg64, sizeof(arg64)); | |
6114 | ||
6115 | if (err) | |
6116 | return -EFAULT; | |
6117 | ||
42a91641 | 6118 | err = hpsa_ioctl(dev, CCISS_BIG_PASSTHRU, p); |
edd16368 SC |
6119 | if (err) |
6120 | return err; | |
6121 | err |= copy_in_user(&arg32->error_info, &p->error_info, | |
6122 | sizeof(arg32->error_info)); | |
6123 | if (err) | |
6124 | return -EFAULT; | |
6125 | return err; | |
6126 | } | |
71fe75a7 | 6127 | |
42a91641 | 6128 | static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void __user *arg) |
71fe75a7 SC |
6129 | { |
6130 | switch (cmd) { | |
6131 | case CCISS_GETPCIINFO: | |
6132 | case CCISS_GETINTINFO: | |
6133 | case CCISS_SETINTINFO: | |
6134 | case CCISS_GETNODENAME: | |
6135 | case CCISS_SETNODENAME: | |
6136 | case CCISS_GETHEARTBEAT: | |
6137 | case CCISS_GETBUSTYPES: | |
6138 | case CCISS_GETFIRMVER: | |
6139 | case CCISS_GETDRIVVER: | |
6140 | case CCISS_REVALIDVOLS: | |
6141 | case CCISS_DEREGDISK: | |
6142 | case CCISS_REGNEWDISK: | |
6143 | case CCISS_REGNEWD: | |
6144 | case CCISS_RESCANDISK: | |
6145 | case CCISS_GETLUNINFO: | |
6146 | return hpsa_ioctl(dev, cmd, arg); | |
6147 | ||
6148 | case CCISS_PASSTHRU32: | |
6149 | return hpsa_ioctl32_passthru(dev, cmd, arg); | |
6150 | case CCISS_BIG_PASSTHRU32: | |
6151 | return hpsa_ioctl32_big_passthru(dev, cmd, arg); | |
6152 | ||
6153 | default: | |
6154 | return -ENOIOCTLCMD; | |
6155 | } | |
6156 | } | |
edd16368 SC |
6157 | #endif |
6158 | ||
6159 | static int hpsa_getpciinfo_ioctl(struct ctlr_info *h, void __user *argp) | |
6160 | { | |
6161 | struct hpsa_pci_info pciinfo; | |
6162 | ||
6163 | if (!argp) | |
6164 | return -EINVAL; | |
6165 | pciinfo.domain = pci_domain_nr(h->pdev->bus); | |
6166 | pciinfo.bus = h->pdev->bus->number; | |
6167 | pciinfo.dev_fn = h->pdev->devfn; | |
6168 | pciinfo.board_id = h->board_id; | |
6169 | if (copy_to_user(argp, &pciinfo, sizeof(pciinfo))) | |
6170 | return -EFAULT; | |
6171 | return 0; | |
6172 | } | |
6173 | ||
6174 | static int hpsa_getdrivver_ioctl(struct ctlr_info *h, void __user *argp) | |
6175 | { | |
6176 | DriverVer_type DriverVer; | |
6177 | unsigned char vmaj, vmin, vsubmin; | |
6178 | int rc; | |
6179 | ||
6180 | rc = sscanf(HPSA_DRIVER_VERSION, "%hhu.%hhu.%hhu", | |
6181 | &vmaj, &vmin, &vsubmin); | |
6182 | if (rc != 3) { | |
6183 | dev_info(&h->pdev->dev, "driver version string '%s' " | |
6184 | "unrecognized.", HPSA_DRIVER_VERSION); | |
6185 | vmaj = 0; | |
6186 | vmin = 0; | |
6187 | vsubmin = 0; | |
6188 | } | |
6189 | DriverVer = (vmaj << 16) | (vmin << 8) | vsubmin; | |
6190 | if (!argp) | |
6191 | return -EINVAL; | |
6192 | if (copy_to_user(argp, &DriverVer, sizeof(DriverVer_type))) | |
6193 | return -EFAULT; | |
6194 | return 0; | |
6195 | } | |
6196 | ||
6197 | static int hpsa_passthru_ioctl(struct ctlr_info *h, void __user *argp) | |
6198 | { | |
6199 | IOCTL_Command_struct iocommand; | |
6200 | struct CommandList *c; | |
6201 | char *buff = NULL; | |
50a0decf | 6202 | u64 temp64; |
c1f63c8f | 6203 | int rc = 0; |
edd16368 SC |
6204 | |
6205 | if (!argp) | |
6206 | return -EINVAL; | |
6207 | if (!capable(CAP_SYS_RAWIO)) | |
6208 | return -EPERM; | |
6209 | if (copy_from_user(&iocommand, argp, sizeof(iocommand))) | |
6210 | return -EFAULT; | |
6211 | if ((iocommand.buf_size < 1) && | |
6212 | (iocommand.Request.Type.Direction != XFER_NONE)) { | |
6213 | return -EINVAL; | |
6214 | } | |
6215 | if (iocommand.buf_size > 0) { | |
6216 | buff = kmalloc(iocommand.buf_size, GFP_KERNEL); | |
6217 | if (buff == NULL) | |
2dd02d74 | 6218 | return -ENOMEM; |
9233fb10 | 6219 | if (iocommand.Request.Type.Direction & XFER_WRITE) { |
b03a7771 SC |
6220 | /* Copy the data into the buffer we created */ |
6221 | if (copy_from_user(buff, iocommand.buf, | |
6222 | iocommand.buf_size)) { | |
c1f63c8f SC |
6223 | rc = -EFAULT; |
6224 | goto out_kfree; | |
b03a7771 SC |
6225 | } |
6226 | } else { | |
6227 | memset(buff, 0, iocommand.buf_size); | |
edd16368 | 6228 | } |
b03a7771 | 6229 | } |
45fcb86e | 6230 | c = cmd_alloc(h); |
bf43caf3 | 6231 | |
edd16368 SC |
6232 | /* Fill in the command type */ |
6233 | c->cmd_type = CMD_IOCTL_PEND; | |
a58e7e53 | 6234 | c->scsi_cmd = SCSI_CMD_BUSY; |
edd16368 SC |
6235 | /* Fill in Command Header */ |
6236 | c->Header.ReplyQueue = 0; /* unused in simple mode */ | |
6237 | if (iocommand.buf_size > 0) { /* buffer to fill */ | |
6238 | c->Header.SGList = 1; | |
50a0decf | 6239 | c->Header.SGTotal = cpu_to_le16(1); |
edd16368 SC |
6240 | } else { /* no buffers to fill */ |
6241 | c->Header.SGList = 0; | |
50a0decf | 6242 | c->Header.SGTotal = cpu_to_le16(0); |
edd16368 SC |
6243 | } |
6244 | memcpy(&c->Header.LUN, &iocommand.LUN_info, sizeof(c->Header.LUN)); | |
edd16368 SC |
6245 | |
6246 | /* Fill in Request block */ | |
6247 | memcpy(&c->Request, &iocommand.Request, | |
6248 | sizeof(c->Request)); | |
6249 | ||
6250 | /* Fill in the scatter gather information */ | |
6251 | if (iocommand.buf_size > 0) { | |
50a0decf | 6252 | temp64 = pci_map_single(h->pdev, buff, |
edd16368 | 6253 | iocommand.buf_size, PCI_DMA_BIDIRECTIONAL); |
50a0decf SC |
6254 | if (dma_mapping_error(&h->pdev->dev, (dma_addr_t) temp64)) { |
6255 | c->SG[0].Addr = cpu_to_le64(0); | |
6256 | c->SG[0].Len = cpu_to_le32(0); | |
bcc48ffa SC |
6257 | rc = -ENOMEM; |
6258 | goto out; | |
6259 | } | |
50a0decf SC |
6260 | c->SG[0].Addr = cpu_to_le64(temp64); |
6261 | c->SG[0].Len = cpu_to_le32(iocommand.buf_size); | |
6262 | c->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* not chaining */ | |
edd16368 | 6263 | } |
25163bd5 | 6264 | rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT); |
c2dd32e0 SC |
6265 | if (iocommand.buf_size > 0) |
6266 | hpsa_pci_unmap(h->pdev, c, 1, PCI_DMA_BIDIRECTIONAL); | |
edd16368 | 6267 | check_ioctl_unit_attention(h, c); |
25163bd5 WS |
6268 | if (rc) { |
6269 | rc = -EIO; | |
6270 | goto out; | |
6271 | } | |
edd16368 SC |
6272 | |
6273 | /* Copy the error information out */ | |
6274 | memcpy(&iocommand.error_info, c->err_info, | |
6275 | sizeof(iocommand.error_info)); | |
6276 | if (copy_to_user(argp, &iocommand, sizeof(iocommand))) { | |
c1f63c8f SC |
6277 | rc = -EFAULT; |
6278 | goto out; | |
edd16368 | 6279 | } |
9233fb10 | 6280 | if ((iocommand.Request.Type.Direction & XFER_READ) && |
b03a7771 | 6281 | iocommand.buf_size > 0) { |
edd16368 SC |
6282 | /* Copy the data out of the buffer we created */ |
6283 | if (copy_to_user(iocommand.buf, buff, iocommand.buf_size)) { | |
c1f63c8f SC |
6284 | rc = -EFAULT; |
6285 | goto out; | |
edd16368 SC |
6286 | } |
6287 | } | |
c1f63c8f | 6288 | out: |
45fcb86e | 6289 | cmd_free(h, c); |
c1f63c8f SC |
6290 | out_kfree: |
6291 | kfree(buff); | |
6292 | return rc; | |
edd16368 SC |
6293 | } |
6294 | ||
6295 | static int hpsa_big_passthru_ioctl(struct ctlr_info *h, void __user *argp) | |
6296 | { | |
6297 | BIG_IOCTL_Command_struct *ioc; | |
6298 | struct CommandList *c; | |
6299 | unsigned char **buff = NULL; | |
6300 | int *buff_size = NULL; | |
50a0decf | 6301 | u64 temp64; |
edd16368 SC |
6302 | BYTE sg_used = 0; |
6303 | int status = 0; | |
01a02ffc SC |
6304 | u32 left; |
6305 | u32 sz; | |
edd16368 SC |
6306 | BYTE __user *data_ptr; |
6307 | ||
6308 | if (!argp) | |
6309 | return -EINVAL; | |
6310 | if (!capable(CAP_SYS_RAWIO)) | |
6311 | return -EPERM; | |
6312 | ioc = (BIG_IOCTL_Command_struct *) | |
6313 | kmalloc(sizeof(*ioc), GFP_KERNEL); | |
6314 | if (!ioc) { | |
6315 | status = -ENOMEM; | |
6316 | goto cleanup1; | |
6317 | } | |
6318 | if (copy_from_user(ioc, argp, sizeof(*ioc))) { | |
6319 | status = -EFAULT; | |
6320 | goto cleanup1; | |
6321 | } | |
6322 | if ((ioc->buf_size < 1) && | |
6323 | (ioc->Request.Type.Direction != XFER_NONE)) { | |
6324 | status = -EINVAL; | |
6325 | goto cleanup1; | |
6326 | } | |
6327 | /* Check kmalloc limits using all SGs */ | |
6328 | if (ioc->malloc_size > MAX_KMALLOC_SIZE) { | |
6329 | status = -EINVAL; | |
6330 | goto cleanup1; | |
6331 | } | |
d66ae08b | 6332 | if (ioc->buf_size > ioc->malloc_size * SG_ENTRIES_IN_CMD) { |
edd16368 SC |
6333 | status = -EINVAL; |
6334 | goto cleanup1; | |
6335 | } | |
d66ae08b | 6336 | buff = kzalloc(SG_ENTRIES_IN_CMD * sizeof(char *), GFP_KERNEL); |
edd16368 SC |
6337 | if (!buff) { |
6338 | status = -ENOMEM; | |
6339 | goto cleanup1; | |
6340 | } | |
d66ae08b | 6341 | buff_size = kmalloc(SG_ENTRIES_IN_CMD * sizeof(int), GFP_KERNEL); |
edd16368 SC |
6342 | if (!buff_size) { |
6343 | status = -ENOMEM; | |
6344 | goto cleanup1; | |
6345 | } | |
6346 | left = ioc->buf_size; | |
6347 | data_ptr = ioc->buf; | |
6348 | while (left) { | |
6349 | sz = (left > ioc->malloc_size) ? ioc->malloc_size : left; | |
6350 | buff_size[sg_used] = sz; | |
6351 | buff[sg_used] = kmalloc(sz, GFP_KERNEL); | |
6352 | if (buff[sg_used] == NULL) { | |
6353 | status = -ENOMEM; | |
6354 | goto cleanup1; | |
6355 | } | |
9233fb10 | 6356 | if (ioc->Request.Type.Direction & XFER_WRITE) { |
edd16368 | 6357 | if (copy_from_user(buff[sg_used], data_ptr, sz)) { |
0758f4f7 | 6358 | status = -EFAULT; |
edd16368 SC |
6359 | goto cleanup1; |
6360 | } | |
6361 | } else | |
6362 | memset(buff[sg_used], 0, sz); | |
6363 | left -= sz; | |
6364 | data_ptr += sz; | |
6365 | sg_used++; | |
6366 | } | |
45fcb86e | 6367 | c = cmd_alloc(h); |
bf43caf3 | 6368 | |
edd16368 | 6369 | c->cmd_type = CMD_IOCTL_PEND; |
a58e7e53 | 6370 | c->scsi_cmd = SCSI_CMD_BUSY; |
edd16368 | 6371 | c->Header.ReplyQueue = 0; |
50a0decf SC |
6372 | c->Header.SGList = (u8) sg_used; |
6373 | c->Header.SGTotal = cpu_to_le16(sg_used); | |
edd16368 | 6374 | memcpy(&c->Header.LUN, &ioc->LUN_info, sizeof(c->Header.LUN)); |
edd16368 SC |
6375 | memcpy(&c->Request, &ioc->Request, sizeof(c->Request)); |
6376 | if (ioc->buf_size > 0) { | |
6377 | int i; | |
6378 | for (i = 0; i < sg_used; i++) { | |
50a0decf | 6379 | temp64 = pci_map_single(h->pdev, buff[i], |
edd16368 | 6380 | buff_size[i], PCI_DMA_BIDIRECTIONAL); |
50a0decf SC |
6381 | if (dma_mapping_error(&h->pdev->dev, |
6382 | (dma_addr_t) temp64)) { | |
6383 | c->SG[i].Addr = cpu_to_le64(0); | |
6384 | c->SG[i].Len = cpu_to_le32(0); | |
bcc48ffa SC |
6385 | hpsa_pci_unmap(h->pdev, c, i, |
6386 | PCI_DMA_BIDIRECTIONAL); | |
6387 | status = -ENOMEM; | |
e2d4a1f6 | 6388 | goto cleanup0; |
bcc48ffa | 6389 | } |
50a0decf SC |
6390 | c->SG[i].Addr = cpu_to_le64(temp64); |
6391 | c->SG[i].Len = cpu_to_le32(buff_size[i]); | |
6392 | c->SG[i].Ext = cpu_to_le32(0); | |
edd16368 | 6393 | } |
50a0decf | 6394 | c->SG[--i].Ext = cpu_to_le32(HPSA_SG_LAST); |
edd16368 | 6395 | } |
25163bd5 | 6396 | status = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT); |
b03a7771 SC |
6397 | if (sg_used) |
6398 | hpsa_pci_unmap(h->pdev, c, sg_used, PCI_DMA_BIDIRECTIONAL); | |
edd16368 | 6399 | check_ioctl_unit_attention(h, c); |
25163bd5 WS |
6400 | if (status) { |
6401 | status = -EIO; | |
6402 | goto cleanup0; | |
6403 | } | |
6404 | ||
edd16368 SC |
6405 | /* Copy the error information out */ |
6406 | memcpy(&ioc->error_info, c->err_info, sizeof(ioc->error_info)); | |
6407 | if (copy_to_user(argp, ioc, sizeof(*ioc))) { | |
edd16368 | 6408 | status = -EFAULT; |
e2d4a1f6 | 6409 | goto cleanup0; |
edd16368 | 6410 | } |
9233fb10 | 6411 | if ((ioc->Request.Type.Direction & XFER_READ) && ioc->buf_size > 0) { |
2b08b3e9 DB |
6412 | int i; |
6413 | ||
edd16368 SC |
6414 | /* Copy the data out of the buffer we created */ |
6415 | BYTE __user *ptr = ioc->buf; | |
6416 | for (i = 0; i < sg_used; i++) { | |
6417 | if (copy_to_user(ptr, buff[i], buff_size[i])) { | |
edd16368 | 6418 | status = -EFAULT; |
e2d4a1f6 | 6419 | goto cleanup0; |
edd16368 SC |
6420 | } |
6421 | ptr += buff_size[i]; | |
6422 | } | |
6423 | } | |
edd16368 | 6424 | status = 0; |
e2d4a1f6 | 6425 | cleanup0: |
45fcb86e | 6426 | cmd_free(h, c); |
edd16368 SC |
6427 | cleanup1: |
6428 | if (buff) { | |
2b08b3e9 DB |
6429 | int i; |
6430 | ||
edd16368 SC |
6431 | for (i = 0; i < sg_used; i++) |
6432 | kfree(buff[i]); | |
6433 | kfree(buff); | |
6434 | } | |
6435 | kfree(buff_size); | |
6436 | kfree(ioc); | |
6437 | return status; | |
6438 | } | |
6439 | ||
6440 | static void check_ioctl_unit_attention(struct ctlr_info *h, | |
6441 | struct CommandList *c) | |
6442 | { | |
6443 | if (c->err_info->CommandStatus == CMD_TARGET_STATUS && | |
6444 | c->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION) | |
6445 | (void) check_for_unit_attention(h, c); | |
6446 | } | |
0390f0c0 | 6447 | |
edd16368 SC |
6448 | /* |
6449 | * ioctl | |
6450 | */ | |
42a91641 | 6451 | static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg) |
edd16368 SC |
6452 | { |
6453 | struct ctlr_info *h; | |
6454 | void __user *argp = (void __user *)arg; | |
0390f0c0 | 6455 | int rc; |
edd16368 SC |
6456 | |
6457 | h = sdev_to_hba(dev); | |
6458 | ||
6459 | switch (cmd) { | |
6460 | case CCISS_DEREGDISK: | |
6461 | case CCISS_REGNEWDISK: | |
6462 | case CCISS_REGNEWD: | |
a08a8471 | 6463 | hpsa_scan_start(h->scsi_host); |
edd16368 SC |
6464 | return 0; |
6465 | case CCISS_GETPCIINFO: | |
6466 | return hpsa_getpciinfo_ioctl(h, argp); | |
6467 | case CCISS_GETDRIVVER: | |
6468 | return hpsa_getdrivver_ioctl(h, argp); | |
6469 | case CCISS_PASSTHRU: | |
34f0c627 | 6470 | if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0) |
0390f0c0 SC |
6471 | return -EAGAIN; |
6472 | rc = hpsa_passthru_ioctl(h, argp); | |
34f0c627 | 6473 | atomic_inc(&h->passthru_cmds_avail); |
0390f0c0 | 6474 | return rc; |
edd16368 | 6475 | case CCISS_BIG_PASSTHRU: |
34f0c627 | 6476 | if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0) |
0390f0c0 SC |
6477 | return -EAGAIN; |
6478 | rc = hpsa_big_passthru_ioctl(h, argp); | |
34f0c627 | 6479 | atomic_inc(&h->passthru_cmds_avail); |
0390f0c0 | 6480 | return rc; |
edd16368 SC |
6481 | default: |
6482 | return -ENOTTY; | |
6483 | } | |
6484 | } | |
6485 | ||
bf43caf3 | 6486 | static void hpsa_send_host_reset(struct ctlr_info *h, unsigned char *scsi3addr, |
6f039790 | 6487 | u8 reset_type) |
64670ac8 SC |
6488 | { |
6489 | struct CommandList *c; | |
6490 | ||
6491 | c = cmd_alloc(h); | |
bf43caf3 | 6492 | |
a2dac136 SC |
6493 | /* fill_cmd can't fail here, no data buffer to map */ |
6494 | (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0, | |
64670ac8 SC |
6495 | RAID_CTLR_LUNID, TYPE_MSG); |
6496 | c->Request.CDB[1] = reset_type; /* fill_cmd defaults to target reset */ | |
6497 | c->waiting = NULL; | |
6498 | enqueue_cmd_and_start_io(h, c); | |
6499 | /* Don't wait for completion, the reset won't complete. Don't free | |
6500 | * the command either. This is the last command we will send before | |
6501 | * re-initializing everything, so it doesn't matter and won't leak. | |
6502 | */ | |
bf43caf3 | 6503 | return; |
64670ac8 SC |
6504 | } |
6505 | ||
a2dac136 | 6506 | static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h, |
b7bb24eb | 6507 | void *buff, size_t size, u16 page_code, unsigned char *scsi3addr, |
edd16368 SC |
6508 | int cmd_type) |
6509 | { | |
6510 | int pci_dir = XFER_NONE; | |
9b5c48c2 | 6511 | u64 tag; /* for commands to be aborted */ |
edd16368 SC |
6512 | |
6513 | c->cmd_type = CMD_IOCTL_PEND; | |
a58e7e53 | 6514 | c->scsi_cmd = SCSI_CMD_BUSY; |
edd16368 SC |
6515 | c->Header.ReplyQueue = 0; |
6516 | if (buff != NULL && size > 0) { | |
6517 | c->Header.SGList = 1; | |
50a0decf | 6518 | c->Header.SGTotal = cpu_to_le16(1); |
edd16368 SC |
6519 | } else { |
6520 | c->Header.SGList = 0; | |
50a0decf | 6521 | c->Header.SGTotal = cpu_to_le16(0); |
edd16368 | 6522 | } |
edd16368 SC |
6523 | memcpy(c->Header.LUN.LunAddrBytes, scsi3addr, 8); |
6524 | ||
edd16368 SC |
6525 | if (cmd_type == TYPE_CMD) { |
6526 | switch (cmd) { | |
6527 | case HPSA_INQUIRY: | |
6528 | /* are we trying to read a vital product page */ | |
b7bb24eb | 6529 | if (page_code & VPD_PAGE) { |
edd16368 | 6530 | c->Request.CDB[1] = 0x01; |
b7bb24eb | 6531 | c->Request.CDB[2] = (page_code & 0xff); |
edd16368 SC |
6532 | } |
6533 | c->Request.CDBLen = 6; | |
a505b86f SC |
6534 | c->Request.type_attr_dir = |
6535 | TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ); | |
edd16368 SC |
6536 | c->Request.Timeout = 0; |
6537 | c->Request.CDB[0] = HPSA_INQUIRY; | |
6538 | c->Request.CDB[4] = size & 0xFF; | |
6539 | break; | |
6540 | case HPSA_REPORT_LOG: | |
6541 | case HPSA_REPORT_PHYS: | |
6542 | /* Talking to controller so It's a physical command | |
6543 | mode = 00 target = 0. Nothing to write. | |
6544 | */ | |
6545 | c->Request.CDBLen = 12; | |
a505b86f SC |
6546 | c->Request.type_attr_dir = |
6547 | TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ); | |
edd16368 SC |
6548 | c->Request.Timeout = 0; |
6549 | c->Request.CDB[0] = cmd; | |
6550 | c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */ | |
6551 | c->Request.CDB[7] = (size >> 16) & 0xFF; | |
6552 | c->Request.CDB[8] = (size >> 8) & 0xFF; | |
6553 | c->Request.CDB[9] = size & 0xFF; | |
6554 | break; | |
c2adae44 ST |
6555 | case BMIC_SENSE_DIAG_OPTIONS: |
6556 | c->Request.CDBLen = 16; | |
6557 | c->Request.type_attr_dir = | |
6558 | TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ); | |
6559 | c->Request.Timeout = 0; | |
6560 | /* Spec says this should be BMIC_WRITE */ | |
6561 | c->Request.CDB[0] = BMIC_READ; | |
6562 | c->Request.CDB[6] = BMIC_SENSE_DIAG_OPTIONS; | |
6563 | break; | |
6564 | case BMIC_SET_DIAG_OPTIONS: | |
6565 | c->Request.CDBLen = 16; | |
6566 | c->Request.type_attr_dir = | |
6567 | TYPE_ATTR_DIR(cmd_type, | |
6568 | ATTR_SIMPLE, XFER_WRITE); | |
6569 | c->Request.Timeout = 0; | |
6570 | c->Request.CDB[0] = BMIC_WRITE; | |
6571 | c->Request.CDB[6] = BMIC_SET_DIAG_OPTIONS; | |
6572 | break; | |
edd16368 SC |
6573 | case HPSA_CACHE_FLUSH: |
6574 | c->Request.CDBLen = 12; | |
a505b86f SC |
6575 | c->Request.type_attr_dir = |
6576 | TYPE_ATTR_DIR(cmd_type, | |
6577 | ATTR_SIMPLE, XFER_WRITE); | |
edd16368 SC |
6578 | c->Request.Timeout = 0; |
6579 | c->Request.CDB[0] = BMIC_WRITE; | |
6580 | c->Request.CDB[6] = BMIC_CACHE_FLUSH; | |
bb158eab SC |
6581 | c->Request.CDB[7] = (size >> 8) & 0xFF; |
6582 | c->Request.CDB[8] = size & 0xFF; | |
edd16368 SC |
6583 | break; |
6584 | case TEST_UNIT_READY: | |
6585 | c->Request.CDBLen = 6; | |
a505b86f SC |
6586 | c->Request.type_attr_dir = |
6587 | TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE); | |
edd16368 SC |
6588 | c->Request.Timeout = 0; |
6589 | break; | |
283b4a9b SC |
6590 | case HPSA_GET_RAID_MAP: |
6591 | c->Request.CDBLen = 12; | |
a505b86f SC |
6592 | c->Request.type_attr_dir = |
6593 | TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ); | |
283b4a9b SC |
6594 | c->Request.Timeout = 0; |
6595 | c->Request.CDB[0] = HPSA_CISS_READ; | |
6596 | c->Request.CDB[1] = cmd; | |
6597 | c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */ | |
6598 | c->Request.CDB[7] = (size >> 16) & 0xFF; | |
6599 | c->Request.CDB[8] = (size >> 8) & 0xFF; | |
6600 | c->Request.CDB[9] = size & 0xFF; | |
6601 | break; | |
316b221a SC |
6602 | case BMIC_SENSE_CONTROLLER_PARAMETERS: |
6603 | c->Request.CDBLen = 10; | |
a505b86f SC |
6604 | c->Request.type_attr_dir = |
6605 | TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ); | |
316b221a SC |
6606 | c->Request.Timeout = 0; |
6607 | c->Request.CDB[0] = BMIC_READ; | |
6608 | c->Request.CDB[6] = BMIC_SENSE_CONTROLLER_PARAMETERS; | |
6609 | c->Request.CDB[7] = (size >> 16) & 0xFF; | |
6610 | c->Request.CDB[8] = (size >> 8) & 0xFF; | |
6611 | break; | |
03383736 DB |
6612 | case BMIC_IDENTIFY_PHYSICAL_DEVICE: |
6613 | c->Request.CDBLen = 10; | |
6614 | c->Request.type_attr_dir = | |
6615 | TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ); | |
6616 | c->Request.Timeout = 0; | |
6617 | c->Request.CDB[0] = BMIC_READ; | |
6618 | c->Request.CDB[6] = BMIC_IDENTIFY_PHYSICAL_DEVICE; | |
6619 | c->Request.CDB[7] = (size >> 16) & 0xFF; | |
6620 | c->Request.CDB[8] = (size >> 8) & 0XFF; | |
6621 | break; | |
d04e62b9 KB |
6622 | case BMIC_SENSE_SUBSYSTEM_INFORMATION: |
6623 | c->Request.CDBLen = 10; | |
6624 | c->Request.type_attr_dir = | |
6625 | TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ); | |
6626 | c->Request.Timeout = 0; | |
6627 | c->Request.CDB[0] = BMIC_READ; | |
6628 | c->Request.CDB[6] = BMIC_SENSE_SUBSYSTEM_INFORMATION; | |
6629 | c->Request.CDB[7] = (size >> 16) & 0xFF; | |
6630 | c->Request.CDB[8] = (size >> 8) & 0XFF; | |
6631 | break; | |
66749d0d ST |
6632 | case BMIC_IDENTIFY_CONTROLLER: |
6633 | c->Request.CDBLen = 10; | |
6634 | c->Request.type_attr_dir = | |
6635 | TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ); | |
6636 | c->Request.Timeout = 0; | |
6637 | c->Request.CDB[0] = BMIC_READ; | |
6638 | c->Request.CDB[1] = 0; | |
6639 | c->Request.CDB[2] = 0; | |
6640 | c->Request.CDB[3] = 0; | |
6641 | c->Request.CDB[4] = 0; | |
6642 | c->Request.CDB[5] = 0; | |
6643 | c->Request.CDB[6] = BMIC_IDENTIFY_CONTROLLER; | |
6644 | c->Request.CDB[7] = (size >> 16) & 0xFF; | |
6645 | c->Request.CDB[8] = (size >> 8) & 0XFF; | |
6646 | c->Request.CDB[9] = 0; | |
6647 | break; | |
edd16368 SC |
6648 | default: |
6649 | dev_warn(&h->pdev->dev, "unknown command 0x%c\n", cmd); | |
6650 | BUG(); | |
a2dac136 | 6651 | return -1; |
edd16368 SC |
6652 | } |
6653 | } else if (cmd_type == TYPE_MSG) { | |
6654 | switch (cmd) { | |
6655 | ||
0b9b7b6e ST |
6656 | case HPSA_PHYS_TARGET_RESET: |
6657 | c->Request.CDBLen = 16; | |
6658 | c->Request.type_attr_dir = | |
6659 | TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE); | |
6660 | c->Request.Timeout = 0; /* Don't time out */ | |
6661 | memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB)); | |
6662 | c->Request.CDB[0] = HPSA_RESET; | |
6663 | c->Request.CDB[1] = HPSA_TARGET_RESET_TYPE; | |
6664 | /* Physical target reset needs no control bytes 4-7*/ | |
6665 | c->Request.CDB[4] = 0x00; | |
6666 | c->Request.CDB[5] = 0x00; | |
6667 | c->Request.CDB[6] = 0x00; | |
6668 | c->Request.CDB[7] = 0x00; | |
6669 | break; | |
edd16368 SC |
6670 | case HPSA_DEVICE_RESET_MSG: |
6671 | c->Request.CDBLen = 16; | |
a505b86f SC |
6672 | c->Request.type_attr_dir = |
6673 | TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE); | |
edd16368 | 6674 | c->Request.Timeout = 0; /* Don't time out */ |
64670ac8 SC |
6675 | memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB)); |
6676 | c->Request.CDB[0] = cmd; | |
21e89afd | 6677 | c->Request.CDB[1] = HPSA_RESET_TYPE_LUN; |
edd16368 SC |
6678 | /* If bytes 4-7 are zero, it means reset the */ |
6679 | /* LunID device */ | |
6680 | c->Request.CDB[4] = 0x00; | |
6681 | c->Request.CDB[5] = 0x00; | |
6682 | c->Request.CDB[6] = 0x00; | |
6683 | c->Request.CDB[7] = 0x00; | |
75167d2c SC |
6684 | break; |
6685 | case HPSA_ABORT_MSG: | |
9b5c48c2 | 6686 | memcpy(&tag, buff, sizeof(tag)); |
2b08b3e9 | 6687 | dev_dbg(&h->pdev->dev, |
9b5c48c2 SC |
6688 | "Abort Tag:0x%016llx using rqst Tag:0x%016llx", |
6689 | tag, c->Header.tag); | |
75167d2c | 6690 | c->Request.CDBLen = 16; |
a505b86f SC |
6691 | c->Request.type_attr_dir = |
6692 | TYPE_ATTR_DIR(cmd_type, | |
6693 | ATTR_SIMPLE, XFER_WRITE); | |
75167d2c SC |
6694 | c->Request.Timeout = 0; /* Don't time out */ |
6695 | c->Request.CDB[0] = HPSA_TASK_MANAGEMENT; | |
6696 | c->Request.CDB[1] = HPSA_TMF_ABORT_TASK; | |
6697 | c->Request.CDB[2] = 0x00; /* reserved */ | |
6698 | c->Request.CDB[3] = 0x00; /* reserved */ | |
6699 | /* Tag to abort goes in CDB[4]-CDB[11] */ | |
9b5c48c2 | 6700 | memcpy(&c->Request.CDB[4], &tag, sizeof(tag)); |
75167d2c SC |
6701 | c->Request.CDB[12] = 0x00; /* reserved */ |
6702 | c->Request.CDB[13] = 0x00; /* reserved */ | |
6703 | c->Request.CDB[14] = 0x00; /* reserved */ | |
6704 | c->Request.CDB[15] = 0x00; /* reserved */ | |
edd16368 | 6705 | break; |
edd16368 SC |
6706 | default: |
6707 | dev_warn(&h->pdev->dev, "unknown message type %d\n", | |
6708 | cmd); | |
6709 | BUG(); | |
6710 | } | |
6711 | } else { | |
6712 | dev_warn(&h->pdev->dev, "unknown command type %d\n", cmd_type); | |
6713 | BUG(); | |
6714 | } | |
6715 | ||
a505b86f | 6716 | switch (GET_DIR(c->Request.type_attr_dir)) { |
edd16368 SC |
6717 | case XFER_READ: |
6718 | pci_dir = PCI_DMA_FROMDEVICE; | |
6719 | break; | |
6720 | case XFER_WRITE: | |
6721 | pci_dir = PCI_DMA_TODEVICE; | |
6722 | break; | |
6723 | case XFER_NONE: | |
6724 | pci_dir = PCI_DMA_NONE; | |
6725 | break; | |
6726 | default: | |
6727 | pci_dir = PCI_DMA_BIDIRECTIONAL; | |
6728 | } | |
a2dac136 SC |
6729 | if (hpsa_map_one(h->pdev, c, buff, size, pci_dir)) |
6730 | return -1; | |
6731 | return 0; | |
edd16368 SC |
6732 | } |
6733 | ||
6734 | /* | |
6735 | * Map (physical) PCI mem into (virtual) kernel space | |
6736 | */ | |
6737 | static void __iomem *remap_pci_mem(ulong base, ulong size) | |
6738 | { | |
6739 | ulong page_base = ((ulong) base) & PAGE_MASK; | |
6740 | ulong page_offs = ((ulong) base) - page_base; | |
088ba34c SC |
6741 | void __iomem *page_remapped = ioremap_nocache(page_base, |
6742 | page_offs + size); | |
edd16368 SC |
6743 | |
6744 | return page_remapped ? (page_remapped + page_offs) : NULL; | |
6745 | } | |
6746 | ||
254f796b | 6747 | static inline unsigned long get_next_completion(struct ctlr_info *h, u8 q) |
edd16368 | 6748 | { |
254f796b | 6749 | return h->access.command_completed(h, q); |
edd16368 SC |
6750 | } |
6751 | ||
900c5440 | 6752 | static inline bool interrupt_pending(struct ctlr_info *h) |
edd16368 SC |
6753 | { |
6754 | return h->access.intr_pending(h); | |
6755 | } | |
6756 | ||
6757 | static inline long interrupt_not_for_us(struct ctlr_info *h) | |
6758 | { | |
10f66018 SC |
6759 | return (h->access.intr_pending(h) == 0) || |
6760 | (h->interrupts_enabled == 0); | |
edd16368 SC |
6761 | } |
6762 | ||
01a02ffc SC |
6763 | static inline int bad_tag(struct ctlr_info *h, u32 tag_index, |
6764 | u32 raw_tag) | |
edd16368 SC |
6765 | { |
6766 | if (unlikely(tag_index >= h->nr_cmds)) { | |
6767 | dev_warn(&h->pdev->dev, "bad tag 0x%08x ignored.\n", raw_tag); | |
6768 | return 1; | |
6769 | } | |
6770 | return 0; | |
6771 | } | |
6772 | ||
5a3d16f5 | 6773 | static inline void finish_cmd(struct CommandList *c) |
edd16368 | 6774 | { |
e85c5974 | 6775 | dial_up_lockup_detection_on_fw_flash_complete(c->h, c); |
c349775e ST |
6776 | if (likely(c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_SCSI |
6777 | || c->cmd_type == CMD_IOACCEL2)) | |
1fb011fb | 6778 | complete_scsi_command(c); |
8be986cc | 6779 | else if (c->cmd_type == CMD_IOCTL_PEND || c->cmd_type == IOACCEL2_TMF) |
edd16368 | 6780 | complete(c->waiting); |
a104c99f SC |
6781 | } |
6782 | ||
303932fd | 6783 | /* process completion of an indexed ("direct lookup") command */ |
1d94f94d | 6784 | static inline void process_indexed_cmd(struct ctlr_info *h, |
303932fd DB |
6785 | u32 raw_tag) |
6786 | { | |
6787 | u32 tag_index; | |
6788 | struct CommandList *c; | |
6789 | ||
f2405db8 | 6790 | tag_index = raw_tag >> DIRECT_LOOKUP_SHIFT; |
1d94f94d SC |
6791 | if (!bad_tag(h, tag_index, raw_tag)) { |
6792 | c = h->cmd_pool + tag_index; | |
6793 | finish_cmd(c); | |
6794 | } | |
303932fd DB |
6795 | } |
6796 | ||
64670ac8 SC |
6797 | /* Some controllers, like p400, will give us one interrupt |
6798 | * after a soft reset, even if we turned interrupts off. | |
6799 | * Only need to check for this in the hpsa_xxx_discard_completions | |
6800 | * functions. | |
6801 | */ | |
6802 | static int ignore_bogus_interrupt(struct ctlr_info *h) | |
6803 | { | |
6804 | if (likely(!reset_devices)) | |
6805 | return 0; | |
6806 | ||
6807 | if (likely(h->interrupts_enabled)) | |
6808 | return 0; | |
6809 | ||
6810 | dev_info(&h->pdev->dev, "Received interrupt while interrupts disabled " | |
6811 | "(known firmware bug.) Ignoring.\n"); | |
6812 | ||
6813 | return 1; | |
6814 | } | |
6815 | ||
254f796b MG |
6816 | /* |
6817 | * Convert &h->q[x] (passed to interrupt handlers) back to h. | |
6818 | * Relies on (h-q[x] == x) being true for x such that | |
6819 | * 0 <= x < MAX_REPLY_QUEUES. | |
6820 | */ | |
6821 | static struct ctlr_info *queue_to_hba(u8 *queue) | |
64670ac8 | 6822 | { |
254f796b MG |
6823 | return container_of((queue - *queue), struct ctlr_info, q[0]); |
6824 | } | |
6825 | ||
6826 | static irqreturn_t hpsa_intx_discard_completions(int irq, void *queue) | |
6827 | { | |
6828 | struct ctlr_info *h = queue_to_hba(queue); | |
6829 | u8 q = *(u8 *) queue; | |
64670ac8 SC |
6830 | u32 raw_tag; |
6831 | ||
6832 | if (ignore_bogus_interrupt(h)) | |
6833 | return IRQ_NONE; | |
6834 | ||
6835 | if (interrupt_not_for_us(h)) | |
6836 | return IRQ_NONE; | |
a0c12413 | 6837 | h->last_intr_timestamp = get_jiffies_64(); |
64670ac8 | 6838 | while (interrupt_pending(h)) { |
254f796b | 6839 | raw_tag = get_next_completion(h, q); |
64670ac8 | 6840 | while (raw_tag != FIFO_EMPTY) |
254f796b | 6841 | raw_tag = next_command(h, q); |
64670ac8 | 6842 | } |
64670ac8 SC |
6843 | return IRQ_HANDLED; |
6844 | } | |
6845 | ||
254f796b | 6846 | static irqreturn_t hpsa_msix_discard_completions(int irq, void *queue) |
64670ac8 | 6847 | { |
254f796b | 6848 | struct ctlr_info *h = queue_to_hba(queue); |
64670ac8 | 6849 | u32 raw_tag; |
254f796b | 6850 | u8 q = *(u8 *) queue; |
64670ac8 SC |
6851 | |
6852 | if (ignore_bogus_interrupt(h)) | |
6853 | return IRQ_NONE; | |
6854 | ||
a0c12413 | 6855 | h->last_intr_timestamp = get_jiffies_64(); |
254f796b | 6856 | raw_tag = get_next_completion(h, q); |
64670ac8 | 6857 | while (raw_tag != FIFO_EMPTY) |
254f796b | 6858 | raw_tag = next_command(h, q); |
64670ac8 SC |
6859 | return IRQ_HANDLED; |
6860 | } | |
6861 | ||
254f796b | 6862 | static irqreturn_t do_hpsa_intr_intx(int irq, void *queue) |
edd16368 | 6863 | { |
254f796b | 6864 | struct ctlr_info *h = queue_to_hba((u8 *) queue); |
303932fd | 6865 | u32 raw_tag; |
254f796b | 6866 | u8 q = *(u8 *) queue; |
edd16368 SC |
6867 | |
6868 | if (interrupt_not_for_us(h)) | |
6869 | return IRQ_NONE; | |
a0c12413 | 6870 | h->last_intr_timestamp = get_jiffies_64(); |
10f66018 | 6871 | while (interrupt_pending(h)) { |
254f796b | 6872 | raw_tag = get_next_completion(h, q); |
10f66018 | 6873 | while (raw_tag != FIFO_EMPTY) { |
f2405db8 | 6874 | process_indexed_cmd(h, raw_tag); |
254f796b | 6875 | raw_tag = next_command(h, q); |
10f66018 SC |
6876 | } |
6877 | } | |
10f66018 SC |
6878 | return IRQ_HANDLED; |
6879 | } | |
6880 | ||
254f796b | 6881 | static irqreturn_t do_hpsa_intr_msi(int irq, void *queue) |
10f66018 | 6882 | { |
254f796b | 6883 | struct ctlr_info *h = queue_to_hba(queue); |
10f66018 | 6884 | u32 raw_tag; |
254f796b | 6885 | u8 q = *(u8 *) queue; |
10f66018 | 6886 | |
a0c12413 | 6887 | h->last_intr_timestamp = get_jiffies_64(); |
254f796b | 6888 | raw_tag = get_next_completion(h, q); |
303932fd | 6889 | while (raw_tag != FIFO_EMPTY) { |
f2405db8 | 6890 | process_indexed_cmd(h, raw_tag); |
254f796b | 6891 | raw_tag = next_command(h, q); |
edd16368 | 6892 | } |
edd16368 SC |
6893 | return IRQ_HANDLED; |
6894 | } | |
6895 | ||
a9a3a273 SC |
6896 | /* Send a message CDB to the firmware. Careful, this only works |
6897 | * in simple mode, not performant mode due to the tag lookup. | |
6898 | * We only ever use this immediately after a controller reset. | |
6899 | */ | |
6f039790 GKH |
6900 | static int hpsa_message(struct pci_dev *pdev, unsigned char opcode, |
6901 | unsigned char type) | |
edd16368 SC |
6902 | { |
6903 | struct Command { | |
6904 | struct CommandListHeader CommandHeader; | |
6905 | struct RequestBlock Request; | |
6906 | struct ErrDescriptor ErrorDescriptor; | |
6907 | }; | |
6908 | struct Command *cmd; | |
6909 | static const size_t cmd_sz = sizeof(*cmd) + | |
6910 | sizeof(cmd->ErrorDescriptor); | |
6911 | dma_addr_t paddr64; | |
2b08b3e9 DB |
6912 | __le32 paddr32; |
6913 | u32 tag; | |
edd16368 SC |
6914 | void __iomem *vaddr; |
6915 | int i, err; | |
6916 | ||
6917 | vaddr = pci_ioremap_bar(pdev, 0); | |
6918 | if (vaddr == NULL) | |
6919 | return -ENOMEM; | |
6920 | ||
6921 | /* The Inbound Post Queue only accepts 32-bit physical addresses for the | |
6922 | * CCISS commands, so they must be allocated from the lower 4GiB of | |
6923 | * memory. | |
6924 | */ | |
6925 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); | |
6926 | if (err) { | |
6927 | iounmap(vaddr); | |
1eaec8f3 | 6928 | return err; |
edd16368 SC |
6929 | } |
6930 | ||
6931 | cmd = pci_alloc_consistent(pdev, cmd_sz, &paddr64); | |
6932 | if (cmd == NULL) { | |
6933 | iounmap(vaddr); | |
6934 | return -ENOMEM; | |
6935 | } | |
6936 | ||
6937 | /* This must fit, because of the 32-bit consistent DMA mask. Also, | |
6938 | * although there's no guarantee, we assume that the address is at | |
6939 | * least 4-byte aligned (most likely, it's page-aligned). | |
6940 | */ | |
2b08b3e9 | 6941 | paddr32 = cpu_to_le32(paddr64); |
edd16368 SC |
6942 | |
6943 | cmd->CommandHeader.ReplyQueue = 0; | |
6944 | cmd->CommandHeader.SGList = 0; | |
50a0decf | 6945 | cmd->CommandHeader.SGTotal = cpu_to_le16(0); |
2b08b3e9 | 6946 | cmd->CommandHeader.tag = cpu_to_le64(paddr64); |
edd16368 SC |
6947 | memset(&cmd->CommandHeader.LUN.LunAddrBytes, 0, 8); |
6948 | ||
6949 | cmd->Request.CDBLen = 16; | |
a505b86f SC |
6950 | cmd->Request.type_attr_dir = |
6951 | TYPE_ATTR_DIR(TYPE_MSG, ATTR_HEADOFQUEUE, XFER_NONE); | |
edd16368 SC |
6952 | cmd->Request.Timeout = 0; /* Don't time out */ |
6953 | cmd->Request.CDB[0] = opcode; | |
6954 | cmd->Request.CDB[1] = type; | |
6955 | memset(&cmd->Request.CDB[2], 0, 14); /* rest of the CDB is reserved */ | |
50a0decf | 6956 | cmd->ErrorDescriptor.Addr = |
2b08b3e9 | 6957 | cpu_to_le64((le32_to_cpu(paddr32) + sizeof(*cmd))); |
50a0decf | 6958 | cmd->ErrorDescriptor.Len = cpu_to_le32(sizeof(struct ErrorInfo)); |
edd16368 | 6959 | |
2b08b3e9 | 6960 | writel(le32_to_cpu(paddr32), vaddr + SA5_REQUEST_PORT_OFFSET); |
edd16368 SC |
6961 | |
6962 | for (i = 0; i < HPSA_MSG_SEND_RETRY_LIMIT; i++) { | |
6963 | tag = readl(vaddr + SA5_REPLY_PORT_OFFSET); | |
2b08b3e9 | 6964 | if ((tag & ~HPSA_SIMPLE_ERROR_BITS) == paddr64) |
edd16368 SC |
6965 | break; |
6966 | msleep(HPSA_MSG_SEND_RETRY_INTERVAL_MSECS); | |
6967 | } | |
6968 | ||
6969 | iounmap(vaddr); | |
6970 | ||
6971 | /* we leak the DMA buffer here ... no choice since the controller could | |
6972 | * still complete the command. | |
6973 | */ | |
6974 | if (i == HPSA_MSG_SEND_RETRY_LIMIT) { | |
6975 | dev_err(&pdev->dev, "controller message %02x:%02x timed out\n", | |
6976 | opcode, type); | |
6977 | return -ETIMEDOUT; | |
6978 | } | |
6979 | ||
6980 | pci_free_consistent(pdev, cmd_sz, cmd, paddr64); | |
6981 | ||
6982 | if (tag & HPSA_ERROR_BIT) { | |
6983 | dev_err(&pdev->dev, "controller message %02x:%02x failed\n", | |
6984 | opcode, type); | |
6985 | return -EIO; | |
6986 | } | |
6987 | ||
6988 | dev_info(&pdev->dev, "controller message %02x:%02x succeeded\n", | |
6989 | opcode, type); | |
6990 | return 0; | |
6991 | } | |
6992 | ||
edd16368 SC |
6993 | #define hpsa_noop(p) hpsa_message(p, 3, 0) |
6994 | ||
1df8552a | 6995 | static int hpsa_controller_hard_reset(struct pci_dev *pdev, |
42a91641 | 6996 | void __iomem *vaddr, u32 use_doorbell) |
1df8552a | 6997 | { |
1df8552a SC |
6998 | |
6999 | if (use_doorbell) { | |
7000 | /* For everything after the P600, the PCI power state method | |
7001 | * of resetting the controller doesn't work, so we have this | |
7002 | * other way using the doorbell register. | |
7003 | */ | |
7004 | dev_info(&pdev->dev, "using doorbell to reset controller\n"); | |
cf0b08d0 | 7005 | writel(use_doorbell, vaddr + SA5_DOORBELL); |
85009239 | 7006 | |
00701a96 | 7007 | /* PMC hardware guys tell us we need a 10 second delay after |
85009239 SC |
7008 | * doorbell reset and before any attempt to talk to the board |
7009 | * at all to ensure that this actually works and doesn't fall | |
7010 | * over in some weird corner cases. | |
7011 | */ | |
00701a96 | 7012 | msleep(10000); |
1df8552a SC |
7013 | } else { /* Try to do it the PCI power state way */ |
7014 | ||
7015 | /* Quoting from the Open CISS Specification: "The Power | |
7016 | * Management Control/Status Register (CSR) controls the power | |
7017 | * state of the device. The normal operating state is D0, | |
7018 | * CSR=00h. The software off state is D3, CSR=03h. To reset | |
7019 | * the controller, place the interface device in D3 then to D0, | |
7020 | * this causes a secondary PCI reset which will reset the | |
7021 | * controller." */ | |
2662cab8 DB |
7022 | |
7023 | int rc = 0; | |
7024 | ||
1df8552a | 7025 | dev_info(&pdev->dev, "using PCI PM to reset controller\n"); |
2662cab8 | 7026 | |
1df8552a | 7027 | /* enter the D3hot power management state */ |
2662cab8 DB |
7028 | rc = pci_set_power_state(pdev, PCI_D3hot); |
7029 | if (rc) | |
7030 | return rc; | |
1df8552a SC |
7031 | |
7032 | msleep(500); | |
7033 | ||
7034 | /* enter the D0 power management state */ | |
2662cab8 DB |
7035 | rc = pci_set_power_state(pdev, PCI_D0); |
7036 | if (rc) | |
7037 | return rc; | |
c4853efe MM |
7038 | |
7039 | /* | |
7040 | * The P600 requires a small delay when changing states. | |
7041 | * Otherwise we may think the board did not reset and we bail. | |
7042 | * This for kdump only and is particular to the P600. | |
7043 | */ | |
7044 | msleep(500); | |
1df8552a SC |
7045 | } |
7046 | return 0; | |
7047 | } | |
7048 | ||
6f039790 | 7049 | static void init_driver_version(char *driver_version, int len) |
580ada3c SC |
7050 | { |
7051 | memset(driver_version, 0, len); | |
f79cfec6 | 7052 | strncpy(driver_version, HPSA " " HPSA_DRIVER_VERSION, len - 1); |
580ada3c SC |
7053 | } |
7054 | ||
6f039790 | 7055 | static int write_driver_ver_to_cfgtable(struct CfgTable __iomem *cfgtable) |
580ada3c SC |
7056 | { |
7057 | char *driver_version; | |
7058 | int i, size = sizeof(cfgtable->driver_version); | |
7059 | ||
7060 | driver_version = kmalloc(size, GFP_KERNEL); | |
7061 | if (!driver_version) | |
7062 | return -ENOMEM; | |
7063 | ||
7064 | init_driver_version(driver_version, size); | |
7065 | for (i = 0; i < size; i++) | |
7066 | writeb(driver_version[i], &cfgtable->driver_version[i]); | |
7067 | kfree(driver_version); | |
7068 | return 0; | |
7069 | } | |
7070 | ||
6f039790 GKH |
7071 | static void read_driver_ver_from_cfgtable(struct CfgTable __iomem *cfgtable, |
7072 | unsigned char *driver_ver) | |
580ada3c SC |
7073 | { |
7074 | int i; | |
7075 | ||
7076 | for (i = 0; i < sizeof(cfgtable->driver_version); i++) | |
7077 | driver_ver[i] = readb(&cfgtable->driver_version[i]); | |
7078 | } | |
7079 | ||
6f039790 | 7080 | static int controller_reset_failed(struct CfgTable __iomem *cfgtable) |
580ada3c SC |
7081 | { |
7082 | ||
7083 | char *driver_ver, *old_driver_ver; | |
7084 | int rc, size = sizeof(cfgtable->driver_version); | |
7085 | ||
7086 | old_driver_ver = kmalloc(2 * size, GFP_KERNEL); | |
7087 | if (!old_driver_ver) | |
7088 | return -ENOMEM; | |
7089 | driver_ver = old_driver_ver + size; | |
7090 | ||
7091 | /* After a reset, the 32 bytes of "driver version" in the cfgtable | |
7092 | * should have been changed, otherwise we know the reset failed. | |
7093 | */ | |
7094 | init_driver_version(old_driver_ver, size); | |
7095 | read_driver_ver_from_cfgtable(cfgtable, driver_ver); | |
7096 | rc = !memcmp(driver_ver, old_driver_ver, size); | |
7097 | kfree(old_driver_ver); | |
7098 | return rc; | |
7099 | } | |
edd16368 | 7100 | /* This does a hard reset of the controller using PCI power management |
1df8552a | 7101 | * states or the using the doorbell register. |
edd16368 | 7102 | */ |
6b6c1cd7 | 7103 | static int hpsa_kdump_hard_reset_controller(struct pci_dev *pdev, u32 board_id) |
edd16368 | 7104 | { |
1df8552a SC |
7105 | u64 cfg_offset; |
7106 | u32 cfg_base_addr; | |
7107 | u64 cfg_base_addr_index; | |
7108 | void __iomem *vaddr; | |
7109 | unsigned long paddr; | |
580ada3c | 7110 | u32 misc_fw_support; |
270d05de | 7111 | int rc; |
1df8552a | 7112 | struct CfgTable __iomem *cfgtable; |
cf0b08d0 | 7113 | u32 use_doorbell; |
270d05de | 7114 | u16 command_register; |
edd16368 | 7115 | |
1df8552a SC |
7116 | /* For controllers as old as the P600, this is very nearly |
7117 | * the same thing as | |
edd16368 SC |
7118 | * |
7119 | * pci_save_state(pci_dev); | |
7120 | * pci_set_power_state(pci_dev, PCI_D3hot); | |
7121 | * pci_set_power_state(pci_dev, PCI_D0); | |
7122 | * pci_restore_state(pci_dev); | |
7123 | * | |
1df8552a SC |
7124 | * For controllers newer than the P600, the pci power state |
7125 | * method of resetting doesn't work so we have another way | |
7126 | * using the doorbell register. | |
edd16368 | 7127 | */ |
18867659 | 7128 | |
60f923b9 RE |
7129 | if (!ctlr_is_resettable(board_id)) { |
7130 | dev_warn(&pdev->dev, "Controller not resettable\n"); | |
25c1e56a SC |
7131 | return -ENODEV; |
7132 | } | |
46380786 SC |
7133 | |
7134 | /* if controller is soft- but not hard resettable... */ | |
7135 | if (!ctlr_is_hard_resettable(board_id)) | |
7136 | return -ENOTSUPP; /* try soft reset later. */ | |
18867659 | 7137 | |
270d05de SC |
7138 | /* Save the PCI command register */ |
7139 | pci_read_config_word(pdev, 4, &command_register); | |
270d05de | 7140 | pci_save_state(pdev); |
edd16368 | 7141 | |
1df8552a SC |
7142 | /* find the first memory BAR, so we can find the cfg table */ |
7143 | rc = hpsa_pci_find_memory_BAR(pdev, &paddr); | |
7144 | if (rc) | |
7145 | return rc; | |
7146 | vaddr = remap_pci_mem(paddr, 0x250); | |
7147 | if (!vaddr) | |
7148 | return -ENOMEM; | |
edd16368 | 7149 | |
1df8552a SC |
7150 | /* find cfgtable in order to check if reset via doorbell is supported */ |
7151 | rc = hpsa_find_cfg_addrs(pdev, vaddr, &cfg_base_addr, | |
7152 | &cfg_base_addr_index, &cfg_offset); | |
7153 | if (rc) | |
7154 | goto unmap_vaddr; | |
7155 | cfgtable = remap_pci_mem(pci_resource_start(pdev, | |
7156 | cfg_base_addr_index) + cfg_offset, sizeof(*cfgtable)); | |
7157 | if (!cfgtable) { | |
7158 | rc = -ENOMEM; | |
7159 | goto unmap_vaddr; | |
7160 | } | |
580ada3c SC |
7161 | rc = write_driver_ver_to_cfgtable(cfgtable); |
7162 | if (rc) | |
03741d95 | 7163 | goto unmap_cfgtable; |
edd16368 | 7164 | |
cf0b08d0 SC |
7165 | /* If reset via doorbell register is supported, use that. |
7166 | * There are two such methods. Favor the newest method. | |
7167 | */ | |
1df8552a | 7168 | misc_fw_support = readl(&cfgtable->misc_fw_support); |
cf0b08d0 SC |
7169 | use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET2; |
7170 | if (use_doorbell) { | |
7171 | use_doorbell = DOORBELL_CTLR_RESET2; | |
7172 | } else { | |
7173 | use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET; | |
7174 | if (use_doorbell) { | |
050f7147 SC |
7175 | dev_warn(&pdev->dev, |
7176 | "Soft reset not supported. Firmware update is required.\n"); | |
64670ac8 | 7177 | rc = -ENOTSUPP; /* try soft reset */ |
cf0b08d0 SC |
7178 | goto unmap_cfgtable; |
7179 | } | |
7180 | } | |
edd16368 | 7181 | |
1df8552a SC |
7182 | rc = hpsa_controller_hard_reset(pdev, vaddr, use_doorbell); |
7183 | if (rc) | |
7184 | goto unmap_cfgtable; | |
edd16368 | 7185 | |
270d05de | 7186 | pci_restore_state(pdev); |
270d05de | 7187 | pci_write_config_word(pdev, 4, command_register); |
edd16368 | 7188 | |
1df8552a SC |
7189 | /* Some devices (notably the HP Smart Array 5i Controller) |
7190 | need a little pause here */ | |
7191 | msleep(HPSA_POST_RESET_PAUSE_MSECS); | |
7192 | ||
fe5389c8 SC |
7193 | rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_READY); |
7194 | if (rc) { | |
7195 | dev_warn(&pdev->dev, | |
050f7147 | 7196 | "Failed waiting for board to become ready after hard reset\n"); |
fe5389c8 SC |
7197 | goto unmap_cfgtable; |
7198 | } | |
fe5389c8 | 7199 | |
580ada3c SC |
7200 | rc = controller_reset_failed(vaddr); |
7201 | if (rc < 0) | |
7202 | goto unmap_cfgtable; | |
7203 | if (rc) { | |
64670ac8 SC |
7204 | dev_warn(&pdev->dev, "Unable to successfully reset " |
7205 | "controller. Will try soft reset.\n"); | |
7206 | rc = -ENOTSUPP; | |
580ada3c | 7207 | } else { |
64670ac8 | 7208 | dev_info(&pdev->dev, "board ready after hard reset.\n"); |
1df8552a SC |
7209 | } |
7210 | ||
7211 | unmap_cfgtable: | |
7212 | iounmap(cfgtable); | |
7213 | ||
7214 | unmap_vaddr: | |
7215 | iounmap(vaddr); | |
7216 | return rc; | |
edd16368 SC |
7217 | } |
7218 | ||
7219 | /* | |
7220 | * We cannot read the structure directly, for portability we must use | |
7221 | * the io functions. | |
7222 | * This is for debug only. | |
7223 | */ | |
42a91641 | 7224 | static void print_cfg_table(struct device *dev, struct CfgTable __iomem *tb) |
edd16368 | 7225 | { |
58f8665c | 7226 | #ifdef HPSA_DEBUG |
edd16368 SC |
7227 | int i; |
7228 | char temp_name[17]; | |
7229 | ||
7230 | dev_info(dev, "Controller Configuration information\n"); | |
7231 | dev_info(dev, "------------------------------------\n"); | |
7232 | for (i = 0; i < 4; i++) | |
7233 | temp_name[i] = readb(&(tb->Signature[i])); | |
7234 | temp_name[4] = '\0'; | |
7235 | dev_info(dev, " Signature = %s\n", temp_name); | |
7236 | dev_info(dev, " Spec Number = %d\n", readl(&(tb->SpecValence))); | |
7237 | dev_info(dev, " Transport methods supported = 0x%x\n", | |
7238 | readl(&(tb->TransportSupport))); | |
7239 | dev_info(dev, " Transport methods active = 0x%x\n", | |
7240 | readl(&(tb->TransportActive))); | |
7241 | dev_info(dev, " Requested transport Method = 0x%x\n", | |
7242 | readl(&(tb->HostWrite.TransportRequest))); | |
7243 | dev_info(dev, " Coalesce Interrupt Delay = 0x%x\n", | |
7244 | readl(&(tb->HostWrite.CoalIntDelay))); | |
7245 | dev_info(dev, " Coalesce Interrupt Count = 0x%x\n", | |
7246 | readl(&(tb->HostWrite.CoalIntCount))); | |
69d6e33d | 7247 | dev_info(dev, " Max outstanding commands = %d\n", |
edd16368 SC |
7248 | readl(&(tb->CmdsOutMax))); |
7249 | dev_info(dev, " Bus Types = 0x%x\n", readl(&(tb->BusTypes))); | |
7250 | for (i = 0; i < 16; i++) | |
7251 | temp_name[i] = readb(&(tb->ServerName[i])); | |
7252 | temp_name[16] = '\0'; | |
7253 | dev_info(dev, " Server Name = %s\n", temp_name); | |
7254 | dev_info(dev, " Heartbeat Counter = 0x%x\n\n\n", | |
7255 | readl(&(tb->HeartBeat))); | |
edd16368 | 7256 | #endif /* HPSA_DEBUG */ |
58f8665c | 7257 | } |
edd16368 SC |
7258 | |
7259 | static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr) | |
7260 | { | |
7261 | int i, offset, mem_type, bar_type; | |
7262 | ||
7263 | if (pci_bar_addr == PCI_BASE_ADDRESS_0) /* looking for BAR zero? */ | |
7264 | return 0; | |
7265 | offset = 0; | |
7266 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
7267 | bar_type = pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE; | |
7268 | if (bar_type == PCI_BASE_ADDRESS_SPACE_IO) | |
7269 | offset += 4; | |
7270 | else { | |
7271 | mem_type = pci_resource_flags(pdev, i) & | |
7272 | PCI_BASE_ADDRESS_MEM_TYPE_MASK; | |
7273 | switch (mem_type) { | |
7274 | case PCI_BASE_ADDRESS_MEM_TYPE_32: | |
7275 | case PCI_BASE_ADDRESS_MEM_TYPE_1M: | |
7276 | offset += 4; /* 32 bit */ | |
7277 | break; | |
7278 | case PCI_BASE_ADDRESS_MEM_TYPE_64: | |
7279 | offset += 8; | |
7280 | break; | |
7281 | default: /* reserved in PCI 2.2 */ | |
7282 | dev_warn(&pdev->dev, | |
7283 | "base address is invalid\n"); | |
7284 | return -1; | |
7285 | break; | |
7286 | } | |
7287 | } | |
7288 | if (offset == pci_bar_addr - PCI_BASE_ADDRESS_0) | |
7289 | return i + 1; | |
7290 | } | |
7291 | return -1; | |
7292 | } | |
7293 | ||
cc64c817 RE |
7294 | static void hpsa_disable_interrupt_mode(struct ctlr_info *h) |
7295 | { | |
7296 | if (h->msix_vector) { | |
7297 | if (h->pdev->msix_enabled) | |
7298 | pci_disable_msix(h->pdev); | |
105a3dbc | 7299 | h->msix_vector = 0; |
cc64c817 RE |
7300 | } else if (h->msi_vector) { |
7301 | if (h->pdev->msi_enabled) | |
7302 | pci_disable_msi(h->pdev); | |
105a3dbc | 7303 | h->msi_vector = 0; |
cc64c817 RE |
7304 | } |
7305 | } | |
7306 | ||
edd16368 | 7307 | /* If MSI/MSI-X is supported by the kernel we will try to enable it on |
050f7147 | 7308 | * controllers that are capable. If not, we use legacy INTx mode. |
edd16368 | 7309 | */ |
6f039790 | 7310 | static void hpsa_interrupt_mode(struct ctlr_info *h) |
edd16368 SC |
7311 | { |
7312 | #ifdef CONFIG_PCI_MSI | |
254f796b MG |
7313 | int err, i; |
7314 | struct msix_entry hpsa_msix_entries[MAX_REPLY_QUEUES]; | |
7315 | ||
7316 | for (i = 0; i < MAX_REPLY_QUEUES; i++) { | |
7317 | hpsa_msix_entries[i].vector = 0; | |
7318 | hpsa_msix_entries[i].entry = i; | |
7319 | } | |
edd16368 SC |
7320 | |
7321 | /* Some boards advertise MSI but don't really support it */ | |
6b3f4c52 SC |
7322 | if ((h->board_id == 0x40700E11) || (h->board_id == 0x40800E11) || |
7323 | (h->board_id == 0x40820E11) || (h->board_id == 0x40830E11)) | |
edd16368 | 7324 | goto default_int_mode; |
55c06c71 | 7325 | if (pci_find_capability(h->pdev, PCI_CAP_ID_MSIX)) { |
050f7147 | 7326 | dev_info(&h->pdev->dev, "MSI-X capable controller\n"); |
eee0f03a | 7327 | h->msix_vector = MAX_REPLY_QUEUES; |
f89439bc SC |
7328 | if (h->msix_vector > num_online_cpus()) |
7329 | h->msix_vector = num_online_cpus(); | |
18fce3c4 AG |
7330 | err = pci_enable_msix_range(h->pdev, hpsa_msix_entries, |
7331 | 1, h->msix_vector); | |
7332 | if (err < 0) { | |
7333 | dev_warn(&h->pdev->dev, "MSI-X init failed %d\n", err); | |
7334 | h->msix_vector = 0; | |
7335 | goto single_msi_mode; | |
7336 | } else if (err < h->msix_vector) { | |
55c06c71 | 7337 | dev_warn(&h->pdev->dev, "only %d MSI-X vectors " |
edd16368 | 7338 | "available\n", err); |
edd16368 | 7339 | } |
18fce3c4 AG |
7340 | h->msix_vector = err; |
7341 | for (i = 0; i < h->msix_vector; i++) | |
7342 | h->intr[i] = hpsa_msix_entries[i].vector; | |
7343 | return; | |
edd16368 | 7344 | } |
18fce3c4 | 7345 | single_msi_mode: |
55c06c71 | 7346 | if (pci_find_capability(h->pdev, PCI_CAP_ID_MSI)) { |
050f7147 | 7347 | dev_info(&h->pdev->dev, "MSI capable controller\n"); |
55c06c71 | 7348 | if (!pci_enable_msi(h->pdev)) |
edd16368 SC |
7349 | h->msi_vector = 1; |
7350 | else | |
55c06c71 | 7351 | dev_warn(&h->pdev->dev, "MSI init failed\n"); |
edd16368 SC |
7352 | } |
7353 | default_int_mode: | |
7354 | #endif /* CONFIG_PCI_MSI */ | |
7355 | /* if we get here we're going to use the default interrupt mode */ | |
a9a3a273 | 7356 | h->intr[h->intr_mode] = h->pdev->irq; |
edd16368 SC |
7357 | } |
7358 | ||
6f039790 | 7359 | static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id) |
e5c880d1 SC |
7360 | { |
7361 | int i; | |
7362 | u32 subsystem_vendor_id, subsystem_device_id; | |
7363 | ||
7364 | subsystem_vendor_id = pdev->subsystem_vendor; | |
7365 | subsystem_device_id = pdev->subsystem_device; | |
7366 | *board_id = ((subsystem_device_id << 16) & 0xffff0000) | | |
7367 | subsystem_vendor_id; | |
7368 | ||
7369 | for (i = 0; i < ARRAY_SIZE(products); i++) | |
7370 | if (*board_id == products[i].board_id) | |
7371 | return i; | |
7372 | ||
6798cc0a SC |
7373 | if ((subsystem_vendor_id != PCI_VENDOR_ID_HP && |
7374 | subsystem_vendor_id != PCI_VENDOR_ID_COMPAQ) || | |
7375 | !hpsa_allow_any) { | |
e5c880d1 SC |
7376 | dev_warn(&pdev->dev, "unrecognized board ID: " |
7377 | "0x%08x, ignoring.\n", *board_id); | |
7378 | return -ENODEV; | |
7379 | } | |
7380 | return ARRAY_SIZE(products) - 1; /* generic unknown smart array */ | |
7381 | } | |
7382 | ||
6f039790 GKH |
7383 | static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev, |
7384 | unsigned long *memory_bar) | |
3a7774ce SC |
7385 | { |
7386 | int i; | |
7387 | ||
7388 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) | |
12d2cd47 | 7389 | if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) { |
3a7774ce | 7390 | /* addressing mode bits already removed */ |
12d2cd47 SC |
7391 | *memory_bar = pci_resource_start(pdev, i); |
7392 | dev_dbg(&pdev->dev, "memory BAR = %lx\n", | |
3a7774ce SC |
7393 | *memory_bar); |
7394 | return 0; | |
7395 | } | |
12d2cd47 | 7396 | dev_warn(&pdev->dev, "no memory BAR found\n"); |
3a7774ce SC |
7397 | return -ENODEV; |
7398 | } | |
7399 | ||
6f039790 GKH |
7400 | static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr, |
7401 | int wait_for_ready) | |
2c4c8c8b | 7402 | { |
fe5389c8 | 7403 | int i, iterations; |
2c4c8c8b | 7404 | u32 scratchpad; |
fe5389c8 SC |
7405 | if (wait_for_ready) |
7406 | iterations = HPSA_BOARD_READY_ITERATIONS; | |
7407 | else | |
7408 | iterations = HPSA_BOARD_NOT_READY_ITERATIONS; | |
2c4c8c8b | 7409 | |
fe5389c8 SC |
7410 | for (i = 0; i < iterations; i++) { |
7411 | scratchpad = readl(vaddr + SA5_SCRATCHPAD_OFFSET); | |
7412 | if (wait_for_ready) { | |
7413 | if (scratchpad == HPSA_FIRMWARE_READY) | |
7414 | return 0; | |
7415 | } else { | |
7416 | if (scratchpad != HPSA_FIRMWARE_READY) | |
7417 | return 0; | |
7418 | } | |
2c4c8c8b SC |
7419 | msleep(HPSA_BOARD_READY_POLL_INTERVAL_MSECS); |
7420 | } | |
fe5389c8 | 7421 | dev_warn(&pdev->dev, "board not ready, timed out.\n"); |
2c4c8c8b SC |
7422 | return -ENODEV; |
7423 | } | |
7424 | ||
6f039790 GKH |
7425 | static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr, |
7426 | u32 *cfg_base_addr, u64 *cfg_base_addr_index, | |
7427 | u64 *cfg_offset) | |
a51fd47f SC |
7428 | { |
7429 | *cfg_base_addr = readl(vaddr + SA5_CTCFG_OFFSET); | |
7430 | *cfg_offset = readl(vaddr + SA5_CTMEM_OFFSET); | |
7431 | *cfg_base_addr &= (u32) 0x0000ffff; | |
7432 | *cfg_base_addr_index = find_PCI_BAR_index(pdev, *cfg_base_addr); | |
7433 | if (*cfg_base_addr_index == -1) { | |
7434 | dev_warn(&pdev->dev, "cannot find cfg_base_addr_index\n"); | |
7435 | return -ENODEV; | |
7436 | } | |
7437 | return 0; | |
7438 | } | |
7439 | ||
195f2c65 RE |
7440 | static void hpsa_free_cfgtables(struct ctlr_info *h) |
7441 | { | |
105a3dbc | 7442 | if (h->transtable) { |
195f2c65 | 7443 | iounmap(h->transtable); |
105a3dbc RE |
7444 | h->transtable = NULL; |
7445 | } | |
7446 | if (h->cfgtable) { | |
195f2c65 | 7447 | iounmap(h->cfgtable); |
105a3dbc RE |
7448 | h->cfgtable = NULL; |
7449 | } | |
195f2c65 RE |
7450 | } |
7451 | ||
7452 | /* Find and map CISS config table and transfer table | |
7453 | + * several items must be unmapped (freed) later | |
7454 | + * */ | |
6f039790 | 7455 | static int hpsa_find_cfgtables(struct ctlr_info *h) |
edd16368 | 7456 | { |
01a02ffc SC |
7457 | u64 cfg_offset; |
7458 | u32 cfg_base_addr; | |
7459 | u64 cfg_base_addr_index; | |
303932fd | 7460 | u32 trans_offset; |
a51fd47f | 7461 | int rc; |
77c4495c | 7462 | |
a51fd47f SC |
7463 | rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr, |
7464 | &cfg_base_addr_index, &cfg_offset); | |
7465 | if (rc) | |
7466 | return rc; | |
77c4495c | 7467 | h->cfgtable = remap_pci_mem(pci_resource_start(h->pdev, |
a51fd47f | 7468 | cfg_base_addr_index) + cfg_offset, sizeof(*h->cfgtable)); |
cd3c81c4 RE |
7469 | if (!h->cfgtable) { |
7470 | dev_err(&h->pdev->dev, "Failed mapping cfgtable\n"); | |
77c4495c | 7471 | return -ENOMEM; |
cd3c81c4 | 7472 | } |
580ada3c SC |
7473 | rc = write_driver_ver_to_cfgtable(h->cfgtable); |
7474 | if (rc) | |
7475 | return rc; | |
77c4495c | 7476 | /* Find performant mode table. */ |
a51fd47f | 7477 | trans_offset = readl(&h->cfgtable->TransMethodOffset); |
77c4495c SC |
7478 | h->transtable = remap_pci_mem(pci_resource_start(h->pdev, |
7479 | cfg_base_addr_index)+cfg_offset+trans_offset, | |
7480 | sizeof(*h->transtable)); | |
195f2c65 RE |
7481 | if (!h->transtable) { |
7482 | dev_err(&h->pdev->dev, "Failed mapping transfer table\n"); | |
7483 | hpsa_free_cfgtables(h); | |
77c4495c | 7484 | return -ENOMEM; |
195f2c65 | 7485 | } |
77c4495c SC |
7486 | return 0; |
7487 | } | |
7488 | ||
6f039790 | 7489 | static void hpsa_get_max_perf_mode_cmds(struct ctlr_info *h) |
cba3d38b | 7490 | { |
41ce4c35 SC |
7491 | #define MIN_MAX_COMMANDS 16 |
7492 | BUILD_BUG_ON(MIN_MAX_COMMANDS <= HPSA_NRESERVED_CMDS); | |
7493 | ||
7494 | h->max_commands = readl(&h->cfgtable->MaxPerformantModeCommands); | |
72ceeaec SC |
7495 | |
7496 | /* Limit commands in memory limited kdump scenario. */ | |
7497 | if (reset_devices && h->max_commands > 32) | |
7498 | h->max_commands = 32; | |
7499 | ||
41ce4c35 SC |
7500 | if (h->max_commands < MIN_MAX_COMMANDS) { |
7501 | dev_warn(&h->pdev->dev, | |
7502 | "Controller reports max supported commands of %d Using %d instead. Ensure that firmware is up to date.\n", | |
7503 | h->max_commands, | |
7504 | MIN_MAX_COMMANDS); | |
7505 | h->max_commands = MIN_MAX_COMMANDS; | |
cba3d38b SC |
7506 | } |
7507 | } | |
7508 | ||
c7ee65b3 WS |
7509 | /* If the controller reports that the total max sg entries is greater than 512, |
7510 | * then we know that chained SG blocks work. (Original smart arrays did not | |
7511 | * support chained SG blocks and would return zero for max sg entries.) | |
7512 | */ | |
7513 | static int hpsa_supports_chained_sg_blocks(struct ctlr_info *h) | |
7514 | { | |
7515 | return h->maxsgentries > 512; | |
7516 | } | |
7517 | ||
b93d7536 SC |
7518 | /* Interrogate the hardware for some limits: |
7519 | * max commands, max SG elements without chaining, and with chaining, | |
7520 | * SG chain block size, etc. | |
7521 | */ | |
6f039790 | 7522 | static void hpsa_find_board_params(struct ctlr_info *h) |
b93d7536 | 7523 | { |
cba3d38b | 7524 | hpsa_get_max_perf_mode_cmds(h); |
45fcb86e | 7525 | h->nr_cmds = h->max_commands; |
b93d7536 | 7526 | h->maxsgentries = readl(&(h->cfgtable->MaxScatterGatherElements)); |
283b4a9b | 7527 | h->fw_support = readl(&(h->cfgtable->misc_fw_support)); |
c7ee65b3 WS |
7528 | if (hpsa_supports_chained_sg_blocks(h)) { |
7529 | /* Limit in-command s/g elements to 32 save dma'able memory. */ | |
b93d7536 | 7530 | h->max_cmd_sg_entries = 32; |
1a63ea6f | 7531 | h->chainsize = h->maxsgentries - h->max_cmd_sg_entries; |
b93d7536 SC |
7532 | h->maxsgentries--; /* save one for chain pointer */ |
7533 | } else { | |
c7ee65b3 WS |
7534 | /* |
7535 | * Original smart arrays supported at most 31 s/g entries | |
7536 | * embedded inline in the command (trying to use more | |
7537 | * would lock up the controller) | |
7538 | */ | |
7539 | h->max_cmd_sg_entries = 31; | |
1a63ea6f | 7540 | h->maxsgentries = 31; /* default to traditional values */ |
c7ee65b3 | 7541 | h->chainsize = 0; |
b93d7536 | 7542 | } |
75167d2c SC |
7543 | |
7544 | /* Find out what task management functions are supported and cache */ | |
7545 | h->TMFSupportFlags = readl(&(h->cfgtable->TMFSupportFlags)); | |
0e7a7fce ST |
7546 | if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags)) |
7547 | dev_warn(&h->pdev->dev, "Physical aborts not supported\n"); | |
7548 | if (!(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags)) | |
7549 | dev_warn(&h->pdev->dev, "Logical aborts not supported\n"); | |
8be986cc SC |
7550 | if (!(HPSATMF_IOACCEL_ENABLED & h->TMFSupportFlags)) |
7551 | dev_warn(&h->pdev->dev, "HP SSD Smart Path aborts not supported\n"); | |
b93d7536 SC |
7552 | } |
7553 | ||
76c46e49 SC |
7554 | static inline bool hpsa_CISS_signature_present(struct ctlr_info *h) |
7555 | { | |
0fc9fd40 | 7556 | if (!check_signature(h->cfgtable->Signature, "CISS", 4)) { |
050f7147 | 7557 | dev_err(&h->pdev->dev, "not a valid CISS config table\n"); |
76c46e49 SC |
7558 | return false; |
7559 | } | |
7560 | return true; | |
7561 | } | |
7562 | ||
97a5e98c | 7563 | static inline void hpsa_set_driver_support_bits(struct ctlr_info *h) |
f7c39101 | 7564 | { |
97a5e98c | 7565 | u32 driver_support; |
f7c39101 | 7566 | |
97a5e98c | 7567 | driver_support = readl(&(h->cfgtable->driver_support)); |
0b9e7b74 AB |
7568 | /* Need to enable prefetch in the SCSI core for 6400 in x86 */ |
7569 | #ifdef CONFIG_X86 | |
97a5e98c | 7570 | driver_support |= ENABLE_SCSI_PREFETCH; |
f7c39101 | 7571 | #endif |
28e13446 SC |
7572 | driver_support |= ENABLE_UNIT_ATTN; |
7573 | writel(driver_support, &(h->cfgtable->driver_support)); | |
f7c39101 SC |
7574 | } |
7575 | ||
3d0eab67 SC |
7576 | /* Disable DMA prefetch for the P600. Otherwise an ASIC bug may result |
7577 | * in a prefetch beyond physical memory. | |
7578 | */ | |
7579 | static inline void hpsa_p600_dma_prefetch_quirk(struct ctlr_info *h) | |
7580 | { | |
7581 | u32 dma_prefetch; | |
7582 | ||
7583 | if (h->board_id != 0x3225103C) | |
7584 | return; | |
7585 | dma_prefetch = readl(h->vaddr + I2O_DMA1_CFG); | |
7586 | dma_prefetch |= 0x8000; | |
7587 | writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG); | |
7588 | } | |
7589 | ||
c706a795 | 7590 | static int hpsa_wait_for_clear_event_notify_ack(struct ctlr_info *h) |
76438d08 SC |
7591 | { |
7592 | int i; | |
7593 | u32 doorbell_value; | |
7594 | unsigned long flags; | |
7595 | /* wait until the clear_event_notify bit 6 is cleared by controller. */ | |
007e7aa9 | 7596 | for (i = 0; i < MAX_CLEAR_EVENT_WAIT; i++) { |
76438d08 SC |
7597 | spin_lock_irqsave(&h->lock, flags); |
7598 | doorbell_value = readl(h->vaddr + SA5_DOORBELL); | |
7599 | spin_unlock_irqrestore(&h->lock, flags); | |
7600 | if (!(doorbell_value & DOORBELL_CLEAR_EVENTS)) | |
c706a795 | 7601 | goto done; |
76438d08 | 7602 | /* delay and try again */ |
007e7aa9 | 7603 | msleep(CLEAR_EVENT_WAIT_INTERVAL); |
76438d08 | 7604 | } |
c706a795 RE |
7605 | return -ENODEV; |
7606 | done: | |
7607 | return 0; | |
76438d08 SC |
7608 | } |
7609 | ||
c706a795 | 7610 | static int hpsa_wait_for_mode_change_ack(struct ctlr_info *h) |
eb6b2ae9 SC |
7611 | { |
7612 | int i; | |
6eaf46fd SC |
7613 | u32 doorbell_value; |
7614 | unsigned long flags; | |
eb6b2ae9 SC |
7615 | |
7616 | /* under certain very rare conditions, this can take awhile. | |
7617 | * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right | |
7618 | * as we enter this code.) | |
7619 | */ | |
007e7aa9 | 7620 | for (i = 0; i < MAX_MODE_CHANGE_WAIT; i++) { |
25163bd5 WS |
7621 | if (h->remove_in_progress) |
7622 | goto done; | |
6eaf46fd SC |
7623 | spin_lock_irqsave(&h->lock, flags); |
7624 | doorbell_value = readl(h->vaddr + SA5_DOORBELL); | |
7625 | spin_unlock_irqrestore(&h->lock, flags); | |
382be668 | 7626 | if (!(doorbell_value & CFGTBL_ChangeReq)) |
c706a795 | 7627 | goto done; |
eb6b2ae9 | 7628 | /* delay and try again */ |
007e7aa9 | 7629 | msleep(MODE_CHANGE_WAIT_INTERVAL); |
eb6b2ae9 | 7630 | } |
c706a795 RE |
7631 | return -ENODEV; |
7632 | done: | |
7633 | return 0; | |
3f4336f3 SC |
7634 | } |
7635 | ||
c706a795 | 7636 | /* return -ENODEV or other reason on error, 0 on success */ |
6f039790 | 7637 | static int hpsa_enter_simple_mode(struct ctlr_info *h) |
3f4336f3 SC |
7638 | { |
7639 | u32 trans_support; | |
7640 | ||
7641 | trans_support = readl(&(h->cfgtable->TransportSupport)); | |
7642 | if (!(trans_support & SIMPLE_MODE)) | |
7643 | return -ENOTSUPP; | |
7644 | ||
7645 | h->max_commands = readl(&(h->cfgtable->CmdsOutMax)); | |
283b4a9b | 7646 | |
3f4336f3 SC |
7647 | /* Update the field, and then ring the doorbell */ |
7648 | writel(CFGTBL_Trans_Simple, &(h->cfgtable->HostWrite.TransportRequest)); | |
b9af4937 | 7649 | writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi); |
3f4336f3 | 7650 | writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL); |
c706a795 RE |
7651 | if (hpsa_wait_for_mode_change_ack(h)) |
7652 | goto error; | |
eb6b2ae9 | 7653 | print_cfg_table(&h->pdev->dev, h->cfgtable); |
283b4a9b SC |
7654 | if (!(readl(&(h->cfgtable->TransportActive)) & CFGTBL_Trans_Simple)) |
7655 | goto error; | |
960a30e7 | 7656 | h->transMethod = CFGTBL_Trans_Simple; |
eb6b2ae9 | 7657 | return 0; |
283b4a9b | 7658 | error: |
050f7147 | 7659 | dev_err(&h->pdev->dev, "failed to enter simple mode\n"); |
283b4a9b | 7660 | return -ENODEV; |
eb6b2ae9 SC |
7661 | } |
7662 | ||
195f2c65 RE |
7663 | /* free items allocated or mapped by hpsa_pci_init */ |
7664 | static void hpsa_free_pci_init(struct ctlr_info *h) | |
7665 | { | |
7666 | hpsa_free_cfgtables(h); /* pci_init 4 */ | |
7667 | iounmap(h->vaddr); /* pci_init 3 */ | |
105a3dbc | 7668 | h->vaddr = NULL; |
195f2c65 | 7669 | hpsa_disable_interrupt_mode(h); /* pci_init 2 */ |
943a7021 RE |
7670 | /* |
7671 | * call pci_disable_device before pci_release_regions per | |
7672 | * Documentation/PCI/pci.txt | |
7673 | */ | |
195f2c65 | 7674 | pci_disable_device(h->pdev); /* pci_init 1 */ |
943a7021 | 7675 | pci_release_regions(h->pdev); /* pci_init 2 */ |
195f2c65 RE |
7676 | } |
7677 | ||
7678 | /* several items must be freed later */ | |
6f039790 | 7679 | static int hpsa_pci_init(struct ctlr_info *h) |
77c4495c | 7680 | { |
eb6b2ae9 | 7681 | int prod_index, err; |
edd16368 | 7682 | |
e5c880d1 SC |
7683 | prod_index = hpsa_lookup_board_id(h->pdev, &h->board_id); |
7684 | if (prod_index < 0) | |
60f923b9 | 7685 | return prod_index; |
e5c880d1 SC |
7686 | h->product_name = products[prod_index].product_name; |
7687 | h->access = *(products[prod_index].access); | |
edd16368 | 7688 | |
9b5c48c2 SC |
7689 | h->needs_abort_tags_swizzled = |
7690 | ctlr_needs_abort_tags_swizzled(h->board_id); | |
7691 | ||
e5a44df8 MG |
7692 | pci_disable_link_state(h->pdev, PCIE_LINK_STATE_L0S | |
7693 | PCIE_LINK_STATE_L1 | PCIE_LINK_STATE_CLKPM); | |
7694 | ||
55c06c71 | 7695 | err = pci_enable_device(h->pdev); |
edd16368 | 7696 | if (err) { |
195f2c65 | 7697 | dev_err(&h->pdev->dev, "failed to enable PCI device\n"); |
943a7021 | 7698 | pci_disable_device(h->pdev); |
edd16368 SC |
7699 | return err; |
7700 | } | |
7701 | ||
f79cfec6 | 7702 | err = pci_request_regions(h->pdev, HPSA); |
edd16368 | 7703 | if (err) { |
55c06c71 | 7704 | dev_err(&h->pdev->dev, |
195f2c65 | 7705 | "failed to obtain PCI resources\n"); |
943a7021 RE |
7706 | pci_disable_device(h->pdev); |
7707 | return err; | |
edd16368 | 7708 | } |
4fa604e1 RE |
7709 | |
7710 | pci_set_master(h->pdev); | |
7711 | ||
6b3f4c52 | 7712 | hpsa_interrupt_mode(h); |
12d2cd47 | 7713 | err = hpsa_pci_find_memory_BAR(h->pdev, &h->paddr); |
3a7774ce | 7714 | if (err) |
195f2c65 | 7715 | goto clean2; /* intmode+region, pci */ |
edd16368 | 7716 | h->vaddr = remap_pci_mem(h->paddr, 0x250); |
204892e9 | 7717 | if (!h->vaddr) { |
195f2c65 | 7718 | dev_err(&h->pdev->dev, "failed to remap PCI mem\n"); |
204892e9 | 7719 | err = -ENOMEM; |
195f2c65 | 7720 | goto clean2; /* intmode+region, pci */ |
204892e9 | 7721 | } |
fe5389c8 | 7722 | err = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY); |
2c4c8c8b | 7723 | if (err) |
195f2c65 | 7724 | goto clean3; /* vaddr, intmode+region, pci */ |
77c4495c SC |
7725 | err = hpsa_find_cfgtables(h); |
7726 | if (err) | |
195f2c65 | 7727 | goto clean3; /* vaddr, intmode+region, pci */ |
b93d7536 | 7728 | hpsa_find_board_params(h); |
edd16368 | 7729 | |
76c46e49 | 7730 | if (!hpsa_CISS_signature_present(h)) { |
edd16368 | 7731 | err = -ENODEV; |
195f2c65 | 7732 | goto clean4; /* cfgtables, vaddr, intmode+region, pci */ |
edd16368 | 7733 | } |
97a5e98c | 7734 | hpsa_set_driver_support_bits(h); |
3d0eab67 | 7735 | hpsa_p600_dma_prefetch_quirk(h); |
eb6b2ae9 SC |
7736 | err = hpsa_enter_simple_mode(h); |
7737 | if (err) | |
195f2c65 | 7738 | goto clean4; /* cfgtables, vaddr, intmode+region, pci */ |
edd16368 SC |
7739 | return 0; |
7740 | ||
195f2c65 RE |
7741 | clean4: /* cfgtables, vaddr, intmode+region, pci */ |
7742 | hpsa_free_cfgtables(h); | |
7743 | clean3: /* vaddr, intmode+region, pci */ | |
7744 | iounmap(h->vaddr); | |
105a3dbc | 7745 | h->vaddr = NULL; |
195f2c65 RE |
7746 | clean2: /* intmode+region, pci */ |
7747 | hpsa_disable_interrupt_mode(h); | |
943a7021 RE |
7748 | /* |
7749 | * call pci_disable_device before pci_release_regions per | |
7750 | * Documentation/PCI/pci.txt | |
7751 | */ | |
195f2c65 | 7752 | pci_disable_device(h->pdev); |
943a7021 | 7753 | pci_release_regions(h->pdev); |
edd16368 SC |
7754 | return err; |
7755 | } | |
7756 | ||
6f039790 | 7757 | static void hpsa_hba_inquiry(struct ctlr_info *h) |
339b2b14 SC |
7758 | { |
7759 | int rc; | |
7760 | ||
7761 | #define HBA_INQUIRY_BYTE_COUNT 64 | |
7762 | h->hba_inquiry_data = kmalloc(HBA_INQUIRY_BYTE_COUNT, GFP_KERNEL); | |
7763 | if (!h->hba_inquiry_data) | |
7764 | return; | |
7765 | rc = hpsa_scsi_do_inquiry(h, RAID_CTLR_LUNID, 0, | |
7766 | h->hba_inquiry_data, HBA_INQUIRY_BYTE_COUNT); | |
7767 | if (rc != 0) { | |
7768 | kfree(h->hba_inquiry_data); | |
7769 | h->hba_inquiry_data = NULL; | |
7770 | } | |
7771 | } | |
7772 | ||
6b6c1cd7 | 7773 | static int hpsa_init_reset_devices(struct pci_dev *pdev, u32 board_id) |
4c2a8c40 | 7774 | { |
1df8552a | 7775 | int rc, i; |
3b747298 | 7776 | void __iomem *vaddr; |
4c2a8c40 SC |
7777 | |
7778 | if (!reset_devices) | |
7779 | return 0; | |
7780 | ||
132aa220 TH |
7781 | /* kdump kernel is loading, we don't know in which state is |
7782 | * the pci interface. The dev->enable_cnt is equal zero | |
7783 | * so we call enable+disable, wait a while and switch it on. | |
7784 | */ | |
7785 | rc = pci_enable_device(pdev); | |
7786 | if (rc) { | |
7787 | dev_warn(&pdev->dev, "Failed to enable PCI device\n"); | |
7788 | return -ENODEV; | |
7789 | } | |
7790 | pci_disable_device(pdev); | |
7791 | msleep(260); /* a randomly chosen number */ | |
7792 | rc = pci_enable_device(pdev); | |
7793 | if (rc) { | |
7794 | dev_warn(&pdev->dev, "failed to enable device.\n"); | |
7795 | return -ENODEV; | |
7796 | } | |
4fa604e1 | 7797 | |
859c75ab | 7798 | pci_set_master(pdev); |
4fa604e1 | 7799 | |
3b747298 TH |
7800 | vaddr = pci_ioremap_bar(pdev, 0); |
7801 | if (vaddr == NULL) { | |
7802 | rc = -ENOMEM; | |
7803 | goto out_disable; | |
7804 | } | |
7805 | writel(SA5_INTR_OFF, vaddr + SA5_REPLY_INTR_MASK_OFFSET); | |
7806 | iounmap(vaddr); | |
7807 | ||
1df8552a | 7808 | /* Reset the controller with a PCI power-cycle or via doorbell */ |
6b6c1cd7 | 7809 | rc = hpsa_kdump_hard_reset_controller(pdev, board_id); |
4c2a8c40 | 7810 | |
1df8552a SC |
7811 | /* -ENOTSUPP here means we cannot reset the controller |
7812 | * but it's already (and still) up and running in | |
18867659 SC |
7813 | * "performant mode". Or, it might be 640x, which can't reset |
7814 | * due to concerns about shared bbwc between 6402/6404 pair. | |
1df8552a | 7815 | */ |
adf1b3a3 | 7816 | if (rc) |
132aa220 | 7817 | goto out_disable; |
4c2a8c40 SC |
7818 | |
7819 | /* Now try to get the controller to respond to a no-op */ | |
1ba66c9c | 7820 | dev_info(&pdev->dev, "Waiting for controller to respond to no-op\n"); |
4c2a8c40 SC |
7821 | for (i = 0; i < HPSA_POST_RESET_NOOP_RETRIES; i++) { |
7822 | if (hpsa_noop(pdev) == 0) | |
7823 | break; | |
7824 | else | |
7825 | dev_warn(&pdev->dev, "no-op failed%s\n", | |
7826 | (i < 11 ? "; re-trying" : "")); | |
7827 | } | |
132aa220 TH |
7828 | |
7829 | out_disable: | |
7830 | ||
7831 | pci_disable_device(pdev); | |
7832 | return rc; | |
4c2a8c40 SC |
7833 | } |
7834 | ||
1fb7c98a RE |
7835 | static void hpsa_free_cmd_pool(struct ctlr_info *h) |
7836 | { | |
7837 | kfree(h->cmd_pool_bits); | |
105a3dbc RE |
7838 | h->cmd_pool_bits = NULL; |
7839 | if (h->cmd_pool) { | |
1fb7c98a RE |
7840 | pci_free_consistent(h->pdev, |
7841 | h->nr_cmds * sizeof(struct CommandList), | |
7842 | h->cmd_pool, | |
7843 | h->cmd_pool_dhandle); | |
105a3dbc RE |
7844 | h->cmd_pool = NULL; |
7845 | h->cmd_pool_dhandle = 0; | |
7846 | } | |
7847 | if (h->errinfo_pool) { | |
1fb7c98a RE |
7848 | pci_free_consistent(h->pdev, |
7849 | h->nr_cmds * sizeof(struct ErrorInfo), | |
7850 | h->errinfo_pool, | |
7851 | h->errinfo_pool_dhandle); | |
105a3dbc RE |
7852 | h->errinfo_pool = NULL; |
7853 | h->errinfo_pool_dhandle = 0; | |
7854 | } | |
1fb7c98a RE |
7855 | } |
7856 | ||
d37ffbe4 | 7857 | static int hpsa_alloc_cmd_pool(struct ctlr_info *h) |
2e9d1b36 SC |
7858 | { |
7859 | h->cmd_pool_bits = kzalloc( | |
7860 | DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG) * | |
7861 | sizeof(unsigned long), GFP_KERNEL); | |
7862 | h->cmd_pool = pci_alloc_consistent(h->pdev, | |
7863 | h->nr_cmds * sizeof(*h->cmd_pool), | |
7864 | &(h->cmd_pool_dhandle)); | |
7865 | h->errinfo_pool = pci_alloc_consistent(h->pdev, | |
7866 | h->nr_cmds * sizeof(*h->errinfo_pool), | |
7867 | &(h->errinfo_pool_dhandle)); | |
7868 | if ((h->cmd_pool_bits == NULL) | |
7869 | || (h->cmd_pool == NULL) | |
7870 | || (h->errinfo_pool == NULL)) { | |
7871 | dev_err(&h->pdev->dev, "out of memory in %s", __func__); | |
2c143342 | 7872 | goto clean_up; |
2e9d1b36 | 7873 | } |
360c73bd | 7874 | hpsa_preinitialize_commands(h); |
2e9d1b36 | 7875 | return 0; |
2c143342 RE |
7876 | clean_up: |
7877 | hpsa_free_cmd_pool(h); | |
7878 | return -ENOMEM; | |
2e9d1b36 SC |
7879 | } |
7880 | ||
41b3cf08 SC |
7881 | static void hpsa_irq_affinity_hints(struct ctlr_info *h) |
7882 | { | |
ec429952 | 7883 | int i, cpu; |
41b3cf08 SC |
7884 | |
7885 | cpu = cpumask_first(cpu_online_mask); | |
7886 | for (i = 0; i < h->msix_vector; i++) { | |
ec429952 | 7887 | irq_set_affinity_hint(h->intr[i], get_cpu_mask(cpu)); |
41b3cf08 SC |
7888 | cpu = cpumask_next(cpu, cpu_online_mask); |
7889 | } | |
7890 | } | |
7891 | ||
ec501a18 RE |
7892 | /* clear affinity hints and free MSI-X, MSI, or legacy INTx vectors */ |
7893 | static void hpsa_free_irqs(struct ctlr_info *h) | |
7894 | { | |
7895 | int i; | |
7896 | ||
7897 | if (!h->msix_vector || h->intr_mode != PERF_MODE_INT) { | |
7898 | /* Single reply queue, only one irq to free */ | |
7899 | i = h->intr_mode; | |
7900 | irq_set_affinity_hint(h->intr[i], NULL); | |
7901 | free_irq(h->intr[i], &h->q[i]); | |
105a3dbc | 7902 | h->q[i] = 0; |
ec501a18 RE |
7903 | return; |
7904 | } | |
7905 | ||
7906 | for (i = 0; i < h->msix_vector; i++) { | |
7907 | irq_set_affinity_hint(h->intr[i], NULL); | |
7908 | free_irq(h->intr[i], &h->q[i]); | |
105a3dbc | 7909 | h->q[i] = 0; |
ec501a18 | 7910 | } |
a4e17fc1 RE |
7911 | for (; i < MAX_REPLY_QUEUES; i++) |
7912 | h->q[i] = 0; | |
ec501a18 RE |
7913 | } |
7914 | ||
9ee61794 RE |
7915 | /* returns 0 on success; cleans up and returns -Enn on error */ |
7916 | static int hpsa_request_irqs(struct ctlr_info *h, | |
0ae01a32 SC |
7917 | irqreturn_t (*msixhandler)(int, void *), |
7918 | irqreturn_t (*intxhandler)(int, void *)) | |
7919 | { | |
254f796b | 7920 | int rc, i; |
0ae01a32 | 7921 | |
254f796b MG |
7922 | /* |
7923 | * initialize h->q[x] = x so that interrupt handlers know which | |
7924 | * queue to process. | |
7925 | */ | |
7926 | for (i = 0; i < MAX_REPLY_QUEUES; i++) | |
7927 | h->q[i] = (u8) i; | |
7928 | ||
eee0f03a | 7929 | if (h->intr_mode == PERF_MODE_INT && h->msix_vector > 0) { |
254f796b | 7930 | /* If performant mode and MSI-X, use multiple reply queues */ |
a4e17fc1 | 7931 | for (i = 0; i < h->msix_vector; i++) { |
8b47004a | 7932 | sprintf(h->intrname[i], "%s-msix%d", h->devname, i); |
254f796b | 7933 | rc = request_irq(h->intr[i], msixhandler, |
8b47004a | 7934 | 0, h->intrname[i], |
254f796b | 7935 | &h->q[i]); |
a4e17fc1 RE |
7936 | if (rc) { |
7937 | int j; | |
7938 | ||
7939 | dev_err(&h->pdev->dev, | |
7940 | "failed to get irq %d for %s\n", | |
7941 | h->intr[i], h->devname); | |
7942 | for (j = 0; j < i; j++) { | |
7943 | free_irq(h->intr[j], &h->q[j]); | |
7944 | h->q[j] = 0; | |
7945 | } | |
7946 | for (; j < MAX_REPLY_QUEUES; j++) | |
7947 | h->q[j] = 0; | |
7948 | return rc; | |
7949 | } | |
7950 | } | |
41b3cf08 | 7951 | hpsa_irq_affinity_hints(h); |
254f796b MG |
7952 | } else { |
7953 | /* Use single reply pool */ | |
eee0f03a | 7954 | if (h->msix_vector > 0 || h->msi_vector) { |
8b47004a RE |
7955 | if (h->msix_vector) |
7956 | sprintf(h->intrname[h->intr_mode], | |
7957 | "%s-msix", h->devname); | |
7958 | else | |
7959 | sprintf(h->intrname[h->intr_mode], | |
7960 | "%s-msi", h->devname); | |
254f796b | 7961 | rc = request_irq(h->intr[h->intr_mode], |
8b47004a RE |
7962 | msixhandler, 0, |
7963 | h->intrname[h->intr_mode], | |
254f796b MG |
7964 | &h->q[h->intr_mode]); |
7965 | } else { | |
8b47004a RE |
7966 | sprintf(h->intrname[h->intr_mode], |
7967 | "%s-intx", h->devname); | |
254f796b | 7968 | rc = request_irq(h->intr[h->intr_mode], |
8b47004a RE |
7969 | intxhandler, IRQF_SHARED, |
7970 | h->intrname[h->intr_mode], | |
254f796b MG |
7971 | &h->q[h->intr_mode]); |
7972 | } | |
105a3dbc | 7973 | irq_set_affinity_hint(h->intr[h->intr_mode], NULL); |
254f796b | 7974 | } |
0ae01a32 | 7975 | if (rc) { |
195f2c65 | 7976 | dev_err(&h->pdev->dev, "failed to get irq %d for %s\n", |
0ae01a32 | 7977 | h->intr[h->intr_mode], h->devname); |
195f2c65 | 7978 | hpsa_free_irqs(h); |
0ae01a32 SC |
7979 | return -ENODEV; |
7980 | } | |
7981 | return 0; | |
7982 | } | |
7983 | ||
6f039790 | 7984 | static int hpsa_kdump_soft_reset(struct ctlr_info *h) |
64670ac8 | 7985 | { |
39c53f55 | 7986 | int rc; |
bf43caf3 | 7987 | hpsa_send_host_reset(h, RAID_CTLR_LUNID, HPSA_RESET_TYPE_CONTROLLER); |
64670ac8 SC |
7988 | |
7989 | dev_info(&h->pdev->dev, "Waiting for board to soft reset.\n"); | |
39c53f55 RE |
7990 | rc = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_NOT_READY); |
7991 | if (rc) { | |
64670ac8 | 7992 | dev_warn(&h->pdev->dev, "Soft reset had no effect.\n"); |
39c53f55 | 7993 | return rc; |
64670ac8 SC |
7994 | } |
7995 | ||
7996 | dev_info(&h->pdev->dev, "Board reset, awaiting READY status.\n"); | |
39c53f55 RE |
7997 | rc = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY); |
7998 | if (rc) { | |
64670ac8 SC |
7999 | dev_warn(&h->pdev->dev, "Board failed to become ready " |
8000 | "after soft reset.\n"); | |
39c53f55 | 8001 | return rc; |
64670ac8 SC |
8002 | } |
8003 | ||
8004 | return 0; | |
8005 | } | |
8006 | ||
072b0518 SC |
8007 | static void hpsa_free_reply_queues(struct ctlr_info *h) |
8008 | { | |
8009 | int i; | |
8010 | ||
8011 | for (i = 0; i < h->nreply_queues; i++) { | |
8012 | if (!h->reply_queue[i].head) | |
8013 | continue; | |
1fb7c98a RE |
8014 | pci_free_consistent(h->pdev, |
8015 | h->reply_queue_size, | |
8016 | h->reply_queue[i].head, | |
8017 | h->reply_queue[i].busaddr); | |
072b0518 SC |
8018 | h->reply_queue[i].head = NULL; |
8019 | h->reply_queue[i].busaddr = 0; | |
8020 | } | |
105a3dbc | 8021 | h->reply_queue_size = 0; |
072b0518 SC |
8022 | } |
8023 | ||
0097f0f4 SC |
8024 | static void hpsa_undo_allocations_after_kdump_soft_reset(struct ctlr_info *h) |
8025 | { | |
105a3dbc RE |
8026 | hpsa_free_performant_mode(h); /* init_one 7 */ |
8027 | hpsa_free_sg_chain_blocks(h); /* init_one 6 */ | |
8028 | hpsa_free_cmd_pool(h); /* init_one 5 */ | |
8029 | hpsa_free_irqs(h); /* init_one 4 */ | |
2946e82b RE |
8030 | scsi_host_put(h->scsi_host); /* init_one 3 */ |
8031 | h->scsi_host = NULL; /* init_one 3 */ | |
8032 | hpsa_free_pci_init(h); /* init_one 2_5 */ | |
9ecd953a RE |
8033 | free_percpu(h->lockup_detected); /* init_one 2 */ |
8034 | h->lockup_detected = NULL; /* init_one 2 */ | |
8035 | if (h->resubmit_wq) { | |
8036 | destroy_workqueue(h->resubmit_wq); /* init_one 1 */ | |
8037 | h->resubmit_wq = NULL; | |
8038 | } | |
8039 | if (h->rescan_ctlr_wq) { | |
8040 | destroy_workqueue(h->rescan_ctlr_wq); | |
8041 | h->rescan_ctlr_wq = NULL; | |
8042 | } | |
105a3dbc | 8043 | kfree(h); /* init_one 1 */ |
64670ac8 SC |
8044 | } |
8045 | ||
a0c12413 | 8046 | /* Called when controller lockup detected. */ |
f2405db8 | 8047 | static void fail_all_outstanding_cmds(struct ctlr_info *h) |
a0c12413 | 8048 | { |
281a7fd0 WS |
8049 | int i, refcount; |
8050 | struct CommandList *c; | |
25163bd5 | 8051 | int failcount = 0; |
a0c12413 | 8052 | |
080ef1cc | 8053 | flush_workqueue(h->resubmit_wq); /* ensure all cmds are fully built */ |
f2405db8 | 8054 | for (i = 0; i < h->nr_cmds; i++) { |
f2405db8 | 8055 | c = h->cmd_pool + i; |
281a7fd0 WS |
8056 | refcount = atomic_inc_return(&c->refcount); |
8057 | if (refcount > 1) { | |
25163bd5 | 8058 | c->err_info->CommandStatus = CMD_CTLR_LOCKUP; |
281a7fd0 | 8059 | finish_cmd(c); |
433b5f4d | 8060 | atomic_dec(&h->commands_outstanding); |
25163bd5 | 8061 | failcount++; |
281a7fd0 WS |
8062 | } |
8063 | cmd_free(h, c); | |
a0c12413 | 8064 | } |
25163bd5 WS |
8065 | dev_warn(&h->pdev->dev, |
8066 | "failed %d commands in fail_all\n", failcount); | |
a0c12413 SC |
8067 | } |
8068 | ||
094963da SC |
8069 | static void set_lockup_detected_for_all_cpus(struct ctlr_info *h, u32 value) |
8070 | { | |
c8ed0010 | 8071 | int cpu; |
094963da | 8072 | |
c8ed0010 | 8073 | for_each_online_cpu(cpu) { |
094963da SC |
8074 | u32 *lockup_detected; |
8075 | lockup_detected = per_cpu_ptr(h->lockup_detected, cpu); | |
8076 | *lockup_detected = value; | |
094963da SC |
8077 | } |
8078 | wmb(); /* be sure the per-cpu variables are out to memory */ | |
8079 | } | |
8080 | ||
a0c12413 SC |
8081 | static void controller_lockup_detected(struct ctlr_info *h) |
8082 | { | |
8083 | unsigned long flags; | |
094963da | 8084 | u32 lockup_detected; |
a0c12413 | 8085 | |
a0c12413 SC |
8086 | h->access.set_intr_mask(h, HPSA_INTR_OFF); |
8087 | spin_lock_irqsave(&h->lock, flags); | |
094963da SC |
8088 | lockup_detected = readl(h->vaddr + SA5_SCRATCHPAD_OFFSET); |
8089 | if (!lockup_detected) { | |
8090 | /* no heartbeat, but controller gave us a zero. */ | |
8091 | dev_warn(&h->pdev->dev, | |
25163bd5 WS |
8092 | "lockup detected after %d but scratchpad register is zero\n", |
8093 | h->heartbeat_sample_interval / HZ); | |
094963da SC |
8094 | lockup_detected = 0xffffffff; |
8095 | } | |
8096 | set_lockup_detected_for_all_cpus(h, lockup_detected); | |
a0c12413 | 8097 | spin_unlock_irqrestore(&h->lock, flags); |
25163bd5 WS |
8098 | dev_warn(&h->pdev->dev, "Controller lockup detected: 0x%08x after %d\n", |
8099 | lockup_detected, h->heartbeat_sample_interval / HZ); | |
a0c12413 | 8100 | pci_disable_device(h->pdev); |
f2405db8 | 8101 | fail_all_outstanding_cmds(h); |
a0c12413 SC |
8102 | } |
8103 | ||
25163bd5 | 8104 | static int detect_controller_lockup(struct ctlr_info *h) |
a0c12413 SC |
8105 | { |
8106 | u64 now; | |
8107 | u32 heartbeat; | |
8108 | unsigned long flags; | |
8109 | ||
a0c12413 SC |
8110 | now = get_jiffies_64(); |
8111 | /* If we've received an interrupt recently, we're ok. */ | |
8112 | if (time_after64(h->last_intr_timestamp + | |
e85c5974 | 8113 | (h->heartbeat_sample_interval), now)) |
25163bd5 | 8114 | return false; |
a0c12413 SC |
8115 | |
8116 | /* | |
8117 | * If we've already checked the heartbeat recently, we're ok. | |
8118 | * This could happen if someone sends us a signal. We | |
8119 | * otherwise don't care about signals in this thread. | |
8120 | */ | |
8121 | if (time_after64(h->last_heartbeat_timestamp + | |
e85c5974 | 8122 | (h->heartbeat_sample_interval), now)) |
25163bd5 | 8123 | return false; |
a0c12413 SC |
8124 | |
8125 | /* If heartbeat has not changed since we last looked, we're not ok. */ | |
8126 | spin_lock_irqsave(&h->lock, flags); | |
8127 | heartbeat = readl(&h->cfgtable->HeartBeat); | |
8128 | spin_unlock_irqrestore(&h->lock, flags); | |
8129 | if (h->last_heartbeat == heartbeat) { | |
8130 | controller_lockup_detected(h); | |
25163bd5 | 8131 | return true; |
a0c12413 SC |
8132 | } |
8133 | ||
8134 | /* We're ok. */ | |
8135 | h->last_heartbeat = heartbeat; | |
8136 | h->last_heartbeat_timestamp = now; | |
25163bd5 | 8137 | return false; |
a0c12413 SC |
8138 | } |
8139 | ||
9846590e | 8140 | static void hpsa_ack_ctlr_events(struct ctlr_info *h) |
76438d08 SC |
8141 | { |
8142 | int i; | |
8143 | char *event_type; | |
8144 | ||
e4aa3e6a SC |
8145 | if (!(h->fw_support & MISC_FW_EVENT_NOTIFY)) |
8146 | return; | |
8147 | ||
76438d08 | 8148 | /* Ask the controller to clear the events we're handling. */ |
1f7cee8c SC |
8149 | if ((h->transMethod & (CFGTBL_Trans_io_accel1 |
8150 | | CFGTBL_Trans_io_accel2)) && | |
76438d08 SC |
8151 | (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE || |
8152 | h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)) { | |
8153 | ||
8154 | if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE) | |
8155 | event_type = "state change"; | |
8156 | if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE) | |
8157 | event_type = "configuration change"; | |
8158 | /* Stop sending new RAID offload reqs via the IO accelerator */ | |
8159 | scsi_block_requests(h->scsi_host); | |
8160 | for (i = 0; i < h->ndevices; i++) | |
8161 | h->dev[i]->offload_enabled = 0; | |
23100dd9 | 8162 | hpsa_drain_accel_commands(h); |
76438d08 SC |
8163 | /* Set 'accelerator path config change' bit */ |
8164 | dev_warn(&h->pdev->dev, | |
8165 | "Acknowledging event: 0x%08x (HP SSD Smart Path %s)\n", | |
8166 | h->events, event_type); | |
8167 | writel(h->events, &(h->cfgtable->clear_event_notify)); | |
8168 | /* Set the "clear event notify field update" bit 6 */ | |
8169 | writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL); | |
8170 | /* Wait until ctlr clears 'clear event notify field', bit 6 */ | |
8171 | hpsa_wait_for_clear_event_notify_ack(h); | |
8172 | scsi_unblock_requests(h->scsi_host); | |
8173 | } else { | |
8174 | /* Acknowledge controller notification events. */ | |
8175 | writel(h->events, &(h->cfgtable->clear_event_notify)); | |
8176 | writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL); | |
8177 | hpsa_wait_for_clear_event_notify_ack(h); | |
8178 | #if 0 | |
8179 | writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL); | |
8180 | hpsa_wait_for_mode_change_ack(h); | |
8181 | #endif | |
8182 | } | |
9846590e | 8183 | return; |
76438d08 SC |
8184 | } |
8185 | ||
8186 | /* Check a register on the controller to see if there are configuration | |
8187 | * changes (added/changed/removed logical drives, etc.) which mean that | |
e863d68e ST |
8188 | * we should rescan the controller for devices. |
8189 | * Also check flag for driver-initiated rescan. | |
76438d08 | 8190 | */ |
9846590e | 8191 | static int hpsa_ctlr_needs_rescan(struct ctlr_info *h) |
76438d08 | 8192 | { |
853633e8 DB |
8193 | if (h->drv_req_rescan) { |
8194 | h->drv_req_rescan = 0; | |
8195 | return 1; | |
8196 | } | |
8197 | ||
76438d08 | 8198 | if (!(h->fw_support & MISC_FW_EVENT_NOTIFY)) |
9846590e | 8199 | return 0; |
76438d08 SC |
8200 | |
8201 | h->events = readl(&(h->cfgtable->event_notify)); | |
9846590e SC |
8202 | return h->events & RESCAN_REQUIRED_EVENT_BITS; |
8203 | } | |
76438d08 | 8204 | |
9846590e SC |
8205 | /* |
8206 | * Check if any of the offline devices have become ready | |
8207 | */ | |
8208 | static int hpsa_offline_devices_ready(struct ctlr_info *h) | |
8209 | { | |
8210 | unsigned long flags; | |
8211 | struct offline_device_entry *d; | |
8212 | struct list_head *this, *tmp; | |
8213 | ||
8214 | spin_lock_irqsave(&h->offline_device_lock, flags); | |
8215 | list_for_each_safe(this, tmp, &h->offline_device_list) { | |
8216 | d = list_entry(this, struct offline_device_entry, | |
8217 | offline_list); | |
8218 | spin_unlock_irqrestore(&h->offline_device_lock, flags); | |
d1fea47c SC |
8219 | if (!hpsa_volume_offline(h, d->scsi3addr)) { |
8220 | spin_lock_irqsave(&h->offline_device_lock, flags); | |
8221 | list_del(&d->offline_list); | |
8222 | spin_unlock_irqrestore(&h->offline_device_lock, flags); | |
9846590e | 8223 | return 1; |
d1fea47c | 8224 | } |
9846590e SC |
8225 | spin_lock_irqsave(&h->offline_device_lock, flags); |
8226 | } | |
8227 | spin_unlock_irqrestore(&h->offline_device_lock, flags); | |
8228 | return 0; | |
76438d08 SC |
8229 | } |
8230 | ||
34592254 ST |
8231 | static int hpsa_luns_changed(struct ctlr_info *h) |
8232 | { | |
8233 | int rc = 1; /* assume there are changes */ | |
8234 | struct ReportLUNdata *logdev = NULL; | |
8235 | ||
8236 | /* if we can't find out if lun data has changed, | |
8237 | * assume that it has. | |
8238 | */ | |
8239 | ||
8240 | if (!h->lastlogicals) | |
8241 | goto out; | |
8242 | ||
8243 | logdev = kzalloc(sizeof(*logdev), GFP_KERNEL); | |
8244 | if (!logdev) { | |
8245 | dev_warn(&h->pdev->dev, | |
8246 | "Out of memory, can't track lun changes.\n"); | |
8247 | goto out; | |
8248 | } | |
8249 | if (hpsa_scsi_do_report_luns(h, 1, logdev, sizeof(*logdev), 0)) { | |
8250 | dev_warn(&h->pdev->dev, | |
8251 | "report luns failed, can't track lun changes.\n"); | |
8252 | goto out; | |
8253 | } | |
8254 | if (memcmp(logdev, h->lastlogicals, sizeof(*logdev))) { | |
8255 | dev_info(&h->pdev->dev, | |
8256 | "Lun changes detected.\n"); | |
8257 | memcpy(h->lastlogicals, logdev, sizeof(*logdev)); | |
8258 | goto out; | |
8259 | } else | |
8260 | rc = 0; /* no changes detected. */ | |
8261 | out: | |
8262 | kfree(logdev); | |
8263 | return rc; | |
8264 | } | |
8265 | ||
6636e7f4 | 8266 | static void hpsa_rescan_ctlr_worker(struct work_struct *work) |
a0c12413 SC |
8267 | { |
8268 | unsigned long flags; | |
8a98db73 | 8269 | struct ctlr_info *h = container_of(to_delayed_work(work), |
6636e7f4 DB |
8270 | struct ctlr_info, rescan_ctlr_work); |
8271 | ||
8272 | ||
8273 | if (h->remove_in_progress) | |
8a98db73 | 8274 | return; |
9846590e SC |
8275 | |
8276 | if (hpsa_ctlr_needs_rescan(h) || hpsa_offline_devices_ready(h)) { | |
8277 | scsi_host_get(h->scsi_host); | |
9846590e SC |
8278 | hpsa_ack_ctlr_events(h); |
8279 | hpsa_scan_start(h->scsi_host); | |
8280 | scsi_host_put(h->scsi_host); | |
34592254 | 8281 | } else if (h->discovery_polling) { |
c2adae44 | 8282 | hpsa_disable_rld_caching(h); |
34592254 ST |
8283 | if (hpsa_luns_changed(h)) { |
8284 | struct Scsi_Host *sh = NULL; | |
8285 | ||
8286 | dev_info(&h->pdev->dev, | |
8287 | "driver discovery polling rescan.\n"); | |
8288 | sh = scsi_host_get(h->scsi_host); | |
8289 | if (sh != NULL) { | |
8290 | hpsa_scan_start(sh); | |
8291 | scsi_host_put(sh); | |
8292 | } | |
8293 | } | |
9846590e | 8294 | } |
8a98db73 | 8295 | spin_lock_irqsave(&h->lock, flags); |
6636e7f4 DB |
8296 | if (!h->remove_in_progress) |
8297 | queue_delayed_work(h->rescan_ctlr_wq, &h->rescan_ctlr_work, | |
8298 | h->heartbeat_sample_interval); | |
8299 | spin_unlock_irqrestore(&h->lock, flags); | |
8300 | } | |
8301 | ||
8302 | static void hpsa_monitor_ctlr_worker(struct work_struct *work) | |
8303 | { | |
8304 | unsigned long flags; | |
8305 | struct ctlr_info *h = container_of(to_delayed_work(work), | |
8306 | struct ctlr_info, monitor_ctlr_work); | |
8307 | ||
8308 | detect_controller_lockup(h); | |
8309 | if (lockup_detected(h)) | |
a0c12413 | 8310 | return; |
6636e7f4 DB |
8311 | |
8312 | spin_lock_irqsave(&h->lock, flags); | |
8313 | if (!h->remove_in_progress) | |
8314 | schedule_delayed_work(&h->monitor_ctlr_work, | |
8a98db73 SC |
8315 | h->heartbeat_sample_interval); |
8316 | spin_unlock_irqrestore(&h->lock, flags); | |
a0c12413 SC |
8317 | } |
8318 | ||
6636e7f4 DB |
8319 | static struct workqueue_struct *hpsa_create_controller_wq(struct ctlr_info *h, |
8320 | char *name) | |
8321 | { | |
8322 | struct workqueue_struct *wq = NULL; | |
6636e7f4 | 8323 | |
397ea9cb | 8324 | wq = alloc_ordered_workqueue("%s_%d_hpsa", 0, name, h->ctlr); |
6636e7f4 DB |
8325 | if (!wq) |
8326 | dev_err(&h->pdev->dev, "failed to create %s workqueue\n", name); | |
8327 | ||
8328 | return wq; | |
8329 | } | |
8330 | ||
6f039790 | 8331 | static int hpsa_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
edd16368 | 8332 | { |
4c2a8c40 | 8333 | int dac, rc; |
edd16368 | 8334 | struct ctlr_info *h; |
64670ac8 SC |
8335 | int try_soft_reset = 0; |
8336 | unsigned long flags; | |
6b6c1cd7 | 8337 | u32 board_id; |
edd16368 SC |
8338 | |
8339 | if (number_of_controllers == 0) | |
8340 | printk(KERN_INFO DRIVER_NAME "\n"); | |
edd16368 | 8341 | |
6b6c1cd7 TH |
8342 | rc = hpsa_lookup_board_id(pdev, &board_id); |
8343 | if (rc < 0) { | |
8344 | dev_warn(&pdev->dev, "Board ID not found\n"); | |
8345 | return rc; | |
8346 | } | |
8347 | ||
8348 | rc = hpsa_init_reset_devices(pdev, board_id); | |
64670ac8 SC |
8349 | if (rc) { |
8350 | if (rc != -ENOTSUPP) | |
8351 | return rc; | |
8352 | /* If the reset fails in a particular way (it has no way to do | |
8353 | * a proper hard reset, so returns -ENOTSUPP) we can try to do | |
8354 | * a soft reset once we get the controller configured up to the | |
8355 | * point that it can accept a command. | |
8356 | */ | |
8357 | try_soft_reset = 1; | |
8358 | rc = 0; | |
8359 | } | |
8360 | ||
8361 | reinit_after_soft_reset: | |
edd16368 | 8362 | |
303932fd DB |
8363 | /* Command structures must be aligned on a 32-byte boundary because |
8364 | * the 5 lower bits of the address are used by the hardware. and by | |
8365 | * the driver. See comments in hpsa.h for more info. | |
8366 | */ | |
303932fd | 8367 | BUILD_BUG_ON(sizeof(struct CommandList) % COMMANDLIST_ALIGNMENT); |
edd16368 | 8368 | h = kzalloc(sizeof(*h), GFP_KERNEL); |
105a3dbc RE |
8369 | if (!h) { |
8370 | dev_err(&pdev->dev, "Failed to allocate controller head\n"); | |
ecd9aad4 | 8371 | return -ENOMEM; |
105a3dbc | 8372 | } |
edd16368 | 8373 | |
55c06c71 | 8374 | h->pdev = pdev; |
105a3dbc | 8375 | |
a9a3a273 | 8376 | h->intr_mode = hpsa_simple_mode ? SIMPLE_MODE_INT : PERF_MODE_INT; |
9846590e | 8377 | INIT_LIST_HEAD(&h->offline_device_list); |
6eaf46fd | 8378 | spin_lock_init(&h->lock); |
9846590e | 8379 | spin_lock_init(&h->offline_device_lock); |
6eaf46fd | 8380 | spin_lock_init(&h->scan_lock); |
34f0c627 | 8381 | atomic_set(&h->passthru_cmds_avail, HPSA_MAX_CONCURRENT_PASSTHRUS); |
9b5c48c2 | 8382 | atomic_set(&h->abort_cmds_available, HPSA_CMDS_RESERVED_FOR_ABORTS); |
094963da SC |
8383 | |
8384 | /* Allocate and clear per-cpu variable lockup_detected */ | |
8385 | h->lockup_detected = alloc_percpu(u32); | |
2a5ac326 | 8386 | if (!h->lockup_detected) { |
105a3dbc | 8387 | dev_err(&h->pdev->dev, "Failed to allocate lockup detector\n"); |
2a5ac326 | 8388 | rc = -ENOMEM; |
2efa5929 | 8389 | goto clean1; /* aer/h */ |
2a5ac326 | 8390 | } |
094963da SC |
8391 | set_lockup_detected_for_all_cpus(h, 0); |
8392 | ||
55c06c71 | 8393 | rc = hpsa_pci_init(h); |
105a3dbc | 8394 | if (rc) |
2946e82b RE |
8395 | goto clean2; /* lu, aer/h */ |
8396 | ||
8397 | /* relies on h-> settings made by hpsa_pci_init, including | |
8398 | * interrupt_mode h->intr */ | |
8399 | rc = hpsa_scsi_host_alloc(h); | |
8400 | if (rc) | |
8401 | goto clean2_5; /* pci, lu, aer/h */ | |
edd16368 | 8402 | |
2946e82b | 8403 | sprintf(h->devname, HPSA "%d", h->scsi_host->host_no); |
edd16368 SC |
8404 | h->ctlr = number_of_controllers; |
8405 | number_of_controllers++; | |
edd16368 SC |
8406 | |
8407 | /* configure PCI DMA stuff */ | |
ecd9aad4 SC |
8408 | rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); |
8409 | if (rc == 0) { | |
edd16368 | 8410 | dac = 1; |
ecd9aad4 SC |
8411 | } else { |
8412 | rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
8413 | if (rc == 0) { | |
8414 | dac = 0; | |
8415 | } else { | |
8416 | dev_err(&pdev->dev, "no suitable DMA available\n"); | |
2946e82b | 8417 | goto clean3; /* shost, pci, lu, aer/h */ |
ecd9aad4 | 8418 | } |
edd16368 SC |
8419 | } |
8420 | ||
8421 | /* make sure the board interrupts are off */ | |
8422 | h->access.set_intr_mask(h, HPSA_INTR_OFF); | |
10f66018 | 8423 | |
105a3dbc RE |
8424 | rc = hpsa_request_irqs(h, do_hpsa_intr_msi, do_hpsa_intr_intx); |
8425 | if (rc) | |
2946e82b | 8426 | goto clean3; /* shost, pci, lu, aer/h */ |
d37ffbe4 | 8427 | rc = hpsa_alloc_cmd_pool(h); |
8947fd10 | 8428 | if (rc) |
2946e82b | 8429 | goto clean4; /* irq, shost, pci, lu, aer/h */ |
105a3dbc RE |
8430 | rc = hpsa_alloc_sg_chain_blocks(h); |
8431 | if (rc) | |
2946e82b | 8432 | goto clean5; /* cmd, irq, shost, pci, lu, aer/h */ |
a08a8471 | 8433 | init_waitqueue_head(&h->scan_wait_queue); |
9b5c48c2 | 8434 | init_waitqueue_head(&h->abort_cmd_wait_queue); |
d604f533 WS |
8435 | init_waitqueue_head(&h->event_sync_wait_queue); |
8436 | mutex_init(&h->reset_mutex); | |
a08a8471 | 8437 | h->scan_finished = 1; /* no scan currently in progress */ |
edd16368 SC |
8438 | |
8439 | pci_set_drvdata(pdev, h); | |
9a41338e | 8440 | h->ndevices = 0; |
2946e82b | 8441 | |
9a41338e | 8442 | spin_lock_init(&h->devlock); |
105a3dbc RE |
8443 | rc = hpsa_put_ctlr_into_performant_mode(h); |
8444 | if (rc) | |
2946e82b RE |
8445 | goto clean6; /* sg, cmd, irq, shost, pci, lu, aer/h */ |
8446 | ||
8447 | /* hook into SCSI subsystem */ | |
8448 | rc = hpsa_scsi_add_host(h); | |
8449 | if (rc) | |
8450 | goto clean7; /* perf, sg, cmd, irq, shost, pci, lu, aer/h */ | |
2efa5929 RE |
8451 | |
8452 | /* create the resubmit workqueue */ | |
8453 | h->rescan_ctlr_wq = hpsa_create_controller_wq(h, "rescan"); | |
8454 | if (!h->rescan_ctlr_wq) { | |
8455 | rc = -ENOMEM; | |
8456 | goto clean7; | |
8457 | } | |
8458 | ||
8459 | h->resubmit_wq = hpsa_create_controller_wq(h, "resubmit"); | |
8460 | if (!h->resubmit_wq) { | |
8461 | rc = -ENOMEM; | |
8462 | goto clean7; /* aer/h */ | |
8463 | } | |
64670ac8 | 8464 | |
105a3dbc RE |
8465 | /* |
8466 | * At this point, the controller is ready to take commands. | |
64670ac8 SC |
8467 | * Now, if reset_devices and the hard reset didn't work, try |
8468 | * the soft reset and see if that works. | |
8469 | */ | |
8470 | if (try_soft_reset) { | |
8471 | ||
8472 | /* This is kind of gross. We may or may not get a completion | |
8473 | * from the soft reset command, and if we do, then the value | |
8474 | * from the fifo may or may not be valid. So, we wait 10 secs | |
8475 | * after the reset throwing away any completions we get during | |
8476 | * that time. Unregister the interrupt handler and register | |
8477 | * fake ones to scoop up any residual completions. | |
8478 | */ | |
8479 | spin_lock_irqsave(&h->lock, flags); | |
8480 | h->access.set_intr_mask(h, HPSA_INTR_OFF); | |
8481 | spin_unlock_irqrestore(&h->lock, flags); | |
ec501a18 | 8482 | hpsa_free_irqs(h); |
9ee61794 | 8483 | rc = hpsa_request_irqs(h, hpsa_msix_discard_completions, |
64670ac8 SC |
8484 | hpsa_intx_discard_completions); |
8485 | if (rc) { | |
9ee61794 RE |
8486 | dev_warn(&h->pdev->dev, |
8487 | "Failed to request_irq after soft reset.\n"); | |
d498757c | 8488 | /* |
b2ef480c RE |
8489 | * cannot goto clean7 or free_irqs will be called |
8490 | * again. Instead, do its work | |
8491 | */ | |
8492 | hpsa_free_performant_mode(h); /* clean7 */ | |
8493 | hpsa_free_sg_chain_blocks(h); /* clean6 */ | |
8494 | hpsa_free_cmd_pool(h); /* clean5 */ | |
8495 | /* | |
8496 | * skip hpsa_free_irqs(h) clean4 since that | |
8497 | * was just called before request_irqs failed | |
d498757c RE |
8498 | */ |
8499 | goto clean3; | |
64670ac8 SC |
8500 | } |
8501 | ||
8502 | rc = hpsa_kdump_soft_reset(h); | |
8503 | if (rc) | |
8504 | /* Neither hard nor soft reset worked, we're hosed. */ | |
7ef7323f | 8505 | goto clean7; |
64670ac8 SC |
8506 | |
8507 | dev_info(&h->pdev->dev, "Board READY.\n"); | |
8508 | dev_info(&h->pdev->dev, | |
8509 | "Waiting for stale completions to drain.\n"); | |
8510 | h->access.set_intr_mask(h, HPSA_INTR_ON); | |
8511 | msleep(10000); | |
8512 | h->access.set_intr_mask(h, HPSA_INTR_OFF); | |
8513 | ||
8514 | rc = controller_reset_failed(h->cfgtable); | |
8515 | if (rc) | |
8516 | dev_info(&h->pdev->dev, | |
8517 | "Soft reset appears to have failed.\n"); | |
8518 | ||
8519 | /* since the controller's reset, we have to go back and re-init | |
8520 | * everything. Easiest to just forget what we've done and do it | |
8521 | * all over again. | |
8522 | */ | |
8523 | hpsa_undo_allocations_after_kdump_soft_reset(h); | |
8524 | try_soft_reset = 0; | |
8525 | if (rc) | |
b2ef480c | 8526 | /* don't goto clean, we already unallocated */ |
64670ac8 SC |
8527 | return -ENODEV; |
8528 | ||
8529 | goto reinit_after_soft_reset; | |
8530 | } | |
edd16368 | 8531 | |
105a3dbc RE |
8532 | /* Enable Accelerated IO path at driver layer */ |
8533 | h->acciopath_status = 1; | |
34592254 ST |
8534 | /* Disable discovery polling.*/ |
8535 | h->discovery_polling = 0; | |
da0697bd | 8536 | |
e863d68e | 8537 | |
edd16368 SC |
8538 | /* Turn the interrupts on so we can service requests */ |
8539 | h->access.set_intr_mask(h, HPSA_INTR_ON); | |
8540 | ||
339b2b14 | 8541 | hpsa_hba_inquiry(h); |
8a98db73 | 8542 | |
34592254 ST |
8543 | h->lastlogicals = kzalloc(sizeof(*(h->lastlogicals)), GFP_KERNEL); |
8544 | if (!h->lastlogicals) | |
8545 | dev_info(&h->pdev->dev, | |
8546 | "Can't track change to report lun data\n"); | |
8547 | ||
8a98db73 SC |
8548 | /* Monitor the controller for firmware lockups */ |
8549 | h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL; | |
8550 | INIT_DELAYED_WORK(&h->monitor_ctlr_work, hpsa_monitor_ctlr_worker); | |
8551 | schedule_delayed_work(&h->monitor_ctlr_work, | |
8552 | h->heartbeat_sample_interval); | |
6636e7f4 DB |
8553 | INIT_DELAYED_WORK(&h->rescan_ctlr_work, hpsa_rescan_ctlr_worker); |
8554 | queue_delayed_work(h->rescan_ctlr_wq, &h->rescan_ctlr_work, | |
8555 | h->heartbeat_sample_interval); | |
88bf6d62 | 8556 | return 0; |
edd16368 | 8557 | |
2946e82b | 8558 | clean7: /* perf, sg, cmd, irq, shost, pci, lu, aer/h */ |
105a3dbc RE |
8559 | hpsa_free_performant_mode(h); |
8560 | h->access.set_intr_mask(h, HPSA_INTR_OFF); | |
8561 | clean6: /* sg, cmd, irq, pci, lockup, wq/aer/h */ | |
33a2ffce | 8562 | hpsa_free_sg_chain_blocks(h); |
2946e82b | 8563 | clean5: /* cmd, irq, shost, pci, lu, aer/h */ |
2e9d1b36 | 8564 | hpsa_free_cmd_pool(h); |
2946e82b | 8565 | clean4: /* irq, shost, pci, lu, aer/h */ |
ec501a18 | 8566 | hpsa_free_irqs(h); |
2946e82b RE |
8567 | clean3: /* shost, pci, lu, aer/h */ |
8568 | scsi_host_put(h->scsi_host); | |
8569 | h->scsi_host = NULL; | |
8570 | clean2_5: /* pci, lu, aer/h */ | |
195f2c65 | 8571 | hpsa_free_pci_init(h); |
2946e82b | 8572 | clean2: /* lu, aer/h */ |
105a3dbc RE |
8573 | if (h->lockup_detected) { |
8574 | free_percpu(h->lockup_detected); | |
8575 | h->lockup_detected = NULL; | |
8576 | } | |
8577 | clean1: /* wq/aer/h */ | |
8578 | if (h->resubmit_wq) { | |
080ef1cc | 8579 | destroy_workqueue(h->resubmit_wq); |
105a3dbc RE |
8580 | h->resubmit_wq = NULL; |
8581 | } | |
8582 | if (h->rescan_ctlr_wq) { | |
6636e7f4 | 8583 | destroy_workqueue(h->rescan_ctlr_wq); |
105a3dbc RE |
8584 | h->rescan_ctlr_wq = NULL; |
8585 | } | |
edd16368 | 8586 | kfree(h); |
ecd9aad4 | 8587 | return rc; |
edd16368 SC |
8588 | } |
8589 | ||
8590 | static void hpsa_flush_cache(struct ctlr_info *h) | |
8591 | { | |
8592 | char *flush_buf; | |
8593 | struct CommandList *c; | |
25163bd5 | 8594 | int rc; |
702890e3 | 8595 | |
094963da | 8596 | if (unlikely(lockup_detected(h))) |
702890e3 | 8597 | return; |
edd16368 SC |
8598 | flush_buf = kzalloc(4, GFP_KERNEL); |
8599 | if (!flush_buf) | |
8600 | return; | |
8601 | ||
45fcb86e | 8602 | c = cmd_alloc(h); |
bf43caf3 | 8603 | |
a2dac136 SC |
8604 | if (fill_cmd(c, HPSA_CACHE_FLUSH, h, flush_buf, 4, 0, |
8605 | RAID_CTLR_LUNID, TYPE_CMD)) { | |
8606 | goto out; | |
8607 | } | |
25163bd5 WS |
8608 | rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, |
8609 | PCI_DMA_TODEVICE, NO_TIMEOUT); | |
8610 | if (rc) | |
8611 | goto out; | |
edd16368 | 8612 | if (c->err_info->CommandStatus != 0) |
a2dac136 | 8613 | out: |
edd16368 SC |
8614 | dev_warn(&h->pdev->dev, |
8615 | "error flushing cache on controller\n"); | |
45fcb86e | 8616 | cmd_free(h, c); |
edd16368 SC |
8617 | kfree(flush_buf); |
8618 | } | |
8619 | ||
c2adae44 ST |
8620 | /* Make controller gather fresh report lun data each time we |
8621 | * send down a report luns request | |
8622 | */ | |
8623 | static void hpsa_disable_rld_caching(struct ctlr_info *h) | |
8624 | { | |
8625 | u32 *options; | |
8626 | struct CommandList *c; | |
8627 | int rc; | |
8628 | ||
8629 | /* Don't bother trying to set diag options if locked up */ | |
8630 | if (unlikely(h->lockup_detected)) | |
8631 | return; | |
8632 | ||
8633 | options = kzalloc(sizeof(*options), GFP_KERNEL); | |
8634 | if (!options) { | |
8635 | dev_err(&h->pdev->dev, | |
8636 | "Error: failed to disable rld caching, during alloc.\n"); | |
8637 | return; | |
8638 | } | |
8639 | ||
8640 | c = cmd_alloc(h); | |
8641 | ||
8642 | /* first, get the current diag options settings */ | |
8643 | if (fill_cmd(c, BMIC_SENSE_DIAG_OPTIONS, h, options, 4, 0, | |
8644 | RAID_CTLR_LUNID, TYPE_CMD)) | |
8645 | goto errout; | |
8646 | ||
8647 | rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, | |
8648 | PCI_DMA_FROMDEVICE, NO_TIMEOUT); | |
8649 | if ((rc != 0) || (c->err_info->CommandStatus != 0)) | |
8650 | goto errout; | |
8651 | ||
8652 | /* Now, set the bit for disabling the RLD caching */ | |
8653 | *options |= HPSA_DIAG_OPTS_DISABLE_RLD_CACHING; | |
8654 | ||
8655 | if (fill_cmd(c, BMIC_SET_DIAG_OPTIONS, h, options, 4, 0, | |
8656 | RAID_CTLR_LUNID, TYPE_CMD)) | |
8657 | goto errout; | |
8658 | ||
8659 | rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, | |
8660 | PCI_DMA_TODEVICE, NO_TIMEOUT); | |
8661 | if ((rc != 0) || (c->err_info->CommandStatus != 0)) | |
8662 | goto errout; | |
8663 | ||
8664 | /* Now verify that it got set: */ | |
8665 | if (fill_cmd(c, BMIC_SENSE_DIAG_OPTIONS, h, options, 4, 0, | |
8666 | RAID_CTLR_LUNID, TYPE_CMD)) | |
8667 | goto errout; | |
8668 | ||
8669 | rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, | |
8670 | PCI_DMA_FROMDEVICE, NO_TIMEOUT); | |
8671 | if ((rc != 0) || (c->err_info->CommandStatus != 0)) | |
8672 | goto errout; | |
8673 | ||
d8a080c3 | 8674 | if (*options & HPSA_DIAG_OPTS_DISABLE_RLD_CACHING) |
c2adae44 ST |
8675 | goto out; |
8676 | ||
8677 | errout: | |
8678 | dev_err(&h->pdev->dev, | |
8679 | "Error: failed to disable report lun data caching.\n"); | |
8680 | out: | |
8681 | cmd_free(h, c); | |
8682 | kfree(options); | |
8683 | } | |
8684 | ||
edd16368 SC |
8685 | static void hpsa_shutdown(struct pci_dev *pdev) |
8686 | { | |
8687 | struct ctlr_info *h; | |
8688 | ||
8689 | h = pci_get_drvdata(pdev); | |
8690 | /* Turn board interrupts off and send the flush cache command | |
8691 | * sendcmd will turn off interrupt, and send the flush... | |
8692 | * To write all data in the battery backed cache to disks | |
8693 | */ | |
8694 | hpsa_flush_cache(h); | |
8695 | h->access.set_intr_mask(h, HPSA_INTR_OFF); | |
105a3dbc | 8696 | hpsa_free_irqs(h); /* init_one 4 */ |
cc64c817 | 8697 | hpsa_disable_interrupt_mode(h); /* pci_init 2 */ |
edd16368 SC |
8698 | } |
8699 | ||
6f039790 | 8700 | static void hpsa_free_device_info(struct ctlr_info *h) |
55e14e76 SC |
8701 | { |
8702 | int i; | |
8703 | ||
105a3dbc | 8704 | for (i = 0; i < h->ndevices; i++) { |
55e14e76 | 8705 | kfree(h->dev[i]); |
105a3dbc RE |
8706 | h->dev[i] = NULL; |
8707 | } | |
55e14e76 SC |
8708 | } |
8709 | ||
6f039790 | 8710 | static void hpsa_remove_one(struct pci_dev *pdev) |
edd16368 SC |
8711 | { |
8712 | struct ctlr_info *h; | |
8a98db73 | 8713 | unsigned long flags; |
edd16368 SC |
8714 | |
8715 | if (pci_get_drvdata(pdev) == NULL) { | |
a0c12413 | 8716 | dev_err(&pdev->dev, "unable to remove device\n"); |
edd16368 SC |
8717 | return; |
8718 | } | |
8719 | h = pci_get_drvdata(pdev); | |
8a98db73 SC |
8720 | |
8721 | /* Get rid of any controller monitoring work items */ | |
8722 | spin_lock_irqsave(&h->lock, flags); | |
8723 | h->remove_in_progress = 1; | |
8a98db73 | 8724 | spin_unlock_irqrestore(&h->lock, flags); |
6636e7f4 DB |
8725 | cancel_delayed_work_sync(&h->monitor_ctlr_work); |
8726 | cancel_delayed_work_sync(&h->rescan_ctlr_work); | |
8727 | destroy_workqueue(h->rescan_ctlr_wq); | |
8728 | destroy_workqueue(h->resubmit_wq); | |
cc64c817 | 8729 | |
2d041306 DB |
8730 | /* |
8731 | * Call before disabling interrupts. | |
8732 | * scsi_remove_host can trigger I/O operations especially | |
8733 | * when multipath is enabled. There can be SYNCHRONIZE CACHE | |
8734 | * operations which cannot complete and will hang the system. | |
8735 | */ | |
8736 | if (h->scsi_host) | |
8737 | scsi_remove_host(h->scsi_host); /* init_one 8 */ | |
105a3dbc | 8738 | /* includes hpsa_free_irqs - init_one 4 */ |
195f2c65 | 8739 | /* includes hpsa_disable_interrupt_mode - pci_init 2 */ |
edd16368 | 8740 | hpsa_shutdown(pdev); |
cc64c817 | 8741 | |
105a3dbc RE |
8742 | hpsa_free_device_info(h); /* scan */ |
8743 | ||
2946e82b RE |
8744 | kfree(h->hba_inquiry_data); /* init_one 10 */ |
8745 | h->hba_inquiry_data = NULL; /* init_one 10 */ | |
2946e82b | 8746 | hpsa_free_ioaccel2_sg_chain_blocks(h); |
105a3dbc RE |
8747 | hpsa_free_performant_mode(h); /* init_one 7 */ |
8748 | hpsa_free_sg_chain_blocks(h); /* init_one 6 */ | |
8749 | hpsa_free_cmd_pool(h); /* init_one 5 */ | |
34592254 | 8750 | kfree(h->lastlogicals); |
105a3dbc RE |
8751 | |
8752 | /* hpsa_free_irqs already called via hpsa_shutdown init_one 4 */ | |
195f2c65 | 8753 | |
2946e82b RE |
8754 | scsi_host_put(h->scsi_host); /* init_one 3 */ |
8755 | h->scsi_host = NULL; /* init_one 3 */ | |
8756 | ||
195f2c65 | 8757 | /* includes hpsa_disable_interrupt_mode - pci_init 2 */ |
2946e82b | 8758 | hpsa_free_pci_init(h); /* init_one 2.5 */ |
195f2c65 | 8759 | |
105a3dbc RE |
8760 | free_percpu(h->lockup_detected); /* init_one 2 */ |
8761 | h->lockup_detected = NULL; /* init_one 2 */ | |
8762 | /* (void) pci_disable_pcie_error_reporting(pdev); */ /* init_one 1 */ | |
d04e62b9 KB |
8763 | |
8764 | hpsa_delete_sas_host(h); | |
8765 | ||
105a3dbc | 8766 | kfree(h); /* init_one 1 */ |
edd16368 SC |
8767 | } |
8768 | ||
8769 | static int hpsa_suspend(__attribute__((unused)) struct pci_dev *pdev, | |
8770 | __attribute__((unused)) pm_message_t state) | |
8771 | { | |
8772 | return -ENOSYS; | |
8773 | } | |
8774 | ||
8775 | static int hpsa_resume(__attribute__((unused)) struct pci_dev *pdev) | |
8776 | { | |
8777 | return -ENOSYS; | |
8778 | } | |
8779 | ||
8780 | static struct pci_driver hpsa_pci_driver = { | |
f79cfec6 | 8781 | .name = HPSA, |
edd16368 | 8782 | .probe = hpsa_init_one, |
6f039790 | 8783 | .remove = hpsa_remove_one, |
edd16368 SC |
8784 | .id_table = hpsa_pci_device_id, /* id_table */ |
8785 | .shutdown = hpsa_shutdown, | |
8786 | .suspend = hpsa_suspend, | |
8787 | .resume = hpsa_resume, | |
8788 | }; | |
8789 | ||
303932fd DB |
8790 | /* Fill in bucket_map[], given nsgs (the max number of |
8791 | * scatter gather elements supported) and bucket[], | |
8792 | * which is an array of 8 integers. The bucket[] array | |
8793 | * contains 8 different DMA transfer sizes (in 16 | |
8794 | * byte increments) which the controller uses to fetch | |
8795 | * commands. This function fills in bucket_map[], which | |
8796 | * maps a given number of scatter gather elements to one of | |
8797 | * the 8 DMA transfer sizes. The point of it is to allow the | |
8798 | * controller to only do as much DMA as needed to fetch the | |
8799 | * command, with the DMA transfer size encoded in the lower | |
8800 | * bits of the command address. | |
8801 | */ | |
8802 | static void calc_bucket_map(int bucket[], int num_buckets, | |
2b08b3e9 | 8803 | int nsgs, int min_blocks, u32 *bucket_map) |
303932fd DB |
8804 | { |
8805 | int i, j, b, size; | |
8806 | ||
303932fd DB |
8807 | /* Note, bucket_map must have nsgs+1 entries. */ |
8808 | for (i = 0; i <= nsgs; i++) { | |
8809 | /* Compute size of a command with i SG entries */ | |
e1f7de0c | 8810 | size = i + min_blocks; |
303932fd DB |
8811 | b = num_buckets; /* Assume the biggest bucket */ |
8812 | /* Find the bucket that is just big enough */ | |
e1f7de0c | 8813 | for (j = 0; j < num_buckets; j++) { |
303932fd DB |
8814 | if (bucket[j] >= size) { |
8815 | b = j; | |
8816 | break; | |
8817 | } | |
8818 | } | |
8819 | /* for a command with i SG entries, use bucket b. */ | |
8820 | bucket_map[i] = b; | |
8821 | } | |
8822 | } | |
8823 | ||
105a3dbc RE |
8824 | /* |
8825 | * return -ENODEV on err, 0 on success (or no action) | |
8826 | * allocates numerous items that must be freed later | |
8827 | */ | |
c706a795 | 8828 | static int hpsa_enter_performant_mode(struct ctlr_info *h, u32 trans_support) |
303932fd | 8829 | { |
6c311b57 SC |
8830 | int i; |
8831 | unsigned long register_value; | |
e1f7de0c MG |
8832 | unsigned long transMethod = CFGTBL_Trans_Performant | |
8833 | (trans_support & CFGTBL_Trans_use_short_tags) | | |
b9af4937 SC |
8834 | CFGTBL_Trans_enable_directed_msix | |
8835 | (trans_support & (CFGTBL_Trans_io_accel1 | | |
8836 | CFGTBL_Trans_io_accel2)); | |
e1f7de0c | 8837 | struct access_method access = SA5_performant_access; |
def342bd SC |
8838 | |
8839 | /* This is a bit complicated. There are 8 registers on | |
8840 | * the controller which we write to to tell it 8 different | |
8841 | * sizes of commands which there may be. It's a way of | |
8842 | * reducing the DMA done to fetch each command. Encoded into | |
8843 | * each command's tag are 3 bits which communicate to the controller | |
8844 | * which of the eight sizes that command fits within. The size of | |
8845 | * each command depends on how many scatter gather entries there are. | |
8846 | * Each SG entry requires 16 bytes. The eight registers are programmed | |
8847 | * with the number of 16-byte blocks a command of that size requires. | |
8848 | * The smallest command possible requires 5 such 16 byte blocks. | |
d66ae08b | 8849 | * the largest command possible requires SG_ENTRIES_IN_CMD + 4 16-byte |
def342bd SC |
8850 | * blocks. Note, this only extends to the SG entries contained |
8851 | * within the command block, and does not extend to chained blocks | |
8852 | * of SG elements. bft[] contains the eight values we write to | |
8853 | * the registers. They are not evenly distributed, but have more | |
8854 | * sizes for small commands, and fewer sizes for larger commands. | |
8855 | */ | |
d66ae08b | 8856 | int bft[8] = {5, 6, 8, 10, 12, 20, 28, SG_ENTRIES_IN_CMD + 4}; |
b9af4937 SC |
8857 | #define MIN_IOACCEL2_BFT_ENTRY 5 |
8858 | #define HPSA_IOACCEL2_HEADER_SZ 4 | |
8859 | int bft2[16] = {MIN_IOACCEL2_BFT_ENTRY, 6, 7, 8, 9, 10, 11, 12, | |
8860 | 13, 14, 15, 16, 17, 18, 19, | |
8861 | HPSA_IOACCEL2_HEADER_SZ + IOACCEL2_MAXSGENTRIES}; | |
8862 | BUILD_BUG_ON(ARRAY_SIZE(bft2) != 16); | |
8863 | BUILD_BUG_ON(ARRAY_SIZE(bft) != 8); | |
8864 | BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) > | |
8865 | 16 * MIN_IOACCEL2_BFT_ENTRY); | |
8866 | BUILD_BUG_ON(sizeof(struct ioaccel2_sg_element) != 16); | |
d66ae08b | 8867 | BUILD_BUG_ON(28 > SG_ENTRIES_IN_CMD + 4); |
303932fd DB |
8868 | /* 5 = 1 s/g entry or 4k |
8869 | * 6 = 2 s/g entry or 8k | |
8870 | * 8 = 4 s/g entry or 16k | |
8871 | * 10 = 6 s/g entry or 24k | |
8872 | */ | |
303932fd | 8873 | |
b3a52e79 SC |
8874 | /* If the controller supports either ioaccel method then |
8875 | * we can also use the RAID stack submit path that does not | |
8876 | * perform the superfluous readl() after each command submission. | |
8877 | */ | |
8878 | if (trans_support & (CFGTBL_Trans_io_accel1 | CFGTBL_Trans_io_accel2)) | |
8879 | access = SA5_performant_access_no_read; | |
8880 | ||
303932fd | 8881 | /* Controller spec: zero out this buffer. */ |
072b0518 SC |
8882 | for (i = 0; i < h->nreply_queues; i++) |
8883 | memset(h->reply_queue[i].head, 0, h->reply_queue_size); | |
303932fd | 8884 | |
d66ae08b SC |
8885 | bft[7] = SG_ENTRIES_IN_CMD + 4; |
8886 | calc_bucket_map(bft, ARRAY_SIZE(bft), | |
e1f7de0c | 8887 | SG_ENTRIES_IN_CMD, 4, h->blockFetchTable); |
303932fd DB |
8888 | for (i = 0; i < 8; i++) |
8889 | writel(bft[i], &h->transtable->BlockFetch[i]); | |
8890 | ||
8891 | /* size of controller ring buffer */ | |
8892 | writel(h->max_commands, &h->transtable->RepQSize); | |
254f796b | 8893 | writel(h->nreply_queues, &h->transtable->RepQCount); |
303932fd DB |
8894 | writel(0, &h->transtable->RepQCtrAddrLow32); |
8895 | writel(0, &h->transtable->RepQCtrAddrHigh32); | |
254f796b MG |
8896 | |
8897 | for (i = 0; i < h->nreply_queues; i++) { | |
8898 | writel(0, &h->transtable->RepQAddr[i].upper); | |
072b0518 | 8899 | writel(h->reply_queue[i].busaddr, |
254f796b MG |
8900 | &h->transtable->RepQAddr[i].lower); |
8901 | } | |
8902 | ||
b9af4937 | 8903 | writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi); |
e1f7de0c MG |
8904 | writel(transMethod, &(h->cfgtable->HostWrite.TransportRequest)); |
8905 | /* | |
8906 | * enable outbound interrupt coalescing in accelerator mode; | |
8907 | */ | |
8908 | if (trans_support & CFGTBL_Trans_io_accel1) { | |
8909 | access = SA5_ioaccel_mode1_access; | |
8910 | writel(10, &h->cfgtable->HostWrite.CoalIntDelay); | |
8911 | writel(4, &h->cfgtable->HostWrite.CoalIntCount); | |
c349775e ST |
8912 | } else { |
8913 | if (trans_support & CFGTBL_Trans_io_accel2) { | |
8914 | access = SA5_ioaccel_mode2_access; | |
8915 | writel(10, &h->cfgtable->HostWrite.CoalIntDelay); | |
8916 | writel(4, &h->cfgtable->HostWrite.CoalIntCount); | |
8917 | } | |
e1f7de0c | 8918 | } |
303932fd | 8919 | writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL); |
c706a795 RE |
8920 | if (hpsa_wait_for_mode_change_ack(h)) { |
8921 | dev_err(&h->pdev->dev, | |
8922 | "performant mode problem - doorbell timeout\n"); | |
8923 | return -ENODEV; | |
8924 | } | |
303932fd DB |
8925 | register_value = readl(&(h->cfgtable->TransportActive)); |
8926 | if (!(register_value & CFGTBL_Trans_Performant)) { | |
050f7147 SC |
8927 | dev_err(&h->pdev->dev, |
8928 | "performant mode problem - transport not active\n"); | |
c706a795 | 8929 | return -ENODEV; |
303932fd | 8930 | } |
960a30e7 | 8931 | /* Change the access methods to the performant access methods */ |
e1f7de0c MG |
8932 | h->access = access; |
8933 | h->transMethod = transMethod; | |
8934 | ||
b9af4937 SC |
8935 | if (!((trans_support & CFGTBL_Trans_io_accel1) || |
8936 | (trans_support & CFGTBL_Trans_io_accel2))) | |
c706a795 | 8937 | return 0; |
e1f7de0c | 8938 | |
b9af4937 SC |
8939 | if (trans_support & CFGTBL_Trans_io_accel1) { |
8940 | /* Set up I/O accelerator mode */ | |
8941 | for (i = 0; i < h->nreply_queues; i++) { | |
8942 | writel(i, h->vaddr + IOACCEL_MODE1_REPLY_QUEUE_INDEX); | |
8943 | h->reply_queue[i].current_entry = | |
8944 | readl(h->vaddr + IOACCEL_MODE1_PRODUCER_INDEX); | |
8945 | } | |
8946 | bft[7] = h->ioaccel_maxsg + 8; | |
8947 | calc_bucket_map(bft, ARRAY_SIZE(bft), h->ioaccel_maxsg, 8, | |
8948 | h->ioaccel1_blockFetchTable); | |
e1f7de0c | 8949 | |
b9af4937 | 8950 | /* initialize all reply queue entries to unused */ |
072b0518 SC |
8951 | for (i = 0; i < h->nreply_queues; i++) |
8952 | memset(h->reply_queue[i].head, | |
8953 | (u8) IOACCEL_MODE1_REPLY_UNUSED, | |
8954 | h->reply_queue_size); | |
e1f7de0c | 8955 | |
b9af4937 SC |
8956 | /* set all the constant fields in the accelerator command |
8957 | * frames once at init time to save CPU cycles later. | |
8958 | */ | |
8959 | for (i = 0; i < h->nr_cmds; i++) { | |
8960 | struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[i]; | |
8961 | ||
8962 | cp->function = IOACCEL1_FUNCTION_SCSIIO; | |
8963 | cp->err_info = (u32) (h->errinfo_pool_dhandle + | |
8964 | (i * sizeof(struct ErrorInfo))); | |
8965 | cp->err_info_len = sizeof(struct ErrorInfo); | |
8966 | cp->sgl_offset = IOACCEL1_SGLOFFSET; | |
2b08b3e9 DB |
8967 | cp->host_context_flags = |
8968 | cpu_to_le16(IOACCEL1_HCFLAGS_CISS_FORMAT); | |
b9af4937 SC |
8969 | cp->timeout_sec = 0; |
8970 | cp->ReplyQueue = 0; | |
50a0decf | 8971 | cp->tag = |
f2405db8 | 8972 | cpu_to_le64((i << DIRECT_LOOKUP_SHIFT)); |
50a0decf SC |
8973 | cp->host_addr = |
8974 | cpu_to_le64(h->ioaccel_cmd_pool_dhandle + | |
b9af4937 | 8975 | (i * sizeof(struct io_accel1_cmd))); |
b9af4937 SC |
8976 | } |
8977 | } else if (trans_support & CFGTBL_Trans_io_accel2) { | |
8978 | u64 cfg_offset, cfg_base_addr_index; | |
8979 | u32 bft2_offset, cfg_base_addr; | |
8980 | int rc; | |
8981 | ||
8982 | rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr, | |
8983 | &cfg_base_addr_index, &cfg_offset); | |
8984 | BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) != 64); | |
8985 | bft2[15] = h->ioaccel_maxsg + HPSA_IOACCEL2_HEADER_SZ; | |
8986 | calc_bucket_map(bft2, ARRAY_SIZE(bft2), h->ioaccel_maxsg, | |
8987 | 4, h->ioaccel2_blockFetchTable); | |
8988 | bft2_offset = readl(&h->cfgtable->io_accel_request_size_offset); | |
8989 | BUILD_BUG_ON(offsetof(struct CfgTable, | |
8990 | io_accel_request_size_offset) != 0xb8); | |
8991 | h->ioaccel2_bft2_regs = | |
8992 | remap_pci_mem(pci_resource_start(h->pdev, | |
8993 | cfg_base_addr_index) + | |
8994 | cfg_offset + bft2_offset, | |
8995 | ARRAY_SIZE(bft2) * | |
8996 | sizeof(*h->ioaccel2_bft2_regs)); | |
8997 | for (i = 0; i < ARRAY_SIZE(bft2); i++) | |
8998 | writel(bft2[i], &h->ioaccel2_bft2_regs[i]); | |
e1f7de0c | 8999 | } |
b9af4937 | 9000 | writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL); |
c706a795 RE |
9001 | if (hpsa_wait_for_mode_change_ack(h)) { |
9002 | dev_err(&h->pdev->dev, | |
9003 | "performant mode problem - enabling ioaccel mode\n"); | |
9004 | return -ENODEV; | |
9005 | } | |
9006 | return 0; | |
e1f7de0c MG |
9007 | } |
9008 | ||
1fb7c98a RE |
9009 | /* Free ioaccel1 mode command blocks and block fetch table */ |
9010 | static void hpsa_free_ioaccel1_cmd_and_bft(struct ctlr_info *h) | |
9011 | { | |
105a3dbc | 9012 | if (h->ioaccel_cmd_pool) { |
1fb7c98a RE |
9013 | pci_free_consistent(h->pdev, |
9014 | h->nr_cmds * sizeof(*h->ioaccel_cmd_pool), | |
9015 | h->ioaccel_cmd_pool, | |
9016 | h->ioaccel_cmd_pool_dhandle); | |
105a3dbc RE |
9017 | h->ioaccel_cmd_pool = NULL; |
9018 | h->ioaccel_cmd_pool_dhandle = 0; | |
9019 | } | |
1fb7c98a | 9020 | kfree(h->ioaccel1_blockFetchTable); |
105a3dbc | 9021 | h->ioaccel1_blockFetchTable = NULL; |
1fb7c98a RE |
9022 | } |
9023 | ||
d37ffbe4 RE |
9024 | /* Allocate ioaccel1 mode command blocks and block fetch table */ |
9025 | static int hpsa_alloc_ioaccel1_cmd_and_bft(struct ctlr_info *h) | |
e1f7de0c | 9026 | { |
283b4a9b SC |
9027 | h->ioaccel_maxsg = |
9028 | readl(&(h->cfgtable->io_accel_max_embedded_sg_count)); | |
9029 | if (h->ioaccel_maxsg > IOACCEL1_MAXSGENTRIES) | |
9030 | h->ioaccel_maxsg = IOACCEL1_MAXSGENTRIES; | |
9031 | ||
e1f7de0c MG |
9032 | /* Command structures must be aligned on a 128-byte boundary |
9033 | * because the 7 lower bits of the address are used by the | |
9034 | * hardware. | |
9035 | */ | |
e1f7de0c MG |
9036 | BUILD_BUG_ON(sizeof(struct io_accel1_cmd) % |
9037 | IOACCEL1_COMMANDLIST_ALIGNMENT); | |
9038 | h->ioaccel_cmd_pool = | |
9039 | pci_alloc_consistent(h->pdev, | |
9040 | h->nr_cmds * sizeof(*h->ioaccel_cmd_pool), | |
9041 | &(h->ioaccel_cmd_pool_dhandle)); | |
9042 | ||
9043 | h->ioaccel1_blockFetchTable = | |
283b4a9b | 9044 | kmalloc(((h->ioaccel_maxsg + 1) * |
e1f7de0c MG |
9045 | sizeof(u32)), GFP_KERNEL); |
9046 | ||
9047 | if ((h->ioaccel_cmd_pool == NULL) || | |
9048 | (h->ioaccel1_blockFetchTable == NULL)) | |
9049 | goto clean_up; | |
9050 | ||
9051 | memset(h->ioaccel_cmd_pool, 0, | |
9052 | h->nr_cmds * sizeof(*h->ioaccel_cmd_pool)); | |
9053 | return 0; | |
9054 | ||
9055 | clean_up: | |
1fb7c98a | 9056 | hpsa_free_ioaccel1_cmd_and_bft(h); |
2dd02d74 | 9057 | return -ENOMEM; |
6c311b57 SC |
9058 | } |
9059 | ||
1fb7c98a RE |
9060 | /* Free ioaccel2 mode command blocks and block fetch table */ |
9061 | static void hpsa_free_ioaccel2_cmd_and_bft(struct ctlr_info *h) | |
9062 | { | |
d9a729f3 WS |
9063 | hpsa_free_ioaccel2_sg_chain_blocks(h); |
9064 | ||
105a3dbc | 9065 | if (h->ioaccel2_cmd_pool) { |
1fb7c98a RE |
9066 | pci_free_consistent(h->pdev, |
9067 | h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool), | |
9068 | h->ioaccel2_cmd_pool, | |
9069 | h->ioaccel2_cmd_pool_dhandle); | |
105a3dbc RE |
9070 | h->ioaccel2_cmd_pool = NULL; |
9071 | h->ioaccel2_cmd_pool_dhandle = 0; | |
9072 | } | |
1fb7c98a | 9073 | kfree(h->ioaccel2_blockFetchTable); |
105a3dbc | 9074 | h->ioaccel2_blockFetchTable = NULL; |
1fb7c98a RE |
9075 | } |
9076 | ||
d37ffbe4 RE |
9077 | /* Allocate ioaccel2 mode command blocks and block fetch table */ |
9078 | static int hpsa_alloc_ioaccel2_cmd_and_bft(struct ctlr_info *h) | |
aca9012a | 9079 | { |
d9a729f3 WS |
9080 | int rc; |
9081 | ||
aca9012a SC |
9082 | /* Allocate ioaccel2 mode command blocks and block fetch table */ |
9083 | ||
9084 | h->ioaccel_maxsg = | |
9085 | readl(&(h->cfgtable->io_accel_max_embedded_sg_count)); | |
9086 | if (h->ioaccel_maxsg > IOACCEL2_MAXSGENTRIES) | |
9087 | h->ioaccel_maxsg = IOACCEL2_MAXSGENTRIES; | |
9088 | ||
aca9012a SC |
9089 | BUILD_BUG_ON(sizeof(struct io_accel2_cmd) % |
9090 | IOACCEL2_COMMANDLIST_ALIGNMENT); | |
9091 | h->ioaccel2_cmd_pool = | |
9092 | pci_alloc_consistent(h->pdev, | |
9093 | h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool), | |
9094 | &(h->ioaccel2_cmd_pool_dhandle)); | |
9095 | ||
9096 | h->ioaccel2_blockFetchTable = | |
9097 | kmalloc(((h->ioaccel_maxsg + 1) * | |
9098 | sizeof(u32)), GFP_KERNEL); | |
9099 | ||
9100 | if ((h->ioaccel2_cmd_pool == NULL) || | |
d9a729f3 WS |
9101 | (h->ioaccel2_blockFetchTable == NULL)) { |
9102 | rc = -ENOMEM; | |
9103 | goto clean_up; | |
9104 | } | |
9105 | ||
9106 | rc = hpsa_allocate_ioaccel2_sg_chain_blocks(h); | |
9107 | if (rc) | |
aca9012a SC |
9108 | goto clean_up; |
9109 | ||
9110 | memset(h->ioaccel2_cmd_pool, 0, | |
9111 | h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool)); | |
9112 | return 0; | |
9113 | ||
9114 | clean_up: | |
1fb7c98a | 9115 | hpsa_free_ioaccel2_cmd_and_bft(h); |
d9a729f3 | 9116 | return rc; |
aca9012a SC |
9117 | } |
9118 | ||
105a3dbc RE |
9119 | /* Free items allocated by hpsa_put_ctlr_into_performant_mode */ |
9120 | static void hpsa_free_performant_mode(struct ctlr_info *h) | |
9121 | { | |
9122 | kfree(h->blockFetchTable); | |
9123 | h->blockFetchTable = NULL; | |
9124 | hpsa_free_reply_queues(h); | |
9125 | hpsa_free_ioaccel1_cmd_and_bft(h); | |
9126 | hpsa_free_ioaccel2_cmd_and_bft(h); | |
9127 | } | |
9128 | ||
9129 | /* return -ENODEV on error, 0 on success (or no action) | |
9130 | * allocates numerous items that must be freed later | |
9131 | */ | |
9132 | static int hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h) | |
6c311b57 SC |
9133 | { |
9134 | u32 trans_support; | |
e1f7de0c MG |
9135 | unsigned long transMethod = CFGTBL_Trans_Performant | |
9136 | CFGTBL_Trans_use_short_tags; | |
105a3dbc | 9137 | int i, rc; |
6c311b57 | 9138 | |
02ec19c8 | 9139 | if (hpsa_simple_mode) |
105a3dbc | 9140 | return 0; |
02ec19c8 | 9141 | |
67c99a72 | 9142 | trans_support = readl(&(h->cfgtable->TransportSupport)); |
9143 | if (!(trans_support & PERFORMANT_MODE)) | |
105a3dbc | 9144 | return 0; |
67c99a72 | 9145 | |
e1f7de0c MG |
9146 | /* Check for I/O accelerator mode support */ |
9147 | if (trans_support & CFGTBL_Trans_io_accel1) { | |
9148 | transMethod |= CFGTBL_Trans_io_accel1 | | |
9149 | CFGTBL_Trans_enable_directed_msix; | |
105a3dbc RE |
9150 | rc = hpsa_alloc_ioaccel1_cmd_and_bft(h); |
9151 | if (rc) | |
9152 | return rc; | |
9153 | } else if (trans_support & CFGTBL_Trans_io_accel2) { | |
9154 | transMethod |= CFGTBL_Trans_io_accel2 | | |
aca9012a | 9155 | CFGTBL_Trans_enable_directed_msix; |
105a3dbc RE |
9156 | rc = hpsa_alloc_ioaccel2_cmd_and_bft(h); |
9157 | if (rc) | |
9158 | return rc; | |
e1f7de0c MG |
9159 | } |
9160 | ||
eee0f03a | 9161 | h->nreply_queues = h->msix_vector > 0 ? h->msix_vector : 1; |
cba3d38b | 9162 | hpsa_get_max_perf_mode_cmds(h); |
6c311b57 | 9163 | /* Performant mode ring buffer and supporting data structures */ |
072b0518 | 9164 | h->reply_queue_size = h->max_commands * sizeof(u64); |
6c311b57 | 9165 | |
254f796b | 9166 | for (i = 0; i < h->nreply_queues; i++) { |
072b0518 SC |
9167 | h->reply_queue[i].head = pci_alloc_consistent(h->pdev, |
9168 | h->reply_queue_size, | |
9169 | &(h->reply_queue[i].busaddr)); | |
105a3dbc RE |
9170 | if (!h->reply_queue[i].head) { |
9171 | rc = -ENOMEM; | |
9172 | goto clean1; /* rq, ioaccel */ | |
9173 | } | |
254f796b MG |
9174 | h->reply_queue[i].size = h->max_commands; |
9175 | h->reply_queue[i].wraparound = 1; /* spec: init to 1 */ | |
9176 | h->reply_queue[i].current_entry = 0; | |
9177 | } | |
9178 | ||
6c311b57 | 9179 | /* Need a block fetch table for performant mode */ |
d66ae08b | 9180 | h->blockFetchTable = kmalloc(((SG_ENTRIES_IN_CMD + 1) * |
6c311b57 | 9181 | sizeof(u32)), GFP_KERNEL); |
105a3dbc RE |
9182 | if (!h->blockFetchTable) { |
9183 | rc = -ENOMEM; | |
9184 | goto clean1; /* rq, ioaccel */ | |
9185 | } | |
6c311b57 | 9186 | |
105a3dbc RE |
9187 | rc = hpsa_enter_performant_mode(h, trans_support); |
9188 | if (rc) | |
9189 | goto clean2; /* bft, rq, ioaccel */ | |
9190 | return 0; | |
303932fd | 9191 | |
105a3dbc | 9192 | clean2: /* bft, rq, ioaccel */ |
303932fd | 9193 | kfree(h->blockFetchTable); |
105a3dbc RE |
9194 | h->blockFetchTable = NULL; |
9195 | clean1: /* rq, ioaccel */ | |
9196 | hpsa_free_reply_queues(h); | |
9197 | hpsa_free_ioaccel1_cmd_and_bft(h); | |
9198 | hpsa_free_ioaccel2_cmd_and_bft(h); | |
9199 | return rc; | |
303932fd DB |
9200 | } |
9201 | ||
23100dd9 | 9202 | static int is_accelerated_cmd(struct CommandList *c) |
76438d08 | 9203 | { |
23100dd9 SC |
9204 | return c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_IOACCEL2; |
9205 | } | |
9206 | ||
9207 | static void hpsa_drain_accel_commands(struct ctlr_info *h) | |
9208 | { | |
9209 | struct CommandList *c = NULL; | |
f2405db8 | 9210 | int i, accel_cmds_out; |
281a7fd0 | 9211 | int refcount; |
76438d08 | 9212 | |
f2405db8 | 9213 | do { /* wait for all outstanding ioaccel commands to drain out */ |
23100dd9 | 9214 | accel_cmds_out = 0; |
f2405db8 | 9215 | for (i = 0; i < h->nr_cmds; i++) { |
f2405db8 | 9216 | c = h->cmd_pool + i; |
281a7fd0 WS |
9217 | refcount = atomic_inc_return(&c->refcount); |
9218 | if (refcount > 1) /* Command is allocated */ | |
9219 | accel_cmds_out += is_accelerated_cmd(c); | |
9220 | cmd_free(h, c); | |
f2405db8 | 9221 | } |
23100dd9 | 9222 | if (accel_cmds_out <= 0) |
281a7fd0 | 9223 | break; |
76438d08 SC |
9224 | msleep(100); |
9225 | } while (1); | |
9226 | } | |
9227 | ||
d04e62b9 KB |
9228 | static struct hpsa_sas_phy *hpsa_alloc_sas_phy( |
9229 | struct hpsa_sas_port *hpsa_sas_port) | |
9230 | { | |
9231 | struct hpsa_sas_phy *hpsa_sas_phy; | |
9232 | struct sas_phy *phy; | |
9233 | ||
9234 | hpsa_sas_phy = kzalloc(sizeof(*hpsa_sas_phy), GFP_KERNEL); | |
9235 | if (!hpsa_sas_phy) | |
9236 | return NULL; | |
9237 | ||
9238 | phy = sas_phy_alloc(hpsa_sas_port->parent_node->parent_dev, | |
9239 | hpsa_sas_port->next_phy_index); | |
9240 | if (!phy) { | |
9241 | kfree(hpsa_sas_phy); | |
9242 | return NULL; | |
9243 | } | |
9244 | ||
9245 | hpsa_sas_port->next_phy_index++; | |
9246 | hpsa_sas_phy->phy = phy; | |
9247 | hpsa_sas_phy->parent_port = hpsa_sas_port; | |
9248 | ||
9249 | return hpsa_sas_phy; | |
9250 | } | |
9251 | ||
9252 | static void hpsa_free_sas_phy(struct hpsa_sas_phy *hpsa_sas_phy) | |
9253 | { | |
9254 | struct sas_phy *phy = hpsa_sas_phy->phy; | |
9255 | ||
9256 | sas_port_delete_phy(hpsa_sas_phy->parent_port->port, phy); | |
9257 | sas_phy_free(phy); | |
9258 | if (hpsa_sas_phy->added_to_port) | |
9259 | list_del(&hpsa_sas_phy->phy_list_entry); | |
9260 | kfree(hpsa_sas_phy); | |
9261 | } | |
9262 | ||
9263 | static int hpsa_sas_port_add_phy(struct hpsa_sas_phy *hpsa_sas_phy) | |
9264 | { | |
9265 | int rc; | |
9266 | struct hpsa_sas_port *hpsa_sas_port; | |
9267 | struct sas_phy *phy; | |
9268 | struct sas_identify *identify; | |
9269 | ||
9270 | hpsa_sas_port = hpsa_sas_phy->parent_port; | |
9271 | phy = hpsa_sas_phy->phy; | |
9272 | ||
9273 | identify = &phy->identify; | |
9274 | memset(identify, 0, sizeof(*identify)); | |
9275 | identify->sas_address = hpsa_sas_port->sas_address; | |
9276 | identify->device_type = SAS_END_DEVICE; | |
9277 | identify->initiator_port_protocols = SAS_PROTOCOL_STP; | |
9278 | identify->target_port_protocols = SAS_PROTOCOL_STP; | |
9279 | phy->minimum_linkrate_hw = SAS_LINK_RATE_UNKNOWN; | |
9280 | phy->maximum_linkrate_hw = SAS_LINK_RATE_UNKNOWN; | |
9281 | phy->minimum_linkrate = SAS_LINK_RATE_UNKNOWN; | |
9282 | phy->maximum_linkrate = SAS_LINK_RATE_UNKNOWN; | |
9283 | phy->negotiated_linkrate = SAS_LINK_RATE_UNKNOWN; | |
9284 | ||
9285 | rc = sas_phy_add(hpsa_sas_phy->phy); | |
9286 | if (rc) | |
9287 | return rc; | |
9288 | ||
9289 | sas_port_add_phy(hpsa_sas_port->port, hpsa_sas_phy->phy); | |
9290 | list_add_tail(&hpsa_sas_phy->phy_list_entry, | |
9291 | &hpsa_sas_port->phy_list_head); | |
9292 | hpsa_sas_phy->added_to_port = true; | |
9293 | ||
9294 | return 0; | |
9295 | } | |
9296 | ||
9297 | static int | |
9298 | hpsa_sas_port_add_rphy(struct hpsa_sas_port *hpsa_sas_port, | |
9299 | struct sas_rphy *rphy) | |
9300 | { | |
9301 | struct sas_identify *identify; | |
9302 | ||
9303 | identify = &rphy->identify; | |
9304 | identify->sas_address = hpsa_sas_port->sas_address; | |
9305 | identify->initiator_port_protocols = SAS_PROTOCOL_STP; | |
9306 | identify->target_port_protocols = SAS_PROTOCOL_STP; | |
9307 | ||
9308 | return sas_rphy_add(rphy); | |
9309 | } | |
9310 | ||
9311 | static struct hpsa_sas_port | |
9312 | *hpsa_alloc_sas_port(struct hpsa_sas_node *hpsa_sas_node, | |
9313 | u64 sas_address) | |
9314 | { | |
9315 | int rc; | |
9316 | struct hpsa_sas_port *hpsa_sas_port; | |
9317 | struct sas_port *port; | |
9318 | ||
9319 | hpsa_sas_port = kzalloc(sizeof(*hpsa_sas_port), GFP_KERNEL); | |
9320 | if (!hpsa_sas_port) | |
9321 | return NULL; | |
9322 | ||
9323 | INIT_LIST_HEAD(&hpsa_sas_port->phy_list_head); | |
9324 | hpsa_sas_port->parent_node = hpsa_sas_node; | |
9325 | ||
9326 | port = sas_port_alloc_num(hpsa_sas_node->parent_dev); | |
9327 | if (!port) | |
9328 | goto free_hpsa_port; | |
9329 | ||
9330 | rc = sas_port_add(port); | |
9331 | if (rc) | |
9332 | goto free_sas_port; | |
9333 | ||
9334 | hpsa_sas_port->port = port; | |
9335 | hpsa_sas_port->sas_address = sas_address; | |
9336 | list_add_tail(&hpsa_sas_port->port_list_entry, | |
9337 | &hpsa_sas_node->port_list_head); | |
9338 | ||
9339 | return hpsa_sas_port; | |
9340 | ||
9341 | free_sas_port: | |
9342 | sas_port_free(port); | |
9343 | free_hpsa_port: | |
9344 | kfree(hpsa_sas_port); | |
9345 | ||
9346 | return NULL; | |
9347 | } | |
9348 | ||
9349 | static void hpsa_free_sas_port(struct hpsa_sas_port *hpsa_sas_port) | |
9350 | { | |
9351 | struct hpsa_sas_phy *hpsa_sas_phy; | |
9352 | struct hpsa_sas_phy *next; | |
9353 | ||
9354 | list_for_each_entry_safe(hpsa_sas_phy, next, | |
9355 | &hpsa_sas_port->phy_list_head, phy_list_entry) | |
9356 | hpsa_free_sas_phy(hpsa_sas_phy); | |
9357 | ||
9358 | sas_port_delete(hpsa_sas_port->port); | |
9359 | list_del(&hpsa_sas_port->port_list_entry); | |
9360 | kfree(hpsa_sas_port); | |
9361 | } | |
9362 | ||
9363 | static struct hpsa_sas_node *hpsa_alloc_sas_node(struct device *parent_dev) | |
9364 | { | |
9365 | struct hpsa_sas_node *hpsa_sas_node; | |
9366 | ||
9367 | hpsa_sas_node = kzalloc(sizeof(*hpsa_sas_node), GFP_KERNEL); | |
9368 | if (hpsa_sas_node) { | |
9369 | hpsa_sas_node->parent_dev = parent_dev; | |
9370 | INIT_LIST_HEAD(&hpsa_sas_node->port_list_head); | |
9371 | } | |
9372 | ||
9373 | return hpsa_sas_node; | |
9374 | } | |
9375 | ||
9376 | static void hpsa_free_sas_node(struct hpsa_sas_node *hpsa_sas_node) | |
9377 | { | |
9378 | struct hpsa_sas_port *hpsa_sas_port; | |
9379 | struct hpsa_sas_port *next; | |
9380 | ||
9381 | if (!hpsa_sas_node) | |
9382 | return; | |
9383 | ||
9384 | list_for_each_entry_safe(hpsa_sas_port, next, | |
9385 | &hpsa_sas_node->port_list_head, port_list_entry) | |
9386 | hpsa_free_sas_port(hpsa_sas_port); | |
9387 | ||
9388 | kfree(hpsa_sas_node); | |
9389 | } | |
9390 | ||
9391 | static struct hpsa_scsi_dev_t | |
9392 | *hpsa_find_device_by_sas_rphy(struct ctlr_info *h, | |
9393 | struct sas_rphy *rphy) | |
9394 | { | |
9395 | int i; | |
9396 | struct hpsa_scsi_dev_t *device; | |
9397 | ||
9398 | for (i = 0; i < h->ndevices; i++) { | |
9399 | device = h->dev[i]; | |
9400 | if (!device->sas_port) | |
9401 | continue; | |
9402 | if (device->sas_port->rphy == rphy) | |
9403 | return device; | |
9404 | } | |
9405 | ||
9406 | return NULL; | |
9407 | } | |
9408 | ||
9409 | static int hpsa_add_sas_host(struct ctlr_info *h) | |
9410 | { | |
9411 | int rc; | |
9412 | struct device *parent_dev; | |
9413 | struct hpsa_sas_node *hpsa_sas_node; | |
9414 | struct hpsa_sas_port *hpsa_sas_port; | |
9415 | struct hpsa_sas_phy *hpsa_sas_phy; | |
9416 | ||
9417 | parent_dev = &h->scsi_host->shost_gendev; | |
9418 | ||
9419 | hpsa_sas_node = hpsa_alloc_sas_node(parent_dev); | |
9420 | if (!hpsa_sas_node) | |
9421 | return -ENOMEM; | |
9422 | ||
9423 | hpsa_sas_port = hpsa_alloc_sas_port(hpsa_sas_node, h->sas_address); | |
9424 | if (!hpsa_sas_port) { | |
9425 | rc = -ENODEV; | |
9426 | goto free_sas_node; | |
9427 | } | |
9428 | ||
9429 | hpsa_sas_phy = hpsa_alloc_sas_phy(hpsa_sas_port); | |
9430 | if (!hpsa_sas_phy) { | |
9431 | rc = -ENODEV; | |
9432 | goto free_sas_port; | |
9433 | } | |
9434 | ||
9435 | rc = hpsa_sas_port_add_phy(hpsa_sas_phy); | |
9436 | if (rc) | |
9437 | goto free_sas_phy; | |
9438 | ||
9439 | h->sas_host = hpsa_sas_node; | |
9440 | ||
9441 | return 0; | |
9442 | ||
9443 | free_sas_phy: | |
9444 | hpsa_free_sas_phy(hpsa_sas_phy); | |
9445 | free_sas_port: | |
9446 | hpsa_free_sas_port(hpsa_sas_port); | |
9447 | free_sas_node: | |
9448 | hpsa_free_sas_node(hpsa_sas_node); | |
9449 | ||
9450 | return rc; | |
9451 | } | |
9452 | ||
9453 | static void hpsa_delete_sas_host(struct ctlr_info *h) | |
9454 | { | |
9455 | hpsa_free_sas_node(h->sas_host); | |
9456 | } | |
9457 | ||
9458 | static int hpsa_add_sas_device(struct hpsa_sas_node *hpsa_sas_node, | |
9459 | struct hpsa_scsi_dev_t *device) | |
9460 | { | |
9461 | int rc; | |
9462 | struct hpsa_sas_port *hpsa_sas_port; | |
9463 | struct sas_rphy *rphy; | |
9464 | ||
9465 | hpsa_sas_port = hpsa_alloc_sas_port(hpsa_sas_node, device->sas_address); | |
9466 | if (!hpsa_sas_port) | |
9467 | return -ENOMEM; | |
9468 | ||
9469 | rphy = sas_end_device_alloc(hpsa_sas_port->port); | |
9470 | if (!rphy) { | |
9471 | rc = -ENODEV; | |
9472 | goto free_sas_port; | |
9473 | } | |
9474 | ||
9475 | hpsa_sas_port->rphy = rphy; | |
9476 | device->sas_port = hpsa_sas_port; | |
9477 | ||
9478 | rc = hpsa_sas_port_add_rphy(hpsa_sas_port, rphy); | |
9479 | if (rc) | |
9480 | goto free_sas_port; | |
9481 | ||
9482 | return 0; | |
9483 | ||
9484 | free_sas_port: | |
9485 | hpsa_free_sas_port(hpsa_sas_port); | |
9486 | device->sas_port = NULL; | |
9487 | ||
9488 | return rc; | |
9489 | } | |
9490 | ||
9491 | static void hpsa_remove_sas_device(struct hpsa_scsi_dev_t *device) | |
9492 | { | |
9493 | if (device->sas_port) { | |
9494 | hpsa_free_sas_port(device->sas_port); | |
9495 | device->sas_port = NULL; | |
9496 | } | |
9497 | } | |
9498 | ||
9499 | static int | |
9500 | hpsa_sas_get_linkerrors(struct sas_phy *phy) | |
9501 | { | |
9502 | return 0; | |
9503 | } | |
9504 | ||
9505 | static int | |
9506 | hpsa_sas_get_enclosure_identifier(struct sas_rphy *rphy, u64 *identifier) | |
9507 | { | |
9508 | return 0; | |
9509 | } | |
9510 | ||
9511 | static int | |
9512 | hpsa_sas_get_bay_identifier(struct sas_rphy *rphy) | |
9513 | { | |
9514 | return -ENXIO; | |
9515 | } | |
9516 | ||
9517 | static int | |
9518 | hpsa_sas_phy_reset(struct sas_phy *phy, int hard_reset) | |
9519 | { | |
9520 | return 0; | |
9521 | } | |
9522 | ||
9523 | static int | |
9524 | hpsa_sas_phy_enable(struct sas_phy *phy, int enable) | |
9525 | { | |
9526 | return 0; | |
9527 | } | |
9528 | ||
9529 | static int | |
9530 | hpsa_sas_phy_setup(struct sas_phy *phy) | |
9531 | { | |
9532 | return 0; | |
9533 | } | |
9534 | ||
9535 | static void | |
9536 | hpsa_sas_phy_release(struct sas_phy *phy) | |
9537 | { | |
9538 | } | |
9539 | ||
9540 | static int | |
9541 | hpsa_sas_phy_speed(struct sas_phy *phy, struct sas_phy_linkrates *rates) | |
9542 | { | |
9543 | return -EINVAL; | |
9544 | } | |
9545 | ||
9546 | /* SMP = Serial Management Protocol */ | |
9547 | static int | |
9548 | hpsa_sas_smp_handler(struct Scsi_Host *shost, struct sas_rphy *rphy, | |
9549 | struct request *req) | |
9550 | { | |
9551 | return -EINVAL; | |
9552 | } | |
9553 | ||
9554 | static struct sas_function_template hpsa_sas_transport_functions = { | |
9555 | .get_linkerrors = hpsa_sas_get_linkerrors, | |
9556 | .get_enclosure_identifier = hpsa_sas_get_enclosure_identifier, | |
9557 | .get_bay_identifier = hpsa_sas_get_bay_identifier, | |
9558 | .phy_reset = hpsa_sas_phy_reset, | |
9559 | .phy_enable = hpsa_sas_phy_enable, | |
9560 | .phy_setup = hpsa_sas_phy_setup, | |
9561 | .phy_release = hpsa_sas_phy_release, | |
9562 | .set_phy_speed = hpsa_sas_phy_speed, | |
9563 | .smp_handler = hpsa_sas_smp_handler, | |
9564 | }; | |
9565 | ||
edd16368 SC |
9566 | /* |
9567 | * This is it. Register the PCI driver information for the cards we control | |
9568 | * the OS will call our registered routines when it finds one of our cards. | |
9569 | */ | |
9570 | static int __init hpsa_init(void) | |
9571 | { | |
d04e62b9 KB |
9572 | int rc; |
9573 | ||
9574 | hpsa_sas_transport_template = | |
9575 | sas_attach_transport(&hpsa_sas_transport_functions); | |
9576 | if (!hpsa_sas_transport_template) | |
9577 | return -ENODEV; | |
9578 | ||
9579 | rc = pci_register_driver(&hpsa_pci_driver); | |
9580 | ||
9581 | if (rc) | |
9582 | sas_release_transport(hpsa_sas_transport_template); | |
9583 | ||
9584 | return rc; | |
edd16368 SC |
9585 | } |
9586 | ||
9587 | static void __exit hpsa_cleanup(void) | |
9588 | { | |
9589 | pci_unregister_driver(&hpsa_pci_driver); | |
d04e62b9 | 9590 | sas_release_transport(hpsa_sas_transport_template); |
edd16368 SC |
9591 | } |
9592 | ||
e1f7de0c MG |
9593 | static void __attribute__((unused)) verify_offsets(void) |
9594 | { | |
dd0e19f3 ST |
9595 | #define VERIFY_OFFSET(member, offset) \ |
9596 | BUILD_BUG_ON(offsetof(struct raid_map_data, member) != offset) | |
9597 | ||
9598 | VERIFY_OFFSET(structure_size, 0); | |
9599 | VERIFY_OFFSET(volume_blk_size, 4); | |
9600 | VERIFY_OFFSET(volume_blk_cnt, 8); | |
9601 | VERIFY_OFFSET(phys_blk_shift, 16); | |
9602 | VERIFY_OFFSET(parity_rotation_shift, 17); | |
9603 | VERIFY_OFFSET(strip_size, 18); | |
9604 | VERIFY_OFFSET(disk_starting_blk, 20); | |
9605 | VERIFY_OFFSET(disk_blk_cnt, 28); | |
9606 | VERIFY_OFFSET(data_disks_per_row, 36); | |
9607 | VERIFY_OFFSET(metadata_disks_per_row, 38); | |
9608 | VERIFY_OFFSET(row_cnt, 40); | |
9609 | VERIFY_OFFSET(layout_map_count, 42); | |
9610 | VERIFY_OFFSET(flags, 44); | |
9611 | VERIFY_OFFSET(dekindex, 46); | |
9612 | /* VERIFY_OFFSET(reserved, 48 */ | |
9613 | VERIFY_OFFSET(data, 64); | |
9614 | ||
9615 | #undef VERIFY_OFFSET | |
9616 | ||
b66cc250 MM |
9617 | #define VERIFY_OFFSET(member, offset) \ |
9618 | BUILD_BUG_ON(offsetof(struct io_accel2_cmd, member) != offset) | |
9619 | ||
9620 | VERIFY_OFFSET(IU_type, 0); | |
9621 | VERIFY_OFFSET(direction, 1); | |
9622 | VERIFY_OFFSET(reply_queue, 2); | |
9623 | /* VERIFY_OFFSET(reserved1, 3); */ | |
9624 | VERIFY_OFFSET(scsi_nexus, 4); | |
9625 | VERIFY_OFFSET(Tag, 8); | |
9626 | VERIFY_OFFSET(cdb, 16); | |
9627 | VERIFY_OFFSET(cciss_lun, 32); | |
9628 | VERIFY_OFFSET(data_len, 40); | |
9629 | VERIFY_OFFSET(cmd_priority_task_attr, 44); | |
9630 | VERIFY_OFFSET(sg_count, 45); | |
9631 | /* VERIFY_OFFSET(reserved3 */ | |
9632 | VERIFY_OFFSET(err_ptr, 48); | |
9633 | VERIFY_OFFSET(err_len, 56); | |
9634 | /* VERIFY_OFFSET(reserved4 */ | |
9635 | VERIFY_OFFSET(sg, 64); | |
9636 | ||
9637 | #undef VERIFY_OFFSET | |
9638 | ||
e1f7de0c MG |
9639 | #define VERIFY_OFFSET(member, offset) \ |
9640 | BUILD_BUG_ON(offsetof(struct io_accel1_cmd, member) != offset) | |
9641 | ||
9642 | VERIFY_OFFSET(dev_handle, 0x00); | |
9643 | VERIFY_OFFSET(reserved1, 0x02); | |
9644 | VERIFY_OFFSET(function, 0x03); | |
9645 | VERIFY_OFFSET(reserved2, 0x04); | |
9646 | VERIFY_OFFSET(err_info, 0x0C); | |
9647 | VERIFY_OFFSET(reserved3, 0x10); | |
9648 | VERIFY_OFFSET(err_info_len, 0x12); | |
9649 | VERIFY_OFFSET(reserved4, 0x13); | |
9650 | VERIFY_OFFSET(sgl_offset, 0x14); | |
9651 | VERIFY_OFFSET(reserved5, 0x15); | |
9652 | VERIFY_OFFSET(transfer_len, 0x1C); | |
9653 | VERIFY_OFFSET(reserved6, 0x20); | |
9654 | VERIFY_OFFSET(io_flags, 0x24); | |
9655 | VERIFY_OFFSET(reserved7, 0x26); | |
9656 | VERIFY_OFFSET(LUN, 0x34); | |
9657 | VERIFY_OFFSET(control, 0x3C); | |
9658 | VERIFY_OFFSET(CDB, 0x40); | |
9659 | VERIFY_OFFSET(reserved8, 0x50); | |
9660 | VERIFY_OFFSET(host_context_flags, 0x60); | |
9661 | VERIFY_OFFSET(timeout_sec, 0x62); | |
9662 | VERIFY_OFFSET(ReplyQueue, 0x64); | |
9663 | VERIFY_OFFSET(reserved9, 0x65); | |
50a0decf | 9664 | VERIFY_OFFSET(tag, 0x68); |
e1f7de0c MG |
9665 | VERIFY_OFFSET(host_addr, 0x70); |
9666 | VERIFY_OFFSET(CISS_LUN, 0x78); | |
9667 | VERIFY_OFFSET(SG, 0x78 + 8); | |
9668 | #undef VERIFY_OFFSET | |
9669 | } | |
9670 | ||
edd16368 SC |
9671 | module_init(hpsa_init); |
9672 | module_exit(hpsa_cleanup); |