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hpsa: use workqueue to resubmit failed ioaccel commands
[deliverable/linux.git] / drivers / scsi / hpsa.c
CommitLineData
edd16368
SC		 1/*
2 * Disk Array driver for HP Smart Array SAS controllers
51c35139 3 * Copyright 2000, 2014 Hewlett-Packard Development Company, L.P.
edd16368
SC		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
12 * NON INFRINGEMENT. See the GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 *
18 * Questions/Comments/Bugfixes to iss_storagedev@hp.com
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/interrupt.h>
24#include <linux/types.h>
25#include <linux/pci.h>
e5a44df8 26#include <linux/pci-aspm.h>
edd16368
SC		 27#include <linux/kernel.h>
28#include <linux/slab.h>
29#include <linux/delay.h>
30#include <linux/fs.h>
31#include <linux/timer.h>
edd16368
SC		 32#include <linux/init.h>
33#include <linux/spinlock.h>
edd16368
SC		 34#include <linux/compat.h>
35#include <linux/blktrace_api.h>
36#include <linux/uaccess.h>
37#include <linux/io.h>
38#include <linux/dma-mapping.h>
39#include <linux/completion.h>
40#include <linux/moduleparam.h>
41#include <scsi/scsi.h>
42#include <scsi/scsi_cmnd.h>
43#include <scsi/scsi_device.h>
44#include <scsi/scsi_host.h>
667e23d4 45#include <scsi/scsi_tcq.h>
edd16368
SC		 46#include <linux/cciss_ioctl.h>
47#include <linux/string.h>
48#include <linux/bitmap.h>
60063497 49#include <linux/atomic.h>
a0c12413 50#include <linux/jiffies.h>
42a91641 51#include <linux/percpu-defs.h>
094963da 52#include <linux/percpu.h>
2b08b3e9 53#include <asm/unaligned.h>
283b4a9b 54#include <asm/div64.h>
edd16368
SC		 55#include "hpsa_cmd.h"
56#include "hpsa.h"
57
58/* HPSA_DRIVER_VERSION must be 3 byte values (0-255) separated by '.' */
9a993302 59#define HPSA_DRIVER_VERSION "3.4.4-1"
edd16368 60#define DRIVER_NAME "HP HPSA Driver (v " HPSA_DRIVER_VERSION ")"
f79cfec6 61#define HPSA "hpsa"
edd16368
SC		 62
63/* How long to wait (in milliseconds) for board to go into simple mode */
64#define MAX_CONFIG_WAIT 30000
65#define MAX_IOCTL_CONFIG_WAIT 1000
66
67/*define how many times we will try a command because of bus resets */
68#define MAX_CMD_RETRIES 3
69
70/* Embedded module documentation macros - see modules.h */
71MODULE_AUTHOR("Hewlett-Packard Company");
72MODULE_DESCRIPTION("Driver for HP Smart Array Controller version " \
73 HPSA_DRIVER_VERSION);
74MODULE_SUPPORTED_DEVICE("HP Smart Array Controllers");
75MODULE_VERSION(HPSA_DRIVER_VERSION);
76MODULE_LICENSE("GPL");
77
78static int hpsa_allow_any;
79module_param(hpsa_allow_any, int, S_IRUGO|S_IWUSR);
80MODULE_PARM_DESC(hpsa_allow_any,
81 "Allow hpsa driver to access unknown HP Smart Array hardware");
02ec19c8
SC		 82static int hpsa_simple_mode;
83module_param(hpsa_simple_mode, int, S_IRUGO|S_IWUSR);
84MODULE_PARM_DESC(hpsa_simple_mode,
85 "Use 'simple mode' rather than 'performant mode'");
edd16368
SC		 86
87/* define the PCI info for the cards we can control */
88static const struct pci_device_id hpsa_pci_device_id[] = {
edd16368
SC		 89 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3241},
90 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3243},
91 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3245},
92 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3247},
93 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3249},
163dbcd8
MM		 94 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324A},
95 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324B},
f8b01eb9 96 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3233},
9143a961 97 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3350},
98 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3351},
99 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3352},
100 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3353},
101 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3354},
102 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3355},
103 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3356},
fe0c9610
MM		 104 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1921},
105 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1922},
106 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1923},
107 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1924},
fe0c9610
MM		 108 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1926},
109 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1928},
97b9f53d
MM		 110 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1929},
111 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BD},
112 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BE},
113 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BF},
114 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C0},
115 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C1},
116 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C2},
117 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C3},
118 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C4},
119 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C5},
3b7a45e5 120 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C6},
97b9f53d
MM		 121 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C7},
122 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C8},
123 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C9},
3b7a45e5
JH		 124 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CA},
125 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CB},
126 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CC},
127 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CD},
128 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CE},
8e616a5e
SC		 129 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0076},
130 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0087},
131 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x007D},
132 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0088},
133 {PCI_VENDOR_ID_HP, 0x333f, 0x103c, 0x333f},
7c03b870 134 {PCI_VENDOR_ID_HP, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
6798cc0a 135 PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0},
edd16368
SC		 136 {0,}
137};
138
139MODULE_DEVICE_TABLE(pci, hpsa_pci_device_id);
140
141/* board_id = Subsystem Device ID & Vendor ID
142 * product = Marketing Name for the board
143 * access = Address of the struct of function pointers
144 */
145static struct board_type products[] = {
edd16368
SC		 146 {0x3241103C, "Smart Array P212", &SA5_access},
147 {0x3243103C, "Smart Array P410", &SA5_access},
148 {0x3245103C, "Smart Array P410i", &SA5_access},
149 {0x3247103C, "Smart Array P411", &SA5_access},
150 {0x3249103C, "Smart Array P812", &SA5_access},
163dbcd8
MM		 151 {0x324A103C, "Smart Array P712m", &SA5_access},
152 {0x324B103C, "Smart Array P711m", &SA5_access},
7d2cce58 153 {0x3233103C, "HP StorageWorks 1210m", &SA5_access}, /* alias of 333f */
fe0c9610
MM		 154 {0x3350103C, "Smart Array P222", &SA5_access},
155 {0x3351103C, "Smart Array P420", &SA5_access},
156 {0x3352103C, "Smart Array P421", &SA5_access},
157 {0x3353103C, "Smart Array P822", &SA5_access},
158 {0x3354103C, "Smart Array P420i", &SA5_access},
159 {0x3355103C, "Smart Array P220i", &SA5_access},
160 {0x3356103C, "Smart Array P721m", &SA5_access},
1fd6c8e3
MM		 161 {0x1921103C, "Smart Array P830i", &SA5_access},
162 {0x1922103C, "Smart Array P430", &SA5_access},
163 {0x1923103C, "Smart Array P431", &SA5_access},
164 {0x1924103C, "Smart Array P830", &SA5_access},
165 {0x1926103C, "Smart Array P731m", &SA5_access},
166 {0x1928103C, "Smart Array P230i", &SA5_access},
167 {0x1929103C, "Smart Array P530", &SA5_access},
97b9f53d
MM		 168 {0x21BD103C, "Smart Array", &SA5_access},
169 {0x21BE103C, "Smart Array", &SA5_access},
170 {0x21BF103C, "Smart Array", &SA5_access},
171 {0x21C0103C, "Smart Array", &SA5_access},
172 {0x21C1103C, "Smart Array", &SA5_access},
173 {0x21C2103C, "Smart Array", &SA5_access},
174 {0x21C3103C, "Smart Array", &SA5_access},
175 {0x21C4103C, "Smart Array", &SA5_access},
176 {0x21C5103C, "Smart Array", &SA5_access},
3b7a45e5 177 {0x21C6103C, "Smart Array", &SA5_access},
97b9f53d
MM		 178 {0x21C7103C, "Smart Array", &SA5_access},
179 {0x21C8103C, "Smart Array", &SA5_access},
180 {0x21C9103C, "Smart Array", &SA5_access},
3b7a45e5
JH		 181 {0x21CA103C, "Smart Array", &SA5_access},
182 {0x21CB103C, "Smart Array", &SA5_access},
183 {0x21CC103C, "Smart Array", &SA5_access},
184 {0x21CD103C, "Smart Array", &SA5_access},
185 {0x21CE103C, "Smart Array", &SA5_access},
8e616a5e
SC		 186 {0x00761590, "HP Storage P1224 Array Controller", &SA5_access},
187 {0x00871590, "HP Storage P1224e Array Controller", &SA5_access},
188 {0x007D1590, "HP Storage P1228 Array Controller", &SA5_access},
189 {0x00881590, "HP Storage P1228e Array Controller", &SA5_access},
190 {0x333f103c, "HP StorageWorks 1210m Array Controller", &SA5_access},
edd16368
SC		 191 {0xFFFF103C, "Unknown Smart Array", &SA5_access},
192};
193
194static int number_of_controllers;
195
10f66018
SC		 196static irqreturn_t do_hpsa_intr_intx(int irq, void *dev_id);
197static irqreturn_t do_hpsa_intr_msi(int irq, void *dev_id);
42a91641 198static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg);
edd16368
SC		 199
200#ifdef CONFIG_COMPAT
42a91641
DB		 201static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd,
202 void __user *arg);
edd16368
SC		 203#endif
204
205static void cmd_free(struct ctlr_info *h, struct CommandList *c);
edd16368 206static struct CommandList *cmd_alloc(struct ctlr_info *h);
a2dac136 207static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
b7bb24eb 208 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
edd16368 209 int cmd_type);
2c143342 210static void hpsa_free_cmd_pool(struct ctlr_info *h);
b7bb24eb 211#define VPD_PAGE (1 << 8)
edd16368 212
f281233d 213static int hpsa_scsi_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd);
a08a8471
SC		 214static void hpsa_scan_start(struct Scsi_Host *);
215static int hpsa_scan_finished(struct Scsi_Host *sh,
216 unsigned long elapsed_time);
7c0a0229 217static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth);
edd16368
SC		 218
219static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd);
75167d2c 220static int hpsa_eh_abort_handler(struct scsi_cmnd *scsicmd);
edd16368
SC		 221static int hpsa_slave_alloc(struct scsi_device *sdev);
222static void hpsa_slave_destroy(struct scsi_device *sdev);
223
edd16368 224static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno);
edd16368
SC		 225static int check_for_unit_attention(struct ctlr_info *h,
226 struct CommandList *c);
227static void check_ioctl_unit_attention(struct ctlr_info *h,
228 struct CommandList *c);
303932fd
DB		 229/* performant mode helper functions */
230static void calc_bucket_map(int *bucket, int num_buckets,
2b08b3e9 231 int nsgs, int min_blocks, u32 *bucket_map);
6f039790 232static void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h);
254f796b 233static inline u32 next_command(struct ctlr_info *h, u8 q);
6f039790
GKH		 234static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
235 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
236 u64 *cfg_offset);
237static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
238 unsigned long *memory_bar);
239static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id);
240static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
241 int wait_for_ready);
75167d2c 242static inline void finish_cmd(struct CommandList *c);
283b4a9b 243static void hpsa_wait_for_mode_change_ack(struct ctlr_info *h);
fe5389c8
SC		 244#define BOARD_NOT_READY 0
245#define BOARD_READY 1
23100dd9 246static void hpsa_drain_accel_commands(struct ctlr_info *h);
76438d08 247static void hpsa_flush_cache(struct ctlr_info *h);
c349775e
ST		 248static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
249 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
250 u8 *scsi3addr);
080ef1cc 251static void hpsa_command_resubmit_worker(struct work_struct *work);
edd16368 252
edd16368
SC		 253static inline struct ctlr_info *sdev_to_hba(struct scsi_device *sdev)
254{
255 unsigned long *priv = shost_priv(sdev->host);
256 return (struct ctlr_info *) *priv;
257}
258
a23513e8
SC		 259static inline struct ctlr_info *shost_to_hba(struct Scsi_Host *sh)
260{
261 unsigned long *priv = shost_priv(sh);
262 return (struct ctlr_info *) *priv;
263}
264
edd16368
SC		 265static int check_for_unit_attention(struct ctlr_info *h,
266 struct CommandList *c)
267{
268 if (c->err_info->SenseInfo[2] != UNIT_ATTENTION)
269 return 0;
270
271 switch (c->err_info->SenseInfo[12]) {
272 case STATE_CHANGED:
f79cfec6 273 dev_warn(&h->pdev->dev, HPSA "%d: a state change "
edd16368
SC		 274 "detected, command retried\n", h->ctlr);
275 break;
276 case LUN_FAILED:
7f73695a
SC		 277 dev_warn(&h->pdev->dev,
278 HPSA "%d: LUN failure detected\n", h->ctlr);
edd16368
SC		 279 break;
280 case REPORT_LUNS_CHANGED:
7f73695a
SC		 281 dev_warn(&h->pdev->dev,
282 HPSA "%d: report LUN data changed\n", h->ctlr);
edd16368 283 /*
4f4eb9f1
ST		 284 * Note: this REPORT_LUNS_CHANGED condition only occurs on the external
285 * target (array) devices.
edd16368
SC		 286 */
287 break;
288 case POWER_OR_RESET:
f79cfec6 289 dev_warn(&h->pdev->dev, HPSA "%d: a power on "
edd16368
SC		 290 "or device reset detected\n", h->ctlr);
291 break;
292 case UNIT_ATTENTION_CLEARED:
f79cfec6 293 dev_warn(&h->pdev->dev, HPSA "%d: unit attention "
edd16368
SC		 294 "cleared by another initiator\n", h->ctlr);
295 break;
296 default:
f79cfec6 297 dev_warn(&h->pdev->dev, HPSA "%d: unknown "
edd16368
SC		 298 "unit attention detected\n", h->ctlr);
299 break;
300 }
301 return 1;
302}
303
852af20a
MB		 304static int check_for_busy(struct ctlr_info *h, struct CommandList *c)
305{
306 if (c->err_info->CommandStatus != CMD_TARGET_STATUS ||
307 (c->err_info->ScsiStatus != SAM_STAT_BUSY &&
308 c->err_info->ScsiStatus != SAM_STAT_TASK_SET_FULL))
309 return 0;
310 dev_warn(&h->pdev->dev, HPSA "device busy");
311 return 1;
312}
313
da0697bd
ST		 314static ssize_t host_store_hp_ssd_smart_path_status(struct device *dev,
315 struct device_attribute *attr,
316 const char *buf, size_t count)
317{
318 int status, len;
319 struct ctlr_info *h;
320 struct Scsi_Host *shost = class_to_shost(dev);
321 char tmpbuf[10];
322
323 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
324 return -EACCES;
325 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
326 strncpy(tmpbuf, buf, len);
327 tmpbuf[len] = '\0';
328 if (sscanf(tmpbuf, "%d", &status) != 1)
329 return -EINVAL;
330 h = shost_to_hba(shost);
331 h->acciopath_status = !!status;
332 dev_warn(&h->pdev->dev,
333 "hpsa: HP SSD Smart Path %s via sysfs update.\n",
334 h->acciopath_status ? "enabled" : "disabled");
335 return count;
336}
337
2ba8bfc8
SC		 338static ssize_t host_store_raid_offload_debug(struct device *dev,
339 struct device_attribute *attr,
340 const char *buf, size_t count)
341{
342 int debug_level, len;
343 struct ctlr_info *h;
344 struct Scsi_Host *shost = class_to_shost(dev);
345 char tmpbuf[10];
346
347 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
348 return -EACCES;
349 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
350 strncpy(tmpbuf, buf, len);
351 tmpbuf[len] = '\0';
352 if (sscanf(tmpbuf, "%d", &debug_level) != 1)
353 return -EINVAL;
354 if (debug_level < 0)
355 debug_level = 0;
356 h = shost_to_hba(shost);
357 h->raid_offload_debug = debug_level;
358 dev_warn(&h->pdev->dev, "hpsa: Set raid_offload_debug level = %d\n",
359 h->raid_offload_debug);
360 return count;
361}
362
edd16368
SC		 363static ssize_t host_store_rescan(struct device *dev,
364 struct device_attribute *attr,
365 const char *buf, size_t count)
366{
367 struct ctlr_info *h;
368 struct Scsi_Host *shost = class_to_shost(dev);
a23513e8 369 h = shost_to_hba(shost);
31468401 370 hpsa_scan_start(h->scsi_host);
edd16368
SC		 371 return count;
372}
373
d28ce020
SC		 374static ssize_t host_show_firmware_revision(struct device *dev,
375 struct device_attribute *attr, char *buf)
376{
377 struct ctlr_info *h;
378 struct Scsi_Host *shost = class_to_shost(dev);
379 unsigned char *fwrev;
380
381 h = shost_to_hba(shost);
382 if (!h->hba_inquiry_data)
383 return 0;
384 fwrev = &h->hba_inquiry_data[32];
385 return snprintf(buf, 20, "%c%c%c%c\n",
386 fwrev[0], fwrev[1], fwrev[2], fwrev[3]);
387}
388
94a13649
SC		 389static ssize_t host_show_commands_outstanding(struct device *dev,
390 struct device_attribute *attr, char *buf)
391{
392 struct Scsi_Host *shost = class_to_shost(dev);
393 struct ctlr_info *h = shost_to_hba(shost);
394
0cbf768e
SC		 395 return snprintf(buf, 20, "%d\n",
396 atomic_read(&h->commands_outstanding));
94a13649
SC		 397}
398
745a7a25
SC		 399static ssize_t host_show_transport_mode(struct device *dev,
400 struct device_attribute *attr, char *buf)
401{
402 struct ctlr_info *h;
403 struct Scsi_Host *shost = class_to_shost(dev);
404
405 h = shost_to_hba(shost);
406 return snprintf(buf, 20, "%s\n",
960a30e7 407 h->transMethod & CFGTBL_Trans_Performant ?
745a7a25
SC		 408 "performant" : "simple");
409}
410
da0697bd
ST		 411static ssize_t host_show_hp_ssd_smart_path_status(struct device *dev,
412 struct device_attribute *attr, char *buf)
413{
414 struct ctlr_info *h;
415 struct Scsi_Host *shost = class_to_shost(dev);
416
417 h = shost_to_hba(shost);
418 return snprintf(buf, 30, "HP SSD Smart Path %s\n",
419 (h->acciopath_status == 1) ? "enabled" : "disabled");
420}
421
46380786 422/* List of controllers which cannot be hard reset on kexec with reset_devices */
941b1cda
SC		 423static u32 unresettable_controller[] = {
424 0x324a103C, /* Smart Array P712m */
425 0x324b103C, /* SmartArray P711m */
426 0x3223103C, /* Smart Array P800 */
427 0x3234103C, /* Smart Array P400 */
428 0x3235103C, /* Smart Array P400i */
429 0x3211103C, /* Smart Array E200i */
430 0x3212103C, /* Smart Array E200 */
431 0x3213103C, /* Smart Array E200i */
432 0x3214103C, /* Smart Array E200i */
433 0x3215103C, /* Smart Array E200i */
434 0x3237103C, /* Smart Array E500 */
435 0x323D103C, /* Smart Array P700m */
7af0abbc 436 0x40800E11, /* Smart Array 5i */
941b1cda
SC		 437 0x409C0E11, /* Smart Array 6400 */
438 0x409D0E11, /* Smart Array 6400 EM */
5a4f934e
TH		 439 0x40700E11, /* Smart Array 5300 */
440 0x40820E11, /* Smart Array 532 */
441 0x40830E11, /* Smart Array 5312 */
442 0x409A0E11, /* Smart Array 641 */
443 0x409B0E11, /* Smart Array 642 */
444 0x40910E11, /* Smart Array 6i */
941b1cda
SC		 445};
446
46380786
SC		 447/* List of controllers which cannot even be soft reset */
448static u32 soft_unresettable_controller[] = {
7af0abbc 449 0x40800E11, /* Smart Array 5i */
5a4f934e
TH		 450 0x40700E11, /* Smart Array 5300 */
451 0x40820E11, /* Smart Array 532 */
452 0x40830E11, /* Smart Array 5312 */
453 0x409A0E11, /* Smart Array 641 */
454 0x409B0E11, /* Smart Array 642 */
455 0x40910E11, /* Smart Array 6i */
46380786
SC		 456 /* Exclude 640x boards. These are two pci devices in one slot
457 * which share a battery backed cache module. One controls the
458 * cache, the other accesses the cache through the one that controls
459 * it. If we reset the one controlling the cache, the other will
460 * likely not be happy. Just forbid resetting this conjoined mess.
461 * The 640x isn't really supported by hpsa anyway.
462 */
463 0x409C0E11, /* Smart Array 6400 */
464 0x409D0E11, /* Smart Array 6400 EM */
465};
466
467static int ctlr_is_hard_resettable(u32 board_id)
941b1cda
SC		 468{
469 int i;
470
471 for (i = 0; i < ARRAY_SIZE(unresettable_controller); i++)
46380786
SC		 472 if (unresettable_controller[i] == board_id)
473 return 0;
474 return 1;
475}
476
477static int ctlr_is_soft_resettable(u32 board_id)
478{
479 int i;
480
481 for (i = 0; i < ARRAY_SIZE(soft_unresettable_controller); i++)
482 if (soft_unresettable_controller[i] == board_id)
941b1cda
SC		 483 return 0;
484 return 1;
485}
486
46380786
SC		 487static int ctlr_is_resettable(u32 board_id)
488{
489 return ctlr_is_hard_resettable(board_id) ||
490 ctlr_is_soft_resettable(board_id);
491}
492
941b1cda
SC		 493static ssize_t host_show_resettable(struct device *dev,
494 struct device_attribute *attr, char *buf)
495{
496 struct ctlr_info *h;
497 struct Scsi_Host *shost = class_to_shost(dev);
498
499 h = shost_to_hba(shost);
46380786 500 return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h->board_id));
941b1cda
SC		 501}
502
edd16368
SC		 503static inline int is_logical_dev_addr_mode(unsigned char scsi3addr[])
504{
505 return (scsi3addr[3] & 0xC0) == 0x40;
506}
507
f2ef0ce7
RE		 508static const char * const raid_label[] = { "0", "4", "1(+0)", "5", "5+1", "6",
509 "1(+0)ADM", "UNKNOWN"
edd16368 510};
6b80b18f
ST		 511#define HPSA_RAID_0 0
512#define HPSA_RAID_4 1
513#define HPSA_RAID_1 2 /* also used for RAID 10 */
514#define HPSA_RAID_5 3 /* also used for RAID 50 */
515#define HPSA_RAID_51 4
516#define HPSA_RAID_6 5 /* also used for RAID 60 */
517#define HPSA_RAID_ADM 6 /* also used for RAID 1+0 ADM */
edd16368
SC		 518#define RAID_UNKNOWN (ARRAY_SIZE(raid_label) - 1)
519
520static ssize_t raid_level_show(struct device *dev,
521 struct device_attribute *attr, char *buf)
522{
523 ssize_t l = 0;
82a72c0a 524 unsigned char rlevel;
edd16368
SC		 525 struct ctlr_info *h;
526 struct scsi_device *sdev;
527 struct hpsa_scsi_dev_t *hdev;
528 unsigned long flags;
529
530 sdev = to_scsi_device(dev);
531 h = sdev_to_hba(sdev);
532 spin_lock_irqsave(&h->lock, flags);
533 hdev = sdev->hostdata;
534 if (!hdev) {
535 spin_unlock_irqrestore(&h->lock, flags);
536 return -ENODEV;
537 }
538
539 /* Is this even a logical drive? */
540 if (!is_logical_dev_addr_mode(hdev->scsi3addr)) {
541 spin_unlock_irqrestore(&h->lock, flags);
542 l = snprintf(buf, PAGE_SIZE, "N/A\n");
543 return l;
544 }
545
546 rlevel = hdev->raid_level;
547 spin_unlock_irqrestore(&h->lock, flags);
82a72c0a 548 if (rlevel > RAID_UNKNOWN)
edd16368
SC		 549 rlevel = RAID_UNKNOWN;
550 l = snprintf(buf, PAGE_SIZE, "RAID %s\n", raid_label[rlevel]);
551 return l;
552}
553
554static ssize_t lunid_show(struct device *dev,
555 struct device_attribute *attr, char *buf)
556{
557 struct ctlr_info *h;
558 struct scsi_device *sdev;
559 struct hpsa_scsi_dev_t *hdev;
560 unsigned long flags;
561 unsigned char lunid[8];
562
563 sdev = to_scsi_device(dev);
564 h = sdev_to_hba(sdev);
565 spin_lock_irqsave(&h->lock, flags);
566 hdev = sdev->hostdata;
567 if (!hdev) {
568 spin_unlock_irqrestore(&h->lock, flags);
569 return -ENODEV;
570 }
571 memcpy(lunid, hdev->scsi3addr, sizeof(lunid));
572 spin_unlock_irqrestore(&h->lock, flags);
573 return snprintf(buf, 20, "0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
574 lunid[0], lunid[1], lunid[2], lunid[3],
575 lunid[4], lunid[5], lunid[6], lunid[7]);
576}
577
578static ssize_t unique_id_show(struct device *dev,
579 struct device_attribute *attr, char *buf)
580{
581 struct ctlr_info *h;
582 struct scsi_device *sdev;
583 struct hpsa_scsi_dev_t *hdev;
584 unsigned long flags;
585 unsigned char sn[16];
586
587 sdev = to_scsi_device(dev);
588 h = sdev_to_hba(sdev);
589 spin_lock_irqsave(&h->lock, flags);
590 hdev = sdev->hostdata;
591 if (!hdev) {
592 spin_unlock_irqrestore(&h->lock, flags);
593 return -ENODEV;
594 }
595 memcpy(sn, hdev->device_id, sizeof(sn));
596 spin_unlock_irqrestore(&h->lock, flags);
597 return snprintf(buf, 16 * 2 + 2,
598 "%02X%02X%02X%02X%02X%02X%02X%02X"
599 "%02X%02X%02X%02X%02X%02X%02X%02X\n",
600 sn[0], sn[1], sn[2], sn[3],
601 sn[4], sn[5], sn[6], sn[7],
602 sn[8], sn[9], sn[10], sn[11],
603 sn[12], sn[13], sn[14], sn[15]);
604}
605
c1988684
ST		 606static ssize_t host_show_hp_ssd_smart_path_enabled(struct device *dev,
607 struct device_attribute *attr, char *buf)
608{
609 struct ctlr_info *h;
610 struct scsi_device *sdev;
611 struct hpsa_scsi_dev_t *hdev;
612 unsigned long flags;
613 int offload_enabled;
614
615 sdev = to_scsi_device(dev);
616 h = sdev_to_hba(sdev);
617 spin_lock_irqsave(&h->lock, flags);
618 hdev = sdev->hostdata;
619 if (!hdev) {
620 spin_unlock_irqrestore(&h->lock, flags);
621 return -ENODEV;
622 }
623 offload_enabled = hdev->offload_enabled;
624 spin_unlock_irqrestore(&h->lock, flags);
625 return snprintf(buf, 20, "%d\n", offload_enabled);
626}
627
3f5eac3a
SC		 628static DEVICE_ATTR(raid_level, S_IRUGO, raid_level_show, NULL);
629static DEVICE_ATTR(lunid, S_IRUGO, lunid_show, NULL);
630static DEVICE_ATTR(unique_id, S_IRUGO, unique_id_show, NULL);
631static DEVICE_ATTR(rescan, S_IWUSR, NULL, host_store_rescan);
c1988684
ST		 632static DEVICE_ATTR(hp_ssd_smart_path_enabled, S_IRUGO,
633 host_show_hp_ssd_smart_path_enabled, NULL);
da0697bd
ST		 634static DEVICE_ATTR(hp_ssd_smart_path_status, S_IWUSR|S_IRUGO|S_IROTH,
635 host_show_hp_ssd_smart_path_status,
636 host_store_hp_ssd_smart_path_status);
2ba8bfc8
SC		 637static DEVICE_ATTR(raid_offload_debug, S_IWUSR, NULL,
638 host_store_raid_offload_debug);
3f5eac3a
SC		 639static DEVICE_ATTR(firmware_revision, S_IRUGO,
640 host_show_firmware_revision, NULL);
641static DEVICE_ATTR(commands_outstanding, S_IRUGO,
642 host_show_commands_outstanding, NULL);
643static DEVICE_ATTR(transport_mode, S_IRUGO,
644 host_show_transport_mode, NULL);
941b1cda
SC		 645static DEVICE_ATTR(resettable, S_IRUGO,
646 host_show_resettable, NULL);
3f5eac3a
SC		 647
648static struct device_attribute *hpsa_sdev_attrs[] = {
649 &dev_attr_raid_level,
650 &dev_attr_lunid,
651 &dev_attr_unique_id,
c1988684 652 &dev_attr_hp_ssd_smart_path_enabled,
3f5eac3a
SC		 653 NULL,
654};
655
656static struct device_attribute *hpsa_shost_attrs[] = {
657 &dev_attr_rescan,
658 &dev_attr_firmware_revision,
659 &dev_attr_commands_outstanding,
660 &dev_attr_transport_mode,
941b1cda 661 &dev_attr_resettable,
da0697bd 662 &dev_attr_hp_ssd_smart_path_status,
2ba8bfc8 663 &dev_attr_raid_offload_debug,
3f5eac3a
SC		 664 NULL,
665};
666
667static struct scsi_host_template hpsa_driver_template = {
668 .module = THIS_MODULE,
f79cfec6
SC		 669 .name = HPSA,
670 .proc_name = HPSA,
3f5eac3a
SC		 671 .queuecommand = hpsa_scsi_queue_command,
672 .scan_start = hpsa_scan_start,
673 .scan_finished = hpsa_scan_finished,
7c0a0229 674 .change_queue_depth = hpsa_change_queue_depth,
3f5eac3a
SC		 675 .this_id = -1,
676 .use_clustering = ENABLE_CLUSTERING,
75167d2c 677 .eh_abort_handler = hpsa_eh_abort_handler,
3f5eac3a
SC		 678 .eh_device_reset_handler = hpsa_eh_device_reset_handler,
679 .ioctl = hpsa_ioctl,
680 .slave_alloc = hpsa_slave_alloc,
681 .slave_destroy = hpsa_slave_destroy,
682#ifdef CONFIG_COMPAT
683 .compat_ioctl = hpsa_compat_ioctl,
684#endif
685 .sdev_attrs = hpsa_sdev_attrs,
686 .shost_attrs = hpsa_shost_attrs,
c0d6a4d1 687 .max_sectors = 8192,
54b2b50c 688 .no_write_same = 1,
3f5eac3a
SC		 689};
690
254f796b 691static inline u32 next_command(struct ctlr_info *h, u8 q)
3f5eac3a
SC		 692{
693 u32 a;
072b0518 694 struct reply_queue_buffer *rq = &h->reply_queue[q];
3f5eac3a 695
e1f7de0c
MG		 696 if (h->transMethod & CFGTBL_Trans_io_accel1)
697 return h->access.command_completed(h, q);
698
3f5eac3a 699 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
254f796b 700 return h->access.command_completed(h, q);
3f5eac3a 701
254f796b
MG		 702 if ((rq->head[rq->current_entry] & 1) == rq->wraparound) {
703 a = rq->head[rq->current_entry];
704 rq->current_entry++;
0cbf768e 705 atomic_dec(&h->commands_outstanding);
3f5eac3a
SC		 706 } else {
707 a = FIFO_EMPTY;
708 }
709 /* Check for wraparound */
254f796b
MG		 710 if (rq->current_entry == h->max_commands) {
711 rq->current_entry = 0;
712 rq->wraparound ^= 1;
3f5eac3a
SC		 713 }
714 return a;
715}
716
c349775e
ST		 717/*
718 * There are some special bits in the bus address of the
719 * command that we have to set for the controller to know
720 * how to process the command:
721 *
722 * Normal performant mode:
723 * bit 0: 1 means performant mode, 0 means simple mode.
724 * bits 1-3 = block fetch table entry
725 * bits 4-6 = command type (== 0)
726 *
727 * ioaccel1 mode:
728 * bit 0 = "performant mode" bit.
729 * bits 1-3 = block fetch table entry
730 * bits 4-6 = command type (== 110)
731 * (command type is needed because ioaccel1 mode
732 * commands are submitted through the same register as normal
733 * mode commands, so this is how the controller knows whether
734 * the command is normal mode or ioaccel1 mode.)
735 *
736 * ioaccel2 mode:
737 * bit 0 = "performant mode" bit.
738 * bits 1-4 = block fetch table entry (note extra bit)
739 * bits 4-6 = not needed, because ioaccel2 mode has
740 * a separate special register for submitting commands.
741 */
742
3f5eac3a
SC		 743/* set_performant_mode: Modify the tag for cciss performant
744 * set bit 0 for pull model, bits 3-1 for block fetch
745 * register number
746 */
747static void set_performant_mode(struct ctlr_info *h, struct CommandList *c)
748{
254f796b 749 if (likely(h->transMethod & CFGTBL_Trans_Performant)) {
3f5eac3a 750 c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1);
eee0f03a 751 if (likely(h->msix_vector > 0))
254f796b 752 c->Header.ReplyQueue =
804a5cb5 753 raw_smp_processor_id() % h->nreply_queues;
254f796b 754 }
3f5eac3a
SC		 755}
756
c349775e
ST		 757static void set_ioaccel1_performant_mode(struct ctlr_info *h,
758 struct CommandList *c)
759{
760 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
761
762 /* Tell the controller to post the reply to the queue for this
763 * processor. This seems to give the best I/O throughput.
764 */
765 cp->ReplyQueue = smp_processor_id() % h->nreply_queues;
766 /* Set the bits in the address sent down to include:
767 * - performant mode bit (bit 0)
768 * - pull count (bits 1-3)
769 * - command type (bits 4-6)
770 */
771 c->busaddr |= 1 | (h->ioaccel1_blockFetchTable[c->Header.SGList] << 1) |
772 IOACCEL1_BUSADDR_CMDTYPE;
773}
774
775static void set_ioaccel2_performant_mode(struct ctlr_info *h,
776 struct CommandList *c)
777{
778 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
779
780 /* Tell the controller to post the reply to the queue for this
781 * processor. This seems to give the best I/O throughput.
782 */
783 cp->reply_queue = smp_processor_id() % h->nreply_queues;
784 /* Set the bits in the address sent down to include:
785 * - performant mode bit not used in ioaccel mode 2
786 * - pull count (bits 0-3)
787 * - command type isn't needed for ioaccel2
788 */
789 c->busaddr |= (h->ioaccel2_blockFetchTable[cp->sg_count]);
790}
791
e85c5974
SC		 792static int is_firmware_flash_cmd(u8 *cdb)
793{
794 return cdb[0] == BMIC_WRITE && cdb[6] == BMIC_FLASH_FIRMWARE;
795}
796
797/*
798 * During firmware flash, the heartbeat register may not update as frequently
799 * as it should. So we dial down lockup detection during firmware flash. and
800 * dial it back up when firmware flash completes.
801 */
802#define HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH (240 * HZ)
803#define HEARTBEAT_SAMPLE_INTERVAL (30 * HZ)
804static void dial_down_lockup_detection_during_fw_flash(struct ctlr_info *h,
805 struct CommandList *c)
806{
807 if (!is_firmware_flash_cmd(c->Request.CDB))
808 return;
809 atomic_inc(&h->firmware_flash_in_progress);
810 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH;
811}
812
813static void dial_up_lockup_detection_on_fw_flash_complete(struct ctlr_info *h,
814 struct CommandList *c)
815{
816 if (is_firmware_flash_cmd(c->Request.CDB) &&
817 atomic_dec_and_test(&h->firmware_flash_in_progress))
818 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
819}
820
3f5eac3a
SC		 821static void enqueue_cmd_and_start_io(struct ctlr_info *h,
822 struct CommandList *c)
823{
c349775e
ST		 824 switch (c->cmd_type) {
825 case CMD_IOACCEL1:
826 set_ioaccel1_performant_mode(h, c);
827 break;
828 case CMD_IOACCEL2:
829 set_ioaccel2_performant_mode(h, c);
830 break;
831 default:
832 set_performant_mode(h, c);
833 }
e85c5974 834 dial_down_lockup_detection_during_fw_flash(h, c);
f2405db8
DB		 835 atomic_inc(&h->commands_outstanding);
836 h->access.submit_command(h, c);
3f5eac3a
SC		 837}
838
839static inline int is_hba_lunid(unsigned char scsi3addr[])
840{
841 return memcmp(scsi3addr, RAID_CTLR_LUNID, 8) == 0;
842}
843
844static inline int is_scsi_rev_5(struct ctlr_info *h)
845{
846 if (!h->hba_inquiry_data)
847 return 0;
848 if ((h->hba_inquiry_data[2] & 0x07) == 5)
849 return 1;
850 return 0;
851}
852
edd16368
SC		 853static int hpsa_find_target_lun(struct ctlr_info *h,
854 unsigned char scsi3addr[], int bus, int *target, int *lun)
855{
856 /* finds an unused bus, target, lun for a new physical device
857 * assumes h->devlock is held
858 */
859 int i, found = 0;
cfe5badc 860 DECLARE_BITMAP(lun_taken, HPSA_MAX_DEVICES);
edd16368 861
263d9401 862 bitmap_zero(lun_taken, HPSA_MAX_DEVICES);
edd16368
SC		 863
864 for (i = 0; i < h->ndevices; i++) {
865 if (h->dev[i]->bus == bus && h->dev[i]->target != -1)
263d9401 866 __set_bit(h->dev[i]->target, lun_taken);
edd16368
SC		 867 }
868
263d9401
AM		 869 i = find_first_zero_bit(lun_taken, HPSA_MAX_DEVICES);
870 if (i < HPSA_MAX_DEVICES) {
871 /* *bus = 1; */
872 *target = i;
873 *lun = 0;
874 found = 1;
edd16368
SC		 875 }
876 return !found;
877}
878
879/* Add an entry into h->dev[] array. */
880static int hpsa_scsi_add_entry(struct ctlr_info *h, int hostno,
881 struct hpsa_scsi_dev_t *device,
882 struct hpsa_scsi_dev_t *added[], int *nadded)
883{
884 /* assumes h->devlock is held */
885 int n = h->ndevices;
886 int i;
887 unsigned char addr1[8], addr2[8];
888 struct hpsa_scsi_dev_t *sd;
889
cfe5badc 890 if (n >= HPSA_MAX_DEVICES) {
edd16368
SC		 891 dev_err(&h->pdev->dev, "too many devices, some will be "
892 "inaccessible.\n");
893 return -1;
894 }
895
896 /* physical devices do not have lun or target assigned until now. */
897 if (device->lun != -1)
898 /* Logical device, lun is already assigned. */
899 goto lun_assigned;
900
901 /* If this device a non-zero lun of a multi-lun device
902 * byte 4 of the 8-byte LUN addr will contain the logical
2b08b3e9 903 * unit no, zero otherwise.
edd16368
SC		 904 */
905 if (device->scsi3addr[4] == 0) {
906 /* This is not a non-zero lun of a multi-lun device */
907 if (hpsa_find_target_lun(h, device->scsi3addr,
908 device->bus, &device->target, &device->lun) != 0)
909 return -1;
910 goto lun_assigned;
911 }
912
913 /* This is a non-zero lun of a multi-lun device.
914 * Search through our list and find the device which
915 * has the same 8 byte LUN address, excepting byte 4.
916 * Assign the same bus and target for this new LUN.
917 * Use the logical unit number from the firmware.
918 */
919 memcpy(addr1, device->scsi3addr, 8);
920 addr1[4] = 0;
921 for (i = 0; i < n; i++) {
922 sd = h->dev[i];
923 memcpy(addr2, sd->scsi3addr, 8);
924 addr2[4] = 0;
925 /* differ only in byte 4? */
926 if (memcmp(addr1, addr2, 8) == 0) {
927 device->bus = sd->bus;
928 device->target = sd->target;
929 device->lun = device->scsi3addr[4];
930 break;
931 }
932 }
933 if (device->lun == -1) {
934 dev_warn(&h->pdev->dev, "physical device with no LUN=0,"
935 " suspect firmware bug or unsupported hardware "
936 "configuration.\n");
937 return -1;
938 }
939
940lun_assigned:
941
942 h->dev[n] = device;
943 h->ndevices++;
944 added[*nadded] = device;
945 (*nadded)++;
946
947 /* initially, (before registering with scsi layer) we don't
948 * know our hostno and we don't want to print anything first
949 * time anyway (the scsi layer's inquiries will show that info)
950 */
951 /* if (hostno != -1) */
952 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d added.\n",
953 scsi_device_type(device->devtype), hostno,
954 device->bus, device->target, device->lun);
955 return 0;
956}
957
bd9244f7
ST		 958/* Update an entry in h->dev[] array. */
959static void hpsa_scsi_update_entry(struct ctlr_info *h, int hostno,
960 int entry, struct hpsa_scsi_dev_t *new_entry)
961{
962 /* assumes h->devlock is held */
963 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
964
965 /* Raid level changed. */
966 h->dev[entry]->raid_level = new_entry->raid_level;
250fb125
SC		 967
968 /* Raid offload parameters changed. */
969 h->dev[entry]->offload_config = new_entry->offload_config;
970 h->dev[entry]->offload_enabled = new_entry->offload_enabled;
9fb0de2d
SC		 971 h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
972 h->dev[entry]->offload_to_mirror = new_entry->offload_to_mirror;
973 h->dev[entry]->raid_map = new_entry->raid_map;
250fb125 974
bd9244f7
ST		 975 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d updated.\n",
976 scsi_device_type(new_entry->devtype), hostno, new_entry->bus,
977 new_entry->target, new_entry->lun);
978}
979
2a8ccf31
SC		 980/* Replace an entry from h->dev[] array. */
981static void hpsa_scsi_replace_entry(struct ctlr_info *h, int hostno,
982 int entry, struct hpsa_scsi_dev_t *new_entry,
983 struct hpsa_scsi_dev_t *added[], int *nadded,
984 struct hpsa_scsi_dev_t *removed[], int *nremoved)
985{
986 /* assumes h->devlock is held */
cfe5badc 987 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
2a8ccf31
SC		 988 removed[*nremoved] = h->dev[entry];
989 (*nremoved)++;
01350d05
SC		 990
991 /*
992 * New physical devices won't have target/lun assigned yet
993 * so we need to preserve the values in the slot we are replacing.
994 */
995 if (new_entry->target == -1) {
996 new_entry->target = h->dev[entry]->target;
997 new_entry->lun = h->dev[entry]->lun;
998 }
999
2a8ccf31
SC		 1000 h->dev[entry] = new_entry;
1001 added[*nadded] = new_entry;
1002 (*nadded)++;
1003 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d changed.\n",
1004 scsi_device_type(new_entry->devtype), hostno, new_entry->bus,
1005 new_entry->target, new_entry->lun);
1006}
1007
edd16368
SC		 1008/* Remove an entry from h->dev[] array. */
1009static void hpsa_scsi_remove_entry(struct ctlr_info *h, int hostno, int entry,
1010 struct hpsa_scsi_dev_t *removed[], int *nremoved)
1011{
1012 /* assumes h->devlock is held */
1013 int i;
1014 struct hpsa_scsi_dev_t *sd;
1015
cfe5badc 1016 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
edd16368
SC		 1017
1018 sd = h->dev[entry];
1019 removed[*nremoved] = h->dev[entry];
1020 (*nremoved)++;
1021
1022 for (i = entry; i < h->ndevices-1; i++)
1023 h->dev[i] = h->dev[i+1];
1024 h->ndevices--;
1025 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d removed.\n",
1026 scsi_device_type(sd->devtype), hostno, sd->bus, sd->target,
1027 sd->lun);
1028}
1029
1030#define SCSI3ADDR_EQ(a, b) ( \
1031 (a)[7] == (b)[7] && \
1032 (a)[6] == (b)[6] && \
1033 (a)[5] == (b)[5] && \
1034 (a)[4] == (b)[4] && \
1035 (a)[3] == (b)[3] && \
1036 (a)[2] == (b)[2] && \
1037 (a)[1] == (b)[1] && \
1038 (a)[0] == (b)[0])
1039
1040static void fixup_botched_add(struct ctlr_info *h,
1041 struct hpsa_scsi_dev_t *added)
1042{
1043 /* called when scsi_add_device fails in order to re-adjust
1044 * h->dev[] to match the mid layer's view.
1045 */
1046 unsigned long flags;
1047 int i, j;
1048
1049 spin_lock_irqsave(&h->lock, flags);
1050 for (i = 0; i < h->ndevices; i++) {
1051 if (h->dev[i] == added) {
1052 for (j = i; j < h->ndevices-1; j++)
1053 h->dev[j] = h->dev[j+1];
1054 h->ndevices--;
1055 break;
1056 }
1057 }
1058 spin_unlock_irqrestore(&h->lock, flags);
1059 kfree(added);
1060}
1061
1062static inline int device_is_the_same(struct hpsa_scsi_dev_t *dev1,
1063 struct hpsa_scsi_dev_t *dev2)
1064{
edd16368
SC		 1065 /* we compare everything except lun and target as these
1066 * are not yet assigned. Compare parts likely
1067 * to differ first
1068 */
1069 if (memcmp(dev1->scsi3addr, dev2->scsi3addr,
1070 sizeof(dev1->scsi3addr)) != 0)
1071 return 0;
1072 if (memcmp(dev1->device_id, dev2->device_id,
1073 sizeof(dev1->device_id)) != 0)
1074 return 0;
1075 if (memcmp(dev1->model, dev2->model, sizeof(dev1->model)) != 0)
1076 return 0;
1077 if (memcmp(dev1->vendor, dev2->vendor, sizeof(dev1->vendor)) != 0)
1078 return 0;
edd16368
SC		 1079 if (dev1->devtype != dev2->devtype)
1080 return 0;
edd16368
SC		 1081 if (dev1->bus != dev2->bus)
1082 return 0;
1083 return 1;
1084}
1085
bd9244f7
ST		 1086static inline int device_updated(struct hpsa_scsi_dev_t *dev1,
1087 struct hpsa_scsi_dev_t *dev2)
1088{
1089 /* Device attributes that can change, but don't mean
1090 * that the device is a different device, nor that the OS
1091 * needs to be told anything about the change.
1092 */
1093 if (dev1->raid_level != dev2->raid_level)
1094 return 1;
250fb125
SC		 1095 if (dev1->offload_config != dev2->offload_config)
1096 return 1;
1097 if (dev1->offload_enabled != dev2->offload_enabled)
1098 return 1;
bd9244f7
ST		 1099 return 0;
1100}
1101
edd16368
SC		 1102/* Find needle in haystack. If exact match found, return DEVICE_SAME,
1103 * and return needle location in *index. If scsi3addr matches, but not
1104 * vendor, model, serial num, etc. return DEVICE_CHANGED, and return needle
bd9244f7
ST		 1105 * location in *index.
1106 * In the case of a minor device attribute change, such as RAID level, just
1107 * return DEVICE_UPDATED, along with the updated device's location in index.
1108 * If needle not found, return DEVICE_NOT_FOUND.
edd16368
SC		 1109 */
1110static int hpsa_scsi_find_entry(struct hpsa_scsi_dev_t *needle,
1111 struct hpsa_scsi_dev_t *haystack[], int haystack_size,
1112 int *index)
1113{
1114 int i;
1115#define DEVICE_NOT_FOUND 0
1116#define DEVICE_CHANGED 1
1117#define DEVICE_SAME 2
bd9244f7 1118#define DEVICE_UPDATED 3
edd16368 1119 for (i = 0; i < haystack_size; i++) {
23231048
SC		 1120 if (haystack[i] == NULL) /* previously removed. */
1121 continue;
edd16368
SC		 1122 if (SCSI3ADDR_EQ(needle->scsi3addr, haystack[i]->scsi3addr)) {
1123 *index = i;
bd9244f7
ST		 1124 if (device_is_the_same(needle, haystack[i])) {
1125 if (device_updated(needle, haystack[i]))
1126 return DEVICE_UPDATED;
edd16368 1127 return DEVICE_SAME;
bd9244f7 1128 } else {
9846590e
SC		 1129 /* Keep offline devices offline */
1130 if (needle->volume_offline)
1131 return DEVICE_NOT_FOUND;
edd16368 1132 return DEVICE_CHANGED;
bd9244f7 1133 }
edd16368
SC		 1134 }
1135 }
1136 *index = -1;
1137 return DEVICE_NOT_FOUND;
1138}
1139
9846590e
SC		 1140static void hpsa_monitor_offline_device(struct ctlr_info *h,
1141 unsigned char scsi3addr[])
1142{
1143 struct offline_device_entry *device;
1144 unsigned long flags;
1145
1146 /* Check to see if device is already on the list */
1147 spin_lock_irqsave(&h->offline_device_lock, flags);
1148 list_for_each_entry(device, &h->offline_device_list, offline_list) {
1149 if (memcmp(device->scsi3addr, scsi3addr,
1150 sizeof(device->scsi3addr)) == 0) {
1151 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1152 return;
1153 }
1154 }
1155 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1156
1157 /* Device is not on the list, add it. */
1158 device = kmalloc(sizeof(*device), GFP_KERNEL);
1159 if (!device) {
1160 dev_warn(&h->pdev->dev, "out of memory in %s\n", __func__);
1161 return;
1162 }
1163 memcpy(device->scsi3addr, scsi3addr, sizeof(device->scsi3addr));
1164 spin_lock_irqsave(&h->offline_device_lock, flags);
1165 list_add_tail(&device->offline_list, &h->offline_device_list);
1166 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1167}
1168
1169/* Print a message explaining various offline volume states */
1170static void hpsa_show_volume_status(struct ctlr_info *h,
1171 struct hpsa_scsi_dev_t *sd)
1172{
1173 if (sd->volume_offline == HPSA_VPD_LV_STATUS_UNSUPPORTED)
1174 dev_info(&h->pdev->dev,
1175 "C%d:B%d:T%d:L%d Volume status is not available through vital product data pages.\n",
1176 h->scsi_host->host_no,
1177 sd->bus, sd->target, sd->lun);
1178 switch (sd->volume_offline) {
1179 case HPSA_LV_OK:
1180 break;
1181 case HPSA_LV_UNDERGOING_ERASE:
1182 dev_info(&h->pdev->dev,
1183 "C%d:B%d:T%d:L%d Volume is undergoing background erase process.\n",
1184 h->scsi_host->host_no,
1185 sd->bus, sd->target, sd->lun);
1186 break;
1187 case HPSA_LV_UNDERGOING_RPI:
1188 dev_info(&h->pdev->dev,
1189 "C%d:B%d:T%d:L%d Volume is undergoing rapid parity initialization process.\n",
1190 h->scsi_host->host_no,
1191 sd->bus, sd->target, sd->lun);
1192 break;
1193 case HPSA_LV_PENDING_RPI:
1194 dev_info(&h->pdev->dev,
1195 "C%d:B%d:T%d:L%d Volume is queued for rapid parity initialization process.\n",
1196 h->scsi_host->host_no,
1197 sd->bus, sd->target, sd->lun);
1198 break;
1199 case HPSA_LV_ENCRYPTED_NO_KEY:
1200 dev_info(&h->pdev->dev,
1201 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because key is not present.\n",
1202 h->scsi_host->host_no,
1203 sd->bus, sd->target, sd->lun);
1204 break;
1205 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
1206 dev_info(&h->pdev->dev,
1207 "C%d:B%d:T%d:L%d Volume is not encrypted and cannot be accessed because controller is in encryption-only mode.\n",
1208 h->scsi_host->host_no,
1209 sd->bus, sd->target, sd->lun);
1210 break;
1211 case HPSA_LV_UNDERGOING_ENCRYPTION:
1212 dev_info(&h->pdev->dev,
1213 "C%d:B%d:T%d:L%d Volume is undergoing encryption process.\n",
1214 h->scsi_host->host_no,
1215 sd->bus, sd->target, sd->lun);
1216 break;
1217 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
1218 dev_info(&h->pdev->dev,
1219 "C%d:B%d:T%d:L%d Volume is undergoing encryption re-keying process.\n",
1220 h->scsi_host->host_no,
1221 sd->bus, sd->target, sd->lun);
1222 break;
1223 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
1224 dev_info(&h->pdev->dev,
1225 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because controller does not have encryption enabled.\n",
1226 h->scsi_host->host_no,
1227 sd->bus, sd->target, sd->lun);
1228 break;
1229 case HPSA_LV_PENDING_ENCRYPTION:
1230 dev_info(&h->pdev->dev,
1231 "C%d:B%d:T%d:L%d Volume is pending migration to encrypted state, but process has not started.\n",
1232 h->scsi_host->host_no,
1233 sd->bus, sd->target, sd->lun);
1234 break;
1235 case HPSA_LV_PENDING_ENCRYPTION_REKEYING:
1236 dev_info(&h->pdev->dev,
1237 "C%d:B%d:T%d:L%d Volume is encrypted and is pending encryption rekeying.\n",
1238 h->scsi_host->host_no,
1239 sd->bus, sd->target, sd->lun);
1240 break;
1241 }
1242}
1243
4967bd3e 1244static void adjust_hpsa_scsi_table(struct ctlr_info *h, int hostno,
edd16368
SC		 1245 struct hpsa_scsi_dev_t *sd[], int nsds)
1246{
1247 /* sd contains scsi3 addresses and devtypes, and inquiry
1248 * data. This function takes what's in sd to be the current
1249 * reality and updates h->dev[] to reflect that reality.
1250 */
1251 int i, entry, device_change, changes = 0;
1252 struct hpsa_scsi_dev_t *csd;
1253 unsigned long flags;
1254 struct hpsa_scsi_dev_t **added, **removed;
1255 int nadded, nremoved;
1256 struct Scsi_Host *sh = NULL;
1257
cfe5badc
ST		 1258 added = kzalloc(sizeof(*added) * HPSA_MAX_DEVICES, GFP_KERNEL);
1259 removed = kzalloc(sizeof(*removed) * HPSA_MAX_DEVICES, GFP_KERNEL);
edd16368
SC		 1260
1261 if (!added || !removed) {
1262 dev_warn(&h->pdev->dev, "out of memory in "
1263 "adjust_hpsa_scsi_table\n");
1264 goto free_and_out;
1265 }
1266
1267 spin_lock_irqsave(&h->devlock, flags);
1268
1269 /* find any devices in h->dev[] that are not in
1270 * sd[] and remove them from h->dev[], and for any
1271 * devices which have changed, remove the old device
1272 * info and add the new device info.
bd9244f7
ST		 1273 * If minor device attributes change, just update
1274 * the existing device structure.
edd16368
SC		 1275 */
1276 i = 0;
1277 nremoved = 0;
1278 nadded = 0;
1279 while (i < h->ndevices) {
1280 csd = h->dev[i];
1281 device_change = hpsa_scsi_find_entry(csd, sd, nsds, &entry);
1282 if (device_change == DEVICE_NOT_FOUND) {
1283 changes++;
1284 hpsa_scsi_remove_entry(h, hostno, i,
1285 removed, &nremoved);
1286 continue; /* remove ^^^, hence i not incremented */
1287 } else if (device_change == DEVICE_CHANGED) {
1288 changes++;
2a8ccf31
SC		 1289 hpsa_scsi_replace_entry(h, hostno, i, sd[entry],
1290 added, &nadded, removed, &nremoved);
c7f172dc
SC		 1291 /* Set it to NULL to prevent it from being freed
1292 * at the bottom of hpsa_update_scsi_devices()
1293 */
1294 sd[entry] = NULL;
bd9244f7
ST		 1295 } else if (device_change == DEVICE_UPDATED) {
1296 hpsa_scsi_update_entry(h, hostno, i, sd[entry]);
edd16368
SC		 1297 }
1298 i++;
1299 }
1300
1301 /* Now, make sure every device listed in sd[] is also
1302 * listed in h->dev[], adding them if they aren't found
1303 */
1304
1305 for (i = 0; i < nsds; i++) {
1306 if (!sd[i]) /* if already added above. */
1307 continue;
9846590e
SC		 1308
1309 /* Don't add devices which are NOT READY, FORMAT IN PROGRESS
1310 * as the SCSI mid-layer does not handle such devices well.
1311 * It relentlessly loops sending TUR at 3Hz, then READ(10)
1312 * at 160Hz, and prevents the system from coming up.
1313 */
1314 if (sd[i]->volume_offline) {
1315 hpsa_show_volume_status(h, sd[i]);
1316 dev_info(&h->pdev->dev, "c%db%dt%dl%d: temporarily offline\n",
1317 h->scsi_host->host_no,
1318 sd[i]->bus, sd[i]->target, sd[i]->lun);
1319 continue;
1320 }
1321
edd16368
SC		 1322 device_change = hpsa_scsi_find_entry(sd[i], h->dev,
1323 h->ndevices, &entry);
1324 if (device_change == DEVICE_NOT_FOUND) {
1325 changes++;
1326 if (hpsa_scsi_add_entry(h, hostno, sd[i],
1327 added, &nadded) != 0)
1328 break;
1329 sd[i] = NULL; /* prevent from being freed later. */
1330 } else if (device_change == DEVICE_CHANGED) {
1331 /* should never happen... */
1332 changes++;
1333 dev_warn(&h->pdev->dev,
1334 "device unexpectedly changed.\n");
1335 /* but if it does happen, we just ignore that device */
1336 }
1337 }
1338 spin_unlock_irqrestore(&h->devlock, flags);
1339
9846590e
SC		 1340 /* Monitor devices which are in one of several NOT READY states to be
1341 * brought online later. This must be done without holding h->devlock,
1342 * so don't touch h->dev[]
1343 */
1344 for (i = 0; i < nsds; i++) {
1345 if (!sd[i]) /* if already added above. */
1346 continue;
1347 if (sd[i]->volume_offline)
1348 hpsa_monitor_offline_device(h, sd[i]->scsi3addr);
1349 }
1350
edd16368
SC		 1351 /* Don't notify scsi mid layer of any changes the first time through
1352 * (or if there are no changes) scsi_scan_host will do it later the
1353 * first time through.
1354 */
1355 if (hostno == -1 || !changes)
1356 goto free_and_out;
1357
1358 sh = h->scsi_host;
1359 /* Notify scsi mid layer of any removed devices */
1360 for (i = 0; i < nremoved; i++) {
1361 struct scsi_device *sdev =
1362 scsi_device_lookup(sh, removed[i]->bus,
1363 removed[i]->target, removed[i]->lun);
1364 if (sdev != NULL) {
1365 scsi_remove_device(sdev);
1366 scsi_device_put(sdev);
1367 } else {
1368 /* We don't expect to get here.
1369 * future cmds to this device will get selection
1370 * timeout as if the device was gone.
1371 */
1372 dev_warn(&h->pdev->dev, "didn't find c%db%dt%dl%d "
1373 " for removal.", hostno, removed[i]->bus,
1374 removed[i]->target, removed[i]->lun);
1375 }
1376 kfree(removed[i]);
1377 removed[i] = NULL;
1378 }
1379
1380 /* Notify scsi mid layer of any added devices */
1381 for (i = 0; i < nadded; i++) {
1382 if (scsi_add_device(sh, added[i]->bus,
1383 added[i]->target, added[i]->lun) == 0)
1384 continue;
1385 dev_warn(&h->pdev->dev, "scsi_add_device c%db%dt%dl%d failed, "
1386 "device not added.\n", hostno, added[i]->bus,
1387 added[i]->target, added[i]->lun);
1388 /* now we have to remove it from h->dev,
1389 * since it didn't get added to scsi mid layer
1390 */
1391 fixup_botched_add(h, added[i]);
1392 }
1393
1394free_and_out:
1395 kfree(added);
1396 kfree(removed);
edd16368
SC		 1397}
1398
1399/*
9e03aa2f 1400 * Lookup bus/target/lun and return corresponding struct hpsa_scsi_dev_t *
edd16368
SC		 1401 * Assume's h->devlock is held.
1402 */
1403static struct hpsa_scsi_dev_t *lookup_hpsa_scsi_dev(struct ctlr_info *h,
1404 int bus, int target, int lun)
1405{
1406 int i;
1407 struct hpsa_scsi_dev_t *sd;
1408
1409 for (i = 0; i < h->ndevices; i++) {
1410 sd = h->dev[i];
1411 if (sd->bus == bus && sd->target == target && sd->lun == lun)
1412 return sd;
1413 }
1414 return NULL;
1415}
1416
1417/* link sdev->hostdata to our per-device structure. */
1418static int hpsa_slave_alloc(struct scsi_device *sdev)
1419{
1420 struct hpsa_scsi_dev_t *sd;
1421 unsigned long flags;
1422 struct ctlr_info *h;
1423
1424 h = sdev_to_hba(sdev);
1425 spin_lock_irqsave(&h->devlock, flags);
1426 sd = lookup_hpsa_scsi_dev(h, sdev_channel(sdev),
1427 sdev_id(sdev), sdev->lun);
1428 if (sd != NULL)
1429 sdev->hostdata = sd;
1430 spin_unlock_irqrestore(&h->devlock, flags);
1431 return 0;
1432}
1433
1434static void hpsa_slave_destroy(struct scsi_device *sdev)
1435{
bcc44255 1436 /* nothing to do. */
edd16368
SC		 1437}
1438
33a2ffce
SC		 1439static void hpsa_free_sg_chain_blocks(struct ctlr_info *h)
1440{
1441 int i;
1442
1443 if (!h->cmd_sg_list)
1444 return;
1445 for (i = 0; i < h->nr_cmds; i++) {
1446 kfree(h->cmd_sg_list[i]);
1447 h->cmd_sg_list[i] = NULL;
1448 }
1449 kfree(h->cmd_sg_list);
1450 h->cmd_sg_list = NULL;
1451}
1452
1453static int hpsa_allocate_sg_chain_blocks(struct ctlr_info *h)
1454{
1455 int i;
1456
1457 if (h->chainsize <= 0)
1458 return 0;
1459
1460 h->cmd_sg_list = kzalloc(sizeof(*h->cmd_sg_list) * h->nr_cmds,
1461 GFP_KERNEL);
3d4e6af8
RE		 1462 if (!h->cmd_sg_list) {
1463 dev_err(&h->pdev->dev, "Failed to allocate SG list\n");
33a2ffce 1464 return -ENOMEM;
3d4e6af8 1465 }
33a2ffce
SC		 1466 for (i = 0; i < h->nr_cmds; i++) {
1467 h->cmd_sg_list[i] = kmalloc(sizeof(*h->cmd_sg_list[i]) *
1468 h->chainsize, GFP_KERNEL);
3d4e6af8
RE		 1469 if (!h->cmd_sg_list[i]) {
1470 dev_err(&h->pdev->dev, "Failed to allocate cmd SG\n");
33a2ffce 1471 goto clean;
3d4e6af8 1472 }
33a2ffce
SC		 1473 }
1474 return 0;
1475
1476clean:
1477 hpsa_free_sg_chain_blocks(h);
1478 return -ENOMEM;
1479}
1480
e2bea6df 1481static int hpsa_map_sg_chain_block(struct ctlr_info *h,
33a2ffce
SC		 1482 struct CommandList *c)
1483{
1484 struct SGDescriptor *chain_sg, *chain_block;
1485 u64 temp64;
50a0decf 1486 u32 chain_len;
33a2ffce
SC		 1487
1488 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
1489 chain_block = h->cmd_sg_list[c->cmdindex];
50a0decf
SC		 1490 chain_sg->Ext = cpu_to_le32(HPSA_SG_CHAIN);
1491 chain_len = sizeof(*chain_sg) *
2b08b3e9 1492 (le16_to_cpu(c->Header.SGTotal) - h->max_cmd_sg_entries);
50a0decf
SC		 1493 chain_sg->Len = cpu_to_le32(chain_len);
1494 temp64 = pci_map_single(h->pdev, chain_block, chain_len,
33a2ffce 1495 PCI_DMA_TODEVICE);
e2bea6df
SC		 1496 if (dma_mapping_error(&h->pdev->dev, temp64)) {
1497 /* prevent subsequent unmapping */
50a0decf 1498 chain_sg->Addr = cpu_to_le64(0);
e2bea6df
SC		 1499 return -1;
1500 }
50a0decf 1501 chain_sg->Addr = cpu_to_le64(temp64);
e2bea6df 1502 return 0;
33a2ffce
SC		 1503}
1504
1505static void hpsa_unmap_sg_chain_block(struct ctlr_info *h,
1506 struct CommandList *c)
1507{
1508 struct SGDescriptor *chain_sg;
33a2ffce 1509
50a0decf 1510 if (le16_to_cpu(c->Header.SGTotal) <= h->max_cmd_sg_entries)
33a2ffce
SC		 1511 return;
1512
1513 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
50a0decf
SC		 1514 pci_unmap_single(h->pdev, le64_to_cpu(chain_sg->Addr),
1515 le32_to_cpu(chain_sg->Len), PCI_DMA_TODEVICE);
33a2ffce
SC		 1516}
1517
a09c1441
ST		 1518
1519/* Decode the various types of errors on ioaccel2 path.
1520 * Return 1 for any error that should generate a RAID path retry.
1521 * Return 0 for errors that don't require a RAID path retry.
1522 */
1523static int handle_ioaccel_mode2_error(struct ctlr_info *h,
c349775e
ST		 1524 struct CommandList *c,
1525 struct scsi_cmnd *cmd,
1526 struct io_accel2_cmd *c2)
1527{
1528 int data_len;
a09c1441 1529 int retry = 0;
c349775e
ST		 1530
1531 switch (c2->error_data.serv_response) {
1532 case IOACCEL2_SERV_RESPONSE_COMPLETE:
1533 switch (c2->error_data.status) {
1534 case IOACCEL2_STATUS_SR_TASK_COMP_GOOD:
1535 break;
1536 case IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND:
1537 dev_warn(&h->pdev->dev,
1538 "%s: task complete with check condition.\n",
1539 "HP SSD Smart Path");
ee6b1889 1540 cmd->result |= SAM_STAT_CHECK_CONDITION;
c349775e 1541 if (c2->error_data.data_present !=
ee6b1889
SC		 1542 IOACCEL2_SENSE_DATA_PRESENT) {
1543 memset(cmd->sense_buffer, 0,
1544 SCSI_SENSE_BUFFERSIZE);
c349775e 1545 break;
ee6b1889 1546 }
c349775e
ST		 1547 /* copy the sense data */
1548 data_len = c2->error_data.sense_data_len;
1549 if (data_len > SCSI_SENSE_BUFFERSIZE)
1550 data_len = SCSI_SENSE_BUFFERSIZE;
1551 if (data_len > sizeof(c2->error_data.sense_data_buff))
1552 data_len =
1553 sizeof(c2->error_data.sense_data_buff);
1554 memcpy(cmd->sense_buffer,
1555 c2->error_data.sense_data_buff, data_len);
a09c1441 1556 retry = 1;
c349775e
ST		 1557 break;
1558 case IOACCEL2_STATUS_SR_TASK_COMP_BUSY:
1559 dev_warn(&h->pdev->dev,
1560 "%s: task complete with BUSY status.\n",
1561 "HP SSD Smart Path");
a09c1441 1562 retry = 1;
c349775e
ST		 1563 break;
1564 case IOACCEL2_STATUS_SR_TASK_COMP_RES_CON:
1565 dev_warn(&h->pdev->dev,
1566 "%s: task complete with reservation conflict.\n",
1567 "HP SSD Smart Path");
a09c1441 1568 retry = 1;
c349775e
ST		 1569 break;
1570 case IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL:
1571 /* Make scsi midlayer do unlimited retries */
1572 cmd->result = DID_IMM_RETRY << 16;
1573 break;
1574 case IOACCEL2_STATUS_SR_TASK_COMP_ABORTED:
1575 dev_warn(&h->pdev->dev,
1576 "%s: task complete with aborted status.\n",
1577 "HP SSD Smart Path");
a09c1441 1578 retry = 1;
c349775e
ST		 1579 break;
1580 default:
1581 dev_warn(&h->pdev->dev,
1582 "%s: task complete with unrecognized status: 0x%02x\n",
1583 "HP SSD Smart Path", c2->error_data.status);
a09c1441 1584 retry = 1;
c349775e
ST		 1585 break;
1586 }
1587 break;
1588 case IOACCEL2_SERV_RESPONSE_FAILURE:
1589 /* don't expect to get here. */
1590 dev_warn(&h->pdev->dev,
1591 "unexpected delivery or target failure, status = 0x%02x\n",
1592 c2->error_data.status);
a09c1441 1593 retry = 1;
c349775e
ST		 1594 break;
1595 case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE:
1596 break;
1597 case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS:
1598 break;
1599 case IOACCEL2_SERV_RESPONSE_TMF_REJECTED:
1600 dev_warn(&h->pdev->dev, "task management function rejected.\n");
a09c1441 1601 retry = 1;
c349775e
ST		 1602 break;
1603 case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN:
1604 dev_warn(&h->pdev->dev, "task management function invalid LUN\n");
1605 break;
1606 default:
1607 dev_warn(&h->pdev->dev,
1608 "%s: Unrecognized server response: 0x%02x\n",
a09c1441
ST		 1609 "HP SSD Smart Path",
1610 c2->error_data.serv_response);
1611 retry = 1;
c349775e
ST		 1612 break;
1613 }
a09c1441
ST		 1614
1615 return retry; /* retry on raid path? */
c349775e
ST		 1616}
1617
1618static void process_ioaccel2_completion(struct ctlr_info *h,
1619 struct CommandList *c, struct scsi_cmnd *cmd,
1620 struct hpsa_scsi_dev_t *dev)
1621{
1622 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
1623
1624 /* check for good status */
1625 if (likely(c2->error_data.serv_response == 0 &&
1626 c2->error_data.status == 0)) {
1627 cmd_free(h, c);
1628 cmd->scsi_done(cmd);
1629 return;
1630 }
1631
1632 /* Any RAID offload error results in retry which will use
1633 * the normal I/O path so the controller can handle whatever's
1634 * wrong.
1635 */
1636 if (is_logical_dev_addr_mode(dev->scsi3addr) &&
1637 c2->error_data.serv_response ==
1638 IOACCEL2_SERV_RESPONSE_FAILURE) {
080ef1cc
DB		 1639 if (c2->error_data.status ==
1640 IOACCEL2_STATUS_SR_IOACCEL_DISABLED)
1641 dev->offload_enabled = 0;
1642 goto retry_cmd;
a09c1441 1643 }
080ef1cc
DB		 1644
1645 if (handle_ioaccel_mode2_error(h, c, cmd, c2))
1646 goto retry_cmd;
1647
c349775e
ST		 1648 cmd_free(h, c);
1649 cmd->scsi_done(cmd);
080ef1cc
DB		 1650 return;
1651
1652retry_cmd:
1653 INIT_WORK(&c->work, hpsa_command_resubmit_worker);
1654 queue_work_on(raw_smp_processor_id(), h->resubmit_wq, &c->work);
c349775e
ST		 1655}
1656
1fb011fb 1657static void complete_scsi_command(struct CommandList *cp)
edd16368
SC		 1658{
1659 struct scsi_cmnd *cmd;
1660 struct ctlr_info *h;
1661 struct ErrorInfo *ei;
283b4a9b 1662 struct hpsa_scsi_dev_t *dev;
edd16368
SC		 1663
1664 unsigned char sense_key;
1665 unsigned char asc; /* additional sense code */
1666 unsigned char ascq; /* additional sense code qualifier */
db111e18 1667 unsigned long sense_data_size;
edd16368
SC		 1668
1669 ei = cp->err_info;
1670 cmd = (struct scsi_cmnd *) cp->scsi_cmd;
1671 h = cp->h;
283b4a9b 1672 dev = cmd->device->hostdata;
edd16368
SC		 1673
1674 scsi_dma_unmap(cmd); /* undo the DMA mappings */
e1f7de0c 1675 if ((cp->cmd_type == CMD_SCSI) &&
2b08b3e9 1676 (le16_to_cpu(cp->Header.SGTotal) > h->max_cmd_sg_entries))
33a2ffce 1677 hpsa_unmap_sg_chain_block(h, cp);
edd16368
SC		 1678
1679 cmd->result = (DID_OK << 16); /* host byte */
1680 cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
c349775e
ST		 1681
1682 if (cp->cmd_type == CMD_IOACCEL2)
1683 return process_ioaccel2_completion(h, cp, cmd, dev);
1684
5512672f 1685 cmd->result |= ei->ScsiStatus;
edd16368 1686
6aa4c361
RE		 1687 scsi_set_resid(cmd, ei->ResidualCnt);
1688 if (ei->CommandStatus == 0) {
1689 cmd_free(h, cp);
1690 cmd->scsi_done(cmd);
1691 return;
1692 }
1693
1694 /* copy the sense data */
db111e18
SC		 1695 if (SCSI_SENSE_BUFFERSIZE < sizeof(ei->SenseInfo))
1696 sense_data_size = SCSI_SENSE_BUFFERSIZE;
1697 else
1698 sense_data_size = sizeof(ei->SenseInfo);
1699 if (ei->SenseLen < sense_data_size)
1700 sense_data_size = ei->SenseLen;
1701
1702 memcpy(cmd->sense_buffer, ei->SenseInfo, sense_data_size);
edd16368 1703
e1f7de0c
MG		 1704 /* For I/O accelerator commands, copy over some fields to the normal
1705 * CISS header used below for error handling.
1706 */
1707 if (cp->cmd_type == CMD_IOACCEL1) {
1708 struct io_accel1_cmd *c = &h->ioaccel_cmd_pool[cp->cmdindex];
2b08b3e9
DB		 1709 cp->Header.SGList = scsi_sg_count(cmd);
1710 cp->Header.SGTotal = cpu_to_le16(cp->Header.SGList);
1711 cp->Request.CDBLen = le16_to_cpu(c->io_flags) &
1712 IOACCEL1_IOFLAGS_CDBLEN_MASK;
50a0decf 1713 cp->Header.tag = c->tag;
e1f7de0c
MG		 1714 memcpy(cp->Header.LUN.LunAddrBytes, c->CISS_LUN, 8);
1715 memcpy(cp->Request.CDB, c->CDB, cp->Request.CDBLen);
283b4a9b
SC		 1716
1717 /* Any RAID offload error results in retry which will use
1718 * the normal I/O path so the controller can handle whatever's
1719 * wrong.
1720 */
1721 if (is_logical_dev_addr_mode(dev->scsi3addr)) {
1722 if (ei->CommandStatus == CMD_IOACCEL_DISABLED)
1723 dev->offload_enabled = 0;
080ef1cc
DB		 1724 INIT_WORK(&cp->work, hpsa_command_resubmit_worker);
1725 queue_work_on(raw_smp_processor_id(),
1726 h->resubmit_wq, &cp->work);
283b4a9b
SC		 1727 return;
1728 }
e1f7de0c
MG		 1729 }
1730
edd16368
SC		 1731 /* an error has occurred */
1732 switch (ei->CommandStatus) {
1733
1734 case CMD_TARGET_STATUS:
1735 if (ei->ScsiStatus) {
1736 /* Get sense key */
1737 sense_key = 0xf & ei->SenseInfo[2];
1738 /* Get additional sense code */
1739 asc = ei->SenseInfo[12];
1740 /* Get addition sense code qualifier */
1741 ascq = ei->SenseInfo[13];
1742 }
edd16368 1743 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION) {
1d3b3609 1744 if (sense_key == ABORTED_COMMAND) {
2e311fba 1745 cmd->result |= DID_SOFT_ERROR << 16;
1d3b3609
MG		 1746 break;
1747 }
edd16368
SC		 1748 break;
1749 }
edd16368
SC		 1750 /* Problem was not a check condition
1751 * Pass it up to the upper layers...
1752 */
1753 if (ei->ScsiStatus) {
1754 dev_warn(&h->pdev->dev, "cp %p has status 0x%x "
1755 "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
1756 "Returning result: 0x%x\n",
1757 cp, ei->ScsiStatus,
1758 sense_key, asc, ascq,
1759 cmd->result);
1760 } else { /* scsi status is zero??? How??? */
1761 dev_warn(&h->pdev->dev, "cp %p SCSI status was 0. "
1762 "Returning no connection.\n", cp),
1763
1764 /* Ordinarily, this case should never happen,
1765 * but there is a bug in some released firmware
1766 * revisions that allows it to happen if, for
1767 * example, a 4100 backplane loses power and
1768 * the tape drive is in it. We assume that
1769 * it's a fatal error of some kind because we
1770 * can't show that it wasn't. We will make it
1771 * look like selection timeout since that is
1772 * the most common reason for this to occur,
1773 * and it's severe enough.
1774 */
1775
1776 cmd->result = DID_NO_CONNECT << 16;
1777 }
1778 break;
1779
1780 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
1781 break;
1782 case CMD_DATA_OVERRUN:
1783 dev_warn(&h->pdev->dev, "cp %p has"
1784 " completed with data overrun "
1785 "reported\n", cp);
1786 break;
1787 case CMD_INVALID: {
1788 /* print_bytes(cp, sizeof(*cp), 1, 0);
1789 print_cmd(cp); */
1790 /* We get CMD_INVALID if you address a non-existent device
1791 * instead of a selection timeout (no response). You will
1792 * see this if you yank out a drive, then try to access it.
1793 * This is kind of a shame because it means that any other
1794 * CMD_INVALID (e.g. driver bug) will get interpreted as a
1795 * missing target. */
1796 cmd->result = DID_NO_CONNECT << 16;
1797 }
1798 break;
1799 case CMD_PROTOCOL_ERR:
256d0eaa 1800 cmd->result = DID_ERROR << 16;
edd16368 1801 dev_warn(&h->pdev->dev, "cp %p has "
256d0eaa 1802 "protocol error\n", cp);
edd16368
SC		 1803 break;
1804 case CMD_HARDWARE_ERR:
1805 cmd->result = DID_ERROR << 16;
1806 dev_warn(&h->pdev->dev, "cp %p had hardware error\n", cp);
1807 break;
1808 case CMD_CONNECTION_LOST:
1809 cmd->result = DID_ERROR << 16;
1810 dev_warn(&h->pdev->dev, "cp %p had connection lost\n", cp);
1811 break;
1812 case CMD_ABORTED:
1813 cmd->result = DID_ABORT << 16;
1814 dev_warn(&h->pdev->dev, "cp %p was aborted with status 0x%x\n",
1815 cp, ei->ScsiStatus);
1816 break;
1817 case CMD_ABORT_FAILED:
1818 cmd->result = DID_ERROR << 16;
1819 dev_warn(&h->pdev->dev, "cp %p reports abort failed\n", cp);
1820 break;
1821 case CMD_UNSOLICITED_ABORT:
f6e76055
SC		 1822 cmd->result = DID_SOFT_ERROR << 16; /* retry the command */
1823 dev_warn(&h->pdev->dev, "cp %p aborted due to an unsolicited "
edd16368
SC		 1824 "abort\n", cp);
1825 break;
1826 case CMD_TIMEOUT:
1827 cmd->result = DID_TIME_OUT << 16;
1828 dev_warn(&h->pdev->dev, "cp %p timedout\n", cp);
1829 break;
1d5e2ed0
SC		 1830 case CMD_UNABORTABLE:
1831 cmd->result = DID_ERROR << 16;
1832 dev_warn(&h->pdev->dev, "Command unabortable\n");
1833 break;
283b4a9b
SC		 1834 case CMD_IOACCEL_DISABLED:
1835 /* This only handles the direct pass-through case since RAID
1836 * offload is handled above. Just attempt a retry.
1837 */
1838 cmd->result = DID_SOFT_ERROR << 16;
1839 dev_warn(&h->pdev->dev,
1840 "cp %p had HP SSD Smart Path error\n", cp);
1841 break;
edd16368
SC		 1842 default:
1843 cmd->result = DID_ERROR << 16;
1844 dev_warn(&h->pdev->dev, "cp %p returned unknown status %x\n",
1845 cp, ei->CommandStatus);
1846 }
edd16368 1847 cmd_free(h, cp);
2cc5bfaf 1848 cmd->scsi_done(cmd);
edd16368
SC		 1849}
1850
edd16368
SC		 1851static void hpsa_pci_unmap(struct pci_dev *pdev,
1852 struct CommandList *c, int sg_used, int data_direction)
1853{
1854 int i;
edd16368 1855
50a0decf
SC		 1856 for (i = 0; i < sg_used; i++)
1857 pci_unmap_single(pdev, (dma_addr_t) le64_to_cpu(c->SG[i].Addr),
1858 le32_to_cpu(c->SG[i].Len),
1859 data_direction);
edd16368
SC		 1860}
1861
a2dac136 1862static int hpsa_map_one(struct pci_dev *pdev,
edd16368
SC		 1863 struct CommandList *cp,
1864 unsigned char *buf,
1865 size_t buflen,
1866 int data_direction)
1867{
01a02ffc 1868 u64 addr64;
edd16368
SC		 1869
1870 if (buflen == 0 || data_direction == PCI_DMA_NONE) {
1871 cp->Header.SGList = 0;
50a0decf 1872 cp->Header.SGTotal = cpu_to_le16(0);
a2dac136 1873 return 0;
edd16368
SC		 1874 }
1875
50a0decf 1876 addr64 = pci_map_single(pdev, buf, buflen, data_direction);
eceaae18 1877 if (dma_mapping_error(&pdev->dev, addr64)) {
a2dac136 1878 /* Prevent subsequent unmap of something never mapped */
eceaae18 1879 cp->Header.SGList = 0;
50a0decf 1880 cp->Header.SGTotal = cpu_to_le16(0);
a2dac136 1881 return -1;
eceaae18 1882 }
50a0decf
SC		 1883 cp->SG[0].Addr = cpu_to_le64(addr64);
1884 cp->SG[0].Len = cpu_to_le32(buflen);
1885 cp->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* we are not chaining */
1886 cp->Header.SGList = 1; /* no. SGs contig in this cmd */
1887 cp->Header.SGTotal = cpu_to_le16(1); /* total sgs in cmd list */
a2dac136 1888 return 0;
edd16368
SC		 1889}
1890
1891static inline void hpsa_scsi_do_simple_cmd_core(struct ctlr_info *h,
1892 struct CommandList *c)
1893{
1894 DECLARE_COMPLETION_ONSTACK(wait);
1895
1896 c->waiting = &wait;
1897 enqueue_cmd_and_start_io(h, c);
1898 wait_for_completion(&wait);
1899}
1900
094963da
SC		 1901static u32 lockup_detected(struct ctlr_info *h)
1902{
1903 int cpu;
1904 u32 rc, *lockup_detected;
1905
1906 cpu = get_cpu();
1907 lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
1908 rc = *lockup_detected;
1909 put_cpu();
1910 return rc;
1911}
1912
a0c12413
SC		 1913static void hpsa_scsi_do_simple_cmd_core_if_no_lockup(struct ctlr_info *h,
1914 struct CommandList *c)
1915{
a0c12413 1916 /* If controller lockup detected, fake a hardware error. */
094963da 1917 if (unlikely(lockup_detected(h)))
a0c12413 1918 c->err_info->CommandStatus = CMD_HARDWARE_ERR;
094963da 1919 else
a0c12413 1920 hpsa_scsi_do_simple_cmd_core(h, c);
a0c12413
SC		 1921}
1922
9c2fc160 1923#define MAX_DRIVER_CMD_RETRIES 25
edd16368
SC		 1924static void hpsa_scsi_do_simple_cmd_with_retry(struct ctlr_info *h,
1925 struct CommandList *c, int data_direction)
1926{
9c2fc160 1927 int backoff_time = 10, retry_count = 0;
edd16368
SC		 1928
1929 do {
7630abd0 1930 memset(c->err_info, 0, sizeof(*c->err_info));
edd16368
SC		 1931 hpsa_scsi_do_simple_cmd_core(h, c);
1932 retry_count++;
9c2fc160
SC		 1933 if (retry_count > 3) {
1934 msleep(backoff_time);
1935 if (backoff_time < 1000)
1936 backoff_time *= 2;
1937 }
852af20a 1938 } while ((check_for_unit_attention(h, c) ||
9c2fc160
SC		 1939 check_for_busy(h, c)) &&
1940 retry_count <= MAX_DRIVER_CMD_RETRIES);
edd16368
SC		 1941 hpsa_pci_unmap(h->pdev, c, 1, data_direction);
1942}
1943
d1e8beac
SC		 1944static void hpsa_print_cmd(struct ctlr_info *h, char *txt,
1945 struct CommandList *c)
edd16368 1946{
d1e8beac
SC		 1947 const u8 *cdb = c->Request.CDB;
1948 const u8 *lun = c->Header.LUN.LunAddrBytes;
1949
1950 dev_warn(&h->pdev->dev, "%s: LUN:%02x%02x%02x%02x%02x%02x%02x%02x"
1951 " CDB:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\n",
1952 txt, lun[0], lun[1], lun[2], lun[3],
1953 lun[4], lun[5], lun[6], lun[7],
1954 cdb[0], cdb[1], cdb[2], cdb[3],
1955 cdb[4], cdb[5], cdb[6], cdb[7],
1956 cdb[8], cdb[9], cdb[10], cdb[11],
1957 cdb[12], cdb[13], cdb[14], cdb[15]);
1958}
1959
1960static void hpsa_scsi_interpret_error(struct ctlr_info *h,
1961 struct CommandList *cp)
1962{
1963 const struct ErrorInfo *ei = cp->err_info;
edd16368 1964 struct device *d = &cp->h->pdev->dev;
d1e8beac 1965 const u8 *sd = ei->SenseInfo;
edd16368 1966
edd16368
SC		 1967 switch (ei->CommandStatus) {
1968 case CMD_TARGET_STATUS:
d1e8beac
SC		 1969 hpsa_print_cmd(h, "SCSI status", cp);
1970 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION)
1971 dev_warn(d, "SCSI Status = 02, Sense key = %02x, ASC = %02x, ASCQ = %02x\n",
1972 sd[2] & 0x0f, sd[12], sd[13]);
1973 else
1974 dev_warn(d, "SCSI Status = %02x\n", ei->ScsiStatus);
edd16368
SC		 1975 if (ei->ScsiStatus == 0)
1976 dev_warn(d, "SCSI status is abnormally zero. "
1977 "(probably indicates selection timeout "
1978 "reported incorrectly due to a known "
1979 "firmware bug, circa July, 2001.)\n");
1980 break;
1981 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
edd16368
SC		 1982 break;
1983 case CMD_DATA_OVERRUN:
d1e8beac 1984 hpsa_print_cmd(h, "overrun condition", cp);
edd16368
SC		 1985 break;
1986 case CMD_INVALID: {
1987 /* controller unfortunately reports SCSI passthru's
1988 * to non-existent targets as invalid commands.
1989 */
d1e8beac
SC		 1990 hpsa_print_cmd(h, "invalid command", cp);
1991 dev_warn(d, "probably means device no longer present\n");
edd16368
SC		 1992 }
1993 break;
1994 case CMD_PROTOCOL_ERR:
d1e8beac 1995 hpsa_print_cmd(h, "protocol error", cp);
edd16368
SC		 1996 break;
1997 case CMD_HARDWARE_ERR:
d1e8beac 1998 hpsa_print_cmd(h, "hardware error", cp);
edd16368
SC		 1999 break;
2000 case CMD_CONNECTION_LOST:
d1e8beac 2001 hpsa_print_cmd(h, "connection lost", cp);
edd16368
SC		 2002 break;
2003 case CMD_ABORTED:
d1e8beac 2004 hpsa_print_cmd(h, "aborted", cp);
edd16368
SC		 2005 break;
2006 case CMD_ABORT_FAILED:
d1e8beac 2007 hpsa_print_cmd(h, "abort failed", cp);
edd16368
SC		 2008 break;
2009 case CMD_UNSOLICITED_ABORT:
d1e8beac 2010 hpsa_print_cmd(h, "unsolicited abort", cp);
edd16368
SC		 2011 break;
2012 case CMD_TIMEOUT:
d1e8beac 2013 hpsa_print_cmd(h, "timed out", cp);
edd16368 2014 break;
1d5e2ed0 2015 case CMD_UNABORTABLE:
d1e8beac 2016 hpsa_print_cmd(h, "unabortable", cp);
1d5e2ed0 2017 break;
edd16368 2018 default:
d1e8beac
SC		 2019 hpsa_print_cmd(h, "unknown status", cp);
2020 dev_warn(d, "Unknown command status %x\n",
edd16368
SC		 2021 ei->CommandStatus);
2022 }
2023}
2024
2025static int hpsa_scsi_do_inquiry(struct ctlr_info *h, unsigned char *scsi3addr,
b7bb24eb 2026 u16 page, unsigned char *buf,
edd16368
SC		 2027 unsigned char bufsize)
2028{
2029 int rc = IO_OK;
2030 struct CommandList *c;
2031 struct ErrorInfo *ei;
2032
45fcb86e 2033 c = cmd_alloc(h);
edd16368 2034
574f05d3 2035 if (c == NULL) {
45fcb86e 2036 dev_warn(&h->pdev->dev, "cmd_alloc returned NULL!\n");
ecd9aad4 2037 return -ENOMEM;
edd16368
SC		 2038 }
2039
a2dac136
SC		 2040 if (fill_cmd(c, HPSA_INQUIRY, h, buf, bufsize,
2041 page, scsi3addr, TYPE_CMD)) {
2042 rc = -1;
2043 goto out;
2044 }
edd16368
SC		 2045 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
2046 ei = c->err_info;
2047 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2048 hpsa_scsi_interpret_error(h, c);
edd16368
SC		 2049 rc = -1;
2050 }
a2dac136 2051out:
45fcb86e 2052 cmd_free(h, c);
edd16368
SC		 2053 return rc;
2054}
2055
316b221a
SC		 2056static int hpsa_bmic_ctrl_mode_sense(struct ctlr_info *h,
2057 unsigned char *scsi3addr, unsigned char page,
2058 struct bmic_controller_parameters *buf, size_t bufsize)
2059{
2060 int rc = IO_OK;
2061 struct CommandList *c;
2062 struct ErrorInfo *ei;
2063
45fcb86e 2064 c = cmd_alloc(h);
316b221a 2065 if (c == NULL) { /* trouble... */
45fcb86e 2066 dev_warn(&h->pdev->dev, "cmd_alloc returned NULL!\n");
316b221a
SC		 2067 return -ENOMEM;
2068 }
2069
2070 if (fill_cmd(c, BMIC_SENSE_CONTROLLER_PARAMETERS, h, buf, bufsize,
2071 page, scsi3addr, TYPE_CMD)) {
2072 rc = -1;
2073 goto out;
2074 }
2075 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
2076 ei = c->err_info;
2077 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
2078 hpsa_scsi_interpret_error(h, c);
2079 rc = -1;
2080 }
2081out:
45fcb86e 2082 cmd_free(h, c);
316b221a
SC		 2083 return rc;
2084 }
2085
bf711ac6
ST		 2086static int hpsa_send_reset(struct ctlr_info *h, unsigned char *scsi3addr,
2087 u8 reset_type)
edd16368
SC		 2088{
2089 int rc = IO_OK;
2090 struct CommandList *c;
2091 struct ErrorInfo *ei;
2092
45fcb86e 2093 c = cmd_alloc(h);
edd16368
SC		 2094
2095 if (c == NULL) { /* trouble... */
45fcb86e 2096 dev_warn(&h->pdev->dev, "cmd_alloc returned NULL!\n");
e9ea04a6 2097 return -ENOMEM;
edd16368
SC		 2098 }
2099
a2dac136 2100 /* fill_cmd can't fail here, no data buffer to map. */
bf711ac6
ST		 2101 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
2102 scsi3addr, TYPE_MSG);
2103 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to LUN reset */
edd16368
SC		 2104 hpsa_scsi_do_simple_cmd_core(h, c);
2105 /* no unmap needed here because no data xfer. */
2106
2107 ei = c->err_info;
2108 if (ei->CommandStatus != 0) {
d1e8beac 2109 hpsa_scsi_interpret_error(h, c);
edd16368
SC		 2110 rc = -1;
2111 }
45fcb86e 2112 cmd_free(h, c);
edd16368
SC		 2113 return rc;
2114}
2115
2116static void hpsa_get_raid_level(struct ctlr_info *h,
2117 unsigned char *scsi3addr, unsigned char *raid_level)
2118{
2119 int rc;
2120 unsigned char *buf;
2121
2122 *raid_level = RAID_UNKNOWN;
2123 buf = kzalloc(64, GFP_KERNEL);
2124 if (!buf)
2125 return;
b7bb24eb 2126 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0xC1, buf, 64);
edd16368
SC		 2127 if (rc == 0)
2128 *raid_level = buf[8];
2129 if (*raid_level > RAID_UNKNOWN)
2130 *raid_level = RAID_UNKNOWN;
2131 kfree(buf);
2132 return;
2133}
2134
283b4a9b
SC		 2135#define HPSA_MAP_DEBUG
2136#ifdef HPSA_MAP_DEBUG
2137static void hpsa_debug_map_buff(struct ctlr_info *h, int rc,
2138 struct raid_map_data *map_buff)
2139{
2140 struct raid_map_disk_data *dd = &map_buff->data[0];
2141 int map, row, col;
2142 u16 map_cnt, row_cnt, disks_per_row;
2143
2144 if (rc != 0)
2145 return;
2146
2ba8bfc8
SC		 2147 /* Show details only if debugging has been activated. */
2148 if (h->raid_offload_debug < 2)
2149 return;
2150
283b4a9b
SC		 2151 dev_info(&h->pdev->dev, "structure_size = %u\n",
2152 le32_to_cpu(map_buff->structure_size));
2153 dev_info(&h->pdev->dev, "volume_blk_size = %u\n",
2154 le32_to_cpu(map_buff->volume_blk_size));
2155 dev_info(&h->pdev->dev, "volume_blk_cnt = 0x%llx\n",
2156 le64_to_cpu(map_buff->volume_blk_cnt));
2157 dev_info(&h->pdev->dev, "physicalBlockShift = %u\n",
2158 map_buff->phys_blk_shift);
2159 dev_info(&h->pdev->dev, "parity_rotation_shift = %u\n",
2160 map_buff->parity_rotation_shift);
2161 dev_info(&h->pdev->dev, "strip_size = %u\n",
2162 le16_to_cpu(map_buff->strip_size));
2163 dev_info(&h->pdev->dev, "disk_starting_blk = 0x%llx\n",
2164 le64_to_cpu(map_buff->disk_starting_blk));
2165 dev_info(&h->pdev->dev, "disk_blk_cnt = 0x%llx\n",
2166 le64_to_cpu(map_buff->disk_blk_cnt));
2167 dev_info(&h->pdev->dev, "data_disks_per_row = %u\n",
2168 le16_to_cpu(map_buff->data_disks_per_row));
2169 dev_info(&h->pdev->dev, "metadata_disks_per_row = %u\n",
2170 le16_to_cpu(map_buff->metadata_disks_per_row));
2171 dev_info(&h->pdev->dev, "row_cnt = %u\n",
2172 le16_to_cpu(map_buff->row_cnt));
2173 dev_info(&h->pdev->dev, "layout_map_count = %u\n",
2174 le16_to_cpu(map_buff->layout_map_count));
2b08b3e9 2175 dev_info(&h->pdev->dev, "flags = 0x%x\n",
dd0e19f3 2176 le16_to_cpu(map_buff->flags));
2b08b3e9
DB		 2177 dev_info(&h->pdev->dev, "encrypytion = %s\n",
2178 le16_to_cpu(map_buff->flags) &
2179 RAID_MAP_FLAG_ENCRYPT_ON ? "ON" : "OFF");
dd0e19f3
ST		 2180 dev_info(&h->pdev->dev, "dekindex = %u\n",
2181 le16_to_cpu(map_buff->dekindex));
283b4a9b
SC		 2182 map_cnt = le16_to_cpu(map_buff->layout_map_count);
2183 for (map = 0; map < map_cnt; map++) {
2184 dev_info(&h->pdev->dev, "Map%u:\n", map);
2185 row_cnt = le16_to_cpu(map_buff->row_cnt);
2186 for (row = 0; row < row_cnt; row++) {
2187 dev_info(&h->pdev->dev, " Row%u:\n", row);
2188 disks_per_row =
2189 le16_to_cpu(map_buff->data_disks_per_row);
2190 for (col = 0; col < disks_per_row; col++, dd++)
2191 dev_info(&h->pdev->dev,
2192 " D%02u: h=0x%04x xor=%u,%u\n",
2193 col, dd->ioaccel_handle,
2194 dd->xor_mult[0], dd->xor_mult[1]);
2195 disks_per_row =
2196 le16_to_cpu(map_buff->metadata_disks_per_row);
2197 for (col = 0; col < disks_per_row; col++, dd++)
2198 dev_info(&h->pdev->dev,
2199 " M%02u: h=0x%04x xor=%u,%u\n",
2200 col, dd->ioaccel_handle,
2201 dd->xor_mult[0], dd->xor_mult[1]);
2202 }
2203 }
2204}
2205#else
2206static void hpsa_debug_map_buff(__attribute__((unused)) struct ctlr_info *h,
2207 __attribute__((unused)) int rc,
2208 __attribute__((unused)) struct raid_map_data *map_buff)
2209{
2210}
2211#endif
2212
2213static int hpsa_get_raid_map(struct ctlr_info *h,
2214 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
2215{
2216 int rc = 0;
2217 struct CommandList *c;
2218 struct ErrorInfo *ei;
2219
45fcb86e 2220 c = cmd_alloc(h);
283b4a9b 2221 if (c == NULL) {
45fcb86e 2222 dev_warn(&h->pdev->dev, "cmd_alloc returned NULL!\n");
283b4a9b
SC		 2223 return -ENOMEM;
2224 }
2225 if (fill_cmd(c, HPSA_GET_RAID_MAP, h, &this_device->raid_map,
2226 sizeof(this_device->raid_map), 0,
2227 scsi3addr, TYPE_CMD)) {
2228 dev_warn(&h->pdev->dev, "Out of memory in hpsa_get_raid_map()\n");
45fcb86e 2229 cmd_free(h, c);
283b4a9b
SC		 2230 return -ENOMEM;
2231 }
2232 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
2233 ei = c->err_info;
2234 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2235 hpsa_scsi_interpret_error(h, c);
45fcb86e 2236 cmd_free(h, c);
283b4a9b
SC		 2237 return -1;
2238 }
45fcb86e 2239 cmd_free(h, c);
283b4a9b
SC		 2240
2241 /* @todo in the future, dynamically allocate RAID map memory */
2242 if (le32_to_cpu(this_device->raid_map.structure_size) >
2243 sizeof(this_device->raid_map)) {
2244 dev_warn(&h->pdev->dev, "RAID map size is too large!\n");
2245 rc = -1;
2246 }
2247 hpsa_debug_map_buff(h, rc, &this_device->raid_map);
2248 return rc;
2249}
2250
1b70150a
SC		 2251static int hpsa_vpd_page_supported(struct ctlr_info *h,
2252 unsigned char scsi3addr[], u8 page)
2253{
2254 int rc;
2255 int i;
2256 int pages;
2257 unsigned char *buf, bufsize;
2258
2259 buf = kzalloc(256, GFP_KERNEL);
2260 if (!buf)
2261 return 0;
2262
2263 /* Get the size of the page list first */
2264 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
2265 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
2266 buf, HPSA_VPD_HEADER_SZ);
2267 if (rc != 0)
2268 goto exit_unsupported;
2269 pages = buf[3];
2270 if ((pages + HPSA_VPD_HEADER_SZ) <= 255)
2271 bufsize = pages + HPSA_VPD_HEADER_SZ;
2272 else
2273 bufsize = 255;
2274
2275 /* Get the whole VPD page list */
2276 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
2277 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
2278 buf, bufsize);
2279 if (rc != 0)
2280 goto exit_unsupported;
2281
2282 pages = buf[3];
2283 for (i = 1; i <= pages; i++)
2284 if (buf[3 + i] == page)
2285 goto exit_supported;
2286exit_unsupported:
2287 kfree(buf);
2288 return 0;
2289exit_supported:
2290 kfree(buf);
2291 return 1;
2292}
2293
283b4a9b
SC		 2294static void hpsa_get_ioaccel_status(struct ctlr_info *h,
2295 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
2296{
2297 int rc;
2298 unsigned char *buf;
2299 u8 ioaccel_status;
2300
2301 this_device->offload_config = 0;
2302 this_device->offload_enabled = 0;
2303
2304 buf = kzalloc(64, GFP_KERNEL);
2305 if (!buf)
2306 return;
1b70150a
SC		 2307 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_IOACCEL_STATUS))
2308 goto out;
283b4a9b 2309 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
b7bb24eb 2310 VPD_PAGE | HPSA_VPD_LV_IOACCEL_STATUS, buf, 64);
283b4a9b
SC		 2311 if (rc != 0)
2312 goto out;
2313
2314#define IOACCEL_STATUS_BYTE 4
2315#define OFFLOAD_CONFIGURED_BIT 0x01
2316#define OFFLOAD_ENABLED_BIT 0x02
2317 ioaccel_status = buf[IOACCEL_STATUS_BYTE];
2318 this_device->offload_config =
2319 !!(ioaccel_status & OFFLOAD_CONFIGURED_BIT);
2320 if (this_device->offload_config) {
2321 this_device->offload_enabled =
2322 !!(ioaccel_status & OFFLOAD_ENABLED_BIT);
2323 if (hpsa_get_raid_map(h, scsi3addr, this_device))
2324 this_device->offload_enabled = 0;
2325 }
2326out:
2327 kfree(buf);
2328 return;
2329}
2330
edd16368
SC		 2331/* Get the device id from inquiry page 0x83 */
2332static int hpsa_get_device_id(struct ctlr_info *h, unsigned char *scsi3addr,
2333 unsigned char *device_id, int buflen)
2334{
2335 int rc;
2336 unsigned char *buf;
2337
2338 if (buflen > 16)
2339 buflen = 16;
2340 buf = kzalloc(64, GFP_KERNEL);
2341 if (!buf)
a84d794d 2342 return -ENOMEM;
b7bb24eb 2343 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0x83, buf, 64);
edd16368
SC		 2344 if (rc == 0)
2345 memcpy(device_id, &buf[8], buflen);
2346 kfree(buf);
2347 return rc != 0;
2348}
2349
2350static int hpsa_scsi_do_report_luns(struct ctlr_info *h, int logical,
2351 struct ReportLUNdata *buf, int bufsize,
2352 int extended_response)
2353{
2354 int rc = IO_OK;
2355 struct CommandList *c;
2356 unsigned char scsi3addr[8];
2357 struct ErrorInfo *ei;
2358
45fcb86e 2359 c = cmd_alloc(h);
edd16368 2360 if (c == NULL) { /* trouble... */
45fcb86e 2361 dev_err(&h->pdev->dev, "cmd_alloc returned NULL!\n");
edd16368
SC		 2362 return -1;
2363 }
e89c0ae7
SC		 2364 /* address the controller */
2365 memset(scsi3addr, 0, sizeof(scsi3addr));
a2dac136
SC		 2366 if (fill_cmd(c, logical ? HPSA_REPORT_LOG : HPSA_REPORT_PHYS, h,
2367 buf, bufsize, 0, scsi3addr, TYPE_CMD)) {
2368 rc = -1;
2369 goto out;
2370 }
edd16368
SC		 2371 if (extended_response)
2372 c->Request.CDB[1] = extended_response;
2373 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
2374 ei = c->err_info;
2375 if (ei->CommandStatus != 0 &&
2376 ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2377 hpsa_scsi_interpret_error(h, c);
edd16368 2378 rc = -1;
283b4a9b
SC		 2379 } else {
2380 if (buf->extended_response_flag != extended_response) {
2381 dev_err(&h->pdev->dev,
2382 "report luns requested format %u, got %u\n",
2383 extended_response,
2384 buf->extended_response_flag);
2385 rc = -1;
2386 }
edd16368 2387 }
a2dac136 2388out:
45fcb86e 2389 cmd_free(h, c);
edd16368
SC		 2390 return rc;
2391}
2392
2393static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h,
2394 struct ReportLUNdata *buf,
2395 int bufsize, int extended_response)
2396{
2397 return hpsa_scsi_do_report_luns(h, 0, buf, bufsize, extended_response);
2398}
2399
2400static inline int hpsa_scsi_do_report_log_luns(struct ctlr_info *h,
2401 struct ReportLUNdata *buf, int bufsize)
2402{
2403 return hpsa_scsi_do_report_luns(h, 1, buf, bufsize, 0);
2404}
2405
2406static inline void hpsa_set_bus_target_lun(struct hpsa_scsi_dev_t *device,
2407 int bus, int target, int lun)
2408{
2409 device->bus = bus;
2410 device->target = target;
2411 device->lun = lun;
2412}
2413
9846590e
SC		 2414/* Use VPD inquiry to get details of volume status */
2415static int hpsa_get_volume_status(struct ctlr_info *h,
2416 unsigned char scsi3addr[])
2417{
2418 int rc;
2419 int status;
2420 int size;
2421 unsigned char *buf;
2422
2423 buf = kzalloc(64, GFP_KERNEL);
2424 if (!buf)
2425 return HPSA_VPD_LV_STATUS_UNSUPPORTED;
2426
2427 /* Does controller have VPD for logical volume status? */
24a4b078 2428 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_STATUS))
9846590e 2429 goto exit_failed;
9846590e
SC		 2430
2431 /* Get the size of the VPD return buffer */
2432 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
2433 buf, HPSA_VPD_HEADER_SZ);
24a4b078 2434 if (rc != 0)
9846590e 2435 goto exit_failed;
9846590e
SC		 2436 size = buf[3];
2437
2438 /* Now get the whole VPD buffer */
2439 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
2440 buf, size + HPSA_VPD_HEADER_SZ);
24a4b078 2441 if (rc != 0)
9846590e 2442 goto exit_failed;
9846590e
SC		 2443 status = buf[4]; /* status byte */
2444
2445 kfree(buf);
2446 return status;
2447exit_failed:
2448 kfree(buf);
2449 return HPSA_VPD_LV_STATUS_UNSUPPORTED;
2450}
2451
2452/* Determine offline status of a volume.
2453 * Return either:
2454 * 0 (not offline)
67955ba3 2455 * 0xff (offline for unknown reasons)
9846590e
SC		 2456 * # (integer code indicating one of several NOT READY states
2457 * describing why a volume is to be kept offline)
2458 */
67955ba3 2459static int hpsa_volume_offline(struct ctlr_info *h,
9846590e
SC		 2460 unsigned char scsi3addr[])
2461{
2462 struct CommandList *c;
2463 unsigned char *sense, sense_key, asc, ascq;
2464 int ldstat = 0;
2465 u16 cmd_status;
2466 u8 scsi_status;
2467#define ASC_LUN_NOT_READY 0x04
2468#define ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS 0x04
2469#define ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ 0x02
2470
2471 c = cmd_alloc(h);
2472 if (!c)
2473 return 0;
2474 (void) fill_cmd(c, TEST_UNIT_READY, h, NULL, 0, 0, scsi3addr, TYPE_CMD);
2475 hpsa_scsi_do_simple_cmd_core(h, c);
2476 sense = c->err_info->SenseInfo;
2477 sense_key = sense[2];
2478 asc = sense[12];
2479 ascq = sense[13];
2480 cmd_status = c->err_info->CommandStatus;
2481 scsi_status = c->err_info->ScsiStatus;
2482 cmd_free(h, c);
2483 /* Is the volume 'not ready'? */
2484 if (cmd_status != CMD_TARGET_STATUS ||
2485 scsi_status != SAM_STAT_CHECK_CONDITION ||
2486 sense_key != NOT_READY ||
2487 asc != ASC_LUN_NOT_READY) {
2488 return 0;
2489 }
2490
2491 /* Determine the reason for not ready state */
2492 ldstat = hpsa_get_volume_status(h, scsi3addr);
2493
2494 /* Keep volume offline in certain cases: */
2495 switch (ldstat) {
2496 case HPSA_LV_UNDERGOING_ERASE:
2497 case HPSA_LV_UNDERGOING_RPI:
2498 case HPSA_LV_PENDING_RPI:
2499 case HPSA_LV_ENCRYPTED_NO_KEY:
2500 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
2501 case HPSA_LV_UNDERGOING_ENCRYPTION:
2502 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
2503 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
2504 return ldstat;
2505 case HPSA_VPD_LV_STATUS_UNSUPPORTED:
2506 /* If VPD status page isn't available,
2507 * use ASC/ASCQ to determine state
2508 */
2509 if ((ascq == ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS) ||
2510 (ascq == ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ))
2511 return ldstat;
2512 break;
2513 default:
2514 break;
2515 }
2516 return 0;
2517}
2518
edd16368 2519static int hpsa_update_device_info(struct ctlr_info *h,
0b0e1d6c
SC		 2520 unsigned char scsi3addr[], struct hpsa_scsi_dev_t *this_device,
2521 unsigned char *is_OBDR_device)
edd16368 2522{
0b0e1d6c
SC		 2523
2524#define OBDR_SIG_OFFSET 43
2525#define OBDR_TAPE_SIG "$DR-10"
2526#define OBDR_SIG_LEN (sizeof(OBDR_TAPE_SIG) - 1)
2527#define OBDR_TAPE_INQ_SIZE (OBDR_SIG_OFFSET + OBDR_SIG_LEN)
2528
ea6d3bc3 2529 unsigned char *inq_buff;
0b0e1d6c 2530 unsigned char *obdr_sig;
edd16368 2531
ea6d3bc3 2532 inq_buff = kzalloc(OBDR_TAPE_INQ_SIZE, GFP_KERNEL);
edd16368
SC		 2533 if (!inq_buff)
2534 goto bail_out;
2535
edd16368
SC		 2536 /* Do an inquiry to the device to see what it is. */
2537 if (hpsa_scsi_do_inquiry(h, scsi3addr, 0, inq_buff,
2538 (unsigned char) OBDR_TAPE_INQ_SIZE) != 0) {
2539 /* Inquiry failed (msg printed already) */
2540 dev_err(&h->pdev->dev,
2541 "hpsa_update_device_info: inquiry failed\n");
2542 goto bail_out;
2543 }
2544
edd16368
SC		 2545 this_device->devtype = (inq_buff[0] & 0x1f);
2546 memcpy(this_device->scsi3addr, scsi3addr, 8);
2547 memcpy(this_device->vendor, &inq_buff[8],
2548 sizeof(this_device->vendor));
2549 memcpy(this_device->model, &inq_buff[16],
2550 sizeof(this_device->model));
edd16368
SC		 2551 memset(this_device->device_id, 0,
2552 sizeof(this_device->device_id));
2553 hpsa_get_device_id(h, scsi3addr, this_device->device_id,
2554 sizeof(this_device->device_id));
2555
2556 if (this_device->devtype == TYPE_DISK &&
283b4a9b 2557 is_logical_dev_addr_mode(scsi3addr)) {
67955ba3
SC		 2558 int volume_offline;
2559
edd16368 2560 hpsa_get_raid_level(h, scsi3addr, &this_device->raid_level);
283b4a9b
SC		 2561 if (h->fw_support & MISC_FW_RAID_OFFLOAD_BASIC)
2562 hpsa_get_ioaccel_status(h, scsi3addr, this_device);
67955ba3
SC		 2563 volume_offline = hpsa_volume_offline(h, scsi3addr);
2564 if (volume_offline < 0 || volume_offline > 0xff)
2565 volume_offline = HPSA_VPD_LV_STATUS_UNSUPPORTED;
2566 this_device->volume_offline = volume_offline & 0xff;
283b4a9b 2567 } else {
edd16368 2568 this_device->raid_level = RAID_UNKNOWN;
283b4a9b
SC		 2569 this_device->offload_config = 0;
2570 this_device->offload_enabled = 0;
9846590e 2571 this_device->volume_offline = 0;
283b4a9b 2572 }
edd16368 2573
0b0e1d6c
SC		 2574 if (is_OBDR_device) {
2575 /* See if this is a One-Button-Disaster-Recovery device
2576 * by looking for "$DR-10" at offset 43 in inquiry data.
2577 */
2578 obdr_sig = &inq_buff[OBDR_SIG_OFFSET];
2579 *is_OBDR_device = (this_device->devtype == TYPE_ROM &&
2580 strncmp(obdr_sig, OBDR_TAPE_SIG,
2581 OBDR_SIG_LEN) == 0);
2582 }
2583
edd16368
SC		 2584 kfree(inq_buff);
2585 return 0;
2586
2587bail_out:
2588 kfree(inq_buff);
2589 return 1;
2590}
2591
4f4eb9f1 2592static unsigned char *ext_target_model[] = {
edd16368
SC		 2593 "MSA2012",
2594 "MSA2024",
2595 "MSA2312",
2596 "MSA2324",
fda38518 2597 "P2000 G3 SAS",
e06c8e5c 2598 "MSA 2040 SAS",
edd16368
SC		 2599 NULL,
2600};
2601
4f4eb9f1 2602static int is_ext_target(struct ctlr_info *h, struct hpsa_scsi_dev_t *device)
edd16368
SC		 2603{
2604 int i;
2605
4f4eb9f1
ST		 2606 for (i = 0; ext_target_model[i]; i++)
2607 if (strncmp(device->model, ext_target_model[i],
2608 strlen(ext_target_model[i])) == 0)
edd16368
SC		 2609 return 1;
2610 return 0;
2611}
2612
2613/* Helper function to assign bus, target, lun mapping of devices.
4f4eb9f1 2614 * Puts non-external target logical volumes on bus 0, external target logical
edd16368
SC		 2615 * volumes on bus 1, physical devices on bus 2. and the hba on bus 3.
2616 * Logical drive target and lun are assigned at this time, but
2617 * physical device lun and target assignment are deferred (assigned
2618 * in hpsa_find_target_lun, called by hpsa_scsi_add_entry.)
2619 */
2620static void figure_bus_target_lun(struct ctlr_info *h,
1f310bde 2621 u8 *lunaddrbytes, struct hpsa_scsi_dev_t *device)
edd16368 2622{
1f310bde
SC		 2623 u32 lunid = le32_to_cpu(*((__le32 *) lunaddrbytes));
2624
2625 if (!is_logical_dev_addr_mode(lunaddrbytes)) {
2626 /* physical device, target and lun filled in later */
edd16368 2627 if (is_hba_lunid(lunaddrbytes))
1f310bde 2628 hpsa_set_bus_target_lun(device, 3, 0, lunid & 0x3fff);
edd16368 2629 else
1f310bde
SC		 2630 /* defer target, lun assignment for physical devices */
2631 hpsa_set_bus_target_lun(device, 2, -1, -1);
2632 return;
2633 }
2634 /* It's a logical device */
4f4eb9f1
ST		 2635 if (is_ext_target(h, device)) {
2636 /* external target way, put logicals on bus 1
1f310bde
SC		 2637 * and match target/lun numbers box
2638 * reports, other smart array, bus 0, target 0, match lunid
2639 */
2640 hpsa_set_bus_target_lun(device,
2641 1, (lunid >> 16) & 0x3fff, lunid & 0x00ff);
2642 return;
edd16368 2643 }
1f310bde 2644 hpsa_set_bus_target_lun(device, 0, 0, lunid & 0x3fff);
edd16368
SC		 2645}
2646
2647/*
2648 * If there is no lun 0 on a target, linux won't find any devices.
4f4eb9f1 2649 * For the external targets (arrays), we have to manually detect the enclosure
edd16368
SC		 2650 * which is at lun zero, as CCISS_REPORT_PHYSICAL_LUNS doesn't report
2651 * it for some reason. *tmpdevice is the target we're adding,
2652 * this_device is a pointer into the current element of currentsd[]
2653 * that we're building up in update_scsi_devices(), below.
2654 * lunzerobits is a bitmap that tracks which targets already have a
2655 * lun 0 assigned.
2656 * Returns 1 if an enclosure was added, 0 if not.
2657 */
4f4eb9f1 2658static int add_ext_target_dev(struct ctlr_info *h,
edd16368 2659 struct hpsa_scsi_dev_t *tmpdevice,
01a02ffc 2660 struct hpsa_scsi_dev_t *this_device, u8 *lunaddrbytes,
4f4eb9f1 2661 unsigned long lunzerobits[], int *n_ext_target_devs)
edd16368
SC		 2662{
2663 unsigned char scsi3addr[8];
2664
1f310bde 2665 if (test_bit(tmpdevice->target, lunzerobits))
edd16368
SC		 2666 return 0; /* There is already a lun 0 on this target. */
2667
2668 if (!is_logical_dev_addr_mode(lunaddrbytes))
2669 return 0; /* It's the logical targets that may lack lun 0. */
2670
4f4eb9f1
ST		 2671 if (!is_ext_target(h, tmpdevice))
2672 return 0; /* Only external target devices have this problem. */
edd16368 2673
1f310bde 2674 if (tmpdevice->lun == 0) /* if lun is 0, then we have a lun 0. */
edd16368
SC		 2675 return 0;
2676
c4f8a299 2677 memset(scsi3addr, 0, 8);
1f310bde 2678 scsi3addr[3] = tmpdevice->target;
edd16368
SC		 2679 if (is_hba_lunid(scsi3addr))
2680 return 0; /* Don't add the RAID controller here. */
2681
339b2b14
SC		 2682 if (is_scsi_rev_5(h))
2683 return 0; /* p1210m doesn't need to do this. */
2684
4f4eb9f1 2685 if (*n_ext_target_devs >= MAX_EXT_TARGETS) {
aca4a520
ST		 2686 dev_warn(&h->pdev->dev, "Maximum number of external "
2687 "target devices exceeded. Check your hardware "
edd16368
SC		 2688 "configuration.");
2689 return 0;
2690 }
2691
0b0e1d6c 2692 if (hpsa_update_device_info(h, scsi3addr, this_device, NULL))
edd16368 2693 return 0;
4f4eb9f1 2694 (*n_ext_target_devs)++;
1f310bde
SC		 2695 hpsa_set_bus_target_lun(this_device,
2696 tmpdevice->bus, tmpdevice->target, 0);
2697 set_bit(tmpdevice->target, lunzerobits);
edd16368
SC		 2698 return 1;
2699}
2700
54b6e9e9
ST		 2701/*
2702 * Get address of physical disk used for an ioaccel2 mode command:
2703 * 1. Extract ioaccel2 handle from the command.
2704 * 2. Find a matching ioaccel2 handle from list of physical disks.
2705 * 3. Return:
2706 * 1 and set scsi3addr to address of matching physical
2707 * 0 if no matching physical disk was found.
2708 */
2709static int hpsa_get_pdisk_of_ioaccel2(struct ctlr_info *h,
2710 struct CommandList *ioaccel2_cmd_to_abort, unsigned char *scsi3addr)
2711{
2712 struct ReportExtendedLUNdata *physicals = NULL;
2713 int responsesize = 24; /* size of physical extended response */
2714 int extended = 2; /* flag forces reporting 'other dev info'. */
2715 int reportsize = sizeof(*physicals) + HPSA_MAX_PHYS_LUN * responsesize;
2716 u32 nphysicals = 0; /* number of reported physical devs */
2717 int found = 0; /* found match (1) or not (0) */
2718 u32 find; /* handle we need to match */
2719 int i;
2720 struct scsi_cmnd *scmd; /* scsi command within request being aborted */
2721 struct hpsa_scsi_dev_t *d; /* device of request being aborted */
2722 struct io_accel2_cmd *c2a; /* ioaccel2 command to abort */
2b08b3e9
DB		 2723 __le32 it_nexus; /* 4 byte device handle for the ioaccel2 cmd */
2724 __le32 scsi_nexus; /* 4 byte device handle for the ioaccel2 cmd */
54b6e9e9
ST		 2725
2726 if (ioaccel2_cmd_to_abort->cmd_type != CMD_IOACCEL2)
2727 return 0; /* no match */
2728
2729 /* point to the ioaccel2 device handle */
2730 c2a = &h->ioaccel2_cmd_pool[ioaccel2_cmd_to_abort->cmdindex];
2731 if (c2a == NULL)
2732 return 0; /* no match */
2733
2734 scmd = (struct scsi_cmnd *) ioaccel2_cmd_to_abort->scsi_cmd;
2735 if (scmd == NULL)
2736 return 0; /* no match */
2737
2738 d = scmd->device->hostdata;
2739 if (d == NULL)
2740 return 0; /* no match */
2741
50a0decf 2742 it_nexus = cpu_to_le32(d->ioaccel_handle);
2b08b3e9
DB		 2743 scsi_nexus = c2a->scsi_nexus;
2744 find = le32_to_cpu(c2a->scsi_nexus);
54b6e9e9 2745
2ba8bfc8
SC		 2746 if (h->raid_offload_debug > 0)
2747 dev_info(&h->pdev->dev,
2748 "%s: scsi_nexus:0x%08x device id: 0x%02x%02x%02x%02x %02x%02x%02x%02x %02x%02x%02x%02x %02x%02x%02x%02x\n",
2749 __func__, scsi_nexus,
2750 d->device_id[0], d->device_id[1], d->device_id[2],
2751 d->device_id[3], d->device_id[4], d->device_id[5],
2752 d->device_id[6], d->device_id[7], d->device_id[8],
2753 d->device_id[9], d->device_id[10], d->device_id[11],
2754 d->device_id[12], d->device_id[13], d->device_id[14],
2755 d->device_id[15]);
2756
54b6e9e9
ST		 2757 /* Get the list of physical devices */
2758 physicals = kzalloc(reportsize, GFP_KERNEL);
3b51a7a3
JH		 2759 if (physicals == NULL)
2760 return 0;
54b6e9e9
ST		 2761 if (hpsa_scsi_do_report_phys_luns(h, (struct ReportLUNdata *) physicals,
2762 reportsize, extended)) {
2763 dev_err(&h->pdev->dev,
2764 "Can't lookup %s device handle: report physical LUNs failed.\n",
2765 "HP SSD Smart Path");
2766 kfree(physicals);
2767 return 0;
2768 }
2769 nphysicals = be32_to_cpu(*((__be32 *)physicals->LUNListLength)) /
2770 responsesize;
2771
54b6e9e9
ST		 2772 /* find ioaccel2 handle in list of physicals: */
2773 for (i = 0; i < nphysicals; i++) {
d5b5d964
SC		 2774 struct ext_report_lun_entry *entry = &physicals->LUN[i];
2775
54b6e9e9 2776 /* handle is in bytes 28-31 of each lun */
d5b5d964 2777 if (entry->ioaccel_handle != find)
54b6e9e9 2778 continue; /* didn't match */
54b6e9e9 2779 found = 1;
d5b5d964 2780 memcpy(scsi3addr, entry->lunid, 8);
2ba8bfc8
SC		 2781 if (h->raid_offload_debug > 0)
2782 dev_info(&h->pdev->dev,
d5b5d964 2783 "%s: Searched h=0x%08x, Found h=0x%08x, scsiaddr 0x%8phN\n",
2ba8bfc8 2784 __func__, find,
d5b5d964 2785 entry->ioaccel_handle, scsi3addr);
54b6e9e9
ST		 2786 break; /* found it */
2787 }
2788
2789 kfree(physicals);
2790 if (found)
2791 return 1;
2792 else
2793 return 0;
2794
2795}
edd16368
SC		 2796/*
2797 * Do CISS_REPORT_PHYS and CISS_REPORT_LOG. Data is returned in physdev,
2798 * logdev. The number of luns in physdev and logdev are returned in
2799 * *nphysicals and *nlogicals, respectively.
2800 * Returns 0 on success, -1 otherwise.
2801 */
2802static int hpsa_gather_lun_info(struct ctlr_info *h,
92084715 2803 int reportphyslunsize, int reportloglunsize,
283b4a9b 2804 struct ReportLUNdata *physdev, u32 *nphysicals, int *physical_mode,
01a02ffc 2805 struct ReportLUNdata *logdev, u32 *nlogicals)
edd16368 2806{
283b4a9b
SC		 2807 int physical_entry_size = 8;
2808
2809 *physical_mode = 0;
2810
2811 /* For I/O accelerator mode we need to read physical device handles */
317d4adf
MM		 2812 if (h->transMethod & CFGTBL_Trans_io_accel1 ||
2813 h->transMethod & CFGTBL_Trans_io_accel2) {
283b4a9b
SC		 2814 *physical_mode = HPSA_REPORT_PHYS_EXTENDED;
2815 physical_entry_size = 24;
2816 }
92084715 2817 if (hpsa_scsi_do_report_phys_luns(h, physdev, reportphyslunsize,
283b4a9b 2818 *physical_mode)) {
edd16368
SC		 2819 dev_err(&h->pdev->dev, "report physical LUNs failed.\n");
2820 return -1;
2821 }
283b4a9b
SC		 2822 *nphysicals = be32_to_cpu(*((__be32 *)physdev->LUNListLength)) /
2823 physical_entry_size;
edd16368
SC		 2824 if (*nphysicals > HPSA_MAX_PHYS_LUN) {
2825 dev_warn(&h->pdev->dev, "maximum physical LUNs (%d) exceeded."
2826 " %d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
2827 *nphysicals - HPSA_MAX_PHYS_LUN);
2828 *nphysicals = HPSA_MAX_PHYS_LUN;
2829 }
92084715 2830 if (hpsa_scsi_do_report_log_luns(h, logdev, reportloglunsize)) {
edd16368
SC		 2831 dev_err(&h->pdev->dev, "report logical LUNs failed.\n");
2832 return -1;
2833 }
6df1e954 2834 *nlogicals = be32_to_cpu(*((__be32 *) logdev->LUNListLength)) / 8;
edd16368
SC		 2835 /* Reject Logicals in excess of our max capability. */
2836 if (*nlogicals > HPSA_MAX_LUN) {
2837 dev_warn(&h->pdev->dev,
2838 "maximum logical LUNs (%d) exceeded. "
2839 "%d LUNs ignored.\n", HPSA_MAX_LUN,
2840 *nlogicals - HPSA_MAX_LUN);
2841 *nlogicals = HPSA_MAX_LUN;
2842 }
2843 if (*nlogicals + *nphysicals > HPSA_MAX_PHYS_LUN) {
2844 dev_warn(&h->pdev->dev,
2845 "maximum logical + physical LUNs (%d) exceeded. "
2846 "%d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
2847 *nphysicals + *nlogicals - HPSA_MAX_PHYS_LUN);
2848 *nlogicals = HPSA_MAX_PHYS_LUN - *nphysicals;
2849 }
2850 return 0;
2851}
2852
42a91641
DB		 2853static u8 *figure_lunaddrbytes(struct ctlr_info *h, int raid_ctlr_position,
2854 int i, int nphysicals, int nlogicals,
a93aa1fe 2855 struct ReportExtendedLUNdata *physdev_list,
339b2b14
SC		 2856 struct ReportLUNdata *logdev_list)
2857{
2858 /* Helper function, figure out where the LUN ID info is coming from
2859 * given index i, lists of physical and logical devices, where in
2860 * the list the raid controller is supposed to appear (first or last)
2861 */
2862
2863 int logicals_start = nphysicals + (raid_ctlr_position == 0);
2864 int last_device = nphysicals + nlogicals + (raid_ctlr_position == 0);
2865
2866 if (i == raid_ctlr_position)
2867 return RAID_CTLR_LUNID;
2868
2869 if (i < logicals_start)
d5b5d964
SC		 2870 return &physdev_list->LUN[i -
2871 (raid_ctlr_position == 0)].lunid[0];
339b2b14
SC		 2872
2873 if (i < last_device)
2874 return &logdev_list->LUN[i - nphysicals -
2875 (raid_ctlr_position == 0)][0];
2876 BUG();
2877 return NULL;
2878}
2879
316b221a
SC		 2880static int hpsa_hba_mode_enabled(struct ctlr_info *h)
2881{
2882 int rc;
6e8e8088 2883 int hba_mode_enabled;
316b221a
SC		 2884 struct bmic_controller_parameters *ctlr_params;
2885 ctlr_params = kzalloc(sizeof(struct bmic_controller_parameters),
2886 GFP_KERNEL);
2887
2888 if (!ctlr_params)
96444fbb 2889 return -ENOMEM;
316b221a
SC		 2890 rc = hpsa_bmic_ctrl_mode_sense(h, RAID_CTLR_LUNID, 0, ctlr_params,
2891 sizeof(struct bmic_controller_parameters));
96444fbb 2892 if (rc) {
316b221a 2893 kfree(ctlr_params);
96444fbb 2894 return rc;
316b221a 2895 }
6e8e8088
JH		 2896
2897 hba_mode_enabled =
2898 ((ctlr_params->nvram_flags & HBA_MODE_ENABLED_FLAG) != 0);
2899 kfree(ctlr_params);
2900 return hba_mode_enabled;
316b221a
SC		 2901}
2902
edd16368
SC		 2903static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno)
2904{
2905 /* the idea here is we could get notified
2906 * that some devices have changed, so we do a report
2907 * physical luns and report logical luns cmd, and adjust
2908 * our list of devices accordingly.
2909 *
2910 * The scsi3addr's of devices won't change so long as the
2911 * adapter is not reset. That means we can rescan and
2912 * tell which devices we already know about, vs. new
2913 * devices, vs. disappearing devices.
2914 */
a93aa1fe 2915 struct ReportExtendedLUNdata *physdev_list = NULL;
edd16368 2916 struct ReportLUNdata *logdev_list = NULL;
01a02ffc
SC		 2917 u32 nphysicals = 0;
2918 u32 nlogicals = 0;
283b4a9b 2919 int physical_mode = 0;
01a02ffc 2920 u32 ndev_allocated = 0;
edd16368
SC		 2921 struct hpsa_scsi_dev_t **currentsd, *this_device, *tmpdevice;
2922 int ncurrent = 0;
4f4eb9f1 2923 int i, n_ext_target_devs, ndevs_to_allocate;
339b2b14 2924 int raid_ctlr_position;
2bbf5c7f 2925 int rescan_hba_mode;
aca4a520 2926 DECLARE_BITMAP(lunzerobits, MAX_EXT_TARGETS);
edd16368 2927
cfe5badc 2928 currentsd = kzalloc(sizeof(*currentsd) * HPSA_MAX_DEVICES, GFP_KERNEL);
92084715
SC		 2929 physdev_list = kzalloc(sizeof(*physdev_list), GFP_KERNEL);
2930 logdev_list = kzalloc(sizeof(*logdev_list), GFP_KERNEL);
edd16368
SC		 2931 tmpdevice = kzalloc(sizeof(*tmpdevice), GFP_KERNEL);
2932
0b0e1d6c 2933 if (!currentsd || !physdev_list || !logdev_list || !tmpdevice) {
edd16368
SC		 2934 dev_err(&h->pdev->dev, "out of memory\n");
2935 goto out;
2936 }
2937 memset(lunzerobits, 0, sizeof(lunzerobits));
2938
316b221a 2939 rescan_hba_mode = hpsa_hba_mode_enabled(h);
96444fbb
JH		 2940 if (rescan_hba_mode < 0)
2941 goto out;
316b221a
SC		 2942
2943 if (!h->hba_mode_enabled && rescan_hba_mode)
2944 dev_warn(&h->pdev->dev, "HBA mode enabled\n");
2945 else if (h->hba_mode_enabled && !rescan_hba_mode)
2946 dev_warn(&h->pdev->dev, "HBA mode disabled\n");
2947
2948 h->hba_mode_enabled = rescan_hba_mode;
2949
92084715
SC		 2950 if (hpsa_gather_lun_info(h,
2951 sizeof(*physdev_list), sizeof(*logdev_list),
a93aa1fe 2952 (struct ReportLUNdata *) physdev_list, &nphysicals,
283b4a9b 2953 &physical_mode, logdev_list, &nlogicals))
edd16368
SC		 2954 goto out;
2955
aca4a520
ST		 2956 /* We might see up to the maximum number of logical and physical disks
2957 * plus external target devices, and a device for the local RAID
2958 * controller.
edd16368 2959 */
aca4a520 2960 ndevs_to_allocate = nphysicals + nlogicals + MAX_EXT_TARGETS + 1;
edd16368
SC		 2961
2962 /* Allocate the per device structures */
2963 for (i = 0; i < ndevs_to_allocate; i++) {
b7ec021f
ST		 2964 if (i >= HPSA_MAX_DEVICES) {
2965 dev_warn(&h->pdev->dev, "maximum devices (%d) exceeded."
2966 " %d devices ignored.\n", HPSA_MAX_DEVICES,
2967 ndevs_to_allocate - HPSA_MAX_DEVICES);
2968 break;
2969 }
2970
edd16368
SC		 2971 currentsd[i] = kzalloc(sizeof(*currentsd[i]), GFP_KERNEL);
2972 if (!currentsd[i]) {
2973 dev_warn(&h->pdev->dev, "out of memory at %s:%d\n",
2974 __FILE__, __LINE__);
2975 goto out;
2976 }
2977 ndev_allocated++;
2978 }
2979
8645291b 2980 if (is_scsi_rev_5(h))
339b2b14
SC		 2981 raid_ctlr_position = 0;
2982 else
2983 raid_ctlr_position = nphysicals + nlogicals;
2984
edd16368 2985 /* adjust our table of devices */
4f4eb9f1 2986 n_ext_target_devs = 0;
edd16368 2987 for (i = 0; i < nphysicals + nlogicals + 1; i++) {
0b0e1d6c 2988 u8 *lunaddrbytes, is_OBDR = 0;
edd16368
SC		 2989
2990 /* Figure out where the LUN ID info is coming from */
339b2b14
SC		 2991 lunaddrbytes = figure_lunaddrbytes(h, raid_ctlr_position,
2992 i, nphysicals, nlogicals, physdev_list, logdev_list);
edd16368 2993 /* skip masked physical devices. */
339b2b14
SC		 2994 if (lunaddrbytes[3] & 0xC0 &&
2995 i < nphysicals + (raid_ctlr_position == 0))
edd16368
SC		 2996 continue;
2997
2998 /* Get device type, vendor, model, device id */
0b0e1d6c
SC		 2999 if (hpsa_update_device_info(h, lunaddrbytes, tmpdevice,
3000 &is_OBDR))
edd16368 3001 continue; /* skip it if we can't talk to it. */
1f310bde 3002 figure_bus_target_lun(h, lunaddrbytes, tmpdevice);
edd16368
SC		 3003 this_device = currentsd[ncurrent];
3004
3005 /*
4f4eb9f1 3006 * For external target devices, we have to insert a LUN 0 which
edd16368
SC		 3007 * doesn't show up in CCISS_REPORT_PHYSICAL data, but there
3008 * is nonetheless an enclosure device there. We have to
3009 * present that otherwise linux won't find anything if
3010 * there is no lun 0.
3011 */
4f4eb9f1 3012 if (add_ext_target_dev(h, tmpdevice, this_device,
1f310bde 3013 lunaddrbytes, lunzerobits,
4f4eb9f1 3014 &n_ext_target_devs)) {
edd16368
SC		 3015 ncurrent++;
3016 this_device = currentsd[ncurrent];
3017 }
3018
3019 *this_device = *tmpdevice;
edd16368
SC		 3020
3021 switch (this_device->devtype) {
0b0e1d6c 3022 case TYPE_ROM:
edd16368
SC		 3023 /* We don't *really* support actual CD-ROM devices,
3024 * just "One Button Disaster Recovery" tape drive
3025 * which temporarily pretends to be a CD-ROM drive.
3026 * So we check that the device is really an OBDR tape
3027 * device by checking for "$DR-10" in bytes 43-48 of
3028 * the inquiry data.
3029 */
0b0e1d6c
SC		 3030 if (is_OBDR)
3031 ncurrent++;
edd16368
SC		 3032 break;
3033 case TYPE_DISK:
316b221a
SC		 3034 if (h->hba_mode_enabled) {
3035 /* never use raid mapper in HBA mode */
3036 this_device->offload_enabled = 0;
3037 ncurrent++;
3038 break;
3039 } else if (h->acciopath_status) {
3040 if (i >= nphysicals) {
3041 ncurrent++;
3042 break;
3043 }
3044 } else {
3045 if (i < nphysicals)
3046 break;
283b4a9b 3047 ncurrent++;
edd16368 3048 break;
283b4a9b
SC		 3049 }
3050 if (physical_mode == HPSA_REPORT_PHYS_EXTENDED) {
3051 memcpy(&this_device->ioaccel_handle,
3052 &lunaddrbytes[20],
3053 sizeof(this_device->ioaccel_handle));
3054 ncurrent++;
3055 }
edd16368
SC		 3056 break;
3057 case TYPE_TAPE:
3058 case TYPE_MEDIUM_CHANGER:
3059 ncurrent++;
3060 break;
3061 case TYPE_RAID:
3062 /* Only present the Smartarray HBA as a RAID controller.
3063 * If it's a RAID controller other than the HBA itself
3064 * (an external RAID controller, MSA500 or similar)
3065 * don't present it.
3066 */
3067 if (!is_hba_lunid(lunaddrbytes))
3068 break;
3069 ncurrent++;
3070 break;
3071 default:
3072 break;
3073 }
cfe5badc 3074 if (ncurrent >= HPSA_MAX_DEVICES)
edd16368
SC		 3075 break;
3076 }
3077 adjust_hpsa_scsi_table(h, hostno, currentsd, ncurrent);
3078out:
3079 kfree(tmpdevice);
3080 for (i = 0; i < ndev_allocated; i++)
3081 kfree(currentsd[i]);
3082 kfree(currentsd);
edd16368
SC		 3083 kfree(physdev_list);
3084 kfree(logdev_list);
edd16368
SC		 3085}
3086
c7ee65b3
WS		 3087/*
3088 * hpsa_scatter_gather takes a struct scsi_cmnd, (cmd), and does the pci
edd16368
SC		 3089 * dma mapping and fills in the scatter gather entries of the
3090 * hpsa command, cp.
3091 */
33a2ffce 3092static int hpsa_scatter_gather(struct ctlr_info *h,
edd16368
SC		 3093 struct CommandList *cp,
3094 struct scsi_cmnd *cmd)
3095{
3096 unsigned int len;
3097 struct scatterlist *sg;
01a02ffc 3098 u64 addr64;
33a2ffce
SC		 3099 int use_sg, i, sg_index, chained;
3100 struct SGDescriptor *curr_sg;
edd16368 3101
33a2ffce 3102 BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
edd16368
SC		 3103
3104 use_sg = scsi_dma_map(cmd);
3105 if (use_sg < 0)
3106 return use_sg;
3107
3108 if (!use_sg)
3109 goto sglist_finished;
3110
33a2ffce
SC		 3111 curr_sg = cp->SG;
3112 chained = 0;
3113 sg_index = 0;
edd16368 3114 scsi_for_each_sg(cmd, sg, use_sg, i) {
33a2ffce
SC		 3115 if (i == h->max_cmd_sg_entries - 1 &&
3116 use_sg > h->max_cmd_sg_entries) {
3117 chained = 1;
3118 curr_sg = h->cmd_sg_list[cp->cmdindex];
3119 sg_index = 0;
3120 }
01a02ffc 3121 addr64 = (u64) sg_dma_address(sg);
edd16368 3122 len = sg_dma_len(sg);
50a0decf
SC		 3123 curr_sg->Addr = cpu_to_le64(addr64);
3124 curr_sg->Len = cpu_to_le32(len);
3125 curr_sg->Ext = cpu_to_le32(0);
33a2ffce
SC		 3126 curr_sg++;
3127 }
50a0decf 3128 (--curr_sg)->Ext = cpu_to_le32(HPSA_SG_LAST);
33a2ffce
SC		 3129
3130 if (use_sg + chained > h->maxSG)
3131 h->maxSG = use_sg + chained;
3132
3133 if (chained) {
3134 cp->Header.SGList = h->max_cmd_sg_entries;
50a0decf 3135 cp->Header.SGTotal = cpu_to_le16(use_sg + 1);
e2bea6df
SC		 3136 if (hpsa_map_sg_chain_block(h, cp)) {
3137 scsi_dma_unmap(cmd);
3138 return -1;
3139 }
33a2ffce 3140 return 0;
edd16368
SC		 3141 }
3142
3143sglist_finished:
3144
01a02ffc 3145 cp->Header.SGList = (u8) use_sg; /* no. SGs contig in this cmd */
c7ee65b3 3146 cp->Header.SGTotal = cpu_to_le16(use_sg); /* total sgs in cmd list */
edd16368
SC		 3147 return 0;
3148}
3149
283b4a9b
SC		 3150#define IO_ACCEL_INELIGIBLE (1)
3151static int fixup_ioaccel_cdb(u8 *cdb, int *cdb_len)
3152{
3153 int is_write = 0;
3154 u32 block;
3155 u32 block_cnt;
3156
3157 /* Perform some CDB fixups if needed using 10 byte reads/writes only */
3158 switch (cdb[0]) {
3159 case WRITE_6:
3160 case WRITE_12:
3161 is_write = 1;
3162 case READ_6:
3163 case READ_12:
3164 if (*cdb_len == 6) {
3165 block = (((u32) cdb[2]) << 8) | cdb[3];
3166 block_cnt = cdb[4];
3167 } else {
3168 BUG_ON(*cdb_len != 12);
3169 block = (((u32) cdb[2]) << 24) |
3170 (((u32) cdb[3]) << 16) |
3171 (((u32) cdb[4]) << 8) |
3172 cdb[5];
3173 block_cnt =
3174 (((u32) cdb[6]) << 24) |
3175 (((u32) cdb[7]) << 16) |
3176 (((u32) cdb[8]) << 8) |
3177 cdb[9];
3178 }
3179 if (block_cnt > 0xffff)
3180 return IO_ACCEL_INELIGIBLE;
3181
3182 cdb[0] = is_write ? WRITE_10 : READ_10;
3183 cdb[1] = 0;
3184 cdb[2] = (u8) (block >> 24);
3185 cdb[3] = (u8) (block >> 16);
3186 cdb[4] = (u8) (block >> 8);
3187 cdb[5] = (u8) (block);
3188 cdb[6] = 0;
3189 cdb[7] = (u8) (block_cnt >> 8);
3190 cdb[8] = (u8) (block_cnt);
3191 cdb[9] = 0;
3192 *cdb_len = 10;
3193 break;
3194 }
3195 return 0;
3196}
3197
c349775e 3198static int hpsa_scsi_ioaccel1_queue_command(struct ctlr_info *h,
283b4a9b
SC		 3199 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
3200 u8 *scsi3addr)
e1f7de0c
MG		 3201{
3202 struct scsi_cmnd *cmd = c->scsi_cmd;
e1f7de0c
MG		 3203 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
3204 unsigned int len;
3205 unsigned int total_len = 0;
3206 struct scatterlist *sg;
3207 u64 addr64;
3208 int use_sg, i;
3209 struct SGDescriptor *curr_sg;
3210 u32 control = IOACCEL1_CONTROL_SIMPLEQUEUE;
3211
283b4a9b
SC		 3212 /* TODO: implement chaining support */
3213 if (scsi_sg_count(cmd) > h->ioaccel_maxsg)
3214 return IO_ACCEL_INELIGIBLE;
3215
e1f7de0c
MG		 3216 BUG_ON(cmd->cmd_len > IOACCEL1_IOFLAGS_CDBLEN_MAX);
3217
283b4a9b
SC		 3218 if (fixup_ioaccel_cdb(cdb, &cdb_len))
3219 return IO_ACCEL_INELIGIBLE;
3220
e1f7de0c
MG		 3221 c->cmd_type = CMD_IOACCEL1;
3222
3223 /* Adjust the DMA address to point to the accelerated command buffer */
3224 c->busaddr = (u32) h->ioaccel_cmd_pool_dhandle +
3225 (c->cmdindex * sizeof(*cp));
3226 BUG_ON(c->busaddr & 0x0000007F);
3227
3228 use_sg = scsi_dma_map(cmd);
3229 if (use_sg < 0)
3230 return use_sg;
3231
3232 if (use_sg) {
3233 curr_sg = cp->SG;
3234 scsi_for_each_sg(cmd, sg, use_sg, i) {
3235 addr64 = (u64) sg_dma_address(sg);
3236 len = sg_dma_len(sg);
3237 total_len += len;
50a0decf
SC		 3238 curr_sg->Addr = cpu_to_le64(addr64);
3239 curr_sg->Len = cpu_to_le32(len);
3240 curr_sg->Ext = cpu_to_le32(0);
e1f7de0c
MG		 3241 curr_sg++;
3242 }
50a0decf 3243 (--curr_sg)->Ext = cpu_to_le32(HPSA_SG_LAST);
e1f7de0c
MG		 3244
3245 switch (cmd->sc_data_direction) {
3246 case DMA_TO_DEVICE:
3247 control |= IOACCEL1_CONTROL_DATA_OUT;
3248 break;
3249 case DMA_FROM_DEVICE:
3250 control |= IOACCEL1_CONTROL_DATA_IN;
3251 break;
3252 case DMA_NONE:
3253 control |= IOACCEL1_CONTROL_NODATAXFER;
3254 break;
3255 default:
3256 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
3257 cmd->sc_data_direction);
3258 BUG();
3259 break;
3260 }
3261 } else {
3262 control |= IOACCEL1_CONTROL_NODATAXFER;
3263 }
3264
c349775e 3265 c->Header.SGList = use_sg;
e1f7de0c 3266 /* Fill out the command structure to submit */
2b08b3e9
DB		 3267 cp->dev_handle = cpu_to_le16(ioaccel_handle & 0xFFFF);
3268 cp->transfer_len = cpu_to_le32(total_len);
3269 cp->io_flags = cpu_to_le16(IOACCEL1_IOFLAGS_IO_REQ |
3270 (cdb_len & IOACCEL1_IOFLAGS_CDBLEN_MASK));
3271 cp->control = cpu_to_le32(control);
283b4a9b
SC		 3272 memcpy(cp->CDB, cdb, cdb_len);
3273 memcpy(cp->CISS_LUN, scsi3addr, 8);
c349775e 3274 /* Tag was already set at init time. */
283b4a9b 3275 enqueue_cmd_and_start_io(h, c);
e1f7de0c
MG		 3276 return 0;
3277}
edd16368 3278
283b4a9b
SC		 3279/*
3280 * Queue a command directly to a device behind the controller using the
3281 * I/O accelerator path.
3282 */
3283static int hpsa_scsi_ioaccel_direct_map(struct ctlr_info *h,
3284 struct CommandList *c)
3285{
3286 struct scsi_cmnd *cmd = c->scsi_cmd;
3287 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
3288
3289 return hpsa_scsi_ioaccel_queue_command(h, c, dev->ioaccel_handle,
3290 cmd->cmnd, cmd->cmd_len, dev->scsi3addr);
3291}
3292
dd0e19f3
ST		 3293/*
3294 * Set encryption parameters for the ioaccel2 request
3295 */
3296static void set_encrypt_ioaccel2(struct ctlr_info *h,
3297 struct CommandList *c, struct io_accel2_cmd *cp)
3298{
3299 struct scsi_cmnd *cmd = c->scsi_cmd;
3300 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
3301 struct raid_map_data *map = &dev->raid_map;
3302 u64 first_block;
3303
3304 BUG_ON(!(dev->offload_config && dev->offload_enabled));
3305
3306 /* Are we doing encryption on this device */
2b08b3e9 3307 if (!(le16_to_cpu(map->flags) & RAID_MAP_FLAG_ENCRYPT_ON))
dd0e19f3
ST		 3308 return;
3309 /* Set the data encryption key index. */
3310 cp->dekindex = map->dekindex;
3311
3312 /* Set the encryption enable flag, encoded into direction field. */
3313 cp->direction |= IOACCEL2_DIRECTION_ENCRYPT_MASK;
3314
3315 /* Set encryption tweak values based on logical block address
3316 * If block size is 512, tweak value is LBA.
3317 * For other block sizes, tweak is (LBA * block size)/ 512)
3318 */
3319 switch (cmd->cmnd[0]) {
3320 /* Required? 6-byte cdbs eliminated by fixup_ioaccel_cdb */
3321 case WRITE_6:
3322 case READ_6:
2b08b3e9 3323 first_block = get_unaligned_be16(&cmd->cmnd[2]);
dd0e19f3
ST		 3324 break;
3325 case WRITE_10:
3326 case READ_10:
dd0e19f3
ST		 3327 /* Required? 12-byte cdbs eliminated by fixup_ioaccel_cdb */
3328 case WRITE_12:
3329 case READ_12:
2b08b3e9 3330 first_block = get_unaligned_be32(&cmd->cmnd[2]);
dd0e19f3
ST		 3331 break;
3332 case WRITE_16:
3333 case READ_16:
2b08b3e9 3334 first_block = get_unaligned_be64(&cmd->cmnd[2]);
dd0e19f3
ST		 3335 break;
3336 default:
3337 dev_err(&h->pdev->dev,
2b08b3e9
DB		 3338 "ERROR: %s: size (0x%x) not supported for encryption\n",
3339 __func__, cmd->cmnd[0]);
dd0e19f3
ST		 3340 BUG();
3341 break;
3342 }
2b08b3e9
DB		 3343
3344 if (le32_to_cpu(map->volume_blk_size) != 512)
3345 first_block = first_block *
3346 le32_to_cpu(map->volume_blk_size)/512;
3347
3348 cp->tweak_lower = cpu_to_le32(first_block);
3349 cp->tweak_upper = cpu_to_le32(first_block >> 32);
dd0e19f3
ST		 3350}
3351
c349775e
ST		 3352static int hpsa_scsi_ioaccel2_queue_command(struct ctlr_info *h,
3353 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
3354 u8 *scsi3addr)
3355{
3356 struct scsi_cmnd *cmd = c->scsi_cmd;
3357 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
3358 struct ioaccel2_sg_element *curr_sg;
3359 int use_sg, i;
3360 struct scatterlist *sg;
3361 u64 addr64;
3362 u32 len;
3363 u32 total_len = 0;
3364
3365 if (scsi_sg_count(cmd) > h->ioaccel_maxsg)
3366 return IO_ACCEL_INELIGIBLE;
3367
3368 if (fixup_ioaccel_cdb(cdb, &cdb_len))
3369 return IO_ACCEL_INELIGIBLE;
3370 c->cmd_type = CMD_IOACCEL2;
3371 /* Adjust the DMA address to point to the accelerated command buffer */
3372 c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle +
3373 (c->cmdindex * sizeof(*cp));
3374 BUG_ON(c->busaddr & 0x0000007F);
3375
3376 memset(cp, 0, sizeof(*cp));
3377 cp->IU_type = IOACCEL2_IU_TYPE;
3378
3379 use_sg = scsi_dma_map(cmd);
3380 if (use_sg < 0)
3381 return use_sg;
3382
3383 if (use_sg) {
3384 BUG_ON(use_sg > IOACCEL2_MAXSGENTRIES);
3385 curr_sg = cp->sg;
3386 scsi_for_each_sg(cmd, sg, use_sg, i) {
3387 addr64 = (u64) sg_dma_address(sg);
3388 len = sg_dma_len(sg);
3389 total_len += len;
3390 curr_sg->address = cpu_to_le64(addr64);
3391 curr_sg->length = cpu_to_le32(len);
3392 curr_sg->reserved[0] = 0;
3393 curr_sg->reserved[1] = 0;
3394 curr_sg->reserved[2] = 0;
3395 curr_sg->chain_indicator = 0;
3396 curr_sg++;
3397 }
3398
3399 switch (cmd->sc_data_direction) {
3400 case DMA_TO_DEVICE:
dd0e19f3
ST		 3401 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3402 cp->direction |= IOACCEL2_DIR_DATA_OUT;
c349775e
ST		 3403 break;
3404 case DMA_FROM_DEVICE:
dd0e19f3
ST		 3405 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3406 cp->direction |= IOACCEL2_DIR_DATA_IN;
c349775e
ST		 3407 break;
3408 case DMA_NONE:
dd0e19f3
ST		 3409 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3410 cp->direction |= IOACCEL2_DIR_NO_DATA;
c349775e
ST		 3411 break;
3412 default:
3413 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
3414 cmd->sc_data_direction);
3415 BUG();
3416 break;
3417 }
3418 } else {
dd0e19f3
ST		 3419 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3420 cp->direction |= IOACCEL2_DIR_NO_DATA;
c349775e 3421 }
dd0e19f3
ST		 3422
3423 /* Set encryption parameters, if necessary */
3424 set_encrypt_ioaccel2(h, c, cp);
3425
2b08b3e9 3426 cp->scsi_nexus = cpu_to_le32(ioaccel_handle);
f2405db8 3427 cp->Tag = cpu_to_le32(c->cmdindex << DIRECT_LOOKUP_SHIFT);
c349775e 3428 memcpy(cp->cdb, cdb, sizeof(cp->cdb));
c349775e
ST		 3429
3430 /* fill in sg elements */
3431 cp->sg_count = (u8) use_sg;
3432
3433 cp->data_len = cpu_to_le32(total_len);
3434 cp->err_ptr = cpu_to_le64(c->busaddr +
3435 offsetof(struct io_accel2_cmd, error_data));
50a0decf 3436 cp->err_len = cpu_to_le32(sizeof(cp->error_data));
c349775e
ST		 3437
3438 enqueue_cmd_and_start_io(h, c);
3439 return 0;
3440}
3441
3442/*
3443 * Queue a command to the correct I/O accelerator path.
3444 */
3445static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
3446 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
3447 u8 *scsi3addr)
3448{
3449 if (h->transMethod & CFGTBL_Trans_io_accel1)
3450 return hpsa_scsi_ioaccel1_queue_command(h, c, ioaccel_handle,
3451 cdb, cdb_len, scsi3addr);
3452 else
3453 return hpsa_scsi_ioaccel2_queue_command(h, c, ioaccel_handle,
3454 cdb, cdb_len, scsi3addr);
3455}
3456
6b80b18f
ST		 3457static void raid_map_helper(struct raid_map_data *map,
3458 int offload_to_mirror, u32 *map_index, u32 *current_group)
3459{
3460 if (offload_to_mirror == 0) {
3461 /* use physical disk in the first mirrored group. */
2b08b3e9 3462 *map_index %= le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 3463 return;
3464 }
3465 do {
3466 /* determine mirror group that *map_index indicates */
2b08b3e9
DB		 3467 *current_group = *map_index /
3468 le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 3469 if (offload_to_mirror == *current_group)
3470 continue;
2b08b3e9 3471 if (*current_group < le16_to_cpu(map->layout_map_count) - 1) {
6b80b18f 3472 /* select map index from next group */
2b08b3e9 3473 *map_index += le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 3474 (*current_group)++;
3475 } else {
3476 /* select map index from first group */
2b08b3e9 3477 *map_index %= le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 3478 *current_group = 0;
3479 }
3480 } while (offload_to_mirror != *current_group);
3481}
3482
283b4a9b
SC		 3483/*
3484 * Attempt to perform offload RAID mapping for a logical volume I/O.
3485 */
3486static int hpsa_scsi_ioaccel_raid_map(struct ctlr_info *h,
3487 struct CommandList *c)
3488{
3489 struct scsi_cmnd *cmd = c->scsi_cmd;
3490 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
3491 struct raid_map_data *map = &dev->raid_map;
3492 struct raid_map_disk_data *dd = &map->data[0];
3493 int is_write = 0;
3494 u32 map_index;
3495 u64 first_block, last_block;
3496 u32 block_cnt;
3497 u32 blocks_per_row;
3498 u64 first_row, last_row;
3499 u32 first_row_offset, last_row_offset;
3500 u32 first_column, last_column;
6b80b18f
ST		 3501 u64 r0_first_row, r0_last_row;
3502 u32 r5or6_blocks_per_row;
3503 u64 r5or6_first_row, r5or6_last_row;
3504 u32 r5or6_first_row_offset, r5or6_last_row_offset;
3505 u32 r5or6_first_column, r5or6_last_column;
3506 u32 total_disks_per_row;
3507 u32 stripesize;
3508 u32 first_group, last_group, current_group;
283b4a9b
SC		 3509 u32 map_row;
3510 u32 disk_handle;
3511 u64 disk_block;
3512 u32 disk_block_cnt;
3513 u8 cdb[16];
3514 u8 cdb_len;
2b08b3e9 3515 u16 strip_size;
283b4a9b
SC		 3516#if BITS_PER_LONG == 32
3517 u64 tmpdiv;
3518#endif
6b80b18f 3519 int offload_to_mirror;
283b4a9b
SC		 3520
3521 BUG_ON(!(dev->offload_config && dev->offload_enabled));
3522
3523 /* check for valid opcode, get LBA and block count */
3524 switch (cmd->cmnd[0]) {
3525 case WRITE_6:
3526 is_write = 1;
3527 case READ_6:
3528 first_block =
3529 (((u64) cmd->cmnd[2]) << 8) |
3530 cmd->cmnd[3];
3531 block_cnt = cmd->cmnd[4];
3fa89a04
SC		 3532 if (block_cnt == 0)
3533 block_cnt = 256;
283b4a9b
SC		 3534 break;
3535 case WRITE_10:
3536 is_write = 1;
3537 case READ_10:
3538 first_block =
3539 (((u64) cmd->cmnd[2]) << 24) |
3540 (((u64) cmd->cmnd[3]) << 16) |
3541 (((u64) cmd->cmnd[4]) << 8) |
3542 cmd->cmnd[5];
3543 block_cnt =
3544 (((u32) cmd->cmnd[7]) << 8) |
3545 cmd->cmnd[8];
3546 break;
3547 case WRITE_12:
3548 is_write = 1;
3549 case READ_12:
3550 first_block =
3551 (((u64) cmd->cmnd[2]) << 24) |
3552 (((u64) cmd->cmnd[3]) << 16) |
3553 (((u64) cmd->cmnd[4]) << 8) |
3554 cmd->cmnd[5];
3555 block_cnt =
3556 (((u32) cmd->cmnd[6]) << 24) |
3557 (((u32) cmd->cmnd[7]) << 16) |
3558 (((u32) cmd->cmnd[8]) << 8) |
3559 cmd->cmnd[9];
3560 break;
3561 case WRITE_16:
3562 is_write = 1;
3563 case READ_16:
3564 first_block =
3565 (((u64) cmd->cmnd[2]) << 56) |
3566 (((u64) cmd->cmnd[3]) << 48) |
3567 (((u64) cmd->cmnd[4]) << 40) |
3568 (((u64) cmd->cmnd[5]) << 32) |
3569 (((u64) cmd->cmnd[6]) << 24) |
3570 (((u64) cmd->cmnd[7]) << 16) |
3571 (((u64) cmd->cmnd[8]) << 8) |
3572 cmd->cmnd[9];
3573 block_cnt =
3574 (((u32) cmd->cmnd[10]) << 24) |
3575 (((u32) cmd->cmnd[11]) << 16) |
3576 (((u32) cmd->cmnd[12]) << 8) |
3577 cmd->cmnd[13];
3578 break;
3579 default:
3580 return IO_ACCEL_INELIGIBLE; /* process via normal I/O path */
3581 }
283b4a9b
SC		 3582 last_block = first_block + block_cnt - 1;
3583
3584 /* check for write to non-RAID-0 */
3585 if (is_write && dev->raid_level != 0)
3586 return IO_ACCEL_INELIGIBLE;
3587
3588 /* check for invalid block or wraparound */
2b08b3e9
DB		 3589 if (last_block >= le64_to_cpu(map->volume_blk_cnt) ||
3590 last_block < first_block)
283b4a9b
SC		 3591 return IO_ACCEL_INELIGIBLE;
3592
3593 /* calculate stripe information for the request */
2b08b3e9
DB		 3594 blocks_per_row = le16_to_cpu(map->data_disks_per_row) *
3595 le16_to_cpu(map->strip_size);
3596 strip_size = le16_to_cpu(map->strip_size);
283b4a9b
SC		 3597#if BITS_PER_LONG == 32
3598 tmpdiv = first_block;
3599 (void) do_div(tmpdiv, blocks_per_row);
3600 first_row = tmpdiv;
3601 tmpdiv = last_block;
3602 (void) do_div(tmpdiv, blocks_per_row);
3603 last_row = tmpdiv;
3604 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
3605 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
3606 tmpdiv = first_row_offset;
2b08b3e9 3607 (void) do_div(tmpdiv, strip_size);
283b4a9b
SC		 3608 first_column = tmpdiv;
3609 tmpdiv = last_row_offset;
2b08b3e9 3610 (void) do_div(tmpdiv, strip_size);
283b4a9b
SC		 3611 last_column = tmpdiv;
3612#else
3613 first_row = first_block / blocks_per_row;
3614 last_row = last_block / blocks_per_row;
3615 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
3616 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
2b08b3e9
DB		 3617 first_column = first_row_offset / strip_size;
3618 last_column = last_row_offset / strip_size;
283b4a9b
SC		 3619#endif
3620
3621 /* if this isn't a single row/column then give to the controller */
3622 if ((first_row != last_row) || (first_column != last_column))
3623 return IO_ACCEL_INELIGIBLE;
3624
3625 /* proceeding with driver mapping */
2b08b3e9
DB		 3626 total_disks_per_row = le16_to_cpu(map->data_disks_per_row) +
3627 le16_to_cpu(map->metadata_disks_per_row);
283b4a9b 3628 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
2b08b3e9 3629 le16_to_cpu(map->row_cnt);
6b80b18f
ST		 3630 map_index = (map_row * total_disks_per_row) + first_column;
3631
3632 switch (dev->raid_level) {
3633 case HPSA_RAID_0:
3634 break; /* nothing special to do */
3635 case HPSA_RAID_1:
3636 /* Handles load balance across RAID 1 members.
3637 * (2-drive R1 and R10 with even # of drives.)
3638 * Appropriate for SSDs, not optimal for HDDs
283b4a9b 3639 */
2b08b3e9 3640 BUG_ON(le16_to_cpu(map->layout_map_count) != 2);
283b4a9b 3641 if (dev->offload_to_mirror)
2b08b3e9 3642 map_index += le16_to_cpu(map->data_disks_per_row);
283b4a9b 3643 dev->offload_to_mirror = !dev->offload_to_mirror;
6b80b18f
ST		 3644 break;
3645 case HPSA_RAID_ADM:
3646 /* Handles N-way mirrors (R1-ADM)
3647 * and R10 with # of drives divisible by 3.)
3648 */
2b08b3e9 3649 BUG_ON(le16_to_cpu(map->layout_map_count) != 3);
6b80b18f
ST		 3650
3651 offload_to_mirror = dev->offload_to_mirror;
3652 raid_map_helper(map, offload_to_mirror,
3653 &map_index, &current_group);
3654 /* set mirror group to use next time */
3655 offload_to_mirror =
2b08b3e9
DB		 3656 (offload_to_mirror >=
3657 le16_to_cpu(map->layout_map_count) - 1)
6b80b18f 3658 ? 0 : offload_to_mirror + 1;
6b80b18f
ST		 3659 dev->offload_to_mirror = offload_to_mirror;
3660 /* Avoid direct use of dev->offload_to_mirror within this
3661 * function since multiple threads might simultaneously
3662 * increment it beyond the range of dev->layout_map_count -1.
3663 */
3664 break;
3665 case HPSA_RAID_5:
3666 case HPSA_RAID_6:
2b08b3e9 3667 if (le16_to_cpu(map->layout_map_count) <= 1)
6b80b18f
ST		 3668 break;
3669
3670 /* Verify first and last block are in same RAID group */
3671 r5or6_blocks_per_row =
2b08b3e9
DB		 3672 le16_to_cpu(map->strip_size) *
3673 le16_to_cpu(map->data_disks_per_row);
6b80b18f 3674 BUG_ON(r5or6_blocks_per_row == 0);
2b08b3e9
DB		 3675 stripesize = r5or6_blocks_per_row *
3676 le16_to_cpu(map->layout_map_count);
6b80b18f
ST		 3677#if BITS_PER_LONG == 32
3678 tmpdiv = first_block;
3679 first_group = do_div(tmpdiv, stripesize);
3680 tmpdiv = first_group;
3681 (void) do_div(tmpdiv, r5or6_blocks_per_row);
3682 first_group = tmpdiv;
3683 tmpdiv = last_block;
3684 last_group = do_div(tmpdiv, stripesize);
3685 tmpdiv = last_group;
3686 (void) do_div(tmpdiv, r5or6_blocks_per_row);
3687 last_group = tmpdiv;
3688#else
3689 first_group = (first_block % stripesize) / r5or6_blocks_per_row;
3690 last_group = (last_block % stripesize) / r5or6_blocks_per_row;
6b80b18f 3691#endif
000ff7c2 3692 if (first_group != last_group)
6b80b18f
ST		 3693 return IO_ACCEL_INELIGIBLE;
3694
3695 /* Verify request is in a single row of RAID 5/6 */
3696#if BITS_PER_LONG == 32
3697 tmpdiv = first_block;
3698 (void) do_div(tmpdiv, stripesize);
3699 first_row = r5or6_first_row = r0_first_row = tmpdiv;
3700 tmpdiv = last_block;
3701 (void) do_div(tmpdiv, stripesize);
3702 r5or6_last_row = r0_last_row = tmpdiv;
3703#else
3704 first_row = r5or6_first_row = r0_first_row =
3705 first_block / stripesize;
3706 r5or6_last_row = r0_last_row = last_block / stripesize;
3707#endif
3708 if (r5or6_first_row != r5or6_last_row)
3709 return IO_ACCEL_INELIGIBLE;
3710
3711
3712 /* Verify request is in a single column */
3713#if BITS_PER_LONG == 32
3714 tmpdiv = first_block;
3715 first_row_offset = do_div(tmpdiv, stripesize);
3716 tmpdiv = first_row_offset;
3717 first_row_offset = (u32) do_div(tmpdiv, r5or6_blocks_per_row);
3718 r5or6_first_row_offset = first_row_offset;
3719 tmpdiv = last_block;
3720 r5or6_last_row_offset = do_div(tmpdiv, stripesize);
3721 tmpdiv = r5or6_last_row_offset;
3722 r5or6_last_row_offset = do_div(tmpdiv, r5or6_blocks_per_row);
3723 tmpdiv = r5or6_first_row_offset;
3724 (void) do_div(tmpdiv, map->strip_size);
3725 first_column = r5or6_first_column = tmpdiv;
3726 tmpdiv = r5or6_last_row_offset;
3727 (void) do_div(tmpdiv, map->strip_size);
3728 r5or6_last_column = tmpdiv;
3729#else
3730 first_row_offset = r5or6_first_row_offset =
3731 (u32)((first_block % stripesize) %
3732 r5or6_blocks_per_row);
3733
3734 r5or6_last_row_offset =
3735 (u32)((last_block % stripesize) %
3736 r5or6_blocks_per_row);
3737
3738 first_column = r5or6_first_column =
2b08b3e9 3739 r5or6_first_row_offset / le16_to_cpu(map->strip_size);
6b80b18f 3740 r5or6_last_column =
2b08b3e9 3741 r5or6_last_row_offset / le16_to_cpu(map->strip_size);
6b80b18f
ST		 3742#endif
3743 if (r5or6_first_column != r5or6_last_column)
3744 return IO_ACCEL_INELIGIBLE;
3745
3746 /* Request is eligible */
3747 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
2b08b3e9 3748 le16_to_cpu(map->row_cnt);
6b80b18f
ST		 3749
3750 map_index = (first_group *
2b08b3e9 3751 (le16_to_cpu(map->row_cnt) * total_disks_per_row)) +
6b80b18f
ST		 3752 (map_row * total_disks_per_row) + first_column;
3753 break;
3754 default:
3755 return IO_ACCEL_INELIGIBLE;
283b4a9b 3756 }
6b80b18f 3757
283b4a9b 3758 disk_handle = dd[map_index].ioaccel_handle;
2b08b3e9
DB		 3759 disk_block = le64_to_cpu(map->disk_starting_blk) +
3760 first_row * le16_to_cpu(map->strip_size) +
3761 (first_row_offset - first_column *
3762 le16_to_cpu(map->strip_size));
283b4a9b
SC		 3763 disk_block_cnt = block_cnt;
3764
3765 /* handle differing logical/physical block sizes */
3766 if (map->phys_blk_shift) {
3767 disk_block <<= map->phys_blk_shift;
3768 disk_block_cnt <<= map->phys_blk_shift;
3769 }
3770 BUG_ON(disk_block_cnt > 0xffff);
3771
3772 /* build the new CDB for the physical disk I/O */
3773 if (disk_block > 0xffffffff) {
3774 cdb[0] = is_write ? WRITE_16 : READ_16;
3775 cdb[1] = 0;
3776 cdb[2] = (u8) (disk_block >> 56);
3777 cdb[3] = (u8) (disk_block >> 48);
3778 cdb[4] = (u8) (disk_block >> 40);
3779 cdb[5] = (u8) (disk_block >> 32);
3780 cdb[6] = (u8) (disk_block >> 24);
3781 cdb[7] = (u8) (disk_block >> 16);
3782 cdb[8] = (u8) (disk_block >> 8);
3783 cdb[9] = (u8) (disk_block);
3784 cdb[10] = (u8) (disk_block_cnt >> 24);
3785 cdb[11] = (u8) (disk_block_cnt >> 16);
3786 cdb[12] = (u8) (disk_block_cnt >> 8);
3787 cdb[13] = (u8) (disk_block_cnt);
3788 cdb[14] = 0;
3789 cdb[15] = 0;
3790 cdb_len = 16;
3791 } else {
3792 cdb[0] = is_write ? WRITE_10 : READ_10;
3793 cdb[1] = 0;
3794 cdb[2] = (u8) (disk_block >> 24);
3795 cdb[3] = (u8) (disk_block >> 16);
3796 cdb[4] = (u8) (disk_block >> 8);
3797 cdb[5] = (u8) (disk_block);
3798 cdb[6] = 0;
3799 cdb[7] = (u8) (disk_block_cnt >> 8);
3800 cdb[8] = (u8) (disk_block_cnt);
3801 cdb[9] = 0;
3802 cdb_len = 10;
3803 }
3804 return hpsa_scsi_ioaccel_queue_command(h, c, disk_handle, cdb, cdb_len,
3805 dev->scsi3addr);
3806}
3807
574f05d3
SC		 3808/* Submit commands down the "normal" RAID stack path */
3809static int hpsa_ciss_submit(struct ctlr_info *h,
3810 struct CommandList *c, struct scsi_cmnd *cmd,
3811 unsigned char scsi3addr[])
edd16368 3812{
edd16368 3813 cmd->host_scribble = (unsigned char *) c;
edd16368
SC		 3814 c->cmd_type = CMD_SCSI;
3815 c->scsi_cmd = cmd;
3816 c->Header.ReplyQueue = 0; /* unused in simple mode */
3817 memcpy(&c->Header.LUN.LunAddrBytes[0], &scsi3addr[0], 8);
f2405db8 3818 c->Header.tag = cpu_to_le64((c->cmdindex << DIRECT_LOOKUP_SHIFT));
edd16368
SC		 3819
3820 /* Fill in the request block... */
3821
3822 c->Request.Timeout = 0;
3823 memset(c->Request.CDB, 0, sizeof(c->Request.CDB));
3824 BUG_ON(cmd->cmd_len > sizeof(c->Request.CDB));
3825 c->Request.CDBLen = cmd->cmd_len;
3826 memcpy(c->Request.CDB, cmd->cmnd, cmd->cmd_len);
edd16368
SC		 3827 switch (cmd->sc_data_direction) {
3828 case DMA_TO_DEVICE:
a505b86f
SC		 3829 c->Request.type_attr_dir =
3830 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_WRITE);
edd16368
SC		 3831 break;
3832 case DMA_FROM_DEVICE:
a505b86f
SC		 3833 c->Request.type_attr_dir =
3834 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 3835 break;
3836 case DMA_NONE:
a505b86f
SC		 3837 c->Request.type_attr_dir =
3838 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_NONE);
edd16368
SC		 3839 break;
3840 case DMA_BIDIRECTIONAL:
3841 /* This can happen if a buggy application does a scsi passthru
3842 * and sets both inlen and outlen to non-zero. ( see
3843 * ../scsi/scsi_ioctl.c:scsi_ioctl_send_command() )
3844 */
3845
a505b86f
SC		 3846 c->Request.type_attr_dir =
3847 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_RSVD);
edd16368
SC		 3848 /* This is technically wrong, and hpsa controllers should
3849 * reject it with CMD_INVALID, which is the most correct
3850 * response, but non-fibre backends appear to let it
3851 * slide by, and give the same results as if this field
3852 * were set correctly. Either way is acceptable for
3853 * our purposes here.
3854 */
3855
3856 break;
3857
3858 default:
3859 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
3860 cmd->sc_data_direction);
3861 BUG();
3862 break;
3863 }
3864
33a2ffce 3865 if (hpsa_scatter_gather(h, c, cmd) < 0) { /* Fill SG list */
edd16368
SC		 3866 cmd_free(h, c);
3867 return SCSI_MLQUEUE_HOST_BUSY;
3868 }
3869 enqueue_cmd_and_start_io(h, c);
3870 /* the cmd'll come back via intr handler in complete_scsi_command() */
3871 return 0;
3872}
3873
080ef1cc
DB		 3874static void hpsa_command_resubmit_worker(struct work_struct *work)
3875{
3876 struct scsi_cmnd *cmd;
3877 struct hpsa_scsi_dev_t *dev;
3878 struct CommandList *c =
3879 container_of(work, struct CommandList, work);
3880
3881 cmd = c->scsi_cmd;
3882 dev = cmd->device->hostdata;
3883 if (!dev) {
3884 cmd->result = DID_NO_CONNECT << 16;
3885 cmd->scsi_done(cmd);
3886 return;
3887 }
3888 if (hpsa_ciss_submit(c->h, c, cmd, dev->scsi3addr)) {
3889 /*
3890 * If we get here, it means dma mapping failed. Try
3891 * again via scsi mid layer, which will then get
3892 * SCSI_MLQUEUE_HOST_BUSY.
3893 */
3894 cmd->result = DID_IMM_RETRY << 16;
3895 cmd->scsi_done(cmd);
3896 }
3897}
3898
574f05d3
SC		 3899/* Running in struct Scsi_Host->host_lock less mode */
3900static int hpsa_scsi_queue_command(struct Scsi_Host *sh, struct scsi_cmnd *cmd)
3901{
3902 struct ctlr_info *h;
3903 struct hpsa_scsi_dev_t *dev;
3904 unsigned char scsi3addr[8];
3905 struct CommandList *c;
3906 int rc = 0;
3907
3908 /* Get the ptr to our adapter structure out of cmd->host. */
3909 h = sdev_to_hba(cmd->device);
3910 dev = cmd->device->hostdata;
3911 if (!dev) {
3912 cmd->result = DID_NO_CONNECT << 16;
3913 cmd->scsi_done(cmd);
3914 return 0;
3915 }
3916 memcpy(scsi3addr, dev->scsi3addr, sizeof(scsi3addr));
3917
3918 if (unlikely(lockup_detected(h))) {
3919 cmd->result = DID_ERROR << 16;
3920 cmd->scsi_done(cmd);
3921 return 0;
3922 }
3923 c = cmd_alloc(h);
3924 if (c == NULL) { /* trouble... */
3925 dev_err(&h->pdev->dev, "cmd_alloc returned NULL!\n");
3926 return SCSI_MLQUEUE_HOST_BUSY;
3927 }
3928
3929 /* Call alternate submit routine for I/O accelerated commands.
3930 * Retries always go down the normal I/O path.
3931 */
3932 if (likely(cmd->retries == 0 &&
3933 cmd->request->cmd_type == REQ_TYPE_FS &&
3934 h->acciopath_status)) {
3935
3936 cmd->host_scribble = (unsigned char *) c;
3937 c->cmd_type = CMD_SCSI;
3938 c->scsi_cmd = cmd;
3939
3940 if (dev->offload_enabled) {
3941 rc = hpsa_scsi_ioaccel_raid_map(h, c);
3942 if (rc == 0)
3943 return 0; /* Sent on ioaccel path */
3944 if (rc < 0) { /* scsi_dma_map failed. */
3945 cmd_free(h, c);
3946 return SCSI_MLQUEUE_HOST_BUSY;
3947 }
3948 } else if (dev->ioaccel_handle) {
3949 rc = hpsa_scsi_ioaccel_direct_map(h, c);
3950 if (rc == 0)
3951 return 0; /* Sent on direct map path */
3952 if (rc < 0) { /* scsi_dma_map failed. */
3953 cmd_free(h, c);
3954 return SCSI_MLQUEUE_HOST_BUSY;
3955 }
3956 }
3957 }
3958 return hpsa_ciss_submit(h, c, cmd, scsi3addr);
3959}
3960
5f389360
SC		 3961static int do_not_scan_if_controller_locked_up(struct ctlr_info *h)
3962{
3963 unsigned long flags;
3964
3965 /*
3966 * Don't let rescans be initiated on a controller known
3967 * to be locked up. If the controller locks up *during*
3968 * a rescan, that thread is probably hosed, but at least
3969 * we can prevent new rescan threads from piling up on a
3970 * locked up controller.
3971 */
094963da 3972 if (unlikely(lockup_detected(h))) {
5f389360
SC		 3973 spin_lock_irqsave(&h->scan_lock, flags);
3974 h->scan_finished = 1;
3975 wake_up_all(&h->scan_wait_queue);
3976 spin_unlock_irqrestore(&h->scan_lock, flags);
3977 return 1;
3978 }
5f389360
SC		 3979 return 0;
3980}
3981
a08a8471
SC		 3982static void hpsa_scan_start(struct Scsi_Host *sh)
3983{
3984 struct ctlr_info *h = shost_to_hba(sh);
3985 unsigned long flags;
3986
5f389360
SC		 3987 if (do_not_scan_if_controller_locked_up(h))
3988 return;
3989
a08a8471
SC		 3990 /* wait until any scan already in progress is finished. */
3991 while (1) {
3992 spin_lock_irqsave(&h->scan_lock, flags);
3993 if (h->scan_finished)
3994 break;
3995 spin_unlock_irqrestore(&h->scan_lock, flags);
3996 wait_event(h->scan_wait_queue, h->scan_finished);
3997 /* Note: We don't need to worry about a race between this
3998 * thread and driver unload because the midlayer will
3999 * have incremented the reference count, so unload won't
4000 * happen if we're in here.
4001 */
4002 }
4003 h->scan_finished = 0; /* mark scan as in progress */
4004 spin_unlock_irqrestore(&h->scan_lock, flags);
4005
5f389360
SC		 4006 if (do_not_scan_if_controller_locked_up(h))
4007 return;
4008
a08a8471
SC		 4009 hpsa_update_scsi_devices(h, h->scsi_host->host_no);
4010
4011 spin_lock_irqsave(&h->scan_lock, flags);
4012 h->scan_finished = 1; /* mark scan as finished. */
4013 wake_up_all(&h->scan_wait_queue);
4014 spin_unlock_irqrestore(&h->scan_lock, flags);
4015}
4016
7c0a0229
DB		 4017static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth)
4018{
4019 struct ctlr_info *h = sdev_to_hba(sdev);
4020
4021 if (qdepth < 1)
4022 qdepth = 1;
4023 else
4024 if (qdepth > h->nr_cmds)
4025 qdepth = h->nr_cmds;
4026 scsi_change_queue_depth(sdev, qdepth);
4027 return sdev->queue_depth;
4028}
4029
a08a8471
SC		 4030static int hpsa_scan_finished(struct Scsi_Host *sh,
4031 unsigned long elapsed_time)
4032{
4033 struct ctlr_info *h = shost_to_hba(sh);
4034 unsigned long flags;
4035 int finished;
4036
4037 spin_lock_irqsave(&h->scan_lock, flags);
4038 finished = h->scan_finished;
4039 spin_unlock_irqrestore(&h->scan_lock, flags);
4040 return finished;
4041}
4042
edd16368
SC		 4043static void hpsa_unregister_scsi(struct ctlr_info *h)
4044{
4045 /* we are being forcibly unloaded, and may not refuse. */
4046 scsi_remove_host(h->scsi_host);
4047 scsi_host_put(h->scsi_host);
4048 h->scsi_host = NULL;
4049}
4050
4051static int hpsa_register_scsi(struct ctlr_info *h)
4052{
b705690d
SC		 4053 struct Scsi_Host *sh;
4054 int error;
edd16368 4055
b705690d
SC		 4056 sh = scsi_host_alloc(&hpsa_driver_template, sizeof(h));
4057 if (sh == NULL)
4058 goto fail;
4059
4060 sh->io_port = 0;
4061 sh->n_io_port = 0;
4062 sh->this_id = -1;
4063 sh->max_channel = 3;
4064 sh->max_cmd_len = MAX_COMMAND_SIZE;
4065 sh->max_lun = HPSA_MAX_LUN;
4066 sh->max_id = HPSA_MAX_LUN;
d54c5c24
SC		 4067 sh->can_queue = h->nr_cmds -
4068 HPSA_CMDS_RESERVED_FOR_ABORTS -
4069 HPSA_CMDS_RESERVED_FOR_DRIVER -
4070 HPSA_MAX_CONCURRENT_PASSTHRUS;
316b221a
SC		 4071 if (h->hba_mode_enabled)
4072 sh->cmd_per_lun = 7;
4073 else
d54c5c24 4074 sh->cmd_per_lun = sh->can_queue;
b705690d
SC		 4075 sh->sg_tablesize = h->maxsgentries;
4076 h->scsi_host = sh;
4077 sh->hostdata[0] = (unsigned long) h;
4078 sh->irq = h->intr[h->intr_mode];
4079 sh->unique_id = sh->irq;
4080 error = scsi_add_host(sh, &h->pdev->dev);
4081 if (error)
4082 goto fail_host_put;
4083 scsi_scan_host(sh);
4084 return 0;
4085
4086 fail_host_put:
4087 dev_err(&h->pdev->dev, "%s: scsi_add_host"
4088 " failed for controller %d\n", __func__, h->ctlr);
4089 scsi_host_put(sh);
4090 return error;
4091 fail:
4092 dev_err(&h->pdev->dev, "%s: scsi_host_alloc"
4093 " failed for controller %d\n", __func__, h->ctlr);
4094 return -ENOMEM;
edd16368
SC		 4095}
4096
4097static int wait_for_device_to_become_ready(struct ctlr_info *h,
4098 unsigned char lunaddr[])
4099{
8919358e 4100 int rc;
edd16368
SC		 4101 int count = 0;
4102 int waittime = 1; /* seconds */
4103 struct CommandList *c;
4104
45fcb86e 4105 c = cmd_alloc(h);
edd16368
SC		 4106 if (!c) {
4107 dev_warn(&h->pdev->dev, "out of memory in "
4108 "wait_for_device_to_become_ready.\n");
4109 return IO_ERROR;
4110 }
4111
4112 /* Send test unit ready until device ready, or give up. */
4113 while (count < HPSA_TUR_RETRY_LIMIT) {
4114
4115 /* Wait for a bit. do this first, because if we send
4116 * the TUR right away, the reset will just abort it.
4117 */
4118 msleep(1000 * waittime);
4119 count++;
8919358e 4120 rc = 0; /* Device ready. */
edd16368
SC		 4121
4122 /* Increase wait time with each try, up to a point. */
4123 if (waittime < HPSA_MAX_WAIT_INTERVAL_SECS)
4124 waittime = waittime * 2;
4125
a2dac136
SC		 4126 /* Send the Test Unit Ready, fill_cmd can't fail, no mapping */
4127 (void) fill_cmd(c, TEST_UNIT_READY, h,
4128 NULL, 0, 0, lunaddr, TYPE_CMD);
edd16368
SC		 4129 hpsa_scsi_do_simple_cmd_core(h, c);
4130 /* no unmap needed here because no data xfer. */
4131
4132 if (c->err_info->CommandStatus == CMD_SUCCESS)
4133 break;
4134
4135 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
4136 c->err_info->ScsiStatus == SAM_STAT_CHECK_CONDITION &&
4137 (c->err_info->SenseInfo[2] == NO_SENSE ||
4138 c->err_info->SenseInfo[2] == UNIT_ATTENTION))
4139 break;
4140
4141 dev_warn(&h->pdev->dev, "waiting %d secs "
4142 "for device to become ready.\n", waittime);
4143 rc = 1; /* device not ready. */
4144 }
4145
4146 if (rc)
4147 dev_warn(&h->pdev->dev, "giving up on device.\n");
4148 else
4149 dev_warn(&h->pdev->dev, "device is ready.\n");
4150
45fcb86e 4151 cmd_free(h, c);
edd16368
SC		 4152 return rc;
4153}
4154
4155/* Need at least one of these error handlers to keep ../scsi/hosts.c from
4156 * complaining. Doing a host- or bus-reset can't do anything good here.
4157 */
4158static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd)
4159{
4160 int rc;
4161 struct ctlr_info *h;
4162 struct hpsa_scsi_dev_t *dev;
4163
4164 /* find the controller to which the command to be aborted was sent */
4165 h = sdev_to_hba(scsicmd->device);
4166 if (h == NULL) /* paranoia */
4167 return FAILED;
edd16368
SC		 4168 dev = scsicmd->device->hostdata;
4169 if (!dev) {
4170 dev_err(&h->pdev->dev, "hpsa_eh_device_reset_handler: "
4171 "device lookup failed.\n");
4172 return FAILED;
4173 }
d416b0c7
SC		 4174 dev_warn(&h->pdev->dev, "resetting device %d:%d:%d:%d\n",
4175 h->scsi_host->host_no, dev->bus, dev->target, dev->lun);
edd16368 4176 /* send a reset to the SCSI LUN which the command was sent to */
bf711ac6 4177 rc = hpsa_send_reset(h, dev->scsi3addr, HPSA_RESET_TYPE_LUN);
edd16368
SC		 4178 if (rc == 0 && wait_for_device_to_become_ready(h, dev->scsi3addr) == 0)
4179 return SUCCESS;
4180
4181 dev_warn(&h->pdev->dev, "resetting device failed.\n");
4182 return FAILED;
4183}
4184
6cba3f19
SC		 4185static void swizzle_abort_tag(u8 *tag)
4186{
4187 u8 original_tag[8];
4188
4189 memcpy(original_tag, tag, 8);
4190 tag[0] = original_tag[3];
4191 tag[1] = original_tag[2];
4192 tag[2] = original_tag[1];
4193 tag[3] = original_tag[0];
4194 tag[4] = original_tag[7];
4195 tag[5] = original_tag[6];
4196 tag[6] = original_tag[5];
4197 tag[7] = original_tag[4];
4198}
4199
17eb87d2 4200static void hpsa_get_tag(struct ctlr_info *h,
2b08b3e9 4201 struct CommandList *c, __le32 *taglower, __le32 *tagupper)
17eb87d2 4202{
2b08b3e9 4203 u64 tag;
17eb87d2
ST		 4204 if (c->cmd_type == CMD_IOACCEL1) {
4205 struct io_accel1_cmd *cm1 = (struct io_accel1_cmd *)
4206 &h->ioaccel_cmd_pool[c->cmdindex];
2b08b3e9
DB		 4207 tag = le64_to_cpu(cm1->tag);
4208 *tagupper = cpu_to_le32(tag >> 32);
4209 *taglower = cpu_to_le32(tag);
54b6e9e9
ST		 4210 return;
4211 }
4212 if (c->cmd_type == CMD_IOACCEL2) {
4213 struct io_accel2_cmd *cm2 = (struct io_accel2_cmd *)
4214 &h->ioaccel2_cmd_pool[c->cmdindex];
dd0e19f3
ST		 4215 /* upper tag not used in ioaccel2 mode */
4216 memset(tagupper, 0, sizeof(*tagupper));
4217 *taglower = cm2->Tag;
54b6e9e9 4218 return;
17eb87d2 4219 }
2b08b3e9
DB		 4220 tag = le64_to_cpu(c->Header.tag);
4221 *tagupper = cpu_to_le32(tag >> 32);
4222 *taglower = cpu_to_le32(tag);
17eb87d2
ST		 4223}
4224
75167d2c 4225static int hpsa_send_abort(struct ctlr_info *h, unsigned char *scsi3addr,
6cba3f19 4226 struct CommandList *abort, int swizzle)
75167d2c
SC		 4227{
4228 int rc = IO_OK;
4229 struct CommandList *c;
4230 struct ErrorInfo *ei;
2b08b3e9 4231 __le32 tagupper, taglower;
75167d2c 4232
45fcb86e 4233 c = cmd_alloc(h);
75167d2c 4234 if (c == NULL) { /* trouble... */
45fcb86e 4235 dev_warn(&h->pdev->dev, "cmd_alloc returned NULL!\n");
75167d2c
SC		 4236 return -ENOMEM;
4237 }
4238
a2dac136
SC		 4239 /* fill_cmd can't fail here, no buffer to map */
4240 (void) fill_cmd(c, HPSA_ABORT_MSG, h, abort,
4241 0, 0, scsi3addr, TYPE_MSG);
6cba3f19
SC		 4242 if (swizzle)
4243 swizzle_abort_tag(&c->Request.CDB[4]);
75167d2c 4244 hpsa_scsi_do_simple_cmd_core(h, c);
17eb87d2 4245 hpsa_get_tag(h, abort, &taglower, &tagupper);
75167d2c 4246 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: do_simple_cmd_core completed.\n",
17eb87d2 4247 __func__, tagupper, taglower);
75167d2c
SC		 4248 /* no unmap needed here because no data xfer. */
4249
4250 ei = c->err_info;
4251 switch (ei->CommandStatus) {
4252 case CMD_SUCCESS:
4253 break;
4254 case CMD_UNABORTABLE: /* Very common, don't make noise. */
4255 rc = -1;
4256 break;
4257 default:
4258 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: interpreting error.\n",
17eb87d2 4259 __func__, tagupper, taglower);
d1e8beac 4260 hpsa_scsi_interpret_error(h, c);
75167d2c
SC		 4261 rc = -1;
4262 break;
4263 }
45fcb86e 4264 cmd_free(h, c);
dd0e19f3
ST		 4265 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n",
4266 __func__, tagupper, taglower);
75167d2c
SC		 4267 return rc;
4268}
4269
54b6e9e9
ST		 4270/* ioaccel2 path firmware cannot handle abort task requests.
4271 * Change abort requests to physical target reset, and send to the
4272 * address of the physical disk used for the ioaccel 2 command.
4273 * Return 0 on success (IO_OK)
4274 * -1 on failure
4275 */
4276
4277static int hpsa_send_reset_as_abort_ioaccel2(struct ctlr_info *h,
4278 unsigned char *scsi3addr, struct CommandList *abort)
4279{
4280 int rc = IO_OK;
4281 struct scsi_cmnd *scmd; /* scsi command within request being aborted */
4282 struct hpsa_scsi_dev_t *dev; /* device to which scsi cmd was sent */
4283 unsigned char phys_scsi3addr[8]; /* addr of phys disk with volume */
4284 unsigned char *psa = &phys_scsi3addr[0];
4285
4286 /* Get a pointer to the hpsa logical device. */
4287 scmd = (struct scsi_cmnd *) abort->scsi_cmd;
4288 dev = (struct hpsa_scsi_dev_t *)(scmd->device->hostdata);
4289 if (dev == NULL) {
4290 dev_warn(&h->pdev->dev,
4291 "Cannot abort: no device pointer for command.\n");
4292 return -1; /* not abortable */
4293 }
4294
2ba8bfc8
SC		 4295 if (h->raid_offload_debug > 0)
4296 dev_info(&h->pdev->dev,
4297 "Reset as abort: Abort requested on C%d:B%d:T%d:L%d scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4298 h->scsi_host->host_no, dev->bus, dev->target, dev->lun,
4299 scsi3addr[0], scsi3addr[1], scsi3addr[2], scsi3addr[3],
4300 scsi3addr[4], scsi3addr[5], scsi3addr[6], scsi3addr[7]);
4301
54b6e9e9
ST		 4302 if (!dev->offload_enabled) {
4303 dev_warn(&h->pdev->dev,
4304 "Can't abort: device is not operating in HP SSD Smart Path mode.\n");
4305 return -1; /* not abortable */
4306 }
4307
4308 /* Incoming scsi3addr is logical addr. We need physical disk addr. */
4309 if (!hpsa_get_pdisk_of_ioaccel2(h, abort, psa)) {
4310 dev_warn(&h->pdev->dev, "Can't abort: Failed lookup of physical address.\n");
4311 return -1; /* not abortable */
4312 }
4313
4314 /* send the reset */
2ba8bfc8
SC		 4315 if (h->raid_offload_debug > 0)
4316 dev_info(&h->pdev->dev,
4317 "Reset as abort: Resetting physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4318 psa[0], psa[1], psa[2], psa[3],
4319 psa[4], psa[5], psa[6], psa[7]);
54b6e9e9
ST		 4320 rc = hpsa_send_reset(h, psa, HPSA_RESET_TYPE_TARGET);
4321 if (rc != 0) {
4322 dev_warn(&h->pdev->dev,
4323 "Reset as abort: Failed on physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4324 psa[0], psa[1], psa[2], psa[3],
4325 psa[4], psa[5], psa[6], psa[7]);
4326 return rc; /* failed to reset */
4327 }
4328
4329 /* wait for device to recover */
4330 if (wait_for_device_to_become_ready(h, psa) != 0) {
4331 dev_warn(&h->pdev->dev,
4332 "Reset as abort: Failed: Device never recovered from reset: 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4333 psa[0], psa[1], psa[2], psa[3],
4334 psa[4], psa[5], psa[6], psa[7]);
4335 return -1; /* failed to recover */
4336 }
4337
4338 /* device recovered */
4339 dev_info(&h->pdev->dev,
4340 "Reset as abort: Device recovered from reset: scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4341 psa[0], psa[1], psa[2], psa[3],
4342 psa[4], psa[5], psa[6], psa[7]);
4343
4344 return rc; /* success */
4345}
4346
6cba3f19
SC		 4347/* Some Smart Arrays need the abort tag swizzled, and some don't. It's hard to
4348 * tell which kind we're dealing with, so we send the abort both ways. There
4349 * shouldn't be any collisions between swizzled and unswizzled tags due to the
4350 * way we construct our tags but we check anyway in case the assumptions which
4351 * make this true someday become false.
4352 */
4353static int hpsa_send_abort_both_ways(struct ctlr_info *h,
4354 unsigned char *scsi3addr, struct CommandList *abort)
4355{
54b6e9e9
ST		 4356 /* ioccelerator mode 2 commands should be aborted via the
4357 * accelerated path, since RAID path is unaware of these commands,
4358 * but underlying firmware can't handle abort TMF.
4359 * Change abort to physical device reset.
4360 */
4361 if (abort->cmd_type == CMD_IOACCEL2)
4362 return hpsa_send_reset_as_abort_ioaccel2(h, scsi3addr, abort);
4363
f2405db8
DB		 4364 return hpsa_send_abort(h, scsi3addr, abort, 0) &&
4365 hpsa_send_abort(h, scsi3addr, abort, 1);
6cba3f19
SC		 4366}
4367
75167d2c
SC		 4368/* Send an abort for the specified command.
4369 * If the device and controller support it,
4370 * send a task abort request.
4371 */
4372static int hpsa_eh_abort_handler(struct scsi_cmnd *sc)
4373{
4374
4375 int i, rc;
4376 struct ctlr_info *h;
4377 struct hpsa_scsi_dev_t *dev;
4378 struct CommandList *abort; /* pointer to command to be aborted */
75167d2c
SC		 4379 struct scsi_cmnd *as; /* ptr to scsi cmd inside aborted command. */
4380 char msg[256]; /* For debug messaging. */
4381 int ml = 0;
2b08b3e9 4382 __le32 tagupper, taglower;
75167d2c
SC		 4383
4384 /* Find the controller of the command to be aborted */
4385 h = sdev_to_hba(sc->device);
4386 if (WARN(h == NULL,
4387 "ABORT REQUEST FAILED, Controller lookup failed.\n"))
4388 return FAILED;
4389
4390 /* Check that controller supports some kind of task abort */
4391 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags) &&
4392 !(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
4393 return FAILED;
4394
4395 memset(msg, 0, sizeof(msg));
9cb78c16 4396 ml += sprintf(msg+ml, "ABORT REQUEST on C%d:B%d:T%d:L%llu ",
75167d2c
SC		 4397 h->scsi_host->host_no, sc->device->channel,
4398 sc->device->id, sc->device->lun);
4399
4400 /* Find the device of the command to be aborted */
4401 dev = sc->device->hostdata;
4402 if (!dev) {
4403 dev_err(&h->pdev->dev, "%s FAILED, Device lookup failed.\n",
4404 msg);
4405 return FAILED;
4406 }
4407
4408 /* Get SCSI command to be aborted */
4409 abort = (struct CommandList *) sc->host_scribble;
4410 if (abort == NULL) {
4411 dev_err(&h->pdev->dev, "%s FAILED, Command to abort is NULL.\n",
4412 msg);
4413 return FAILED;
4414 }
17eb87d2
ST		 4415 hpsa_get_tag(h, abort, &taglower, &tagupper);
4416 ml += sprintf(msg+ml, "Tag:0x%08x:%08x ", tagupper, taglower);
75167d2c
SC		 4417 as = (struct scsi_cmnd *) abort->scsi_cmd;
4418 if (as != NULL)
4419 ml += sprintf(msg+ml, "Command:0x%x SN:0x%lx ",
4420 as->cmnd[0], as->serial_number);
4421 dev_dbg(&h->pdev->dev, "%s\n", msg);
4422 dev_warn(&h->pdev->dev, "Abort request on C%d:B%d:T%d:L%d\n",
4423 h->scsi_host->host_no, dev->bus, dev->target, dev->lun);
75167d2c
SC		 4424 /*
4425 * Command is in flight, or possibly already completed
4426 * by the firmware (but not to the scsi mid layer) but we can't
4427 * distinguish which. Send the abort down.
4428 */
6cba3f19 4429 rc = hpsa_send_abort_both_ways(h, dev->scsi3addr, abort);
75167d2c
SC		 4430 if (rc != 0) {
4431 dev_dbg(&h->pdev->dev, "%s Request FAILED.\n", msg);
4432 dev_warn(&h->pdev->dev, "FAILED abort on device C%d:B%d:T%d:L%d\n",
4433 h->scsi_host->host_no,
4434 dev->bus, dev->target, dev->lun);
4435 return FAILED;
4436 }
4437 dev_info(&h->pdev->dev, "%s REQUEST SUCCEEDED.\n", msg);
4438
4439 /* If the abort(s) above completed and actually aborted the
4440 * command, then the command to be aborted should already be
4441 * completed. If not, wait around a bit more to see if they
4442 * manage to complete normally.
4443 */
4444#define ABORT_COMPLETE_WAIT_SECS 30
4445 for (i = 0; i < ABORT_COMPLETE_WAIT_SECS * 10; i++) {
f2405db8
DB		 4446 if (test_bit(abort->cmdindex & (BITS_PER_LONG - 1),
4447 h->cmd_pool_bits +
4448 (abort->cmdindex / BITS_PER_LONG)))
4449 msleep(100);
4450 else
75167d2c 4451 return SUCCESS;
75167d2c
SC		 4452 }
4453 dev_warn(&h->pdev->dev, "%s FAILED. Aborted command has not completed after %d seconds.\n",
4454 msg, ABORT_COMPLETE_WAIT_SECS);
4455 return FAILED;
4456}
4457
4458
edd16368
SC		 4459/*
4460 * For operations that cannot sleep, a command block is allocated at init,
4461 * and managed by cmd_alloc() and cmd_free() using a simple bitmap to track
4462 * which ones are free or in use. Lock must be held when calling this.
4463 * cmd_free() is the complement.
4464 */
4465static struct CommandList *cmd_alloc(struct ctlr_info *h)
4466{
4467 struct CommandList *c;
4468 int i;
4469 union u64bit temp64;
4470 dma_addr_t cmd_dma_handle, err_dma_handle;
4c413128
SC		 4471 int loopcount;
4472
4473 /* There is some *extremely* small but non-zero chance that that
4474 * multiple threads could get in here, and one thread could
4475 * be scanning through the list of bits looking for a free
4476 * one, but the free ones are always behind him, and other
4477 * threads sneak in behind him and eat them before he can
4478 * get to them, so that while there is always a free one, a
4479 * very unlucky thread might be starved anyway, never able to
4480 * beat the other threads. In reality, this happens so
4481 * infrequently as to be indistinguishable from never.
4482 */
edd16368 4483
4c413128 4484 loopcount = 0;
edd16368
SC		 4485 do {
4486 i = find_first_zero_bit(h->cmd_pool_bits, h->nr_cmds);
4c413128
SC		 4487 if (i == h->nr_cmds)
4488 i = 0;
4489 loopcount++;
4490 } while (test_and_set_bit(i & (BITS_PER_LONG - 1),
4491 h->cmd_pool_bits + (i / BITS_PER_LONG)) != 0 &&
4492 loopcount < 10);
4493
4494 /* Thread got starved? We do not expect this to ever happen. */
4495 if (loopcount >= 10)
4496 return NULL;
e16a33ad 4497
edd16368
SC		 4498 c = h->cmd_pool + i;
4499 memset(c, 0, sizeof(*c));
f2405db8
DB		 4500 c->Header.tag = cpu_to_le64((u64) i << DIRECT_LOOKUP_SHIFT);
4501 cmd_dma_handle = h->cmd_pool_dhandle + i * sizeof(*c);
edd16368
SC		 4502 c->err_info = h->errinfo_pool + i;
4503 memset(c->err_info, 0, sizeof(*c->err_info));
4504 err_dma_handle = h->errinfo_pool_dhandle
4505 + i * sizeof(*c->err_info);
edd16368
SC		 4506
4507 c->cmdindex = i;
4508
01a02ffc
SC		 4509 c->busaddr = (u32) cmd_dma_handle;
4510 temp64.val = (u64) err_dma_handle;
50a0decf
SC		 4511 c->ErrDesc.Addr = cpu_to_le64(err_dma_handle);
4512 c->ErrDesc.Len = cpu_to_le32(sizeof(*c->err_info));
edd16368
SC		 4513
4514 c->h = h;
4515 return c;
4516}
4517
edd16368
SC		 4518static void cmd_free(struct ctlr_info *h, struct CommandList *c)
4519{
4520 int i;
4521
4522 i = c - h->cmd_pool;
4523 clear_bit(i & (BITS_PER_LONG - 1),
4524 h->cmd_pool_bits + (i / BITS_PER_LONG));
edd16368
SC		 4525}
4526
edd16368
SC		 4527#ifdef CONFIG_COMPAT
4528
42a91641
DB		 4529static int hpsa_ioctl32_passthru(struct scsi_device *dev, int cmd,
4530 void __user *arg)
edd16368
SC		 4531{
4532 IOCTL32_Command_struct __user *arg32 =
4533 (IOCTL32_Command_struct __user *) arg;
4534 IOCTL_Command_struct arg64;
4535 IOCTL_Command_struct __user *p = compat_alloc_user_space(sizeof(arg64));
4536 int err;
4537 u32 cp;
4538
938abd84 4539 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 4540 err = 0;
4541 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
4542 sizeof(arg64.LUN_info));
4543 err |= copy_from_user(&arg64.Request, &arg32->Request,
4544 sizeof(arg64.Request));
4545 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
4546 sizeof(arg64.error_info));
4547 err |= get_user(arg64.buf_size, &arg32->buf_size);
4548 err |= get_user(cp, &arg32->buf);
4549 arg64.buf = compat_ptr(cp);
4550 err |= copy_to_user(p, &arg64, sizeof(arg64));
4551
4552 if (err)
4553 return -EFAULT;
4554
42a91641 4555 err = hpsa_ioctl(dev, CCISS_PASSTHRU, p);
edd16368
SC		 4556 if (err)
4557 return err;
4558 err |= copy_in_user(&arg32->error_info, &p->error_info,
4559 sizeof(arg32->error_info));
4560 if (err)
4561 return -EFAULT;
4562 return err;
4563}
4564
4565static int hpsa_ioctl32_big_passthru(struct scsi_device *dev,
42a91641 4566 int cmd, void __user *arg)
edd16368
SC		 4567{
4568 BIG_IOCTL32_Command_struct __user *arg32 =
4569 (BIG_IOCTL32_Command_struct __user *) arg;
4570 BIG_IOCTL_Command_struct arg64;
4571 BIG_IOCTL_Command_struct __user *p =
4572 compat_alloc_user_space(sizeof(arg64));
4573 int err;
4574 u32 cp;
4575
938abd84 4576 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 4577 err = 0;
4578 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
4579 sizeof(arg64.LUN_info));
4580 err |= copy_from_user(&arg64.Request, &arg32->Request,
4581 sizeof(arg64.Request));
4582 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
4583 sizeof(arg64.error_info));
4584 err |= get_user(arg64.buf_size, &arg32->buf_size);
4585 err |= get_user(arg64.malloc_size, &arg32->malloc_size);
4586 err |= get_user(cp, &arg32->buf);
4587 arg64.buf = compat_ptr(cp);
4588 err |= copy_to_user(p, &arg64, sizeof(arg64));
4589
4590 if (err)
4591 return -EFAULT;
4592
42a91641 4593 err = hpsa_ioctl(dev, CCISS_BIG_PASSTHRU, p);
edd16368
SC		 4594 if (err)
4595 return err;
4596 err |= copy_in_user(&arg32->error_info, &p->error_info,
4597 sizeof(arg32->error_info));
4598 if (err)
4599 return -EFAULT;
4600 return err;
4601}
71fe75a7 4602
42a91641 4603static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void __user *arg)
71fe75a7
SC		 4604{
4605 switch (cmd) {
4606 case CCISS_GETPCIINFO:
4607 case CCISS_GETINTINFO:
4608 case CCISS_SETINTINFO:
4609 case CCISS_GETNODENAME:
4610 case CCISS_SETNODENAME:
4611 case CCISS_GETHEARTBEAT:
4612 case CCISS_GETBUSTYPES:
4613 case CCISS_GETFIRMVER:
4614 case CCISS_GETDRIVVER:
4615 case CCISS_REVALIDVOLS:
4616 case CCISS_DEREGDISK:
4617 case CCISS_REGNEWDISK:
4618 case CCISS_REGNEWD:
4619 case CCISS_RESCANDISK:
4620 case CCISS_GETLUNINFO:
4621 return hpsa_ioctl(dev, cmd, arg);
4622
4623 case CCISS_PASSTHRU32:
4624 return hpsa_ioctl32_passthru(dev, cmd, arg);
4625 case CCISS_BIG_PASSTHRU32:
4626 return hpsa_ioctl32_big_passthru(dev, cmd, arg);
4627
4628 default:
4629 return -ENOIOCTLCMD;
4630 }
4631}
edd16368
SC		 4632#endif
4633
4634static int hpsa_getpciinfo_ioctl(struct ctlr_info *h, void __user *argp)
4635{
4636 struct hpsa_pci_info pciinfo;
4637
4638 if (!argp)
4639 return -EINVAL;
4640 pciinfo.domain = pci_domain_nr(h->pdev->bus);
4641 pciinfo.bus = h->pdev->bus->number;
4642 pciinfo.dev_fn = h->pdev->devfn;
4643 pciinfo.board_id = h->board_id;
4644 if (copy_to_user(argp, &pciinfo, sizeof(pciinfo)))
4645 return -EFAULT;
4646 return 0;
4647}
4648
4649static int hpsa_getdrivver_ioctl(struct ctlr_info *h, void __user *argp)
4650{
4651 DriverVer_type DriverVer;
4652 unsigned char vmaj, vmin, vsubmin;
4653 int rc;
4654
4655 rc = sscanf(HPSA_DRIVER_VERSION, "%hhu.%hhu.%hhu",
4656 &vmaj, &vmin, &vsubmin);
4657 if (rc != 3) {
4658 dev_info(&h->pdev->dev, "driver version string '%s' "
4659 "unrecognized.", HPSA_DRIVER_VERSION);
4660 vmaj = 0;
4661 vmin = 0;
4662 vsubmin = 0;
4663 }
4664 DriverVer = (vmaj << 16) | (vmin << 8) | vsubmin;
4665 if (!argp)
4666 return -EINVAL;
4667 if (copy_to_user(argp, &DriverVer, sizeof(DriverVer_type)))
4668 return -EFAULT;
4669 return 0;
4670}
4671
4672static int hpsa_passthru_ioctl(struct ctlr_info *h, void __user *argp)
4673{
4674 IOCTL_Command_struct iocommand;
4675 struct CommandList *c;
4676 char *buff = NULL;
50a0decf 4677 u64 temp64;
c1f63c8f 4678 int rc = 0;
edd16368
SC		 4679
4680 if (!argp)
4681 return -EINVAL;
4682 if (!capable(CAP_SYS_RAWIO))
4683 return -EPERM;
4684 if (copy_from_user(&iocommand, argp, sizeof(iocommand)))
4685 return -EFAULT;
4686 if ((iocommand.buf_size < 1) &&
4687 (iocommand.Request.Type.Direction != XFER_NONE)) {
4688 return -EINVAL;
4689 }
4690 if (iocommand.buf_size > 0) {
4691 buff = kmalloc(iocommand.buf_size, GFP_KERNEL);
4692 if (buff == NULL)
4693 return -EFAULT;
9233fb10 4694 if (iocommand.Request.Type.Direction & XFER_WRITE) {
b03a7771
SC		 4695 /* Copy the data into the buffer we created */
4696 if (copy_from_user(buff, iocommand.buf,
4697 iocommand.buf_size)) {
c1f63c8f
SC		 4698 rc = -EFAULT;
4699 goto out_kfree;
b03a7771
SC		 4700 }
4701 } else {
4702 memset(buff, 0, iocommand.buf_size);
edd16368 4703 }
b03a7771 4704 }
45fcb86e 4705 c = cmd_alloc(h);
edd16368 4706 if (c == NULL) {
c1f63c8f
SC		 4707 rc = -ENOMEM;
4708 goto out_kfree;
edd16368
SC		 4709 }
4710 /* Fill in the command type */
4711 c->cmd_type = CMD_IOCTL_PEND;
4712 /* Fill in Command Header */
4713 c->Header.ReplyQueue = 0; /* unused in simple mode */
4714 if (iocommand.buf_size > 0) { /* buffer to fill */
4715 c->Header.SGList = 1;
50a0decf 4716 c->Header.SGTotal = cpu_to_le16(1);
edd16368
SC		 4717 } else { /* no buffers to fill */
4718 c->Header.SGList = 0;
50a0decf 4719 c->Header.SGTotal = cpu_to_le16(0);
edd16368
SC		 4720 }
4721 memcpy(&c->Header.LUN, &iocommand.LUN_info, sizeof(c->Header.LUN));
edd16368
SC		 4722
4723 /* Fill in Request block */
4724 memcpy(&c->Request, &iocommand.Request,
4725 sizeof(c->Request));
4726
4727 /* Fill in the scatter gather information */
4728 if (iocommand.buf_size > 0) {
50a0decf 4729 temp64 = pci_map_single(h->pdev, buff,
edd16368 4730 iocommand.buf_size, PCI_DMA_BIDIRECTIONAL);
50a0decf
SC		 4731 if (dma_mapping_error(&h->pdev->dev, (dma_addr_t) temp64)) {
4732 c->SG[0].Addr = cpu_to_le64(0);
4733 c->SG[0].Len = cpu_to_le32(0);
bcc48ffa
SC		 4734 rc = -ENOMEM;
4735 goto out;
4736 }
50a0decf
SC		 4737 c->SG[0].Addr = cpu_to_le64(temp64);
4738 c->SG[0].Len = cpu_to_le32(iocommand.buf_size);
4739 c->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* not chaining */
edd16368 4740 }
a0c12413 4741 hpsa_scsi_do_simple_cmd_core_if_no_lockup(h, c);
c2dd32e0
SC		 4742 if (iocommand.buf_size > 0)
4743 hpsa_pci_unmap(h->pdev, c, 1, PCI_DMA_BIDIRECTIONAL);
edd16368
SC		 4744 check_ioctl_unit_attention(h, c);
4745
4746 /* Copy the error information out */
4747 memcpy(&iocommand.error_info, c->err_info,
4748 sizeof(iocommand.error_info));
4749 if (copy_to_user(argp, &iocommand, sizeof(iocommand))) {
c1f63c8f
SC		 4750 rc = -EFAULT;
4751 goto out;
edd16368 4752 }
9233fb10 4753 if ((iocommand.Request.Type.Direction & XFER_READ) &&
b03a7771 4754 iocommand.buf_size > 0) {
edd16368
SC		 4755 /* Copy the data out of the buffer we created */
4756 if (copy_to_user(iocommand.buf, buff, iocommand.buf_size)) {
c1f63c8f
SC		 4757 rc = -EFAULT;
4758 goto out;
edd16368
SC		 4759 }
4760 }
c1f63c8f 4761out:
45fcb86e 4762 cmd_free(h, c);
c1f63c8f
SC		 4763out_kfree:
4764 kfree(buff);
4765 return rc;
edd16368
SC		 4766}
4767
4768static int hpsa_big_passthru_ioctl(struct ctlr_info *h, void __user *argp)
4769{
4770 BIG_IOCTL_Command_struct *ioc;
4771 struct CommandList *c;
4772 unsigned char **buff = NULL;
4773 int *buff_size = NULL;
50a0decf 4774 u64 temp64;
edd16368
SC		 4775 BYTE sg_used = 0;
4776 int status = 0;
01a02ffc
SC		 4777 u32 left;
4778 u32 sz;
edd16368
SC		 4779 BYTE __user *data_ptr;
4780
4781 if (!argp)
4782 return -EINVAL;
4783 if (!capable(CAP_SYS_RAWIO))
4784 return -EPERM;
4785 ioc = (BIG_IOCTL_Command_struct *)
4786 kmalloc(sizeof(*ioc), GFP_KERNEL);
4787 if (!ioc) {
4788 status = -ENOMEM;
4789 goto cleanup1;
4790 }
4791 if (copy_from_user(ioc, argp, sizeof(*ioc))) {
4792 status = -EFAULT;
4793 goto cleanup1;
4794 }
4795 if ((ioc->buf_size < 1) &&
4796 (ioc->Request.Type.Direction != XFER_NONE)) {
4797 status = -EINVAL;
4798 goto cleanup1;
4799 }
4800 /* Check kmalloc limits using all SGs */
4801 if (ioc->malloc_size > MAX_KMALLOC_SIZE) {
4802 status = -EINVAL;
4803 goto cleanup1;
4804 }
d66ae08b 4805 if (ioc->buf_size > ioc->malloc_size * SG_ENTRIES_IN_CMD) {
edd16368
SC		 4806 status = -EINVAL;
4807 goto cleanup1;
4808 }
d66ae08b 4809 buff = kzalloc(SG_ENTRIES_IN_CMD * sizeof(char *), GFP_KERNEL);
edd16368
SC		 4810 if (!buff) {
4811 status = -ENOMEM;
4812 goto cleanup1;
4813 }
d66ae08b 4814 buff_size = kmalloc(SG_ENTRIES_IN_CMD * sizeof(int), GFP_KERNEL);
edd16368
SC		 4815 if (!buff_size) {
4816 status = -ENOMEM;
4817 goto cleanup1;
4818 }
4819 left = ioc->buf_size;
4820 data_ptr = ioc->buf;
4821 while (left) {
4822 sz = (left > ioc->malloc_size) ? ioc->malloc_size : left;
4823 buff_size[sg_used] = sz;
4824 buff[sg_used] = kmalloc(sz, GFP_KERNEL);
4825 if (buff[sg_used] == NULL) {
4826 status = -ENOMEM;
4827 goto cleanup1;
4828 }
9233fb10 4829 if (ioc->Request.Type.Direction & XFER_WRITE) {
edd16368 4830 if (copy_from_user(buff[sg_used], data_ptr, sz)) {
0758f4f7 4831 status = -EFAULT;
edd16368
SC		 4832 goto cleanup1;
4833 }
4834 } else
4835 memset(buff[sg_used], 0, sz);
4836 left -= sz;
4837 data_ptr += sz;
4838 sg_used++;
4839 }
45fcb86e 4840 c = cmd_alloc(h);
edd16368
SC		 4841 if (c == NULL) {
4842 status = -ENOMEM;
4843 goto cleanup1;
4844 }
4845 c->cmd_type = CMD_IOCTL_PEND;
4846 c->Header.ReplyQueue = 0;
50a0decf
SC		 4847 c->Header.SGList = (u8) sg_used;
4848 c->Header.SGTotal = cpu_to_le16(sg_used);
edd16368 4849 memcpy(&c->Header.LUN, &ioc->LUN_info, sizeof(c->Header.LUN));
edd16368
SC		 4850 memcpy(&c->Request, &ioc->Request, sizeof(c->Request));
4851 if (ioc->buf_size > 0) {
4852 int i;
4853 for (i = 0; i < sg_used; i++) {
50a0decf 4854 temp64 = pci_map_single(h->pdev, buff[i],
edd16368 4855 buff_size[i], PCI_DMA_BIDIRECTIONAL);
50a0decf
SC		 4856 if (dma_mapping_error(&h->pdev->dev,
4857 (dma_addr_t) temp64)) {
4858 c->SG[i].Addr = cpu_to_le64(0);
4859 c->SG[i].Len = cpu_to_le32(0);
bcc48ffa
SC		 4860 hpsa_pci_unmap(h->pdev, c, i,
4861 PCI_DMA_BIDIRECTIONAL);
4862 status = -ENOMEM;
e2d4a1f6 4863 goto cleanup0;
bcc48ffa 4864 }
50a0decf
SC		 4865 c->SG[i].Addr = cpu_to_le64(temp64);
4866 c->SG[i].Len = cpu_to_le32(buff_size[i]);
4867 c->SG[i].Ext = cpu_to_le32(0);
edd16368 4868 }
50a0decf 4869 c->SG[--i].Ext = cpu_to_le32(HPSA_SG_LAST);
edd16368 4870 }
a0c12413 4871 hpsa_scsi_do_simple_cmd_core_if_no_lockup(h, c);
b03a7771
SC		 4872 if (sg_used)
4873 hpsa_pci_unmap(h->pdev, c, sg_used, PCI_DMA_BIDIRECTIONAL);
edd16368
SC		 4874 check_ioctl_unit_attention(h, c);
4875 /* Copy the error information out */
4876 memcpy(&ioc->error_info, c->err_info, sizeof(ioc->error_info));
4877 if (copy_to_user(argp, ioc, sizeof(*ioc))) {
edd16368 4878 status = -EFAULT;
e2d4a1f6 4879 goto cleanup0;
edd16368 4880 }
9233fb10 4881 if ((ioc->Request.Type.Direction & XFER_READ) && ioc->buf_size > 0) {
2b08b3e9
DB		 4882 int i;
4883
edd16368
SC		 4884 /* Copy the data out of the buffer we created */
4885 BYTE __user *ptr = ioc->buf;
4886 for (i = 0; i < sg_used; i++) {
4887 if (copy_to_user(ptr, buff[i], buff_size[i])) {
edd16368 4888 status = -EFAULT;
e2d4a1f6 4889 goto cleanup0;
edd16368
SC		 4890 }
4891 ptr += buff_size[i];
4892 }
4893 }
edd16368 4894 status = 0;
e2d4a1f6 4895cleanup0:
45fcb86e 4896 cmd_free(h, c);
edd16368
SC		 4897cleanup1:
4898 if (buff) {
2b08b3e9
DB		 4899 int i;
4900
edd16368
SC		 4901 for (i = 0; i < sg_used; i++)
4902 kfree(buff[i]);
4903 kfree(buff);
4904 }
4905 kfree(buff_size);
4906 kfree(ioc);
4907 return status;
4908}
4909
4910static void check_ioctl_unit_attention(struct ctlr_info *h,
4911 struct CommandList *c)
4912{
4913 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
4914 c->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION)
4915 (void) check_for_unit_attention(h, c);
4916}
0390f0c0
SC		 4917
4918static int increment_passthru_count(struct ctlr_info *h)
4919{
4920 unsigned long flags;
4921
4922 spin_lock_irqsave(&h->passthru_count_lock, flags);
4923 if (h->passthru_count >= HPSA_MAX_CONCURRENT_PASSTHRUS) {
4924 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
4925 return -1;
4926 }
4927 h->passthru_count++;
4928 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
4929 return 0;
4930}
4931
4932static void decrement_passthru_count(struct ctlr_info *h)
4933{
4934 unsigned long flags;
4935
4936 spin_lock_irqsave(&h->passthru_count_lock, flags);
4937 if (h->passthru_count <= 0) {
4938 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
4939 /* not expecting to get here. */
4940 dev_warn(&h->pdev->dev, "Bug detected, passthru_count seems to be incorrect.\n");
4941 return;
4942 }
4943 h->passthru_count--;
4944 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
4945}
4946
edd16368
SC		 4947/*
4948 * ioctl
4949 */
42a91641 4950static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg)
edd16368
SC		 4951{
4952 struct ctlr_info *h;
4953 void __user *argp = (void __user *)arg;
0390f0c0 4954 int rc;
edd16368
SC		 4955
4956 h = sdev_to_hba(dev);
4957
4958 switch (cmd) {
4959 case CCISS_DEREGDISK:
4960 case CCISS_REGNEWDISK:
4961 case CCISS_REGNEWD:
a08a8471 4962 hpsa_scan_start(h->scsi_host);
edd16368
SC		 4963 return 0;
4964 case CCISS_GETPCIINFO:
4965 return hpsa_getpciinfo_ioctl(h, argp);
4966 case CCISS_GETDRIVVER:
4967 return hpsa_getdrivver_ioctl(h, argp);
4968 case CCISS_PASSTHRU:
0390f0c0
SC		 4969 if (increment_passthru_count(h))
4970 return -EAGAIN;
4971 rc = hpsa_passthru_ioctl(h, argp);
4972 decrement_passthru_count(h);
4973 return rc;
edd16368 4974 case CCISS_BIG_PASSTHRU:
0390f0c0
SC		 4975 if (increment_passthru_count(h))
4976 return -EAGAIN;
4977 rc = hpsa_big_passthru_ioctl(h, argp);
4978 decrement_passthru_count(h);
4979 return rc;
edd16368
SC		 4980 default:
4981 return -ENOTTY;
4982 }
4983}
4984
6f039790
GKH		 4985static int hpsa_send_host_reset(struct ctlr_info *h, unsigned char *scsi3addr,
4986 u8 reset_type)
64670ac8
SC		 4987{
4988 struct CommandList *c;
4989
4990 c = cmd_alloc(h);
4991 if (!c)
4992 return -ENOMEM;
a2dac136
SC		 4993 /* fill_cmd can't fail here, no data buffer to map */
4994 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
64670ac8
SC		 4995 RAID_CTLR_LUNID, TYPE_MSG);
4996 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to target reset */
4997 c->waiting = NULL;
4998 enqueue_cmd_and_start_io(h, c);
4999 /* Don't wait for completion, the reset won't complete. Don't free
5000 * the command either. This is the last command we will send before
5001 * re-initializing everything, so it doesn't matter and won't leak.
5002 */
5003 return 0;
5004}
5005
a2dac136 5006static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
b7bb24eb 5007 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
edd16368
SC		 5008 int cmd_type)
5009{
5010 int pci_dir = XFER_NONE;
75167d2c 5011 struct CommandList *a; /* for commands to be aborted */
edd16368
SC		 5012
5013 c->cmd_type = CMD_IOCTL_PEND;
5014 c->Header.ReplyQueue = 0;
5015 if (buff != NULL && size > 0) {
5016 c->Header.SGList = 1;
50a0decf 5017 c->Header.SGTotal = cpu_to_le16(1);
edd16368
SC		 5018 } else {
5019 c->Header.SGList = 0;
50a0decf 5020 c->Header.SGTotal = cpu_to_le16(0);
edd16368 5021 }
edd16368
SC		 5022 memcpy(c->Header.LUN.LunAddrBytes, scsi3addr, 8);
5023
edd16368
SC		 5024 if (cmd_type == TYPE_CMD) {
5025 switch (cmd) {
5026 case HPSA_INQUIRY:
5027 /* are we trying to read a vital product page */
b7bb24eb 5028 if (page_code & VPD_PAGE) {
edd16368 5029 c->Request.CDB[1] = 0x01;
b7bb24eb 5030 c->Request.CDB[2] = (page_code & 0xff);
edd16368
SC		 5031 }
5032 c->Request.CDBLen = 6;
a505b86f
SC		 5033 c->Request.type_attr_dir =
5034 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 5035 c->Request.Timeout = 0;
5036 c->Request.CDB[0] = HPSA_INQUIRY;
5037 c->Request.CDB[4] = size & 0xFF;
5038 break;
5039 case HPSA_REPORT_LOG:
5040 case HPSA_REPORT_PHYS:
5041 /* Talking to controller so It's a physical command
5042 mode = 00 target = 0. Nothing to write.
5043 */
5044 c->Request.CDBLen = 12;
a505b86f
SC		 5045 c->Request.type_attr_dir =
5046 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 5047 c->Request.Timeout = 0;
5048 c->Request.CDB[0] = cmd;
5049 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
5050 c->Request.CDB[7] = (size >> 16) & 0xFF;
5051 c->Request.CDB[8] = (size >> 8) & 0xFF;
5052 c->Request.CDB[9] = size & 0xFF;
5053 break;
edd16368
SC		 5054 case HPSA_CACHE_FLUSH:
5055 c->Request.CDBLen = 12;
a505b86f
SC		 5056 c->Request.type_attr_dir =
5057 TYPE_ATTR_DIR(cmd_type,
5058 ATTR_SIMPLE, XFER_WRITE);
edd16368
SC		 5059 c->Request.Timeout = 0;
5060 c->Request.CDB[0] = BMIC_WRITE;
5061 c->Request.CDB[6] = BMIC_CACHE_FLUSH;
bb158eab
SC		 5062 c->Request.CDB[7] = (size >> 8) & 0xFF;
5063 c->Request.CDB[8] = size & 0xFF;
edd16368
SC		 5064 break;
5065 case TEST_UNIT_READY:
5066 c->Request.CDBLen = 6;
a505b86f
SC		 5067 c->Request.type_attr_dir =
5068 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
edd16368
SC		 5069 c->Request.Timeout = 0;
5070 break;
283b4a9b
SC		 5071 case HPSA_GET_RAID_MAP:
5072 c->Request.CDBLen = 12;
a505b86f
SC		 5073 c->Request.type_attr_dir =
5074 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
283b4a9b
SC		 5075 c->Request.Timeout = 0;
5076 c->Request.CDB[0] = HPSA_CISS_READ;
5077 c->Request.CDB[1] = cmd;
5078 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
5079 c->Request.CDB[7] = (size >> 16) & 0xFF;
5080 c->Request.CDB[8] = (size >> 8) & 0xFF;
5081 c->Request.CDB[9] = size & 0xFF;
5082 break;
316b221a
SC		 5083 case BMIC_SENSE_CONTROLLER_PARAMETERS:
5084 c->Request.CDBLen = 10;
a505b86f
SC		 5085 c->Request.type_attr_dir =
5086 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
316b221a
SC		 5087 c->Request.Timeout = 0;
5088 c->Request.CDB[0] = BMIC_READ;
5089 c->Request.CDB[6] = BMIC_SENSE_CONTROLLER_PARAMETERS;
5090 c->Request.CDB[7] = (size >> 16) & 0xFF;
5091 c->Request.CDB[8] = (size >> 8) & 0xFF;
5092 break;
edd16368
SC		 5093 default:
5094 dev_warn(&h->pdev->dev, "unknown command 0x%c\n", cmd);
5095 BUG();
a2dac136 5096 return -1;
edd16368
SC		 5097 }
5098 } else if (cmd_type == TYPE_MSG) {
5099 switch (cmd) {
5100
5101 case HPSA_DEVICE_RESET_MSG:
5102 c->Request.CDBLen = 16;
a505b86f
SC		 5103 c->Request.type_attr_dir =
5104 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
edd16368 5105 c->Request.Timeout = 0; /* Don't time out */
64670ac8
SC		 5106 memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
5107 c->Request.CDB[0] = cmd;
21e89afd 5108 c->Request.CDB[1] = HPSA_RESET_TYPE_LUN;
edd16368
SC		 5109 /* If bytes 4-7 are zero, it means reset the */
5110 /* LunID device */
5111 c->Request.CDB[4] = 0x00;
5112 c->Request.CDB[5] = 0x00;
5113 c->Request.CDB[6] = 0x00;
5114 c->Request.CDB[7] = 0x00;
75167d2c
SC		 5115 break;
5116 case HPSA_ABORT_MSG:
5117 a = buff; /* point to command to be aborted */
2b08b3e9
DB		 5118 dev_dbg(&h->pdev->dev,
5119 "Abort Tag:0x%016llx request Tag:0x%016llx",
50a0decf 5120 a->Header.tag, c->Header.tag);
75167d2c 5121 c->Request.CDBLen = 16;
a505b86f
SC		 5122 c->Request.type_attr_dir =
5123 TYPE_ATTR_DIR(cmd_type,
5124 ATTR_SIMPLE, XFER_WRITE);
75167d2c
SC		 5125 c->Request.Timeout = 0; /* Don't time out */
5126 c->Request.CDB[0] = HPSA_TASK_MANAGEMENT;
5127 c->Request.CDB[1] = HPSA_TMF_ABORT_TASK;
5128 c->Request.CDB[2] = 0x00; /* reserved */
5129 c->Request.CDB[3] = 0x00; /* reserved */
5130 /* Tag to abort goes in CDB[4]-CDB[11] */
2b08b3e9
DB		 5131 memcpy(&c->Request.CDB[4], &a->Header.tag,
5132 sizeof(a->Header.tag));
75167d2c
SC		 5133 c->Request.CDB[12] = 0x00; /* reserved */
5134 c->Request.CDB[13] = 0x00; /* reserved */
5135 c->Request.CDB[14] = 0x00; /* reserved */
5136 c->Request.CDB[15] = 0x00; /* reserved */
edd16368 5137 break;
edd16368
SC		 5138 default:
5139 dev_warn(&h->pdev->dev, "unknown message type %d\n",
5140 cmd);
5141 BUG();
5142 }
5143 } else {
5144 dev_warn(&h->pdev->dev, "unknown command type %d\n", cmd_type);
5145 BUG();
5146 }
5147
a505b86f 5148 switch (GET_DIR(c->Request.type_attr_dir)) {
edd16368
SC		 5149 case XFER_READ:
5150 pci_dir = PCI_DMA_FROMDEVICE;
5151 break;
5152 case XFER_WRITE:
5153 pci_dir = PCI_DMA_TODEVICE;
5154 break;
5155 case XFER_NONE:
5156 pci_dir = PCI_DMA_NONE;
5157 break;
5158 default:
5159 pci_dir = PCI_DMA_BIDIRECTIONAL;
5160 }
a2dac136
SC		 5161 if (hpsa_map_one(h->pdev, c, buff, size, pci_dir))
5162 return -1;
5163 return 0;
edd16368
SC		 5164}
5165
5166/*
5167 * Map (physical) PCI mem into (virtual) kernel space
5168 */
5169static void __iomem *remap_pci_mem(ulong base, ulong size)
5170{
5171 ulong page_base = ((ulong) base) & PAGE_MASK;
5172 ulong page_offs = ((ulong) base) - page_base;
088ba34c
SC		 5173 void __iomem *page_remapped = ioremap_nocache(page_base,
5174 page_offs + size);
edd16368
SC		 5175
5176 return page_remapped ? (page_remapped + page_offs) : NULL;
5177}
5178
254f796b 5179static inline unsigned long get_next_completion(struct ctlr_info *h, u8 q)
edd16368 5180{
254f796b 5181 return h->access.command_completed(h, q);
edd16368
SC		 5182}
5183
900c5440 5184static inline bool interrupt_pending(struct ctlr_info *h)
edd16368
SC		 5185{
5186 return h->access.intr_pending(h);
5187}
5188
5189static inline long interrupt_not_for_us(struct ctlr_info *h)
5190{
10f66018
SC		 5191 return (h->access.intr_pending(h) == 0) ||
5192 (h->interrupts_enabled == 0);
edd16368
SC		 5193}
5194
01a02ffc
SC		 5195static inline int bad_tag(struct ctlr_info *h, u32 tag_index,
5196 u32 raw_tag)
edd16368
SC		 5197{
5198 if (unlikely(tag_index >= h->nr_cmds)) {
5199 dev_warn(&h->pdev->dev, "bad tag 0x%08x ignored.\n", raw_tag);
5200 return 1;
5201 }
5202 return 0;
5203}
5204
5a3d16f5 5205static inline void finish_cmd(struct CommandList *c)
edd16368 5206{
e85c5974 5207 dial_up_lockup_detection_on_fw_flash_complete(c->h, c);
c349775e
ST		 5208 if (likely(c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_SCSI
5209 || c->cmd_type == CMD_IOACCEL2))
1fb011fb 5210 complete_scsi_command(c);
edd16368
SC		 5211 else if (c->cmd_type == CMD_IOCTL_PEND)
5212 complete(c->waiting);
a104c99f
SC		 5213}
5214
a9a3a273
SC		 5215
5216static inline u32 hpsa_tag_discard_error_bits(struct ctlr_info *h, u32 tag)
a104c99f 5217{
a9a3a273
SC		 5218#define HPSA_PERF_ERROR_BITS ((1 << DIRECT_LOOKUP_SHIFT) - 1)
5219#define HPSA_SIMPLE_ERROR_BITS 0x03
960a30e7 5220 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
a9a3a273
SC		 5221 return tag & ~HPSA_SIMPLE_ERROR_BITS;
5222 return tag & ~HPSA_PERF_ERROR_BITS;
a104c99f
SC		 5223}
5224
303932fd 5225/* process completion of an indexed ("direct lookup") command */
1d94f94d 5226static inline void process_indexed_cmd(struct ctlr_info *h,
303932fd
DB		 5227 u32 raw_tag)
5228{
5229 u32 tag_index;
5230 struct CommandList *c;
5231
f2405db8 5232 tag_index = raw_tag >> DIRECT_LOOKUP_SHIFT;
1d94f94d
SC		 5233 if (!bad_tag(h, tag_index, raw_tag)) {
5234 c = h->cmd_pool + tag_index;
5235 finish_cmd(c);
5236 }
303932fd
DB		 5237}
5238
64670ac8
SC		 5239/* Some controllers, like p400, will give us one interrupt
5240 * after a soft reset, even if we turned interrupts off.
5241 * Only need to check for this in the hpsa_xxx_discard_completions
5242 * functions.
5243 */
5244static int ignore_bogus_interrupt(struct ctlr_info *h)
5245{
5246 if (likely(!reset_devices))
5247 return 0;
5248
5249 if (likely(h->interrupts_enabled))
5250 return 0;
5251
5252 dev_info(&h->pdev->dev, "Received interrupt while interrupts disabled "
5253 "(known firmware bug.) Ignoring.\n");
5254
5255 return 1;
5256}
5257
254f796b
MG		 5258/*
5259 * Convert &h->q[x] (passed to interrupt handlers) back to h.
5260 * Relies on (h-q[x] == x) being true for x such that
5261 * 0 <= x < MAX_REPLY_QUEUES.
5262 */
5263static struct ctlr_info *queue_to_hba(u8 *queue)
64670ac8 5264{
254f796b
MG		 5265 return container_of((queue - *queue), struct ctlr_info, q[0]);
5266}
5267
5268static irqreturn_t hpsa_intx_discard_completions(int irq, void *queue)
5269{
5270 struct ctlr_info *h = queue_to_hba(queue);
5271 u8 q = *(u8 *) queue;
64670ac8
SC		 5272 u32 raw_tag;
5273
5274 if (ignore_bogus_interrupt(h))
5275 return IRQ_NONE;
5276
5277 if (interrupt_not_for_us(h))
5278 return IRQ_NONE;
a0c12413 5279 h->last_intr_timestamp = get_jiffies_64();
64670ac8 5280 while (interrupt_pending(h)) {
254f796b 5281 raw_tag = get_next_completion(h, q);
64670ac8 5282 while (raw_tag != FIFO_EMPTY)
254f796b 5283 raw_tag = next_command(h, q);
64670ac8 5284 }
64670ac8
SC		 5285 return IRQ_HANDLED;
5286}
5287
254f796b 5288static irqreturn_t hpsa_msix_discard_completions(int irq, void *queue)
64670ac8 5289{
254f796b 5290 struct ctlr_info *h = queue_to_hba(queue);
64670ac8 5291 u32 raw_tag;
254f796b 5292 u8 q = *(u8 *) queue;
64670ac8
SC		 5293
5294 if (ignore_bogus_interrupt(h))
5295 return IRQ_NONE;
5296
a0c12413 5297 h->last_intr_timestamp = get_jiffies_64();
254f796b 5298 raw_tag = get_next_completion(h, q);
64670ac8 5299 while (raw_tag != FIFO_EMPTY)
254f796b 5300 raw_tag = next_command(h, q);
64670ac8
SC		 5301 return IRQ_HANDLED;
5302}
5303
254f796b 5304static irqreturn_t do_hpsa_intr_intx(int irq, void *queue)
edd16368 5305{
254f796b 5306 struct ctlr_info *h = queue_to_hba((u8 *) queue);
303932fd 5307 u32 raw_tag;
254f796b 5308 u8 q = *(u8 *) queue;
edd16368
SC		 5309
5310 if (interrupt_not_for_us(h))
5311 return IRQ_NONE;
a0c12413 5312 h->last_intr_timestamp = get_jiffies_64();
10f66018 5313 while (interrupt_pending(h)) {
254f796b 5314 raw_tag = get_next_completion(h, q);
10f66018 5315 while (raw_tag != FIFO_EMPTY) {
f2405db8 5316 process_indexed_cmd(h, raw_tag);
254f796b 5317 raw_tag = next_command(h, q);
10f66018
SC		 5318 }
5319 }
10f66018
SC		 5320 return IRQ_HANDLED;
5321}
5322
254f796b 5323static irqreturn_t do_hpsa_intr_msi(int irq, void *queue)
10f66018 5324{
254f796b 5325 struct ctlr_info *h = queue_to_hba(queue);
10f66018 5326 u32 raw_tag;
254f796b 5327 u8 q = *(u8 *) queue;
10f66018 5328
a0c12413 5329 h->last_intr_timestamp = get_jiffies_64();
254f796b 5330 raw_tag = get_next_completion(h, q);
303932fd 5331 while (raw_tag != FIFO_EMPTY) {
f2405db8 5332 process_indexed_cmd(h, raw_tag);
254f796b 5333 raw_tag = next_command(h, q);
edd16368 5334 }
edd16368
SC		 5335 return IRQ_HANDLED;
5336}
5337
a9a3a273
SC		 5338/* Send a message CDB to the firmware. Careful, this only works
5339 * in simple mode, not performant mode due to the tag lookup.
5340 * We only ever use this immediately after a controller reset.
5341 */
6f039790
GKH		 5342static int hpsa_message(struct pci_dev *pdev, unsigned char opcode,
5343 unsigned char type)
edd16368
SC		 5344{
5345 struct Command {
5346 struct CommandListHeader CommandHeader;
5347 struct RequestBlock Request;
5348 struct ErrDescriptor ErrorDescriptor;
5349 };
5350 struct Command *cmd;
5351 static const size_t cmd_sz = sizeof(*cmd) +
5352 sizeof(cmd->ErrorDescriptor);
5353 dma_addr_t paddr64;
2b08b3e9
DB		 5354 __le32 paddr32;
5355 u32 tag;
edd16368
SC		 5356 void __iomem *vaddr;
5357 int i, err;
5358
5359 vaddr = pci_ioremap_bar(pdev, 0);
5360 if (vaddr == NULL)
5361 return -ENOMEM;
5362
5363 /* The Inbound Post Queue only accepts 32-bit physical addresses for the
5364 * CCISS commands, so they must be allocated from the lower 4GiB of
5365 * memory.
5366 */
5367 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
5368 if (err) {
5369 iounmap(vaddr);
1eaec8f3 5370 return err;
edd16368
SC		 5371 }
5372
5373 cmd = pci_alloc_consistent(pdev, cmd_sz, &paddr64);
5374 if (cmd == NULL) {
5375 iounmap(vaddr);
5376 return -ENOMEM;
5377 }
5378
5379 /* This must fit, because of the 32-bit consistent DMA mask. Also,
5380 * although there's no guarantee, we assume that the address is at
5381 * least 4-byte aligned (most likely, it's page-aligned).
5382 */
2b08b3e9 5383 paddr32 = cpu_to_le32(paddr64);
edd16368
SC		 5384
5385 cmd->CommandHeader.ReplyQueue = 0;
5386 cmd->CommandHeader.SGList = 0;
50a0decf 5387 cmd->CommandHeader.SGTotal = cpu_to_le16(0);
2b08b3e9 5388 cmd->CommandHeader.tag = cpu_to_le64(paddr64);
edd16368
SC		 5389 memset(&cmd->CommandHeader.LUN.LunAddrBytes, 0, 8);
5390
5391 cmd->Request.CDBLen = 16;
a505b86f
SC		 5392 cmd->Request.type_attr_dir =
5393 TYPE_ATTR_DIR(TYPE_MSG, ATTR_HEADOFQUEUE, XFER_NONE);
edd16368
SC		 5394 cmd->Request.Timeout = 0; /* Don't time out */
5395 cmd->Request.CDB[0] = opcode;
5396 cmd->Request.CDB[1] = type;
5397 memset(&cmd->Request.CDB[2], 0, 14); /* rest of the CDB is reserved */
50a0decf 5398 cmd->ErrorDescriptor.Addr =
2b08b3e9 5399 cpu_to_le64((le32_to_cpu(paddr32) + sizeof(*cmd)));
50a0decf 5400 cmd->ErrorDescriptor.Len = cpu_to_le32(sizeof(struct ErrorInfo));
edd16368 5401
2b08b3e9 5402 writel(le32_to_cpu(paddr32), vaddr + SA5_REQUEST_PORT_OFFSET);
edd16368
SC		 5403
5404 for (i = 0; i < HPSA_MSG_SEND_RETRY_LIMIT; i++) {
5405 tag = readl(vaddr + SA5_REPLY_PORT_OFFSET);
2b08b3e9 5406 if ((tag & ~HPSA_SIMPLE_ERROR_BITS) == paddr64)
edd16368
SC		 5407 break;
5408 msleep(HPSA_MSG_SEND_RETRY_INTERVAL_MSECS);
5409 }
5410
5411 iounmap(vaddr);
5412
5413 /* we leak the DMA buffer here ... no choice since the controller could
5414 * still complete the command.
5415 */
5416 if (i == HPSA_MSG_SEND_RETRY_LIMIT) {
5417 dev_err(&pdev->dev, "controller message %02x:%02x timed out\n",
5418 opcode, type);
5419 return -ETIMEDOUT;
5420 }
5421
5422 pci_free_consistent(pdev, cmd_sz, cmd, paddr64);
5423
5424 if (tag & HPSA_ERROR_BIT) {
5425 dev_err(&pdev->dev, "controller message %02x:%02x failed\n",
5426 opcode, type);
5427 return -EIO;
5428 }
5429
5430 dev_info(&pdev->dev, "controller message %02x:%02x succeeded\n",
5431 opcode, type);
5432 return 0;
5433}
5434
edd16368
SC		 5435#define hpsa_noop(p) hpsa_message(p, 3, 0)
5436
1df8552a 5437static int hpsa_controller_hard_reset(struct pci_dev *pdev,
42a91641 5438 void __iomem *vaddr, u32 use_doorbell)
1df8552a 5439{
1df8552a
SC		 5440
5441 if (use_doorbell) {
5442 /* For everything after the P600, the PCI power state method
5443 * of resetting the controller doesn't work, so we have this
5444 * other way using the doorbell register.
5445 */
5446 dev_info(&pdev->dev, "using doorbell to reset controller\n");
cf0b08d0 5447 writel(use_doorbell, vaddr + SA5_DOORBELL);
85009239 5448
00701a96 5449 /* PMC hardware guys tell us we need a 10 second delay after
85009239
SC		 5450 * doorbell reset and before any attempt to talk to the board
5451 * at all to ensure that this actually works and doesn't fall
5452 * over in some weird corner cases.
5453 */
00701a96 5454 msleep(10000);
1df8552a
SC		 5455 } else { /* Try to do it the PCI power state way */
5456
5457 /* Quoting from the Open CISS Specification: "The Power
5458 * Management Control/Status Register (CSR) controls the power
5459 * state of the device. The normal operating state is D0,
5460 * CSR=00h. The software off state is D3, CSR=03h. To reset
5461 * the controller, place the interface device in D3 then to D0,
5462 * this causes a secondary PCI reset which will reset the
5463 * controller." */
2662cab8
DB		 5464
5465 int rc = 0;
5466
1df8552a 5467 dev_info(&pdev->dev, "using PCI PM to reset controller\n");
2662cab8 5468
1df8552a 5469 /* enter the D3hot power management state */
2662cab8
DB		 5470 rc = pci_set_power_state(pdev, PCI_D3hot);
5471 if (rc)
5472 return rc;
1df8552a
SC		 5473
5474 msleep(500);
5475
5476 /* enter the D0 power management state */
2662cab8
DB		 5477 rc = pci_set_power_state(pdev, PCI_D0);
5478 if (rc)
5479 return rc;
c4853efe
MM		 5480
5481 /*
5482 * The P600 requires a small delay when changing states.
5483 * Otherwise we may think the board did not reset and we bail.
5484 * This for kdump only and is particular to the P600.
5485 */
5486 msleep(500);
1df8552a
SC		 5487 }
5488 return 0;
5489}
5490
6f039790 5491static void init_driver_version(char *driver_version, int len)
580ada3c
SC		 5492{
5493 memset(driver_version, 0, len);
f79cfec6 5494 strncpy(driver_version, HPSA " " HPSA_DRIVER_VERSION, len - 1);
580ada3c
SC		 5495}
5496
6f039790 5497static int write_driver_ver_to_cfgtable(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 5498{
5499 char *driver_version;
5500 int i, size = sizeof(cfgtable->driver_version);
5501
5502 driver_version = kmalloc(size, GFP_KERNEL);
5503 if (!driver_version)
5504 return -ENOMEM;
5505
5506 init_driver_version(driver_version, size);
5507 for (i = 0; i < size; i++)
5508 writeb(driver_version[i], &cfgtable->driver_version[i]);
5509 kfree(driver_version);
5510 return 0;
5511}
5512
6f039790
GKH		 5513static void read_driver_ver_from_cfgtable(struct CfgTable __iomem *cfgtable,
5514 unsigned char *driver_ver)
580ada3c
SC		 5515{
5516 int i;
5517
5518 for (i = 0; i < sizeof(cfgtable->driver_version); i++)
5519 driver_ver[i] = readb(&cfgtable->driver_version[i]);
5520}
5521
6f039790 5522static int controller_reset_failed(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 5523{
5524
5525 char *driver_ver, *old_driver_ver;
5526 int rc, size = sizeof(cfgtable->driver_version);
5527
5528 old_driver_ver = kmalloc(2 * size, GFP_KERNEL);
5529 if (!old_driver_ver)
5530 return -ENOMEM;
5531 driver_ver = old_driver_ver + size;
5532
5533 /* After a reset, the 32 bytes of "driver version" in the cfgtable
5534 * should have been changed, otherwise we know the reset failed.
5535 */
5536 init_driver_version(old_driver_ver, size);
5537 read_driver_ver_from_cfgtable(cfgtable, driver_ver);
5538 rc = !memcmp(driver_ver, old_driver_ver, size);
5539 kfree(old_driver_ver);
5540 return rc;
5541}
edd16368 5542/* This does a hard reset of the controller using PCI power management
1df8552a 5543 * states or the using the doorbell register.
edd16368 5544 */
6f039790 5545static int hpsa_kdump_hard_reset_controller(struct pci_dev *pdev)
edd16368 5546{
1df8552a
SC		 5547 u64 cfg_offset;
5548 u32 cfg_base_addr;
5549 u64 cfg_base_addr_index;
5550 void __iomem *vaddr;
5551 unsigned long paddr;
580ada3c 5552 u32 misc_fw_support;
270d05de 5553 int rc;
1df8552a 5554 struct CfgTable __iomem *cfgtable;
cf0b08d0 5555 u32 use_doorbell;
18867659 5556 u32 board_id;
270d05de 5557 u16 command_register;
edd16368 5558
1df8552a
SC		 5559 /* For controllers as old as the P600, this is very nearly
5560 * the same thing as
edd16368
SC		 5561 *
5562 * pci_save_state(pci_dev);
5563 * pci_set_power_state(pci_dev, PCI_D3hot);
5564 * pci_set_power_state(pci_dev, PCI_D0);
5565 * pci_restore_state(pci_dev);
5566 *
1df8552a
SC		 5567 * For controllers newer than the P600, the pci power state
5568 * method of resetting doesn't work so we have another way
5569 * using the doorbell register.
edd16368 5570 */
18867659 5571
25c1e56a 5572 rc = hpsa_lookup_board_id(pdev, &board_id);
60f923b9
RE		 5573 if (rc < 0) {
5574 dev_warn(&pdev->dev, "Board ID not found\n");
5575 return rc;
5576 }
5577 if (!ctlr_is_resettable(board_id)) {
5578 dev_warn(&pdev->dev, "Controller not resettable\n");
25c1e56a
SC		 5579 return -ENODEV;
5580 }
46380786
SC		 5581
5582 /* if controller is soft- but not hard resettable... */
5583 if (!ctlr_is_hard_resettable(board_id))
5584 return -ENOTSUPP; /* try soft reset later. */
18867659 5585
270d05de
SC		 5586 /* Save the PCI command register */
5587 pci_read_config_word(pdev, 4, &command_register);
270d05de 5588 pci_save_state(pdev);
edd16368 5589
1df8552a
SC		 5590 /* find the first memory BAR, so we can find the cfg table */
5591 rc = hpsa_pci_find_memory_BAR(pdev, &paddr);
5592 if (rc)
5593 return rc;
5594 vaddr = remap_pci_mem(paddr, 0x250);
5595 if (!vaddr)
5596 return -ENOMEM;
edd16368 5597
1df8552a
SC		 5598 /* find cfgtable in order to check if reset via doorbell is supported */
5599 rc = hpsa_find_cfg_addrs(pdev, vaddr, &cfg_base_addr,
5600 &cfg_base_addr_index, &cfg_offset);
5601 if (rc)
5602 goto unmap_vaddr;
5603 cfgtable = remap_pci_mem(pci_resource_start(pdev,
5604 cfg_base_addr_index) + cfg_offset, sizeof(*cfgtable));
5605 if (!cfgtable) {
5606 rc = -ENOMEM;
5607 goto unmap_vaddr;
5608 }
580ada3c
SC		 5609 rc = write_driver_ver_to_cfgtable(cfgtable);
5610 if (rc)
03741d95 5611 goto unmap_cfgtable;
edd16368 5612
cf0b08d0
SC		 5613 /* If reset via doorbell register is supported, use that.
5614 * There are two such methods. Favor the newest method.
5615 */
1df8552a 5616 misc_fw_support = readl(&cfgtable->misc_fw_support);
cf0b08d0
SC		 5617 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET2;
5618 if (use_doorbell) {
5619 use_doorbell = DOORBELL_CTLR_RESET2;
5620 } else {
5621 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET;
5622 if (use_doorbell) {
050f7147
SC		 5623 dev_warn(&pdev->dev,
5624 "Soft reset not supported. Firmware update is required.\n");
64670ac8 5625 rc = -ENOTSUPP; /* try soft reset */
cf0b08d0
SC		 5626 goto unmap_cfgtable;
5627 }
5628 }
edd16368 5629
1df8552a
SC		 5630 rc = hpsa_controller_hard_reset(pdev, vaddr, use_doorbell);
5631 if (rc)
5632 goto unmap_cfgtable;
edd16368 5633
270d05de 5634 pci_restore_state(pdev);
270d05de 5635 pci_write_config_word(pdev, 4, command_register);
edd16368 5636
1df8552a
SC		 5637 /* Some devices (notably the HP Smart Array 5i Controller)
5638 need a little pause here */
5639 msleep(HPSA_POST_RESET_PAUSE_MSECS);
5640
fe5389c8
SC		 5641 rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_READY);
5642 if (rc) {
5643 dev_warn(&pdev->dev,
050f7147 5644 "Failed waiting for board to become ready after hard reset\n");
fe5389c8
SC		 5645 goto unmap_cfgtable;
5646 }
fe5389c8 5647
580ada3c
SC		 5648 rc = controller_reset_failed(vaddr);
5649 if (rc < 0)
5650 goto unmap_cfgtable;
5651 if (rc) {
64670ac8
SC		 5652 dev_warn(&pdev->dev, "Unable to successfully reset "
5653 "controller. Will try soft reset.\n");
5654 rc = -ENOTSUPP;
580ada3c 5655 } else {
64670ac8 5656 dev_info(&pdev->dev, "board ready after hard reset.\n");
1df8552a
SC		 5657 }
5658
5659unmap_cfgtable:
5660 iounmap(cfgtable);
5661
5662unmap_vaddr:
5663 iounmap(vaddr);
5664 return rc;
edd16368
SC		 5665}
5666
5667/*
5668 * We cannot read the structure directly, for portability we must use
5669 * the io functions.
5670 * This is for debug only.
5671 */
42a91641 5672static void print_cfg_table(struct device *dev, struct CfgTable __iomem *tb)
edd16368 5673{
58f8665c 5674#ifdef HPSA_DEBUG
edd16368
SC		 5675 int i;
5676 char temp_name[17];
5677
5678 dev_info(dev, "Controller Configuration information\n");
5679 dev_info(dev, "------------------------------------\n");
5680 for (i = 0; i < 4; i++)
5681 temp_name[i] = readb(&(tb->Signature[i]));
5682 temp_name[4] = '\0';
5683 dev_info(dev, " Signature = %s\n", temp_name);
5684 dev_info(dev, " Spec Number = %d\n", readl(&(tb->SpecValence)));
5685 dev_info(dev, " Transport methods supported = 0x%x\n",
5686 readl(&(tb->TransportSupport)));
5687 dev_info(dev, " Transport methods active = 0x%x\n",
5688 readl(&(tb->TransportActive)));
5689 dev_info(dev, " Requested transport Method = 0x%x\n",
5690 readl(&(tb->HostWrite.TransportRequest)));
5691 dev_info(dev, " Coalesce Interrupt Delay = 0x%x\n",
5692 readl(&(tb->HostWrite.CoalIntDelay)));
5693 dev_info(dev, " Coalesce Interrupt Count = 0x%x\n",
5694 readl(&(tb->HostWrite.CoalIntCount)));
69d6e33d 5695 dev_info(dev, " Max outstanding commands = %d\n",
edd16368
SC		 5696 readl(&(tb->CmdsOutMax)));
5697 dev_info(dev, " Bus Types = 0x%x\n", readl(&(tb->BusTypes)));
5698 for (i = 0; i < 16; i++)
5699 temp_name[i] = readb(&(tb->ServerName[i]));
5700 temp_name[16] = '\0';
5701 dev_info(dev, " Server Name = %s\n", temp_name);
5702 dev_info(dev, " Heartbeat Counter = 0x%x\n\n\n",
5703 readl(&(tb->HeartBeat)));
edd16368 5704#endif /* HPSA_DEBUG */
58f8665c 5705}
edd16368
SC		 5706
5707static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr)
5708{
5709 int i, offset, mem_type, bar_type;
5710
5711 if (pci_bar_addr == PCI_BASE_ADDRESS_0) /* looking for BAR zero? */
5712 return 0;
5713 offset = 0;
5714 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
5715 bar_type = pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE;
5716 if (bar_type == PCI_BASE_ADDRESS_SPACE_IO)
5717 offset += 4;
5718 else {
5719 mem_type = pci_resource_flags(pdev, i) &
5720 PCI_BASE_ADDRESS_MEM_TYPE_MASK;
5721 switch (mem_type) {
5722 case PCI_BASE_ADDRESS_MEM_TYPE_32:
5723 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
5724 offset += 4; /* 32 bit */
5725 break;
5726 case PCI_BASE_ADDRESS_MEM_TYPE_64:
5727 offset += 8;
5728 break;
5729 default: /* reserved in PCI 2.2 */
5730 dev_warn(&pdev->dev,
5731 "base address is invalid\n");
5732 return -1;
5733 break;
5734 }
5735 }
5736 if (offset == pci_bar_addr - PCI_BASE_ADDRESS_0)
5737 return i + 1;
5738 }
5739 return -1;
5740}
5741
5742/* If MSI/MSI-X is supported by the kernel we will try to enable it on
050f7147 5743 * controllers that are capable. If not, we use legacy INTx mode.
edd16368
SC		 5744 */
5745
6f039790 5746static void hpsa_interrupt_mode(struct ctlr_info *h)
edd16368
SC		 5747{
5748#ifdef CONFIG_PCI_MSI
254f796b
MG		 5749 int err, i;
5750 struct msix_entry hpsa_msix_entries[MAX_REPLY_QUEUES];
5751
5752 for (i = 0; i < MAX_REPLY_QUEUES; i++) {
5753 hpsa_msix_entries[i].vector = 0;
5754 hpsa_msix_entries[i].entry = i;
5755 }
edd16368
SC		 5756
5757 /* Some boards advertise MSI but don't really support it */
6b3f4c52
SC		 5758 if ((h->board_id == 0x40700E11) || (h->board_id == 0x40800E11) ||
5759 (h->board_id == 0x40820E11) || (h->board_id == 0x40830E11))
edd16368 5760 goto default_int_mode;
55c06c71 5761 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSIX)) {
050f7147 5762 dev_info(&h->pdev->dev, "MSI-X capable controller\n");
eee0f03a 5763 h->msix_vector = MAX_REPLY_QUEUES;
f89439bc
SC		 5764 if (h->msix_vector > num_online_cpus())
5765 h->msix_vector = num_online_cpus();
18fce3c4
AG		 5766 err = pci_enable_msix_range(h->pdev, hpsa_msix_entries,
5767 1, h->msix_vector);
5768 if (err < 0) {
5769 dev_warn(&h->pdev->dev, "MSI-X init failed %d\n", err);
5770 h->msix_vector = 0;
5771 goto single_msi_mode;
5772 } else if (err < h->msix_vector) {
55c06c71 5773 dev_warn(&h->pdev->dev, "only %d MSI-X vectors "
edd16368 5774 "available\n", err);
edd16368 5775 }
18fce3c4
AG		 5776 h->msix_vector = err;
5777 for (i = 0; i < h->msix_vector; i++)
5778 h->intr[i] = hpsa_msix_entries[i].vector;
5779 return;
edd16368 5780 }
18fce3c4 5781single_msi_mode:
55c06c71 5782 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSI)) {
050f7147 5783 dev_info(&h->pdev->dev, "MSI capable controller\n");
55c06c71 5784 if (!pci_enable_msi(h->pdev))
edd16368
SC		 5785 h->msi_vector = 1;
5786 else
55c06c71 5787 dev_warn(&h->pdev->dev, "MSI init failed\n");
edd16368
SC		 5788 }
5789default_int_mode:
5790#endif /* CONFIG_PCI_MSI */
5791 /* if we get here we're going to use the default interrupt mode */
a9a3a273 5792 h->intr[h->intr_mode] = h->pdev->irq;
edd16368
SC		 5793}
5794
6f039790 5795static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id)
e5c880d1
SC		 5796{
5797 int i;
5798 u32 subsystem_vendor_id, subsystem_device_id;
5799
5800 subsystem_vendor_id = pdev->subsystem_vendor;
5801 subsystem_device_id = pdev->subsystem_device;
5802 *board_id = ((subsystem_device_id << 16) & 0xffff0000) |
5803 subsystem_vendor_id;
5804
5805 for (i = 0; i < ARRAY_SIZE(products); i++)
5806 if (*board_id == products[i].board_id)
5807 return i;
5808
6798cc0a
SC		 5809 if ((subsystem_vendor_id != PCI_VENDOR_ID_HP &&
5810 subsystem_vendor_id != PCI_VENDOR_ID_COMPAQ) ||
5811 !hpsa_allow_any) {
e5c880d1
SC		 5812 dev_warn(&pdev->dev, "unrecognized board ID: "
5813 "0x%08x, ignoring.\n", *board_id);
5814 return -ENODEV;
5815 }
5816 return ARRAY_SIZE(products) - 1; /* generic unknown smart array */
5817}
5818
6f039790
GKH		 5819static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
5820 unsigned long *memory_bar)
3a7774ce
SC		 5821{
5822 int i;
5823
5824 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
12d2cd47 5825 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
3a7774ce 5826 /* addressing mode bits already removed */
12d2cd47
SC		 5827 *memory_bar = pci_resource_start(pdev, i);
5828 dev_dbg(&pdev->dev, "memory BAR = %lx\n",
3a7774ce
SC		 5829 *memory_bar);
5830 return 0;
5831 }
12d2cd47 5832 dev_warn(&pdev->dev, "no memory BAR found\n");
3a7774ce
SC		 5833 return -ENODEV;
5834}
5835
6f039790
GKH		 5836static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
5837 int wait_for_ready)
2c4c8c8b 5838{
fe5389c8 5839 int i, iterations;
2c4c8c8b 5840 u32 scratchpad;
fe5389c8
SC		 5841 if (wait_for_ready)
5842 iterations = HPSA_BOARD_READY_ITERATIONS;
5843 else
5844 iterations = HPSA_BOARD_NOT_READY_ITERATIONS;
2c4c8c8b 5845
fe5389c8
SC		 5846 for (i = 0; i < iterations; i++) {
5847 scratchpad = readl(vaddr + SA5_SCRATCHPAD_OFFSET);
5848 if (wait_for_ready) {
5849 if (scratchpad == HPSA_FIRMWARE_READY)
5850 return 0;
5851 } else {
5852 if (scratchpad != HPSA_FIRMWARE_READY)
5853 return 0;
5854 }
2c4c8c8b
SC		 5855 msleep(HPSA_BOARD_READY_POLL_INTERVAL_MSECS);
5856 }
fe5389c8 5857 dev_warn(&pdev->dev, "board not ready, timed out.\n");
2c4c8c8b
SC		 5858 return -ENODEV;
5859}
5860
6f039790
GKH		 5861static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
5862 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
5863 u64 *cfg_offset)
a51fd47f
SC		 5864{
5865 *cfg_base_addr = readl(vaddr + SA5_CTCFG_OFFSET);
5866 *cfg_offset = readl(vaddr + SA5_CTMEM_OFFSET);
5867 *cfg_base_addr &= (u32) 0x0000ffff;
5868 *cfg_base_addr_index = find_PCI_BAR_index(pdev, *cfg_base_addr);
5869 if (*cfg_base_addr_index == -1) {
5870 dev_warn(&pdev->dev, "cannot find cfg_base_addr_index\n");
5871 return -ENODEV;
5872 }
5873 return 0;
5874}
5875
6f039790 5876static int hpsa_find_cfgtables(struct ctlr_info *h)
edd16368 5877{
01a02ffc
SC		 5878 u64 cfg_offset;
5879 u32 cfg_base_addr;
5880 u64 cfg_base_addr_index;
303932fd 5881 u32 trans_offset;
a51fd47f 5882 int rc;
77c4495c 5883
a51fd47f
SC		 5884 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
5885 &cfg_base_addr_index, &cfg_offset);
5886 if (rc)
5887 return rc;
77c4495c 5888 h->cfgtable = remap_pci_mem(pci_resource_start(h->pdev,
a51fd47f 5889 cfg_base_addr_index) + cfg_offset, sizeof(*h->cfgtable));
cd3c81c4
RE		 5890 if (!h->cfgtable) {
5891 dev_err(&h->pdev->dev, "Failed mapping cfgtable\n");
77c4495c 5892 return -ENOMEM;
cd3c81c4 5893 }
580ada3c
SC		 5894 rc = write_driver_ver_to_cfgtable(h->cfgtable);
5895 if (rc)
5896 return rc;
77c4495c 5897 /* Find performant mode table. */
a51fd47f 5898 trans_offset = readl(&h->cfgtable->TransMethodOffset);
77c4495c
SC		 5899 h->transtable = remap_pci_mem(pci_resource_start(h->pdev,
5900 cfg_base_addr_index)+cfg_offset+trans_offset,
5901 sizeof(*h->transtable));
5902 if (!h->transtable)
5903 return -ENOMEM;
5904 return 0;
5905}
5906
6f039790 5907static void hpsa_get_max_perf_mode_cmds(struct ctlr_info *h)
cba3d38b
SC		 5908{
5909 h->max_commands = readl(&(h->cfgtable->MaxPerformantModeCommands));
72ceeaec
SC		 5910
5911 /* Limit commands in memory limited kdump scenario. */
5912 if (reset_devices && h->max_commands > 32)
5913 h->max_commands = 32;
5914
cba3d38b
SC		 5915 if (h->max_commands < 16) {
5916 dev_warn(&h->pdev->dev, "Controller reports "
5917 "max supported commands of %d, an obvious lie. "
5918 "Using 16. Ensure that firmware is up to date.\n",
5919 h->max_commands);
5920 h->max_commands = 16;
5921 }
5922}
5923
c7ee65b3
WS		 5924/* If the controller reports that the total max sg entries is greater than 512,
5925 * then we know that chained SG blocks work. (Original smart arrays did not
5926 * support chained SG blocks and would return zero for max sg entries.)
5927 */
5928static int hpsa_supports_chained_sg_blocks(struct ctlr_info *h)
5929{
5930 return h->maxsgentries > 512;
5931}
5932
b93d7536
SC		 5933/* Interrogate the hardware for some limits:
5934 * max commands, max SG elements without chaining, and with chaining,
5935 * SG chain block size, etc.
5936 */
6f039790 5937static void hpsa_find_board_params(struct ctlr_info *h)
b93d7536 5938{
cba3d38b 5939 hpsa_get_max_perf_mode_cmds(h);
45fcb86e 5940 h->nr_cmds = h->max_commands;
b93d7536 5941 h->maxsgentries = readl(&(h->cfgtable->MaxScatterGatherElements));
283b4a9b 5942 h->fw_support = readl(&(h->cfgtable->misc_fw_support));
c7ee65b3
WS		 5943 if (hpsa_supports_chained_sg_blocks(h)) {
5944 /* Limit in-command s/g elements to 32 save dma'able memory. */
b93d7536 5945 h->max_cmd_sg_entries = 32;
1a63ea6f 5946 h->chainsize = h->maxsgentries - h->max_cmd_sg_entries;
b93d7536
SC		 5947 h->maxsgentries--; /* save one for chain pointer */
5948 } else {
c7ee65b3
WS		 5949 /*
5950 * Original smart arrays supported at most 31 s/g entries
5951 * embedded inline in the command (trying to use more
5952 * would lock up the controller)
5953 */
5954 h->max_cmd_sg_entries = 31;
1a63ea6f 5955 h->maxsgentries = 31; /* default to traditional values */
c7ee65b3 5956 h->chainsize = 0;
b93d7536 5957 }
75167d2c
SC		 5958
5959 /* Find out what task management functions are supported and cache */
5960 h->TMFSupportFlags = readl(&(h->cfgtable->TMFSupportFlags));
0e7a7fce
ST		 5961 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags))
5962 dev_warn(&h->pdev->dev, "Physical aborts not supported\n");
5963 if (!(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
5964 dev_warn(&h->pdev->dev, "Logical aborts not supported\n");
b93d7536
SC		 5965}
5966
76c46e49
SC		 5967static inline bool hpsa_CISS_signature_present(struct ctlr_info *h)
5968{
0fc9fd40 5969 if (!check_signature(h->cfgtable->Signature, "CISS", 4)) {
050f7147 5970 dev_err(&h->pdev->dev, "not a valid CISS config table\n");
76c46e49
SC		 5971 return false;
5972 }
5973 return true;
5974}
5975
97a5e98c 5976static inline void hpsa_set_driver_support_bits(struct ctlr_info *h)
f7c39101 5977{
97a5e98c 5978 u32 driver_support;
f7c39101 5979
97a5e98c 5980 driver_support = readl(&(h->cfgtable->driver_support));
0b9e7b74
AB		 5981 /* Need to enable prefetch in the SCSI core for 6400 in x86 */
5982#ifdef CONFIG_X86
97a5e98c 5983 driver_support |= ENABLE_SCSI_PREFETCH;
f7c39101 5984#endif
28e13446
SC		 5985 driver_support |= ENABLE_UNIT_ATTN;
5986 writel(driver_support, &(h->cfgtable->driver_support));
f7c39101
SC		 5987}
5988
3d0eab67
SC		 5989/* Disable DMA prefetch for the P600. Otherwise an ASIC bug may result
5990 * in a prefetch beyond physical memory.
5991 */
5992static inline void hpsa_p600_dma_prefetch_quirk(struct ctlr_info *h)
5993{
5994 u32 dma_prefetch;
5995
5996 if (h->board_id != 0x3225103C)
5997 return;
5998 dma_prefetch = readl(h->vaddr + I2O_DMA1_CFG);
5999 dma_prefetch |= 0x8000;
6000 writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG);
6001}
6002
76438d08
SC		 6003static void hpsa_wait_for_clear_event_notify_ack(struct ctlr_info *h)
6004{
6005 int i;
6006 u32 doorbell_value;
6007 unsigned long flags;
6008 /* wait until the clear_event_notify bit 6 is cleared by controller. */
6009 for (i = 0; i < MAX_CONFIG_WAIT; i++) {
6010 spin_lock_irqsave(&h->lock, flags);
6011 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
6012 spin_unlock_irqrestore(&h->lock, flags);
6013 if (!(doorbell_value & DOORBELL_CLEAR_EVENTS))
6014 break;
6015 /* delay and try again */
6016 msleep(20);
6017 }
6018}
6019
6f039790 6020static void hpsa_wait_for_mode_change_ack(struct ctlr_info *h)
eb6b2ae9
SC		 6021{
6022 int i;
6eaf46fd
SC		 6023 u32 doorbell_value;
6024 unsigned long flags;
eb6b2ae9
SC		 6025
6026 /* under certain very rare conditions, this can take awhile.
6027 * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right
6028 * as we enter this code.)
6029 */
6030 for (i = 0; i < MAX_CONFIG_WAIT; i++) {
6eaf46fd
SC		 6031 spin_lock_irqsave(&h->lock, flags);
6032 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
6033 spin_unlock_irqrestore(&h->lock, flags);
382be668 6034 if (!(doorbell_value & CFGTBL_ChangeReq))
eb6b2ae9
SC		 6035 break;
6036 /* delay and try again */
60d3f5b0 6037 usleep_range(10000, 20000);
eb6b2ae9 6038 }
3f4336f3
SC		 6039}
6040
6f039790 6041static int hpsa_enter_simple_mode(struct ctlr_info *h)
3f4336f3
SC		 6042{
6043 u32 trans_support;
6044
6045 trans_support = readl(&(h->cfgtable->TransportSupport));
6046 if (!(trans_support & SIMPLE_MODE))
6047 return -ENOTSUPP;
6048
6049 h->max_commands = readl(&(h->cfgtable->CmdsOutMax));
283b4a9b 6050
3f4336f3
SC		 6051 /* Update the field, and then ring the doorbell */
6052 writel(CFGTBL_Trans_Simple, &(h->cfgtable->HostWrite.TransportRequest));
b9af4937 6053 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
3f4336f3
SC		 6054 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
6055 hpsa_wait_for_mode_change_ack(h);
eb6b2ae9 6056 print_cfg_table(&h->pdev->dev, h->cfgtable);
283b4a9b
SC		 6057 if (!(readl(&(h->cfgtable->TransportActive)) & CFGTBL_Trans_Simple))
6058 goto error;
960a30e7 6059 h->transMethod = CFGTBL_Trans_Simple;
eb6b2ae9 6060 return 0;
283b4a9b 6061error:
050f7147 6062 dev_err(&h->pdev->dev, "failed to enter simple mode\n");
283b4a9b 6063 return -ENODEV;
eb6b2ae9
SC		 6064}
6065
6f039790 6066static int hpsa_pci_init(struct ctlr_info *h)
77c4495c 6067{
eb6b2ae9 6068 int prod_index, err;
edd16368 6069
e5c880d1
SC		 6070 prod_index = hpsa_lookup_board_id(h->pdev, &h->board_id);
6071 if (prod_index < 0)
60f923b9 6072 return prod_index;
e5c880d1
SC		 6073 h->product_name = products[prod_index].product_name;
6074 h->access = *(products[prod_index].access);
edd16368 6075
e5a44df8
MG		 6076 pci_disable_link_state(h->pdev, PCIE_LINK_STATE_L0S |
6077 PCIE_LINK_STATE_L1 | PCIE_LINK_STATE_CLKPM);
6078
55c06c71 6079 err = pci_enable_device(h->pdev);
edd16368 6080 if (err) {
55c06c71 6081 dev_warn(&h->pdev->dev, "unable to enable PCI device\n");
edd16368
SC		 6082 return err;
6083 }
6084
f79cfec6 6085 err = pci_request_regions(h->pdev, HPSA);
edd16368 6086 if (err) {
55c06c71
SC		 6087 dev_err(&h->pdev->dev,
6088 "cannot obtain PCI resources, aborting\n");
edd16368
SC		 6089 return err;
6090 }
4fa604e1
RE		 6091
6092 pci_set_master(h->pdev);
6093
6b3f4c52 6094 hpsa_interrupt_mode(h);
12d2cd47 6095 err = hpsa_pci_find_memory_BAR(h->pdev, &h->paddr);
3a7774ce 6096 if (err)
edd16368 6097 goto err_out_free_res;
edd16368 6098 h->vaddr = remap_pci_mem(h->paddr, 0x250);
204892e9
SC		 6099 if (!h->vaddr) {
6100 err = -ENOMEM;
6101 goto err_out_free_res;
6102 }
fe5389c8 6103 err = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
2c4c8c8b 6104 if (err)
edd16368 6105 goto err_out_free_res;
77c4495c
SC		 6106 err = hpsa_find_cfgtables(h);
6107 if (err)
edd16368 6108 goto err_out_free_res;
b93d7536 6109 hpsa_find_board_params(h);
edd16368 6110
76c46e49 6111 if (!hpsa_CISS_signature_present(h)) {
edd16368
SC		 6112 err = -ENODEV;
6113 goto err_out_free_res;
6114 }
97a5e98c 6115 hpsa_set_driver_support_bits(h);
3d0eab67 6116 hpsa_p600_dma_prefetch_quirk(h);
eb6b2ae9
SC		 6117 err = hpsa_enter_simple_mode(h);
6118 if (err)
edd16368 6119 goto err_out_free_res;
edd16368
SC		 6120 return 0;
6121
6122err_out_free_res:
204892e9
SC		 6123 if (h->transtable)
6124 iounmap(h->transtable);
6125 if (h->cfgtable)
6126 iounmap(h->cfgtable);
6127 if (h->vaddr)
6128 iounmap(h->vaddr);
f0bd0b68 6129 pci_disable_device(h->pdev);
55c06c71 6130 pci_release_regions(h->pdev);
edd16368
SC		 6131 return err;
6132}
6133
6f039790 6134static void hpsa_hba_inquiry(struct ctlr_info *h)
339b2b14
SC		 6135{
6136 int rc;
6137
6138#define HBA_INQUIRY_BYTE_COUNT 64
6139 h->hba_inquiry_data = kmalloc(HBA_INQUIRY_BYTE_COUNT, GFP_KERNEL);
6140 if (!h->hba_inquiry_data)
6141 return;
6142 rc = hpsa_scsi_do_inquiry(h, RAID_CTLR_LUNID, 0,
6143 h->hba_inquiry_data, HBA_INQUIRY_BYTE_COUNT);
6144 if (rc != 0) {
6145 kfree(h->hba_inquiry_data);
6146 h->hba_inquiry_data = NULL;
6147 }
6148}
6149
6f039790 6150static int hpsa_init_reset_devices(struct pci_dev *pdev)
4c2a8c40 6151{
1df8552a 6152 int rc, i;
3b747298 6153 void __iomem *vaddr;
4c2a8c40
SC		 6154
6155 if (!reset_devices)
6156 return 0;
6157
132aa220
TH		 6158 /* kdump kernel is loading, we don't know in which state is
6159 * the pci interface. The dev->enable_cnt is equal zero
6160 * so we call enable+disable, wait a while and switch it on.
6161 */
6162 rc = pci_enable_device(pdev);
6163 if (rc) {
6164 dev_warn(&pdev->dev, "Failed to enable PCI device\n");
6165 return -ENODEV;
6166 }
6167 pci_disable_device(pdev);
6168 msleep(260); /* a randomly chosen number */
6169 rc = pci_enable_device(pdev);
6170 if (rc) {
6171 dev_warn(&pdev->dev, "failed to enable device.\n");
6172 return -ENODEV;
6173 }
4fa604e1 6174
859c75ab 6175 pci_set_master(pdev);
4fa604e1 6176
3b747298
TH		 6177 vaddr = pci_ioremap_bar(pdev, 0);
6178 if (vaddr == NULL) {
6179 rc = -ENOMEM;
6180 goto out_disable;
6181 }
6182 writel(SA5_INTR_OFF, vaddr + SA5_REPLY_INTR_MASK_OFFSET);
6183 iounmap(vaddr);
6184
1df8552a
SC		 6185 /* Reset the controller with a PCI power-cycle or via doorbell */
6186 rc = hpsa_kdump_hard_reset_controller(pdev);
4c2a8c40 6187
1df8552a
SC		 6188 /* -ENOTSUPP here means we cannot reset the controller
6189 * but it's already (and still) up and running in
18867659
SC		 6190 * "performant mode". Or, it might be 640x, which can't reset
6191 * due to concerns about shared bbwc between 6402/6404 pair.
1df8552a 6192 */
adf1b3a3 6193 if (rc)
132aa220 6194 goto out_disable;
4c2a8c40
SC		 6195
6196 /* Now try to get the controller to respond to a no-op */
1ba66c9c 6197 dev_info(&pdev->dev, "Waiting for controller to respond to no-op\n");
4c2a8c40
SC		 6198 for (i = 0; i < HPSA_POST_RESET_NOOP_RETRIES; i++) {
6199 if (hpsa_noop(pdev) == 0)
6200 break;
6201 else
6202 dev_warn(&pdev->dev, "no-op failed%s\n",
6203 (i < 11 ? "; re-trying" : ""));
6204 }
132aa220
TH		 6205
6206out_disable:
6207
6208 pci_disable_device(pdev);
6209 return rc;
4c2a8c40
SC		 6210}
6211
6f039790 6212static int hpsa_allocate_cmd_pool(struct ctlr_info *h)
2e9d1b36
SC		 6213{
6214 h->cmd_pool_bits = kzalloc(
6215 DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG) *
6216 sizeof(unsigned long), GFP_KERNEL);
6217 h->cmd_pool = pci_alloc_consistent(h->pdev,
6218 h->nr_cmds * sizeof(*h->cmd_pool),
6219 &(h->cmd_pool_dhandle));
6220 h->errinfo_pool = pci_alloc_consistent(h->pdev,
6221 h->nr_cmds * sizeof(*h->errinfo_pool),
6222 &(h->errinfo_pool_dhandle));
6223 if ((h->cmd_pool_bits == NULL)
6224 || (h->cmd_pool == NULL)
6225 || (h->errinfo_pool == NULL)) {
6226 dev_err(&h->pdev->dev, "out of memory in %s", __func__);
2c143342 6227 goto clean_up;
2e9d1b36
SC		 6228 }
6229 return 0;
2c143342
RE		 6230clean_up:
6231 hpsa_free_cmd_pool(h);
6232 return -ENOMEM;
2e9d1b36
SC		 6233}
6234
6235static void hpsa_free_cmd_pool(struct ctlr_info *h)
6236{
6237 kfree(h->cmd_pool_bits);
6238 if (h->cmd_pool)
6239 pci_free_consistent(h->pdev,
6240 h->nr_cmds * sizeof(struct CommandList),
6241 h->cmd_pool, h->cmd_pool_dhandle);
aca9012a
SC		 6242 if (h->ioaccel2_cmd_pool)
6243 pci_free_consistent(h->pdev,
6244 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
6245 h->ioaccel2_cmd_pool, h->ioaccel2_cmd_pool_dhandle);
2e9d1b36
SC		 6246 if (h->errinfo_pool)
6247 pci_free_consistent(h->pdev,
6248 h->nr_cmds * sizeof(struct ErrorInfo),
6249 h->errinfo_pool,
6250 h->errinfo_pool_dhandle);
e1f7de0c
MG		 6251 if (h->ioaccel_cmd_pool)
6252 pci_free_consistent(h->pdev,
6253 h->nr_cmds * sizeof(struct io_accel1_cmd),
6254 h->ioaccel_cmd_pool, h->ioaccel_cmd_pool_dhandle);
2e9d1b36
SC		 6255}
6256
41b3cf08
SC		 6257static void hpsa_irq_affinity_hints(struct ctlr_info *h)
6258{
ec429952 6259 int i, cpu;
41b3cf08
SC		 6260
6261 cpu = cpumask_first(cpu_online_mask);
6262 for (i = 0; i < h->msix_vector; i++) {
ec429952 6263 irq_set_affinity_hint(h->intr[i], get_cpu_mask(cpu));
41b3cf08
SC		 6264 cpu = cpumask_next(cpu, cpu_online_mask);
6265 }
6266}
6267
ec501a18
RE		 6268/* clear affinity hints and free MSI-X, MSI, or legacy INTx vectors */
6269static void hpsa_free_irqs(struct ctlr_info *h)
6270{
6271 int i;
6272
6273 if (!h->msix_vector || h->intr_mode != PERF_MODE_INT) {
6274 /* Single reply queue, only one irq to free */
6275 i = h->intr_mode;
6276 irq_set_affinity_hint(h->intr[i], NULL);
6277 free_irq(h->intr[i], &h->q[i]);
6278 return;
6279 }
6280
6281 for (i = 0; i < h->msix_vector; i++) {
6282 irq_set_affinity_hint(h->intr[i], NULL);
6283 free_irq(h->intr[i], &h->q[i]);
6284 }
a4e17fc1
RE		 6285 for (; i < MAX_REPLY_QUEUES; i++)
6286 h->q[i] = 0;
ec501a18
RE		 6287}
6288
9ee61794
RE		 6289/* returns 0 on success; cleans up and returns -Enn on error */
6290static int hpsa_request_irqs(struct ctlr_info *h,
0ae01a32
SC		 6291 irqreturn_t (*msixhandler)(int, void *),
6292 irqreturn_t (*intxhandler)(int, void *))
6293{
254f796b 6294 int rc, i;
0ae01a32 6295
254f796b
MG		 6296 /*
6297 * initialize h->q[x] = x so that interrupt handlers know which
6298 * queue to process.
6299 */
6300 for (i = 0; i < MAX_REPLY_QUEUES; i++)
6301 h->q[i] = (u8) i;
6302
eee0f03a 6303 if (h->intr_mode == PERF_MODE_INT && h->msix_vector > 0) {
254f796b 6304 /* If performant mode and MSI-X, use multiple reply queues */
a4e17fc1 6305 for (i = 0; i < h->msix_vector; i++) {
254f796b
MG		 6306 rc = request_irq(h->intr[i], msixhandler,
6307 0, h->devname,
6308 &h->q[i]);
a4e17fc1
RE		 6309 if (rc) {
6310 int j;
6311
6312 dev_err(&h->pdev->dev,
6313 "failed to get irq %d for %s\n",
6314 h->intr[i], h->devname);
6315 for (j = 0; j < i; j++) {
6316 free_irq(h->intr[j], &h->q[j]);
6317 h->q[j] = 0;
6318 }
6319 for (; j < MAX_REPLY_QUEUES; j++)
6320 h->q[j] = 0;
6321 return rc;
6322 }
6323 }
41b3cf08 6324 hpsa_irq_affinity_hints(h);
254f796b
MG		 6325 } else {
6326 /* Use single reply pool */
eee0f03a 6327 if (h->msix_vector > 0 || h->msi_vector) {
254f796b
MG		 6328 rc = request_irq(h->intr[h->intr_mode],
6329 msixhandler, 0, h->devname,
6330 &h->q[h->intr_mode]);
6331 } else {
6332 rc = request_irq(h->intr[h->intr_mode],
6333 intxhandler, IRQF_SHARED, h->devname,
6334 &h->q[h->intr_mode]);
6335 }
6336 }
0ae01a32
SC		 6337 if (rc) {
6338 dev_err(&h->pdev->dev, "unable to get irq %d for %s\n",
6339 h->intr[h->intr_mode], h->devname);
6340 return -ENODEV;
6341 }
6342 return 0;
6343}
6344
6f039790 6345static int hpsa_kdump_soft_reset(struct ctlr_info *h)
64670ac8
SC		 6346{
6347 if (hpsa_send_host_reset(h, RAID_CTLR_LUNID,
6348 HPSA_RESET_TYPE_CONTROLLER)) {
6349 dev_warn(&h->pdev->dev, "Resetting array controller failed.\n");
6350 return -EIO;
6351 }
6352
6353 dev_info(&h->pdev->dev, "Waiting for board to soft reset.\n");
6354 if (hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_NOT_READY)) {
6355 dev_warn(&h->pdev->dev, "Soft reset had no effect.\n");
6356 return -1;
6357 }
6358
6359 dev_info(&h->pdev->dev, "Board reset, awaiting READY status.\n");
6360 if (hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY)) {
6361 dev_warn(&h->pdev->dev, "Board failed to become ready "
6362 "after soft reset.\n");
6363 return -1;
6364 }
6365
6366 return 0;
6367}
6368
0097f0f4 6369static void hpsa_free_irqs_and_disable_msix(struct ctlr_info *h)
64670ac8 6370{
ec501a18 6371 hpsa_free_irqs(h);
64670ac8 6372#ifdef CONFIG_PCI_MSI
0097f0f4
SC		 6373 if (h->msix_vector) {
6374 if (h->pdev->msix_enabled)
6375 pci_disable_msix(h->pdev);
6376 } else if (h->msi_vector) {
6377 if (h->pdev->msi_enabled)
6378 pci_disable_msi(h->pdev);
6379 }
64670ac8 6380#endif /* CONFIG_PCI_MSI */
0097f0f4
SC		 6381}
6382
072b0518
SC		 6383static void hpsa_free_reply_queues(struct ctlr_info *h)
6384{
6385 int i;
6386
6387 for (i = 0; i < h->nreply_queues; i++) {
6388 if (!h->reply_queue[i].head)
6389 continue;
6390 pci_free_consistent(h->pdev, h->reply_queue_size,
6391 h->reply_queue[i].head, h->reply_queue[i].busaddr);
6392 h->reply_queue[i].head = NULL;
6393 h->reply_queue[i].busaddr = 0;
6394 }
6395}
6396
0097f0f4
SC		 6397static void hpsa_undo_allocations_after_kdump_soft_reset(struct ctlr_info *h)
6398{
6399 hpsa_free_irqs_and_disable_msix(h);
64670ac8
SC		 6400 hpsa_free_sg_chain_blocks(h);
6401 hpsa_free_cmd_pool(h);
e1f7de0c 6402 kfree(h->ioaccel1_blockFetchTable);
64670ac8 6403 kfree(h->blockFetchTable);
072b0518 6404 hpsa_free_reply_queues(h);
64670ac8
SC		 6405 if (h->vaddr)
6406 iounmap(h->vaddr);
6407 if (h->transtable)
6408 iounmap(h->transtable);
6409 if (h->cfgtable)
6410 iounmap(h->cfgtable);
132aa220 6411 pci_disable_device(h->pdev);
64670ac8
SC		 6412 pci_release_regions(h->pdev);
6413 kfree(h);
6414}
6415
a0c12413 6416/* Called when controller lockup detected. */
f2405db8 6417static void fail_all_outstanding_cmds(struct ctlr_info *h)
a0c12413 6418{
f2405db8 6419 int i;
a0c12413
SC		 6420 struct CommandList *c = NULL;
6421
080ef1cc 6422 flush_workqueue(h->resubmit_wq); /* ensure all cmds are fully built */
f2405db8
DB		 6423 for (i = 0; i < h->nr_cmds; i++) {
6424 if (!test_bit(i & (BITS_PER_LONG - 1),
6425 h->cmd_pool_bits + (i / BITS_PER_LONG)))
6426 continue;
6427 c = h->cmd_pool + i;
a0c12413 6428 c->err_info->CommandStatus = CMD_HARDWARE_ERR;
5a3d16f5 6429 finish_cmd(c);
a0c12413
SC		 6430 }
6431}
6432
094963da
SC		 6433static void set_lockup_detected_for_all_cpus(struct ctlr_info *h, u32 value)
6434{
6435 int i, cpu;
6436
6437 cpu = cpumask_first(cpu_online_mask);
6438 for (i = 0; i < num_online_cpus(); i++) {
6439 u32 *lockup_detected;
6440 lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
6441 *lockup_detected = value;
6442 cpu = cpumask_next(cpu, cpu_online_mask);
6443 }
6444 wmb(); /* be sure the per-cpu variables are out to memory */
6445}
6446
a0c12413
SC		 6447static void controller_lockup_detected(struct ctlr_info *h)
6448{
6449 unsigned long flags;
094963da 6450 u32 lockup_detected;
a0c12413 6451
a0c12413
SC		 6452 h->access.set_intr_mask(h, HPSA_INTR_OFF);
6453 spin_lock_irqsave(&h->lock, flags);
094963da
SC		 6454 lockup_detected = readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
6455 if (!lockup_detected) {
6456 /* no heartbeat, but controller gave us a zero. */
6457 dev_warn(&h->pdev->dev,
6458 "lockup detected but scratchpad register is zero\n");
6459 lockup_detected = 0xffffffff;
6460 }
6461 set_lockup_detected_for_all_cpus(h, lockup_detected);
a0c12413
SC		 6462 spin_unlock_irqrestore(&h->lock, flags);
6463 dev_warn(&h->pdev->dev, "Controller lockup detected: 0x%08x\n",
094963da 6464 lockup_detected);
a0c12413
SC		 6465 pci_disable_device(h->pdev);
6466 spin_lock_irqsave(&h->lock, flags);
f2405db8 6467 fail_all_outstanding_cmds(h);
a0c12413
SC		 6468 spin_unlock_irqrestore(&h->lock, flags);
6469}
6470
a0c12413
SC		 6471static void detect_controller_lockup(struct ctlr_info *h)
6472{
6473 u64 now;
6474 u32 heartbeat;
6475 unsigned long flags;
6476
a0c12413
SC		 6477 now = get_jiffies_64();
6478 /* If we've received an interrupt recently, we're ok. */
6479 if (time_after64(h->last_intr_timestamp +
e85c5974 6480 (h->heartbeat_sample_interval), now))
a0c12413
SC		 6481 return;
6482
6483 /*
6484 * If we've already checked the heartbeat recently, we're ok.
6485 * This could happen if someone sends us a signal. We
6486 * otherwise don't care about signals in this thread.
6487 */
6488 if (time_after64(h->last_heartbeat_timestamp +
e85c5974 6489 (h->heartbeat_sample_interval), now))
a0c12413
SC		 6490 return;
6491
6492 /* If heartbeat has not changed since we last looked, we're not ok. */
6493 spin_lock_irqsave(&h->lock, flags);
6494 heartbeat = readl(&h->cfgtable->HeartBeat);
6495 spin_unlock_irqrestore(&h->lock, flags);
6496 if (h->last_heartbeat == heartbeat) {
6497 controller_lockup_detected(h);
6498 return;
6499 }
6500
6501 /* We're ok. */
6502 h->last_heartbeat = heartbeat;
6503 h->last_heartbeat_timestamp = now;
6504}
6505
9846590e 6506static void hpsa_ack_ctlr_events(struct ctlr_info *h)
76438d08
SC		 6507{
6508 int i;
6509 char *event_type;
6510
6511 /* Ask the controller to clear the events we're handling. */
1f7cee8c
SC		 6512 if ((h->transMethod & (CFGTBL_Trans_io_accel1
6513 | CFGTBL_Trans_io_accel2)) &&
76438d08
SC		 6514 (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE ||
6515 h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)) {
6516
6517 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE)
6518 event_type = "state change";
6519 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)
6520 event_type = "configuration change";
6521 /* Stop sending new RAID offload reqs via the IO accelerator */
6522 scsi_block_requests(h->scsi_host);
6523 for (i = 0; i < h->ndevices; i++)
6524 h->dev[i]->offload_enabled = 0;
23100dd9 6525 hpsa_drain_accel_commands(h);
76438d08
SC		 6526 /* Set 'accelerator path config change' bit */
6527 dev_warn(&h->pdev->dev,
6528 "Acknowledging event: 0x%08x (HP SSD Smart Path %s)\n",
6529 h->events, event_type);
6530 writel(h->events, &(h->cfgtable->clear_event_notify));
6531 /* Set the "clear event notify field update" bit 6 */
6532 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
6533 /* Wait until ctlr clears 'clear event notify field', bit 6 */
6534 hpsa_wait_for_clear_event_notify_ack(h);
6535 scsi_unblock_requests(h->scsi_host);
6536 } else {
6537 /* Acknowledge controller notification events. */
6538 writel(h->events, &(h->cfgtable->clear_event_notify));
6539 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
6540 hpsa_wait_for_clear_event_notify_ack(h);
6541#if 0
6542 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
6543 hpsa_wait_for_mode_change_ack(h);
6544#endif
6545 }
9846590e 6546 return;
76438d08
SC		 6547}
6548
6549/* Check a register on the controller to see if there are configuration
6550 * changes (added/changed/removed logical drives, etc.) which mean that
e863d68e
ST		 6551 * we should rescan the controller for devices.
6552 * Also check flag for driver-initiated rescan.
76438d08 6553 */
9846590e 6554static int hpsa_ctlr_needs_rescan(struct ctlr_info *h)
76438d08
SC		 6555{
6556 if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
9846590e 6557 return 0;
76438d08
SC		 6558
6559 h->events = readl(&(h->cfgtable->event_notify));
9846590e
SC		 6560 return h->events & RESCAN_REQUIRED_EVENT_BITS;
6561}
76438d08 6562
9846590e
SC		 6563/*
6564 * Check if any of the offline devices have become ready
6565 */
6566static int hpsa_offline_devices_ready(struct ctlr_info *h)
6567{
6568 unsigned long flags;
6569 struct offline_device_entry *d;
6570 struct list_head *this, *tmp;
6571
6572 spin_lock_irqsave(&h->offline_device_lock, flags);
6573 list_for_each_safe(this, tmp, &h->offline_device_list) {
6574 d = list_entry(this, struct offline_device_entry,
6575 offline_list);
6576 spin_unlock_irqrestore(&h->offline_device_lock, flags);
d1fea47c
SC		 6577 if (!hpsa_volume_offline(h, d->scsi3addr)) {
6578 spin_lock_irqsave(&h->offline_device_lock, flags);
6579 list_del(&d->offline_list);
6580 spin_unlock_irqrestore(&h->offline_device_lock, flags);
9846590e 6581 return 1;
d1fea47c 6582 }
9846590e
SC		 6583 spin_lock_irqsave(&h->offline_device_lock, flags);
6584 }
6585 spin_unlock_irqrestore(&h->offline_device_lock, flags);
6586 return 0;
76438d08
SC		 6587}
6588
9846590e 6589
8a98db73 6590static void hpsa_monitor_ctlr_worker(struct work_struct *work)
a0c12413
SC		 6591{
6592 unsigned long flags;
8a98db73
SC		 6593 struct ctlr_info *h = container_of(to_delayed_work(work),
6594 struct ctlr_info, monitor_ctlr_work);
6595 detect_controller_lockup(h);
094963da 6596 if (lockup_detected(h))
8a98db73 6597 return;
9846590e
SC		 6598
6599 if (hpsa_ctlr_needs_rescan(h) || hpsa_offline_devices_ready(h)) {
6600 scsi_host_get(h->scsi_host);
9846590e
SC		 6601 hpsa_ack_ctlr_events(h);
6602 hpsa_scan_start(h->scsi_host);
6603 scsi_host_put(h->scsi_host);
6604 }
6605
8a98db73
SC		 6606 spin_lock_irqsave(&h->lock, flags);
6607 if (h->remove_in_progress) {
6608 spin_unlock_irqrestore(&h->lock, flags);
a0c12413
SC		 6609 return;
6610 }
8a98db73
SC		 6611 schedule_delayed_work(&h->monitor_ctlr_work,
6612 h->heartbeat_sample_interval);
6613 spin_unlock_irqrestore(&h->lock, flags);
a0c12413
SC		 6614}
6615
6f039790 6616static int hpsa_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
edd16368 6617{
4c2a8c40 6618 int dac, rc;
edd16368 6619 struct ctlr_info *h;
64670ac8
SC		 6620 int try_soft_reset = 0;
6621 unsigned long flags;
edd16368
SC		 6622
6623 if (number_of_controllers == 0)
6624 printk(KERN_INFO DRIVER_NAME "\n");
edd16368 6625
4c2a8c40 6626 rc = hpsa_init_reset_devices(pdev);
64670ac8
SC		 6627 if (rc) {
6628 if (rc != -ENOTSUPP)
6629 return rc;
6630 /* If the reset fails in a particular way (it has no way to do
6631 * a proper hard reset, so returns -ENOTSUPP) we can try to do
6632 * a soft reset once we get the controller configured up to the
6633 * point that it can accept a command.
6634 */
6635 try_soft_reset = 1;
6636 rc = 0;
6637 }
6638
6639reinit_after_soft_reset:
edd16368 6640
303932fd
DB		 6641 /* Command structures must be aligned on a 32-byte boundary because
6642 * the 5 lower bits of the address are used by the hardware. and by
6643 * the driver. See comments in hpsa.h for more info.
6644 */
303932fd 6645 BUILD_BUG_ON(sizeof(struct CommandList) % COMMANDLIST_ALIGNMENT);
edd16368
SC		 6646 h = kzalloc(sizeof(*h), GFP_KERNEL);
6647 if (!h)
ecd9aad4 6648 return -ENOMEM;
edd16368 6649
55c06c71 6650 h->pdev = pdev;
a9a3a273 6651 h->intr_mode = hpsa_simple_mode ? SIMPLE_MODE_INT : PERF_MODE_INT;
9846590e 6652 INIT_LIST_HEAD(&h->offline_device_list);
6eaf46fd 6653 spin_lock_init(&h->lock);
9846590e 6654 spin_lock_init(&h->offline_device_lock);
6eaf46fd 6655 spin_lock_init(&h->scan_lock);
0390f0c0 6656 spin_lock_init(&h->passthru_count_lock);
094963da 6657
080ef1cc
DB		 6658 h->resubmit_wq = alloc_workqueue("hpsa", WQ_MEM_RECLAIM, 0);
6659 if (!h->resubmit_wq) {
6660 dev_err(&h->pdev->dev, "Failed to allocate work queue\n");
6661 rc = -ENOMEM;
6662 goto clean1;
6663 }
094963da
SC		 6664 /* Allocate and clear per-cpu variable lockup_detected */
6665 h->lockup_detected = alloc_percpu(u32);
2a5ac326
SC		 6666 if (!h->lockup_detected) {
6667 rc = -ENOMEM;
094963da 6668 goto clean1;
2a5ac326 6669 }
094963da
SC		 6670 set_lockup_detected_for_all_cpus(h, 0);
6671
55c06c71 6672 rc = hpsa_pci_init(h);
ecd9aad4 6673 if (rc != 0)
edd16368
SC		 6674 goto clean1;
6675
f79cfec6 6676 sprintf(h->devname, HPSA "%d", number_of_controllers);
edd16368
SC		 6677 h->ctlr = number_of_controllers;
6678 number_of_controllers++;
edd16368
SC		 6679
6680 /* configure PCI DMA stuff */
ecd9aad4
SC		 6681 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
6682 if (rc == 0) {
edd16368 6683 dac = 1;
ecd9aad4
SC		 6684 } else {
6685 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6686 if (rc == 0) {
6687 dac = 0;
6688 } else {
6689 dev_err(&pdev->dev, "no suitable DMA available\n");
6690 goto clean1;
6691 }
edd16368
SC		 6692 }
6693
6694 /* make sure the board interrupts are off */
6695 h->access.set_intr_mask(h, HPSA_INTR_OFF);
10f66018 6696
9ee61794 6697 if (hpsa_request_irqs(h, do_hpsa_intr_msi, do_hpsa_intr_intx))
edd16368 6698 goto clean2;
303932fd
DB		 6699 dev_info(&pdev->dev, "%s: <0x%x> at IRQ %d%s using DAC\n",
6700 h->devname, pdev->device,
a9a3a273 6701 h->intr[h->intr_mode], dac ? "" : " not");
8947fd10
RE		 6702 rc = hpsa_allocate_cmd_pool(h);
6703 if (rc)
6704 goto clean2_and_free_irqs;
33a2ffce
SC		 6705 if (hpsa_allocate_sg_chain_blocks(h))
6706 goto clean4;
a08a8471
SC		 6707 init_waitqueue_head(&h->scan_wait_queue);
6708 h->scan_finished = 1; /* no scan currently in progress */
edd16368
SC		 6709
6710 pci_set_drvdata(pdev, h);
9a41338e 6711 h->ndevices = 0;
316b221a 6712 h->hba_mode_enabled = 0;
9a41338e
SC		 6713 h->scsi_host = NULL;
6714 spin_lock_init(&h->devlock);
64670ac8
SC		 6715 hpsa_put_ctlr_into_performant_mode(h);
6716
6717 /* At this point, the controller is ready to take commands.
6718 * Now, if reset_devices and the hard reset didn't work, try
6719 * the soft reset and see if that works.
6720 */
6721 if (try_soft_reset) {
6722
6723 /* This is kind of gross. We may or may not get a completion
6724 * from the soft reset command, and if we do, then the value
6725 * from the fifo may or may not be valid. So, we wait 10 secs
6726 * after the reset throwing away any completions we get during
6727 * that time. Unregister the interrupt handler and register
6728 * fake ones to scoop up any residual completions.
6729 */
6730 spin_lock_irqsave(&h->lock, flags);
6731 h->access.set_intr_mask(h, HPSA_INTR_OFF);
6732 spin_unlock_irqrestore(&h->lock, flags);
ec501a18 6733 hpsa_free_irqs(h);
9ee61794 6734 rc = hpsa_request_irqs(h, hpsa_msix_discard_completions,
64670ac8
SC		 6735 hpsa_intx_discard_completions);
6736 if (rc) {
9ee61794
RE		 6737 dev_warn(&h->pdev->dev,
6738 "Failed to request_irq after soft reset.\n");
64670ac8
SC		 6739 goto clean4;
6740 }
6741
6742 rc = hpsa_kdump_soft_reset(h);
6743 if (rc)
6744 /* Neither hard nor soft reset worked, we're hosed. */
6745 goto clean4;
6746
6747 dev_info(&h->pdev->dev, "Board READY.\n");
6748 dev_info(&h->pdev->dev,
6749 "Waiting for stale completions to drain.\n");
6750 h->access.set_intr_mask(h, HPSA_INTR_ON);
6751 msleep(10000);
6752 h->access.set_intr_mask(h, HPSA_INTR_OFF);
6753
6754 rc = controller_reset_failed(h->cfgtable);
6755 if (rc)
6756 dev_info(&h->pdev->dev,
6757 "Soft reset appears to have failed.\n");
6758
6759 /* since the controller's reset, we have to go back and re-init
6760 * everything. Easiest to just forget what we've done and do it
6761 * all over again.
6762 */
6763 hpsa_undo_allocations_after_kdump_soft_reset(h);
6764 try_soft_reset = 0;
6765 if (rc)
6766 /* don't go to clean4, we already unallocated */
6767 return -ENODEV;
6768
6769 goto reinit_after_soft_reset;
6770 }
edd16368 6771
316b221a
SC		 6772 /* Enable Accelerated IO path at driver layer */
6773 h->acciopath_status = 1;
da0697bd 6774
e863d68e 6775
edd16368
SC		 6776 /* Turn the interrupts on so we can service requests */
6777 h->access.set_intr_mask(h, HPSA_INTR_ON);
6778
339b2b14 6779 hpsa_hba_inquiry(h);
edd16368 6780 hpsa_register_scsi(h); /* hook ourselves into SCSI subsystem */
8a98db73
SC		 6781
6782 /* Monitor the controller for firmware lockups */
6783 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
6784 INIT_DELAYED_WORK(&h->monitor_ctlr_work, hpsa_monitor_ctlr_worker);
6785 schedule_delayed_work(&h->monitor_ctlr_work,
6786 h->heartbeat_sample_interval);
88bf6d62 6787 return 0;
edd16368
SC		 6788
6789clean4:
33a2ffce 6790 hpsa_free_sg_chain_blocks(h);
2e9d1b36 6791 hpsa_free_cmd_pool(h);
8947fd10 6792clean2_and_free_irqs:
ec501a18 6793 hpsa_free_irqs(h);
edd16368
SC		 6794clean2:
6795clean1:
080ef1cc
DB		 6796 if (h->resubmit_wq)
6797 destroy_workqueue(h->resubmit_wq);
094963da
SC		 6798 if (h->lockup_detected)
6799 free_percpu(h->lockup_detected);
edd16368 6800 kfree(h);
ecd9aad4 6801 return rc;
edd16368
SC		 6802}
6803
6804static void hpsa_flush_cache(struct ctlr_info *h)
6805{
6806 char *flush_buf;
6807 struct CommandList *c;
702890e3
SC		 6808
6809 /* Don't bother trying to flush the cache if locked up */
094963da 6810 if (unlikely(lockup_detected(h)))
702890e3 6811 return;
edd16368
SC		 6812 flush_buf = kzalloc(4, GFP_KERNEL);
6813 if (!flush_buf)
6814 return;
6815
45fcb86e 6816 c = cmd_alloc(h);
edd16368 6817 if (!c) {
45fcb86e 6818 dev_warn(&h->pdev->dev, "cmd_alloc returned NULL!\n");
edd16368
SC		 6819 goto out_of_memory;
6820 }
a2dac136
SC		 6821 if (fill_cmd(c, HPSA_CACHE_FLUSH, h, flush_buf, 4, 0,
6822 RAID_CTLR_LUNID, TYPE_CMD)) {
6823 goto out;
6824 }
edd16368
SC		 6825 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_TODEVICE);
6826 if (c->err_info->CommandStatus != 0)
a2dac136 6827out:
edd16368
SC		 6828 dev_warn(&h->pdev->dev,
6829 "error flushing cache on controller\n");
45fcb86e 6830 cmd_free(h, c);
edd16368
SC		 6831out_of_memory:
6832 kfree(flush_buf);
6833}
6834
6835static void hpsa_shutdown(struct pci_dev *pdev)
6836{
6837 struct ctlr_info *h;
6838
6839 h = pci_get_drvdata(pdev);
6840 /* Turn board interrupts off and send the flush cache command
6841 * sendcmd will turn off interrupt, and send the flush...
6842 * To write all data in the battery backed cache to disks
6843 */
6844 hpsa_flush_cache(h);
6845 h->access.set_intr_mask(h, HPSA_INTR_OFF);
0097f0f4 6846 hpsa_free_irqs_and_disable_msix(h);
edd16368
SC		 6847}
6848
6f039790 6849static void hpsa_free_device_info(struct ctlr_info *h)
55e14e76
SC		 6850{
6851 int i;
6852
6853 for (i = 0; i < h->ndevices; i++)
6854 kfree(h->dev[i]);
6855}
6856
6f039790 6857static void hpsa_remove_one(struct pci_dev *pdev)
edd16368
SC		 6858{
6859 struct ctlr_info *h;
8a98db73 6860 unsigned long flags;
edd16368
SC		 6861
6862 if (pci_get_drvdata(pdev) == NULL) {
a0c12413 6863 dev_err(&pdev->dev, "unable to remove device\n");
edd16368
SC		 6864 return;
6865 }
6866 h = pci_get_drvdata(pdev);
8a98db73
SC		 6867
6868 /* Get rid of any controller monitoring work items */
6869 spin_lock_irqsave(&h->lock, flags);
6870 h->remove_in_progress = 1;
6871 cancel_delayed_work(&h->monitor_ctlr_work);
6872 spin_unlock_irqrestore(&h->lock, flags);
edd16368
SC		 6873 hpsa_unregister_scsi(h); /* unhook from SCSI subsystem */
6874 hpsa_shutdown(pdev);
080ef1cc 6875 destroy_workqueue(h->resubmit_wq);
edd16368 6876 iounmap(h->vaddr);
204892e9
SC		 6877 iounmap(h->transtable);
6878 iounmap(h->cfgtable);
55e14e76 6879 hpsa_free_device_info(h);
33a2ffce 6880 hpsa_free_sg_chain_blocks(h);
edd16368
SC		 6881 pci_free_consistent(h->pdev,
6882 h->nr_cmds * sizeof(struct CommandList),
6883 h->cmd_pool, h->cmd_pool_dhandle);
6884 pci_free_consistent(h->pdev,
6885 h->nr_cmds * sizeof(struct ErrorInfo),
6886 h->errinfo_pool, h->errinfo_pool_dhandle);
072b0518 6887 hpsa_free_reply_queues(h);
edd16368 6888 kfree(h->cmd_pool_bits);
303932fd 6889 kfree(h->blockFetchTable);
e1f7de0c 6890 kfree(h->ioaccel1_blockFetchTable);
aca9012a 6891 kfree(h->ioaccel2_blockFetchTable);
339b2b14 6892 kfree(h->hba_inquiry_data);
f0bd0b68 6893 pci_disable_device(pdev);
edd16368 6894 pci_release_regions(pdev);
094963da 6895 free_percpu(h->lockup_detected);
edd16368
SC		 6896 kfree(h);
6897}
6898
6899static int hpsa_suspend(__attribute__((unused)) struct pci_dev *pdev,
6900 __attribute__((unused)) pm_message_t state)
6901{
6902 return -ENOSYS;
6903}
6904
6905static int hpsa_resume(__attribute__((unused)) struct pci_dev *pdev)
6906{
6907 return -ENOSYS;
6908}
6909
6910static struct pci_driver hpsa_pci_driver = {
f79cfec6 6911 .name = HPSA,
edd16368 6912 .probe = hpsa_init_one,
6f039790 6913 .remove = hpsa_remove_one,
edd16368
SC		 6914 .id_table = hpsa_pci_device_id, /* id_table */
6915 .shutdown = hpsa_shutdown,
6916 .suspend = hpsa_suspend,
6917 .resume = hpsa_resume,
6918};
6919
303932fd
DB		 6920/* Fill in bucket_map[], given nsgs (the max number of
6921 * scatter gather elements supported) and bucket[],
6922 * which is an array of 8 integers. The bucket[] array
6923 * contains 8 different DMA transfer sizes (in 16
6924 * byte increments) which the controller uses to fetch
6925 * commands. This function fills in bucket_map[], which
6926 * maps a given number of scatter gather elements to one of
6927 * the 8 DMA transfer sizes. The point of it is to allow the
6928 * controller to only do as much DMA as needed to fetch the
6929 * command, with the DMA transfer size encoded in the lower
6930 * bits of the command address.
6931 */
6932static void calc_bucket_map(int bucket[], int num_buckets,
2b08b3e9 6933 int nsgs, int min_blocks, u32 *bucket_map)
303932fd
DB		 6934{
6935 int i, j, b, size;
6936
303932fd
DB		 6937 /* Note, bucket_map must have nsgs+1 entries. */
6938 for (i = 0; i <= nsgs; i++) {
6939 /* Compute size of a command with i SG entries */
e1f7de0c 6940 size = i + min_blocks;
303932fd
DB		 6941 b = num_buckets; /* Assume the biggest bucket */
6942 /* Find the bucket that is just big enough */
e1f7de0c 6943 for (j = 0; j < num_buckets; j++) {
303932fd
DB		 6944 if (bucket[j] >= size) {
6945 b = j;
6946 break;
6947 }
6948 }
6949 /* for a command with i SG entries, use bucket b. */
6950 bucket_map[i] = b;
6951 }
6952}
6953
e1f7de0c 6954static void hpsa_enter_performant_mode(struct ctlr_info *h, u32 trans_support)
303932fd 6955{
6c311b57
SC		 6956 int i;
6957 unsigned long register_value;
e1f7de0c
MG		 6958 unsigned long transMethod = CFGTBL_Trans_Performant |
6959 (trans_support & CFGTBL_Trans_use_short_tags) |
b9af4937
SC		 6960 CFGTBL_Trans_enable_directed_msix |
6961 (trans_support & (CFGTBL_Trans_io_accel1 |
6962 CFGTBL_Trans_io_accel2));
e1f7de0c 6963 struct access_method access = SA5_performant_access;
def342bd
SC		 6964
6965 /* This is a bit complicated. There are 8 registers on
6966 * the controller which we write to to tell it 8 different
6967 * sizes of commands which there may be. It's a way of
6968 * reducing the DMA done to fetch each command. Encoded into
6969 * each command's tag are 3 bits which communicate to the controller
6970 * which of the eight sizes that command fits within. The size of
6971 * each command depends on how many scatter gather entries there are.
6972 * Each SG entry requires 16 bytes. The eight registers are programmed
6973 * with the number of 16-byte blocks a command of that size requires.
6974 * The smallest command possible requires 5 such 16 byte blocks.
d66ae08b 6975 * the largest command possible requires SG_ENTRIES_IN_CMD + 4 16-byte
def342bd
SC		 6976 * blocks. Note, this only extends to the SG entries contained
6977 * within the command block, and does not extend to chained blocks
6978 * of SG elements. bft[] contains the eight values we write to
6979 * the registers. They are not evenly distributed, but have more
6980 * sizes for small commands, and fewer sizes for larger commands.
6981 */
d66ae08b 6982 int bft[8] = {5, 6, 8, 10, 12, 20, 28, SG_ENTRIES_IN_CMD + 4};
b9af4937
SC		 6983#define MIN_IOACCEL2_BFT_ENTRY 5
6984#define HPSA_IOACCEL2_HEADER_SZ 4
6985 int bft2[16] = {MIN_IOACCEL2_BFT_ENTRY, 6, 7, 8, 9, 10, 11, 12,
6986 13, 14, 15, 16, 17, 18, 19,
6987 HPSA_IOACCEL2_HEADER_SZ + IOACCEL2_MAXSGENTRIES};
6988 BUILD_BUG_ON(ARRAY_SIZE(bft2) != 16);
6989 BUILD_BUG_ON(ARRAY_SIZE(bft) != 8);
6990 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) >
6991 16 * MIN_IOACCEL2_BFT_ENTRY);
6992 BUILD_BUG_ON(sizeof(struct ioaccel2_sg_element) != 16);
d66ae08b 6993 BUILD_BUG_ON(28 > SG_ENTRIES_IN_CMD + 4);
303932fd
DB		 6994 /* 5 = 1 s/g entry or 4k
6995 * 6 = 2 s/g entry or 8k
6996 * 8 = 4 s/g entry or 16k
6997 * 10 = 6 s/g entry or 24k
6998 */
303932fd 6999
b3a52e79
SC		 7000 /* If the controller supports either ioaccel method then
7001 * we can also use the RAID stack submit path that does not
7002 * perform the superfluous readl() after each command submission.
7003 */
7004 if (trans_support & (CFGTBL_Trans_io_accel1 | CFGTBL_Trans_io_accel2))
7005 access = SA5_performant_access_no_read;
7006
303932fd 7007 /* Controller spec: zero out this buffer. */
072b0518
SC		 7008 for (i = 0; i < h->nreply_queues; i++)
7009 memset(h->reply_queue[i].head, 0, h->reply_queue_size);
303932fd 7010
d66ae08b
SC		 7011 bft[7] = SG_ENTRIES_IN_CMD + 4;
7012 calc_bucket_map(bft, ARRAY_SIZE(bft),
e1f7de0c 7013 SG_ENTRIES_IN_CMD, 4, h->blockFetchTable);
303932fd
DB		 7014 for (i = 0; i < 8; i++)
7015 writel(bft[i], &h->transtable->BlockFetch[i]);
7016
7017 /* size of controller ring buffer */
7018 writel(h->max_commands, &h->transtable->RepQSize);
254f796b 7019 writel(h->nreply_queues, &h->transtable->RepQCount);
303932fd
DB		 7020 writel(0, &h->transtable->RepQCtrAddrLow32);
7021 writel(0, &h->transtable->RepQCtrAddrHigh32);
254f796b
MG		 7022
7023 for (i = 0; i < h->nreply_queues; i++) {
7024 writel(0, &h->transtable->RepQAddr[i].upper);
072b0518 7025 writel(h->reply_queue[i].busaddr,
254f796b
MG		 7026 &h->transtable->RepQAddr[i].lower);
7027 }
7028
b9af4937 7029 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
e1f7de0c
MG		 7030 writel(transMethod, &(h->cfgtable->HostWrite.TransportRequest));
7031 /*
7032 * enable outbound interrupt coalescing in accelerator mode;
7033 */
7034 if (trans_support & CFGTBL_Trans_io_accel1) {
7035 access = SA5_ioaccel_mode1_access;
7036 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
7037 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
c349775e
ST		 7038 } else {
7039 if (trans_support & CFGTBL_Trans_io_accel2) {
7040 access = SA5_ioaccel_mode2_access;
7041 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
7042 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
7043 }
e1f7de0c 7044 }
303932fd 7045 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
3f4336f3 7046 hpsa_wait_for_mode_change_ack(h);
303932fd
DB		 7047 register_value = readl(&(h->cfgtable->TransportActive));
7048 if (!(register_value & CFGTBL_Trans_Performant)) {
050f7147
SC		 7049 dev_err(&h->pdev->dev,
7050 "performant mode problem - transport not active\n");
303932fd
DB		 7051 return;
7052 }
960a30e7 7053 /* Change the access methods to the performant access methods */
e1f7de0c
MG		 7054 h->access = access;
7055 h->transMethod = transMethod;
7056
b9af4937
SC		 7057 if (!((trans_support & CFGTBL_Trans_io_accel1) ||
7058 (trans_support & CFGTBL_Trans_io_accel2)))
e1f7de0c
MG		 7059 return;
7060
b9af4937
SC		 7061 if (trans_support & CFGTBL_Trans_io_accel1) {
7062 /* Set up I/O accelerator mode */
7063 for (i = 0; i < h->nreply_queues; i++) {
7064 writel(i, h->vaddr + IOACCEL_MODE1_REPLY_QUEUE_INDEX);
7065 h->reply_queue[i].current_entry =
7066 readl(h->vaddr + IOACCEL_MODE1_PRODUCER_INDEX);
7067 }
7068 bft[7] = h->ioaccel_maxsg + 8;
7069 calc_bucket_map(bft, ARRAY_SIZE(bft), h->ioaccel_maxsg, 8,
7070 h->ioaccel1_blockFetchTable);
e1f7de0c 7071
b9af4937 7072 /* initialize all reply queue entries to unused */
072b0518
SC		 7073 for (i = 0; i < h->nreply_queues; i++)
7074 memset(h->reply_queue[i].head,
7075 (u8) IOACCEL_MODE1_REPLY_UNUSED,
7076 h->reply_queue_size);
e1f7de0c 7077
b9af4937
SC		 7078 /* set all the constant fields in the accelerator command
7079 * frames once at init time to save CPU cycles later.
7080 */
7081 for (i = 0; i < h->nr_cmds; i++) {
7082 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[i];
7083
7084 cp->function = IOACCEL1_FUNCTION_SCSIIO;
7085 cp->err_info = (u32) (h->errinfo_pool_dhandle +
7086 (i * sizeof(struct ErrorInfo)));
7087 cp->err_info_len = sizeof(struct ErrorInfo);
7088 cp->sgl_offset = IOACCEL1_SGLOFFSET;
2b08b3e9
DB		 7089 cp->host_context_flags =
7090 cpu_to_le16(IOACCEL1_HCFLAGS_CISS_FORMAT);
b9af4937
SC		 7091 cp->timeout_sec = 0;
7092 cp->ReplyQueue = 0;
50a0decf 7093 cp->tag =
f2405db8 7094 cpu_to_le64((i << DIRECT_LOOKUP_SHIFT));
50a0decf
SC		 7095 cp->host_addr =
7096 cpu_to_le64(h->ioaccel_cmd_pool_dhandle +
b9af4937 7097 (i * sizeof(struct io_accel1_cmd)));
b9af4937
SC		 7098 }
7099 } else if (trans_support & CFGTBL_Trans_io_accel2) {
7100 u64 cfg_offset, cfg_base_addr_index;
7101 u32 bft2_offset, cfg_base_addr;
7102 int rc;
7103
7104 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
7105 &cfg_base_addr_index, &cfg_offset);
7106 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) != 64);
7107 bft2[15] = h->ioaccel_maxsg + HPSA_IOACCEL2_HEADER_SZ;
7108 calc_bucket_map(bft2, ARRAY_SIZE(bft2), h->ioaccel_maxsg,
7109 4, h->ioaccel2_blockFetchTable);
7110 bft2_offset = readl(&h->cfgtable->io_accel_request_size_offset);
7111 BUILD_BUG_ON(offsetof(struct CfgTable,
7112 io_accel_request_size_offset) != 0xb8);
7113 h->ioaccel2_bft2_regs =
7114 remap_pci_mem(pci_resource_start(h->pdev,
7115 cfg_base_addr_index) +
7116 cfg_offset + bft2_offset,
7117 ARRAY_SIZE(bft2) *
7118 sizeof(*h->ioaccel2_bft2_regs));
7119 for (i = 0; i < ARRAY_SIZE(bft2); i++)
7120 writel(bft2[i], &h->ioaccel2_bft2_regs[i]);
e1f7de0c 7121 }
b9af4937
SC		 7122 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
7123 hpsa_wait_for_mode_change_ack(h);
e1f7de0c
MG		 7124}
7125
7126static int hpsa_alloc_ioaccel_cmd_and_bft(struct ctlr_info *h)
7127{
283b4a9b
SC		 7128 h->ioaccel_maxsg =
7129 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
7130 if (h->ioaccel_maxsg > IOACCEL1_MAXSGENTRIES)
7131 h->ioaccel_maxsg = IOACCEL1_MAXSGENTRIES;
7132
e1f7de0c
MG		 7133 /* Command structures must be aligned on a 128-byte boundary
7134 * because the 7 lower bits of the address are used by the
7135 * hardware.
7136 */
e1f7de0c
MG		 7137 BUILD_BUG_ON(sizeof(struct io_accel1_cmd) %
7138 IOACCEL1_COMMANDLIST_ALIGNMENT);
7139 h->ioaccel_cmd_pool =
7140 pci_alloc_consistent(h->pdev,
7141 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
7142 &(h->ioaccel_cmd_pool_dhandle));
7143
7144 h->ioaccel1_blockFetchTable =
283b4a9b 7145 kmalloc(((h->ioaccel_maxsg + 1) *
e1f7de0c
MG		 7146 sizeof(u32)), GFP_KERNEL);
7147
7148 if ((h->ioaccel_cmd_pool == NULL) ||
7149 (h->ioaccel1_blockFetchTable == NULL))
7150 goto clean_up;
7151
7152 memset(h->ioaccel_cmd_pool, 0,
7153 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool));
7154 return 0;
7155
7156clean_up:
7157 if (h->ioaccel_cmd_pool)
7158 pci_free_consistent(h->pdev,
7159 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
7160 h->ioaccel_cmd_pool, h->ioaccel_cmd_pool_dhandle);
7161 kfree(h->ioaccel1_blockFetchTable);
7162 return 1;
6c311b57
SC		 7163}
7164
aca9012a
SC		 7165static int ioaccel2_alloc_cmds_and_bft(struct ctlr_info *h)
7166{
7167 /* Allocate ioaccel2 mode command blocks and block fetch table */
7168
7169 h->ioaccel_maxsg =
7170 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
7171 if (h->ioaccel_maxsg > IOACCEL2_MAXSGENTRIES)
7172 h->ioaccel_maxsg = IOACCEL2_MAXSGENTRIES;
7173
aca9012a
SC		 7174 BUILD_BUG_ON(sizeof(struct io_accel2_cmd) %
7175 IOACCEL2_COMMANDLIST_ALIGNMENT);
7176 h->ioaccel2_cmd_pool =
7177 pci_alloc_consistent(h->pdev,
7178 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
7179 &(h->ioaccel2_cmd_pool_dhandle));
7180
7181 h->ioaccel2_blockFetchTable =
7182 kmalloc(((h->ioaccel_maxsg + 1) *
7183 sizeof(u32)), GFP_KERNEL);
7184
7185 if ((h->ioaccel2_cmd_pool == NULL) ||
7186 (h->ioaccel2_blockFetchTable == NULL))
7187 goto clean_up;
7188
7189 memset(h->ioaccel2_cmd_pool, 0,
7190 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool));
7191 return 0;
7192
7193clean_up:
7194 if (h->ioaccel2_cmd_pool)
7195 pci_free_consistent(h->pdev,
7196 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
7197 h->ioaccel2_cmd_pool, h->ioaccel2_cmd_pool_dhandle);
7198 kfree(h->ioaccel2_blockFetchTable);
7199 return 1;
7200}
7201
6f039790 7202static void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h)
6c311b57
SC		 7203{
7204 u32 trans_support;
e1f7de0c
MG		 7205 unsigned long transMethod = CFGTBL_Trans_Performant |
7206 CFGTBL_Trans_use_short_tags;
254f796b 7207 int i;
6c311b57 7208
02ec19c8
SC		 7209 if (hpsa_simple_mode)
7210 return;
7211
67c99a72 7212 trans_support = readl(&(h->cfgtable->TransportSupport));
7213 if (!(trans_support & PERFORMANT_MODE))
7214 return;
7215
e1f7de0c
MG		 7216 /* Check for I/O accelerator mode support */
7217 if (trans_support & CFGTBL_Trans_io_accel1) {
7218 transMethod |= CFGTBL_Trans_io_accel1 |
7219 CFGTBL_Trans_enable_directed_msix;
7220 if (hpsa_alloc_ioaccel_cmd_and_bft(h))
7221 goto clean_up;
aca9012a
SC		 7222 } else {
7223 if (trans_support & CFGTBL_Trans_io_accel2) {
7224 transMethod |= CFGTBL_Trans_io_accel2 |
7225 CFGTBL_Trans_enable_directed_msix;
7226 if (ioaccel2_alloc_cmds_and_bft(h))
7227 goto clean_up;
7228 }
e1f7de0c
MG		 7229 }
7230
eee0f03a 7231 h->nreply_queues = h->msix_vector > 0 ? h->msix_vector : 1;
cba3d38b 7232 hpsa_get_max_perf_mode_cmds(h);
6c311b57 7233 /* Performant mode ring buffer and supporting data structures */
072b0518 7234 h->reply_queue_size = h->max_commands * sizeof(u64);
6c311b57 7235
254f796b 7236 for (i = 0; i < h->nreply_queues; i++) {
072b0518
SC		 7237 h->reply_queue[i].head = pci_alloc_consistent(h->pdev,
7238 h->reply_queue_size,
7239 &(h->reply_queue[i].busaddr));
7240 if (!h->reply_queue[i].head)
7241 goto clean_up;
254f796b
MG		 7242 h->reply_queue[i].size = h->max_commands;
7243 h->reply_queue[i].wraparound = 1; /* spec: init to 1 */
7244 h->reply_queue[i].current_entry = 0;
7245 }
7246
6c311b57 7247 /* Need a block fetch table for performant mode */
d66ae08b 7248 h->blockFetchTable = kmalloc(((SG_ENTRIES_IN_CMD + 1) *
6c311b57 7249 sizeof(u32)), GFP_KERNEL);
072b0518 7250 if (!h->blockFetchTable)
6c311b57
SC		 7251 goto clean_up;
7252
e1f7de0c 7253 hpsa_enter_performant_mode(h, trans_support);
303932fd
DB		 7254 return;
7255
7256clean_up:
072b0518 7257 hpsa_free_reply_queues(h);
303932fd
DB		 7258 kfree(h->blockFetchTable);
7259}
7260
23100dd9 7261static int is_accelerated_cmd(struct CommandList *c)
76438d08 7262{
23100dd9
SC		 7263 return c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_IOACCEL2;
7264}
7265
7266static void hpsa_drain_accel_commands(struct ctlr_info *h)
7267{
7268 struct CommandList *c = NULL;
f2405db8 7269 int i, accel_cmds_out;
76438d08 7270
f2405db8 7271 do { /* wait for all outstanding ioaccel commands to drain out */
23100dd9 7272 accel_cmds_out = 0;
f2405db8
DB		 7273 for (i = 0; i < h->nr_cmds; i++) {
7274 if (!test_bit(i & (BITS_PER_LONG - 1),
7275 h->cmd_pool_bits + (i / BITS_PER_LONG)))
7276 continue;
7277 c = h->cmd_pool + i;
23100dd9 7278 accel_cmds_out += is_accelerated_cmd(c);
f2405db8 7279 }
23100dd9 7280 if (accel_cmds_out <= 0)
f2405db8 7281 break;
76438d08
SC		 7282 msleep(100);
7283 } while (1);
7284}
7285
edd16368
SC		 7286/*
7287 * This is it. Register the PCI driver information for the cards we control
7288 * the OS will call our registered routines when it finds one of our cards.
7289 */
7290static int __init hpsa_init(void)
7291{
31468401 7292 return pci_register_driver(&hpsa_pci_driver);
edd16368
SC		 7293}
7294
7295static void __exit hpsa_cleanup(void)
7296{
7297 pci_unregister_driver(&hpsa_pci_driver);
edd16368
SC		 7298}
7299
e1f7de0c
MG		 7300static void __attribute__((unused)) verify_offsets(void)
7301{
dd0e19f3
ST		 7302#define VERIFY_OFFSET(member, offset) \
7303 BUILD_BUG_ON(offsetof(struct raid_map_data, member) != offset)
7304
7305 VERIFY_OFFSET(structure_size, 0);
7306 VERIFY_OFFSET(volume_blk_size, 4);
7307 VERIFY_OFFSET(volume_blk_cnt, 8);
7308 VERIFY_OFFSET(phys_blk_shift, 16);
7309 VERIFY_OFFSET(parity_rotation_shift, 17);
7310 VERIFY_OFFSET(strip_size, 18);
7311 VERIFY_OFFSET(disk_starting_blk, 20);
7312 VERIFY_OFFSET(disk_blk_cnt, 28);
7313 VERIFY_OFFSET(data_disks_per_row, 36);
7314 VERIFY_OFFSET(metadata_disks_per_row, 38);
7315 VERIFY_OFFSET(row_cnt, 40);
7316 VERIFY_OFFSET(layout_map_count, 42);
7317 VERIFY_OFFSET(flags, 44);
7318 VERIFY_OFFSET(dekindex, 46);
7319 /* VERIFY_OFFSET(reserved, 48 */
7320 VERIFY_OFFSET(data, 64);
7321
7322#undef VERIFY_OFFSET
7323
b66cc250
MM		 7324#define VERIFY_OFFSET(member, offset) \
7325 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, member) != offset)
7326
7327 VERIFY_OFFSET(IU_type, 0);
7328 VERIFY_OFFSET(direction, 1);
7329 VERIFY_OFFSET(reply_queue, 2);
7330 /* VERIFY_OFFSET(reserved1, 3); */
7331 VERIFY_OFFSET(scsi_nexus, 4);
7332 VERIFY_OFFSET(Tag, 8);
7333 VERIFY_OFFSET(cdb, 16);
7334 VERIFY_OFFSET(cciss_lun, 32);
7335 VERIFY_OFFSET(data_len, 40);
7336 VERIFY_OFFSET(cmd_priority_task_attr, 44);
7337 VERIFY_OFFSET(sg_count, 45);
7338 /* VERIFY_OFFSET(reserved3 */
7339 VERIFY_OFFSET(err_ptr, 48);
7340 VERIFY_OFFSET(err_len, 56);
7341 /* VERIFY_OFFSET(reserved4 */
7342 VERIFY_OFFSET(sg, 64);
7343
7344#undef VERIFY_OFFSET
7345
e1f7de0c
MG		 7346#define VERIFY_OFFSET(member, offset) \
7347 BUILD_BUG_ON(offsetof(struct io_accel1_cmd, member) != offset)
7348
7349 VERIFY_OFFSET(dev_handle, 0x00);
7350 VERIFY_OFFSET(reserved1, 0x02);
7351 VERIFY_OFFSET(function, 0x03);
7352 VERIFY_OFFSET(reserved2, 0x04);
7353 VERIFY_OFFSET(err_info, 0x0C);
7354 VERIFY_OFFSET(reserved3, 0x10);
7355 VERIFY_OFFSET(err_info_len, 0x12);
7356 VERIFY_OFFSET(reserved4, 0x13);
7357 VERIFY_OFFSET(sgl_offset, 0x14);
7358 VERIFY_OFFSET(reserved5, 0x15);
7359 VERIFY_OFFSET(transfer_len, 0x1C);
7360 VERIFY_OFFSET(reserved6, 0x20);
7361 VERIFY_OFFSET(io_flags, 0x24);
7362 VERIFY_OFFSET(reserved7, 0x26);
7363 VERIFY_OFFSET(LUN, 0x34);
7364 VERIFY_OFFSET(control, 0x3C);
7365 VERIFY_OFFSET(CDB, 0x40);
7366 VERIFY_OFFSET(reserved8, 0x50);
7367 VERIFY_OFFSET(host_context_flags, 0x60);
7368 VERIFY_OFFSET(timeout_sec, 0x62);
7369 VERIFY_OFFSET(ReplyQueue, 0x64);
7370 VERIFY_OFFSET(reserved9, 0x65);
50a0decf 7371 VERIFY_OFFSET(tag, 0x68);
e1f7de0c
MG		 7372 VERIFY_OFFSET(host_addr, 0x70);
7373 VERIFY_OFFSET(CISS_LUN, 0x78);
7374 VERIFY_OFFSET(SG, 0x78 + 8);
7375#undef VERIFY_OFFSET
7376}
7377
edd16368
SC		 7378module_init(hpsa_init);
7379module_exit(hpsa_cleanup);
Linux kernel - Deliverables
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