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hpsa: Rearrange start_io to avoid one unlock/lock sequence in main io path
[deliverable/linux.git] / drivers / scsi / hpsa.c
CommitLineData
edd16368
SC		 1/*
2 * Disk Array driver for HP Smart Array SAS controllers
51c35139 3 * Copyright 2000, 2014 Hewlett-Packard Development Company, L.P.
edd16368
SC		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
12 * NON INFRINGEMENT. See the GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 *
18 * Questions/Comments/Bugfixes to iss_storagedev@hp.com
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/interrupt.h>
24#include <linux/types.h>
25#include <linux/pci.h>
e5a44df8 26#include <linux/pci-aspm.h>
edd16368
SC		 27#include <linux/kernel.h>
28#include <linux/slab.h>
29#include <linux/delay.h>
30#include <linux/fs.h>
31#include <linux/timer.h>
edd16368
SC		 32#include <linux/init.h>
33#include <linux/spinlock.h>
edd16368
SC		 34#include <linux/compat.h>
35#include <linux/blktrace_api.h>
36#include <linux/uaccess.h>
37#include <linux/io.h>
38#include <linux/dma-mapping.h>
39#include <linux/completion.h>
40#include <linux/moduleparam.h>
41#include <scsi/scsi.h>
42#include <scsi/scsi_cmnd.h>
43#include <scsi/scsi_device.h>
44#include <scsi/scsi_host.h>
667e23d4 45#include <scsi/scsi_tcq.h>
edd16368
SC		 46#include <linux/cciss_ioctl.h>
47#include <linux/string.h>
48#include <linux/bitmap.h>
60063497 49#include <linux/atomic.h>
a0c12413 50#include <linux/jiffies.h>
094963da 51#include <linux/percpu.h>
283b4a9b 52#include <asm/div64.h>
edd16368
SC		 53#include "hpsa_cmd.h"
54#include "hpsa.h"
55
56/* HPSA_DRIVER_VERSION must be 3 byte values (0-255) separated by '.' */
9a993302 57#define HPSA_DRIVER_VERSION "3.4.4-1"
edd16368 58#define DRIVER_NAME "HP HPSA Driver (v " HPSA_DRIVER_VERSION ")"
f79cfec6 59#define HPSA "hpsa"
edd16368
SC		 60
61/* How long to wait (in milliseconds) for board to go into simple mode */
62#define MAX_CONFIG_WAIT 30000
63#define MAX_IOCTL_CONFIG_WAIT 1000
64
65/*define how many times we will try a command because of bus resets */
66#define MAX_CMD_RETRIES 3
67
68/* Embedded module documentation macros - see modules.h */
69MODULE_AUTHOR("Hewlett-Packard Company");
70MODULE_DESCRIPTION("Driver for HP Smart Array Controller version " \
71 HPSA_DRIVER_VERSION);
72MODULE_SUPPORTED_DEVICE("HP Smart Array Controllers");
73MODULE_VERSION(HPSA_DRIVER_VERSION);
74MODULE_LICENSE("GPL");
75
76static int hpsa_allow_any;
77module_param(hpsa_allow_any, int, S_IRUGO|S_IWUSR);
78MODULE_PARM_DESC(hpsa_allow_any,
79 "Allow hpsa driver to access unknown HP Smart Array hardware");
02ec19c8
SC		 80static int hpsa_simple_mode;
81module_param(hpsa_simple_mode, int, S_IRUGO|S_IWUSR);
82MODULE_PARM_DESC(hpsa_simple_mode,
83 "Use 'simple mode' rather than 'performant mode'");
edd16368
SC		 84
85/* define the PCI info for the cards we can control */
86static const struct pci_device_id hpsa_pci_device_id[] = {
edd16368
SC		 87 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3241},
88 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3243},
89 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3245},
90 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3247},
91 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3249},
163dbcd8
MM		 92 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324A},
93 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324B},
f8b01eb9 94 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3233},
9143a961 95 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3350},
96 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3351},
97 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3352},
98 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3353},
99 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3354},
100 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3355},
101 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3356},
fe0c9610
MM		 102 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1921},
103 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1922},
104 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1923},
105 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1924},
106 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1925},
107 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1926},
108 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1928},
97b9f53d
MM		 109 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1929},
110 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BD},
111 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BE},
112 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BF},
113 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C0},
114 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C1},
115 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C2},
116 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C3},
117 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C4},
118 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C5},
3b7a45e5 119 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C6},
97b9f53d
MM		 120 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C7},
121 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C8},
122 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C9},
3b7a45e5
JH		 123 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CA},
124 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CB},
125 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CC},
126 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CD},
127 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CE},
8e616a5e
SC		 128 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0076},
129 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0087},
130 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x007D},
131 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0088},
132 {PCI_VENDOR_ID_HP, 0x333f, 0x103c, 0x333f},
7c03b870 133 {PCI_VENDOR_ID_HP, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
6798cc0a 134 PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0},
edd16368
SC		 135 {0,}
136};
137
138MODULE_DEVICE_TABLE(pci, hpsa_pci_device_id);
139
140/* board_id = Subsystem Device ID & Vendor ID
141 * product = Marketing Name for the board
142 * access = Address of the struct of function pointers
143 */
144static struct board_type products[] = {
edd16368
SC		 145 {0x3241103C, "Smart Array P212", &SA5_access},
146 {0x3243103C, "Smart Array P410", &SA5_access},
147 {0x3245103C, "Smart Array P410i", &SA5_access},
148 {0x3247103C, "Smart Array P411", &SA5_access},
149 {0x3249103C, "Smart Array P812", &SA5_access},
163dbcd8
MM		 150 {0x324A103C, "Smart Array P712m", &SA5_access},
151 {0x324B103C, "Smart Array P711m", &SA5_access},
fe0c9610
MM		 152 {0x3350103C, "Smart Array P222", &SA5_access},
153 {0x3351103C, "Smart Array P420", &SA5_access},
154 {0x3352103C, "Smart Array P421", &SA5_access},
155 {0x3353103C, "Smart Array P822", &SA5_access},
156 {0x3354103C, "Smart Array P420i", &SA5_access},
157 {0x3355103C, "Smart Array P220i", &SA5_access},
158 {0x3356103C, "Smart Array P721m", &SA5_access},
1fd6c8e3
MM		 159 {0x1921103C, "Smart Array P830i", &SA5_access},
160 {0x1922103C, "Smart Array P430", &SA5_access},
161 {0x1923103C, "Smart Array P431", &SA5_access},
162 {0x1924103C, "Smart Array P830", &SA5_access},
163 {0x1926103C, "Smart Array P731m", &SA5_access},
164 {0x1928103C, "Smart Array P230i", &SA5_access},
165 {0x1929103C, "Smart Array P530", &SA5_access},
97b9f53d
MM		 166 {0x21BD103C, "Smart Array", &SA5_access},
167 {0x21BE103C, "Smart Array", &SA5_access},
168 {0x21BF103C, "Smart Array", &SA5_access},
169 {0x21C0103C, "Smart Array", &SA5_access},
170 {0x21C1103C, "Smart Array", &SA5_access},
171 {0x21C2103C, "Smart Array", &SA5_access},
172 {0x21C3103C, "Smart Array", &SA5_access},
173 {0x21C4103C, "Smart Array", &SA5_access},
174 {0x21C5103C, "Smart Array", &SA5_access},
3b7a45e5 175 {0x21C6103C, "Smart Array", &SA5_access},
97b9f53d
MM		 176 {0x21C7103C, "Smart Array", &SA5_access},
177 {0x21C8103C, "Smart Array", &SA5_access},
178 {0x21C9103C, "Smart Array", &SA5_access},
3b7a45e5
JH		 179 {0x21CA103C, "Smart Array", &SA5_access},
180 {0x21CB103C, "Smart Array", &SA5_access},
181 {0x21CC103C, "Smart Array", &SA5_access},
182 {0x21CD103C, "Smart Array", &SA5_access},
183 {0x21CE103C, "Smart Array", &SA5_access},
8e616a5e
SC		 184 {0x00761590, "HP Storage P1224 Array Controller", &SA5_access},
185 {0x00871590, "HP Storage P1224e Array Controller", &SA5_access},
186 {0x007D1590, "HP Storage P1228 Array Controller", &SA5_access},
187 {0x00881590, "HP Storage P1228e Array Controller", &SA5_access},
188 {0x333f103c, "HP StorageWorks 1210m Array Controller", &SA5_access},
edd16368
SC		 189 {0xFFFF103C, "Unknown Smart Array", &SA5_access},
190};
191
192static int number_of_controllers;
193
10f66018
SC		 194static irqreturn_t do_hpsa_intr_intx(int irq, void *dev_id);
195static irqreturn_t do_hpsa_intr_msi(int irq, void *dev_id);
edd16368 196static int hpsa_ioctl(struct scsi_device *dev, int cmd, void *arg);
0b57075d
SC		 197static void lock_and_start_io(struct ctlr_info *h);
198static void start_io(struct ctlr_info *h, unsigned long *flags);
edd16368
SC		 199
200#ifdef CONFIG_COMPAT
201static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void *arg);
202#endif
203
204static void cmd_free(struct ctlr_info *h, struct CommandList *c);
205static void cmd_special_free(struct ctlr_info *h, struct CommandList *c);
206static struct CommandList *cmd_alloc(struct ctlr_info *h);
207static struct CommandList *cmd_special_alloc(struct ctlr_info *h);
a2dac136 208static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
b7bb24eb 209 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
edd16368 210 int cmd_type);
b7bb24eb 211#define VPD_PAGE (1 << 8)
edd16368 212
f281233d 213static int hpsa_scsi_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd);
a08a8471
SC		 214static void hpsa_scan_start(struct Scsi_Host *);
215static int hpsa_scan_finished(struct Scsi_Host *sh,
216 unsigned long elapsed_time);
667e23d4
SC		 217static int hpsa_change_queue_depth(struct scsi_device *sdev,
218 int qdepth, int reason);
edd16368
SC		 219
220static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd);
75167d2c 221static int hpsa_eh_abort_handler(struct scsi_cmnd *scsicmd);
edd16368
SC		 222static int hpsa_slave_alloc(struct scsi_device *sdev);
223static void hpsa_slave_destroy(struct scsi_device *sdev);
224
edd16368 225static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno);
edd16368
SC		 226static int check_for_unit_attention(struct ctlr_info *h,
227 struct CommandList *c);
228static void check_ioctl_unit_attention(struct ctlr_info *h,
229 struct CommandList *c);
303932fd
DB		 230/* performant mode helper functions */
231static void calc_bucket_map(int *bucket, int num_buckets,
e1f7de0c 232 int nsgs, int min_blocks, int *bucket_map);
6f039790 233static void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h);
254f796b 234static inline u32 next_command(struct ctlr_info *h, u8 q);
6f039790
GKH		 235static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
236 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
237 u64 *cfg_offset);
238static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
239 unsigned long *memory_bar);
240static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id);
241static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
242 int wait_for_ready);
75167d2c 243static inline void finish_cmd(struct CommandList *c);
283b4a9b 244static void hpsa_wait_for_mode_change_ack(struct ctlr_info *h);
fe5389c8
SC		 245#define BOARD_NOT_READY 0
246#define BOARD_READY 1
23100dd9 247static void hpsa_drain_accel_commands(struct ctlr_info *h);
76438d08 248static void hpsa_flush_cache(struct ctlr_info *h);
c349775e
ST		 249static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
250 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
251 u8 *scsi3addr);
edd16368 252
edd16368
SC		 253static inline struct ctlr_info *sdev_to_hba(struct scsi_device *sdev)
254{
255 unsigned long *priv = shost_priv(sdev->host);
256 return (struct ctlr_info *) *priv;
257}
258
a23513e8
SC		 259static inline struct ctlr_info *shost_to_hba(struct Scsi_Host *sh)
260{
261 unsigned long *priv = shost_priv(sh);
262 return (struct ctlr_info *) *priv;
263}
264
edd16368
SC		 265static int check_for_unit_attention(struct ctlr_info *h,
266 struct CommandList *c)
267{
268 if (c->err_info->SenseInfo[2] != UNIT_ATTENTION)
269 return 0;
270
271 switch (c->err_info->SenseInfo[12]) {
272 case STATE_CHANGED:
f79cfec6 273 dev_warn(&h->pdev->dev, HPSA "%d: a state change "
edd16368
SC		 274 "detected, command retried\n", h->ctlr);
275 break;
276 case LUN_FAILED:
f79cfec6 277 dev_warn(&h->pdev->dev, HPSA "%d: LUN failure "
edd16368
SC		 278 "detected, action required\n", h->ctlr);
279 break;
280 case REPORT_LUNS_CHANGED:
f79cfec6 281 dev_warn(&h->pdev->dev, HPSA "%d: report LUN data "
31468401 282 "changed, action required\n", h->ctlr);
edd16368 283 /*
4f4eb9f1
ST		 284 * Note: this REPORT_LUNS_CHANGED condition only occurs on the external
285 * target (array) devices.
edd16368
SC		 286 */
287 break;
288 case POWER_OR_RESET:
f79cfec6 289 dev_warn(&h->pdev->dev, HPSA "%d: a power on "
edd16368
SC		 290 "or device reset detected\n", h->ctlr);
291 break;
292 case UNIT_ATTENTION_CLEARED:
f79cfec6 293 dev_warn(&h->pdev->dev, HPSA "%d: unit attention "
edd16368
SC		 294 "cleared by another initiator\n", h->ctlr);
295 break;
296 default:
f79cfec6 297 dev_warn(&h->pdev->dev, HPSA "%d: unknown "
edd16368
SC		 298 "unit attention detected\n", h->ctlr);
299 break;
300 }
301 return 1;
302}
303
852af20a
MB		 304static int check_for_busy(struct ctlr_info *h, struct CommandList *c)
305{
306 if (c->err_info->CommandStatus != CMD_TARGET_STATUS ||
307 (c->err_info->ScsiStatus != SAM_STAT_BUSY &&
308 c->err_info->ScsiStatus != SAM_STAT_TASK_SET_FULL))
309 return 0;
310 dev_warn(&h->pdev->dev, HPSA "device busy");
311 return 1;
312}
313
da0697bd
ST		 314static ssize_t host_store_hp_ssd_smart_path_status(struct device *dev,
315 struct device_attribute *attr,
316 const char *buf, size_t count)
317{
318 int status, len;
319 struct ctlr_info *h;
320 struct Scsi_Host *shost = class_to_shost(dev);
321 char tmpbuf[10];
322
323 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
324 return -EACCES;
325 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
326 strncpy(tmpbuf, buf, len);
327 tmpbuf[len] = '\0';
328 if (sscanf(tmpbuf, "%d", &status) != 1)
329 return -EINVAL;
330 h = shost_to_hba(shost);
331 h->acciopath_status = !!status;
332 dev_warn(&h->pdev->dev,
333 "hpsa: HP SSD Smart Path %s via sysfs update.\n",
334 h->acciopath_status ? "enabled" : "disabled");
335 return count;
336}
337
2ba8bfc8
SC		 338static ssize_t host_store_raid_offload_debug(struct device *dev,
339 struct device_attribute *attr,
340 const char *buf, size_t count)
341{
342 int debug_level, len;
343 struct ctlr_info *h;
344 struct Scsi_Host *shost = class_to_shost(dev);
345 char tmpbuf[10];
346
347 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
348 return -EACCES;
349 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
350 strncpy(tmpbuf, buf, len);
351 tmpbuf[len] = '\0';
352 if (sscanf(tmpbuf, "%d", &debug_level) != 1)
353 return -EINVAL;
354 if (debug_level < 0)
355 debug_level = 0;
356 h = shost_to_hba(shost);
357 h->raid_offload_debug = debug_level;
358 dev_warn(&h->pdev->dev, "hpsa: Set raid_offload_debug level = %d\n",
359 h->raid_offload_debug);
360 return count;
361}
362
edd16368
SC		 363static ssize_t host_store_rescan(struct device *dev,
364 struct device_attribute *attr,
365 const char *buf, size_t count)
366{
367 struct ctlr_info *h;
368 struct Scsi_Host *shost = class_to_shost(dev);
a23513e8 369 h = shost_to_hba(shost);
31468401 370 hpsa_scan_start(h->scsi_host);
edd16368
SC		 371 return count;
372}
373
d28ce020
SC		 374static ssize_t host_show_firmware_revision(struct device *dev,
375 struct device_attribute *attr, char *buf)
376{
377 struct ctlr_info *h;
378 struct Scsi_Host *shost = class_to_shost(dev);
379 unsigned char *fwrev;
380
381 h = shost_to_hba(shost);
382 if (!h->hba_inquiry_data)
383 return 0;
384 fwrev = &h->hba_inquiry_data[32];
385 return snprintf(buf, 20, "%c%c%c%c\n",
386 fwrev[0], fwrev[1], fwrev[2], fwrev[3]);
387}
388
94a13649
SC		 389static ssize_t host_show_commands_outstanding(struct device *dev,
390 struct device_attribute *attr, char *buf)
391{
392 struct Scsi_Host *shost = class_to_shost(dev);
393 struct ctlr_info *h = shost_to_hba(shost);
394
395 return snprintf(buf, 20, "%d\n", h->commands_outstanding);
396}
397
745a7a25
SC		 398static ssize_t host_show_transport_mode(struct device *dev,
399 struct device_attribute *attr, char *buf)
400{
401 struct ctlr_info *h;
402 struct Scsi_Host *shost = class_to_shost(dev);
403
404 h = shost_to_hba(shost);
405 return snprintf(buf, 20, "%s\n",
960a30e7 406 h->transMethod & CFGTBL_Trans_Performant ?
745a7a25
SC		 407 "performant" : "simple");
408}
409
da0697bd
ST		 410static ssize_t host_show_hp_ssd_smart_path_status(struct device *dev,
411 struct device_attribute *attr, char *buf)
412{
413 struct ctlr_info *h;
414 struct Scsi_Host *shost = class_to_shost(dev);
415
416 h = shost_to_hba(shost);
417 return snprintf(buf, 30, "HP SSD Smart Path %s\n",
418 (h->acciopath_status == 1) ? "enabled" : "disabled");
419}
420
46380786 421/* List of controllers which cannot be hard reset on kexec with reset_devices */
941b1cda
SC		 422static u32 unresettable_controller[] = {
423 0x324a103C, /* Smart Array P712m */
424 0x324b103C, /* SmartArray P711m */
425 0x3223103C, /* Smart Array P800 */
426 0x3234103C, /* Smart Array P400 */
427 0x3235103C, /* Smart Array P400i */
428 0x3211103C, /* Smart Array E200i */
429 0x3212103C, /* Smart Array E200 */
430 0x3213103C, /* Smart Array E200i */
431 0x3214103C, /* Smart Array E200i */
432 0x3215103C, /* Smart Array E200i */
433 0x3237103C, /* Smart Array E500 */
434 0x323D103C, /* Smart Array P700m */
7af0abbc 435 0x40800E11, /* Smart Array 5i */
941b1cda
SC		 436 0x409C0E11, /* Smart Array 6400 */
437 0x409D0E11, /* Smart Array 6400 EM */
5a4f934e
TH		 438 0x40700E11, /* Smart Array 5300 */
439 0x40820E11, /* Smart Array 532 */
440 0x40830E11, /* Smart Array 5312 */
441 0x409A0E11, /* Smart Array 641 */
442 0x409B0E11, /* Smart Array 642 */
443 0x40910E11, /* Smart Array 6i */
941b1cda
SC		 444};
445
46380786
SC		 446/* List of controllers which cannot even be soft reset */
447static u32 soft_unresettable_controller[] = {
7af0abbc 448 0x40800E11, /* Smart Array 5i */
5a4f934e
TH		 449 0x40700E11, /* Smart Array 5300 */
450 0x40820E11, /* Smart Array 532 */
451 0x40830E11, /* Smart Array 5312 */
452 0x409A0E11, /* Smart Array 641 */
453 0x409B0E11, /* Smart Array 642 */
454 0x40910E11, /* Smart Array 6i */
46380786
SC		 455 /* Exclude 640x boards. These are two pci devices in one slot
456 * which share a battery backed cache module. One controls the
457 * cache, the other accesses the cache through the one that controls
458 * it. If we reset the one controlling the cache, the other will
459 * likely not be happy. Just forbid resetting this conjoined mess.
460 * The 640x isn't really supported by hpsa anyway.
461 */
462 0x409C0E11, /* Smart Array 6400 */
463 0x409D0E11, /* Smart Array 6400 EM */
464};
465
466static int ctlr_is_hard_resettable(u32 board_id)
941b1cda
SC		 467{
468 int i;
469
470 for (i = 0; i < ARRAY_SIZE(unresettable_controller); i++)
46380786
SC		 471 if (unresettable_controller[i] == board_id)
472 return 0;
473 return 1;
474}
475
476static int ctlr_is_soft_resettable(u32 board_id)
477{
478 int i;
479
480 for (i = 0; i < ARRAY_SIZE(soft_unresettable_controller); i++)
481 if (soft_unresettable_controller[i] == board_id)
941b1cda
SC		 482 return 0;
483 return 1;
484}
485
46380786
SC		 486static int ctlr_is_resettable(u32 board_id)
487{
488 return ctlr_is_hard_resettable(board_id) ||
489 ctlr_is_soft_resettable(board_id);
490}
491
941b1cda
SC		 492static ssize_t host_show_resettable(struct device *dev,
493 struct device_attribute *attr, char *buf)
494{
495 struct ctlr_info *h;
496 struct Scsi_Host *shost = class_to_shost(dev);
497
498 h = shost_to_hba(shost);
46380786 499 return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h->board_id));
941b1cda
SC		 500}
501
edd16368
SC		 502static inline int is_logical_dev_addr_mode(unsigned char scsi3addr[])
503{
504 return (scsi3addr[3] & 0xC0) == 0x40;
505}
506
507static const char *raid_label[] = { "0", "4", "1(1+0)", "5", "5+1", "ADG",
d82357ea 508 "1(ADM)", "UNKNOWN"
edd16368 509};
6b80b18f
ST		 510#define HPSA_RAID_0 0
511#define HPSA_RAID_4 1
512#define HPSA_RAID_1 2 /* also used for RAID 10 */
513#define HPSA_RAID_5 3 /* also used for RAID 50 */
514#define HPSA_RAID_51 4
515#define HPSA_RAID_6 5 /* also used for RAID 60 */
516#define HPSA_RAID_ADM 6 /* also used for RAID 1+0 ADM */
edd16368
SC		 517#define RAID_UNKNOWN (ARRAY_SIZE(raid_label) - 1)
518
519static ssize_t raid_level_show(struct device *dev,
520 struct device_attribute *attr, char *buf)
521{
522 ssize_t l = 0;
82a72c0a 523 unsigned char rlevel;
edd16368
SC		 524 struct ctlr_info *h;
525 struct scsi_device *sdev;
526 struct hpsa_scsi_dev_t *hdev;
527 unsigned long flags;
528
529 sdev = to_scsi_device(dev);
530 h = sdev_to_hba(sdev);
531 spin_lock_irqsave(&h->lock, flags);
532 hdev = sdev->hostdata;
533 if (!hdev) {
534 spin_unlock_irqrestore(&h->lock, flags);
535 return -ENODEV;
536 }
537
538 /* Is this even a logical drive? */
539 if (!is_logical_dev_addr_mode(hdev->scsi3addr)) {
540 spin_unlock_irqrestore(&h->lock, flags);
541 l = snprintf(buf, PAGE_SIZE, "N/A\n");
542 return l;
543 }
544
545 rlevel = hdev->raid_level;
546 spin_unlock_irqrestore(&h->lock, flags);
82a72c0a 547 if (rlevel > RAID_UNKNOWN)
edd16368
SC		 548 rlevel = RAID_UNKNOWN;
549 l = snprintf(buf, PAGE_SIZE, "RAID %s\n", raid_label[rlevel]);
550 return l;
551}
552
553static ssize_t lunid_show(struct device *dev,
554 struct device_attribute *attr, char *buf)
555{
556 struct ctlr_info *h;
557 struct scsi_device *sdev;
558 struct hpsa_scsi_dev_t *hdev;
559 unsigned long flags;
560 unsigned char lunid[8];
561
562 sdev = to_scsi_device(dev);
563 h = sdev_to_hba(sdev);
564 spin_lock_irqsave(&h->lock, flags);
565 hdev = sdev->hostdata;
566 if (!hdev) {
567 spin_unlock_irqrestore(&h->lock, flags);
568 return -ENODEV;
569 }
570 memcpy(lunid, hdev->scsi3addr, sizeof(lunid));
571 spin_unlock_irqrestore(&h->lock, flags);
572 return snprintf(buf, 20, "0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
573 lunid[0], lunid[1], lunid[2], lunid[3],
574 lunid[4], lunid[5], lunid[6], lunid[7]);
575}
576
577static ssize_t unique_id_show(struct device *dev,
578 struct device_attribute *attr, char *buf)
579{
580 struct ctlr_info *h;
581 struct scsi_device *sdev;
582 struct hpsa_scsi_dev_t *hdev;
583 unsigned long flags;
584 unsigned char sn[16];
585
586 sdev = to_scsi_device(dev);
587 h = sdev_to_hba(sdev);
588 spin_lock_irqsave(&h->lock, flags);
589 hdev = sdev->hostdata;
590 if (!hdev) {
591 spin_unlock_irqrestore(&h->lock, flags);
592 return -ENODEV;
593 }
594 memcpy(sn, hdev->device_id, sizeof(sn));
595 spin_unlock_irqrestore(&h->lock, flags);
596 return snprintf(buf, 16 * 2 + 2,
597 "%02X%02X%02X%02X%02X%02X%02X%02X"
598 "%02X%02X%02X%02X%02X%02X%02X%02X\n",
599 sn[0], sn[1], sn[2], sn[3],
600 sn[4], sn[5], sn[6], sn[7],
601 sn[8], sn[9], sn[10], sn[11],
602 sn[12], sn[13], sn[14], sn[15]);
603}
604
c1988684
ST		 605static ssize_t host_show_hp_ssd_smart_path_enabled(struct device *dev,
606 struct device_attribute *attr, char *buf)
607{
608 struct ctlr_info *h;
609 struct scsi_device *sdev;
610 struct hpsa_scsi_dev_t *hdev;
611 unsigned long flags;
612 int offload_enabled;
613
614 sdev = to_scsi_device(dev);
615 h = sdev_to_hba(sdev);
616 spin_lock_irqsave(&h->lock, flags);
617 hdev = sdev->hostdata;
618 if (!hdev) {
619 spin_unlock_irqrestore(&h->lock, flags);
620 return -ENODEV;
621 }
622 offload_enabled = hdev->offload_enabled;
623 spin_unlock_irqrestore(&h->lock, flags);
624 return snprintf(buf, 20, "%d\n", offload_enabled);
625}
626
3f5eac3a
SC		 627static DEVICE_ATTR(raid_level, S_IRUGO, raid_level_show, NULL);
628static DEVICE_ATTR(lunid, S_IRUGO, lunid_show, NULL);
629static DEVICE_ATTR(unique_id, S_IRUGO, unique_id_show, NULL);
630static DEVICE_ATTR(rescan, S_IWUSR, NULL, host_store_rescan);
c1988684
ST		 631static DEVICE_ATTR(hp_ssd_smart_path_enabled, S_IRUGO,
632 host_show_hp_ssd_smart_path_enabled, NULL);
da0697bd
ST		 633static DEVICE_ATTR(hp_ssd_smart_path_status, S_IWUSR|S_IRUGO|S_IROTH,
634 host_show_hp_ssd_smart_path_status,
635 host_store_hp_ssd_smart_path_status);
2ba8bfc8
SC		 636static DEVICE_ATTR(raid_offload_debug, S_IWUSR, NULL,
637 host_store_raid_offload_debug);
3f5eac3a
SC		 638static DEVICE_ATTR(firmware_revision, S_IRUGO,
639 host_show_firmware_revision, NULL);
640static DEVICE_ATTR(commands_outstanding, S_IRUGO,
641 host_show_commands_outstanding, NULL);
642static DEVICE_ATTR(transport_mode, S_IRUGO,
643 host_show_transport_mode, NULL);
941b1cda
SC		 644static DEVICE_ATTR(resettable, S_IRUGO,
645 host_show_resettable, NULL);
3f5eac3a
SC		 646
647static struct device_attribute *hpsa_sdev_attrs[] = {
648 &dev_attr_raid_level,
649 &dev_attr_lunid,
650 &dev_attr_unique_id,
c1988684 651 &dev_attr_hp_ssd_smart_path_enabled,
3f5eac3a
SC		 652 NULL,
653};
654
655static struct device_attribute *hpsa_shost_attrs[] = {
656 &dev_attr_rescan,
657 &dev_attr_firmware_revision,
658 &dev_attr_commands_outstanding,
659 &dev_attr_transport_mode,
941b1cda 660 &dev_attr_resettable,
da0697bd 661 &dev_attr_hp_ssd_smart_path_status,
2ba8bfc8 662 &dev_attr_raid_offload_debug,
3f5eac3a
SC		 663 NULL,
664};
665
666static struct scsi_host_template hpsa_driver_template = {
667 .module = THIS_MODULE,
f79cfec6
SC		 668 .name = HPSA,
669 .proc_name = HPSA,
3f5eac3a
SC		 670 .queuecommand = hpsa_scsi_queue_command,
671 .scan_start = hpsa_scan_start,
672 .scan_finished = hpsa_scan_finished,
673 .change_queue_depth = hpsa_change_queue_depth,
674 .this_id = -1,
675 .use_clustering = ENABLE_CLUSTERING,
75167d2c 676 .eh_abort_handler = hpsa_eh_abort_handler,
3f5eac3a
SC		 677 .eh_device_reset_handler = hpsa_eh_device_reset_handler,
678 .ioctl = hpsa_ioctl,
679 .slave_alloc = hpsa_slave_alloc,
680 .slave_destroy = hpsa_slave_destroy,
681#ifdef CONFIG_COMPAT
682 .compat_ioctl = hpsa_compat_ioctl,
683#endif
684 .sdev_attrs = hpsa_sdev_attrs,
685 .shost_attrs = hpsa_shost_attrs,
c0d6a4d1 686 .max_sectors = 8192,
54b2b50c 687 .no_write_same = 1,
3f5eac3a
SC		 688};
689
690
691/* Enqueuing and dequeuing functions for cmdlists. */
692static inline void addQ(struct list_head *list, struct CommandList *c)
693{
694 list_add_tail(&c->list, list);
695}
696
254f796b 697static inline u32 next_command(struct ctlr_info *h, u8 q)
3f5eac3a
SC		 698{
699 u32 a;
072b0518 700 struct reply_queue_buffer *rq = &h->reply_queue[q];
e16a33ad 701 unsigned long flags;
3f5eac3a 702
e1f7de0c
MG		 703 if (h->transMethod & CFGTBL_Trans_io_accel1)
704 return h->access.command_completed(h, q);
705
3f5eac3a 706 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
254f796b 707 return h->access.command_completed(h, q);
3f5eac3a 708
254f796b
MG		 709 if ((rq->head[rq->current_entry] & 1) == rq->wraparound) {
710 a = rq->head[rq->current_entry];
711 rq->current_entry++;
e16a33ad 712 spin_lock_irqsave(&h->lock, flags);
3f5eac3a 713 h->commands_outstanding--;
e16a33ad 714 spin_unlock_irqrestore(&h->lock, flags);
3f5eac3a
SC		 715 } else {
716 a = FIFO_EMPTY;
717 }
718 /* Check for wraparound */
254f796b
MG		 719 if (rq->current_entry == h->max_commands) {
720 rq->current_entry = 0;
721 rq->wraparound ^= 1;
3f5eac3a
SC		 722 }
723 return a;
724}
725
c349775e
ST		 726/*
727 * There are some special bits in the bus address of the
728 * command that we have to set for the controller to know
729 * how to process the command:
730 *
731 * Normal performant mode:
732 * bit 0: 1 means performant mode, 0 means simple mode.
733 * bits 1-3 = block fetch table entry
734 * bits 4-6 = command type (== 0)
735 *
736 * ioaccel1 mode:
737 * bit 0 = "performant mode" bit.
738 * bits 1-3 = block fetch table entry
739 * bits 4-6 = command type (== 110)
740 * (command type is needed because ioaccel1 mode
741 * commands are submitted through the same register as normal
742 * mode commands, so this is how the controller knows whether
743 * the command is normal mode or ioaccel1 mode.)
744 *
745 * ioaccel2 mode:
746 * bit 0 = "performant mode" bit.
747 * bits 1-4 = block fetch table entry (note extra bit)
748 * bits 4-6 = not needed, because ioaccel2 mode has
749 * a separate special register for submitting commands.
750 */
751
3f5eac3a
SC		 752/* set_performant_mode: Modify the tag for cciss performant
753 * set bit 0 for pull model, bits 3-1 for block fetch
754 * register number
755 */
756static void set_performant_mode(struct ctlr_info *h, struct CommandList *c)
757{
254f796b 758 if (likely(h->transMethod & CFGTBL_Trans_Performant)) {
3f5eac3a 759 c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1);
eee0f03a 760 if (likely(h->msix_vector > 0))
254f796b 761 c->Header.ReplyQueue =
804a5cb5 762 raw_smp_processor_id() % h->nreply_queues;
254f796b 763 }
3f5eac3a
SC		 764}
765
c349775e
ST		 766static void set_ioaccel1_performant_mode(struct ctlr_info *h,
767 struct CommandList *c)
768{
769 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
770
771 /* Tell the controller to post the reply to the queue for this
772 * processor. This seems to give the best I/O throughput.
773 */
774 cp->ReplyQueue = smp_processor_id() % h->nreply_queues;
775 /* Set the bits in the address sent down to include:
776 * - performant mode bit (bit 0)
777 * - pull count (bits 1-3)
778 * - command type (bits 4-6)
779 */
780 c->busaddr |= 1 | (h->ioaccel1_blockFetchTable[c->Header.SGList] << 1) |
781 IOACCEL1_BUSADDR_CMDTYPE;
782}
783
784static void set_ioaccel2_performant_mode(struct ctlr_info *h,
785 struct CommandList *c)
786{
787 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
788
789 /* Tell the controller to post the reply to the queue for this
790 * processor. This seems to give the best I/O throughput.
791 */
792 cp->reply_queue = smp_processor_id() % h->nreply_queues;
793 /* Set the bits in the address sent down to include:
794 * - performant mode bit not used in ioaccel mode 2
795 * - pull count (bits 0-3)
796 * - command type isn't needed for ioaccel2
797 */
798 c->busaddr |= (h->ioaccel2_blockFetchTable[cp->sg_count]);
799}
800
e85c5974
SC		 801static int is_firmware_flash_cmd(u8 *cdb)
802{
803 return cdb[0] == BMIC_WRITE && cdb[6] == BMIC_FLASH_FIRMWARE;
804}
805
806/*
807 * During firmware flash, the heartbeat register may not update as frequently
808 * as it should. So we dial down lockup detection during firmware flash. and
809 * dial it back up when firmware flash completes.
810 */
811#define HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH (240 * HZ)
812#define HEARTBEAT_SAMPLE_INTERVAL (30 * HZ)
813static void dial_down_lockup_detection_during_fw_flash(struct ctlr_info *h,
814 struct CommandList *c)
815{
816 if (!is_firmware_flash_cmd(c->Request.CDB))
817 return;
818 atomic_inc(&h->firmware_flash_in_progress);
819 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH;
820}
821
822static void dial_up_lockup_detection_on_fw_flash_complete(struct ctlr_info *h,
823 struct CommandList *c)
824{
825 if (is_firmware_flash_cmd(c->Request.CDB) &&
826 atomic_dec_and_test(&h->firmware_flash_in_progress))
827 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
828}
829
3f5eac3a
SC		 830static void enqueue_cmd_and_start_io(struct ctlr_info *h,
831 struct CommandList *c)
832{
833 unsigned long flags;
834
c349775e
ST		 835 switch (c->cmd_type) {
836 case CMD_IOACCEL1:
837 set_ioaccel1_performant_mode(h, c);
838 break;
839 case CMD_IOACCEL2:
840 set_ioaccel2_performant_mode(h, c);
841 break;
842 default:
843 set_performant_mode(h, c);
844 }
e85c5974 845 dial_down_lockup_detection_during_fw_flash(h, c);
3f5eac3a
SC		 846 spin_lock_irqsave(&h->lock, flags);
847 addQ(&h->reqQ, c);
848 h->Qdepth++;
0b57075d 849 start_io(h, &flags);
3f5eac3a
SC		 850 spin_unlock_irqrestore(&h->lock, flags);
851}
852
853static inline void removeQ(struct CommandList *c)
854{
855 if (WARN_ON(list_empty(&c->list)))
856 return;
857 list_del_init(&c->list);
858}
859
860static inline int is_hba_lunid(unsigned char scsi3addr[])
861{
862 return memcmp(scsi3addr, RAID_CTLR_LUNID, 8) == 0;
863}
864
865static inline int is_scsi_rev_5(struct ctlr_info *h)
866{
867 if (!h->hba_inquiry_data)
868 return 0;
869 if ((h->hba_inquiry_data[2] & 0x07) == 5)
870 return 1;
871 return 0;
872}
873
edd16368
SC		 874static int hpsa_find_target_lun(struct ctlr_info *h,
875 unsigned char scsi3addr[], int bus, int *target, int *lun)
876{
877 /* finds an unused bus, target, lun for a new physical device
878 * assumes h->devlock is held
879 */
880 int i, found = 0;
cfe5badc 881 DECLARE_BITMAP(lun_taken, HPSA_MAX_DEVICES);
edd16368 882
263d9401 883 bitmap_zero(lun_taken, HPSA_MAX_DEVICES);
edd16368
SC		 884
885 for (i = 0; i < h->ndevices; i++) {
886 if (h->dev[i]->bus == bus && h->dev[i]->target != -1)
263d9401 887 __set_bit(h->dev[i]->target, lun_taken);
edd16368
SC		 888 }
889
263d9401
AM		 890 i = find_first_zero_bit(lun_taken, HPSA_MAX_DEVICES);
891 if (i < HPSA_MAX_DEVICES) {
892 /* *bus = 1; */
893 *target = i;
894 *lun = 0;
895 found = 1;
edd16368
SC		 896 }
897 return !found;
898}
899
900/* Add an entry into h->dev[] array. */
901static int hpsa_scsi_add_entry(struct ctlr_info *h, int hostno,
902 struct hpsa_scsi_dev_t *device,
903 struct hpsa_scsi_dev_t *added[], int *nadded)
904{
905 /* assumes h->devlock is held */
906 int n = h->ndevices;
907 int i;
908 unsigned char addr1[8], addr2[8];
909 struct hpsa_scsi_dev_t *sd;
910
cfe5badc 911 if (n >= HPSA_MAX_DEVICES) {
edd16368
SC		 912 dev_err(&h->pdev->dev, "too many devices, some will be "
913 "inaccessible.\n");
914 return -1;
915 }
916
917 /* physical devices do not have lun or target assigned until now. */
918 if (device->lun != -1)
919 /* Logical device, lun is already assigned. */
920 goto lun_assigned;
921
922 /* If this device a non-zero lun of a multi-lun device
923 * byte 4 of the 8-byte LUN addr will contain the logical
924 * unit no, zero otherise.
925 */
926 if (device->scsi3addr[4] == 0) {
927 /* This is not a non-zero lun of a multi-lun device */
928 if (hpsa_find_target_lun(h, device->scsi3addr,
929 device->bus, &device->target, &device->lun) != 0)
930 return -1;
931 goto lun_assigned;
932 }
933
934 /* This is a non-zero lun of a multi-lun device.
935 * Search through our list and find the device which
936 * has the same 8 byte LUN address, excepting byte 4.
937 * Assign the same bus and target for this new LUN.
938 * Use the logical unit number from the firmware.
939 */
940 memcpy(addr1, device->scsi3addr, 8);
941 addr1[4] = 0;
942 for (i = 0; i < n; i++) {
943 sd = h->dev[i];
944 memcpy(addr2, sd->scsi3addr, 8);
945 addr2[4] = 0;
946 /* differ only in byte 4? */
947 if (memcmp(addr1, addr2, 8) == 0) {
948 device->bus = sd->bus;
949 device->target = sd->target;
950 device->lun = device->scsi3addr[4];
951 break;
952 }
953 }
954 if (device->lun == -1) {
955 dev_warn(&h->pdev->dev, "physical device with no LUN=0,"
956 " suspect firmware bug or unsupported hardware "
957 "configuration.\n");
958 return -1;
959 }
960
961lun_assigned:
962
963 h->dev[n] = device;
964 h->ndevices++;
965 added[*nadded] = device;
966 (*nadded)++;
967
968 /* initially, (before registering with scsi layer) we don't
969 * know our hostno and we don't want to print anything first
970 * time anyway (the scsi layer's inquiries will show that info)
971 */
972 /* if (hostno != -1) */
973 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d added.\n",
974 scsi_device_type(device->devtype), hostno,
975 device->bus, device->target, device->lun);
976 return 0;
977}
978
bd9244f7
ST		 979/* Update an entry in h->dev[] array. */
980static void hpsa_scsi_update_entry(struct ctlr_info *h, int hostno,
981 int entry, struct hpsa_scsi_dev_t *new_entry)
982{
983 /* assumes h->devlock is held */
984 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
985
986 /* Raid level changed. */
987 h->dev[entry]->raid_level = new_entry->raid_level;
250fb125
SC		 988
989 /* Raid offload parameters changed. */
990 h->dev[entry]->offload_config = new_entry->offload_config;
991 h->dev[entry]->offload_enabled = new_entry->offload_enabled;
9fb0de2d
SC		 992 h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
993 h->dev[entry]->offload_to_mirror = new_entry->offload_to_mirror;
994 h->dev[entry]->raid_map = new_entry->raid_map;
250fb125 995
bd9244f7
ST		 996 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d updated.\n",
997 scsi_device_type(new_entry->devtype), hostno, new_entry->bus,
998 new_entry->target, new_entry->lun);
999}
1000
2a8ccf31
SC		 1001/* Replace an entry from h->dev[] array. */
1002static void hpsa_scsi_replace_entry(struct ctlr_info *h, int hostno,
1003 int entry, struct hpsa_scsi_dev_t *new_entry,
1004 struct hpsa_scsi_dev_t *added[], int *nadded,
1005 struct hpsa_scsi_dev_t *removed[], int *nremoved)
1006{
1007 /* assumes h->devlock is held */
cfe5badc 1008 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
2a8ccf31
SC		 1009 removed[*nremoved] = h->dev[entry];
1010 (*nremoved)++;
01350d05
SC		 1011
1012 /*
1013 * New physical devices won't have target/lun assigned yet
1014 * so we need to preserve the values in the slot we are replacing.
1015 */
1016 if (new_entry->target == -1) {
1017 new_entry->target = h->dev[entry]->target;
1018 new_entry->lun = h->dev[entry]->lun;
1019 }
1020
2a8ccf31
SC		 1021 h->dev[entry] = new_entry;
1022 added[*nadded] = new_entry;
1023 (*nadded)++;
1024 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d changed.\n",
1025 scsi_device_type(new_entry->devtype), hostno, new_entry->bus,
1026 new_entry->target, new_entry->lun);
1027}
1028
edd16368
SC		 1029/* Remove an entry from h->dev[] array. */
1030static void hpsa_scsi_remove_entry(struct ctlr_info *h, int hostno, int entry,
1031 struct hpsa_scsi_dev_t *removed[], int *nremoved)
1032{
1033 /* assumes h->devlock is held */
1034 int i;
1035 struct hpsa_scsi_dev_t *sd;
1036
cfe5badc 1037 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
edd16368
SC		 1038
1039 sd = h->dev[entry];
1040 removed[*nremoved] = h->dev[entry];
1041 (*nremoved)++;
1042
1043 for (i = entry; i < h->ndevices-1; i++)
1044 h->dev[i] = h->dev[i+1];
1045 h->ndevices--;
1046 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d removed.\n",
1047 scsi_device_type(sd->devtype), hostno, sd->bus, sd->target,
1048 sd->lun);
1049}
1050
1051#define SCSI3ADDR_EQ(a, b) ( \
1052 (a)[7] == (b)[7] && \
1053 (a)[6] == (b)[6] && \
1054 (a)[5] == (b)[5] && \
1055 (a)[4] == (b)[4] && \
1056 (a)[3] == (b)[3] && \
1057 (a)[2] == (b)[2] && \
1058 (a)[1] == (b)[1] && \
1059 (a)[0] == (b)[0])
1060
1061static void fixup_botched_add(struct ctlr_info *h,
1062 struct hpsa_scsi_dev_t *added)
1063{
1064 /* called when scsi_add_device fails in order to re-adjust
1065 * h->dev[] to match the mid layer's view.
1066 */
1067 unsigned long flags;
1068 int i, j;
1069
1070 spin_lock_irqsave(&h->lock, flags);
1071 for (i = 0; i < h->ndevices; i++) {
1072 if (h->dev[i] == added) {
1073 for (j = i; j < h->ndevices-1; j++)
1074 h->dev[j] = h->dev[j+1];
1075 h->ndevices--;
1076 break;
1077 }
1078 }
1079 spin_unlock_irqrestore(&h->lock, flags);
1080 kfree(added);
1081}
1082
1083static inline int device_is_the_same(struct hpsa_scsi_dev_t *dev1,
1084 struct hpsa_scsi_dev_t *dev2)
1085{
edd16368
SC		 1086 /* we compare everything except lun and target as these
1087 * are not yet assigned. Compare parts likely
1088 * to differ first
1089 */
1090 if (memcmp(dev1->scsi3addr, dev2->scsi3addr,
1091 sizeof(dev1->scsi3addr)) != 0)
1092 return 0;
1093 if (memcmp(dev1->device_id, dev2->device_id,
1094 sizeof(dev1->device_id)) != 0)
1095 return 0;
1096 if (memcmp(dev1->model, dev2->model, sizeof(dev1->model)) != 0)
1097 return 0;
1098 if (memcmp(dev1->vendor, dev2->vendor, sizeof(dev1->vendor)) != 0)
1099 return 0;
edd16368
SC		 1100 if (dev1->devtype != dev2->devtype)
1101 return 0;
edd16368
SC		 1102 if (dev1->bus != dev2->bus)
1103 return 0;
1104 return 1;
1105}
1106
bd9244f7
ST		 1107static inline int device_updated(struct hpsa_scsi_dev_t *dev1,
1108 struct hpsa_scsi_dev_t *dev2)
1109{
1110 /* Device attributes that can change, but don't mean
1111 * that the device is a different device, nor that the OS
1112 * needs to be told anything about the change.
1113 */
1114 if (dev1->raid_level != dev2->raid_level)
1115 return 1;
250fb125
SC		 1116 if (dev1->offload_config != dev2->offload_config)
1117 return 1;
1118 if (dev1->offload_enabled != dev2->offload_enabled)
1119 return 1;
bd9244f7
ST		 1120 return 0;
1121}
1122
edd16368
SC		 1123/* Find needle in haystack. If exact match found, return DEVICE_SAME,
1124 * and return needle location in *index. If scsi3addr matches, but not
1125 * vendor, model, serial num, etc. return DEVICE_CHANGED, and return needle
bd9244f7
ST		 1126 * location in *index.
1127 * In the case of a minor device attribute change, such as RAID level, just
1128 * return DEVICE_UPDATED, along with the updated device's location in index.
1129 * If needle not found, return DEVICE_NOT_FOUND.
edd16368
SC		 1130 */
1131static int hpsa_scsi_find_entry(struct hpsa_scsi_dev_t *needle,
1132 struct hpsa_scsi_dev_t *haystack[], int haystack_size,
1133 int *index)
1134{
1135 int i;
1136#define DEVICE_NOT_FOUND 0
1137#define DEVICE_CHANGED 1
1138#define DEVICE_SAME 2
bd9244f7 1139#define DEVICE_UPDATED 3
edd16368 1140 for (i = 0; i < haystack_size; i++) {
23231048
SC		 1141 if (haystack[i] == NULL) /* previously removed. */
1142 continue;
edd16368
SC		 1143 if (SCSI3ADDR_EQ(needle->scsi3addr, haystack[i]->scsi3addr)) {
1144 *index = i;
bd9244f7
ST		 1145 if (device_is_the_same(needle, haystack[i])) {
1146 if (device_updated(needle, haystack[i]))
1147 return DEVICE_UPDATED;
edd16368 1148 return DEVICE_SAME;
bd9244f7 1149 } else {
9846590e
SC		 1150 /* Keep offline devices offline */
1151 if (needle->volume_offline)
1152 return DEVICE_NOT_FOUND;
edd16368 1153 return DEVICE_CHANGED;
bd9244f7 1154 }
edd16368
SC		 1155 }
1156 }
1157 *index = -1;
1158 return DEVICE_NOT_FOUND;
1159}
1160
9846590e
SC		 1161static void hpsa_monitor_offline_device(struct ctlr_info *h,
1162 unsigned char scsi3addr[])
1163{
1164 struct offline_device_entry *device;
1165 unsigned long flags;
1166
1167 /* Check to see if device is already on the list */
1168 spin_lock_irqsave(&h->offline_device_lock, flags);
1169 list_for_each_entry(device, &h->offline_device_list, offline_list) {
1170 if (memcmp(device->scsi3addr, scsi3addr,
1171 sizeof(device->scsi3addr)) == 0) {
1172 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1173 return;
1174 }
1175 }
1176 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1177
1178 /* Device is not on the list, add it. */
1179 device = kmalloc(sizeof(*device), GFP_KERNEL);
1180 if (!device) {
1181 dev_warn(&h->pdev->dev, "out of memory in %s\n", __func__);
1182 return;
1183 }
1184 memcpy(device->scsi3addr, scsi3addr, sizeof(device->scsi3addr));
1185 spin_lock_irqsave(&h->offline_device_lock, flags);
1186 list_add_tail(&device->offline_list, &h->offline_device_list);
1187 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1188}
1189
1190/* Print a message explaining various offline volume states */
1191static void hpsa_show_volume_status(struct ctlr_info *h,
1192 struct hpsa_scsi_dev_t *sd)
1193{
1194 if (sd->volume_offline == HPSA_VPD_LV_STATUS_UNSUPPORTED)
1195 dev_info(&h->pdev->dev,
1196 "C%d:B%d:T%d:L%d Volume status is not available through vital product data pages.\n",
1197 h->scsi_host->host_no,
1198 sd->bus, sd->target, sd->lun);
1199 switch (sd->volume_offline) {
1200 case HPSA_LV_OK:
1201 break;
1202 case HPSA_LV_UNDERGOING_ERASE:
1203 dev_info(&h->pdev->dev,
1204 "C%d:B%d:T%d:L%d Volume is undergoing background erase process.\n",
1205 h->scsi_host->host_no,
1206 sd->bus, sd->target, sd->lun);
1207 break;
1208 case HPSA_LV_UNDERGOING_RPI:
1209 dev_info(&h->pdev->dev,
1210 "C%d:B%d:T%d:L%d Volume is undergoing rapid parity initialization process.\n",
1211 h->scsi_host->host_no,
1212 sd->bus, sd->target, sd->lun);
1213 break;
1214 case HPSA_LV_PENDING_RPI:
1215 dev_info(&h->pdev->dev,
1216 "C%d:B%d:T%d:L%d Volume is queued for rapid parity initialization process.\n",
1217 h->scsi_host->host_no,
1218 sd->bus, sd->target, sd->lun);
1219 break;
1220 case HPSA_LV_ENCRYPTED_NO_KEY:
1221 dev_info(&h->pdev->dev,
1222 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because key is not present.\n",
1223 h->scsi_host->host_no,
1224 sd->bus, sd->target, sd->lun);
1225 break;
1226 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
1227 dev_info(&h->pdev->dev,
1228 "C%d:B%d:T%d:L%d Volume is not encrypted and cannot be accessed because controller is in encryption-only mode.\n",
1229 h->scsi_host->host_no,
1230 sd->bus, sd->target, sd->lun);
1231 break;
1232 case HPSA_LV_UNDERGOING_ENCRYPTION:
1233 dev_info(&h->pdev->dev,
1234 "C%d:B%d:T%d:L%d Volume is undergoing encryption process.\n",
1235 h->scsi_host->host_no,
1236 sd->bus, sd->target, sd->lun);
1237 break;
1238 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
1239 dev_info(&h->pdev->dev,
1240 "C%d:B%d:T%d:L%d Volume is undergoing encryption re-keying process.\n",
1241 h->scsi_host->host_no,
1242 sd->bus, sd->target, sd->lun);
1243 break;
1244 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
1245 dev_info(&h->pdev->dev,
1246 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because controller does not have encryption enabled.\n",
1247 h->scsi_host->host_no,
1248 sd->bus, sd->target, sd->lun);
1249 break;
1250 case HPSA_LV_PENDING_ENCRYPTION:
1251 dev_info(&h->pdev->dev,
1252 "C%d:B%d:T%d:L%d Volume is pending migration to encrypted state, but process has not started.\n",
1253 h->scsi_host->host_no,
1254 sd->bus, sd->target, sd->lun);
1255 break;
1256 case HPSA_LV_PENDING_ENCRYPTION_REKEYING:
1257 dev_info(&h->pdev->dev,
1258 "C%d:B%d:T%d:L%d Volume is encrypted and is pending encryption rekeying.\n",
1259 h->scsi_host->host_no,
1260 sd->bus, sd->target, sd->lun);
1261 break;
1262 }
1263}
1264
4967bd3e 1265static void adjust_hpsa_scsi_table(struct ctlr_info *h, int hostno,
edd16368
SC		 1266 struct hpsa_scsi_dev_t *sd[], int nsds)
1267{
1268 /* sd contains scsi3 addresses and devtypes, and inquiry
1269 * data. This function takes what's in sd to be the current
1270 * reality and updates h->dev[] to reflect that reality.
1271 */
1272 int i, entry, device_change, changes = 0;
1273 struct hpsa_scsi_dev_t *csd;
1274 unsigned long flags;
1275 struct hpsa_scsi_dev_t **added, **removed;
1276 int nadded, nremoved;
1277 struct Scsi_Host *sh = NULL;
1278
cfe5badc
ST		 1279 added = kzalloc(sizeof(*added) * HPSA_MAX_DEVICES, GFP_KERNEL);
1280 removed = kzalloc(sizeof(*removed) * HPSA_MAX_DEVICES, GFP_KERNEL);
edd16368
SC		 1281
1282 if (!added || !removed) {
1283 dev_warn(&h->pdev->dev, "out of memory in "
1284 "adjust_hpsa_scsi_table\n");
1285 goto free_and_out;
1286 }
1287
1288 spin_lock_irqsave(&h->devlock, flags);
1289
1290 /* find any devices in h->dev[] that are not in
1291 * sd[] and remove them from h->dev[], and for any
1292 * devices which have changed, remove the old device
1293 * info and add the new device info.
bd9244f7
ST		 1294 * If minor device attributes change, just update
1295 * the existing device structure.
edd16368
SC		 1296 */
1297 i = 0;
1298 nremoved = 0;
1299 nadded = 0;
1300 while (i < h->ndevices) {
1301 csd = h->dev[i];
1302 device_change = hpsa_scsi_find_entry(csd, sd, nsds, &entry);
1303 if (device_change == DEVICE_NOT_FOUND) {
1304 changes++;
1305 hpsa_scsi_remove_entry(h, hostno, i,
1306 removed, &nremoved);
1307 continue; /* remove ^^^, hence i not incremented */
1308 } else if (device_change == DEVICE_CHANGED) {
1309 changes++;
2a8ccf31
SC		 1310 hpsa_scsi_replace_entry(h, hostno, i, sd[entry],
1311 added, &nadded, removed, &nremoved);
c7f172dc
SC		 1312 /* Set it to NULL to prevent it from being freed
1313 * at the bottom of hpsa_update_scsi_devices()
1314 */
1315 sd[entry] = NULL;
bd9244f7
ST		 1316 } else if (device_change == DEVICE_UPDATED) {
1317 hpsa_scsi_update_entry(h, hostno, i, sd[entry]);
edd16368
SC		 1318 }
1319 i++;
1320 }
1321
1322 /* Now, make sure every device listed in sd[] is also
1323 * listed in h->dev[], adding them if they aren't found
1324 */
1325
1326 for (i = 0; i < nsds; i++) {
1327 if (!sd[i]) /* if already added above. */
1328 continue;
9846590e
SC		 1329
1330 /* Don't add devices which are NOT READY, FORMAT IN PROGRESS
1331 * as the SCSI mid-layer does not handle such devices well.
1332 * It relentlessly loops sending TUR at 3Hz, then READ(10)
1333 * at 160Hz, and prevents the system from coming up.
1334 */
1335 if (sd[i]->volume_offline) {
1336 hpsa_show_volume_status(h, sd[i]);
1337 dev_info(&h->pdev->dev, "c%db%dt%dl%d: temporarily offline\n",
1338 h->scsi_host->host_no,
1339 sd[i]->bus, sd[i]->target, sd[i]->lun);
1340 continue;
1341 }
1342
edd16368
SC		 1343 device_change = hpsa_scsi_find_entry(sd[i], h->dev,
1344 h->ndevices, &entry);
1345 if (device_change == DEVICE_NOT_FOUND) {
1346 changes++;
1347 if (hpsa_scsi_add_entry(h, hostno, sd[i],
1348 added, &nadded) != 0)
1349 break;
1350 sd[i] = NULL; /* prevent from being freed later. */
1351 } else if (device_change == DEVICE_CHANGED) {
1352 /* should never happen... */
1353 changes++;
1354 dev_warn(&h->pdev->dev,
1355 "device unexpectedly changed.\n");
1356 /* but if it does happen, we just ignore that device */
1357 }
1358 }
1359 spin_unlock_irqrestore(&h->devlock, flags);
1360
9846590e
SC		 1361 /* Monitor devices which are in one of several NOT READY states to be
1362 * brought online later. This must be done without holding h->devlock,
1363 * so don't touch h->dev[]
1364 */
1365 for (i = 0; i < nsds; i++) {
1366 if (!sd[i]) /* if already added above. */
1367 continue;
1368 if (sd[i]->volume_offline)
1369 hpsa_monitor_offline_device(h, sd[i]->scsi3addr);
1370 }
1371
edd16368
SC		 1372 /* Don't notify scsi mid layer of any changes the first time through
1373 * (or if there are no changes) scsi_scan_host will do it later the
1374 * first time through.
1375 */
1376 if (hostno == -1 || !changes)
1377 goto free_and_out;
1378
1379 sh = h->scsi_host;
1380 /* Notify scsi mid layer of any removed devices */
1381 for (i = 0; i < nremoved; i++) {
1382 struct scsi_device *sdev =
1383 scsi_device_lookup(sh, removed[i]->bus,
1384 removed[i]->target, removed[i]->lun);
1385 if (sdev != NULL) {
1386 scsi_remove_device(sdev);
1387 scsi_device_put(sdev);
1388 } else {
1389 /* We don't expect to get here.
1390 * future cmds to this device will get selection
1391 * timeout as if the device was gone.
1392 */
1393 dev_warn(&h->pdev->dev, "didn't find c%db%dt%dl%d "
1394 " for removal.", hostno, removed[i]->bus,
1395 removed[i]->target, removed[i]->lun);
1396 }
1397 kfree(removed[i]);
1398 removed[i] = NULL;
1399 }
1400
1401 /* Notify scsi mid layer of any added devices */
1402 for (i = 0; i < nadded; i++) {
1403 if (scsi_add_device(sh, added[i]->bus,
1404 added[i]->target, added[i]->lun) == 0)
1405 continue;
1406 dev_warn(&h->pdev->dev, "scsi_add_device c%db%dt%dl%d failed, "
1407 "device not added.\n", hostno, added[i]->bus,
1408 added[i]->target, added[i]->lun);
1409 /* now we have to remove it from h->dev,
1410 * since it didn't get added to scsi mid layer
1411 */
1412 fixup_botched_add(h, added[i]);
1413 }
1414
1415free_and_out:
1416 kfree(added);
1417 kfree(removed);
edd16368
SC		 1418}
1419
1420/*
9e03aa2f 1421 * Lookup bus/target/lun and return corresponding struct hpsa_scsi_dev_t *
edd16368
SC		 1422 * Assume's h->devlock is held.
1423 */
1424static struct hpsa_scsi_dev_t *lookup_hpsa_scsi_dev(struct ctlr_info *h,
1425 int bus, int target, int lun)
1426{
1427 int i;
1428 struct hpsa_scsi_dev_t *sd;
1429
1430 for (i = 0; i < h->ndevices; i++) {
1431 sd = h->dev[i];
1432 if (sd->bus == bus && sd->target == target && sd->lun == lun)
1433 return sd;
1434 }
1435 return NULL;
1436}
1437
1438/* link sdev->hostdata to our per-device structure. */
1439static int hpsa_slave_alloc(struct scsi_device *sdev)
1440{
1441 struct hpsa_scsi_dev_t *sd;
1442 unsigned long flags;
1443 struct ctlr_info *h;
1444
1445 h = sdev_to_hba(sdev);
1446 spin_lock_irqsave(&h->devlock, flags);
1447 sd = lookup_hpsa_scsi_dev(h, sdev_channel(sdev),
1448 sdev_id(sdev), sdev->lun);
1449 if (sd != NULL)
1450 sdev->hostdata = sd;
1451 spin_unlock_irqrestore(&h->devlock, flags);
1452 return 0;
1453}
1454
1455static void hpsa_slave_destroy(struct scsi_device *sdev)
1456{
bcc44255 1457 /* nothing to do. */
edd16368
SC		 1458}
1459
33a2ffce
SC		 1460static void hpsa_free_sg_chain_blocks(struct ctlr_info *h)
1461{
1462 int i;
1463
1464 if (!h->cmd_sg_list)
1465 return;
1466 for (i = 0; i < h->nr_cmds; i++) {
1467 kfree(h->cmd_sg_list[i]);
1468 h->cmd_sg_list[i] = NULL;
1469 }
1470 kfree(h->cmd_sg_list);
1471 h->cmd_sg_list = NULL;
1472}
1473
1474static int hpsa_allocate_sg_chain_blocks(struct ctlr_info *h)
1475{
1476 int i;
1477
1478 if (h->chainsize <= 0)
1479 return 0;
1480
1481 h->cmd_sg_list = kzalloc(sizeof(*h->cmd_sg_list) * h->nr_cmds,
1482 GFP_KERNEL);
1483 if (!h->cmd_sg_list)
1484 return -ENOMEM;
1485 for (i = 0; i < h->nr_cmds; i++) {
1486 h->cmd_sg_list[i] = kmalloc(sizeof(*h->cmd_sg_list[i]) *
1487 h->chainsize, GFP_KERNEL);
1488 if (!h->cmd_sg_list[i])
1489 goto clean;
1490 }
1491 return 0;
1492
1493clean:
1494 hpsa_free_sg_chain_blocks(h);
1495 return -ENOMEM;
1496}
1497
e2bea6df 1498static int hpsa_map_sg_chain_block(struct ctlr_info *h,
33a2ffce
SC		 1499 struct CommandList *c)
1500{
1501 struct SGDescriptor *chain_sg, *chain_block;
1502 u64 temp64;
1503
1504 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
1505 chain_block = h->cmd_sg_list[c->cmdindex];
1506 chain_sg->Ext = HPSA_SG_CHAIN;
1507 chain_sg->Len = sizeof(*chain_sg) *
1508 (c->Header.SGTotal - h->max_cmd_sg_entries);
1509 temp64 = pci_map_single(h->pdev, chain_block, chain_sg->Len,
1510 PCI_DMA_TODEVICE);
e2bea6df
SC		 1511 if (dma_mapping_error(&h->pdev->dev, temp64)) {
1512 /* prevent subsequent unmapping */
1513 chain_sg->Addr.lower = 0;
1514 chain_sg->Addr.upper = 0;
1515 return -1;
1516 }
33a2ffce
SC		 1517 chain_sg->Addr.lower = (u32) (temp64 & 0x0FFFFFFFFULL);
1518 chain_sg->Addr.upper = (u32) ((temp64 >> 32) & 0x0FFFFFFFFULL);
e2bea6df 1519 return 0;
33a2ffce
SC		 1520}
1521
1522static void hpsa_unmap_sg_chain_block(struct ctlr_info *h,
1523 struct CommandList *c)
1524{
1525 struct SGDescriptor *chain_sg;
1526 union u64bit temp64;
1527
1528 if (c->Header.SGTotal <= h->max_cmd_sg_entries)
1529 return;
1530
1531 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
1532 temp64.val32.lower = chain_sg->Addr.lower;
1533 temp64.val32.upper = chain_sg->Addr.upper;
1534 pci_unmap_single(h->pdev, temp64.val, chain_sg->Len, PCI_DMA_TODEVICE);
1535}
1536
a09c1441
ST		 1537
1538/* Decode the various types of errors on ioaccel2 path.
1539 * Return 1 for any error that should generate a RAID path retry.
1540 * Return 0 for errors that don't require a RAID path retry.
1541 */
1542static int handle_ioaccel_mode2_error(struct ctlr_info *h,
c349775e
ST		 1543 struct CommandList *c,
1544 struct scsi_cmnd *cmd,
1545 struct io_accel2_cmd *c2)
1546{
1547 int data_len;
a09c1441 1548 int retry = 0;
c349775e
ST		 1549
1550 switch (c2->error_data.serv_response) {
1551 case IOACCEL2_SERV_RESPONSE_COMPLETE:
1552 switch (c2->error_data.status) {
1553 case IOACCEL2_STATUS_SR_TASK_COMP_GOOD:
1554 break;
1555 case IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND:
1556 dev_warn(&h->pdev->dev,
1557 "%s: task complete with check condition.\n",
1558 "HP SSD Smart Path");
1559 if (c2->error_data.data_present !=
1560 IOACCEL2_SENSE_DATA_PRESENT)
1561 break;
1562 /* copy the sense data */
1563 data_len = c2->error_data.sense_data_len;
1564 if (data_len > SCSI_SENSE_BUFFERSIZE)
1565 data_len = SCSI_SENSE_BUFFERSIZE;
1566 if (data_len > sizeof(c2->error_data.sense_data_buff))
1567 data_len =
1568 sizeof(c2->error_data.sense_data_buff);
1569 memcpy(cmd->sense_buffer,
1570 c2->error_data.sense_data_buff, data_len);
1571 cmd->result |= SAM_STAT_CHECK_CONDITION;
a09c1441 1572 retry = 1;
c349775e
ST		 1573 break;
1574 case IOACCEL2_STATUS_SR_TASK_COMP_BUSY:
1575 dev_warn(&h->pdev->dev,
1576 "%s: task complete with BUSY status.\n",
1577 "HP SSD Smart Path");
a09c1441 1578 retry = 1;
c349775e
ST		 1579 break;
1580 case IOACCEL2_STATUS_SR_TASK_COMP_RES_CON:
1581 dev_warn(&h->pdev->dev,
1582 "%s: task complete with reservation conflict.\n",
1583 "HP SSD Smart Path");
a09c1441 1584 retry = 1;
c349775e
ST		 1585 break;
1586 case IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL:
1587 /* Make scsi midlayer do unlimited retries */
1588 cmd->result = DID_IMM_RETRY << 16;
1589 break;
1590 case IOACCEL2_STATUS_SR_TASK_COMP_ABORTED:
1591 dev_warn(&h->pdev->dev,
1592 "%s: task complete with aborted status.\n",
1593 "HP SSD Smart Path");
a09c1441 1594 retry = 1;
c349775e
ST		 1595 break;
1596 default:
1597 dev_warn(&h->pdev->dev,
1598 "%s: task complete with unrecognized status: 0x%02x\n",
1599 "HP SSD Smart Path", c2->error_data.status);
a09c1441 1600 retry = 1;
c349775e
ST		 1601 break;
1602 }
1603 break;
1604 case IOACCEL2_SERV_RESPONSE_FAILURE:
1605 /* don't expect to get here. */
1606 dev_warn(&h->pdev->dev,
1607 "unexpected delivery or target failure, status = 0x%02x\n",
1608 c2->error_data.status);
a09c1441 1609 retry = 1;
c349775e
ST		 1610 break;
1611 case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE:
1612 break;
1613 case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS:
1614 break;
1615 case IOACCEL2_SERV_RESPONSE_TMF_REJECTED:
1616 dev_warn(&h->pdev->dev, "task management function rejected.\n");
a09c1441 1617 retry = 1;
c349775e
ST		 1618 break;
1619 case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN:
1620 dev_warn(&h->pdev->dev, "task management function invalid LUN\n");
1621 break;
1622 default:
1623 dev_warn(&h->pdev->dev,
1624 "%s: Unrecognized server response: 0x%02x\n",
a09c1441
ST		 1625 "HP SSD Smart Path",
1626 c2->error_data.serv_response);
1627 retry = 1;
c349775e
ST		 1628 break;
1629 }
a09c1441
ST		 1630
1631 return retry; /* retry on raid path? */
c349775e
ST		 1632}
1633
1634static void process_ioaccel2_completion(struct ctlr_info *h,
1635 struct CommandList *c, struct scsi_cmnd *cmd,
1636 struct hpsa_scsi_dev_t *dev)
1637{
1638 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
a09c1441 1639 int raid_retry = 0;
c349775e
ST		 1640
1641 /* check for good status */
1642 if (likely(c2->error_data.serv_response == 0 &&
1643 c2->error_data.status == 0)) {
1644 cmd_free(h, c);
1645 cmd->scsi_done(cmd);
1646 return;
1647 }
1648
1649 /* Any RAID offload error results in retry which will use
1650 * the normal I/O path so the controller can handle whatever's
1651 * wrong.
1652 */
1653 if (is_logical_dev_addr_mode(dev->scsi3addr) &&
1654 c2->error_data.serv_response ==
1655 IOACCEL2_SERV_RESPONSE_FAILURE) {
a09c1441
ST		 1656 if (c2->error_data.status ==
1657 IOACCEL2_STATUS_SR_IOACCEL_DISABLED)
1658 dev_warn(&h->pdev->dev,
1659 "%s: Path is unavailable, retrying on standard path.\n",
1660 "HP SSD Smart Path");
1661 else
c349775e 1662 dev_warn(&h->pdev->dev,
a09c1441 1663 "%s: Error 0x%02x, retrying on standard path.\n",
c349775e 1664 "HP SSD Smart Path", c2->error_data.status);
a09c1441 1665
c349775e 1666 dev->offload_enabled = 0;
e863d68e 1667 h->drv_req_rescan = 1; /* schedule controller for a rescan */
c349775e
ST		 1668 cmd->result = DID_SOFT_ERROR << 16;
1669 cmd_free(h, c);
1670 cmd->scsi_done(cmd);
1671 return;
1672 }
a09c1441
ST		 1673 raid_retry = handle_ioaccel_mode2_error(h, c, cmd, c2);
1674 /* If error found, disable Smart Path, schedule a rescan,
1675 * and force a retry on the standard path.
1676 */
1677 if (raid_retry) {
1678 dev_warn(&h->pdev->dev, "%s: Retrying on standard path.\n",
1679 "HP SSD Smart Path");
1680 dev->offload_enabled = 0; /* Disable Smart Path */
1681 h->drv_req_rescan = 1; /* schedule controller rescan */
1682 cmd->result = DID_SOFT_ERROR << 16;
1683 }
c349775e
ST		 1684 cmd_free(h, c);
1685 cmd->scsi_done(cmd);
1686}
1687
1fb011fb 1688static void complete_scsi_command(struct CommandList *cp)
edd16368
SC		 1689{
1690 struct scsi_cmnd *cmd;
1691 struct ctlr_info *h;
1692 struct ErrorInfo *ei;
283b4a9b 1693 struct hpsa_scsi_dev_t *dev;
edd16368
SC		 1694
1695 unsigned char sense_key;
1696 unsigned char asc; /* additional sense code */
1697 unsigned char ascq; /* additional sense code qualifier */
db111e18 1698 unsigned long sense_data_size;
edd16368
SC		 1699
1700 ei = cp->err_info;
1701 cmd = (struct scsi_cmnd *) cp->scsi_cmd;
1702 h = cp->h;
283b4a9b 1703 dev = cmd->device->hostdata;
edd16368
SC		 1704
1705 scsi_dma_unmap(cmd); /* undo the DMA mappings */
e1f7de0c
MG		 1706 if ((cp->cmd_type == CMD_SCSI) &&
1707 (cp->Header.SGTotal > h->max_cmd_sg_entries))
33a2ffce 1708 hpsa_unmap_sg_chain_block(h, cp);
edd16368
SC		 1709
1710 cmd->result = (DID_OK << 16); /* host byte */
1711 cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
c349775e
ST		 1712
1713 if (cp->cmd_type == CMD_IOACCEL2)
1714 return process_ioaccel2_completion(h, cp, cmd, dev);
1715
5512672f 1716 cmd->result |= ei->ScsiStatus;
edd16368
SC		 1717
1718 /* copy the sense data whether we need to or not. */
db111e18
SC		 1719 if (SCSI_SENSE_BUFFERSIZE < sizeof(ei->SenseInfo))
1720 sense_data_size = SCSI_SENSE_BUFFERSIZE;
1721 else
1722 sense_data_size = sizeof(ei->SenseInfo);
1723 if (ei->SenseLen < sense_data_size)
1724 sense_data_size = ei->SenseLen;
1725
1726 memcpy(cmd->sense_buffer, ei->SenseInfo, sense_data_size);
edd16368
SC		 1727 scsi_set_resid(cmd, ei->ResidualCnt);
1728
1729 if (ei->CommandStatus == 0) {
edd16368 1730 cmd_free(h, cp);
2cc5bfaf 1731 cmd->scsi_done(cmd);
edd16368
SC		 1732 return;
1733 }
1734
e1f7de0c
MG		 1735 /* For I/O accelerator commands, copy over some fields to the normal
1736 * CISS header used below for error handling.
1737 */
1738 if (cp->cmd_type == CMD_IOACCEL1) {
1739 struct io_accel1_cmd *c = &h->ioaccel_cmd_pool[cp->cmdindex];
1740 cp->Header.SGList = cp->Header.SGTotal = scsi_sg_count(cmd);
1741 cp->Request.CDBLen = c->io_flags & IOACCEL1_IOFLAGS_CDBLEN_MASK;
1742 cp->Header.Tag.lower = c->Tag.lower;
1743 cp->Header.Tag.upper = c->Tag.upper;
1744 memcpy(cp->Header.LUN.LunAddrBytes, c->CISS_LUN, 8);
1745 memcpy(cp->Request.CDB, c->CDB, cp->Request.CDBLen);
283b4a9b
SC		 1746
1747 /* Any RAID offload error results in retry which will use
1748 * the normal I/O path so the controller can handle whatever's
1749 * wrong.
1750 */
1751 if (is_logical_dev_addr_mode(dev->scsi3addr)) {
1752 if (ei->CommandStatus == CMD_IOACCEL_DISABLED)
1753 dev->offload_enabled = 0;
1754 cmd->result = DID_SOFT_ERROR << 16;
1755 cmd_free(h, cp);
1756 cmd->scsi_done(cmd);
1757 return;
1758 }
e1f7de0c
MG		 1759 }
1760
edd16368
SC		 1761 /* an error has occurred */
1762 switch (ei->CommandStatus) {
1763
1764 case CMD_TARGET_STATUS:
1765 if (ei->ScsiStatus) {
1766 /* Get sense key */
1767 sense_key = 0xf & ei->SenseInfo[2];
1768 /* Get additional sense code */
1769 asc = ei->SenseInfo[12];
1770 /* Get addition sense code qualifier */
1771 ascq = ei->SenseInfo[13];
1772 }
1773
1774 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION) {
3ce438df 1775 if (check_for_unit_attention(h, cp))
edd16368 1776 break;
edd16368
SC		 1777 if (sense_key == ILLEGAL_REQUEST) {
1778 /*
1779 * SCSI REPORT_LUNS is commonly unsupported on
1780 * Smart Array. Suppress noisy complaint.
1781 */
1782 if (cp->Request.CDB[0] == REPORT_LUNS)
1783 break;
1784
1785 /* If ASC/ASCQ indicate Logical Unit
1786 * Not Supported condition,
1787 */
1788 if ((asc == 0x25) && (ascq == 0x0)) {
1789 dev_warn(&h->pdev->dev, "cp %p "
1790 "has check condition\n", cp);
1791 break;
1792 }
1793 }
1794
1795 if (sense_key == NOT_READY) {
1796 /* If Sense is Not Ready, Logical Unit
1797 * Not ready, Manual Intervention
1798 * required
1799 */
1800 if ((asc == 0x04) && (ascq == 0x03)) {
edd16368
SC		 1801 dev_warn(&h->pdev->dev, "cp %p "
1802 "has check condition: unit "
1803 "not ready, manual "
1804 "intervention required\n", cp);
1805 break;
1806 }
1807 }
1d3b3609
MG		 1808 if (sense_key == ABORTED_COMMAND) {
1809 /* Aborted command is retryable */
1810 dev_warn(&h->pdev->dev, "cp %p "
1811 "has check condition: aborted command: "
1812 "ASC: 0x%x, ASCQ: 0x%x\n",
1813 cp, asc, ascq);
2e311fba 1814 cmd->result |= DID_SOFT_ERROR << 16;
1d3b3609
MG		 1815 break;
1816 }
edd16368 1817 /* Must be some other type of check condition */
21b8e4ef 1818 dev_dbg(&h->pdev->dev, "cp %p has check condition: "
edd16368
SC		 1819 "unknown type: "
1820 "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
1821 "Returning result: 0x%x, "
1822 "cmd=[%02x %02x %02x %02x %02x "
807be732 1823 "%02x %02x %02x %02x %02x %02x "
edd16368
SC		 1824 "%02x %02x %02x %02x %02x]\n",
1825 cp, sense_key, asc, ascq,
1826 cmd->result,
1827 cmd->cmnd[0], cmd->cmnd[1],
1828 cmd->cmnd[2], cmd->cmnd[3],
1829 cmd->cmnd[4], cmd->cmnd[5],
1830 cmd->cmnd[6], cmd->cmnd[7],
807be732
MM		 1831 cmd->cmnd[8], cmd->cmnd[9],
1832 cmd->cmnd[10], cmd->cmnd[11],
1833 cmd->cmnd[12], cmd->cmnd[13],
1834 cmd->cmnd[14], cmd->cmnd[15]);
edd16368
SC		 1835 break;
1836 }
1837
1838
1839 /* Problem was not a check condition
1840 * Pass it up to the upper layers...
1841 */
1842 if (ei->ScsiStatus) {
1843 dev_warn(&h->pdev->dev, "cp %p has status 0x%x "
1844 "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
1845 "Returning result: 0x%x\n",
1846 cp, ei->ScsiStatus,
1847 sense_key, asc, ascq,
1848 cmd->result);
1849 } else { /* scsi status is zero??? How??? */
1850 dev_warn(&h->pdev->dev, "cp %p SCSI status was 0. "
1851 "Returning no connection.\n", cp),
1852
1853 /* Ordinarily, this case should never happen,
1854 * but there is a bug in some released firmware
1855 * revisions that allows it to happen if, for
1856 * example, a 4100 backplane loses power and
1857 * the tape drive is in it. We assume that
1858 * it's a fatal error of some kind because we
1859 * can't show that it wasn't. We will make it
1860 * look like selection timeout since that is
1861 * the most common reason for this to occur,
1862 * and it's severe enough.
1863 */
1864
1865 cmd->result = DID_NO_CONNECT << 16;
1866 }
1867 break;
1868
1869 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
1870 break;
1871 case CMD_DATA_OVERRUN:
1872 dev_warn(&h->pdev->dev, "cp %p has"
1873 " completed with data overrun "
1874 "reported\n", cp);
1875 break;
1876 case CMD_INVALID: {
1877 /* print_bytes(cp, sizeof(*cp), 1, 0);
1878 print_cmd(cp); */
1879 /* We get CMD_INVALID if you address a non-existent device
1880 * instead of a selection timeout (no response). You will
1881 * see this if you yank out a drive, then try to access it.
1882 * This is kind of a shame because it means that any other
1883 * CMD_INVALID (e.g. driver bug) will get interpreted as a
1884 * missing target. */
1885 cmd->result = DID_NO_CONNECT << 16;
1886 }
1887 break;
1888 case CMD_PROTOCOL_ERR:
256d0eaa 1889 cmd->result = DID_ERROR << 16;
edd16368 1890 dev_warn(&h->pdev->dev, "cp %p has "
256d0eaa 1891 "protocol error\n", cp);
edd16368
SC		 1892 break;
1893 case CMD_HARDWARE_ERR:
1894 cmd->result = DID_ERROR << 16;
1895 dev_warn(&h->pdev->dev, "cp %p had hardware error\n", cp);
1896 break;
1897 case CMD_CONNECTION_LOST:
1898 cmd->result = DID_ERROR << 16;
1899 dev_warn(&h->pdev->dev, "cp %p had connection lost\n", cp);
1900 break;
1901 case CMD_ABORTED:
1902 cmd->result = DID_ABORT << 16;
1903 dev_warn(&h->pdev->dev, "cp %p was aborted with status 0x%x\n",
1904 cp, ei->ScsiStatus);
1905 break;
1906 case CMD_ABORT_FAILED:
1907 cmd->result = DID_ERROR << 16;
1908 dev_warn(&h->pdev->dev, "cp %p reports abort failed\n", cp);
1909 break;
1910 case CMD_UNSOLICITED_ABORT:
f6e76055
SC		 1911 cmd->result = DID_SOFT_ERROR << 16; /* retry the command */
1912 dev_warn(&h->pdev->dev, "cp %p aborted due to an unsolicited "
edd16368
SC		 1913 "abort\n", cp);
1914 break;
1915 case CMD_TIMEOUT:
1916 cmd->result = DID_TIME_OUT << 16;
1917 dev_warn(&h->pdev->dev, "cp %p timedout\n", cp);
1918 break;
1d5e2ed0
SC		 1919 case CMD_UNABORTABLE:
1920 cmd->result = DID_ERROR << 16;
1921 dev_warn(&h->pdev->dev, "Command unabortable\n");
1922 break;
283b4a9b
SC		 1923 case CMD_IOACCEL_DISABLED:
1924 /* This only handles the direct pass-through case since RAID
1925 * offload is handled above. Just attempt a retry.
1926 */
1927 cmd->result = DID_SOFT_ERROR << 16;
1928 dev_warn(&h->pdev->dev,
1929 "cp %p had HP SSD Smart Path error\n", cp);
1930 break;
edd16368
SC		 1931 default:
1932 cmd->result = DID_ERROR << 16;
1933 dev_warn(&h->pdev->dev, "cp %p returned unknown status %x\n",
1934 cp, ei->CommandStatus);
1935 }
edd16368 1936 cmd_free(h, cp);
2cc5bfaf 1937 cmd->scsi_done(cmd);
edd16368
SC		 1938}
1939
edd16368
SC		 1940static void hpsa_pci_unmap(struct pci_dev *pdev,
1941 struct CommandList *c, int sg_used, int data_direction)
1942{
1943 int i;
1944 union u64bit addr64;
1945
1946 for (i = 0; i < sg_used; i++) {
1947 addr64.val32.lower = c->SG[i].Addr.lower;
1948 addr64.val32.upper = c->SG[i].Addr.upper;
1949 pci_unmap_single(pdev, (dma_addr_t) addr64.val, c->SG[i].Len,
1950 data_direction);
1951 }
1952}
1953
a2dac136 1954static int hpsa_map_one(struct pci_dev *pdev,
edd16368
SC		 1955 struct CommandList *cp,
1956 unsigned char *buf,
1957 size_t buflen,
1958 int data_direction)
1959{
01a02ffc 1960 u64 addr64;
edd16368
SC		 1961
1962 if (buflen == 0 || data_direction == PCI_DMA_NONE) {
1963 cp->Header.SGList = 0;
1964 cp->Header.SGTotal = 0;
a2dac136 1965 return 0;
edd16368
SC		 1966 }
1967
01a02ffc 1968 addr64 = (u64) pci_map_single(pdev, buf, buflen, data_direction);
eceaae18 1969 if (dma_mapping_error(&pdev->dev, addr64)) {
a2dac136 1970 /* Prevent subsequent unmap of something never mapped */
eceaae18
SK		 1971 cp->Header.SGList = 0;
1972 cp->Header.SGTotal = 0;
a2dac136 1973 return -1;
eceaae18 1974 }
edd16368 1975 cp->SG[0].Addr.lower =
01a02ffc 1976 (u32) (addr64 & (u64) 0x00000000FFFFFFFF);
edd16368 1977 cp->SG[0].Addr.upper =
01a02ffc 1978 (u32) ((addr64 >> 32) & (u64) 0x00000000FFFFFFFF);
edd16368 1979 cp->SG[0].Len = buflen;
e1d9cbfa 1980 cp->SG[0].Ext = HPSA_SG_LAST; /* we are not chaining */
01a02ffc
SC		 1981 cp->Header.SGList = (u8) 1; /* no. SGs contig in this cmd */
1982 cp->Header.SGTotal = (u16) 1; /* total sgs in this cmd list */
a2dac136 1983 return 0;
edd16368
SC		 1984}
1985
1986static inline void hpsa_scsi_do_simple_cmd_core(struct ctlr_info *h,
1987 struct CommandList *c)
1988{
1989 DECLARE_COMPLETION_ONSTACK(wait);
1990
1991 c->waiting = &wait;
1992 enqueue_cmd_and_start_io(h, c);
1993 wait_for_completion(&wait);
1994}
1995
094963da
SC		 1996static u32 lockup_detected(struct ctlr_info *h)
1997{
1998 int cpu;
1999 u32 rc, *lockup_detected;
2000
2001 cpu = get_cpu();
2002 lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
2003 rc = *lockup_detected;
2004 put_cpu();
2005 return rc;
2006}
2007
a0c12413
SC		 2008static void hpsa_scsi_do_simple_cmd_core_if_no_lockup(struct ctlr_info *h,
2009 struct CommandList *c)
2010{
a0c12413 2011 /* If controller lockup detected, fake a hardware error. */
094963da 2012 if (unlikely(lockup_detected(h)))
a0c12413 2013 c->err_info->CommandStatus = CMD_HARDWARE_ERR;
094963da 2014 else
a0c12413 2015 hpsa_scsi_do_simple_cmd_core(h, c);
a0c12413
SC		 2016}
2017
9c2fc160 2018#define MAX_DRIVER_CMD_RETRIES 25
edd16368
SC		 2019static void hpsa_scsi_do_simple_cmd_with_retry(struct ctlr_info *h,
2020 struct CommandList *c, int data_direction)
2021{
9c2fc160 2022 int backoff_time = 10, retry_count = 0;
edd16368
SC		 2023
2024 do {
7630abd0 2025 memset(c->err_info, 0, sizeof(*c->err_info));
edd16368
SC		 2026 hpsa_scsi_do_simple_cmd_core(h, c);
2027 retry_count++;
9c2fc160
SC		 2028 if (retry_count > 3) {
2029 msleep(backoff_time);
2030 if (backoff_time < 1000)
2031 backoff_time *= 2;
2032 }
852af20a 2033 } while ((check_for_unit_attention(h, c) ||
9c2fc160
SC		 2034 check_for_busy(h, c)) &&
2035 retry_count <= MAX_DRIVER_CMD_RETRIES);
edd16368
SC		 2036 hpsa_pci_unmap(h->pdev, c, 1, data_direction);
2037}
2038
d1e8beac
SC		 2039static void hpsa_print_cmd(struct ctlr_info *h, char *txt,
2040 struct CommandList *c)
edd16368 2041{
d1e8beac
SC		 2042 const u8 *cdb = c->Request.CDB;
2043 const u8 *lun = c->Header.LUN.LunAddrBytes;
2044
2045 dev_warn(&h->pdev->dev, "%s: LUN:%02x%02x%02x%02x%02x%02x%02x%02x"
2046 " CDB:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\n",
2047 txt, lun[0], lun[1], lun[2], lun[3],
2048 lun[4], lun[5], lun[6], lun[7],
2049 cdb[0], cdb[1], cdb[2], cdb[3],
2050 cdb[4], cdb[5], cdb[6], cdb[7],
2051 cdb[8], cdb[9], cdb[10], cdb[11],
2052 cdb[12], cdb[13], cdb[14], cdb[15]);
2053}
2054
2055static void hpsa_scsi_interpret_error(struct ctlr_info *h,
2056 struct CommandList *cp)
2057{
2058 const struct ErrorInfo *ei = cp->err_info;
edd16368 2059 struct device *d = &cp->h->pdev->dev;
d1e8beac 2060 const u8 *sd = ei->SenseInfo;
edd16368 2061
edd16368
SC		 2062 switch (ei->CommandStatus) {
2063 case CMD_TARGET_STATUS:
d1e8beac
SC		 2064 hpsa_print_cmd(h, "SCSI status", cp);
2065 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION)
2066 dev_warn(d, "SCSI Status = 02, Sense key = %02x, ASC = %02x, ASCQ = %02x\n",
2067 sd[2] & 0x0f, sd[12], sd[13]);
2068 else
2069 dev_warn(d, "SCSI Status = %02x\n", ei->ScsiStatus);
edd16368
SC		 2070 if (ei->ScsiStatus == 0)
2071 dev_warn(d, "SCSI status is abnormally zero. "
2072 "(probably indicates selection timeout "
2073 "reported incorrectly due to a known "
2074 "firmware bug, circa July, 2001.)\n");
2075 break;
2076 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
edd16368
SC		 2077 break;
2078 case CMD_DATA_OVERRUN:
d1e8beac 2079 hpsa_print_cmd(h, "overrun condition", cp);
edd16368
SC		 2080 break;
2081 case CMD_INVALID: {
2082 /* controller unfortunately reports SCSI passthru's
2083 * to non-existent targets as invalid commands.
2084 */
d1e8beac
SC		 2085 hpsa_print_cmd(h, "invalid command", cp);
2086 dev_warn(d, "probably means device no longer present\n");
edd16368
SC		 2087 }
2088 break;
2089 case CMD_PROTOCOL_ERR:
d1e8beac 2090 hpsa_print_cmd(h, "protocol error", cp);
edd16368
SC		 2091 break;
2092 case CMD_HARDWARE_ERR:
d1e8beac 2093 hpsa_print_cmd(h, "hardware error", cp);
edd16368
SC		 2094 break;
2095 case CMD_CONNECTION_LOST:
d1e8beac 2096 hpsa_print_cmd(h, "connection lost", cp);
edd16368
SC		 2097 break;
2098 case CMD_ABORTED:
d1e8beac 2099 hpsa_print_cmd(h, "aborted", cp);
edd16368
SC		 2100 break;
2101 case CMD_ABORT_FAILED:
d1e8beac 2102 hpsa_print_cmd(h, "abort failed", cp);
edd16368
SC		 2103 break;
2104 case CMD_UNSOLICITED_ABORT:
d1e8beac 2105 hpsa_print_cmd(h, "unsolicited abort", cp);
edd16368
SC		 2106 break;
2107 case CMD_TIMEOUT:
d1e8beac 2108 hpsa_print_cmd(h, "timed out", cp);
edd16368 2109 break;
1d5e2ed0 2110 case CMD_UNABORTABLE:
d1e8beac 2111 hpsa_print_cmd(h, "unabortable", cp);
1d5e2ed0 2112 break;
edd16368 2113 default:
d1e8beac
SC		 2114 hpsa_print_cmd(h, "unknown status", cp);
2115 dev_warn(d, "Unknown command status %x\n",
edd16368
SC		 2116 ei->CommandStatus);
2117 }
2118}
2119
2120static int hpsa_scsi_do_inquiry(struct ctlr_info *h, unsigned char *scsi3addr,
b7bb24eb 2121 u16 page, unsigned char *buf,
edd16368
SC		 2122 unsigned char bufsize)
2123{
2124 int rc = IO_OK;
2125 struct CommandList *c;
2126 struct ErrorInfo *ei;
2127
2128 c = cmd_special_alloc(h);
2129
2130 if (c == NULL) { /* trouble... */
2131 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
ecd9aad4 2132 return -ENOMEM;
edd16368
SC		 2133 }
2134
a2dac136
SC		 2135 if (fill_cmd(c, HPSA_INQUIRY, h, buf, bufsize,
2136 page, scsi3addr, TYPE_CMD)) {
2137 rc = -1;
2138 goto out;
2139 }
edd16368
SC		 2140 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
2141 ei = c->err_info;
2142 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2143 hpsa_scsi_interpret_error(h, c);
edd16368
SC		 2144 rc = -1;
2145 }
a2dac136 2146out:
edd16368
SC		 2147 cmd_special_free(h, c);
2148 return rc;
2149}
2150
316b221a
SC		 2151static int hpsa_bmic_ctrl_mode_sense(struct ctlr_info *h,
2152 unsigned char *scsi3addr, unsigned char page,
2153 struct bmic_controller_parameters *buf, size_t bufsize)
2154{
2155 int rc = IO_OK;
2156 struct CommandList *c;
2157 struct ErrorInfo *ei;
2158
2159 c = cmd_special_alloc(h);
2160
2161 if (c == NULL) { /* trouble... */
2162 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
2163 return -ENOMEM;
2164 }
2165
2166 if (fill_cmd(c, BMIC_SENSE_CONTROLLER_PARAMETERS, h, buf, bufsize,
2167 page, scsi3addr, TYPE_CMD)) {
2168 rc = -1;
2169 goto out;
2170 }
2171 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
2172 ei = c->err_info;
2173 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
2174 hpsa_scsi_interpret_error(h, c);
2175 rc = -1;
2176 }
2177out:
2178 cmd_special_free(h, c);
2179 return rc;
2180 }
2181
bf711ac6
ST		 2182static int hpsa_send_reset(struct ctlr_info *h, unsigned char *scsi3addr,
2183 u8 reset_type)
edd16368
SC		 2184{
2185 int rc = IO_OK;
2186 struct CommandList *c;
2187 struct ErrorInfo *ei;
2188
2189 c = cmd_special_alloc(h);
2190
2191 if (c == NULL) { /* trouble... */
2192 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
e9ea04a6 2193 return -ENOMEM;
edd16368
SC		 2194 }
2195
a2dac136 2196 /* fill_cmd can't fail here, no data buffer to map. */
bf711ac6
ST		 2197 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
2198 scsi3addr, TYPE_MSG);
2199 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to LUN reset */
edd16368
SC		 2200 hpsa_scsi_do_simple_cmd_core(h, c);
2201 /* no unmap needed here because no data xfer. */
2202
2203 ei = c->err_info;
2204 if (ei->CommandStatus != 0) {
d1e8beac 2205 hpsa_scsi_interpret_error(h, c);
edd16368
SC		 2206 rc = -1;
2207 }
2208 cmd_special_free(h, c);
2209 return rc;
2210}
2211
2212static void hpsa_get_raid_level(struct ctlr_info *h,
2213 unsigned char *scsi3addr, unsigned char *raid_level)
2214{
2215 int rc;
2216 unsigned char *buf;
2217
2218 *raid_level = RAID_UNKNOWN;
2219 buf = kzalloc(64, GFP_KERNEL);
2220 if (!buf)
2221 return;
b7bb24eb 2222 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0xC1, buf, 64);
edd16368
SC		 2223 if (rc == 0)
2224 *raid_level = buf[8];
2225 if (*raid_level > RAID_UNKNOWN)
2226 *raid_level = RAID_UNKNOWN;
2227 kfree(buf);
2228 return;
2229}
2230
283b4a9b
SC		 2231#define HPSA_MAP_DEBUG
2232#ifdef HPSA_MAP_DEBUG
2233static void hpsa_debug_map_buff(struct ctlr_info *h, int rc,
2234 struct raid_map_data *map_buff)
2235{
2236 struct raid_map_disk_data *dd = &map_buff->data[0];
2237 int map, row, col;
2238 u16 map_cnt, row_cnt, disks_per_row;
2239
2240 if (rc != 0)
2241 return;
2242
2ba8bfc8
SC		 2243 /* Show details only if debugging has been activated. */
2244 if (h->raid_offload_debug < 2)
2245 return;
2246
283b4a9b
SC		 2247 dev_info(&h->pdev->dev, "structure_size = %u\n",
2248 le32_to_cpu(map_buff->structure_size));
2249 dev_info(&h->pdev->dev, "volume_blk_size = %u\n",
2250 le32_to_cpu(map_buff->volume_blk_size));
2251 dev_info(&h->pdev->dev, "volume_blk_cnt = 0x%llx\n",
2252 le64_to_cpu(map_buff->volume_blk_cnt));
2253 dev_info(&h->pdev->dev, "physicalBlockShift = %u\n",
2254 map_buff->phys_blk_shift);
2255 dev_info(&h->pdev->dev, "parity_rotation_shift = %u\n",
2256 map_buff->parity_rotation_shift);
2257 dev_info(&h->pdev->dev, "strip_size = %u\n",
2258 le16_to_cpu(map_buff->strip_size));
2259 dev_info(&h->pdev->dev, "disk_starting_blk = 0x%llx\n",
2260 le64_to_cpu(map_buff->disk_starting_blk));
2261 dev_info(&h->pdev->dev, "disk_blk_cnt = 0x%llx\n",
2262 le64_to_cpu(map_buff->disk_blk_cnt));
2263 dev_info(&h->pdev->dev, "data_disks_per_row = %u\n",
2264 le16_to_cpu(map_buff->data_disks_per_row));
2265 dev_info(&h->pdev->dev, "metadata_disks_per_row = %u\n",
2266 le16_to_cpu(map_buff->metadata_disks_per_row));
2267 dev_info(&h->pdev->dev, "row_cnt = %u\n",
2268 le16_to_cpu(map_buff->row_cnt));
2269 dev_info(&h->pdev->dev, "layout_map_count = %u\n",
2270 le16_to_cpu(map_buff->layout_map_count));
dd0e19f3
ST		 2271 dev_info(&h->pdev->dev, "flags = %u\n",
2272 le16_to_cpu(map_buff->flags));
2273 if (map_buff->flags & RAID_MAP_FLAG_ENCRYPT_ON)
2274 dev_info(&h->pdev->dev, "encrypytion = ON\n");
2275 else
2276 dev_info(&h->pdev->dev, "encrypytion = OFF\n");
2277 dev_info(&h->pdev->dev, "dekindex = %u\n",
2278 le16_to_cpu(map_buff->dekindex));
283b4a9b
SC		 2279
2280 map_cnt = le16_to_cpu(map_buff->layout_map_count);
2281 for (map = 0; map < map_cnt; map++) {
2282 dev_info(&h->pdev->dev, "Map%u:\n", map);
2283 row_cnt = le16_to_cpu(map_buff->row_cnt);
2284 for (row = 0; row < row_cnt; row++) {
2285 dev_info(&h->pdev->dev, " Row%u:\n", row);
2286 disks_per_row =
2287 le16_to_cpu(map_buff->data_disks_per_row);
2288 for (col = 0; col < disks_per_row; col++, dd++)
2289 dev_info(&h->pdev->dev,
2290 " D%02u: h=0x%04x xor=%u,%u\n",
2291 col, dd->ioaccel_handle,
2292 dd->xor_mult[0], dd->xor_mult[1]);
2293 disks_per_row =
2294 le16_to_cpu(map_buff->metadata_disks_per_row);
2295 for (col = 0; col < disks_per_row; col++, dd++)
2296 dev_info(&h->pdev->dev,
2297 " M%02u: h=0x%04x xor=%u,%u\n",
2298 col, dd->ioaccel_handle,
2299 dd->xor_mult[0], dd->xor_mult[1]);
2300 }
2301 }
2302}
2303#else
2304static void hpsa_debug_map_buff(__attribute__((unused)) struct ctlr_info *h,
2305 __attribute__((unused)) int rc,
2306 __attribute__((unused)) struct raid_map_data *map_buff)
2307{
2308}
2309#endif
2310
2311static int hpsa_get_raid_map(struct ctlr_info *h,
2312 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
2313{
2314 int rc = 0;
2315 struct CommandList *c;
2316 struct ErrorInfo *ei;
2317
2318 c = cmd_special_alloc(h);
2319 if (c == NULL) {
2320 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
2321 return -ENOMEM;
2322 }
2323 if (fill_cmd(c, HPSA_GET_RAID_MAP, h, &this_device->raid_map,
2324 sizeof(this_device->raid_map), 0,
2325 scsi3addr, TYPE_CMD)) {
2326 dev_warn(&h->pdev->dev, "Out of memory in hpsa_get_raid_map()\n");
2327 cmd_special_free(h, c);
2328 return -ENOMEM;
2329 }
2330 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
2331 ei = c->err_info;
2332 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2333 hpsa_scsi_interpret_error(h, c);
283b4a9b
SC		 2334 cmd_special_free(h, c);
2335 return -1;
2336 }
2337 cmd_special_free(h, c);
2338
2339 /* @todo in the future, dynamically allocate RAID map memory */
2340 if (le32_to_cpu(this_device->raid_map.structure_size) >
2341 sizeof(this_device->raid_map)) {
2342 dev_warn(&h->pdev->dev, "RAID map size is too large!\n");
2343 rc = -1;
2344 }
2345 hpsa_debug_map_buff(h, rc, &this_device->raid_map);
2346 return rc;
2347}
2348
1b70150a
SC		 2349static int hpsa_vpd_page_supported(struct ctlr_info *h,
2350 unsigned char scsi3addr[], u8 page)
2351{
2352 int rc;
2353 int i;
2354 int pages;
2355 unsigned char *buf, bufsize;
2356
2357 buf = kzalloc(256, GFP_KERNEL);
2358 if (!buf)
2359 return 0;
2360
2361 /* Get the size of the page list first */
2362 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
2363 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
2364 buf, HPSA_VPD_HEADER_SZ);
2365 if (rc != 0)
2366 goto exit_unsupported;
2367 pages = buf[3];
2368 if ((pages + HPSA_VPD_HEADER_SZ) <= 255)
2369 bufsize = pages + HPSA_VPD_HEADER_SZ;
2370 else
2371 bufsize = 255;
2372
2373 /* Get the whole VPD page list */
2374 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
2375 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
2376 buf, bufsize);
2377 if (rc != 0)
2378 goto exit_unsupported;
2379
2380 pages = buf[3];
2381 for (i = 1; i <= pages; i++)
2382 if (buf[3 + i] == page)
2383 goto exit_supported;
2384exit_unsupported:
2385 kfree(buf);
2386 return 0;
2387exit_supported:
2388 kfree(buf);
2389 return 1;
2390}
2391
283b4a9b
SC		 2392static void hpsa_get_ioaccel_status(struct ctlr_info *h,
2393 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
2394{
2395 int rc;
2396 unsigned char *buf;
2397 u8 ioaccel_status;
2398
2399 this_device->offload_config = 0;
2400 this_device->offload_enabled = 0;
2401
2402 buf = kzalloc(64, GFP_KERNEL);
2403 if (!buf)
2404 return;
1b70150a
SC		 2405 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_IOACCEL_STATUS))
2406 goto out;
283b4a9b 2407 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
b7bb24eb 2408 VPD_PAGE | HPSA_VPD_LV_IOACCEL_STATUS, buf, 64);
283b4a9b
SC		 2409 if (rc != 0)
2410 goto out;
2411
2412#define IOACCEL_STATUS_BYTE 4
2413#define OFFLOAD_CONFIGURED_BIT 0x01
2414#define OFFLOAD_ENABLED_BIT 0x02
2415 ioaccel_status = buf[IOACCEL_STATUS_BYTE];
2416 this_device->offload_config =
2417 !!(ioaccel_status & OFFLOAD_CONFIGURED_BIT);
2418 if (this_device->offload_config) {
2419 this_device->offload_enabled =
2420 !!(ioaccel_status & OFFLOAD_ENABLED_BIT);
2421 if (hpsa_get_raid_map(h, scsi3addr, this_device))
2422 this_device->offload_enabled = 0;
2423 }
2424out:
2425 kfree(buf);
2426 return;
2427}
2428
edd16368
SC		 2429/* Get the device id from inquiry page 0x83 */
2430static int hpsa_get_device_id(struct ctlr_info *h, unsigned char *scsi3addr,
2431 unsigned char *device_id, int buflen)
2432{
2433 int rc;
2434 unsigned char *buf;
2435
2436 if (buflen > 16)
2437 buflen = 16;
2438 buf = kzalloc(64, GFP_KERNEL);
2439 if (!buf)
2440 return -1;
b7bb24eb 2441 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0x83, buf, 64);
edd16368
SC		 2442 if (rc == 0)
2443 memcpy(device_id, &buf[8], buflen);
2444 kfree(buf);
2445 return rc != 0;
2446}
2447
2448static int hpsa_scsi_do_report_luns(struct ctlr_info *h, int logical,
2449 struct ReportLUNdata *buf, int bufsize,
2450 int extended_response)
2451{
2452 int rc = IO_OK;
2453 struct CommandList *c;
2454 unsigned char scsi3addr[8];
2455 struct ErrorInfo *ei;
2456
2457 c = cmd_special_alloc(h);
2458 if (c == NULL) { /* trouble... */
2459 dev_err(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
2460 return -1;
2461 }
e89c0ae7
SC		 2462 /* address the controller */
2463 memset(scsi3addr, 0, sizeof(scsi3addr));
a2dac136
SC		 2464 if (fill_cmd(c, logical ? HPSA_REPORT_LOG : HPSA_REPORT_PHYS, h,
2465 buf, bufsize, 0, scsi3addr, TYPE_CMD)) {
2466 rc = -1;
2467 goto out;
2468 }
edd16368
SC		 2469 if (extended_response)
2470 c->Request.CDB[1] = extended_response;
2471 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
2472 ei = c->err_info;
2473 if (ei->CommandStatus != 0 &&
2474 ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2475 hpsa_scsi_interpret_error(h, c);
edd16368 2476 rc = -1;
283b4a9b
SC		 2477 } else {
2478 if (buf->extended_response_flag != extended_response) {
2479 dev_err(&h->pdev->dev,
2480 "report luns requested format %u, got %u\n",
2481 extended_response,
2482 buf->extended_response_flag);
2483 rc = -1;
2484 }
edd16368 2485 }
a2dac136 2486out:
edd16368
SC		 2487 cmd_special_free(h, c);
2488 return rc;
2489}
2490
2491static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h,
2492 struct ReportLUNdata *buf,
2493 int bufsize, int extended_response)
2494{
2495 return hpsa_scsi_do_report_luns(h, 0, buf, bufsize, extended_response);
2496}
2497
2498static inline int hpsa_scsi_do_report_log_luns(struct ctlr_info *h,
2499 struct ReportLUNdata *buf, int bufsize)
2500{
2501 return hpsa_scsi_do_report_luns(h, 1, buf, bufsize, 0);
2502}
2503
2504static inline void hpsa_set_bus_target_lun(struct hpsa_scsi_dev_t *device,
2505 int bus, int target, int lun)
2506{
2507 device->bus = bus;
2508 device->target = target;
2509 device->lun = lun;
2510}
2511
9846590e
SC		 2512/* Use VPD inquiry to get details of volume status */
2513static int hpsa_get_volume_status(struct ctlr_info *h,
2514 unsigned char scsi3addr[])
2515{
2516 int rc;
2517 int status;
2518 int size;
2519 unsigned char *buf;
2520
2521 buf = kzalloc(64, GFP_KERNEL);
2522 if (!buf)
2523 return HPSA_VPD_LV_STATUS_UNSUPPORTED;
2524
2525 /* Does controller have VPD for logical volume status? */
2526 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_STATUS)) {
2527 dev_warn(&h->pdev->dev, "Logical volume status VPD page is unsupported.\n");
2528 goto exit_failed;
2529 }
2530
2531 /* Get the size of the VPD return buffer */
2532 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
2533 buf, HPSA_VPD_HEADER_SZ);
2534 if (rc != 0) {
2535 dev_warn(&h->pdev->dev, "Logical volume status VPD inquiry failed.\n");
2536 goto exit_failed;
2537 }
2538 size = buf[3];
2539
2540 /* Now get the whole VPD buffer */
2541 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
2542 buf, size + HPSA_VPD_HEADER_SZ);
2543 if (rc != 0) {
2544 dev_warn(&h->pdev->dev, "Logical volume status VPD inquiry failed.\n");
2545 goto exit_failed;
2546 }
2547 status = buf[4]; /* status byte */
2548
2549 kfree(buf);
2550 return status;
2551exit_failed:
2552 kfree(buf);
2553 return HPSA_VPD_LV_STATUS_UNSUPPORTED;
2554}
2555
2556/* Determine offline status of a volume.
2557 * Return either:
2558 * 0 (not offline)
2559 * -1 (offline for unknown reasons)
2560 * # (integer code indicating one of several NOT READY states
2561 * describing why a volume is to be kept offline)
2562 */
2563static unsigned char hpsa_volume_offline(struct ctlr_info *h,
2564 unsigned char scsi3addr[])
2565{
2566 struct CommandList *c;
2567 unsigned char *sense, sense_key, asc, ascq;
2568 int ldstat = 0;
2569 u16 cmd_status;
2570 u8 scsi_status;
2571#define ASC_LUN_NOT_READY 0x04
2572#define ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS 0x04
2573#define ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ 0x02
2574
2575 c = cmd_alloc(h);
2576 if (!c)
2577 return 0;
2578 (void) fill_cmd(c, TEST_UNIT_READY, h, NULL, 0, 0, scsi3addr, TYPE_CMD);
2579 hpsa_scsi_do_simple_cmd_core(h, c);
2580 sense = c->err_info->SenseInfo;
2581 sense_key = sense[2];
2582 asc = sense[12];
2583 ascq = sense[13];
2584 cmd_status = c->err_info->CommandStatus;
2585 scsi_status = c->err_info->ScsiStatus;
2586 cmd_free(h, c);
2587 /* Is the volume 'not ready'? */
2588 if (cmd_status != CMD_TARGET_STATUS ||
2589 scsi_status != SAM_STAT_CHECK_CONDITION ||
2590 sense_key != NOT_READY ||
2591 asc != ASC_LUN_NOT_READY) {
2592 return 0;
2593 }
2594
2595 /* Determine the reason for not ready state */
2596 ldstat = hpsa_get_volume_status(h, scsi3addr);
2597
2598 /* Keep volume offline in certain cases: */
2599 switch (ldstat) {
2600 case HPSA_LV_UNDERGOING_ERASE:
2601 case HPSA_LV_UNDERGOING_RPI:
2602 case HPSA_LV_PENDING_RPI:
2603 case HPSA_LV_ENCRYPTED_NO_KEY:
2604 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
2605 case HPSA_LV_UNDERGOING_ENCRYPTION:
2606 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
2607 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
2608 return ldstat;
2609 case HPSA_VPD_LV_STATUS_UNSUPPORTED:
2610 /* If VPD status page isn't available,
2611 * use ASC/ASCQ to determine state
2612 */
2613 if ((ascq == ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS) ||
2614 (ascq == ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ))
2615 return ldstat;
2616 break;
2617 default:
2618 break;
2619 }
2620 return 0;
2621}
2622
edd16368 2623static int hpsa_update_device_info(struct ctlr_info *h,
0b0e1d6c
SC		 2624 unsigned char scsi3addr[], struct hpsa_scsi_dev_t *this_device,
2625 unsigned char *is_OBDR_device)
edd16368 2626{
0b0e1d6c
SC		 2627
2628#define OBDR_SIG_OFFSET 43
2629#define OBDR_TAPE_SIG "$DR-10"
2630#define OBDR_SIG_LEN (sizeof(OBDR_TAPE_SIG) - 1)
2631#define OBDR_TAPE_INQ_SIZE (OBDR_SIG_OFFSET + OBDR_SIG_LEN)
2632
ea6d3bc3 2633 unsigned char *inq_buff;
0b0e1d6c 2634 unsigned char *obdr_sig;
edd16368 2635
ea6d3bc3 2636 inq_buff = kzalloc(OBDR_TAPE_INQ_SIZE, GFP_KERNEL);
edd16368
SC		 2637 if (!inq_buff)
2638 goto bail_out;
2639
edd16368
SC		 2640 /* Do an inquiry to the device to see what it is. */
2641 if (hpsa_scsi_do_inquiry(h, scsi3addr, 0, inq_buff,
2642 (unsigned char) OBDR_TAPE_INQ_SIZE) != 0) {
2643 /* Inquiry failed (msg printed already) */
2644 dev_err(&h->pdev->dev,
2645 "hpsa_update_device_info: inquiry failed\n");
2646 goto bail_out;
2647 }
2648
edd16368
SC		 2649 this_device->devtype = (inq_buff[0] & 0x1f);
2650 memcpy(this_device->scsi3addr, scsi3addr, 8);
2651 memcpy(this_device->vendor, &inq_buff[8],
2652 sizeof(this_device->vendor));
2653 memcpy(this_device->model, &inq_buff[16],
2654 sizeof(this_device->model));
edd16368
SC		 2655 memset(this_device->device_id, 0,
2656 sizeof(this_device->device_id));
2657 hpsa_get_device_id(h, scsi3addr, this_device->device_id,
2658 sizeof(this_device->device_id));
2659
2660 if (this_device->devtype == TYPE_DISK &&
283b4a9b 2661 is_logical_dev_addr_mode(scsi3addr)) {
edd16368 2662 hpsa_get_raid_level(h, scsi3addr, &this_device->raid_level);
283b4a9b
SC		 2663 if (h->fw_support & MISC_FW_RAID_OFFLOAD_BASIC)
2664 hpsa_get_ioaccel_status(h, scsi3addr, this_device);
9846590e
SC		 2665 this_device->volume_offline =
2666 hpsa_volume_offline(h, scsi3addr);
283b4a9b 2667 } else {
edd16368 2668 this_device->raid_level = RAID_UNKNOWN;
283b4a9b
SC		 2669 this_device->offload_config = 0;
2670 this_device->offload_enabled = 0;
9846590e 2671 this_device->volume_offline = 0;
283b4a9b 2672 }
edd16368 2673
0b0e1d6c
SC		 2674 if (is_OBDR_device) {
2675 /* See if this is a One-Button-Disaster-Recovery device
2676 * by looking for "$DR-10" at offset 43 in inquiry data.
2677 */
2678 obdr_sig = &inq_buff[OBDR_SIG_OFFSET];
2679 *is_OBDR_device = (this_device->devtype == TYPE_ROM &&
2680 strncmp(obdr_sig, OBDR_TAPE_SIG,
2681 OBDR_SIG_LEN) == 0);
2682 }
2683
edd16368
SC		 2684 kfree(inq_buff);
2685 return 0;
2686
2687bail_out:
2688 kfree(inq_buff);
2689 return 1;
2690}
2691
4f4eb9f1 2692static unsigned char *ext_target_model[] = {
edd16368
SC		 2693 "MSA2012",
2694 "MSA2024",
2695 "MSA2312",
2696 "MSA2324",
fda38518 2697 "P2000 G3 SAS",
e06c8e5c 2698 "MSA 2040 SAS",
edd16368
SC		 2699 NULL,
2700};
2701
4f4eb9f1 2702static int is_ext_target(struct ctlr_info *h, struct hpsa_scsi_dev_t *device)
edd16368
SC		 2703{
2704 int i;
2705
4f4eb9f1
ST		 2706 for (i = 0; ext_target_model[i]; i++)
2707 if (strncmp(device->model, ext_target_model[i],
2708 strlen(ext_target_model[i])) == 0)
edd16368
SC		 2709 return 1;
2710 return 0;
2711}
2712
2713/* Helper function to assign bus, target, lun mapping of devices.
4f4eb9f1 2714 * Puts non-external target logical volumes on bus 0, external target logical
edd16368
SC		 2715 * volumes on bus 1, physical devices on bus 2. and the hba on bus 3.
2716 * Logical drive target and lun are assigned at this time, but
2717 * physical device lun and target assignment are deferred (assigned
2718 * in hpsa_find_target_lun, called by hpsa_scsi_add_entry.)
2719 */
2720static void figure_bus_target_lun(struct ctlr_info *h,
1f310bde 2721 u8 *lunaddrbytes, struct hpsa_scsi_dev_t *device)
edd16368 2722{
1f310bde
SC		 2723 u32 lunid = le32_to_cpu(*((__le32 *) lunaddrbytes));
2724
2725 if (!is_logical_dev_addr_mode(lunaddrbytes)) {
2726 /* physical device, target and lun filled in later */
edd16368 2727 if (is_hba_lunid(lunaddrbytes))
1f310bde 2728 hpsa_set_bus_target_lun(device, 3, 0, lunid & 0x3fff);
edd16368 2729 else
1f310bde
SC		 2730 /* defer target, lun assignment for physical devices */
2731 hpsa_set_bus_target_lun(device, 2, -1, -1);
2732 return;
2733 }
2734 /* It's a logical device */
4f4eb9f1
ST		 2735 if (is_ext_target(h, device)) {
2736 /* external target way, put logicals on bus 1
1f310bde
SC		 2737 * and match target/lun numbers box
2738 * reports, other smart array, bus 0, target 0, match lunid
2739 */
2740 hpsa_set_bus_target_lun(device,
2741 1, (lunid >> 16) & 0x3fff, lunid & 0x00ff);
2742 return;
edd16368 2743 }
1f310bde 2744 hpsa_set_bus_target_lun(device, 0, 0, lunid & 0x3fff);
edd16368
SC		 2745}
2746
2747/*
2748 * If there is no lun 0 on a target, linux won't find any devices.
4f4eb9f1 2749 * For the external targets (arrays), we have to manually detect the enclosure
edd16368
SC		 2750 * which is at lun zero, as CCISS_REPORT_PHYSICAL_LUNS doesn't report
2751 * it for some reason. *tmpdevice is the target we're adding,
2752 * this_device is a pointer into the current element of currentsd[]
2753 * that we're building up in update_scsi_devices(), below.
2754 * lunzerobits is a bitmap that tracks which targets already have a
2755 * lun 0 assigned.
2756 * Returns 1 if an enclosure was added, 0 if not.
2757 */
4f4eb9f1 2758static int add_ext_target_dev(struct ctlr_info *h,
edd16368 2759 struct hpsa_scsi_dev_t *tmpdevice,
01a02ffc 2760 struct hpsa_scsi_dev_t *this_device, u8 *lunaddrbytes,
4f4eb9f1 2761 unsigned long lunzerobits[], int *n_ext_target_devs)
edd16368
SC		 2762{
2763 unsigned char scsi3addr[8];
2764
1f310bde 2765 if (test_bit(tmpdevice->target, lunzerobits))
edd16368
SC		 2766 return 0; /* There is already a lun 0 on this target. */
2767
2768 if (!is_logical_dev_addr_mode(lunaddrbytes))
2769 return 0; /* It's the logical targets that may lack lun 0. */
2770
4f4eb9f1
ST		 2771 if (!is_ext_target(h, tmpdevice))
2772 return 0; /* Only external target devices have this problem. */
edd16368 2773
1f310bde 2774 if (tmpdevice->lun == 0) /* if lun is 0, then we have a lun 0. */
edd16368
SC		 2775 return 0;
2776
c4f8a299 2777 memset(scsi3addr, 0, 8);
1f310bde 2778 scsi3addr[3] = tmpdevice->target;
edd16368
SC		 2779 if (is_hba_lunid(scsi3addr))
2780 return 0; /* Don't add the RAID controller here. */
2781
339b2b14
SC		 2782 if (is_scsi_rev_5(h))
2783 return 0; /* p1210m doesn't need to do this. */
2784
4f4eb9f1 2785 if (*n_ext_target_devs >= MAX_EXT_TARGETS) {
aca4a520
ST		 2786 dev_warn(&h->pdev->dev, "Maximum number of external "
2787 "target devices exceeded. Check your hardware "
edd16368
SC		 2788 "configuration.");
2789 return 0;
2790 }
2791
0b0e1d6c 2792 if (hpsa_update_device_info(h, scsi3addr, this_device, NULL))
edd16368 2793 return 0;
4f4eb9f1 2794 (*n_ext_target_devs)++;
1f310bde
SC		 2795 hpsa_set_bus_target_lun(this_device,
2796 tmpdevice->bus, tmpdevice->target, 0);
2797 set_bit(tmpdevice->target, lunzerobits);
edd16368
SC		 2798 return 1;
2799}
2800
54b6e9e9
ST		 2801/*
2802 * Get address of physical disk used for an ioaccel2 mode command:
2803 * 1. Extract ioaccel2 handle from the command.
2804 * 2. Find a matching ioaccel2 handle from list of physical disks.
2805 * 3. Return:
2806 * 1 and set scsi3addr to address of matching physical
2807 * 0 if no matching physical disk was found.
2808 */
2809static int hpsa_get_pdisk_of_ioaccel2(struct ctlr_info *h,
2810 struct CommandList *ioaccel2_cmd_to_abort, unsigned char *scsi3addr)
2811{
2812 struct ReportExtendedLUNdata *physicals = NULL;
2813 int responsesize = 24; /* size of physical extended response */
2814 int extended = 2; /* flag forces reporting 'other dev info'. */
2815 int reportsize = sizeof(*physicals) + HPSA_MAX_PHYS_LUN * responsesize;
2816 u32 nphysicals = 0; /* number of reported physical devs */
2817 int found = 0; /* found match (1) or not (0) */
2818 u32 find; /* handle we need to match */
2819 int i;
2820 struct scsi_cmnd *scmd; /* scsi command within request being aborted */
2821 struct hpsa_scsi_dev_t *d; /* device of request being aborted */
2822 struct io_accel2_cmd *c2a; /* ioaccel2 command to abort */
2823 u32 it_nexus; /* 4 byte device handle for the ioaccel2 cmd */
2824 u32 scsi_nexus; /* 4 byte device handle for the ioaccel2 cmd */
2825
2826 if (ioaccel2_cmd_to_abort->cmd_type != CMD_IOACCEL2)
2827 return 0; /* no match */
2828
2829 /* point to the ioaccel2 device handle */
2830 c2a = &h->ioaccel2_cmd_pool[ioaccel2_cmd_to_abort->cmdindex];
2831 if (c2a == NULL)
2832 return 0; /* no match */
2833
2834 scmd = (struct scsi_cmnd *) ioaccel2_cmd_to_abort->scsi_cmd;
2835 if (scmd == NULL)
2836 return 0; /* no match */
2837
2838 d = scmd->device->hostdata;
2839 if (d == NULL)
2840 return 0; /* no match */
2841
2842 it_nexus = cpu_to_le32((u32) d->ioaccel_handle);
2843 scsi_nexus = cpu_to_le32((u32) c2a->scsi_nexus);
2844 find = c2a->scsi_nexus;
2845
2ba8bfc8
SC		 2846 if (h->raid_offload_debug > 0)
2847 dev_info(&h->pdev->dev,
2848 "%s: scsi_nexus:0x%08x device id: 0x%02x%02x%02x%02x %02x%02x%02x%02x %02x%02x%02x%02x %02x%02x%02x%02x\n",
2849 __func__, scsi_nexus,
2850 d->device_id[0], d->device_id[1], d->device_id[2],
2851 d->device_id[3], d->device_id[4], d->device_id[5],
2852 d->device_id[6], d->device_id[7], d->device_id[8],
2853 d->device_id[9], d->device_id[10], d->device_id[11],
2854 d->device_id[12], d->device_id[13], d->device_id[14],
2855 d->device_id[15]);
2856
54b6e9e9
ST		 2857 /* Get the list of physical devices */
2858 physicals = kzalloc(reportsize, GFP_KERNEL);
3b51a7a3
JH		 2859 if (physicals == NULL)
2860 return 0;
54b6e9e9
ST		 2861 if (hpsa_scsi_do_report_phys_luns(h, (struct ReportLUNdata *) physicals,
2862 reportsize, extended)) {
2863 dev_err(&h->pdev->dev,
2864 "Can't lookup %s device handle: report physical LUNs failed.\n",
2865 "HP SSD Smart Path");
2866 kfree(physicals);
2867 return 0;
2868 }
2869 nphysicals = be32_to_cpu(*((__be32 *)physicals->LUNListLength)) /
2870 responsesize;
2871
2872
2873 /* find ioaccel2 handle in list of physicals: */
2874 for (i = 0; i < nphysicals; i++) {
2875 /* handle is in bytes 28-31 of each lun */
2876 if (memcmp(&((struct ReportExtendedLUNdata *)
2877 physicals)->LUN[i][20], &find, 4) != 0) {
2878 continue; /* didn't match */
2879 }
2880 found = 1;
2881 memcpy(scsi3addr, &((struct ReportExtendedLUNdata *)
2882 physicals)->LUN[i][0], 8);
2ba8bfc8
SC		 2883 if (h->raid_offload_debug > 0)
2884 dev_info(&h->pdev->dev,
2885 "%s: Searched h=0x%08x, Found h=0x%08x, scsiaddr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
2886 __func__, find,
2887 ((struct ReportExtendedLUNdata *)
2888 physicals)->LUN[i][20],
2889 scsi3addr[0], scsi3addr[1], scsi3addr[2],
2890 scsi3addr[3], scsi3addr[4], scsi3addr[5],
2891 scsi3addr[6], scsi3addr[7]);
54b6e9e9
ST		 2892 break; /* found it */
2893 }
2894
2895 kfree(physicals);
2896 if (found)
2897 return 1;
2898 else
2899 return 0;
2900
2901}
edd16368
SC		 2902/*
2903 * Do CISS_REPORT_PHYS and CISS_REPORT_LOG. Data is returned in physdev,
2904 * logdev. The number of luns in physdev and logdev are returned in
2905 * *nphysicals and *nlogicals, respectively.
2906 * Returns 0 on success, -1 otherwise.
2907 */
2908static int hpsa_gather_lun_info(struct ctlr_info *h,
2909 int reportlunsize,
283b4a9b 2910 struct ReportLUNdata *physdev, u32 *nphysicals, int *physical_mode,
01a02ffc 2911 struct ReportLUNdata *logdev, u32 *nlogicals)
edd16368 2912{
283b4a9b
SC		 2913 int physical_entry_size = 8;
2914
2915 *physical_mode = 0;
2916
2917 /* For I/O accelerator mode we need to read physical device handles */
317d4adf
MM		 2918 if (h->transMethod & CFGTBL_Trans_io_accel1 ||
2919 h->transMethod & CFGTBL_Trans_io_accel2) {
283b4a9b
SC		 2920 *physical_mode = HPSA_REPORT_PHYS_EXTENDED;
2921 physical_entry_size = 24;
2922 }
a93aa1fe 2923 if (hpsa_scsi_do_report_phys_luns(h, physdev, reportlunsize,
283b4a9b 2924 *physical_mode)) {
edd16368
SC		 2925 dev_err(&h->pdev->dev, "report physical LUNs failed.\n");
2926 return -1;
2927 }
283b4a9b
SC		 2928 *nphysicals = be32_to_cpu(*((__be32 *)physdev->LUNListLength)) /
2929 physical_entry_size;
edd16368
SC		 2930 if (*nphysicals > HPSA_MAX_PHYS_LUN) {
2931 dev_warn(&h->pdev->dev, "maximum physical LUNs (%d) exceeded."
2932 " %d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
2933 *nphysicals - HPSA_MAX_PHYS_LUN);
2934 *nphysicals = HPSA_MAX_PHYS_LUN;
2935 }
2936 if (hpsa_scsi_do_report_log_luns(h, logdev, reportlunsize)) {
2937 dev_err(&h->pdev->dev, "report logical LUNs failed.\n");
2938 return -1;
2939 }
6df1e954 2940 *nlogicals = be32_to_cpu(*((__be32 *) logdev->LUNListLength)) / 8;
edd16368
SC		 2941 /* Reject Logicals in excess of our max capability. */
2942 if (*nlogicals > HPSA_MAX_LUN) {
2943 dev_warn(&h->pdev->dev,
2944 "maximum logical LUNs (%d) exceeded. "
2945 "%d LUNs ignored.\n", HPSA_MAX_LUN,
2946 *nlogicals - HPSA_MAX_LUN);
2947 *nlogicals = HPSA_MAX_LUN;
2948 }
2949 if (*nlogicals + *nphysicals > HPSA_MAX_PHYS_LUN) {
2950 dev_warn(&h->pdev->dev,
2951 "maximum logical + physical LUNs (%d) exceeded. "
2952 "%d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
2953 *nphysicals + *nlogicals - HPSA_MAX_PHYS_LUN);
2954 *nlogicals = HPSA_MAX_PHYS_LUN - *nphysicals;
2955 }
2956 return 0;
2957}
2958
339b2b14 2959u8 *figure_lunaddrbytes(struct ctlr_info *h, int raid_ctlr_position, int i,
a93aa1fe
MG		 2960 int nphysicals, int nlogicals,
2961 struct ReportExtendedLUNdata *physdev_list,
339b2b14
SC		 2962 struct ReportLUNdata *logdev_list)
2963{
2964 /* Helper function, figure out where the LUN ID info is coming from
2965 * given index i, lists of physical and logical devices, where in
2966 * the list the raid controller is supposed to appear (first or last)
2967 */
2968
2969 int logicals_start = nphysicals + (raid_ctlr_position == 0);
2970 int last_device = nphysicals + nlogicals + (raid_ctlr_position == 0);
2971
2972 if (i == raid_ctlr_position)
2973 return RAID_CTLR_LUNID;
2974
2975 if (i < logicals_start)
2976 return &physdev_list->LUN[i - (raid_ctlr_position == 0)][0];
2977
2978 if (i < last_device)
2979 return &logdev_list->LUN[i - nphysicals -
2980 (raid_ctlr_position == 0)][0];
2981 BUG();
2982 return NULL;
2983}
2984
316b221a
SC		 2985static int hpsa_hba_mode_enabled(struct ctlr_info *h)
2986{
2987 int rc;
6e8e8088 2988 int hba_mode_enabled;
316b221a
SC		 2989 struct bmic_controller_parameters *ctlr_params;
2990 ctlr_params = kzalloc(sizeof(struct bmic_controller_parameters),
2991 GFP_KERNEL);
2992
2993 if (!ctlr_params)
96444fbb 2994 return -ENOMEM;
316b221a
SC		 2995 rc = hpsa_bmic_ctrl_mode_sense(h, RAID_CTLR_LUNID, 0, ctlr_params,
2996 sizeof(struct bmic_controller_parameters));
96444fbb 2997 if (rc) {
316b221a 2998 kfree(ctlr_params);
96444fbb 2999 return rc;
316b221a 3000 }
6e8e8088
JH		 3001
3002 hba_mode_enabled =
3003 ((ctlr_params->nvram_flags & HBA_MODE_ENABLED_FLAG) != 0);
3004 kfree(ctlr_params);
3005 return hba_mode_enabled;
316b221a
SC		 3006}
3007
edd16368
SC		 3008static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno)
3009{
3010 /* the idea here is we could get notified
3011 * that some devices have changed, so we do a report
3012 * physical luns and report logical luns cmd, and adjust
3013 * our list of devices accordingly.
3014 *
3015 * The scsi3addr's of devices won't change so long as the
3016 * adapter is not reset. That means we can rescan and
3017 * tell which devices we already know about, vs. new
3018 * devices, vs. disappearing devices.
3019 */
a93aa1fe 3020 struct ReportExtendedLUNdata *physdev_list = NULL;
edd16368 3021 struct ReportLUNdata *logdev_list = NULL;
01a02ffc
SC		 3022 u32 nphysicals = 0;
3023 u32 nlogicals = 0;
283b4a9b 3024 int physical_mode = 0;
01a02ffc 3025 u32 ndev_allocated = 0;
edd16368
SC		 3026 struct hpsa_scsi_dev_t **currentsd, *this_device, *tmpdevice;
3027 int ncurrent = 0;
283b4a9b 3028 int reportlunsize = sizeof(*physdev_list) + HPSA_MAX_PHYS_LUN * 24;
4f4eb9f1 3029 int i, n_ext_target_devs, ndevs_to_allocate;
339b2b14 3030 int raid_ctlr_position;
2bbf5c7f 3031 int rescan_hba_mode;
aca4a520 3032 DECLARE_BITMAP(lunzerobits, MAX_EXT_TARGETS);
edd16368 3033
cfe5badc 3034 currentsd = kzalloc(sizeof(*currentsd) * HPSA_MAX_DEVICES, GFP_KERNEL);
edd16368
SC		 3035 physdev_list = kzalloc(reportlunsize, GFP_KERNEL);
3036 logdev_list = kzalloc(reportlunsize, GFP_KERNEL);
edd16368
SC		 3037 tmpdevice = kzalloc(sizeof(*tmpdevice), GFP_KERNEL);
3038
0b0e1d6c 3039 if (!currentsd || !physdev_list || !logdev_list || !tmpdevice) {
edd16368
SC		 3040 dev_err(&h->pdev->dev, "out of memory\n");
3041 goto out;
3042 }
3043 memset(lunzerobits, 0, sizeof(lunzerobits));
3044
316b221a 3045 rescan_hba_mode = hpsa_hba_mode_enabled(h);
96444fbb
JH		 3046 if (rescan_hba_mode < 0)
3047 goto out;
316b221a
SC		 3048
3049 if (!h->hba_mode_enabled && rescan_hba_mode)
3050 dev_warn(&h->pdev->dev, "HBA mode enabled\n");
3051 else if (h->hba_mode_enabled && !rescan_hba_mode)
3052 dev_warn(&h->pdev->dev, "HBA mode disabled\n");
3053
3054 h->hba_mode_enabled = rescan_hba_mode;
3055
a93aa1fe
MG		 3056 if (hpsa_gather_lun_info(h, reportlunsize,
3057 (struct ReportLUNdata *) physdev_list, &nphysicals,
283b4a9b 3058 &physical_mode, logdev_list, &nlogicals))
edd16368
SC		 3059 goto out;
3060
aca4a520
ST		 3061 /* We might see up to the maximum number of logical and physical disks
3062 * plus external target devices, and a device for the local RAID
3063 * controller.
edd16368 3064 */
aca4a520 3065 ndevs_to_allocate = nphysicals + nlogicals + MAX_EXT_TARGETS + 1;
edd16368
SC		 3066
3067 /* Allocate the per device structures */
3068 for (i = 0; i < ndevs_to_allocate; i++) {
b7ec021f
ST		 3069 if (i >= HPSA_MAX_DEVICES) {
3070 dev_warn(&h->pdev->dev, "maximum devices (%d) exceeded."
3071 " %d devices ignored.\n", HPSA_MAX_DEVICES,
3072 ndevs_to_allocate - HPSA_MAX_DEVICES);
3073 break;
3074 }
3075
edd16368
SC		 3076 currentsd[i] = kzalloc(sizeof(*currentsd[i]), GFP_KERNEL);
3077 if (!currentsd[i]) {
3078 dev_warn(&h->pdev->dev, "out of memory at %s:%d\n",
3079 __FILE__, __LINE__);
3080 goto out;
3081 }
3082 ndev_allocated++;
3083 }
3084
339b2b14
SC		 3085 if (unlikely(is_scsi_rev_5(h)))
3086 raid_ctlr_position = 0;
3087 else
3088 raid_ctlr_position = nphysicals + nlogicals;
3089
edd16368 3090 /* adjust our table of devices */
4f4eb9f1 3091 n_ext_target_devs = 0;
edd16368 3092 for (i = 0; i < nphysicals + nlogicals + 1; i++) {
0b0e1d6c 3093 u8 *lunaddrbytes, is_OBDR = 0;
edd16368
SC		 3094
3095 /* Figure out where the LUN ID info is coming from */
339b2b14
SC		 3096 lunaddrbytes = figure_lunaddrbytes(h, raid_ctlr_position,
3097 i, nphysicals, nlogicals, physdev_list, logdev_list);
edd16368 3098 /* skip masked physical devices. */
339b2b14
SC		 3099 if (lunaddrbytes[3] & 0xC0 &&
3100 i < nphysicals + (raid_ctlr_position == 0))
edd16368
SC		 3101 continue;
3102
3103 /* Get device type, vendor, model, device id */
0b0e1d6c
SC		 3104 if (hpsa_update_device_info(h, lunaddrbytes, tmpdevice,
3105 &is_OBDR))
edd16368 3106 continue; /* skip it if we can't talk to it. */
1f310bde 3107 figure_bus_target_lun(h, lunaddrbytes, tmpdevice);
edd16368
SC		 3108 this_device = currentsd[ncurrent];
3109
3110 /*
4f4eb9f1 3111 * For external target devices, we have to insert a LUN 0 which
edd16368
SC		 3112 * doesn't show up in CCISS_REPORT_PHYSICAL data, but there
3113 * is nonetheless an enclosure device there. We have to
3114 * present that otherwise linux won't find anything if
3115 * there is no lun 0.
3116 */
4f4eb9f1 3117 if (add_ext_target_dev(h, tmpdevice, this_device,
1f310bde 3118 lunaddrbytes, lunzerobits,
4f4eb9f1 3119 &n_ext_target_devs)) {
edd16368
SC		 3120 ncurrent++;
3121 this_device = currentsd[ncurrent];
3122 }
3123
3124 *this_device = *tmpdevice;
edd16368
SC		 3125
3126 switch (this_device->devtype) {
0b0e1d6c 3127 case TYPE_ROM:
edd16368
SC		 3128 /* We don't *really* support actual CD-ROM devices,
3129 * just "One Button Disaster Recovery" tape drive
3130 * which temporarily pretends to be a CD-ROM drive.
3131 * So we check that the device is really an OBDR tape
3132 * device by checking for "$DR-10" in bytes 43-48 of
3133 * the inquiry data.
3134 */
0b0e1d6c
SC		 3135 if (is_OBDR)
3136 ncurrent++;
edd16368
SC		 3137 break;
3138 case TYPE_DISK:
316b221a
SC		 3139 if (h->hba_mode_enabled) {
3140 /* never use raid mapper in HBA mode */
3141 this_device->offload_enabled = 0;
3142 ncurrent++;
3143 break;
3144 } else if (h->acciopath_status) {
3145 if (i >= nphysicals) {
3146 ncurrent++;
3147 break;
3148 }
3149 } else {
3150 if (i < nphysicals)
3151 break;
283b4a9b 3152 ncurrent++;
edd16368 3153 break;
283b4a9b
SC		 3154 }
3155 if (physical_mode == HPSA_REPORT_PHYS_EXTENDED) {
3156 memcpy(&this_device->ioaccel_handle,
3157 &lunaddrbytes[20],
3158 sizeof(this_device->ioaccel_handle));
3159 ncurrent++;
3160 }
edd16368
SC		 3161 break;
3162 case TYPE_TAPE:
3163 case TYPE_MEDIUM_CHANGER:
3164 ncurrent++;
3165 break;
3166 case TYPE_RAID:
3167 /* Only present the Smartarray HBA as a RAID controller.
3168 * If it's a RAID controller other than the HBA itself
3169 * (an external RAID controller, MSA500 or similar)
3170 * don't present it.
3171 */
3172 if (!is_hba_lunid(lunaddrbytes))
3173 break;
3174 ncurrent++;
3175 break;
3176 default:
3177 break;
3178 }
cfe5badc 3179 if (ncurrent >= HPSA_MAX_DEVICES)
edd16368
SC		 3180 break;
3181 }
3182 adjust_hpsa_scsi_table(h, hostno, currentsd, ncurrent);
3183out:
3184 kfree(tmpdevice);
3185 for (i = 0; i < ndev_allocated; i++)
3186 kfree(currentsd[i]);
3187 kfree(currentsd);
edd16368
SC		 3188 kfree(physdev_list);
3189 kfree(logdev_list);
edd16368
SC		 3190}
3191
3192/* hpsa_scatter_gather takes a struct scsi_cmnd, (cmd), and does the pci
3193 * dma mapping and fills in the scatter gather entries of the
3194 * hpsa command, cp.
3195 */
33a2ffce 3196static int hpsa_scatter_gather(struct ctlr_info *h,
edd16368
SC		 3197 struct CommandList *cp,
3198 struct scsi_cmnd *cmd)
3199{
3200 unsigned int len;
3201 struct scatterlist *sg;
01a02ffc 3202 u64 addr64;
33a2ffce
SC		 3203 int use_sg, i, sg_index, chained;
3204 struct SGDescriptor *curr_sg;
edd16368 3205
33a2ffce 3206 BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
edd16368
SC		 3207
3208 use_sg = scsi_dma_map(cmd);
3209 if (use_sg < 0)
3210 return use_sg;
3211
3212 if (!use_sg)
3213 goto sglist_finished;
3214
33a2ffce
SC		 3215 curr_sg = cp->SG;
3216 chained = 0;
3217 sg_index = 0;
edd16368 3218 scsi_for_each_sg(cmd, sg, use_sg, i) {
33a2ffce
SC		 3219 if (i == h->max_cmd_sg_entries - 1 &&
3220 use_sg > h->max_cmd_sg_entries) {
3221 chained = 1;
3222 curr_sg = h->cmd_sg_list[cp->cmdindex];
3223 sg_index = 0;
3224 }
01a02ffc 3225 addr64 = (u64) sg_dma_address(sg);
edd16368 3226 len = sg_dma_len(sg);
33a2ffce
SC		 3227 curr_sg->Addr.lower = (u32) (addr64 & 0x0FFFFFFFFULL);
3228 curr_sg->Addr.upper = (u32) ((addr64 >> 32) & 0x0FFFFFFFFULL);
3229 curr_sg->Len = len;
e1d9cbfa 3230 curr_sg->Ext = (i < scsi_sg_count(cmd) - 1) ? 0 : HPSA_SG_LAST;
33a2ffce
SC		 3231 curr_sg++;
3232 }
3233
3234 if (use_sg + chained > h->maxSG)
3235 h->maxSG = use_sg + chained;
3236
3237 if (chained) {
3238 cp->Header.SGList = h->max_cmd_sg_entries;
3239 cp->Header.SGTotal = (u16) (use_sg + 1);
e2bea6df
SC		 3240 if (hpsa_map_sg_chain_block(h, cp)) {
3241 scsi_dma_unmap(cmd);
3242 return -1;
3243 }
33a2ffce 3244 return 0;
edd16368
SC		 3245 }
3246
3247sglist_finished:
3248
01a02ffc
SC		 3249 cp->Header.SGList = (u8) use_sg; /* no. SGs contig in this cmd */
3250 cp->Header.SGTotal = (u16) use_sg; /* total sgs in this cmd list */
edd16368
SC		 3251 return 0;
3252}
3253
283b4a9b
SC		 3254#define IO_ACCEL_INELIGIBLE (1)
3255static int fixup_ioaccel_cdb(u8 *cdb, int *cdb_len)
3256{
3257 int is_write = 0;
3258 u32 block;
3259 u32 block_cnt;
3260
3261 /* Perform some CDB fixups if needed using 10 byte reads/writes only */
3262 switch (cdb[0]) {
3263 case WRITE_6:
3264 case WRITE_12:
3265 is_write = 1;
3266 case READ_6:
3267 case READ_12:
3268 if (*cdb_len == 6) {
3269 block = (((u32) cdb[2]) << 8) | cdb[3];
3270 block_cnt = cdb[4];
3271 } else {
3272 BUG_ON(*cdb_len != 12);
3273 block = (((u32) cdb[2]) << 24) |
3274 (((u32) cdb[3]) << 16) |
3275 (((u32) cdb[4]) << 8) |
3276 cdb[5];
3277 block_cnt =
3278 (((u32) cdb[6]) << 24) |
3279 (((u32) cdb[7]) << 16) |
3280 (((u32) cdb[8]) << 8) |
3281 cdb[9];
3282 }
3283 if (block_cnt > 0xffff)
3284 return IO_ACCEL_INELIGIBLE;
3285
3286 cdb[0] = is_write ? WRITE_10 : READ_10;
3287 cdb[1] = 0;
3288 cdb[2] = (u8) (block >> 24);
3289 cdb[3] = (u8) (block >> 16);
3290 cdb[4] = (u8) (block >> 8);
3291 cdb[5] = (u8) (block);
3292 cdb[6] = 0;
3293 cdb[7] = (u8) (block_cnt >> 8);
3294 cdb[8] = (u8) (block_cnt);
3295 cdb[9] = 0;
3296 *cdb_len = 10;
3297 break;
3298 }
3299 return 0;
3300}
3301
c349775e 3302static int hpsa_scsi_ioaccel1_queue_command(struct ctlr_info *h,
283b4a9b
SC		 3303 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
3304 u8 *scsi3addr)
e1f7de0c
MG		 3305{
3306 struct scsi_cmnd *cmd = c->scsi_cmd;
e1f7de0c
MG		 3307 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
3308 unsigned int len;
3309 unsigned int total_len = 0;
3310 struct scatterlist *sg;
3311 u64 addr64;
3312 int use_sg, i;
3313 struct SGDescriptor *curr_sg;
3314 u32 control = IOACCEL1_CONTROL_SIMPLEQUEUE;
3315
283b4a9b
SC		 3316 /* TODO: implement chaining support */
3317 if (scsi_sg_count(cmd) > h->ioaccel_maxsg)
3318 return IO_ACCEL_INELIGIBLE;
3319
e1f7de0c
MG		 3320 BUG_ON(cmd->cmd_len > IOACCEL1_IOFLAGS_CDBLEN_MAX);
3321
283b4a9b
SC		 3322 if (fixup_ioaccel_cdb(cdb, &cdb_len))
3323 return IO_ACCEL_INELIGIBLE;
3324
e1f7de0c
MG		 3325 c->cmd_type = CMD_IOACCEL1;
3326
3327 /* Adjust the DMA address to point to the accelerated command buffer */
3328 c->busaddr = (u32) h->ioaccel_cmd_pool_dhandle +
3329 (c->cmdindex * sizeof(*cp));
3330 BUG_ON(c->busaddr & 0x0000007F);
3331
3332 use_sg = scsi_dma_map(cmd);
3333 if (use_sg < 0)
3334 return use_sg;
3335
3336 if (use_sg) {
3337 curr_sg = cp->SG;
3338 scsi_for_each_sg(cmd, sg, use_sg, i) {
3339 addr64 = (u64) sg_dma_address(sg);
3340 len = sg_dma_len(sg);
3341 total_len += len;
3342 curr_sg->Addr.lower = (u32) (addr64 & 0x0FFFFFFFFULL);
3343 curr_sg->Addr.upper =
3344 (u32) ((addr64 >> 32) & 0x0FFFFFFFFULL);
3345 curr_sg->Len = len;
3346
3347 if (i == (scsi_sg_count(cmd) - 1))
3348 curr_sg->Ext = HPSA_SG_LAST;
3349 else
3350 curr_sg->Ext = 0; /* we are not chaining */
3351 curr_sg++;
3352 }
3353
3354 switch (cmd->sc_data_direction) {
3355 case DMA_TO_DEVICE:
3356 control |= IOACCEL1_CONTROL_DATA_OUT;
3357 break;
3358 case DMA_FROM_DEVICE:
3359 control |= IOACCEL1_CONTROL_DATA_IN;
3360 break;
3361 case DMA_NONE:
3362 control |= IOACCEL1_CONTROL_NODATAXFER;
3363 break;
3364 default:
3365 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
3366 cmd->sc_data_direction);
3367 BUG();
3368 break;
3369 }
3370 } else {
3371 control |= IOACCEL1_CONTROL_NODATAXFER;
3372 }
3373
c349775e 3374 c->Header.SGList = use_sg;
e1f7de0c 3375 /* Fill out the command structure to submit */
283b4a9b 3376 cp->dev_handle = ioaccel_handle & 0xFFFF;
e1f7de0c
MG		 3377 cp->transfer_len = total_len;
3378 cp->io_flags = IOACCEL1_IOFLAGS_IO_REQ |
283b4a9b 3379 (cdb_len & IOACCEL1_IOFLAGS_CDBLEN_MASK);
e1f7de0c 3380 cp->control = control;
283b4a9b
SC		 3381 memcpy(cp->CDB, cdb, cdb_len);
3382 memcpy(cp->CISS_LUN, scsi3addr, 8);
c349775e 3383 /* Tag was already set at init time. */
283b4a9b 3384 enqueue_cmd_and_start_io(h, c);
e1f7de0c
MG		 3385 return 0;
3386}
edd16368 3387
283b4a9b
SC		 3388/*
3389 * Queue a command directly to a device behind the controller using the
3390 * I/O accelerator path.
3391 */
3392static int hpsa_scsi_ioaccel_direct_map(struct ctlr_info *h,
3393 struct CommandList *c)
3394{
3395 struct scsi_cmnd *cmd = c->scsi_cmd;
3396 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
3397
3398 return hpsa_scsi_ioaccel_queue_command(h, c, dev->ioaccel_handle,
3399 cmd->cmnd, cmd->cmd_len, dev->scsi3addr);
3400}
3401
dd0e19f3
ST		 3402/*
3403 * Set encryption parameters for the ioaccel2 request
3404 */
3405static void set_encrypt_ioaccel2(struct ctlr_info *h,
3406 struct CommandList *c, struct io_accel2_cmd *cp)
3407{
3408 struct scsi_cmnd *cmd = c->scsi_cmd;
3409 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
3410 struct raid_map_data *map = &dev->raid_map;
3411 u64 first_block;
3412
3413 BUG_ON(!(dev->offload_config && dev->offload_enabled));
3414
3415 /* Are we doing encryption on this device */
3416 if (!(map->flags & RAID_MAP_FLAG_ENCRYPT_ON))
3417 return;
3418 /* Set the data encryption key index. */
3419 cp->dekindex = map->dekindex;
3420
3421 /* Set the encryption enable flag, encoded into direction field. */
3422 cp->direction |= IOACCEL2_DIRECTION_ENCRYPT_MASK;
3423
3424 /* Set encryption tweak values based on logical block address
3425 * If block size is 512, tweak value is LBA.
3426 * For other block sizes, tweak is (LBA * block size)/ 512)
3427 */
3428 switch (cmd->cmnd[0]) {
3429 /* Required? 6-byte cdbs eliminated by fixup_ioaccel_cdb */
3430 case WRITE_6:
3431 case READ_6:
3432 if (map->volume_blk_size == 512) {
3433 cp->tweak_lower =
3434 (((u32) cmd->cmnd[2]) << 8) |
3435 cmd->cmnd[3];
3436 cp->tweak_upper = 0;
3437 } else {
3438 first_block =
3439 (((u64) cmd->cmnd[2]) << 8) |
3440 cmd->cmnd[3];
3441 first_block = (first_block * map->volume_blk_size)/512;
3442 cp->tweak_lower = (u32)first_block;
3443 cp->tweak_upper = (u32)(first_block >> 32);
3444 }
3445 break;
3446 case WRITE_10:
3447 case READ_10:
3448 if (map->volume_blk_size == 512) {
3449 cp->tweak_lower =
3450 (((u32) cmd->cmnd[2]) << 24) |
3451 (((u32) cmd->cmnd[3]) << 16) |
3452 (((u32) cmd->cmnd[4]) << 8) |
3453 cmd->cmnd[5];
3454 cp->tweak_upper = 0;
3455 } else {
3456 first_block =
3457 (((u64) cmd->cmnd[2]) << 24) |
3458 (((u64) cmd->cmnd[3]) << 16) |
3459 (((u64) cmd->cmnd[4]) << 8) |
3460 cmd->cmnd[5];
3461 first_block = (first_block * map->volume_blk_size)/512;
3462 cp->tweak_lower = (u32)first_block;
3463 cp->tweak_upper = (u32)(first_block >> 32);
3464 }
3465 break;
3466 /* Required? 12-byte cdbs eliminated by fixup_ioaccel_cdb */
3467 case WRITE_12:
3468 case READ_12:
3469 if (map->volume_blk_size == 512) {
3470 cp->tweak_lower =
3471 (((u32) cmd->cmnd[2]) << 24) |
3472 (((u32) cmd->cmnd[3]) << 16) |
3473 (((u32) cmd->cmnd[4]) << 8) |
3474 cmd->cmnd[5];
3475 cp->tweak_upper = 0;
3476 } else {
3477 first_block =
3478 (((u64) cmd->cmnd[2]) << 24) |
3479 (((u64) cmd->cmnd[3]) << 16) |
3480 (((u64) cmd->cmnd[4]) << 8) |
3481 cmd->cmnd[5];
3482 first_block = (first_block * map->volume_blk_size)/512;
3483 cp->tweak_lower = (u32)first_block;
3484 cp->tweak_upper = (u32)(first_block >> 32);
3485 }
3486 break;
3487 case WRITE_16:
3488 case READ_16:
3489 if (map->volume_blk_size == 512) {
3490 cp->tweak_lower =
3491 (((u32) cmd->cmnd[6]) << 24) |
3492 (((u32) cmd->cmnd[7]) << 16) |
3493 (((u32) cmd->cmnd[8]) << 8) |
3494 cmd->cmnd[9];
3495 cp->tweak_upper =
3496 (((u32) cmd->cmnd[2]) << 24) |
3497 (((u32) cmd->cmnd[3]) << 16) |
3498 (((u32) cmd->cmnd[4]) << 8) |
3499 cmd->cmnd[5];
3500 } else {
3501 first_block =
3502 (((u64) cmd->cmnd[2]) << 56) |
3503 (((u64) cmd->cmnd[3]) << 48) |
3504 (((u64) cmd->cmnd[4]) << 40) |
3505 (((u64) cmd->cmnd[5]) << 32) |
3506 (((u64) cmd->cmnd[6]) << 24) |
3507 (((u64) cmd->cmnd[7]) << 16) |
3508 (((u64) cmd->cmnd[8]) << 8) |
3509 cmd->cmnd[9];
3510 first_block = (first_block * map->volume_blk_size)/512;
3511 cp->tweak_lower = (u32)first_block;
3512 cp->tweak_upper = (u32)(first_block >> 32);
3513 }
3514 break;
3515 default:
3516 dev_err(&h->pdev->dev,
3517 "ERROR: %s: IOACCEL request CDB size not supported for encryption\n",
3518 __func__);
3519 BUG();
3520 break;
3521 }
3522}
3523
c349775e
ST		 3524static int hpsa_scsi_ioaccel2_queue_command(struct ctlr_info *h,
3525 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
3526 u8 *scsi3addr)
3527{
3528 struct scsi_cmnd *cmd = c->scsi_cmd;
3529 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
3530 struct ioaccel2_sg_element *curr_sg;
3531 int use_sg, i;
3532 struct scatterlist *sg;
3533 u64 addr64;
3534 u32 len;
3535 u32 total_len = 0;
3536
3537 if (scsi_sg_count(cmd) > h->ioaccel_maxsg)
3538 return IO_ACCEL_INELIGIBLE;
3539
3540 if (fixup_ioaccel_cdb(cdb, &cdb_len))
3541 return IO_ACCEL_INELIGIBLE;
3542 c->cmd_type = CMD_IOACCEL2;
3543 /* Adjust the DMA address to point to the accelerated command buffer */
3544 c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle +
3545 (c->cmdindex * sizeof(*cp));
3546 BUG_ON(c->busaddr & 0x0000007F);
3547
3548 memset(cp, 0, sizeof(*cp));
3549 cp->IU_type = IOACCEL2_IU_TYPE;
3550
3551 use_sg = scsi_dma_map(cmd);
3552 if (use_sg < 0)
3553 return use_sg;
3554
3555 if (use_sg) {
3556 BUG_ON(use_sg > IOACCEL2_MAXSGENTRIES);
3557 curr_sg = cp->sg;
3558 scsi_for_each_sg(cmd, sg, use_sg, i) {
3559 addr64 = (u64) sg_dma_address(sg);
3560 len = sg_dma_len(sg);
3561 total_len += len;
3562 curr_sg->address = cpu_to_le64(addr64);
3563 curr_sg->length = cpu_to_le32(len);
3564 curr_sg->reserved[0] = 0;
3565 curr_sg->reserved[1] = 0;
3566 curr_sg->reserved[2] = 0;
3567 curr_sg->chain_indicator = 0;
3568 curr_sg++;
3569 }
3570
3571 switch (cmd->sc_data_direction) {
3572 case DMA_TO_DEVICE:
dd0e19f3
ST		 3573 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3574 cp->direction |= IOACCEL2_DIR_DATA_OUT;
c349775e
ST		 3575 break;
3576 case DMA_FROM_DEVICE:
dd0e19f3
ST		 3577 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3578 cp->direction |= IOACCEL2_DIR_DATA_IN;
c349775e
ST		 3579 break;
3580 case DMA_NONE:
dd0e19f3
ST		 3581 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3582 cp->direction |= IOACCEL2_DIR_NO_DATA;
c349775e
ST		 3583 break;
3584 default:
3585 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
3586 cmd->sc_data_direction);
3587 BUG();
3588 break;
3589 }
3590 } else {
dd0e19f3
ST		 3591 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3592 cp->direction |= IOACCEL2_DIR_NO_DATA;
c349775e 3593 }
dd0e19f3
ST		 3594
3595 /* Set encryption parameters, if necessary */
3596 set_encrypt_ioaccel2(h, c, cp);
3597
c349775e 3598 cp->scsi_nexus = ioaccel_handle;
dd0e19f3 3599 cp->Tag = (c->cmdindex << DIRECT_LOOKUP_SHIFT) |
c349775e
ST		 3600 DIRECT_LOOKUP_BIT;
3601 memcpy(cp->cdb, cdb, sizeof(cp->cdb));
c349775e
ST		 3602
3603 /* fill in sg elements */
3604 cp->sg_count = (u8) use_sg;
3605
3606 cp->data_len = cpu_to_le32(total_len);
3607 cp->err_ptr = cpu_to_le64(c->busaddr +
3608 offsetof(struct io_accel2_cmd, error_data));
3609 cp->err_len = cpu_to_le32((u32) sizeof(cp->error_data));
3610
3611 enqueue_cmd_and_start_io(h, c);
3612 return 0;
3613}
3614
3615/*
3616 * Queue a command to the correct I/O accelerator path.
3617 */
3618static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
3619 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
3620 u8 *scsi3addr)
3621{
3622 if (h->transMethod & CFGTBL_Trans_io_accel1)
3623 return hpsa_scsi_ioaccel1_queue_command(h, c, ioaccel_handle,
3624 cdb, cdb_len, scsi3addr);
3625 else
3626 return hpsa_scsi_ioaccel2_queue_command(h, c, ioaccel_handle,
3627 cdb, cdb_len, scsi3addr);
3628}
3629
6b80b18f
ST		 3630static void raid_map_helper(struct raid_map_data *map,
3631 int offload_to_mirror, u32 *map_index, u32 *current_group)
3632{
3633 if (offload_to_mirror == 0) {
3634 /* use physical disk in the first mirrored group. */
3635 *map_index %= map->data_disks_per_row;
3636 return;
3637 }
3638 do {
3639 /* determine mirror group that *map_index indicates */
3640 *current_group = *map_index / map->data_disks_per_row;
3641 if (offload_to_mirror == *current_group)
3642 continue;
3643 if (*current_group < (map->layout_map_count - 1)) {
3644 /* select map index from next group */
3645 *map_index += map->data_disks_per_row;
3646 (*current_group)++;
3647 } else {
3648 /* select map index from first group */
3649 *map_index %= map->data_disks_per_row;
3650 *current_group = 0;
3651 }
3652 } while (offload_to_mirror != *current_group);
3653}
3654
283b4a9b
SC		 3655/*
3656 * Attempt to perform offload RAID mapping for a logical volume I/O.
3657 */
3658static int hpsa_scsi_ioaccel_raid_map(struct ctlr_info *h,
3659 struct CommandList *c)
3660{
3661 struct scsi_cmnd *cmd = c->scsi_cmd;
3662 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
3663 struct raid_map_data *map = &dev->raid_map;
3664 struct raid_map_disk_data *dd = &map->data[0];
3665 int is_write = 0;
3666 u32 map_index;
3667 u64 first_block, last_block;
3668 u32 block_cnt;
3669 u32 blocks_per_row;
3670 u64 first_row, last_row;
3671 u32 first_row_offset, last_row_offset;
3672 u32 first_column, last_column;
6b80b18f
ST		 3673 u64 r0_first_row, r0_last_row;
3674 u32 r5or6_blocks_per_row;
3675 u64 r5or6_first_row, r5or6_last_row;
3676 u32 r5or6_first_row_offset, r5or6_last_row_offset;
3677 u32 r5or6_first_column, r5or6_last_column;
3678 u32 total_disks_per_row;
3679 u32 stripesize;
3680 u32 first_group, last_group, current_group;
283b4a9b
SC		 3681 u32 map_row;
3682 u32 disk_handle;
3683 u64 disk_block;
3684 u32 disk_block_cnt;
3685 u8 cdb[16];
3686 u8 cdb_len;
3687#if BITS_PER_LONG == 32
3688 u64 tmpdiv;
3689#endif
6b80b18f 3690 int offload_to_mirror;
283b4a9b
SC		 3691
3692 BUG_ON(!(dev->offload_config && dev->offload_enabled));
3693
3694 /* check for valid opcode, get LBA and block count */
3695 switch (cmd->cmnd[0]) {
3696 case WRITE_6:
3697 is_write = 1;
3698 case READ_6:
3699 first_block =
3700 (((u64) cmd->cmnd[2]) << 8) |
3701 cmd->cmnd[3];
3702 block_cnt = cmd->cmnd[4];
3703 break;
3704 case WRITE_10:
3705 is_write = 1;
3706 case READ_10:
3707 first_block =
3708 (((u64) cmd->cmnd[2]) << 24) |
3709 (((u64) cmd->cmnd[3]) << 16) |
3710 (((u64) cmd->cmnd[4]) << 8) |
3711 cmd->cmnd[5];
3712 block_cnt =
3713 (((u32) cmd->cmnd[7]) << 8) |
3714 cmd->cmnd[8];
3715 break;
3716 case WRITE_12:
3717 is_write = 1;
3718 case READ_12:
3719 first_block =
3720 (((u64) cmd->cmnd[2]) << 24) |
3721 (((u64) cmd->cmnd[3]) << 16) |
3722 (((u64) cmd->cmnd[4]) << 8) |
3723 cmd->cmnd[5];
3724 block_cnt =
3725 (((u32) cmd->cmnd[6]) << 24) |
3726 (((u32) cmd->cmnd[7]) << 16) |
3727 (((u32) cmd->cmnd[8]) << 8) |
3728 cmd->cmnd[9];
3729 break;
3730 case WRITE_16:
3731 is_write = 1;
3732 case READ_16:
3733 first_block =
3734 (((u64) cmd->cmnd[2]) << 56) |
3735 (((u64) cmd->cmnd[3]) << 48) |
3736 (((u64) cmd->cmnd[4]) << 40) |
3737 (((u64) cmd->cmnd[5]) << 32) |
3738 (((u64) cmd->cmnd[6]) << 24) |
3739 (((u64) cmd->cmnd[7]) << 16) |
3740 (((u64) cmd->cmnd[8]) << 8) |
3741 cmd->cmnd[9];
3742 block_cnt =
3743 (((u32) cmd->cmnd[10]) << 24) |
3744 (((u32) cmd->cmnd[11]) << 16) |
3745 (((u32) cmd->cmnd[12]) << 8) |
3746 cmd->cmnd[13];
3747 break;
3748 default:
3749 return IO_ACCEL_INELIGIBLE; /* process via normal I/O path */
3750 }
3751 BUG_ON(block_cnt == 0);
3752 last_block = first_block + block_cnt - 1;
3753
3754 /* check for write to non-RAID-0 */
3755 if (is_write && dev->raid_level != 0)
3756 return IO_ACCEL_INELIGIBLE;
3757
3758 /* check for invalid block or wraparound */
3759 if (last_block >= map->volume_blk_cnt || last_block < first_block)
3760 return IO_ACCEL_INELIGIBLE;
3761
3762 /* calculate stripe information for the request */
3763 blocks_per_row = map->data_disks_per_row * map->strip_size;
3764#if BITS_PER_LONG == 32
3765 tmpdiv = first_block;
3766 (void) do_div(tmpdiv, blocks_per_row);
3767 first_row = tmpdiv;
3768 tmpdiv = last_block;
3769 (void) do_div(tmpdiv, blocks_per_row);
3770 last_row = tmpdiv;
3771 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
3772 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
3773 tmpdiv = first_row_offset;
3774 (void) do_div(tmpdiv, map->strip_size);
3775 first_column = tmpdiv;
3776 tmpdiv = last_row_offset;
3777 (void) do_div(tmpdiv, map->strip_size);
3778 last_column = tmpdiv;
3779#else
3780 first_row = first_block / blocks_per_row;
3781 last_row = last_block / blocks_per_row;
3782 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
3783 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
3784 first_column = first_row_offset / map->strip_size;
3785 last_column = last_row_offset / map->strip_size;
3786#endif
3787
3788 /* if this isn't a single row/column then give to the controller */
3789 if ((first_row != last_row) || (first_column != last_column))
3790 return IO_ACCEL_INELIGIBLE;
3791
3792 /* proceeding with driver mapping */
6b80b18f
ST		 3793 total_disks_per_row = map->data_disks_per_row +
3794 map->metadata_disks_per_row;
283b4a9b
SC		 3795 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
3796 map->row_cnt;
6b80b18f
ST		 3797 map_index = (map_row * total_disks_per_row) + first_column;
3798
3799 switch (dev->raid_level) {
3800 case HPSA_RAID_0:
3801 break; /* nothing special to do */
3802 case HPSA_RAID_1:
3803 /* Handles load balance across RAID 1 members.
3804 * (2-drive R1 and R10 with even # of drives.)
3805 * Appropriate for SSDs, not optimal for HDDs
283b4a9b 3806 */
6b80b18f 3807 BUG_ON(map->layout_map_count != 2);
283b4a9b
SC		 3808 if (dev->offload_to_mirror)
3809 map_index += map->data_disks_per_row;
3810 dev->offload_to_mirror = !dev->offload_to_mirror;
6b80b18f
ST		 3811 break;
3812 case HPSA_RAID_ADM:
3813 /* Handles N-way mirrors (R1-ADM)
3814 * and R10 with # of drives divisible by 3.)
3815 */
3816 BUG_ON(map->layout_map_count != 3);
3817
3818 offload_to_mirror = dev->offload_to_mirror;
3819 raid_map_helper(map, offload_to_mirror,
3820 &map_index, &current_group);
3821 /* set mirror group to use next time */
3822 offload_to_mirror =
3823 (offload_to_mirror >= map->layout_map_count - 1)
3824 ? 0 : offload_to_mirror + 1;
3825 /* FIXME: remove after debug/dev */
3826 BUG_ON(offload_to_mirror >= map->layout_map_count);
3827 dev_warn(&h->pdev->dev,
3828 "DEBUG: Using physical disk map index %d from mirror group %d\n",
3829 map_index, offload_to_mirror);
3830 dev->offload_to_mirror = offload_to_mirror;
3831 /* Avoid direct use of dev->offload_to_mirror within this
3832 * function since multiple threads might simultaneously
3833 * increment it beyond the range of dev->layout_map_count -1.
3834 */
3835 break;
3836 case HPSA_RAID_5:
3837 case HPSA_RAID_6:
3838 if (map->layout_map_count <= 1)
3839 break;
3840
3841 /* Verify first and last block are in same RAID group */
3842 r5or6_blocks_per_row =
3843 map->strip_size * map->data_disks_per_row;
3844 BUG_ON(r5or6_blocks_per_row == 0);
3845 stripesize = r5or6_blocks_per_row * map->layout_map_count;
3846#if BITS_PER_LONG == 32
3847 tmpdiv = first_block;
3848 first_group = do_div(tmpdiv, stripesize);
3849 tmpdiv = first_group;
3850 (void) do_div(tmpdiv, r5or6_blocks_per_row);
3851 first_group = tmpdiv;
3852 tmpdiv = last_block;
3853 last_group = do_div(tmpdiv, stripesize);
3854 tmpdiv = last_group;
3855 (void) do_div(tmpdiv, r5or6_blocks_per_row);
3856 last_group = tmpdiv;
3857#else
3858 first_group = (first_block % stripesize) / r5or6_blocks_per_row;
3859 last_group = (last_block % stripesize) / r5or6_blocks_per_row;
6b80b18f 3860#endif
000ff7c2 3861 if (first_group != last_group)
6b80b18f
ST		 3862 return IO_ACCEL_INELIGIBLE;
3863
3864 /* Verify request is in a single row of RAID 5/6 */
3865#if BITS_PER_LONG == 32
3866 tmpdiv = first_block;
3867 (void) do_div(tmpdiv, stripesize);
3868 first_row = r5or6_first_row = r0_first_row = tmpdiv;
3869 tmpdiv = last_block;
3870 (void) do_div(tmpdiv, stripesize);
3871 r5or6_last_row = r0_last_row = tmpdiv;
3872#else
3873 first_row = r5or6_first_row = r0_first_row =
3874 first_block / stripesize;
3875 r5or6_last_row = r0_last_row = last_block / stripesize;
3876#endif
3877 if (r5or6_first_row != r5or6_last_row)
3878 return IO_ACCEL_INELIGIBLE;
3879
3880
3881 /* Verify request is in a single column */
3882#if BITS_PER_LONG == 32
3883 tmpdiv = first_block;
3884 first_row_offset = do_div(tmpdiv, stripesize);
3885 tmpdiv = first_row_offset;
3886 first_row_offset = (u32) do_div(tmpdiv, r5or6_blocks_per_row);
3887 r5or6_first_row_offset = first_row_offset;
3888 tmpdiv = last_block;
3889 r5or6_last_row_offset = do_div(tmpdiv, stripesize);
3890 tmpdiv = r5or6_last_row_offset;
3891 r5or6_last_row_offset = do_div(tmpdiv, r5or6_blocks_per_row);
3892 tmpdiv = r5or6_first_row_offset;
3893 (void) do_div(tmpdiv, map->strip_size);
3894 first_column = r5or6_first_column = tmpdiv;
3895 tmpdiv = r5or6_last_row_offset;
3896 (void) do_div(tmpdiv, map->strip_size);
3897 r5or6_last_column = tmpdiv;
3898#else
3899 first_row_offset = r5or6_first_row_offset =
3900 (u32)((first_block % stripesize) %
3901 r5or6_blocks_per_row);
3902
3903 r5or6_last_row_offset =
3904 (u32)((last_block % stripesize) %
3905 r5or6_blocks_per_row);
3906
3907 first_column = r5or6_first_column =
3908 r5or6_first_row_offset / map->strip_size;
3909 r5or6_last_column =
3910 r5or6_last_row_offset / map->strip_size;
3911#endif
3912 if (r5or6_first_column != r5or6_last_column)
3913 return IO_ACCEL_INELIGIBLE;
3914
3915 /* Request is eligible */
3916 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
3917 map->row_cnt;
3918
3919 map_index = (first_group *
3920 (map->row_cnt * total_disks_per_row)) +
3921 (map_row * total_disks_per_row) + first_column;
3922 break;
3923 default:
3924 return IO_ACCEL_INELIGIBLE;
283b4a9b 3925 }
6b80b18f 3926
283b4a9b
SC		 3927 disk_handle = dd[map_index].ioaccel_handle;
3928 disk_block = map->disk_starting_blk + (first_row * map->strip_size) +
3929 (first_row_offset - (first_column * map->strip_size));
3930 disk_block_cnt = block_cnt;
3931
3932 /* handle differing logical/physical block sizes */
3933 if (map->phys_blk_shift) {
3934 disk_block <<= map->phys_blk_shift;
3935 disk_block_cnt <<= map->phys_blk_shift;
3936 }
3937 BUG_ON(disk_block_cnt > 0xffff);
3938
3939 /* build the new CDB for the physical disk I/O */
3940 if (disk_block > 0xffffffff) {
3941 cdb[0] = is_write ? WRITE_16 : READ_16;
3942 cdb[1] = 0;
3943 cdb[2] = (u8) (disk_block >> 56);
3944 cdb[3] = (u8) (disk_block >> 48);
3945 cdb[4] = (u8) (disk_block >> 40);
3946 cdb[5] = (u8) (disk_block >> 32);
3947 cdb[6] = (u8) (disk_block >> 24);
3948 cdb[7] = (u8) (disk_block >> 16);
3949 cdb[8] = (u8) (disk_block >> 8);
3950 cdb[9] = (u8) (disk_block);
3951 cdb[10] = (u8) (disk_block_cnt >> 24);
3952 cdb[11] = (u8) (disk_block_cnt >> 16);
3953 cdb[12] = (u8) (disk_block_cnt >> 8);
3954 cdb[13] = (u8) (disk_block_cnt);
3955 cdb[14] = 0;
3956 cdb[15] = 0;
3957 cdb_len = 16;
3958 } else {
3959 cdb[0] = is_write ? WRITE_10 : READ_10;
3960 cdb[1] = 0;
3961 cdb[2] = (u8) (disk_block >> 24);
3962 cdb[3] = (u8) (disk_block >> 16);
3963 cdb[4] = (u8) (disk_block >> 8);
3964 cdb[5] = (u8) (disk_block);
3965 cdb[6] = 0;
3966 cdb[7] = (u8) (disk_block_cnt >> 8);
3967 cdb[8] = (u8) (disk_block_cnt);
3968 cdb[9] = 0;
3969 cdb_len = 10;
3970 }
3971 return hpsa_scsi_ioaccel_queue_command(h, c, disk_handle, cdb, cdb_len,
3972 dev->scsi3addr);
3973}
3974
f281233d 3975static int hpsa_scsi_queue_command_lck(struct scsi_cmnd *cmd,
edd16368
SC		 3976 void (*done)(struct scsi_cmnd *))
3977{
3978 struct ctlr_info *h;
3979 struct hpsa_scsi_dev_t *dev;
3980 unsigned char scsi3addr[8];
3981 struct CommandList *c;
283b4a9b 3982 int rc = 0;
edd16368
SC		 3983
3984 /* Get the ptr to our adapter structure out of cmd->host. */
3985 h = sdev_to_hba(cmd->device);
3986 dev = cmd->device->hostdata;
3987 if (!dev) {
3988 cmd->result = DID_NO_CONNECT << 16;
3989 done(cmd);
3990 return 0;
3991 }
3992 memcpy(scsi3addr, dev->scsi3addr, sizeof(scsi3addr));
3993
094963da 3994 if (unlikely(lockup_detected(h))) {
a0c12413
SC		 3995 cmd->result = DID_ERROR << 16;
3996 done(cmd);
3997 return 0;
3998 }
e16a33ad 3999 c = cmd_alloc(h);
edd16368
SC		 4000 if (c == NULL) { /* trouble... */
4001 dev_err(&h->pdev->dev, "cmd_alloc returned NULL!\n");
4002 return SCSI_MLQUEUE_HOST_BUSY;
4003 }
4004
4005 /* Fill in the command list header */
4006
4007 cmd->scsi_done = done; /* save this for use by completion code */
4008
4009 /* save c in case we have to abort it */
4010 cmd->host_scribble = (unsigned char *) c;
4011
4012 c->cmd_type = CMD_SCSI;
4013 c->scsi_cmd = cmd;
e1f7de0c 4014
283b4a9b
SC		 4015 /* Call alternate submit routine for I/O accelerated commands.
4016 * Retries always go down the normal I/O path.
4017 */
4018 if (likely(cmd->retries == 0 &&
da0697bd
ST		 4019 cmd->request->cmd_type == REQ_TYPE_FS &&
4020 h->acciopath_status)) {
283b4a9b
SC		 4021 if (dev->offload_enabled) {
4022 rc = hpsa_scsi_ioaccel_raid_map(h, c);
4023 if (rc == 0)
4024 return 0; /* Sent on ioaccel path */
4025 if (rc < 0) { /* scsi_dma_map failed. */
4026 cmd_free(h, c);
4027 return SCSI_MLQUEUE_HOST_BUSY;
4028 }
4029 } else if (dev->ioaccel_handle) {
4030 rc = hpsa_scsi_ioaccel_direct_map(h, c);
4031 if (rc == 0)
4032 return 0; /* Sent on direct map path */
4033 if (rc < 0) { /* scsi_dma_map failed. */
4034 cmd_free(h, c);
4035 return SCSI_MLQUEUE_HOST_BUSY;
4036 }
4037 }
4038 }
e1f7de0c 4039
edd16368
SC		 4040 c->Header.ReplyQueue = 0; /* unused in simple mode */
4041 memcpy(&c->Header.LUN.LunAddrBytes[0], &scsi3addr[0], 8);
303932fd
DB		 4042 c->Header.Tag.lower = (c->cmdindex << DIRECT_LOOKUP_SHIFT);
4043 c->Header.Tag.lower |= DIRECT_LOOKUP_BIT;
edd16368
SC		 4044
4045 /* Fill in the request block... */
4046
4047 c->Request.Timeout = 0;
4048 memset(c->Request.CDB, 0, sizeof(c->Request.CDB));
4049 BUG_ON(cmd->cmd_len > sizeof(c->Request.CDB));
4050 c->Request.CDBLen = cmd->cmd_len;
4051 memcpy(c->Request.CDB, cmd->cmnd, cmd->cmd_len);
4052 c->Request.Type.Type = TYPE_CMD;
4053 c->Request.Type.Attribute = ATTR_SIMPLE;
4054 switch (cmd->sc_data_direction) {
4055 case DMA_TO_DEVICE:
4056 c->Request.Type.Direction = XFER_WRITE;
4057 break;
4058 case DMA_FROM_DEVICE:
4059 c->Request.Type.Direction = XFER_READ;
4060 break;
4061 case DMA_NONE:
4062 c->Request.Type.Direction = XFER_NONE;
4063 break;
4064 case DMA_BIDIRECTIONAL:
4065 /* This can happen if a buggy application does a scsi passthru
4066 * and sets both inlen and outlen to non-zero. ( see
4067 * ../scsi/scsi_ioctl.c:scsi_ioctl_send_command() )
4068 */
4069
4070 c->Request.Type.Direction = XFER_RSVD;
4071 /* This is technically wrong, and hpsa controllers should
4072 * reject it with CMD_INVALID, which is the most correct
4073 * response, but non-fibre backends appear to let it
4074 * slide by, and give the same results as if this field
4075 * were set correctly. Either way is acceptable for
4076 * our purposes here.
4077 */
4078
4079 break;
4080
4081 default:
4082 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
4083 cmd->sc_data_direction);
4084 BUG();
4085 break;
4086 }
4087
33a2ffce 4088 if (hpsa_scatter_gather(h, c, cmd) < 0) { /* Fill SG list */
edd16368
SC		 4089 cmd_free(h, c);
4090 return SCSI_MLQUEUE_HOST_BUSY;
4091 }
4092 enqueue_cmd_and_start_io(h, c);
4093 /* the cmd'll come back via intr handler in complete_scsi_command() */
4094 return 0;
4095}
4096
f281233d
JG		 4097static DEF_SCSI_QCMD(hpsa_scsi_queue_command)
4098
5f389360
SC		 4099static int do_not_scan_if_controller_locked_up(struct ctlr_info *h)
4100{
4101 unsigned long flags;
4102
4103 /*
4104 * Don't let rescans be initiated on a controller known
4105 * to be locked up. If the controller locks up *during*
4106 * a rescan, that thread is probably hosed, but at least
4107 * we can prevent new rescan threads from piling up on a
4108 * locked up controller.
4109 */
094963da 4110 if (unlikely(lockup_detected(h))) {
5f389360
SC		 4111 spin_lock_irqsave(&h->scan_lock, flags);
4112 h->scan_finished = 1;
4113 wake_up_all(&h->scan_wait_queue);
4114 spin_unlock_irqrestore(&h->scan_lock, flags);
4115 return 1;
4116 }
5f389360
SC		 4117 return 0;
4118}
4119
a08a8471
SC		 4120static void hpsa_scan_start(struct Scsi_Host *sh)
4121{
4122 struct ctlr_info *h = shost_to_hba(sh);
4123 unsigned long flags;
4124
5f389360
SC		 4125 if (do_not_scan_if_controller_locked_up(h))
4126 return;
4127
a08a8471
SC		 4128 /* wait until any scan already in progress is finished. */
4129 while (1) {
4130 spin_lock_irqsave(&h->scan_lock, flags);
4131 if (h->scan_finished)
4132 break;
4133 spin_unlock_irqrestore(&h->scan_lock, flags);
4134 wait_event(h->scan_wait_queue, h->scan_finished);
4135 /* Note: We don't need to worry about a race between this
4136 * thread and driver unload because the midlayer will
4137 * have incremented the reference count, so unload won't
4138 * happen if we're in here.
4139 */
4140 }
4141 h->scan_finished = 0; /* mark scan as in progress */
4142 spin_unlock_irqrestore(&h->scan_lock, flags);
4143
5f389360
SC		 4144 if (do_not_scan_if_controller_locked_up(h))
4145 return;
4146
a08a8471
SC		 4147 hpsa_update_scsi_devices(h, h->scsi_host->host_no);
4148
4149 spin_lock_irqsave(&h->scan_lock, flags);
4150 h->scan_finished = 1; /* mark scan as finished. */
4151 wake_up_all(&h->scan_wait_queue);
4152 spin_unlock_irqrestore(&h->scan_lock, flags);
4153}
4154
4155static int hpsa_scan_finished(struct Scsi_Host *sh,
4156 unsigned long elapsed_time)
4157{
4158 struct ctlr_info *h = shost_to_hba(sh);
4159 unsigned long flags;
4160 int finished;
4161
4162 spin_lock_irqsave(&h->scan_lock, flags);
4163 finished = h->scan_finished;
4164 spin_unlock_irqrestore(&h->scan_lock, flags);
4165 return finished;
4166}
4167
667e23d4
SC		 4168static int hpsa_change_queue_depth(struct scsi_device *sdev,
4169 int qdepth, int reason)
4170{
4171 struct ctlr_info *h = sdev_to_hba(sdev);
4172
4173 if (reason != SCSI_QDEPTH_DEFAULT)
4174 return -ENOTSUPP;
4175
4176 if (qdepth < 1)
4177 qdepth = 1;
4178 else
4179 if (qdepth > h->nr_cmds)
4180 qdepth = h->nr_cmds;
4181 scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth);
4182 return sdev->queue_depth;
4183}
4184
edd16368
SC		 4185static void hpsa_unregister_scsi(struct ctlr_info *h)
4186{
4187 /* we are being forcibly unloaded, and may not refuse. */
4188 scsi_remove_host(h->scsi_host);
4189 scsi_host_put(h->scsi_host);
4190 h->scsi_host = NULL;
4191}
4192
4193static int hpsa_register_scsi(struct ctlr_info *h)
4194{
b705690d
SC		 4195 struct Scsi_Host *sh;
4196 int error;
edd16368 4197
b705690d
SC		 4198 sh = scsi_host_alloc(&hpsa_driver_template, sizeof(h));
4199 if (sh == NULL)
4200 goto fail;
4201
4202 sh->io_port = 0;
4203 sh->n_io_port = 0;
4204 sh->this_id = -1;
4205 sh->max_channel = 3;
4206 sh->max_cmd_len = MAX_COMMAND_SIZE;
4207 sh->max_lun = HPSA_MAX_LUN;
4208 sh->max_id = HPSA_MAX_LUN;
4209 sh->can_queue = h->nr_cmds;
316b221a
SC		 4210 if (h->hba_mode_enabled)
4211 sh->cmd_per_lun = 7;
4212 else
4213 sh->cmd_per_lun = h->nr_cmds;
b705690d
SC		 4214 sh->sg_tablesize = h->maxsgentries;
4215 h->scsi_host = sh;
4216 sh->hostdata[0] = (unsigned long) h;
4217 sh->irq = h->intr[h->intr_mode];
4218 sh->unique_id = sh->irq;
4219 error = scsi_add_host(sh, &h->pdev->dev);
4220 if (error)
4221 goto fail_host_put;
4222 scsi_scan_host(sh);
4223 return 0;
4224
4225 fail_host_put:
4226 dev_err(&h->pdev->dev, "%s: scsi_add_host"
4227 " failed for controller %d\n", __func__, h->ctlr);
4228 scsi_host_put(sh);
4229 return error;
4230 fail:
4231 dev_err(&h->pdev->dev, "%s: scsi_host_alloc"
4232 " failed for controller %d\n", __func__, h->ctlr);
4233 return -ENOMEM;
edd16368
SC		 4234}
4235
4236static int wait_for_device_to_become_ready(struct ctlr_info *h,
4237 unsigned char lunaddr[])
4238{
8919358e 4239 int rc;
edd16368
SC		 4240 int count = 0;
4241 int waittime = 1; /* seconds */
4242 struct CommandList *c;
4243
4244 c = cmd_special_alloc(h);
4245 if (!c) {
4246 dev_warn(&h->pdev->dev, "out of memory in "
4247 "wait_for_device_to_become_ready.\n");
4248 return IO_ERROR;
4249 }
4250
4251 /* Send test unit ready until device ready, or give up. */
4252 while (count < HPSA_TUR_RETRY_LIMIT) {
4253
4254 /* Wait for a bit. do this first, because if we send
4255 * the TUR right away, the reset will just abort it.
4256 */
4257 msleep(1000 * waittime);
4258 count++;
8919358e 4259 rc = 0; /* Device ready. */
edd16368
SC		 4260
4261 /* Increase wait time with each try, up to a point. */
4262 if (waittime < HPSA_MAX_WAIT_INTERVAL_SECS)
4263 waittime = waittime * 2;
4264
a2dac136
SC		 4265 /* Send the Test Unit Ready, fill_cmd can't fail, no mapping */
4266 (void) fill_cmd(c, TEST_UNIT_READY, h,
4267 NULL, 0, 0, lunaddr, TYPE_CMD);
edd16368
SC		 4268 hpsa_scsi_do_simple_cmd_core(h, c);
4269 /* no unmap needed here because no data xfer. */
4270
4271 if (c->err_info->CommandStatus == CMD_SUCCESS)
4272 break;
4273
4274 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
4275 c->err_info->ScsiStatus == SAM_STAT_CHECK_CONDITION &&
4276 (c->err_info->SenseInfo[2] == NO_SENSE ||
4277 c->err_info->SenseInfo[2] == UNIT_ATTENTION))
4278 break;
4279
4280 dev_warn(&h->pdev->dev, "waiting %d secs "
4281 "for device to become ready.\n", waittime);
4282 rc = 1; /* device not ready. */
4283 }
4284
4285 if (rc)
4286 dev_warn(&h->pdev->dev, "giving up on device.\n");
4287 else
4288 dev_warn(&h->pdev->dev, "device is ready.\n");
4289
4290 cmd_special_free(h, c);
4291 return rc;
4292}
4293
4294/* Need at least one of these error handlers to keep ../scsi/hosts.c from
4295 * complaining. Doing a host- or bus-reset can't do anything good here.
4296 */
4297static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd)
4298{
4299 int rc;
4300 struct ctlr_info *h;
4301 struct hpsa_scsi_dev_t *dev;
4302
4303 /* find the controller to which the command to be aborted was sent */
4304 h = sdev_to_hba(scsicmd->device);
4305 if (h == NULL) /* paranoia */
4306 return FAILED;
edd16368
SC		 4307 dev = scsicmd->device->hostdata;
4308 if (!dev) {
4309 dev_err(&h->pdev->dev, "hpsa_eh_device_reset_handler: "
4310 "device lookup failed.\n");
4311 return FAILED;
4312 }
d416b0c7
SC		 4313 dev_warn(&h->pdev->dev, "resetting device %d:%d:%d:%d\n",
4314 h->scsi_host->host_no, dev->bus, dev->target, dev->lun);
edd16368 4315 /* send a reset to the SCSI LUN which the command was sent to */
bf711ac6 4316 rc = hpsa_send_reset(h, dev->scsi3addr, HPSA_RESET_TYPE_LUN);
edd16368
SC		 4317 if (rc == 0 && wait_for_device_to_become_ready(h, dev->scsi3addr) == 0)
4318 return SUCCESS;
4319
4320 dev_warn(&h->pdev->dev, "resetting device failed.\n");
4321 return FAILED;
4322}
4323
6cba3f19
SC		 4324static void swizzle_abort_tag(u8 *tag)
4325{
4326 u8 original_tag[8];
4327
4328 memcpy(original_tag, tag, 8);
4329 tag[0] = original_tag[3];
4330 tag[1] = original_tag[2];
4331 tag[2] = original_tag[1];
4332 tag[3] = original_tag[0];
4333 tag[4] = original_tag[7];
4334 tag[5] = original_tag[6];
4335 tag[6] = original_tag[5];
4336 tag[7] = original_tag[4];
4337}
4338
17eb87d2
ST		 4339static void hpsa_get_tag(struct ctlr_info *h,
4340 struct CommandList *c, u32 *taglower, u32 *tagupper)
4341{
4342 if (c->cmd_type == CMD_IOACCEL1) {
4343 struct io_accel1_cmd *cm1 = (struct io_accel1_cmd *)
4344 &h->ioaccel_cmd_pool[c->cmdindex];
4345 *tagupper = cm1->Tag.upper;
4346 *taglower = cm1->Tag.lower;
54b6e9e9
ST		 4347 return;
4348 }
4349 if (c->cmd_type == CMD_IOACCEL2) {
4350 struct io_accel2_cmd *cm2 = (struct io_accel2_cmd *)
4351 &h->ioaccel2_cmd_pool[c->cmdindex];
dd0e19f3
ST		 4352 /* upper tag not used in ioaccel2 mode */
4353 memset(tagupper, 0, sizeof(*tagupper));
4354 *taglower = cm2->Tag;
54b6e9e9 4355 return;
17eb87d2 4356 }
54b6e9e9
ST		 4357 *tagupper = c->Header.Tag.upper;
4358 *taglower = c->Header.Tag.lower;
17eb87d2
ST		 4359}
4360
54b6e9e9 4361
75167d2c 4362static int hpsa_send_abort(struct ctlr_info *h, unsigned char *scsi3addr,
6cba3f19 4363 struct CommandList *abort, int swizzle)
75167d2c
SC		 4364{
4365 int rc = IO_OK;
4366 struct CommandList *c;
4367 struct ErrorInfo *ei;
17eb87d2 4368 u32 tagupper, taglower;
75167d2c
SC		 4369
4370 c = cmd_special_alloc(h);
4371 if (c == NULL) { /* trouble... */
4372 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
4373 return -ENOMEM;
4374 }
4375
a2dac136
SC		 4376 /* fill_cmd can't fail here, no buffer to map */
4377 (void) fill_cmd(c, HPSA_ABORT_MSG, h, abort,
4378 0, 0, scsi3addr, TYPE_MSG);
6cba3f19
SC		 4379 if (swizzle)
4380 swizzle_abort_tag(&c->Request.CDB[4]);
75167d2c 4381 hpsa_scsi_do_simple_cmd_core(h, c);
17eb87d2 4382 hpsa_get_tag(h, abort, &taglower, &tagupper);
75167d2c 4383 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: do_simple_cmd_core completed.\n",
17eb87d2 4384 __func__, tagupper, taglower);
75167d2c
SC		 4385 /* no unmap needed here because no data xfer. */
4386
4387 ei = c->err_info;
4388 switch (ei->CommandStatus) {
4389 case CMD_SUCCESS:
4390 break;
4391 case CMD_UNABORTABLE: /* Very common, don't make noise. */
4392 rc = -1;
4393 break;
4394 default:
4395 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: interpreting error.\n",
17eb87d2 4396 __func__, tagupper, taglower);
d1e8beac 4397 hpsa_scsi_interpret_error(h, c);
75167d2c
SC		 4398 rc = -1;
4399 break;
4400 }
4401 cmd_special_free(h, c);
dd0e19f3
ST		 4402 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n",
4403 __func__, tagupper, taglower);
75167d2c
SC		 4404 return rc;
4405}
4406
4407/*
4408 * hpsa_find_cmd_in_queue
4409 *
4410 * Used to determine whether a command (find) is still present
4411 * in queue_head. Optionally excludes the last element of queue_head.
4412 *
4413 * This is used to avoid unnecessary aborts. Commands in h->reqQ have
4414 * not yet been submitted, and so can be aborted by the driver without
4415 * sending an abort to the hardware.
4416 *
4417 * Returns pointer to command if found in queue, NULL otherwise.
4418 */
4419static struct CommandList *hpsa_find_cmd_in_queue(struct ctlr_info *h,
4420 struct scsi_cmnd *find, struct list_head *queue_head)
4421{
4422 unsigned long flags;
4423 struct CommandList *c = NULL; /* ptr into cmpQ */
4424
4425 if (!find)
4426 return 0;
4427 spin_lock_irqsave(&h->lock, flags);
4428 list_for_each_entry(c, queue_head, list) {
4429 if (c->scsi_cmd == NULL) /* e.g.: passthru ioctl */
4430 continue;
4431 if (c->scsi_cmd == find) {
4432 spin_unlock_irqrestore(&h->lock, flags);
4433 return c;
4434 }
4435 }
4436 spin_unlock_irqrestore(&h->lock, flags);
4437 return NULL;
4438}
4439
6cba3f19
SC		 4440static struct CommandList *hpsa_find_cmd_in_queue_by_tag(struct ctlr_info *h,
4441 u8 *tag, struct list_head *queue_head)
4442{
4443 unsigned long flags;
4444 struct CommandList *c;
4445
4446 spin_lock_irqsave(&h->lock, flags);
4447 list_for_each_entry(c, queue_head, list) {
4448 if (memcmp(&c->Header.Tag, tag, 8) != 0)
4449 continue;
4450 spin_unlock_irqrestore(&h->lock, flags);
4451 return c;
4452 }
4453 spin_unlock_irqrestore(&h->lock, flags);
4454 return NULL;
4455}
4456
54b6e9e9
ST		 4457/* ioaccel2 path firmware cannot handle abort task requests.
4458 * Change abort requests to physical target reset, and send to the
4459 * address of the physical disk used for the ioaccel 2 command.
4460 * Return 0 on success (IO_OK)
4461 * -1 on failure
4462 */
4463
4464static int hpsa_send_reset_as_abort_ioaccel2(struct ctlr_info *h,
4465 unsigned char *scsi3addr, struct CommandList *abort)
4466{
4467 int rc = IO_OK;
4468 struct scsi_cmnd *scmd; /* scsi command within request being aborted */
4469 struct hpsa_scsi_dev_t *dev; /* device to which scsi cmd was sent */
4470 unsigned char phys_scsi3addr[8]; /* addr of phys disk with volume */
4471 unsigned char *psa = &phys_scsi3addr[0];
4472
4473 /* Get a pointer to the hpsa logical device. */
4474 scmd = (struct scsi_cmnd *) abort->scsi_cmd;
4475 dev = (struct hpsa_scsi_dev_t *)(scmd->device->hostdata);
4476 if (dev == NULL) {
4477 dev_warn(&h->pdev->dev,
4478 "Cannot abort: no device pointer for command.\n");
4479 return -1; /* not abortable */
4480 }
4481
2ba8bfc8
SC		 4482 if (h->raid_offload_debug > 0)
4483 dev_info(&h->pdev->dev,
4484 "Reset as abort: Abort requested on C%d:B%d:T%d:L%d scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4485 h->scsi_host->host_no, dev->bus, dev->target, dev->lun,
4486 scsi3addr[0], scsi3addr[1], scsi3addr[2], scsi3addr[3],
4487 scsi3addr[4], scsi3addr[5], scsi3addr[6], scsi3addr[7]);
4488
54b6e9e9
ST		 4489 if (!dev->offload_enabled) {
4490 dev_warn(&h->pdev->dev,
4491 "Can't abort: device is not operating in HP SSD Smart Path mode.\n");
4492 return -1; /* not abortable */
4493 }
4494
4495 /* Incoming scsi3addr is logical addr. We need physical disk addr. */
4496 if (!hpsa_get_pdisk_of_ioaccel2(h, abort, psa)) {
4497 dev_warn(&h->pdev->dev, "Can't abort: Failed lookup of physical address.\n");
4498 return -1; /* not abortable */
4499 }
4500
4501 /* send the reset */
2ba8bfc8
SC		 4502 if (h->raid_offload_debug > 0)
4503 dev_info(&h->pdev->dev,
4504 "Reset as abort: Resetting physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4505 psa[0], psa[1], psa[2], psa[3],
4506 psa[4], psa[5], psa[6], psa[7]);
54b6e9e9
ST		 4507 rc = hpsa_send_reset(h, psa, HPSA_RESET_TYPE_TARGET);
4508 if (rc != 0) {
4509 dev_warn(&h->pdev->dev,
4510 "Reset as abort: Failed on physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4511 psa[0], psa[1], psa[2], psa[3],
4512 psa[4], psa[5], psa[6], psa[7]);
4513 return rc; /* failed to reset */
4514 }
4515
4516 /* wait for device to recover */
4517 if (wait_for_device_to_become_ready(h, psa) != 0) {
4518 dev_warn(&h->pdev->dev,
4519 "Reset as abort: Failed: Device never recovered from reset: 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4520 psa[0], psa[1], psa[2], psa[3],
4521 psa[4], psa[5], psa[6], psa[7]);
4522 return -1; /* failed to recover */
4523 }
4524
4525 /* device recovered */
4526 dev_info(&h->pdev->dev,
4527 "Reset as abort: Device recovered from reset: scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4528 psa[0], psa[1], psa[2], psa[3],
4529 psa[4], psa[5], psa[6], psa[7]);
4530
4531 return rc; /* success */
4532}
4533
6cba3f19
SC		 4534/* Some Smart Arrays need the abort tag swizzled, and some don't. It's hard to
4535 * tell which kind we're dealing with, so we send the abort both ways. There
4536 * shouldn't be any collisions between swizzled and unswizzled tags due to the
4537 * way we construct our tags but we check anyway in case the assumptions which
4538 * make this true someday become false.
4539 */
4540static int hpsa_send_abort_both_ways(struct ctlr_info *h,
4541 unsigned char *scsi3addr, struct CommandList *abort)
4542{
4543 u8 swizzled_tag[8];
4544 struct CommandList *c;
4545 int rc = 0, rc2 = 0;
4546
54b6e9e9
ST		 4547 /* ioccelerator mode 2 commands should be aborted via the
4548 * accelerated path, since RAID path is unaware of these commands,
4549 * but underlying firmware can't handle abort TMF.
4550 * Change abort to physical device reset.
4551 */
4552 if (abort->cmd_type == CMD_IOACCEL2)
4553 return hpsa_send_reset_as_abort_ioaccel2(h, scsi3addr, abort);
4554
6cba3f19
SC		 4555 /* we do not expect to find the swizzled tag in our queue, but
4556 * check anyway just to be sure the assumptions which make this
4557 * the case haven't become wrong.
4558 */
4559 memcpy(swizzled_tag, &abort->Request.CDB[4], 8);
4560 swizzle_abort_tag(swizzled_tag);
4561 c = hpsa_find_cmd_in_queue_by_tag(h, swizzled_tag, &h->cmpQ);
4562 if (c != NULL) {
4563 dev_warn(&h->pdev->dev, "Unexpectedly found byte-swapped tag in completion queue.\n");
4564 return hpsa_send_abort(h, scsi3addr, abort, 0);
4565 }
4566 rc = hpsa_send_abort(h, scsi3addr, abort, 0);
4567
4568 /* if the command is still in our queue, we can't conclude that it was
4569 * aborted (it might have just completed normally) but in any case
4570 * we don't need to try to abort it another way.
4571 */
4572 c = hpsa_find_cmd_in_queue(h, abort->scsi_cmd, &h->cmpQ);
4573 if (c)
4574 rc2 = hpsa_send_abort(h, scsi3addr, abort, 1);
4575 return rc && rc2;
4576}
4577
75167d2c
SC		 4578/* Send an abort for the specified command.
4579 * If the device and controller support it,
4580 * send a task abort request.
4581 */
4582static int hpsa_eh_abort_handler(struct scsi_cmnd *sc)
4583{
4584
4585 int i, rc;
4586 struct ctlr_info *h;
4587 struct hpsa_scsi_dev_t *dev;
4588 struct CommandList *abort; /* pointer to command to be aborted */
4589 struct CommandList *found;
4590 struct scsi_cmnd *as; /* ptr to scsi cmd inside aborted command. */
4591 char msg[256]; /* For debug messaging. */
4592 int ml = 0;
17eb87d2 4593 u32 tagupper, taglower;
75167d2c
SC		 4594
4595 /* Find the controller of the command to be aborted */
4596 h = sdev_to_hba(sc->device);
4597 if (WARN(h == NULL,
4598 "ABORT REQUEST FAILED, Controller lookup failed.\n"))
4599 return FAILED;
4600
4601 /* Check that controller supports some kind of task abort */
4602 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags) &&
4603 !(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
4604 return FAILED;
4605
4606 memset(msg, 0, sizeof(msg));
4607 ml += sprintf(msg+ml, "ABORT REQUEST on C%d:B%d:T%d:L%d ",
4608 h->scsi_host->host_no, sc->device->channel,
4609 sc->device->id, sc->device->lun);
4610
4611 /* Find the device of the command to be aborted */
4612 dev = sc->device->hostdata;
4613 if (!dev) {
4614 dev_err(&h->pdev->dev, "%s FAILED, Device lookup failed.\n",
4615 msg);
4616 return FAILED;
4617 }
4618
4619 /* Get SCSI command to be aborted */
4620 abort = (struct CommandList *) sc->host_scribble;
4621 if (abort == NULL) {
4622 dev_err(&h->pdev->dev, "%s FAILED, Command to abort is NULL.\n",
4623 msg);
4624 return FAILED;
4625 }
17eb87d2
ST		 4626 hpsa_get_tag(h, abort, &taglower, &tagupper);
4627 ml += sprintf(msg+ml, "Tag:0x%08x:%08x ", tagupper, taglower);
75167d2c
SC		 4628 as = (struct scsi_cmnd *) abort->scsi_cmd;
4629 if (as != NULL)
4630 ml += sprintf(msg+ml, "Command:0x%x SN:0x%lx ",
4631 as->cmnd[0], as->serial_number);
4632 dev_dbg(&h->pdev->dev, "%s\n", msg);
4633 dev_warn(&h->pdev->dev, "Abort request on C%d:B%d:T%d:L%d\n",
4634 h->scsi_host->host_no, dev->bus, dev->target, dev->lun);
4635
4636 /* Search reqQ to See if command is queued but not submitted,
4637 * if so, complete the command with aborted status and remove
4638 * it from the reqQ.
4639 */
4640 found = hpsa_find_cmd_in_queue(h, sc, &h->reqQ);
4641 if (found) {
4642 found->err_info->CommandStatus = CMD_ABORTED;
4643 finish_cmd(found);
4644 dev_info(&h->pdev->dev, "%s Request SUCCEEDED (driver queue).\n",
4645 msg);
4646 return SUCCESS;
4647 }
4648
4649 /* not in reqQ, if also not in cmpQ, must have already completed */
4650 found = hpsa_find_cmd_in_queue(h, sc, &h->cmpQ);
4651 if (!found) {
d6ebd0f7 4652 dev_dbg(&h->pdev->dev, "%s Request SUCCEEDED (not known to driver).\n",
75167d2c
SC		 4653 msg);
4654 return SUCCESS;
4655 }
4656
4657 /*
4658 * Command is in flight, or possibly already completed
4659 * by the firmware (but not to the scsi mid layer) but we can't
4660 * distinguish which. Send the abort down.
4661 */
6cba3f19 4662 rc = hpsa_send_abort_both_ways(h, dev->scsi3addr, abort);
75167d2c
SC		 4663 if (rc != 0) {
4664 dev_dbg(&h->pdev->dev, "%s Request FAILED.\n", msg);
4665 dev_warn(&h->pdev->dev, "FAILED abort on device C%d:B%d:T%d:L%d\n",
4666 h->scsi_host->host_no,
4667 dev->bus, dev->target, dev->lun);
4668 return FAILED;
4669 }
4670 dev_info(&h->pdev->dev, "%s REQUEST SUCCEEDED.\n", msg);
4671
4672 /* If the abort(s) above completed and actually aborted the
4673 * command, then the command to be aborted should already be
4674 * completed. If not, wait around a bit more to see if they
4675 * manage to complete normally.
4676 */
4677#define ABORT_COMPLETE_WAIT_SECS 30
4678 for (i = 0; i < ABORT_COMPLETE_WAIT_SECS * 10; i++) {
4679 found = hpsa_find_cmd_in_queue(h, sc, &h->cmpQ);
4680 if (!found)
4681 return SUCCESS;
4682 msleep(100);
4683 }
4684 dev_warn(&h->pdev->dev, "%s FAILED. Aborted command has not completed after %d seconds.\n",
4685 msg, ABORT_COMPLETE_WAIT_SECS);
4686 return FAILED;
4687}
4688
4689
edd16368
SC		 4690/*
4691 * For operations that cannot sleep, a command block is allocated at init,
4692 * and managed by cmd_alloc() and cmd_free() using a simple bitmap to track
4693 * which ones are free or in use. Lock must be held when calling this.
4694 * cmd_free() is the complement.
4695 */
4696static struct CommandList *cmd_alloc(struct ctlr_info *h)
4697{
4698 struct CommandList *c;
4699 int i;
4700 union u64bit temp64;
4701 dma_addr_t cmd_dma_handle, err_dma_handle;
e16a33ad 4702 unsigned long flags;
edd16368 4703
e16a33ad 4704 spin_lock_irqsave(&h->lock, flags);
edd16368
SC		 4705 do {
4706 i = find_first_zero_bit(h->cmd_pool_bits, h->nr_cmds);
e16a33ad
MG		 4707 if (i == h->nr_cmds) {
4708 spin_unlock_irqrestore(&h->lock, flags);
edd16368 4709 return NULL;
e16a33ad 4710 }
edd16368
SC		 4711 } while (test_and_set_bit
4712 (i & (BITS_PER_LONG - 1),
4713 h->cmd_pool_bits + (i / BITS_PER_LONG)) != 0);
e16a33ad
MG		 4714 spin_unlock_irqrestore(&h->lock, flags);
4715
edd16368
SC		 4716 c = h->cmd_pool + i;
4717 memset(c, 0, sizeof(*c));
4718 cmd_dma_handle = h->cmd_pool_dhandle
4719 + i * sizeof(*c);
4720 c->err_info = h->errinfo_pool + i;
4721 memset(c->err_info, 0, sizeof(*c->err_info));
4722 err_dma_handle = h->errinfo_pool_dhandle
4723 + i * sizeof(*c->err_info);
edd16368
SC		 4724
4725 c->cmdindex = i;
4726
9e0fc764 4727 INIT_LIST_HEAD(&c->list);
01a02ffc
SC		 4728 c->busaddr = (u32) cmd_dma_handle;
4729 temp64.val = (u64) err_dma_handle;
edd16368
SC		 4730 c->ErrDesc.Addr.lower = temp64.val32.lower;
4731 c->ErrDesc.Addr.upper = temp64.val32.upper;
4732 c->ErrDesc.Len = sizeof(*c->err_info);
4733
4734 c->h = h;
4735 return c;
4736}
4737
4738/* For operations that can wait for kmalloc to possibly sleep,
4739 * this routine can be called. Lock need not be held to call
4740 * cmd_special_alloc. cmd_special_free() is the complement.
4741 */
4742static struct CommandList *cmd_special_alloc(struct ctlr_info *h)
4743{
4744 struct CommandList *c;
4745 union u64bit temp64;
4746 dma_addr_t cmd_dma_handle, err_dma_handle;
4747
4748 c = pci_alloc_consistent(h->pdev, sizeof(*c), &cmd_dma_handle);
4749 if (c == NULL)
4750 return NULL;
4751 memset(c, 0, sizeof(*c));
4752
e1f7de0c 4753 c->cmd_type = CMD_SCSI;
edd16368
SC		 4754 c->cmdindex = -1;
4755
4756 c->err_info = pci_alloc_consistent(h->pdev, sizeof(*c->err_info),
4757 &err_dma_handle);
4758
4759 if (c->err_info == NULL) {
4760 pci_free_consistent(h->pdev,
4761 sizeof(*c), c, cmd_dma_handle);
4762 return NULL;
4763 }
4764 memset(c->err_info, 0, sizeof(*c->err_info));
4765
9e0fc764 4766 INIT_LIST_HEAD(&c->list);
01a02ffc
SC		 4767 c->busaddr = (u32) cmd_dma_handle;
4768 temp64.val = (u64) err_dma_handle;
edd16368
SC		 4769 c->ErrDesc.Addr.lower = temp64.val32.lower;
4770 c->ErrDesc.Addr.upper = temp64.val32.upper;
4771 c->ErrDesc.Len = sizeof(*c->err_info);
4772
4773 c->h = h;
4774 return c;
4775}
4776
4777static void cmd_free(struct ctlr_info *h, struct CommandList *c)
4778{
4779 int i;
e16a33ad 4780 unsigned long flags;
edd16368
SC		 4781
4782 i = c - h->cmd_pool;
e16a33ad 4783 spin_lock_irqsave(&h->lock, flags);
edd16368
SC		 4784 clear_bit(i & (BITS_PER_LONG - 1),
4785 h->cmd_pool_bits + (i / BITS_PER_LONG));
e16a33ad 4786 spin_unlock_irqrestore(&h->lock, flags);
edd16368
SC		 4787}
4788
4789static void cmd_special_free(struct ctlr_info *h, struct CommandList *c)
4790{
4791 union u64bit temp64;
4792
4793 temp64.val32.lower = c->ErrDesc.Addr.lower;
4794 temp64.val32.upper = c->ErrDesc.Addr.upper;
4795 pci_free_consistent(h->pdev, sizeof(*c->err_info),
4796 c->err_info, (dma_addr_t) temp64.val);
4797 pci_free_consistent(h->pdev, sizeof(*c),
d896f3f3 4798 c, (dma_addr_t) (c->busaddr & DIRECT_LOOKUP_MASK));
edd16368
SC		 4799}
4800
4801#ifdef CONFIG_COMPAT
4802
edd16368
SC		 4803static int hpsa_ioctl32_passthru(struct scsi_device *dev, int cmd, void *arg)
4804{
4805 IOCTL32_Command_struct __user *arg32 =
4806 (IOCTL32_Command_struct __user *) arg;
4807 IOCTL_Command_struct arg64;
4808 IOCTL_Command_struct __user *p = compat_alloc_user_space(sizeof(arg64));
4809 int err;
4810 u32 cp;
4811
938abd84 4812 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 4813 err = 0;
4814 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
4815 sizeof(arg64.LUN_info));
4816 err |= copy_from_user(&arg64.Request, &arg32->Request,
4817 sizeof(arg64.Request));
4818 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
4819 sizeof(arg64.error_info));
4820 err |= get_user(arg64.buf_size, &arg32->buf_size);
4821 err |= get_user(cp, &arg32->buf);
4822 arg64.buf = compat_ptr(cp);
4823 err |= copy_to_user(p, &arg64, sizeof(arg64));
4824
4825 if (err)
4826 return -EFAULT;
4827
e39eeaed 4828 err = hpsa_ioctl(dev, CCISS_PASSTHRU, (void *)p);
edd16368
SC		 4829 if (err)
4830 return err;
4831 err |= copy_in_user(&arg32->error_info, &p->error_info,
4832 sizeof(arg32->error_info));
4833 if (err)
4834 return -EFAULT;
4835 return err;
4836}
4837
4838static int hpsa_ioctl32_big_passthru(struct scsi_device *dev,
4839 int cmd, void *arg)
4840{
4841 BIG_IOCTL32_Command_struct __user *arg32 =
4842 (BIG_IOCTL32_Command_struct __user *) arg;
4843 BIG_IOCTL_Command_struct arg64;
4844 BIG_IOCTL_Command_struct __user *p =
4845 compat_alloc_user_space(sizeof(arg64));
4846 int err;
4847 u32 cp;
4848
938abd84 4849 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 4850 err = 0;
4851 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
4852 sizeof(arg64.LUN_info));
4853 err |= copy_from_user(&arg64.Request, &arg32->Request,
4854 sizeof(arg64.Request));
4855 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
4856 sizeof(arg64.error_info));
4857 err |= get_user(arg64.buf_size, &arg32->buf_size);
4858 err |= get_user(arg64.malloc_size, &arg32->malloc_size);
4859 err |= get_user(cp, &arg32->buf);
4860 arg64.buf = compat_ptr(cp);
4861 err |= copy_to_user(p, &arg64, sizeof(arg64));
4862
4863 if (err)
4864 return -EFAULT;
4865
e39eeaed 4866 err = hpsa_ioctl(dev, CCISS_BIG_PASSTHRU, (void *)p);
edd16368
SC		 4867 if (err)
4868 return err;
4869 err |= copy_in_user(&arg32->error_info, &p->error_info,
4870 sizeof(arg32->error_info));
4871 if (err)
4872 return -EFAULT;
4873 return err;
4874}
71fe75a7
SC		 4875
4876static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void *arg)
4877{
4878 switch (cmd) {
4879 case CCISS_GETPCIINFO:
4880 case CCISS_GETINTINFO:
4881 case CCISS_SETINTINFO:
4882 case CCISS_GETNODENAME:
4883 case CCISS_SETNODENAME:
4884 case CCISS_GETHEARTBEAT:
4885 case CCISS_GETBUSTYPES:
4886 case CCISS_GETFIRMVER:
4887 case CCISS_GETDRIVVER:
4888 case CCISS_REVALIDVOLS:
4889 case CCISS_DEREGDISK:
4890 case CCISS_REGNEWDISK:
4891 case CCISS_REGNEWD:
4892 case CCISS_RESCANDISK:
4893 case CCISS_GETLUNINFO:
4894 return hpsa_ioctl(dev, cmd, arg);
4895
4896 case CCISS_PASSTHRU32:
4897 return hpsa_ioctl32_passthru(dev, cmd, arg);
4898 case CCISS_BIG_PASSTHRU32:
4899 return hpsa_ioctl32_big_passthru(dev, cmd, arg);
4900
4901 default:
4902 return -ENOIOCTLCMD;
4903 }
4904}
edd16368
SC		 4905#endif
4906
4907static int hpsa_getpciinfo_ioctl(struct ctlr_info *h, void __user *argp)
4908{
4909 struct hpsa_pci_info pciinfo;
4910
4911 if (!argp)
4912 return -EINVAL;
4913 pciinfo.domain = pci_domain_nr(h->pdev->bus);
4914 pciinfo.bus = h->pdev->bus->number;
4915 pciinfo.dev_fn = h->pdev->devfn;
4916 pciinfo.board_id = h->board_id;
4917 if (copy_to_user(argp, &pciinfo, sizeof(pciinfo)))
4918 return -EFAULT;
4919 return 0;
4920}
4921
4922static int hpsa_getdrivver_ioctl(struct ctlr_info *h, void __user *argp)
4923{
4924 DriverVer_type DriverVer;
4925 unsigned char vmaj, vmin, vsubmin;
4926 int rc;
4927
4928 rc = sscanf(HPSA_DRIVER_VERSION, "%hhu.%hhu.%hhu",
4929 &vmaj, &vmin, &vsubmin);
4930 if (rc != 3) {
4931 dev_info(&h->pdev->dev, "driver version string '%s' "
4932 "unrecognized.", HPSA_DRIVER_VERSION);
4933 vmaj = 0;
4934 vmin = 0;
4935 vsubmin = 0;
4936 }
4937 DriverVer = (vmaj << 16) | (vmin << 8) | vsubmin;
4938 if (!argp)
4939 return -EINVAL;
4940 if (copy_to_user(argp, &DriverVer, sizeof(DriverVer_type)))
4941 return -EFAULT;
4942 return 0;
4943}
4944
4945static int hpsa_passthru_ioctl(struct ctlr_info *h, void __user *argp)
4946{
4947 IOCTL_Command_struct iocommand;
4948 struct CommandList *c;
4949 char *buff = NULL;
4950 union u64bit temp64;
c1f63c8f 4951 int rc = 0;
edd16368
SC		 4952
4953 if (!argp)
4954 return -EINVAL;
4955 if (!capable(CAP_SYS_RAWIO))
4956 return -EPERM;
4957 if (copy_from_user(&iocommand, argp, sizeof(iocommand)))
4958 return -EFAULT;
4959 if ((iocommand.buf_size < 1) &&
4960 (iocommand.Request.Type.Direction != XFER_NONE)) {
4961 return -EINVAL;
4962 }
4963 if (iocommand.buf_size > 0) {
4964 buff = kmalloc(iocommand.buf_size, GFP_KERNEL);
4965 if (buff == NULL)
4966 return -EFAULT;
9233fb10 4967 if (iocommand.Request.Type.Direction & XFER_WRITE) {
b03a7771
SC		 4968 /* Copy the data into the buffer we created */
4969 if (copy_from_user(buff, iocommand.buf,
4970 iocommand.buf_size)) {
c1f63c8f
SC		 4971 rc = -EFAULT;
4972 goto out_kfree;
b03a7771
SC		 4973 }
4974 } else {
4975 memset(buff, 0, iocommand.buf_size);
edd16368 4976 }
b03a7771 4977 }
edd16368
SC		 4978 c = cmd_special_alloc(h);
4979 if (c == NULL) {
c1f63c8f
SC		 4980 rc = -ENOMEM;
4981 goto out_kfree;
edd16368
SC		 4982 }
4983 /* Fill in the command type */
4984 c->cmd_type = CMD_IOCTL_PEND;
4985 /* Fill in Command Header */
4986 c->Header.ReplyQueue = 0; /* unused in simple mode */
4987 if (iocommand.buf_size > 0) { /* buffer to fill */
4988 c->Header.SGList = 1;
4989 c->Header.SGTotal = 1;
4990 } else { /* no buffers to fill */
4991 c->Header.SGList = 0;
4992 c->Header.SGTotal = 0;
4993 }
4994 memcpy(&c->Header.LUN, &iocommand.LUN_info, sizeof(c->Header.LUN));
4995 /* use the kernel address the cmd block for tag */
4996 c->Header.Tag.lower = c->busaddr;
4997
4998 /* Fill in Request block */
4999 memcpy(&c->Request, &iocommand.Request,
5000 sizeof(c->Request));
5001
5002 /* Fill in the scatter gather information */
5003 if (iocommand.buf_size > 0) {
5004 temp64.val = pci_map_single(h->pdev, buff,
5005 iocommand.buf_size, PCI_DMA_BIDIRECTIONAL);
bcc48ffa
SC		 5006 if (dma_mapping_error(&h->pdev->dev, temp64.val)) {
5007 c->SG[0].Addr.lower = 0;
5008 c->SG[0].Addr.upper = 0;
5009 c->SG[0].Len = 0;
5010 rc = -ENOMEM;
5011 goto out;
5012 }
edd16368
SC		 5013 c->SG[0].Addr.lower = temp64.val32.lower;
5014 c->SG[0].Addr.upper = temp64.val32.upper;
5015 c->SG[0].Len = iocommand.buf_size;
e1d9cbfa 5016 c->SG[0].Ext = HPSA_SG_LAST; /* we are not chaining*/
edd16368 5017 }
a0c12413 5018 hpsa_scsi_do_simple_cmd_core_if_no_lockup(h, c);
c2dd32e0
SC		 5019 if (iocommand.buf_size > 0)
5020 hpsa_pci_unmap(h->pdev, c, 1, PCI_DMA_BIDIRECTIONAL);
edd16368
SC		 5021 check_ioctl_unit_attention(h, c);
5022
5023 /* Copy the error information out */
5024 memcpy(&iocommand.error_info, c->err_info,
5025 sizeof(iocommand.error_info));
5026 if (copy_to_user(argp, &iocommand, sizeof(iocommand))) {
c1f63c8f
SC		 5027 rc = -EFAULT;
5028 goto out;
edd16368 5029 }
9233fb10 5030 if ((iocommand.Request.Type.Direction & XFER_READ) &&
b03a7771 5031 iocommand.buf_size > 0) {
edd16368
SC		 5032 /* Copy the data out of the buffer we created */
5033 if (copy_to_user(iocommand.buf, buff, iocommand.buf_size)) {
c1f63c8f
SC		 5034 rc = -EFAULT;
5035 goto out;
edd16368
SC		 5036 }
5037 }
c1f63c8f 5038out:
edd16368 5039 cmd_special_free(h, c);
c1f63c8f
SC		 5040out_kfree:
5041 kfree(buff);
5042 return rc;
edd16368
SC		 5043}
5044
5045static int hpsa_big_passthru_ioctl(struct ctlr_info *h, void __user *argp)
5046{
5047 BIG_IOCTL_Command_struct *ioc;
5048 struct CommandList *c;
5049 unsigned char **buff = NULL;
5050 int *buff_size = NULL;
5051 union u64bit temp64;
5052 BYTE sg_used = 0;
5053 int status = 0;
5054 int i;
01a02ffc
SC		 5055 u32 left;
5056 u32 sz;
edd16368
SC		 5057 BYTE __user *data_ptr;
5058
5059 if (!argp)
5060 return -EINVAL;
5061 if (!capable(CAP_SYS_RAWIO))
5062 return -EPERM;
5063 ioc = (BIG_IOCTL_Command_struct *)
5064 kmalloc(sizeof(*ioc), GFP_KERNEL);
5065 if (!ioc) {
5066 status = -ENOMEM;
5067 goto cleanup1;
5068 }
5069 if (copy_from_user(ioc, argp, sizeof(*ioc))) {
5070 status = -EFAULT;
5071 goto cleanup1;
5072 }
5073 if ((ioc->buf_size < 1) &&
5074 (ioc->Request.Type.Direction != XFER_NONE)) {
5075 status = -EINVAL;
5076 goto cleanup1;
5077 }
5078 /* Check kmalloc limits using all SGs */
5079 if (ioc->malloc_size > MAX_KMALLOC_SIZE) {
5080 status = -EINVAL;
5081 goto cleanup1;
5082 }
d66ae08b 5083 if (ioc->buf_size > ioc->malloc_size * SG_ENTRIES_IN_CMD) {
edd16368
SC		 5084 status = -EINVAL;
5085 goto cleanup1;
5086 }
d66ae08b 5087 buff = kzalloc(SG_ENTRIES_IN_CMD * sizeof(char *), GFP_KERNEL);
edd16368
SC		 5088 if (!buff) {
5089 status = -ENOMEM;
5090 goto cleanup1;
5091 }
d66ae08b 5092 buff_size = kmalloc(SG_ENTRIES_IN_CMD * sizeof(int), GFP_KERNEL);
edd16368
SC		 5093 if (!buff_size) {
5094 status = -ENOMEM;
5095 goto cleanup1;
5096 }
5097 left = ioc->buf_size;
5098 data_ptr = ioc->buf;
5099 while (left) {
5100 sz = (left > ioc->malloc_size) ? ioc->malloc_size : left;
5101 buff_size[sg_used] = sz;
5102 buff[sg_used] = kmalloc(sz, GFP_KERNEL);
5103 if (buff[sg_used] == NULL) {
5104 status = -ENOMEM;
5105 goto cleanup1;
5106 }
9233fb10 5107 if (ioc->Request.Type.Direction & XFER_WRITE) {
edd16368
SC		 5108 if (copy_from_user(buff[sg_used], data_ptr, sz)) {
5109 status = -ENOMEM;
5110 goto cleanup1;
5111 }
5112 } else
5113 memset(buff[sg_used], 0, sz);
5114 left -= sz;
5115 data_ptr += sz;
5116 sg_used++;
5117 }
5118 c = cmd_special_alloc(h);
5119 if (c == NULL) {
5120 status = -ENOMEM;
5121 goto cleanup1;
5122 }
5123 c->cmd_type = CMD_IOCTL_PEND;
5124 c->Header.ReplyQueue = 0;
b03a7771 5125 c->Header.SGList = c->Header.SGTotal = sg_used;
edd16368
SC		 5126 memcpy(&c->Header.LUN, &ioc->LUN_info, sizeof(c->Header.LUN));
5127 c->Header.Tag.lower = c->busaddr;
5128 memcpy(&c->Request, &ioc->Request, sizeof(c->Request));
5129 if (ioc->buf_size > 0) {
5130 int i;
5131 for (i = 0; i < sg_used; i++) {
5132 temp64.val = pci_map_single(h->pdev, buff[i],
5133 buff_size[i], PCI_DMA_BIDIRECTIONAL);
bcc48ffa
SC		 5134 if (dma_mapping_error(&h->pdev->dev, temp64.val)) {
5135 c->SG[i].Addr.lower = 0;
5136 c->SG[i].Addr.upper = 0;
5137 c->SG[i].Len = 0;
5138 hpsa_pci_unmap(h->pdev, c, i,
5139 PCI_DMA_BIDIRECTIONAL);
5140 status = -ENOMEM;
e2d4a1f6 5141 goto cleanup0;
bcc48ffa 5142 }
edd16368
SC		 5143 c->SG[i].Addr.lower = temp64.val32.lower;
5144 c->SG[i].Addr.upper = temp64.val32.upper;
5145 c->SG[i].Len = buff_size[i];
e1d9cbfa 5146 c->SG[i].Ext = i < sg_used - 1 ? 0 : HPSA_SG_LAST;
edd16368
SC		 5147 }
5148 }
a0c12413 5149 hpsa_scsi_do_simple_cmd_core_if_no_lockup(h, c);
b03a7771
SC		 5150 if (sg_used)
5151 hpsa_pci_unmap(h->pdev, c, sg_used, PCI_DMA_BIDIRECTIONAL);
edd16368
SC		 5152 check_ioctl_unit_attention(h, c);
5153 /* Copy the error information out */
5154 memcpy(&ioc->error_info, c->err_info, sizeof(ioc->error_info));
5155 if (copy_to_user(argp, ioc, sizeof(*ioc))) {
edd16368 5156 status = -EFAULT;
e2d4a1f6 5157 goto cleanup0;
edd16368 5158 }
9233fb10 5159 if ((ioc->Request.Type.Direction & XFER_READ) && ioc->buf_size > 0) {
edd16368
SC		 5160 /* Copy the data out of the buffer we created */
5161 BYTE __user *ptr = ioc->buf;
5162 for (i = 0; i < sg_used; i++) {
5163 if (copy_to_user(ptr, buff[i], buff_size[i])) {
edd16368 5164 status = -EFAULT;
e2d4a1f6 5165 goto cleanup0;
edd16368
SC		 5166 }
5167 ptr += buff_size[i];
5168 }
5169 }
edd16368 5170 status = 0;
e2d4a1f6
SC		 5171cleanup0:
5172 cmd_special_free(h, c);
edd16368
SC		 5173cleanup1:
5174 if (buff) {
5175 for (i = 0; i < sg_used; i++)
5176 kfree(buff[i]);
5177 kfree(buff);
5178 }
5179 kfree(buff_size);
5180 kfree(ioc);
5181 return status;
5182}
5183
5184static void check_ioctl_unit_attention(struct ctlr_info *h,
5185 struct CommandList *c)
5186{
5187 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
5188 c->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION)
5189 (void) check_for_unit_attention(h, c);
5190}
0390f0c0
SC		 5191
5192static int increment_passthru_count(struct ctlr_info *h)
5193{
5194 unsigned long flags;
5195
5196 spin_lock_irqsave(&h->passthru_count_lock, flags);
5197 if (h->passthru_count >= HPSA_MAX_CONCURRENT_PASSTHRUS) {
5198 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
5199 return -1;
5200 }
5201 h->passthru_count++;
5202 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
5203 return 0;
5204}
5205
5206static void decrement_passthru_count(struct ctlr_info *h)
5207{
5208 unsigned long flags;
5209
5210 spin_lock_irqsave(&h->passthru_count_lock, flags);
5211 if (h->passthru_count <= 0) {
5212 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
5213 /* not expecting to get here. */
5214 dev_warn(&h->pdev->dev, "Bug detected, passthru_count seems to be incorrect.\n");
5215 return;
5216 }
5217 h->passthru_count--;
5218 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
5219}
5220
edd16368
SC		 5221/*
5222 * ioctl
5223 */
5224static int hpsa_ioctl(struct scsi_device *dev, int cmd, void *arg)
5225{
5226 struct ctlr_info *h;
5227 void __user *argp = (void __user *)arg;
0390f0c0 5228 int rc;
edd16368
SC		 5229
5230 h = sdev_to_hba(dev);
5231
5232 switch (cmd) {
5233 case CCISS_DEREGDISK:
5234 case CCISS_REGNEWDISK:
5235 case CCISS_REGNEWD:
a08a8471 5236 hpsa_scan_start(h->scsi_host);
edd16368
SC		 5237 return 0;
5238 case CCISS_GETPCIINFO:
5239 return hpsa_getpciinfo_ioctl(h, argp);
5240 case CCISS_GETDRIVVER:
5241 return hpsa_getdrivver_ioctl(h, argp);
5242 case CCISS_PASSTHRU:
0390f0c0
SC		 5243 if (increment_passthru_count(h))
5244 return -EAGAIN;
5245 rc = hpsa_passthru_ioctl(h, argp);
5246 decrement_passthru_count(h);
5247 return rc;
edd16368 5248 case CCISS_BIG_PASSTHRU:
0390f0c0
SC		 5249 if (increment_passthru_count(h))
5250 return -EAGAIN;
5251 rc = hpsa_big_passthru_ioctl(h, argp);
5252 decrement_passthru_count(h);
5253 return rc;
edd16368
SC		 5254 default:
5255 return -ENOTTY;
5256 }
5257}
5258
6f039790
GKH		 5259static int hpsa_send_host_reset(struct ctlr_info *h, unsigned char *scsi3addr,
5260 u8 reset_type)
64670ac8
SC		 5261{
5262 struct CommandList *c;
5263
5264 c = cmd_alloc(h);
5265 if (!c)
5266 return -ENOMEM;
a2dac136
SC		 5267 /* fill_cmd can't fail here, no data buffer to map */
5268 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
64670ac8
SC		 5269 RAID_CTLR_LUNID, TYPE_MSG);
5270 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to target reset */
5271 c->waiting = NULL;
5272 enqueue_cmd_and_start_io(h, c);
5273 /* Don't wait for completion, the reset won't complete. Don't free
5274 * the command either. This is the last command we will send before
5275 * re-initializing everything, so it doesn't matter and won't leak.
5276 */
5277 return 0;
5278}
5279
a2dac136 5280static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
b7bb24eb 5281 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
edd16368
SC		 5282 int cmd_type)
5283{
5284 int pci_dir = XFER_NONE;
75167d2c 5285 struct CommandList *a; /* for commands to be aborted */
edd16368
SC		 5286
5287 c->cmd_type = CMD_IOCTL_PEND;
5288 c->Header.ReplyQueue = 0;
5289 if (buff != NULL && size > 0) {
5290 c->Header.SGList = 1;
5291 c->Header.SGTotal = 1;
5292 } else {
5293 c->Header.SGList = 0;
5294 c->Header.SGTotal = 0;
5295 }
5296 c->Header.Tag.lower = c->busaddr;
5297 memcpy(c->Header.LUN.LunAddrBytes, scsi3addr, 8);
5298
5299 c->Request.Type.Type = cmd_type;
5300 if (cmd_type == TYPE_CMD) {
5301 switch (cmd) {
5302 case HPSA_INQUIRY:
5303 /* are we trying to read a vital product page */
b7bb24eb 5304 if (page_code & VPD_PAGE) {
edd16368 5305 c->Request.CDB[1] = 0x01;
b7bb24eb 5306 c->Request.CDB[2] = (page_code & 0xff);
edd16368
SC		 5307 }
5308 c->Request.CDBLen = 6;
5309 c->Request.Type.Attribute = ATTR_SIMPLE;
5310 c->Request.Type.Direction = XFER_READ;
5311 c->Request.Timeout = 0;
5312 c->Request.CDB[0] = HPSA_INQUIRY;
5313 c->Request.CDB[4] = size & 0xFF;
5314 break;
5315 case HPSA_REPORT_LOG:
5316 case HPSA_REPORT_PHYS:
5317 /* Talking to controller so It's a physical command
5318 mode = 00 target = 0. Nothing to write.
5319 */
5320 c->Request.CDBLen = 12;
5321 c->Request.Type.Attribute = ATTR_SIMPLE;
5322 c->Request.Type.Direction = XFER_READ;
5323 c->Request.Timeout = 0;
5324 c->Request.CDB[0] = cmd;
5325 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
5326 c->Request.CDB[7] = (size >> 16) & 0xFF;
5327 c->Request.CDB[8] = (size >> 8) & 0xFF;
5328 c->Request.CDB[9] = size & 0xFF;
5329 break;
edd16368
SC		 5330 case HPSA_CACHE_FLUSH:
5331 c->Request.CDBLen = 12;
5332 c->Request.Type.Attribute = ATTR_SIMPLE;
5333 c->Request.Type.Direction = XFER_WRITE;
5334 c->Request.Timeout = 0;
5335 c->Request.CDB[0] = BMIC_WRITE;
5336 c->Request.CDB[6] = BMIC_CACHE_FLUSH;
bb158eab
SC		 5337 c->Request.CDB[7] = (size >> 8) & 0xFF;
5338 c->Request.CDB[8] = size & 0xFF;
edd16368
SC		 5339 break;
5340 case TEST_UNIT_READY:
5341 c->Request.CDBLen = 6;
5342 c->Request.Type.Attribute = ATTR_SIMPLE;
5343 c->Request.Type.Direction = XFER_NONE;
5344 c->Request.Timeout = 0;
5345 break;
283b4a9b
SC		 5346 case HPSA_GET_RAID_MAP:
5347 c->Request.CDBLen = 12;
5348 c->Request.Type.Attribute = ATTR_SIMPLE;
5349 c->Request.Type.Direction = XFER_READ;
5350 c->Request.Timeout = 0;
5351 c->Request.CDB[0] = HPSA_CISS_READ;
5352 c->Request.CDB[1] = cmd;
5353 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
5354 c->Request.CDB[7] = (size >> 16) & 0xFF;
5355 c->Request.CDB[8] = (size >> 8) & 0xFF;
5356 c->Request.CDB[9] = size & 0xFF;
5357 break;
316b221a
SC		 5358 case BMIC_SENSE_CONTROLLER_PARAMETERS:
5359 c->Request.CDBLen = 10;
5360 c->Request.Type.Attribute = ATTR_SIMPLE;
5361 c->Request.Type.Direction = XFER_READ;
5362 c->Request.Timeout = 0;
5363 c->Request.CDB[0] = BMIC_READ;
5364 c->Request.CDB[6] = BMIC_SENSE_CONTROLLER_PARAMETERS;
5365 c->Request.CDB[7] = (size >> 16) & 0xFF;
5366 c->Request.CDB[8] = (size >> 8) & 0xFF;
5367 break;
edd16368
SC		 5368 default:
5369 dev_warn(&h->pdev->dev, "unknown command 0x%c\n", cmd);
5370 BUG();
a2dac136 5371 return -1;
edd16368
SC		 5372 }
5373 } else if (cmd_type == TYPE_MSG) {
5374 switch (cmd) {
5375
5376 case HPSA_DEVICE_RESET_MSG:
5377 c->Request.CDBLen = 16;
5378 c->Request.Type.Type = 1; /* It is a MSG not a CMD */
5379 c->Request.Type.Attribute = ATTR_SIMPLE;
5380 c->Request.Type.Direction = XFER_NONE;
5381 c->Request.Timeout = 0; /* Don't time out */
64670ac8
SC		 5382 memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
5383 c->Request.CDB[0] = cmd;
21e89afd 5384 c->Request.CDB[1] = HPSA_RESET_TYPE_LUN;
edd16368
SC		 5385 /* If bytes 4-7 are zero, it means reset the */
5386 /* LunID device */
5387 c->Request.CDB[4] = 0x00;
5388 c->Request.CDB[5] = 0x00;
5389 c->Request.CDB[6] = 0x00;
5390 c->Request.CDB[7] = 0x00;
75167d2c
SC		 5391 break;
5392 case HPSA_ABORT_MSG:
5393 a = buff; /* point to command to be aborted */
5394 dev_dbg(&h->pdev->dev, "Abort Tag:0x%08x:%08x using request Tag:0x%08x:%08x\n",
5395 a->Header.Tag.upper, a->Header.Tag.lower,
5396 c->Header.Tag.upper, c->Header.Tag.lower);
5397 c->Request.CDBLen = 16;
5398 c->Request.Type.Type = TYPE_MSG;
5399 c->Request.Type.Attribute = ATTR_SIMPLE;
5400 c->Request.Type.Direction = XFER_WRITE;
5401 c->Request.Timeout = 0; /* Don't time out */
5402 c->Request.CDB[0] = HPSA_TASK_MANAGEMENT;
5403 c->Request.CDB[1] = HPSA_TMF_ABORT_TASK;
5404 c->Request.CDB[2] = 0x00; /* reserved */
5405 c->Request.CDB[3] = 0x00; /* reserved */
5406 /* Tag to abort goes in CDB[4]-CDB[11] */
5407 c->Request.CDB[4] = a->Header.Tag.lower & 0xFF;
5408 c->Request.CDB[5] = (a->Header.Tag.lower >> 8) & 0xFF;
5409 c->Request.CDB[6] = (a->Header.Tag.lower >> 16) & 0xFF;
5410 c->Request.CDB[7] = (a->Header.Tag.lower >> 24) & 0xFF;
5411 c->Request.CDB[8] = a->Header.Tag.upper & 0xFF;
5412 c->Request.CDB[9] = (a->Header.Tag.upper >> 8) & 0xFF;
5413 c->Request.CDB[10] = (a->Header.Tag.upper >> 16) & 0xFF;
5414 c->Request.CDB[11] = (a->Header.Tag.upper >> 24) & 0xFF;
5415 c->Request.CDB[12] = 0x00; /* reserved */
5416 c->Request.CDB[13] = 0x00; /* reserved */
5417 c->Request.CDB[14] = 0x00; /* reserved */
5418 c->Request.CDB[15] = 0x00; /* reserved */
edd16368 5419 break;
edd16368
SC		 5420 default:
5421 dev_warn(&h->pdev->dev, "unknown message type %d\n",
5422 cmd);
5423 BUG();
5424 }
5425 } else {
5426 dev_warn(&h->pdev->dev, "unknown command type %d\n", cmd_type);
5427 BUG();
5428 }
5429
5430 switch (c->Request.Type.Direction) {
5431 case XFER_READ:
5432 pci_dir = PCI_DMA_FROMDEVICE;
5433 break;
5434 case XFER_WRITE:
5435 pci_dir = PCI_DMA_TODEVICE;
5436 break;
5437 case XFER_NONE:
5438 pci_dir = PCI_DMA_NONE;
5439 break;
5440 default:
5441 pci_dir = PCI_DMA_BIDIRECTIONAL;
5442 }
a2dac136
SC		 5443 if (hpsa_map_one(h->pdev, c, buff, size, pci_dir))
5444 return -1;
5445 return 0;
edd16368
SC		 5446}
5447
5448/*
5449 * Map (physical) PCI mem into (virtual) kernel space
5450 */
5451static void __iomem *remap_pci_mem(ulong base, ulong size)
5452{
5453 ulong page_base = ((ulong) base) & PAGE_MASK;
5454 ulong page_offs = ((ulong) base) - page_base;
088ba34c
SC		 5455 void __iomem *page_remapped = ioremap_nocache(page_base,
5456 page_offs + size);
edd16368
SC		 5457
5458 return page_remapped ? (page_remapped + page_offs) : NULL;
5459}
5460
5461/* Takes cmds off the submission queue and sends them to the hardware,
5462 * then puts them on the queue of cmds waiting for completion.
0b57075d 5463 * Assumes h->lock is held
edd16368 5464 */
0b57075d 5465static void start_io(struct ctlr_info *h, unsigned long *flags)
edd16368
SC		 5466{
5467 struct CommandList *c;
5468
9e0fc764
SC		 5469 while (!list_empty(&h->reqQ)) {
5470 c = list_entry(h->reqQ.next, struct CommandList, list);
edd16368
SC		 5471 /* can't do anything if fifo is full */
5472 if ((h->access.fifo_full(h))) {
396883e2 5473 h->fifo_recently_full = 1;
edd16368
SC		 5474 dev_warn(&h->pdev->dev, "fifo full\n");
5475 break;
5476 }
396883e2 5477 h->fifo_recently_full = 0;
edd16368
SC		 5478
5479 /* Get the first entry from the Request Q */
5480 removeQ(c);
5481 h->Qdepth--;
5482
edd16368
SC		 5483 /* Put job onto the completed Q */
5484 addQ(&h->cmpQ, c);
e16a33ad
MG		 5485
5486 /* Must increment commands_outstanding before unlocking
5487 * and submitting to avoid race checking for fifo full
5488 * condition.
5489 */
5490 h->commands_outstanding++;
e16a33ad
MG		 5491
5492 /* Tell the controller execute command */
0b57075d 5493 spin_unlock_irqrestore(&h->lock, *flags);
e16a33ad 5494 h->access.submit_command(h, c);
0b57075d 5495 spin_lock_irqsave(&h->lock, *flags);
edd16368 5496 }
0b57075d
SC		 5497}
5498
5499static void lock_and_start_io(struct ctlr_info *h)
5500{
5501 unsigned long flags;
5502
5503 spin_lock_irqsave(&h->lock, flags);
5504 start_io(h, &flags);
e16a33ad 5505 spin_unlock_irqrestore(&h->lock, flags);
edd16368
SC		 5506}
5507
254f796b 5508static inline unsigned long get_next_completion(struct ctlr_info *h, u8 q)
edd16368 5509{
254f796b 5510 return h->access.command_completed(h, q);
edd16368
SC		 5511}
5512
900c5440 5513static inline bool interrupt_pending(struct ctlr_info *h)
edd16368
SC		 5514{
5515 return h->access.intr_pending(h);
5516}
5517
5518static inline long interrupt_not_for_us(struct ctlr_info *h)
5519{
10f66018
SC		 5520 return (h->access.intr_pending(h) == 0) ||
5521 (h->interrupts_enabled == 0);
edd16368
SC		 5522}
5523
01a02ffc
SC		 5524static inline int bad_tag(struct ctlr_info *h, u32 tag_index,
5525 u32 raw_tag)
edd16368
SC		 5526{
5527 if (unlikely(tag_index >= h->nr_cmds)) {
5528 dev_warn(&h->pdev->dev, "bad tag 0x%08x ignored.\n", raw_tag);
5529 return 1;
5530 }
5531 return 0;
5532}
5533
5a3d16f5 5534static inline void finish_cmd(struct CommandList *c)
edd16368 5535{
e16a33ad 5536 unsigned long flags;
396883e2
SC		 5537 int io_may_be_stalled = 0;
5538 struct ctlr_info *h = c->h;
e16a33ad 5539
396883e2 5540 spin_lock_irqsave(&h->lock, flags);
edd16368 5541 removeQ(c);
396883e2
SC		 5542
5543 /*
5544 * Check for possibly stalled i/o.
5545 *
5546 * If a fifo_full condition is encountered, requests will back up
5547 * in h->reqQ. This queue is only emptied out by start_io which is
5548 * only called when a new i/o request comes in. If no i/o's are
5549 * forthcoming, the i/o's in h->reqQ can get stuck. So we call
5550 * start_io from here if we detect such a danger.
5551 *
5552 * Normally, we shouldn't hit this case, but pounding on the
5553 * CCISS_PASSTHRU ioctl can provoke it. Only call start_io if
5554 * commands_outstanding is low. We want to avoid calling
5555 * start_io from in here as much as possible, and esp. don't
5556 * want to get in a cycle where we call start_io every time
5557 * through here.
5558 */
5559 if (unlikely(h->fifo_recently_full) &&
5560 h->commands_outstanding < 5)
5561 io_may_be_stalled = 1;
5562
5563 spin_unlock_irqrestore(&h->lock, flags);
5564
e85c5974 5565 dial_up_lockup_detection_on_fw_flash_complete(c->h, c);
c349775e
ST		 5566 if (likely(c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_SCSI
5567 || c->cmd_type == CMD_IOACCEL2))
1fb011fb 5568 complete_scsi_command(c);
edd16368
SC		 5569 else if (c->cmd_type == CMD_IOCTL_PEND)
5570 complete(c->waiting);
396883e2 5571 if (unlikely(io_may_be_stalled))
0b57075d 5572 lock_and_start_io(h);
edd16368
SC		 5573}
5574
a104c99f
SC		 5575static inline u32 hpsa_tag_contains_index(u32 tag)
5576{
a104c99f
SC		 5577 return tag & DIRECT_LOOKUP_BIT;
5578}
5579
5580static inline u32 hpsa_tag_to_index(u32 tag)
5581{
a104c99f
SC		 5582 return tag >> DIRECT_LOOKUP_SHIFT;
5583}
5584
a9a3a273
SC		 5585
5586static inline u32 hpsa_tag_discard_error_bits(struct ctlr_info *h, u32 tag)
a104c99f 5587{
a9a3a273
SC		 5588#define HPSA_PERF_ERROR_BITS ((1 << DIRECT_LOOKUP_SHIFT) - 1)
5589#define HPSA_SIMPLE_ERROR_BITS 0x03
960a30e7 5590 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
a9a3a273
SC		 5591 return tag & ~HPSA_SIMPLE_ERROR_BITS;
5592 return tag & ~HPSA_PERF_ERROR_BITS;
a104c99f
SC		 5593}
5594
303932fd 5595/* process completion of an indexed ("direct lookup") command */
1d94f94d 5596static inline void process_indexed_cmd(struct ctlr_info *h,
303932fd
DB		 5597 u32 raw_tag)
5598{
5599 u32 tag_index;
5600 struct CommandList *c;
5601
5602 tag_index = hpsa_tag_to_index(raw_tag);
1d94f94d
SC		 5603 if (!bad_tag(h, tag_index, raw_tag)) {
5604 c = h->cmd_pool + tag_index;
5605 finish_cmd(c);
5606 }
303932fd
DB		 5607}
5608
5609/* process completion of a non-indexed command */
1d94f94d 5610static inline void process_nonindexed_cmd(struct ctlr_info *h,
303932fd
DB		 5611 u32 raw_tag)
5612{
5613 u32 tag;
5614 struct CommandList *c = NULL;
e16a33ad 5615 unsigned long flags;
303932fd 5616
a9a3a273 5617 tag = hpsa_tag_discard_error_bits(h, raw_tag);
e16a33ad 5618 spin_lock_irqsave(&h->lock, flags);
9e0fc764 5619 list_for_each_entry(c, &h->cmpQ, list) {
303932fd 5620 if ((c->busaddr & 0xFFFFFFE0) == (tag & 0xFFFFFFE0)) {
e16a33ad 5621 spin_unlock_irqrestore(&h->lock, flags);
5a3d16f5 5622 finish_cmd(c);
1d94f94d 5623 return;
303932fd
DB		 5624 }
5625 }
e16a33ad 5626 spin_unlock_irqrestore(&h->lock, flags);
303932fd 5627 bad_tag(h, h->nr_cmds + 1, raw_tag);
303932fd
DB		 5628}
5629
64670ac8
SC		 5630/* Some controllers, like p400, will give us one interrupt
5631 * after a soft reset, even if we turned interrupts off.
5632 * Only need to check for this in the hpsa_xxx_discard_completions
5633 * functions.
5634 */
5635static int ignore_bogus_interrupt(struct ctlr_info *h)
5636{
5637 if (likely(!reset_devices))
5638 return 0;
5639
5640 if (likely(h->interrupts_enabled))
5641 return 0;
5642
5643 dev_info(&h->pdev->dev, "Received interrupt while interrupts disabled "
5644 "(known firmware bug.) Ignoring.\n");
5645
5646 return 1;
5647}
5648
254f796b
MG		 5649/*
5650 * Convert &h->q[x] (passed to interrupt handlers) back to h.
5651 * Relies on (h-q[x] == x) being true for x such that
5652 * 0 <= x < MAX_REPLY_QUEUES.
5653 */
5654static struct ctlr_info *queue_to_hba(u8 *queue)
64670ac8 5655{
254f796b
MG		 5656 return container_of((queue - *queue), struct ctlr_info, q[0]);
5657}
5658
5659static irqreturn_t hpsa_intx_discard_completions(int irq, void *queue)
5660{
5661 struct ctlr_info *h = queue_to_hba(queue);
5662 u8 q = *(u8 *) queue;
64670ac8
SC		 5663 u32 raw_tag;
5664
5665 if (ignore_bogus_interrupt(h))
5666 return IRQ_NONE;
5667
5668 if (interrupt_not_for_us(h))
5669 return IRQ_NONE;
a0c12413 5670 h->last_intr_timestamp = get_jiffies_64();
64670ac8 5671 while (interrupt_pending(h)) {
254f796b 5672 raw_tag = get_next_completion(h, q);
64670ac8 5673 while (raw_tag != FIFO_EMPTY)
254f796b 5674 raw_tag = next_command(h, q);
64670ac8 5675 }
64670ac8
SC		 5676 return IRQ_HANDLED;
5677}
5678
254f796b 5679static irqreturn_t hpsa_msix_discard_completions(int irq, void *queue)
64670ac8 5680{
254f796b 5681 struct ctlr_info *h = queue_to_hba(queue);
64670ac8 5682 u32 raw_tag;
254f796b 5683 u8 q = *(u8 *) queue;
64670ac8
SC		 5684
5685 if (ignore_bogus_interrupt(h))
5686 return IRQ_NONE;
5687
a0c12413 5688 h->last_intr_timestamp = get_jiffies_64();
254f796b 5689 raw_tag = get_next_completion(h, q);
64670ac8 5690 while (raw_tag != FIFO_EMPTY)
254f796b 5691 raw_tag = next_command(h, q);
64670ac8
SC		 5692 return IRQ_HANDLED;
5693}
5694
254f796b 5695static irqreturn_t do_hpsa_intr_intx(int irq, void *queue)
edd16368 5696{
254f796b 5697 struct ctlr_info *h = queue_to_hba((u8 *) queue);
303932fd 5698 u32 raw_tag;
254f796b 5699 u8 q = *(u8 *) queue;
edd16368
SC		 5700
5701 if (interrupt_not_for_us(h))
5702 return IRQ_NONE;
a0c12413 5703 h->last_intr_timestamp = get_jiffies_64();
10f66018 5704 while (interrupt_pending(h)) {
254f796b 5705 raw_tag = get_next_completion(h, q);
10f66018 5706 while (raw_tag != FIFO_EMPTY) {
1d94f94d
SC		 5707 if (likely(hpsa_tag_contains_index(raw_tag)))
5708 process_indexed_cmd(h, raw_tag);
10f66018 5709 else
1d94f94d 5710 process_nonindexed_cmd(h, raw_tag);
254f796b 5711 raw_tag = next_command(h, q);
10f66018
SC		 5712 }
5713 }
10f66018
SC		 5714 return IRQ_HANDLED;
5715}
5716
254f796b 5717static irqreturn_t do_hpsa_intr_msi(int irq, void *queue)
10f66018 5718{
254f796b 5719 struct ctlr_info *h = queue_to_hba(queue);
10f66018 5720 u32 raw_tag;
254f796b 5721 u8 q = *(u8 *) queue;
10f66018 5722
a0c12413 5723 h->last_intr_timestamp = get_jiffies_64();
254f796b 5724 raw_tag = get_next_completion(h, q);
303932fd 5725 while (raw_tag != FIFO_EMPTY) {
1d94f94d
SC		 5726 if (likely(hpsa_tag_contains_index(raw_tag)))
5727 process_indexed_cmd(h, raw_tag);
303932fd 5728 else
1d94f94d 5729 process_nonindexed_cmd(h, raw_tag);
254f796b 5730 raw_tag = next_command(h, q);
edd16368 5731 }
edd16368
SC		 5732 return IRQ_HANDLED;
5733}
5734
a9a3a273
SC		 5735/* Send a message CDB to the firmware. Careful, this only works
5736 * in simple mode, not performant mode due to the tag lookup.
5737 * We only ever use this immediately after a controller reset.
5738 */
6f039790
GKH		 5739static int hpsa_message(struct pci_dev *pdev, unsigned char opcode,
5740 unsigned char type)
edd16368
SC		 5741{
5742 struct Command {
5743 struct CommandListHeader CommandHeader;
5744 struct RequestBlock Request;
5745 struct ErrDescriptor ErrorDescriptor;
5746 };
5747 struct Command *cmd;
5748 static const size_t cmd_sz = sizeof(*cmd) +
5749 sizeof(cmd->ErrorDescriptor);
5750 dma_addr_t paddr64;
5751 uint32_t paddr32, tag;
5752 void __iomem *vaddr;
5753 int i, err;
5754
5755 vaddr = pci_ioremap_bar(pdev, 0);
5756 if (vaddr == NULL)
5757 return -ENOMEM;
5758
5759 /* The Inbound Post Queue only accepts 32-bit physical addresses for the
5760 * CCISS commands, so they must be allocated from the lower 4GiB of
5761 * memory.
5762 */
5763 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
5764 if (err) {
5765 iounmap(vaddr);
5766 return -ENOMEM;
5767 }
5768
5769 cmd = pci_alloc_consistent(pdev, cmd_sz, &paddr64);
5770 if (cmd == NULL) {
5771 iounmap(vaddr);
5772 return -ENOMEM;
5773 }
5774
5775 /* This must fit, because of the 32-bit consistent DMA mask. Also,
5776 * although there's no guarantee, we assume that the address is at
5777 * least 4-byte aligned (most likely, it's page-aligned).
5778 */
5779 paddr32 = paddr64;
5780
5781 cmd->CommandHeader.ReplyQueue = 0;
5782 cmd->CommandHeader.SGList = 0;
5783 cmd->CommandHeader.SGTotal = 0;
5784 cmd->CommandHeader.Tag.lower = paddr32;
5785 cmd->CommandHeader.Tag.upper = 0;
5786 memset(&cmd->CommandHeader.LUN.LunAddrBytes, 0, 8);
5787
5788 cmd->Request.CDBLen = 16;
5789 cmd->Request.Type.Type = TYPE_MSG;
5790 cmd->Request.Type.Attribute = ATTR_HEADOFQUEUE;
5791 cmd->Request.Type.Direction = XFER_NONE;
5792 cmd->Request.Timeout = 0; /* Don't time out */
5793 cmd->Request.CDB[0] = opcode;
5794 cmd->Request.CDB[1] = type;
5795 memset(&cmd->Request.CDB[2], 0, 14); /* rest of the CDB is reserved */
5796 cmd->ErrorDescriptor.Addr.lower = paddr32 + sizeof(*cmd);
5797 cmd->ErrorDescriptor.Addr.upper = 0;
5798 cmd->ErrorDescriptor.Len = sizeof(struct ErrorInfo);
5799
5800 writel(paddr32, vaddr + SA5_REQUEST_PORT_OFFSET);
5801
5802 for (i = 0; i < HPSA_MSG_SEND_RETRY_LIMIT; i++) {
5803 tag = readl(vaddr + SA5_REPLY_PORT_OFFSET);
a9a3a273 5804 if ((tag & ~HPSA_SIMPLE_ERROR_BITS) == paddr32)
edd16368
SC		 5805 break;
5806 msleep(HPSA_MSG_SEND_RETRY_INTERVAL_MSECS);
5807 }
5808
5809 iounmap(vaddr);
5810
5811 /* we leak the DMA buffer here ... no choice since the controller could
5812 * still complete the command.
5813 */
5814 if (i == HPSA_MSG_SEND_RETRY_LIMIT) {
5815 dev_err(&pdev->dev, "controller message %02x:%02x timed out\n",
5816 opcode, type);
5817 return -ETIMEDOUT;
5818 }
5819
5820 pci_free_consistent(pdev, cmd_sz, cmd, paddr64);
5821
5822 if (tag & HPSA_ERROR_BIT) {
5823 dev_err(&pdev->dev, "controller message %02x:%02x failed\n",
5824 opcode, type);
5825 return -EIO;
5826 }
5827
5828 dev_info(&pdev->dev, "controller message %02x:%02x succeeded\n",
5829 opcode, type);
5830 return 0;
5831}
5832
edd16368
SC		 5833#define hpsa_noop(p) hpsa_message(p, 3, 0)
5834
1df8552a 5835static int hpsa_controller_hard_reset(struct pci_dev *pdev,
cf0b08d0 5836 void * __iomem vaddr, u32 use_doorbell)
1df8552a
SC		 5837{
5838 u16 pmcsr;
5839 int pos;
5840
5841 if (use_doorbell) {
5842 /* For everything after the P600, the PCI power state method
5843 * of resetting the controller doesn't work, so we have this
5844 * other way using the doorbell register.
5845 */
5846 dev_info(&pdev->dev, "using doorbell to reset controller\n");
cf0b08d0 5847 writel(use_doorbell, vaddr + SA5_DOORBELL);
85009239 5848
00701a96 5849 /* PMC hardware guys tell us we need a 10 second delay after
85009239
SC		 5850 * doorbell reset and before any attempt to talk to the board
5851 * at all to ensure that this actually works and doesn't fall
5852 * over in some weird corner cases.
5853 */
00701a96 5854 msleep(10000);
1df8552a
SC		 5855 } else { /* Try to do it the PCI power state way */
5856
5857 /* Quoting from the Open CISS Specification: "The Power
5858 * Management Control/Status Register (CSR) controls the power
5859 * state of the device. The normal operating state is D0,
5860 * CSR=00h. The software off state is D3, CSR=03h. To reset
5861 * the controller, place the interface device in D3 then to D0,
5862 * this causes a secondary PCI reset which will reset the
5863 * controller." */
5864
5865 pos = pci_find_capability(pdev, PCI_CAP_ID_PM);
5866 if (pos == 0) {
5867 dev_err(&pdev->dev,
5868 "hpsa_reset_controller: "
5869 "PCI PM not supported\n");
5870 return -ENODEV;
5871 }
5872 dev_info(&pdev->dev, "using PCI PM to reset controller\n");
5873 /* enter the D3hot power management state */
5874 pci_read_config_word(pdev, pos + PCI_PM_CTRL, &pmcsr);
5875 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
5876 pmcsr |= PCI_D3hot;
5877 pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr);
5878
5879 msleep(500);
5880
5881 /* enter the D0 power management state */
5882 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
5883 pmcsr |= PCI_D0;
5884 pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr);
c4853efe
MM		 5885
5886 /*
5887 * The P600 requires a small delay when changing states.
5888 * Otherwise we may think the board did not reset and we bail.
5889 * This for kdump only and is particular to the P600.
5890 */
5891 msleep(500);
1df8552a
SC		 5892 }
5893 return 0;
5894}
5895
6f039790 5896static void init_driver_version(char *driver_version, int len)
580ada3c
SC		 5897{
5898 memset(driver_version, 0, len);
f79cfec6 5899 strncpy(driver_version, HPSA " " HPSA_DRIVER_VERSION, len - 1);
580ada3c
SC		 5900}
5901
6f039790 5902static int write_driver_ver_to_cfgtable(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 5903{
5904 char *driver_version;
5905 int i, size = sizeof(cfgtable->driver_version);
5906
5907 driver_version = kmalloc(size, GFP_KERNEL);
5908 if (!driver_version)
5909 return -ENOMEM;
5910
5911 init_driver_version(driver_version, size);
5912 for (i = 0; i < size; i++)
5913 writeb(driver_version[i], &cfgtable->driver_version[i]);
5914 kfree(driver_version);
5915 return 0;
5916}
5917
6f039790
GKH		 5918static void read_driver_ver_from_cfgtable(struct CfgTable __iomem *cfgtable,
5919 unsigned char *driver_ver)
580ada3c
SC		 5920{
5921 int i;
5922
5923 for (i = 0; i < sizeof(cfgtable->driver_version); i++)
5924 driver_ver[i] = readb(&cfgtable->driver_version[i]);
5925}
5926
6f039790 5927static int controller_reset_failed(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 5928{
5929
5930 char *driver_ver, *old_driver_ver;
5931 int rc, size = sizeof(cfgtable->driver_version);
5932
5933 old_driver_ver = kmalloc(2 * size, GFP_KERNEL);
5934 if (!old_driver_ver)
5935 return -ENOMEM;
5936 driver_ver = old_driver_ver + size;
5937
5938 /* After a reset, the 32 bytes of "driver version" in the cfgtable
5939 * should have been changed, otherwise we know the reset failed.
5940 */
5941 init_driver_version(old_driver_ver, size);
5942 read_driver_ver_from_cfgtable(cfgtable, driver_ver);
5943 rc = !memcmp(driver_ver, old_driver_ver, size);
5944 kfree(old_driver_ver);
5945 return rc;
5946}
edd16368 5947/* This does a hard reset of the controller using PCI power management
1df8552a 5948 * states or the using the doorbell register.
edd16368 5949 */
6f039790 5950static int hpsa_kdump_hard_reset_controller(struct pci_dev *pdev)
edd16368 5951{
1df8552a
SC		 5952 u64 cfg_offset;
5953 u32 cfg_base_addr;
5954 u64 cfg_base_addr_index;
5955 void __iomem *vaddr;
5956 unsigned long paddr;
580ada3c 5957 u32 misc_fw_support;
270d05de 5958 int rc;
1df8552a 5959 struct CfgTable __iomem *cfgtable;
cf0b08d0 5960 u32 use_doorbell;
18867659 5961 u32 board_id;
270d05de 5962 u16 command_register;
edd16368 5963
1df8552a
SC		 5964 /* For controllers as old as the P600, this is very nearly
5965 * the same thing as
edd16368
SC		 5966 *
5967 * pci_save_state(pci_dev);
5968 * pci_set_power_state(pci_dev, PCI_D3hot);
5969 * pci_set_power_state(pci_dev, PCI_D0);
5970 * pci_restore_state(pci_dev);
5971 *
1df8552a
SC		 5972 * For controllers newer than the P600, the pci power state
5973 * method of resetting doesn't work so we have another way
5974 * using the doorbell register.
edd16368 5975 */
18867659 5976
25c1e56a 5977 rc = hpsa_lookup_board_id(pdev, &board_id);
46380786 5978 if (rc < 0 || !ctlr_is_resettable(board_id)) {
25c1e56a
SC		 5979 dev_warn(&pdev->dev, "Not resetting device.\n");
5980 return -ENODEV;
5981 }
46380786
SC		 5982
5983 /* if controller is soft- but not hard resettable... */
5984 if (!ctlr_is_hard_resettable(board_id))
5985 return -ENOTSUPP; /* try soft reset later. */
18867659 5986
270d05de
SC		 5987 /* Save the PCI command register */
5988 pci_read_config_word(pdev, 4, &command_register);
5989 /* Turn the board off. This is so that later pci_restore_state()
5990 * won't turn the board on before the rest of config space is ready.
5991 */
5992 pci_disable_device(pdev);
5993 pci_save_state(pdev);
edd16368 5994
1df8552a
SC		 5995 /* find the first memory BAR, so we can find the cfg table */
5996 rc = hpsa_pci_find_memory_BAR(pdev, &paddr);
5997 if (rc)
5998 return rc;
5999 vaddr = remap_pci_mem(paddr, 0x250);
6000 if (!vaddr)
6001 return -ENOMEM;
edd16368 6002
1df8552a
SC		 6003 /* find cfgtable in order to check if reset via doorbell is supported */
6004 rc = hpsa_find_cfg_addrs(pdev, vaddr, &cfg_base_addr,
6005 &cfg_base_addr_index, &cfg_offset);
6006 if (rc)
6007 goto unmap_vaddr;
6008 cfgtable = remap_pci_mem(pci_resource_start(pdev,
6009 cfg_base_addr_index) + cfg_offset, sizeof(*cfgtable));
6010 if (!cfgtable) {
6011 rc = -ENOMEM;
6012 goto unmap_vaddr;
6013 }
580ada3c
SC		 6014 rc = write_driver_ver_to_cfgtable(cfgtable);
6015 if (rc)
6016 goto unmap_vaddr;
edd16368 6017
cf0b08d0
SC		 6018 /* If reset via doorbell register is supported, use that.
6019 * There are two such methods. Favor the newest method.
6020 */
1df8552a 6021 misc_fw_support = readl(&cfgtable->misc_fw_support);
cf0b08d0
SC		 6022 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET2;
6023 if (use_doorbell) {
6024 use_doorbell = DOORBELL_CTLR_RESET2;
6025 } else {
6026 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET;
6027 if (use_doorbell) {
fba63097
MM		 6028 dev_warn(&pdev->dev, "Soft reset not supported. "
6029 "Firmware update is required.\n");
64670ac8 6030 rc = -ENOTSUPP; /* try soft reset */
cf0b08d0
SC		 6031 goto unmap_cfgtable;
6032 }
6033 }
edd16368 6034
1df8552a
SC		 6035 rc = hpsa_controller_hard_reset(pdev, vaddr, use_doorbell);
6036 if (rc)
6037 goto unmap_cfgtable;
edd16368 6038
270d05de
SC		 6039 pci_restore_state(pdev);
6040 rc = pci_enable_device(pdev);
6041 if (rc) {
6042 dev_warn(&pdev->dev, "failed to enable device.\n");
6043 goto unmap_cfgtable;
edd16368 6044 }
270d05de 6045 pci_write_config_word(pdev, 4, command_register);
edd16368 6046
1df8552a
SC		 6047 /* Some devices (notably the HP Smart Array 5i Controller)
6048 need a little pause here */
6049 msleep(HPSA_POST_RESET_PAUSE_MSECS);
6050
fe5389c8
SC		 6051 rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_READY);
6052 if (rc) {
6053 dev_warn(&pdev->dev,
64670ac8
SC		 6054 "failed waiting for board to become ready "
6055 "after hard reset\n");
fe5389c8
SC		 6056 goto unmap_cfgtable;
6057 }
fe5389c8 6058
580ada3c
SC		 6059 rc = controller_reset_failed(vaddr);
6060 if (rc < 0)
6061 goto unmap_cfgtable;
6062 if (rc) {
64670ac8
SC		 6063 dev_warn(&pdev->dev, "Unable to successfully reset "
6064 "controller. Will try soft reset.\n");
6065 rc = -ENOTSUPP;
580ada3c 6066 } else {
64670ac8 6067 dev_info(&pdev->dev, "board ready after hard reset.\n");
1df8552a
SC		 6068 }
6069
6070unmap_cfgtable:
6071 iounmap(cfgtable);
6072
6073unmap_vaddr:
6074 iounmap(vaddr);
6075 return rc;
edd16368
SC		 6076}
6077
6078/*
6079 * We cannot read the structure directly, for portability we must use
6080 * the io functions.
6081 * This is for debug only.
6082 */
edd16368
SC		 6083static void print_cfg_table(struct device *dev, struct CfgTable *tb)
6084{
58f8665c 6085#ifdef HPSA_DEBUG
edd16368
SC		 6086 int i;
6087 char temp_name[17];
6088
6089 dev_info(dev, "Controller Configuration information\n");
6090 dev_info(dev, "------------------------------------\n");
6091 for (i = 0; i < 4; i++)
6092 temp_name[i] = readb(&(tb->Signature[i]));
6093 temp_name[4] = '\0';
6094 dev_info(dev, " Signature = %s\n", temp_name);
6095 dev_info(dev, " Spec Number = %d\n", readl(&(tb->SpecValence)));
6096 dev_info(dev, " Transport methods supported = 0x%x\n",
6097 readl(&(tb->TransportSupport)));
6098 dev_info(dev, " Transport methods active = 0x%x\n",
6099 readl(&(tb->TransportActive)));
6100 dev_info(dev, " Requested transport Method = 0x%x\n",
6101 readl(&(tb->HostWrite.TransportRequest)));
6102 dev_info(dev, " Coalesce Interrupt Delay = 0x%x\n",
6103 readl(&(tb->HostWrite.CoalIntDelay)));
6104 dev_info(dev, " Coalesce Interrupt Count = 0x%x\n",
6105 readl(&(tb->HostWrite.CoalIntCount)));
6106 dev_info(dev, " Max outstanding commands = 0x%d\n",
6107 readl(&(tb->CmdsOutMax)));
6108 dev_info(dev, " Bus Types = 0x%x\n", readl(&(tb->BusTypes)));
6109 for (i = 0; i < 16; i++)
6110 temp_name[i] = readb(&(tb->ServerName[i]));
6111 temp_name[16] = '\0';
6112 dev_info(dev, " Server Name = %s\n", temp_name);
6113 dev_info(dev, " Heartbeat Counter = 0x%x\n\n\n",
6114 readl(&(tb->HeartBeat)));
edd16368 6115#endif /* HPSA_DEBUG */
58f8665c 6116}
edd16368
SC		 6117
6118static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr)
6119{
6120 int i, offset, mem_type, bar_type;
6121
6122 if (pci_bar_addr == PCI_BASE_ADDRESS_0) /* looking for BAR zero? */
6123 return 0;
6124 offset = 0;
6125 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
6126 bar_type = pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE;
6127 if (bar_type == PCI_BASE_ADDRESS_SPACE_IO)
6128 offset += 4;
6129 else {
6130 mem_type = pci_resource_flags(pdev, i) &
6131 PCI_BASE_ADDRESS_MEM_TYPE_MASK;
6132 switch (mem_type) {
6133 case PCI_BASE_ADDRESS_MEM_TYPE_32:
6134 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
6135 offset += 4; /* 32 bit */
6136 break;
6137 case PCI_BASE_ADDRESS_MEM_TYPE_64:
6138 offset += 8;
6139 break;
6140 default: /* reserved in PCI 2.2 */
6141 dev_warn(&pdev->dev,
6142 "base address is invalid\n");
6143 return -1;
6144 break;
6145 }
6146 }
6147 if (offset == pci_bar_addr - PCI_BASE_ADDRESS_0)
6148 return i + 1;
6149 }
6150 return -1;
6151}
6152
6153/* If MSI/MSI-X is supported by the kernel we will try to enable it on
6154 * controllers that are capable. If not, we use IO-APIC mode.
6155 */
6156
6f039790 6157static void hpsa_interrupt_mode(struct ctlr_info *h)
edd16368
SC		 6158{
6159#ifdef CONFIG_PCI_MSI
254f796b
MG		 6160 int err, i;
6161 struct msix_entry hpsa_msix_entries[MAX_REPLY_QUEUES];
6162
6163 for (i = 0; i < MAX_REPLY_QUEUES; i++) {
6164 hpsa_msix_entries[i].vector = 0;
6165 hpsa_msix_entries[i].entry = i;
6166 }
edd16368
SC		 6167
6168 /* Some boards advertise MSI but don't really support it */
6b3f4c52
SC		 6169 if ((h->board_id == 0x40700E11) || (h->board_id == 0x40800E11) ||
6170 (h->board_id == 0x40820E11) || (h->board_id == 0x40830E11))
edd16368 6171 goto default_int_mode;
55c06c71
SC		 6172 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSIX)) {
6173 dev_info(&h->pdev->dev, "MSIX\n");
eee0f03a 6174 h->msix_vector = MAX_REPLY_QUEUES;
f89439bc
SC		 6175 if (h->msix_vector > num_online_cpus())
6176 h->msix_vector = num_online_cpus();
254f796b 6177 err = pci_enable_msix(h->pdev, hpsa_msix_entries,
eee0f03a 6178 h->msix_vector);
edd16368 6179 if (err > 0) {
55c06c71 6180 dev_warn(&h->pdev->dev, "only %d MSI-X vectors "
edd16368 6181 "available\n", err);
eee0f03a
HR		 6182 h->msix_vector = err;
6183 err = pci_enable_msix(h->pdev, hpsa_msix_entries,
6184 h->msix_vector);
6185 }
6186 if (!err) {
6187 for (i = 0; i < h->msix_vector; i++)
6188 h->intr[i] = hpsa_msix_entries[i].vector;
6189 return;
edd16368 6190 } else {
55c06c71 6191 dev_warn(&h->pdev->dev, "MSI-X init failed %d\n",
edd16368 6192 err);
eee0f03a 6193 h->msix_vector = 0;
edd16368
SC		 6194 goto default_int_mode;
6195 }
6196 }
55c06c71
SC		 6197 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSI)) {
6198 dev_info(&h->pdev->dev, "MSI\n");
6199 if (!pci_enable_msi(h->pdev))
edd16368
SC		 6200 h->msi_vector = 1;
6201 else
55c06c71 6202 dev_warn(&h->pdev->dev, "MSI init failed\n");
edd16368
SC		 6203 }
6204default_int_mode:
6205#endif /* CONFIG_PCI_MSI */
6206 /* if we get here we're going to use the default interrupt mode */
a9a3a273 6207 h->intr[h->intr_mode] = h->pdev->irq;
edd16368
SC		 6208}
6209
6f039790 6210static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id)
e5c880d1
SC		 6211{
6212 int i;
6213 u32 subsystem_vendor_id, subsystem_device_id;
6214
6215 subsystem_vendor_id = pdev->subsystem_vendor;
6216 subsystem_device_id = pdev->subsystem_device;
6217 *board_id = ((subsystem_device_id << 16) & 0xffff0000) |
6218 subsystem_vendor_id;
6219
6220 for (i = 0; i < ARRAY_SIZE(products); i++)
6221 if (*board_id == products[i].board_id)
6222 return i;
6223
6798cc0a
SC		 6224 if ((subsystem_vendor_id != PCI_VENDOR_ID_HP &&
6225 subsystem_vendor_id != PCI_VENDOR_ID_COMPAQ) ||
6226 !hpsa_allow_any) {
e5c880d1
SC		 6227 dev_warn(&pdev->dev, "unrecognized board ID: "
6228 "0x%08x, ignoring.\n", *board_id);
6229 return -ENODEV;
6230 }
6231 return ARRAY_SIZE(products) - 1; /* generic unknown smart array */
6232}
6233
6f039790
GKH		 6234static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
6235 unsigned long *memory_bar)
3a7774ce
SC		 6236{
6237 int i;
6238
6239 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
12d2cd47 6240 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
3a7774ce 6241 /* addressing mode bits already removed */
12d2cd47
SC		 6242 *memory_bar = pci_resource_start(pdev, i);
6243 dev_dbg(&pdev->dev, "memory BAR = %lx\n",
3a7774ce
SC		 6244 *memory_bar);
6245 return 0;
6246 }
12d2cd47 6247 dev_warn(&pdev->dev, "no memory BAR found\n");
3a7774ce
SC		 6248 return -ENODEV;
6249}
6250
6f039790
GKH		 6251static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
6252 int wait_for_ready)
2c4c8c8b 6253{
fe5389c8 6254 int i, iterations;
2c4c8c8b 6255 u32 scratchpad;
fe5389c8
SC		 6256 if (wait_for_ready)
6257 iterations = HPSA_BOARD_READY_ITERATIONS;
6258 else
6259 iterations = HPSA_BOARD_NOT_READY_ITERATIONS;
2c4c8c8b 6260
fe5389c8
SC		 6261 for (i = 0; i < iterations; i++) {
6262 scratchpad = readl(vaddr + SA5_SCRATCHPAD_OFFSET);
6263 if (wait_for_ready) {
6264 if (scratchpad == HPSA_FIRMWARE_READY)
6265 return 0;
6266 } else {
6267 if (scratchpad != HPSA_FIRMWARE_READY)
6268 return 0;
6269 }
2c4c8c8b
SC		 6270 msleep(HPSA_BOARD_READY_POLL_INTERVAL_MSECS);
6271 }
fe5389c8 6272 dev_warn(&pdev->dev, "board not ready, timed out.\n");
2c4c8c8b
SC		 6273 return -ENODEV;
6274}
6275
6f039790
GKH		 6276static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
6277 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
6278 u64 *cfg_offset)
a51fd47f
SC		 6279{
6280 *cfg_base_addr = readl(vaddr + SA5_CTCFG_OFFSET);
6281 *cfg_offset = readl(vaddr + SA5_CTMEM_OFFSET);
6282 *cfg_base_addr &= (u32) 0x0000ffff;
6283 *cfg_base_addr_index = find_PCI_BAR_index(pdev, *cfg_base_addr);
6284 if (*cfg_base_addr_index == -1) {
6285 dev_warn(&pdev->dev, "cannot find cfg_base_addr_index\n");
6286 return -ENODEV;
6287 }
6288 return 0;
6289}
6290
6f039790 6291static int hpsa_find_cfgtables(struct ctlr_info *h)
edd16368 6292{
01a02ffc
SC		 6293 u64 cfg_offset;
6294 u32 cfg_base_addr;
6295 u64 cfg_base_addr_index;
303932fd 6296 u32 trans_offset;
a51fd47f 6297 int rc;
77c4495c 6298
a51fd47f
SC		 6299 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
6300 &cfg_base_addr_index, &cfg_offset);
6301 if (rc)
6302 return rc;
77c4495c 6303 h->cfgtable = remap_pci_mem(pci_resource_start(h->pdev,
a51fd47f 6304 cfg_base_addr_index) + cfg_offset, sizeof(*h->cfgtable));
77c4495c
SC		 6305 if (!h->cfgtable)
6306 return -ENOMEM;
580ada3c
SC		 6307 rc = write_driver_ver_to_cfgtable(h->cfgtable);
6308 if (rc)
6309 return rc;
77c4495c 6310 /* Find performant mode table. */
a51fd47f 6311 trans_offset = readl(&h->cfgtable->TransMethodOffset);
77c4495c
SC		 6312 h->transtable = remap_pci_mem(pci_resource_start(h->pdev,
6313 cfg_base_addr_index)+cfg_offset+trans_offset,
6314 sizeof(*h->transtable));
6315 if (!h->transtable)
6316 return -ENOMEM;
6317 return 0;
6318}
6319
6f039790 6320static void hpsa_get_max_perf_mode_cmds(struct ctlr_info *h)
cba3d38b
SC		 6321{
6322 h->max_commands = readl(&(h->cfgtable->MaxPerformantModeCommands));
72ceeaec
SC		 6323
6324 /* Limit commands in memory limited kdump scenario. */
6325 if (reset_devices && h->max_commands > 32)
6326 h->max_commands = 32;
6327
cba3d38b
SC		 6328 if (h->max_commands < 16) {
6329 dev_warn(&h->pdev->dev, "Controller reports "
6330 "max supported commands of %d, an obvious lie. "
6331 "Using 16. Ensure that firmware is up to date.\n",
6332 h->max_commands);
6333 h->max_commands = 16;
6334 }
6335}
6336
b93d7536
SC		 6337/* Interrogate the hardware for some limits:
6338 * max commands, max SG elements without chaining, and with chaining,
6339 * SG chain block size, etc.
6340 */
6f039790 6341static void hpsa_find_board_params(struct ctlr_info *h)
b93d7536 6342{
cba3d38b 6343 hpsa_get_max_perf_mode_cmds(h);
b93d7536
SC		 6344 h->nr_cmds = h->max_commands - 4; /* Allow room for some ioctls */
6345 h->maxsgentries = readl(&(h->cfgtable->MaxScatterGatherElements));
283b4a9b 6346 h->fw_support = readl(&(h->cfgtable->misc_fw_support));
b93d7536
SC		 6347 /*
6348 * Limit in-command s/g elements to 32 save dma'able memory.
6349 * Howvever spec says if 0, use 31
6350 */
6351 h->max_cmd_sg_entries = 31;
6352 if (h->maxsgentries > 512) {
6353 h->max_cmd_sg_entries = 32;
6354 h->chainsize = h->maxsgentries - h->max_cmd_sg_entries + 1;
6355 h->maxsgentries--; /* save one for chain pointer */
6356 } else {
6357 h->maxsgentries = 31; /* default to traditional values */
6358 h->chainsize = 0;
6359 }
75167d2c
SC		 6360
6361 /* Find out what task management functions are supported and cache */
6362 h->TMFSupportFlags = readl(&(h->cfgtable->TMFSupportFlags));
0e7a7fce
ST		 6363 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags))
6364 dev_warn(&h->pdev->dev, "Physical aborts not supported\n");
6365 if (!(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
6366 dev_warn(&h->pdev->dev, "Logical aborts not supported\n");
b93d7536
SC		 6367}
6368
76c46e49
SC		 6369static inline bool hpsa_CISS_signature_present(struct ctlr_info *h)
6370{
0fc9fd40 6371 if (!check_signature(h->cfgtable->Signature, "CISS", 4)) {
76c46e49
SC		 6372 dev_warn(&h->pdev->dev, "not a valid CISS config table\n");
6373 return false;
6374 }
6375 return true;
6376}
6377
97a5e98c 6378static inline void hpsa_set_driver_support_bits(struct ctlr_info *h)
f7c39101 6379{
97a5e98c 6380 u32 driver_support;
f7c39101 6381
28e13446
SC		 6382#ifdef CONFIG_X86
6383 /* Need to enable prefetch in the SCSI core for 6400 in x86 */
97a5e98c
SC		 6384 driver_support = readl(&(h->cfgtable->driver_support));
6385 driver_support |= ENABLE_SCSI_PREFETCH;
f7c39101 6386#endif
28e13446
SC		 6387 driver_support |= ENABLE_UNIT_ATTN;
6388 writel(driver_support, &(h->cfgtable->driver_support));
f7c39101
SC		 6389}
6390
3d0eab67
SC		 6391/* Disable DMA prefetch for the P600. Otherwise an ASIC bug may result
6392 * in a prefetch beyond physical memory.
6393 */
6394static inline void hpsa_p600_dma_prefetch_quirk(struct ctlr_info *h)
6395{
6396 u32 dma_prefetch;
6397
6398 if (h->board_id != 0x3225103C)
6399 return;
6400 dma_prefetch = readl(h->vaddr + I2O_DMA1_CFG);
6401 dma_prefetch |= 0x8000;
6402 writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG);
6403}
6404
76438d08
SC		 6405static void hpsa_wait_for_clear_event_notify_ack(struct ctlr_info *h)
6406{
6407 int i;
6408 u32 doorbell_value;
6409 unsigned long flags;
6410 /* wait until the clear_event_notify bit 6 is cleared by controller. */
6411 for (i = 0; i < MAX_CONFIG_WAIT; i++) {
6412 spin_lock_irqsave(&h->lock, flags);
6413 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
6414 spin_unlock_irqrestore(&h->lock, flags);
6415 if (!(doorbell_value & DOORBELL_CLEAR_EVENTS))
6416 break;
6417 /* delay and try again */
6418 msleep(20);
6419 }
6420}
6421
6f039790 6422static void hpsa_wait_for_mode_change_ack(struct ctlr_info *h)
eb6b2ae9
SC		 6423{
6424 int i;
6eaf46fd
SC		 6425 u32 doorbell_value;
6426 unsigned long flags;
eb6b2ae9
SC		 6427
6428 /* under certain very rare conditions, this can take awhile.
6429 * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right
6430 * as we enter this code.)
6431 */
6432 for (i = 0; i < MAX_CONFIG_WAIT; i++) {
6eaf46fd
SC		 6433 spin_lock_irqsave(&h->lock, flags);
6434 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
6435 spin_unlock_irqrestore(&h->lock, flags);
382be668 6436 if (!(doorbell_value & CFGTBL_ChangeReq))
eb6b2ae9
SC		 6437 break;
6438 /* delay and try again */
60d3f5b0 6439 usleep_range(10000, 20000);
eb6b2ae9 6440 }
3f4336f3
SC		 6441}
6442
6f039790 6443static int hpsa_enter_simple_mode(struct ctlr_info *h)
3f4336f3
SC		 6444{
6445 u32 trans_support;
6446
6447 trans_support = readl(&(h->cfgtable->TransportSupport));
6448 if (!(trans_support & SIMPLE_MODE))
6449 return -ENOTSUPP;
6450
6451 h->max_commands = readl(&(h->cfgtable->CmdsOutMax));
283b4a9b 6452
3f4336f3
SC		 6453 /* Update the field, and then ring the doorbell */
6454 writel(CFGTBL_Trans_Simple, &(h->cfgtable->HostWrite.TransportRequest));
b9af4937 6455 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
3f4336f3
SC		 6456 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
6457 hpsa_wait_for_mode_change_ack(h);
eb6b2ae9 6458 print_cfg_table(&h->pdev->dev, h->cfgtable);
283b4a9b
SC		 6459 if (!(readl(&(h->cfgtable->TransportActive)) & CFGTBL_Trans_Simple))
6460 goto error;
960a30e7 6461 h->transMethod = CFGTBL_Trans_Simple;
eb6b2ae9 6462 return 0;
283b4a9b
SC		 6463error:
6464 dev_warn(&h->pdev->dev, "unable to get board into simple mode\n");
6465 return -ENODEV;
eb6b2ae9
SC		 6466}
6467
6f039790 6468static int hpsa_pci_init(struct ctlr_info *h)
77c4495c 6469{
eb6b2ae9 6470 int prod_index, err;
edd16368 6471
e5c880d1
SC		 6472 prod_index = hpsa_lookup_board_id(h->pdev, &h->board_id);
6473 if (prod_index < 0)
6474 return -ENODEV;
6475 h->product_name = products[prod_index].product_name;
6476 h->access = *(products[prod_index].access);
edd16368 6477
e5a44df8
MG		 6478 pci_disable_link_state(h->pdev, PCIE_LINK_STATE_L0S |
6479 PCIE_LINK_STATE_L1 | PCIE_LINK_STATE_CLKPM);
6480
55c06c71 6481 err = pci_enable_device(h->pdev);
edd16368 6482 if (err) {
55c06c71 6483 dev_warn(&h->pdev->dev, "unable to enable PCI device\n");
edd16368
SC		 6484 return err;
6485 }
6486
5cb460a6
SC		 6487 /* Enable bus mastering (pci_disable_device may disable this) */
6488 pci_set_master(h->pdev);
6489
f79cfec6 6490 err = pci_request_regions(h->pdev, HPSA);
edd16368 6491 if (err) {
55c06c71
SC		 6492 dev_err(&h->pdev->dev,
6493 "cannot obtain PCI resources, aborting\n");
edd16368
SC		 6494 return err;
6495 }
6b3f4c52 6496 hpsa_interrupt_mode(h);
12d2cd47 6497 err = hpsa_pci_find_memory_BAR(h->pdev, &h->paddr);
3a7774ce 6498 if (err)
edd16368 6499 goto err_out_free_res;
edd16368 6500 h->vaddr = remap_pci_mem(h->paddr, 0x250);
204892e9
SC		 6501 if (!h->vaddr) {
6502 err = -ENOMEM;
6503 goto err_out_free_res;
6504 }
fe5389c8 6505 err = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
2c4c8c8b 6506 if (err)
edd16368 6507 goto err_out_free_res;
77c4495c
SC		 6508 err = hpsa_find_cfgtables(h);
6509 if (err)
edd16368 6510 goto err_out_free_res;
b93d7536 6511 hpsa_find_board_params(h);
edd16368 6512
76c46e49 6513 if (!hpsa_CISS_signature_present(h)) {
edd16368
SC		 6514 err = -ENODEV;
6515 goto err_out_free_res;
6516 }
97a5e98c 6517 hpsa_set_driver_support_bits(h);
3d0eab67 6518 hpsa_p600_dma_prefetch_quirk(h);
eb6b2ae9
SC		 6519 err = hpsa_enter_simple_mode(h);
6520 if (err)
edd16368 6521 goto err_out_free_res;
edd16368
SC		 6522 return 0;
6523
6524err_out_free_res:
204892e9
SC		 6525 if (h->transtable)
6526 iounmap(h->transtable);
6527 if (h->cfgtable)
6528 iounmap(h->cfgtable);
6529 if (h->vaddr)
6530 iounmap(h->vaddr);
f0bd0b68 6531 pci_disable_device(h->pdev);
55c06c71 6532 pci_release_regions(h->pdev);
edd16368
SC		 6533 return err;
6534}
6535
6f039790 6536static void hpsa_hba_inquiry(struct ctlr_info *h)
339b2b14
SC		 6537{
6538 int rc;
6539
6540#define HBA_INQUIRY_BYTE_COUNT 64
6541 h->hba_inquiry_data = kmalloc(HBA_INQUIRY_BYTE_COUNT, GFP_KERNEL);
6542 if (!h->hba_inquiry_data)
6543 return;
6544 rc = hpsa_scsi_do_inquiry(h, RAID_CTLR_LUNID, 0,
6545 h->hba_inquiry_data, HBA_INQUIRY_BYTE_COUNT);
6546 if (rc != 0) {
6547 kfree(h->hba_inquiry_data);
6548 h->hba_inquiry_data = NULL;
6549 }
6550}
6551
6f039790 6552static int hpsa_init_reset_devices(struct pci_dev *pdev)
4c2a8c40 6553{
1df8552a 6554 int rc, i;
4c2a8c40
SC		 6555
6556 if (!reset_devices)
6557 return 0;
6558
1df8552a
SC		 6559 /* Reset the controller with a PCI power-cycle or via doorbell */
6560 rc = hpsa_kdump_hard_reset_controller(pdev);
4c2a8c40 6561
1df8552a
SC		 6562 /* -ENOTSUPP here means we cannot reset the controller
6563 * but it's already (and still) up and running in
18867659
SC		 6564 * "performant mode". Or, it might be 640x, which can't reset
6565 * due to concerns about shared bbwc between 6402/6404 pair.
1df8552a
SC		 6566 */
6567 if (rc == -ENOTSUPP)
64670ac8 6568 return rc; /* just try to do the kdump anyhow. */
1df8552a
SC		 6569 if (rc)
6570 return -ENODEV;
4c2a8c40
SC		 6571
6572 /* Now try to get the controller to respond to a no-op */
2b870cb3 6573 dev_warn(&pdev->dev, "Waiting for controller to respond to no-op\n");
4c2a8c40
SC		 6574 for (i = 0; i < HPSA_POST_RESET_NOOP_RETRIES; i++) {
6575 if (hpsa_noop(pdev) == 0)
6576 break;
6577 else
6578 dev_warn(&pdev->dev, "no-op failed%s\n",
6579 (i < 11 ? "; re-trying" : ""));
6580 }
6581 return 0;
6582}
6583
6f039790 6584static int hpsa_allocate_cmd_pool(struct ctlr_info *h)
2e9d1b36
SC		 6585{
6586 h->cmd_pool_bits = kzalloc(
6587 DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG) *
6588 sizeof(unsigned long), GFP_KERNEL);
6589 h->cmd_pool = pci_alloc_consistent(h->pdev,
6590 h->nr_cmds * sizeof(*h->cmd_pool),
6591 &(h->cmd_pool_dhandle));
6592 h->errinfo_pool = pci_alloc_consistent(h->pdev,
6593 h->nr_cmds * sizeof(*h->errinfo_pool),
6594 &(h->errinfo_pool_dhandle));
6595 if ((h->cmd_pool_bits == NULL)
6596 || (h->cmd_pool == NULL)
6597 || (h->errinfo_pool == NULL)) {
6598 dev_err(&h->pdev->dev, "out of memory in %s", __func__);
6599 return -ENOMEM;
6600 }
6601 return 0;
6602}
6603
6604static void hpsa_free_cmd_pool(struct ctlr_info *h)
6605{
6606 kfree(h->cmd_pool_bits);
6607 if (h->cmd_pool)
6608 pci_free_consistent(h->pdev,
6609 h->nr_cmds * sizeof(struct CommandList),
6610 h->cmd_pool, h->cmd_pool_dhandle);
aca9012a
SC		 6611 if (h->ioaccel2_cmd_pool)
6612 pci_free_consistent(h->pdev,
6613 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
6614 h->ioaccel2_cmd_pool, h->ioaccel2_cmd_pool_dhandle);
2e9d1b36
SC		 6615 if (h->errinfo_pool)
6616 pci_free_consistent(h->pdev,
6617 h->nr_cmds * sizeof(struct ErrorInfo),
6618 h->errinfo_pool,
6619 h->errinfo_pool_dhandle);
e1f7de0c
MG		 6620 if (h->ioaccel_cmd_pool)
6621 pci_free_consistent(h->pdev,
6622 h->nr_cmds * sizeof(struct io_accel1_cmd),
6623 h->ioaccel_cmd_pool, h->ioaccel_cmd_pool_dhandle);
2e9d1b36
SC		 6624}
6625
41b3cf08
SC		 6626static void hpsa_irq_affinity_hints(struct ctlr_info *h)
6627{
6628 int i, cpu, rc;
6629
6630 cpu = cpumask_first(cpu_online_mask);
6631 for (i = 0; i < h->msix_vector; i++) {
6632 rc = irq_set_affinity_hint(h->intr[i], get_cpu_mask(cpu));
6633 cpu = cpumask_next(cpu, cpu_online_mask);
6634 }
6635}
6636
0ae01a32
SC		 6637static int hpsa_request_irq(struct ctlr_info *h,
6638 irqreturn_t (*msixhandler)(int, void *),
6639 irqreturn_t (*intxhandler)(int, void *))
6640{
254f796b 6641 int rc, i;
0ae01a32 6642
254f796b
MG		 6643 /*
6644 * initialize h->q[x] = x so that interrupt handlers know which
6645 * queue to process.
6646 */
6647 for (i = 0; i < MAX_REPLY_QUEUES; i++)
6648 h->q[i] = (u8) i;
6649
eee0f03a 6650 if (h->intr_mode == PERF_MODE_INT && h->msix_vector > 0) {
254f796b 6651 /* If performant mode and MSI-X, use multiple reply queues */
eee0f03a 6652 for (i = 0; i < h->msix_vector; i++)
254f796b
MG		 6653 rc = request_irq(h->intr[i], msixhandler,
6654 0, h->devname,
6655 &h->q[i]);
41b3cf08 6656 hpsa_irq_affinity_hints(h);
254f796b
MG		 6657 } else {
6658 /* Use single reply pool */
eee0f03a 6659 if (h->msix_vector > 0 || h->msi_vector) {
254f796b
MG		 6660 rc = request_irq(h->intr[h->intr_mode],
6661 msixhandler, 0, h->devname,
6662 &h->q[h->intr_mode]);
6663 } else {
6664 rc = request_irq(h->intr[h->intr_mode],
6665 intxhandler, IRQF_SHARED, h->devname,
6666 &h->q[h->intr_mode]);
6667 }
6668 }
0ae01a32
SC		 6669 if (rc) {
6670 dev_err(&h->pdev->dev, "unable to get irq %d for %s\n",
6671 h->intr[h->intr_mode], h->devname);
6672 return -ENODEV;
6673 }
6674 return 0;
6675}
6676
6f039790 6677static int hpsa_kdump_soft_reset(struct ctlr_info *h)
64670ac8
SC		 6678{
6679 if (hpsa_send_host_reset(h, RAID_CTLR_LUNID,
6680 HPSA_RESET_TYPE_CONTROLLER)) {
6681 dev_warn(&h->pdev->dev, "Resetting array controller failed.\n");
6682 return -EIO;
6683 }
6684
6685 dev_info(&h->pdev->dev, "Waiting for board to soft reset.\n");
6686 if (hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_NOT_READY)) {
6687 dev_warn(&h->pdev->dev, "Soft reset had no effect.\n");
6688 return -1;
6689 }
6690
6691 dev_info(&h->pdev->dev, "Board reset, awaiting READY status.\n");
6692 if (hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY)) {
6693 dev_warn(&h->pdev->dev, "Board failed to become ready "
6694 "after soft reset.\n");
6695 return -1;
6696 }
6697
6698 return 0;
6699}
6700
254f796b
MG		 6701static void free_irqs(struct ctlr_info *h)
6702{
6703 int i;
6704
6705 if (!h->msix_vector || h->intr_mode != PERF_MODE_INT) {
6706 /* Single reply queue, only one irq to free */
6707 i = h->intr_mode;
41b3cf08 6708 irq_set_affinity_hint(h->intr[i], NULL);
254f796b
MG		 6709 free_irq(h->intr[i], &h->q[i]);
6710 return;
6711 }
6712
41b3cf08
SC		 6713 for (i = 0; i < h->msix_vector; i++) {
6714 irq_set_affinity_hint(h->intr[i], NULL);
254f796b 6715 free_irq(h->intr[i], &h->q[i]);
41b3cf08 6716 }
254f796b
MG		 6717}
6718
0097f0f4 6719static void hpsa_free_irqs_and_disable_msix(struct ctlr_info *h)
64670ac8 6720{
254f796b 6721 free_irqs(h);
64670ac8 6722#ifdef CONFIG_PCI_MSI
0097f0f4
SC		 6723 if (h->msix_vector) {
6724 if (h->pdev->msix_enabled)
6725 pci_disable_msix(h->pdev);
6726 } else if (h->msi_vector) {
6727 if (h->pdev->msi_enabled)
6728 pci_disable_msi(h->pdev);
6729 }
64670ac8 6730#endif /* CONFIG_PCI_MSI */
0097f0f4
SC		 6731}
6732
072b0518
SC		 6733static void hpsa_free_reply_queues(struct ctlr_info *h)
6734{
6735 int i;
6736
6737 for (i = 0; i < h->nreply_queues; i++) {
6738 if (!h->reply_queue[i].head)
6739 continue;
6740 pci_free_consistent(h->pdev, h->reply_queue_size,
6741 h->reply_queue[i].head, h->reply_queue[i].busaddr);
6742 h->reply_queue[i].head = NULL;
6743 h->reply_queue[i].busaddr = 0;
6744 }
6745}
6746
0097f0f4
SC		 6747static void hpsa_undo_allocations_after_kdump_soft_reset(struct ctlr_info *h)
6748{
6749 hpsa_free_irqs_and_disable_msix(h);
64670ac8
SC		 6750 hpsa_free_sg_chain_blocks(h);
6751 hpsa_free_cmd_pool(h);
e1f7de0c 6752 kfree(h->ioaccel1_blockFetchTable);
64670ac8 6753 kfree(h->blockFetchTable);
072b0518 6754 hpsa_free_reply_queues(h);
64670ac8
SC		 6755 if (h->vaddr)
6756 iounmap(h->vaddr);
6757 if (h->transtable)
6758 iounmap(h->transtable);
6759 if (h->cfgtable)
6760 iounmap(h->cfgtable);
6761 pci_release_regions(h->pdev);
6762 kfree(h);
6763}
6764
a0c12413
SC		 6765/* Called when controller lockup detected. */
6766static void fail_all_cmds_on_list(struct ctlr_info *h, struct list_head *list)
6767{
6768 struct CommandList *c = NULL;
6769
6770 assert_spin_locked(&h->lock);
6771 /* Mark all outstanding commands as failed and complete them. */
6772 while (!list_empty(list)) {
6773 c = list_entry(list->next, struct CommandList, list);
6774 c->err_info->CommandStatus = CMD_HARDWARE_ERR;
5a3d16f5 6775 finish_cmd(c);
a0c12413
SC		 6776 }
6777}
6778
094963da
SC		 6779static void set_lockup_detected_for_all_cpus(struct ctlr_info *h, u32 value)
6780{
6781 int i, cpu;
6782
6783 cpu = cpumask_first(cpu_online_mask);
6784 for (i = 0; i < num_online_cpus(); i++) {
6785 u32 *lockup_detected;
6786 lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
6787 *lockup_detected = value;
6788 cpu = cpumask_next(cpu, cpu_online_mask);
6789 }
6790 wmb(); /* be sure the per-cpu variables are out to memory */
6791}
6792
a0c12413
SC		 6793static void controller_lockup_detected(struct ctlr_info *h)
6794{
6795 unsigned long flags;
094963da 6796 u32 lockup_detected;
a0c12413 6797
a0c12413
SC		 6798 h->access.set_intr_mask(h, HPSA_INTR_OFF);
6799 spin_lock_irqsave(&h->lock, flags);
094963da
SC		 6800 lockup_detected = readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
6801 if (!lockup_detected) {
6802 /* no heartbeat, but controller gave us a zero. */
6803 dev_warn(&h->pdev->dev,
6804 "lockup detected but scratchpad register is zero\n");
6805 lockup_detected = 0xffffffff;
6806 }
6807 set_lockup_detected_for_all_cpus(h, lockup_detected);
a0c12413
SC		 6808 spin_unlock_irqrestore(&h->lock, flags);
6809 dev_warn(&h->pdev->dev, "Controller lockup detected: 0x%08x\n",
094963da 6810 lockup_detected);
a0c12413
SC		 6811 pci_disable_device(h->pdev);
6812 spin_lock_irqsave(&h->lock, flags);
6813 fail_all_cmds_on_list(h, &h->cmpQ);
6814 fail_all_cmds_on_list(h, &h->reqQ);
6815 spin_unlock_irqrestore(&h->lock, flags);
6816}
6817
a0c12413
SC		 6818static void detect_controller_lockup(struct ctlr_info *h)
6819{
6820 u64 now;
6821 u32 heartbeat;
6822 unsigned long flags;
6823
a0c12413
SC		 6824 now = get_jiffies_64();
6825 /* If we've received an interrupt recently, we're ok. */
6826 if (time_after64(h->last_intr_timestamp +
e85c5974 6827 (h->heartbeat_sample_interval), now))
a0c12413
SC		 6828 return;
6829
6830 /*
6831 * If we've already checked the heartbeat recently, we're ok.
6832 * This could happen if someone sends us a signal. We
6833 * otherwise don't care about signals in this thread.
6834 */
6835 if (time_after64(h->last_heartbeat_timestamp +
e85c5974 6836 (h->heartbeat_sample_interval), now))
a0c12413
SC		 6837 return;
6838
6839 /* If heartbeat has not changed since we last looked, we're not ok. */
6840 spin_lock_irqsave(&h->lock, flags);
6841 heartbeat = readl(&h->cfgtable->HeartBeat);
6842 spin_unlock_irqrestore(&h->lock, flags);
6843 if (h->last_heartbeat == heartbeat) {
6844 controller_lockup_detected(h);
6845 return;
6846 }
6847
6848 /* We're ok. */
6849 h->last_heartbeat = heartbeat;
6850 h->last_heartbeat_timestamp = now;
6851}
6852
9846590e 6853static void hpsa_ack_ctlr_events(struct ctlr_info *h)
76438d08
SC		 6854{
6855 int i;
6856 char *event_type;
6857
e863d68e
ST		 6858 /* Clear the driver-requested rescan flag */
6859 h->drv_req_rescan = 0;
6860
76438d08 6861 /* Ask the controller to clear the events we're handling. */
1f7cee8c
SC		 6862 if ((h->transMethod & (CFGTBL_Trans_io_accel1
6863 | CFGTBL_Trans_io_accel2)) &&
76438d08
SC		 6864 (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE ||
6865 h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)) {
6866
6867 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE)
6868 event_type = "state change";
6869 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)
6870 event_type = "configuration change";
6871 /* Stop sending new RAID offload reqs via the IO accelerator */
6872 scsi_block_requests(h->scsi_host);
6873 for (i = 0; i < h->ndevices; i++)
6874 h->dev[i]->offload_enabled = 0;
23100dd9 6875 hpsa_drain_accel_commands(h);
76438d08
SC		 6876 /* Set 'accelerator path config change' bit */
6877 dev_warn(&h->pdev->dev,
6878 "Acknowledging event: 0x%08x (HP SSD Smart Path %s)\n",
6879 h->events, event_type);
6880 writel(h->events, &(h->cfgtable->clear_event_notify));
6881 /* Set the "clear event notify field update" bit 6 */
6882 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
6883 /* Wait until ctlr clears 'clear event notify field', bit 6 */
6884 hpsa_wait_for_clear_event_notify_ack(h);
6885 scsi_unblock_requests(h->scsi_host);
6886 } else {
6887 /* Acknowledge controller notification events. */
6888 writel(h->events, &(h->cfgtable->clear_event_notify));
6889 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
6890 hpsa_wait_for_clear_event_notify_ack(h);
6891#if 0
6892 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
6893 hpsa_wait_for_mode_change_ack(h);
6894#endif
6895 }
9846590e 6896 return;
76438d08
SC		 6897}
6898
6899/* Check a register on the controller to see if there are configuration
6900 * changes (added/changed/removed logical drives, etc.) which mean that
e863d68e
ST		 6901 * we should rescan the controller for devices.
6902 * Also check flag for driver-initiated rescan.
76438d08 6903 */
9846590e 6904static int hpsa_ctlr_needs_rescan(struct ctlr_info *h)
76438d08 6905{
9846590e
SC		 6906 if (h->drv_req_rescan)
6907 return 1;
6908
76438d08 6909 if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
9846590e 6910 return 0;
76438d08
SC		 6911
6912 h->events = readl(&(h->cfgtable->event_notify));
9846590e
SC		 6913 return h->events & RESCAN_REQUIRED_EVENT_BITS;
6914}
76438d08 6915
9846590e
SC		 6916/*
6917 * Check if any of the offline devices have become ready
6918 */
6919static int hpsa_offline_devices_ready(struct ctlr_info *h)
6920{
6921 unsigned long flags;
6922 struct offline_device_entry *d;
6923 struct list_head *this, *tmp;
6924
6925 spin_lock_irqsave(&h->offline_device_lock, flags);
6926 list_for_each_safe(this, tmp, &h->offline_device_list) {
6927 d = list_entry(this, struct offline_device_entry,
6928 offline_list);
6929 spin_unlock_irqrestore(&h->offline_device_lock, flags);
6930 if (!hpsa_volume_offline(h, d->scsi3addr))
6931 return 1;
6932 spin_lock_irqsave(&h->offline_device_lock, flags);
6933 }
6934 spin_unlock_irqrestore(&h->offline_device_lock, flags);
6935 return 0;
76438d08
SC		 6936}
6937
9846590e 6938
8a98db73 6939static void hpsa_monitor_ctlr_worker(struct work_struct *work)
a0c12413
SC		 6940{
6941 unsigned long flags;
8a98db73
SC		 6942 struct ctlr_info *h = container_of(to_delayed_work(work),
6943 struct ctlr_info, monitor_ctlr_work);
6944 detect_controller_lockup(h);
094963da 6945 if (lockup_detected(h))
8a98db73 6946 return;
9846590e
SC		 6947
6948 if (hpsa_ctlr_needs_rescan(h) || hpsa_offline_devices_ready(h)) {
6949 scsi_host_get(h->scsi_host);
6950 h->drv_req_rescan = 0;
6951 hpsa_ack_ctlr_events(h);
6952 hpsa_scan_start(h->scsi_host);
6953 scsi_host_put(h->scsi_host);
6954 }
6955
8a98db73
SC		 6956 spin_lock_irqsave(&h->lock, flags);
6957 if (h->remove_in_progress) {
6958 spin_unlock_irqrestore(&h->lock, flags);
a0c12413
SC		 6959 return;
6960 }
8a98db73
SC		 6961 schedule_delayed_work(&h->monitor_ctlr_work,
6962 h->heartbeat_sample_interval);
6963 spin_unlock_irqrestore(&h->lock, flags);
a0c12413
SC		 6964}
6965
6f039790 6966static int hpsa_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
edd16368 6967{
4c2a8c40 6968 int dac, rc;
edd16368 6969 struct ctlr_info *h;
64670ac8
SC		 6970 int try_soft_reset = 0;
6971 unsigned long flags;
edd16368
SC		 6972
6973 if (number_of_controllers == 0)
6974 printk(KERN_INFO DRIVER_NAME "\n");
edd16368 6975
4c2a8c40 6976 rc = hpsa_init_reset_devices(pdev);
64670ac8
SC		 6977 if (rc) {
6978 if (rc != -ENOTSUPP)
6979 return rc;
6980 /* If the reset fails in a particular way (it has no way to do
6981 * a proper hard reset, so returns -ENOTSUPP) we can try to do
6982 * a soft reset once we get the controller configured up to the
6983 * point that it can accept a command.
6984 */
6985 try_soft_reset = 1;
6986 rc = 0;
6987 }
6988
6989reinit_after_soft_reset:
edd16368 6990
303932fd
DB		 6991 /* Command structures must be aligned on a 32-byte boundary because
6992 * the 5 lower bits of the address are used by the hardware. and by
6993 * the driver. See comments in hpsa.h for more info.
6994 */
303932fd 6995 BUILD_BUG_ON(sizeof(struct CommandList) % COMMANDLIST_ALIGNMENT);
edd16368
SC		 6996 h = kzalloc(sizeof(*h), GFP_KERNEL);
6997 if (!h)
ecd9aad4 6998 return -ENOMEM;
edd16368 6999
55c06c71 7000 h->pdev = pdev;
a9a3a273 7001 h->intr_mode = hpsa_simple_mode ? SIMPLE_MODE_INT : PERF_MODE_INT;
9e0fc764
SC		 7002 INIT_LIST_HEAD(&h->cmpQ);
7003 INIT_LIST_HEAD(&h->reqQ);
9846590e 7004 INIT_LIST_HEAD(&h->offline_device_list);
6eaf46fd 7005 spin_lock_init(&h->lock);
9846590e 7006 spin_lock_init(&h->offline_device_lock);
6eaf46fd 7007 spin_lock_init(&h->scan_lock);
0390f0c0 7008 spin_lock_init(&h->passthru_count_lock);
094963da
SC		 7009
7010 /* Allocate and clear per-cpu variable lockup_detected */
7011 h->lockup_detected = alloc_percpu(u32);
7012 if (!h->lockup_detected)
7013 goto clean1;
7014 set_lockup_detected_for_all_cpus(h, 0);
7015
55c06c71 7016 rc = hpsa_pci_init(h);
ecd9aad4 7017 if (rc != 0)
edd16368
SC		 7018 goto clean1;
7019
f79cfec6 7020 sprintf(h->devname, HPSA "%d", number_of_controllers);
edd16368
SC		 7021 h->ctlr = number_of_controllers;
7022 number_of_controllers++;
edd16368
SC		 7023
7024 /* configure PCI DMA stuff */
ecd9aad4
SC		 7025 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
7026 if (rc == 0) {
edd16368 7027 dac = 1;
ecd9aad4
SC		 7028 } else {
7029 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7030 if (rc == 0) {
7031 dac = 0;
7032 } else {
7033 dev_err(&pdev->dev, "no suitable DMA available\n");
7034 goto clean1;
7035 }
edd16368
SC		 7036 }
7037
7038 /* make sure the board interrupts are off */
7039 h->access.set_intr_mask(h, HPSA_INTR_OFF);
10f66018 7040
0ae01a32 7041 if (hpsa_request_irq(h, do_hpsa_intr_msi, do_hpsa_intr_intx))
edd16368 7042 goto clean2;
303932fd
DB		 7043 dev_info(&pdev->dev, "%s: <0x%x> at IRQ %d%s using DAC\n",
7044 h->devname, pdev->device,
a9a3a273 7045 h->intr[h->intr_mode], dac ? "" : " not");
2e9d1b36 7046 if (hpsa_allocate_cmd_pool(h))
edd16368 7047 goto clean4;
33a2ffce
SC		 7048 if (hpsa_allocate_sg_chain_blocks(h))
7049 goto clean4;
a08a8471
SC		 7050 init_waitqueue_head(&h->scan_wait_queue);
7051 h->scan_finished = 1; /* no scan currently in progress */
edd16368
SC		 7052
7053 pci_set_drvdata(pdev, h);
9a41338e 7054 h->ndevices = 0;
316b221a 7055 h->hba_mode_enabled = 0;
9a41338e
SC		 7056 h->scsi_host = NULL;
7057 spin_lock_init(&h->devlock);
64670ac8
SC		 7058 hpsa_put_ctlr_into_performant_mode(h);
7059
7060 /* At this point, the controller is ready to take commands.
7061 * Now, if reset_devices and the hard reset didn't work, try
7062 * the soft reset and see if that works.
7063 */
7064 if (try_soft_reset) {
7065
7066 /* This is kind of gross. We may or may not get a completion
7067 * from the soft reset command, and if we do, then the value
7068 * from the fifo may or may not be valid. So, we wait 10 secs
7069 * after the reset throwing away any completions we get during
7070 * that time. Unregister the interrupt handler and register
7071 * fake ones to scoop up any residual completions.
7072 */
7073 spin_lock_irqsave(&h->lock, flags);
7074 h->access.set_intr_mask(h, HPSA_INTR_OFF);
7075 spin_unlock_irqrestore(&h->lock, flags);
254f796b 7076 free_irqs(h);
64670ac8
SC		 7077 rc = hpsa_request_irq(h, hpsa_msix_discard_completions,
7078 hpsa_intx_discard_completions);
7079 if (rc) {
7080 dev_warn(&h->pdev->dev, "Failed to request_irq after "
7081 "soft reset.\n");
7082 goto clean4;
7083 }
7084
7085 rc = hpsa_kdump_soft_reset(h);
7086 if (rc)
7087 /* Neither hard nor soft reset worked, we're hosed. */
7088 goto clean4;
7089
7090 dev_info(&h->pdev->dev, "Board READY.\n");
7091 dev_info(&h->pdev->dev,
7092 "Waiting for stale completions to drain.\n");
7093 h->access.set_intr_mask(h, HPSA_INTR_ON);
7094 msleep(10000);
7095 h->access.set_intr_mask(h, HPSA_INTR_OFF);
7096
7097 rc = controller_reset_failed(h->cfgtable);
7098 if (rc)
7099 dev_info(&h->pdev->dev,
7100 "Soft reset appears to have failed.\n");
7101
7102 /* since the controller's reset, we have to go back and re-init
7103 * everything. Easiest to just forget what we've done and do it
7104 * all over again.
7105 */
7106 hpsa_undo_allocations_after_kdump_soft_reset(h);
7107 try_soft_reset = 0;
7108 if (rc)
7109 /* don't go to clean4, we already unallocated */
7110 return -ENODEV;
7111
7112 goto reinit_after_soft_reset;
7113 }
edd16368 7114
316b221a
SC		 7115 /* Enable Accelerated IO path at driver layer */
7116 h->acciopath_status = 1;
da0697bd 7117
e863d68e
ST		 7118 h->drv_req_rescan = 0;
7119
edd16368
SC		 7120 /* Turn the interrupts on so we can service requests */
7121 h->access.set_intr_mask(h, HPSA_INTR_ON);
7122
339b2b14 7123 hpsa_hba_inquiry(h);
edd16368 7124 hpsa_register_scsi(h); /* hook ourselves into SCSI subsystem */
8a98db73
SC		 7125
7126 /* Monitor the controller for firmware lockups */
7127 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
7128 INIT_DELAYED_WORK(&h->monitor_ctlr_work, hpsa_monitor_ctlr_worker);
7129 schedule_delayed_work(&h->monitor_ctlr_work,
7130 h->heartbeat_sample_interval);
88bf6d62 7131 return 0;
edd16368
SC		 7132
7133clean4:
33a2ffce 7134 hpsa_free_sg_chain_blocks(h);
2e9d1b36 7135 hpsa_free_cmd_pool(h);
254f796b 7136 free_irqs(h);
edd16368
SC		 7137clean2:
7138clean1:
094963da
SC		 7139 if (h->lockup_detected)
7140 free_percpu(h->lockup_detected);
edd16368 7141 kfree(h);
ecd9aad4 7142 return rc;
edd16368
SC		 7143}
7144
7145static void hpsa_flush_cache(struct ctlr_info *h)
7146{
7147 char *flush_buf;
7148 struct CommandList *c;
702890e3
SC		 7149
7150 /* Don't bother trying to flush the cache if locked up */
094963da 7151 if (unlikely(lockup_detected(h)))
702890e3 7152 return;
edd16368
SC		 7153 flush_buf = kzalloc(4, GFP_KERNEL);
7154 if (!flush_buf)
7155 return;
7156
7157 c = cmd_special_alloc(h);
7158 if (!c) {
7159 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
7160 goto out_of_memory;
7161 }
a2dac136
SC		 7162 if (fill_cmd(c, HPSA_CACHE_FLUSH, h, flush_buf, 4, 0,
7163 RAID_CTLR_LUNID, TYPE_CMD)) {
7164 goto out;
7165 }
edd16368
SC		 7166 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_TODEVICE);
7167 if (c->err_info->CommandStatus != 0)
a2dac136 7168out:
edd16368
SC		 7169 dev_warn(&h->pdev->dev,
7170 "error flushing cache on controller\n");
7171 cmd_special_free(h, c);
7172out_of_memory:
7173 kfree(flush_buf);
7174}
7175
7176static void hpsa_shutdown(struct pci_dev *pdev)
7177{
7178 struct ctlr_info *h;
7179
7180 h = pci_get_drvdata(pdev);
7181 /* Turn board interrupts off and send the flush cache command
7182 * sendcmd will turn off interrupt, and send the flush...
7183 * To write all data in the battery backed cache to disks
7184 */
7185 hpsa_flush_cache(h);
7186 h->access.set_intr_mask(h, HPSA_INTR_OFF);
0097f0f4 7187 hpsa_free_irqs_and_disable_msix(h);
edd16368
SC		 7188}
7189
6f039790 7190static void hpsa_free_device_info(struct ctlr_info *h)
55e14e76
SC		 7191{
7192 int i;
7193
7194 for (i = 0; i < h->ndevices; i++)
7195 kfree(h->dev[i]);
7196}
7197
6f039790 7198static void hpsa_remove_one(struct pci_dev *pdev)
edd16368
SC		 7199{
7200 struct ctlr_info *h;
8a98db73 7201 unsigned long flags;
edd16368
SC		 7202
7203 if (pci_get_drvdata(pdev) == NULL) {
a0c12413 7204 dev_err(&pdev->dev, "unable to remove device\n");
edd16368
SC		 7205 return;
7206 }
7207 h = pci_get_drvdata(pdev);
8a98db73
SC		 7208
7209 /* Get rid of any controller monitoring work items */
7210 spin_lock_irqsave(&h->lock, flags);
7211 h->remove_in_progress = 1;
7212 cancel_delayed_work(&h->monitor_ctlr_work);
7213 spin_unlock_irqrestore(&h->lock, flags);
7214
edd16368
SC		 7215 hpsa_unregister_scsi(h); /* unhook from SCSI subsystem */
7216 hpsa_shutdown(pdev);
7217 iounmap(h->vaddr);
204892e9
SC		 7218 iounmap(h->transtable);
7219 iounmap(h->cfgtable);
55e14e76 7220 hpsa_free_device_info(h);
33a2ffce 7221 hpsa_free_sg_chain_blocks(h);
edd16368
SC		 7222 pci_free_consistent(h->pdev,
7223 h->nr_cmds * sizeof(struct CommandList),
7224 h->cmd_pool, h->cmd_pool_dhandle);
7225 pci_free_consistent(h->pdev,
7226 h->nr_cmds * sizeof(struct ErrorInfo),
7227 h->errinfo_pool, h->errinfo_pool_dhandle);
072b0518 7228 hpsa_free_reply_queues(h);
edd16368 7229 kfree(h->cmd_pool_bits);
303932fd 7230 kfree(h->blockFetchTable);
e1f7de0c 7231 kfree(h->ioaccel1_blockFetchTable);
aca9012a 7232 kfree(h->ioaccel2_blockFetchTable);
339b2b14 7233 kfree(h->hba_inquiry_data);
f0bd0b68 7234 pci_disable_device(pdev);
edd16368 7235 pci_release_regions(pdev);
094963da 7236 free_percpu(h->lockup_detected);
edd16368
SC		 7237 kfree(h);
7238}
7239
7240static int hpsa_suspend(__attribute__((unused)) struct pci_dev *pdev,
7241 __attribute__((unused)) pm_message_t state)
7242{
7243 return -ENOSYS;
7244}
7245
7246static int hpsa_resume(__attribute__((unused)) struct pci_dev *pdev)
7247{
7248 return -ENOSYS;
7249}
7250
7251static struct pci_driver hpsa_pci_driver = {
f79cfec6 7252 .name = HPSA,
edd16368 7253 .probe = hpsa_init_one,
6f039790 7254 .remove = hpsa_remove_one,
edd16368
SC		 7255 .id_table = hpsa_pci_device_id, /* id_table */
7256 .shutdown = hpsa_shutdown,
7257 .suspend = hpsa_suspend,
7258 .resume = hpsa_resume,
7259};
7260
303932fd
DB		 7261/* Fill in bucket_map[], given nsgs (the max number of
7262 * scatter gather elements supported) and bucket[],
7263 * which is an array of 8 integers. The bucket[] array
7264 * contains 8 different DMA transfer sizes (in 16
7265 * byte increments) which the controller uses to fetch
7266 * commands. This function fills in bucket_map[], which
7267 * maps a given number of scatter gather elements to one of
7268 * the 8 DMA transfer sizes. The point of it is to allow the
7269 * controller to only do as much DMA as needed to fetch the
7270 * command, with the DMA transfer size encoded in the lower
7271 * bits of the command address.
7272 */
7273static void calc_bucket_map(int bucket[], int num_buckets,
e1f7de0c 7274 int nsgs, int min_blocks, int *bucket_map)
303932fd
DB		 7275{
7276 int i, j, b, size;
7277
303932fd
DB		 7278 /* Note, bucket_map must have nsgs+1 entries. */
7279 for (i = 0; i <= nsgs; i++) {
7280 /* Compute size of a command with i SG entries */
e1f7de0c 7281 size = i + min_blocks;
303932fd
DB		 7282 b = num_buckets; /* Assume the biggest bucket */
7283 /* Find the bucket that is just big enough */
e1f7de0c 7284 for (j = 0; j < num_buckets; j++) {
303932fd
DB		 7285 if (bucket[j] >= size) {
7286 b = j;
7287 break;
7288 }
7289 }
7290 /* for a command with i SG entries, use bucket b. */
7291 bucket_map[i] = b;
7292 }
7293}
7294
e1f7de0c 7295static void hpsa_enter_performant_mode(struct ctlr_info *h, u32 trans_support)
303932fd 7296{
6c311b57
SC		 7297 int i;
7298 unsigned long register_value;
e1f7de0c
MG		 7299 unsigned long transMethod = CFGTBL_Trans_Performant |
7300 (trans_support & CFGTBL_Trans_use_short_tags) |
b9af4937
SC		 7301 CFGTBL_Trans_enable_directed_msix |
7302 (trans_support & (CFGTBL_Trans_io_accel1 |
7303 CFGTBL_Trans_io_accel2));
e1f7de0c 7304 struct access_method access = SA5_performant_access;
def342bd
SC		 7305
7306 /* This is a bit complicated. There are 8 registers on
7307 * the controller which we write to to tell it 8 different
7308 * sizes of commands which there may be. It's a way of
7309 * reducing the DMA done to fetch each command. Encoded into
7310 * each command's tag are 3 bits which communicate to the controller
7311 * which of the eight sizes that command fits within. The size of
7312 * each command depends on how many scatter gather entries there are.
7313 * Each SG entry requires 16 bytes. The eight registers are programmed
7314 * with the number of 16-byte blocks a command of that size requires.
7315 * The smallest command possible requires 5 such 16 byte blocks.
d66ae08b 7316 * the largest command possible requires SG_ENTRIES_IN_CMD + 4 16-byte
def342bd
SC		 7317 * blocks. Note, this only extends to the SG entries contained
7318 * within the command block, and does not extend to chained blocks
7319 * of SG elements. bft[] contains the eight values we write to
7320 * the registers. They are not evenly distributed, but have more
7321 * sizes for small commands, and fewer sizes for larger commands.
7322 */
d66ae08b 7323 int bft[8] = {5, 6, 8, 10, 12, 20, 28, SG_ENTRIES_IN_CMD + 4};
b9af4937
SC		 7324#define MIN_IOACCEL2_BFT_ENTRY 5
7325#define HPSA_IOACCEL2_HEADER_SZ 4
7326 int bft2[16] = {MIN_IOACCEL2_BFT_ENTRY, 6, 7, 8, 9, 10, 11, 12,
7327 13, 14, 15, 16, 17, 18, 19,
7328 HPSA_IOACCEL2_HEADER_SZ + IOACCEL2_MAXSGENTRIES};
7329 BUILD_BUG_ON(ARRAY_SIZE(bft2) != 16);
7330 BUILD_BUG_ON(ARRAY_SIZE(bft) != 8);
7331 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) >
7332 16 * MIN_IOACCEL2_BFT_ENTRY);
7333 BUILD_BUG_ON(sizeof(struct ioaccel2_sg_element) != 16);
d66ae08b 7334 BUILD_BUG_ON(28 > SG_ENTRIES_IN_CMD + 4);
303932fd
DB		 7335 /* 5 = 1 s/g entry or 4k
7336 * 6 = 2 s/g entry or 8k
7337 * 8 = 4 s/g entry or 16k
7338 * 10 = 6 s/g entry or 24k
7339 */
303932fd 7340
b3a52e79
SC		 7341 /* If the controller supports either ioaccel method then
7342 * we can also use the RAID stack submit path that does not
7343 * perform the superfluous readl() after each command submission.
7344 */
7345 if (trans_support & (CFGTBL_Trans_io_accel1 | CFGTBL_Trans_io_accel2))
7346 access = SA5_performant_access_no_read;
7347
303932fd 7348 /* Controller spec: zero out this buffer. */
072b0518
SC		 7349 for (i = 0; i < h->nreply_queues; i++)
7350 memset(h->reply_queue[i].head, 0, h->reply_queue_size);
303932fd 7351
d66ae08b
SC		 7352 bft[7] = SG_ENTRIES_IN_CMD + 4;
7353 calc_bucket_map(bft, ARRAY_SIZE(bft),
e1f7de0c 7354 SG_ENTRIES_IN_CMD, 4, h->blockFetchTable);
303932fd
DB		 7355 for (i = 0; i < 8; i++)
7356 writel(bft[i], &h->transtable->BlockFetch[i]);
7357
7358 /* size of controller ring buffer */
7359 writel(h->max_commands, &h->transtable->RepQSize);
254f796b 7360 writel(h->nreply_queues, &h->transtable->RepQCount);
303932fd
DB		 7361 writel(0, &h->transtable->RepQCtrAddrLow32);
7362 writel(0, &h->transtable->RepQCtrAddrHigh32);
254f796b
MG		 7363
7364 for (i = 0; i < h->nreply_queues; i++) {
7365 writel(0, &h->transtable->RepQAddr[i].upper);
072b0518 7366 writel(h->reply_queue[i].busaddr,
254f796b
MG		 7367 &h->transtable->RepQAddr[i].lower);
7368 }
7369
b9af4937 7370 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
e1f7de0c
MG		 7371 writel(transMethod, &(h->cfgtable->HostWrite.TransportRequest));
7372 /*
7373 * enable outbound interrupt coalescing in accelerator mode;
7374 */
7375 if (trans_support & CFGTBL_Trans_io_accel1) {
7376 access = SA5_ioaccel_mode1_access;
7377 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
7378 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
c349775e
ST		 7379 } else {
7380 if (trans_support & CFGTBL_Trans_io_accel2) {
7381 access = SA5_ioaccel_mode2_access;
7382 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
7383 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
7384 }
e1f7de0c 7385 }
303932fd 7386 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
3f4336f3 7387 hpsa_wait_for_mode_change_ack(h);
303932fd
DB		 7388 register_value = readl(&(h->cfgtable->TransportActive));
7389 if (!(register_value & CFGTBL_Trans_Performant)) {
7390 dev_warn(&h->pdev->dev, "unable to get board into"
7391 " performant mode\n");
7392 return;
7393 }
960a30e7 7394 /* Change the access methods to the performant access methods */
e1f7de0c
MG		 7395 h->access = access;
7396 h->transMethod = transMethod;
7397
b9af4937
SC		 7398 if (!((trans_support & CFGTBL_Trans_io_accel1) ||
7399 (trans_support & CFGTBL_Trans_io_accel2)))
e1f7de0c
MG		 7400 return;
7401
b9af4937
SC		 7402 if (trans_support & CFGTBL_Trans_io_accel1) {
7403 /* Set up I/O accelerator mode */
7404 for (i = 0; i < h->nreply_queues; i++) {
7405 writel(i, h->vaddr + IOACCEL_MODE1_REPLY_QUEUE_INDEX);
7406 h->reply_queue[i].current_entry =
7407 readl(h->vaddr + IOACCEL_MODE1_PRODUCER_INDEX);
7408 }
7409 bft[7] = h->ioaccel_maxsg + 8;
7410 calc_bucket_map(bft, ARRAY_SIZE(bft), h->ioaccel_maxsg, 8,
7411 h->ioaccel1_blockFetchTable);
e1f7de0c 7412
b9af4937 7413 /* initialize all reply queue entries to unused */
072b0518
SC		 7414 for (i = 0; i < h->nreply_queues; i++)
7415 memset(h->reply_queue[i].head,
7416 (u8) IOACCEL_MODE1_REPLY_UNUSED,
7417 h->reply_queue_size);
e1f7de0c 7418
b9af4937
SC		 7419 /* set all the constant fields in the accelerator command
7420 * frames once at init time to save CPU cycles later.
7421 */
7422 for (i = 0; i < h->nr_cmds; i++) {
7423 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[i];
7424
7425 cp->function = IOACCEL1_FUNCTION_SCSIIO;
7426 cp->err_info = (u32) (h->errinfo_pool_dhandle +
7427 (i * sizeof(struct ErrorInfo)));
7428 cp->err_info_len = sizeof(struct ErrorInfo);
7429 cp->sgl_offset = IOACCEL1_SGLOFFSET;
7430 cp->host_context_flags = IOACCEL1_HCFLAGS_CISS_FORMAT;
7431 cp->timeout_sec = 0;
7432 cp->ReplyQueue = 0;
7433 cp->Tag.lower = (i << DIRECT_LOOKUP_SHIFT) |
7434 DIRECT_LOOKUP_BIT;
7435 cp->Tag.upper = 0;
7436 cp->host_addr.lower =
7437 (u32) (h->ioaccel_cmd_pool_dhandle +
7438 (i * sizeof(struct io_accel1_cmd)));
7439 cp->host_addr.upper = 0;
7440 }
7441 } else if (trans_support & CFGTBL_Trans_io_accel2) {
7442 u64 cfg_offset, cfg_base_addr_index;
7443 u32 bft2_offset, cfg_base_addr;
7444 int rc;
7445
7446 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
7447 &cfg_base_addr_index, &cfg_offset);
7448 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) != 64);
7449 bft2[15] = h->ioaccel_maxsg + HPSA_IOACCEL2_HEADER_SZ;
7450 calc_bucket_map(bft2, ARRAY_SIZE(bft2), h->ioaccel_maxsg,
7451 4, h->ioaccel2_blockFetchTable);
7452 bft2_offset = readl(&h->cfgtable->io_accel_request_size_offset);
7453 BUILD_BUG_ON(offsetof(struct CfgTable,
7454 io_accel_request_size_offset) != 0xb8);
7455 h->ioaccel2_bft2_regs =
7456 remap_pci_mem(pci_resource_start(h->pdev,
7457 cfg_base_addr_index) +
7458 cfg_offset + bft2_offset,
7459 ARRAY_SIZE(bft2) *
7460 sizeof(*h->ioaccel2_bft2_regs));
7461 for (i = 0; i < ARRAY_SIZE(bft2); i++)
7462 writel(bft2[i], &h->ioaccel2_bft2_regs[i]);
e1f7de0c 7463 }
b9af4937
SC		 7464 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
7465 hpsa_wait_for_mode_change_ack(h);
e1f7de0c
MG		 7466}
7467
7468static int hpsa_alloc_ioaccel_cmd_and_bft(struct ctlr_info *h)
7469{
283b4a9b
SC		 7470 h->ioaccel_maxsg =
7471 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
7472 if (h->ioaccel_maxsg > IOACCEL1_MAXSGENTRIES)
7473 h->ioaccel_maxsg = IOACCEL1_MAXSGENTRIES;
7474
e1f7de0c
MG		 7475 /* Command structures must be aligned on a 128-byte boundary
7476 * because the 7 lower bits of the address are used by the
7477 * hardware.
7478 */
e1f7de0c
MG		 7479 BUILD_BUG_ON(sizeof(struct io_accel1_cmd) %
7480 IOACCEL1_COMMANDLIST_ALIGNMENT);
7481 h->ioaccel_cmd_pool =
7482 pci_alloc_consistent(h->pdev,
7483 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
7484 &(h->ioaccel_cmd_pool_dhandle));
7485
7486 h->ioaccel1_blockFetchTable =
283b4a9b 7487 kmalloc(((h->ioaccel_maxsg + 1) *
e1f7de0c
MG		 7488 sizeof(u32)), GFP_KERNEL);
7489
7490 if ((h->ioaccel_cmd_pool == NULL) ||
7491 (h->ioaccel1_blockFetchTable == NULL))
7492 goto clean_up;
7493
7494 memset(h->ioaccel_cmd_pool, 0,
7495 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool));
7496 return 0;
7497
7498clean_up:
7499 if (h->ioaccel_cmd_pool)
7500 pci_free_consistent(h->pdev,
7501 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
7502 h->ioaccel_cmd_pool, h->ioaccel_cmd_pool_dhandle);
7503 kfree(h->ioaccel1_blockFetchTable);
7504 return 1;
6c311b57
SC		 7505}
7506
aca9012a
SC		 7507static int ioaccel2_alloc_cmds_and_bft(struct ctlr_info *h)
7508{
7509 /* Allocate ioaccel2 mode command blocks and block fetch table */
7510
7511 h->ioaccel_maxsg =
7512 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
7513 if (h->ioaccel_maxsg > IOACCEL2_MAXSGENTRIES)
7514 h->ioaccel_maxsg = IOACCEL2_MAXSGENTRIES;
7515
aca9012a
SC		 7516 BUILD_BUG_ON(sizeof(struct io_accel2_cmd) %
7517 IOACCEL2_COMMANDLIST_ALIGNMENT);
7518 h->ioaccel2_cmd_pool =
7519 pci_alloc_consistent(h->pdev,
7520 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
7521 &(h->ioaccel2_cmd_pool_dhandle));
7522
7523 h->ioaccel2_blockFetchTable =
7524 kmalloc(((h->ioaccel_maxsg + 1) *
7525 sizeof(u32)), GFP_KERNEL);
7526
7527 if ((h->ioaccel2_cmd_pool == NULL) ||
7528 (h->ioaccel2_blockFetchTable == NULL))
7529 goto clean_up;
7530
7531 memset(h->ioaccel2_cmd_pool, 0,
7532 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool));
7533 return 0;
7534
7535clean_up:
7536 if (h->ioaccel2_cmd_pool)
7537 pci_free_consistent(h->pdev,
7538 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
7539 h->ioaccel2_cmd_pool, h->ioaccel2_cmd_pool_dhandle);
7540 kfree(h->ioaccel2_blockFetchTable);
7541 return 1;
7542}
7543
6f039790 7544static void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h)
6c311b57
SC		 7545{
7546 u32 trans_support;
e1f7de0c
MG		 7547 unsigned long transMethod = CFGTBL_Trans_Performant |
7548 CFGTBL_Trans_use_short_tags;
254f796b 7549 int i;
6c311b57 7550
02ec19c8
SC		 7551 if (hpsa_simple_mode)
7552 return;
7553
67c99a72 7554 trans_support = readl(&(h->cfgtable->TransportSupport));
7555 if (!(trans_support & PERFORMANT_MODE))
7556 return;
7557
e1f7de0c
MG		 7558 /* Check for I/O accelerator mode support */
7559 if (trans_support & CFGTBL_Trans_io_accel1) {
7560 transMethod |= CFGTBL_Trans_io_accel1 |
7561 CFGTBL_Trans_enable_directed_msix;
7562 if (hpsa_alloc_ioaccel_cmd_and_bft(h))
7563 goto clean_up;
aca9012a
SC		 7564 } else {
7565 if (trans_support & CFGTBL_Trans_io_accel2) {
7566 transMethod |= CFGTBL_Trans_io_accel2 |
7567 CFGTBL_Trans_enable_directed_msix;
7568 if (ioaccel2_alloc_cmds_and_bft(h))
7569 goto clean_up;
7570 }
e1f7de0c
MG		 7571 }
7572
eee0f03a 7573 h->nreply_queues = h->msix_vector > 0 ? h->msix_vector : 1;
cba3d38b 7574 hpsa_get_max_perf_mode_cmds(h);
6c311b57 7575 /* Performant mode ring buffer and supporting data structures */
072b0518 7576 h->reply_queue_size = h->max_commands * sizeof(u64);
6c311b57 7577
254f796b 7578 for (i = 0; i < h->nreply_queues; i++) {
072b0518
SC		 7579 h->reply_queue[i].head = pci_alloc_consistent(h->pdev,
7580 h->reply_queue_size,
7581 &(h->reply_queue[i].busaddr));
7582 if (!h->reply_queue[i].head)
7583 goto clean_up;
254f796b
MG		 7584 h->reply_queue[i].size = h->max_commands;
7585 h->reply_queue[i].wraparound = 1; /* spec: init to 1 */
7586 h->reply_queue[i].current_entry = 0;
7587 }
7588
6c311b57 7589 /* Need a block fetch table for performant mode */
d66ae08b 7590 h->blockFetchTable = kmalloc(((SG_ENTRIES_IN_CMD + 1) *
6c311b57 7591 sizeof(u32)), GFP_KERNEL);
072b0518 7592 if (!h->blockFetchTable)
6c311b57
SC		 7593 goto clean_up;
7594
e1f7de0c 7595 hpsa_enter_performant_mode(h, trans_support);
303932fd
DB		 7596 return;
7597
7598clean_up:
072b0518 7599 hpsa_free_reply_queues(h);
303932fd
DB		 7600 kfree(h->blockFetchTable);
7601}
7602
23100dd9 7603static int is_accelerated_cmd(struct CommandList *c)
76438d08 7604{
23100dd9
SC		 7605 return c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_IOACCEL2;
7606}
7607
7608static void hpsa_drain_accel_commands(struct ctlr_info *h)
7609{
7610 struct CommandList *c = NULL;
76438d08 7611 unsigned long flags;
23100dd9 7612 int accel_cmds_out;
76438d08
SC		 7613
7614 do { /* wait for all outstanding commands to drain out */
23100dd9 7615 accel_cmds_out = 0;
76438d08 7616 spin_lock_irqsave(&h->lock, flags);
23100dd9
SC		 7617 list_for_each_entry(c, &h->cmpQ, list)
7618 accel_cmds_out += is_accelerated_cmd(c);
7619 list_for_each_entry(c, &h->reqQ, list)
7620 accel_cmds_out += is_accelerated_cmd(c);
76438d08 7621 spin_unlock_irqrestore(&h->lock, flags);
23100dd9 7622 if (accel_cmds_out <= 0)
76438d08
SC		 7623 break;
7624 msleep(100);
7625 } while (1);
7626}
7627
edd16368
SC		 7628/*
7629 * This is it. Register the PCI driver information for the cards we control
7630 * the OS will call our registered routines when it finds one of our cards.
7631 */
7632static int __init hpsa_init(void)
7633{
31468401 7634 return pci_register_driver(&hpsa_pci_driver);
edd16368
SC		 7635}
7636
7637static void __exit hpsa_cleanup(void)
7638{
7639 pci_unregister_driver(&hpsa_pci_driver);
edd16368
SC		 7640}
7641
e1f7de0c
MG		 7642static void __attribute__((unused)) verify_offsets(void)
7643{
dd0e19f3
ST		 7644#define VERIFY_OFFSET(member, offset) \
7645 BUILD_BUG_ON(offsetof(struct raid_map_data, member) != offset)
7646
7647 VERIFY_OFFSET(structure_size, 0);
7648 VERIFY_OFFSET(volume_blk_size, 4);
7649 VERIFY_OFFSET(volume_blk_cnt, 8);
7650 VERIFY_OFFSET(phys_blk_shift, 16);
7651 VERIFY_OFFSET(parity_rotation_shift, 17);
7652 VERIFY_OFFSET(strip_size, 18);
7653 VERIFY_OFFSET(disk_starting_blk, 20);
7654 VERIFY_OFFSET(disk_blk_cnt, 28);
7655 VERIFY_OFFSET(data_disks_per_row, 36);
7656 VERIFY_OFFSET(metadata_disks_per_row, 38);
7657 VERIFY_OFFSET(row_cnt, 40);
7658 VERIFY_OFFSET(layout_map_count, 42);
7659 VERIFY_OFFSET(flags, 44);
7660 VERIFY_OFFSET(dekindex, 46);
7661 /* VERIFY_OFFSET(reserved, 48 */
7662 VERIFY_OFFSET(data, 64);
7663
7664#undef VERIFY_OFFSET
7665
b66cc250
MM		 7666#define VERIFY_OFFSET(member, offset) \
7667 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, member) != offset)
7668
7669 VERIFY_OFFSET(IU_type, 0);
7670 VERIFY_OFFSET(direction, 1);
7671 VERIFY_OFFSET(reply_queue, 2);
7672 /* VERIFY_OFFSET(reserved1, 3); */
7673 VERIFY_OFFSET(scsi_nexus, 4);
7674 VERIFY_OFFSET(Tag, 8);
7675 VERIFY_OFFSET(cdb, 16);
7676 VERIFY_OFFSET(cciss_lun, 32);
7677 VERIFY_OFFSET(data_len, 40);
7678 VERIFY_OFFSET(cmd_priority_task_attr, 44);
7679 VERIFY_OFFSET(sg_count, 45);
7680 /* VERIFY_OFFSET(reserved3 */
7681 VERIFY_OFFSET(err_ptr, 48);
7682 VERIFY_OFFSET(err_len, 56);
7683 /* VERIFY_OFFSET(reserved4 */
7684 VERIFY_OFFSET(sg, 64);
7685
7686#undef VERIFY_OFFSET
7687
e1f7de0c
MG		 7688#define VERIFY_OFFSET(member, offset) \
7689 BUILD_BUG_ON(offsetof(struct io_accel1_cmd, member) != offset)
7690
7691 VERIFY_OFFSET(dev_handle, 0x00);
7692 VERIFY_OFFSET(reserved1, 0x02);
7693 VERIFY_OFFSET(function, 0x03);
7694 VERIFY_OFFSET(reserved2, 0x04);
7695 VERIFY_OFFSET(err_info, 0x0C);
7696 VERIFY_OFFSET(reserved3, 0x10);
7697 VERIFY_OFFSET(err_info_len, 0x12);
7698 VERIFY_OFFSET(reserved4, 0x13);
7699 VERIFY_OFFSET(sgl_offset, 0x14);
7700 VERIFY_OFFSET(reserved5, 0x15);
7701 VERIFY_OFFSET(transfer_len, 0x1C);
7702 VERIFY_OFFSET(reserved6, 0x20);
7703 VERIFY_OFFSET(io_flags, 0x24);
7704 VERIFY_OFFSET(reserved7, 0x26);
7705 VERIFY_OFFSET(LUN, 0x34);
7706 VERIFY_OFFSET(control, 0x3C);
7707 VERIFY_OFFSET(CDB, 0x40);
7708 VERIFY_OFFSET(reserved8, 0x50);
7709 VERIFY_OFFSET(host_context_flags, 0x60);
7710 VERIFY_OFFSET(timeout_sec, 0x62);
7711 VERIFY_OFFSET(ReplyQueue, 0x64);
7712 VERIFY_OFFSET(reserved9, 0x65);
7713 VERIFY_OFFSET(Tag, 0x68);
7714 VERIFY_OFFSET(host_addr, 0x70);
7715 VERIFY_OFFSET(CISS_LUN, 0x78);
7716 VERIFY_OFFSET(SG, 0x78 + 8);
7717#undef VERIFY_OFFSET
7718}
7719
edd16368
SC		 7720module_init(hpsa_init);
7721module_exit(hpsa_cleanup);
Linux kernel - Deliverables
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