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hpsa: Checking for a NULL return from a kzalloc call
[deliverable/linux.git] / drivers / scsi / hpsa.c
CommitLineData
edd16368
SC		 1/*
2 * Disk Array driver for HP Smart Array SAS controllers
51c35139 3 * Copyright 2000, 2014 Hewlett-Packard Development Company, L.P.
edd16368
SC		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
12 * NON INFRINGEMENT. See the GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 *
18 * Questions/Comments/Bugfixes to iss_storagedev@hp.com
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/interrupt.h>
24#include <linux/types.h>
25#include <linux/pci.h>
e5a44df8 26#include <linux/pci-aspm.h>
edd16368
SC		 27#include <linux/kernel.h>
28#include <linux/slab.h>
29#include <linux/delay.h>
30#include <linux/fs.h>
31#include <linux/timer.h>
edd16368
SC		 32#include <linux/init.h>
33#include <linux/spinlock.h>
edd16368
SC		 34#include <linux/compat.h>
35#include <linux/blktrace_api.h>
36#include <linux/uaccess.h>
37#include <linux/io.h>
38#include <linux/dma-mapping.h>
39#include <linux/completion.h>
40#include <linux/moduleparam.h>
41#include <scsi/scsi.h>
42#include <scsi/scsi_cmnd.h>
43#include <scsi/scsi_device.h>
44#include <scsi/scsi_host.h>
667e23d4 45#include <scsi/scsi_tcq.h>
edd16368
SC		 46#include <linux/cciss_ioctl.h>
47#include <linux/string.h>
48#include <linux/bitmap.h>
60063497 49#include <linux/atomic.h>
a0c12413 50#include <linux/jiffies.h>
283b4a9b 51#include <asm/div64.h>
edd16368
SC		 52#include "hpsa_cmd.h"
53#include "hpsa.h"
54
55/* HPSA_DRIVER_VERSION must be 3 byte values (0-255) separated by '.' */
9a993302 56#define HPSA_DRIVER_VERSION "3.4.4-1"
edd16368 57#define DRIVER_NAME "HP HPSA Driver (v " HPSA_DRIVER_VERSION ")"
f79cfec6 58#define HPSA "hpsa"
edd16368
SC		 59
60/* How long to wait (in milliseconds) for board to go into simple mode */
61#define MAX_CONFIG_WAIT 30000
62#define MAX_IOCTL_CONFIG_WAIT 1000
63
64/*define how many times we will try a command because of bus resets */
65#define MAX_CMD_RETRIES 3
66
67/* Embedded module documentation macros - see modules.h */
68MODULE_AUTHOR("Hewlett-Packard Company");
69MODULE_DESCRIPTION("Driver for HP Smart Array Controller version " \
70 HPSA_DRIVER_VERSION);
71MODULE_SUPPORTED_DEVICE("HP Smart Array Controllers");
72MODULE_VERSION(HPSA_DRIVER_VERSION);
73MODULE_LICENSE("GPL");
74
75static int hpsa_allow_any;
76module_param(hpsa_allow_any, int, S_IRUGO|S_IWUSR);
77MODULE_PARM_DESC(hpsa_allow_any,
78 "Allow hpsa driver to access unknown HP Smart Array hardware");
02ec19c8
SC		 79static int hpsa_simple_mode;
80module_param(hpsa_simple_mode, int, S_IRUGO|S_IWUSR);
81MODULE_PARM_DESC(hpsa_simple_mode,
82 "Use 'simple mode' rather than 'performant mode'");
edd16368
SC		 83
84/* define the PCI info for the cards we can control */
85static const struct pci_device_id hpsa_pci_device_id[] = {
edd16368
SC		 86 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3241},
87 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3243},
88 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3245},
89 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3247},
90 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3249},
163dbcd8
MM		 91 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324A},
92 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324B},
f8b01eb9 93 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3233},
9143a961 94 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3350},
95 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3351},
96 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3352},
97 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3353},
98 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3354},
99 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3355},
100 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3356},
fe0c9610
MM		 101 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1921},
102 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1922},
103 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1923},
104 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1924},
105 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1925},
106 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1926},
107 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1928},
97b9f53d
MM		 108 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1929},
109 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BD},
110 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BE},
111 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BF},
112 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C0},
113 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C1},
114 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C2},
115 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C3},
116 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C4},
117 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C5},
118 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C7},
119 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C8},
120 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C9},
8e616a5e
SC		 121 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0076},
122 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0087},
123 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x007D},
124 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0088},
125 {PCI_VENDOR_ID_HP, 0x333f, 0x103c, 0x333f},
7c03b870 126 {PCI_VENDOR_ID_HP, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
6798cc0a 127 PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0},
edd16368
SC		 128 {0,}
129};
130
131MODULE_DEVICE_TABLE(pci, hpsa_pci_device_id);
132
133/* board_id = Subsystem Device ID & Vendor ID
134 * product = Marketing Name for the board
135 * access = Address of the struct of function pointers
136 */
137static struct board_type products[] = {
edd16368
SC		 138 {0x3241103C, "Smart Array P212", &SA5_access},
139 {0x3243103C, "Smart Array P410", &SA5_access},
140 {0x3245103C, "Smart Array P410i", &SA5_access},
141 {0x3247103C, "Smart Array P411", &SA5_access},
142 {0x3249103C, "Smart Array P812", &SA5_access},
163dbcd8
MM		 143 {0x324A103C, "Smart Array P712m", &SA5_access},
144 {0x324B103C, "Smart Array P711m", &SA5_access},
fe0c9610
MM		 145 {0x3350103C, "Smart Array P222", &SA5_access},
146 {0x3351103C, "Smart Array P420", &SA5_access},
147 {0x3352103C, "Smart Array P421", &SA5_access},
148 {0x3353103C, "Smart Array P822", &SA5_access},
149 {0x3354103C, "Smart Array P420i", &SA5_access},
150 {0x3355103C, "Smart Array P220i", &SA5_access},
151 {0x3356103C, "Smart Array P721m", &SA5_access},
1fd6c8e3
MM		 152 {0x1921103C, "Smart Array P830i", &SA5_access},
153 {0x1922103C, "Smart Array P430", &SA5_access},
154 {0x1923103C, "Smart Array P431", &SA5_access},
155 {0x1924103C, "Smart Array P830", &SA5_access},
156 {0x1926103C, "Smart Array P731m", &SA5_access},
157 {0x1928103C, "Smart Array P230i", &SA5_access},
158 {0x1929103C, "Smart Array P530", &SA5_access},
97b9f53d
MM		 159 {0x21BD103C, "Smart Array", &SA5_access},
160 {0x21BE103C, "Smart Array", &SA5_access},
161 {0x21BF103C, "Smart Array", &SA5_access},
162 {0x21C0103C, "Smart Array", &SA5_access},
163 {0x21C1103C, "Smart Array", &SA5_access},
164 {0x21C2103C, "Smart Array", &SA5_access},
165 {0x21C3103C, "Smart Array", &SA5_access},
166 {0x21C4103C, "Smart Array", &SA5_access},
167 {0x21C5103C, "Smart Array", &SA5_access},
168 {0x21C7103C, "Smart Array", &SA5_access},
169 {0x21C8103C, "Smart Array", &SA5_access},
170 {0x21C9103C, "Smart Array", &SA5_access},
8e616a5e
SC		 171 {0x00761590, "HP Storage P1224 Array Controller", &SA5_access},
172 {0x00871590, "HP Storage P1224e Array Controller", &SA5_access},
173 {0x007D1590, "HP Storage P1228 Array Controller", &SA5_access},
174 {0x00881590, "HP Storage P1228e Array Controller", &SA5_access},
175 {0x333f103c, "HP StorageWorks 1210m Array Controller", &SA5_access},
edd16368
SC		 176 {0xFFFF103C, "Unknown Smart Array", &SA5_access},
177};
178
179static int number_of_controllers;
180
10f66018
SC		 181static irqreturn_t do_hpsa_intr_intx(int irq, void *dev_id);
182static irqreturn_t do_hpsa_intr_msi(int irq, void *dev_id);
edd16368
SC		 183static int hpsa_ioctl(struct scsi_device *dev, int cmd, void *arg);
184static void start_io(struct ctlr_info *h);
185
186#ifdef CONFIG_COMPAT
187static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void *arg);
188#endif
189
190static void cmd_free(struct ctlr_info *h, struct CommandList *c);
191static void cmd_special_free(struct ctlr_info *h, struct CommandList *c);
192static struct CommandList *cmd_alloc(struct ctlr_info *h);
193static struct CommandList *cmd_special_alloc(struct ctlr_info *h);
a2dac136 194static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
b7bb24eb 195 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
edd16368 196 int cmd_type);
b7bb24eb 197#define VPD_PAGE (1 << 8)
edd16368 198
f281233d 199static int hpsa_scsi_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd);
a08a8471
SC		 200static void hpsa_scan_start(struct Scsi_Host *);
201static int hpsa_scan_finished(struct Scsi_Host *sh,
202 unsigned long elapsed_time);
667e23d4
SC		 203static int hpsa_change_queue_depth(struct scsi_device *sdev,
204 int qdepth, int reason);
edd16368
SC		 205
206static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd);
75167d2c 207static int hpsa_eh_abort_handler(struct scsi_cmnd *scsicmd);
edd16368
SC		 208static int hpsa_slave_alloc(struct scsi_device *sdev);
209static void hpsa_slave_destroy(struct scsi_device *sdev);
210
edd16368 211static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno);
edd16368
SC		 212static int check_for_unit_attention(struct ctlr_info *h,
213 struct CommandList *c);
214static void check_ioctl_unit_attention(struct ctlr_info *h,
215 struct CommandList *c);
303932fd
DB		 216/* performant mode helper functions */
217static void calc_bucket_map(int *bucket, int num_buckets,
e1f7de0c 218 int nsgs, int min_blocks, int *bucket_map);
6f039790 219static void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h);
254f796b 220static inline u32 next_command(struct ctlr_info *h, u8 q);
6f039790
GKH		 221static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
222 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
223 u64 *cfg_offset);
224static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
225 unsigned long *memory_bar);
226static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id);
227static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
228 int wait_for_ready);
75167d2c 229static inline void finish_cmd(struct CommandList *c);
283b4a9b 230static void hpsa_wait_for_mode_change_ack(struct ctlr_info *h);
fe5389c8
SC		 231#define BOARD_NOT_READY 0
232#define BOARD_READY 1
23100dd9 233static void hpsa_drain_accel_commands(struct ctlr_info *h);
76438d08 234static void hpsa_flush_cache(struct ctlr_info *h);
c349775e
ST		 235static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
236 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
237 u8 *scsi3addr);
edd16368 238
edd16368
SC		 239static inline struct ctlr_info *sdev_to_hba(struct scsi_device *sdev)
240{
241 unsigned long *priv = shost_priv(sdev->host);
242 return (struct ctlr_info *) *priv;
243}
244
a23513e8
SC		 245static inline struct ctlr_info *shost_to_hba(struct Scsi_Host *sh)
246{
247 unsigned long *priv = shost_priv(sh);
248 return (struct ctlr_info *) *priv;
249}
250
edd16368
SC		 251static int check_for_unit_attention(struct ctlr_info *h,
252 struct CommandList *c)
253{
254 if (c->err_info->SenseInfo[2] != UNIT_ATTENTION)
255 return 0;
256
257 switch (c->err_info->SenseInfo[12]) {
258 case STATE_CHANGED:
f79cfec6 259 dev_warn(&h->pdev->dev, HPSA "%d: a state change "
edd16368
SC		 260 "detected, command retried\n", h->ctlr);
261 break;
262 case LUN_FAILED:
f79cfec6 263 dev_warn(&h->pdev->dev, HPSA "%d: LUN failure "
edd16368
SC		 264 "detected, action required\n", h->ctlr);
265 break;
266 case REPORT_LUNS_CHANGED:
f79cfec6 267 dev_warn(&h->pdev->dev, HPSA "%d: report LUN data "
31468401 268 "changed, action required\n", h->ctlr);
edd16368 269 /*
4f4eb9f1
ST		 270 * Note: this REPORT_LUNS_CHANGED condition only occurs on the external
271 * target (array) devices.
edd16368
SC		 272 */
273 break;
274 case POWER_OR_RESET:
f79cfec6 275 dev_warn(&h->pdev->dev, HPSA "%d: a power on "
edd16368
SC		 276 "or device reset detected\n", h->ctlr);
277 break;
278 case UNIT_ATTENTION_CLEARED:
f79cfec6 279 dev_warn(&h->pdev->dev, HPSA "%d: unit attention "
edd16368
SC		 280 "cleared by another initiator\n", h->ctlr);
281 break;
282 default:
f79cfec6 283 dev_warn(&h->pdev->dev, HPSA "%d: unknown "
edd16368
SC		 284 "unit attention detected\n", h->ctlr);
285 break;
286 }
287 return 1;
288}
289
852af20a
MB		 290static int check_for_busy(struct ctlr_info *h, struct CommandList *c)
291{
292 if (c->err_info->CommandStatus != CMD_TARGET_STATUS ||
293 (c->err_info->ScsiStatus != SAM_STAT_BUSY &&
294 c->err_info->ScsiStatus != SAM_STAT_TASK_SET_FULL))
295 return 0;
296 dev_warn(&h->pdev->dev, HPSA "device busy");
297 return 1;
298}
299
da0697bd
ST		 300static ssize_t host_store_hp_ssd_smart_path_status(struct device *dev,
301 struct device_attribute *attr,
302 const char *buf, size_t count)
303{
304 int status, len;
305 struct ctlr_info *h;
306 struct Scsi_Host *shost = class_to_shost(dev);
307 char tmpbuf[10];
308
309 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
310 return -EACCES;
311 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
312 strncpy(tmpbuf, buf, len);
313 tmpbuf[len] = '\0';
314 if (sscanf(tmpbuf, "%d", &status) != 1)
315 return -EINVAL;
316 h = shost_to_hba(shost);
317 h->acciopath_status = !!status;
318 dev_warn(&h->pdev->dev,
319 "hpsa: HP SSD Smart Path %s via sysfs update.\n",
320 h->acciopath_status ? "enabled" : "disabled");
321 return count;
322}
323
2ba8bfc8
SC		 324static ssize_t host_store_raid_offload_debug(struct device *dev,
325 struct device_attribute *attr,
326 const char *buf, size_t count)
327{
328 int debug_level, len;
329 struct ctlr_info *h;
330 struct Scsi_Host *shost = class_to_shost(dev);
331 char tmpbuf[10];
332
333 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
334 return -EACCES;
335 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
336 strncpy(tmpbuf, buf, len);
337 tmpbuf[len] = '\0';
338 if (sscanf(tmpbuf, "%d", &debug_level) != 1)
339 return -EINVAL;
340 if (debug_level < 0)
341 debug_level = 0;
342 h = shost_to_hba(shost);
343 h->raid_offload_debug = debug_level;
344 dev_warn(&h->pdev->dev, "hpsa: Set raid_offload_debug level = %d\n",
345 h->raid_offload_debug);
346 return count;
347}
348
edd16368
SC		 349static ssize_t host_store_rescan(struct device *dev,
350 struct device_attribute *attr,
351 const char *buf, size_t count)
352{
353 struct ctlr_info *h;
354 struct Scsi_Host *shost = class_to_shost(dev);
a23513e8 355 h = shost_to_hba(shost);
31468401 356 hpsa_scan_start(h->scsi_host);
edd16368
SC		 357 return count;
358}
359
d28ce020
SC		 360static ssize_t host_show_firmware_revision(struct device *dev,
361 struct device_attribute *attr, char *buf)
362{
363 struct ctlr_info *h;
364 struct Scsi_Host *shost = class_to_shost(dev);
365 unsigned char *fwrev;
366
367 h = shost_to_hba(shost);
368 if (!h->hba_inquiry_data)
369 return 0;
370 fwrev = &h->hba_inquiry_data[32];
371 return snprintf(buf, 20, "%c%c%c%c\n",
372 fwrev[0], fwrev[1], fwrev[2], fwrev[3]);
373}
374
94a13649
SC		 375static ssize_t host_show_commands_outstanding(struct device *dev,
376 struct device_attribute *attr, char *buf)
377{
378 struct Scsi_Host *shost = class_to_shost(dev);
379 struct ctlr_info *h = shost_to_hba(shost);
380
381 return snprintf(buf, 20, "%d\n", h->commands_outstanding);
382}
383
745a7a25
SC		 384static ssize_t host_show_transport_mode(struct device *dev,
385 struct device_attribute *attr, char *buf)
386{
387 struct ctlr_info *h;
388 struct Scsi_Host *shost = class_to_shost(dev);
389
390 h = shost_to_hba(shost);
391 return snprintf(buf, 20, "%s\n",
960a30e7 392 h->transMethod & CFGTBL_Trans_Performant ?
745a7a25
SC		 393 "performant" : "simple");
394}
395
da0697bd
ST		 396static ssize_t host_show_hp_ssd_smart_path_status(struct device *dev,
397 struct device_attribute *attr, char *buf)
398{
399 struct ctlr_info *h;
400 struct Scsi_Host *shost = class_to_shost(dev);
401
402 h = shost_to_hba(shost);
403 return snprintf(buf, 30, "HP SSD Smart Path %s\n",
404 (h->acciopath_status == 1) ? "enabled" : "disabled");
405}
406
46380786 407/* List of controllers which cannot be hard reset on kexec with reset_devices */
941b1cda
SC		 408static u32 unresettable_controller[] = {
409 0x324a103C, /* Smart Array P712m */
410 0x324b103C, /* SmartArray P711m */
411 0x3223103C, /* Smart Array P800 */
412 0x3234103C, /* Smart Array P400 */
413 0x3235103C, /* Smart Array P400i */
414 0x3211103C, /* Smart Array E200i */
415 0x3212103C, /* Smart Array E200 */
416 0x3213103C, /* Smart Array E200i */
417 0x3214103C, /* Smart Array E200i */
418 0x3215103C, /* Smart Array E200i */
419 0x3237103C, /* Smart Array E500 */
420 0x323D103C, /* Smart Array P700m */
7af0abbc 421 0x40800E11, /* Smart Array 5i */
941b1cda
SC		 422 0x409C0E11, /* Smart Array 6400 */
423 0x409D0E11, /* Smart Array 6400 EM */
5a4f934e
TH		 424 0x40700E11, /* Smart Array 5300 */
425 0x40820E11, /* Smart Array 532 */
426 0x40830E11, /* Smart Array 5312 */
427 0x409A0E11, /* Smart Array 641 */
428 0x409B0E11, /* Smart Array 642 */
429 0x40910E11, /* Smart Array 6i */
941b1cda
SC		 430};
431
46380786
SC		 432/* List of controllers which cannot even be soft reset */
433static u32 soft_unresettable_controller[] = {
7af0abbc 434 0x40800E11, /* Smart Array 5i */
5a4f934e
TH		 435 0x40700E11, /* Smart Array 5300 */
436 0x40820E11, /* Smart Array 532 */
437 0x40830E11, /* Smart Array 5312 */
438 0x409A0E11, /* Smart Array 641 */
439 0x409B0E11, /* Smart Array 642 */
440 0x40910E11, /* Smart Array 6i */
46380786
SC		 441 /* Exclude 640x boards. These are two pci devices in one slot
442 * which share a battery backed cache module. One controls the
443 * cache, the other accesses the cache through the one that controls
444 * it. If we reset the one controlling the cache, the other will
445 * likely not be happy. Just forbid resetting this conjoined mess.
446 * The 640x isn't really supported by hpsa anyway.
447 */
448 0x409C0E11, /* Smart Array 6400 */
449 0x409D0E11, /* Smart Array 6400 EM */
450};
451
452static int ctlr_is_hard_resettable(u32 board_id)
941b1cda
SC		 453{
454 int i;
455
456 for (i = 0; i < ARRAY_SIZE(unresettable_controller); i++)
46380786
SC		 457 if (unresettable_controller[i] == board_id)
458 return 0;
459 return 1;
460}
461
462static int ctlr_is_soft_resettable(u32 board_id)
463{
464 int i;
465
466 for (i = 0; i < ARRAY_SIZE(soft_unresettable_controller); i++)
467 if (soft_unresettable_controller[i] == board_id)
941b1cda
SC		 468 return 0;
469 return 1;
470}
471
46380786
SC		 472static int ctlr_is_resettable(u32 board_id)
473{
474 return ctlr_is_hard_resettable(board_id) ||
475 ctlr_is_soft_resettable(board_id);
476}
477
941b1cda
SC		 478static ssize_t host_show_resettable(struct device *dev,
479 struct device_attribute *attr, char *buf)
480{
481 struct ctlr_info *h;
482 struct Scsi_Host *shost = class_to_shost(dev);
483
484 h = shost_to_hba(shost);
46380786 485 return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h->board_id));
941b1cda
SC		 486}
487
edd16368
SC		 488static inline int is_logical_dev_addr_mode(unsigned char scsi3addr[])
489{
490 return (scsi3addr[3] & 0xC0) == 0x40;
491}
492
493static const char *raid_label[] = { "0", "4", "1(1+0)", "5", "5+1", "ADG",
d82357ea 494 "1(ADM)", "UNKNOWN"
edd16368 495};
6b80b18f
ST		 496#define HPSA_RAID_0 0
497#define HPSA_RAID_4 1
498#define HPSA_RAID_1 2 /* also used for RAID 10 */
499#define HPSA_RAID_5 3 /* also used for RAID 50 */
500#define HPSA_RAID_51 4
501#define HPSA_RAID_6 5 /* also used for RAID 60 */
502#define HPSA_RAID_ADM 6 /* also used for RAID 1+0 ADM */
edd16368
SC		 503#define RAID_UNKNOWN (ARRAY_SIZE(raid_label) - 1)
504
505static ssize_t raid_level_show(struct device *dev,
506 struct device_attribute *attr, char *buf)
507{
508 ssize_t l = 0;
82a72c0a 509 unsigned char rlevel;
edd16368
SC		 510 struct ctlr_info *h;
511 struct scsi_device *sdev;
512 struct hpsa_scsi_dev_t *hdev;
513 unsigned long flags;
514
515 sdev = to_scsi_device(dev);
516 h = sdev_to_hba(sdev);
517 spin_lock_irqsave(&h->lock, flags);
518 hdev = sdev->hostdata;
519 if (!hdev) {
520 spin_unlock_irqrestore(&h->lock, flags);
521 return -ENODEV;
522 }
523
524 /* Is this even a logical drive? */
525 if (!is_logical_dev_addr_mode(hdev->scsi3addr)) {
526 spin_unlock_irqrestore(&h->lock, flags);
527 l = snprintf(buf, PAGE_SIZE, "N/A\n");
528 return l;
529 }
530
531 rlevel = hdev->raid_level;
532 spin_unlock_irqrestore(&h->lock, flags);
82a72c0a 533 if (rlevel > RAID_UNKNOWN)
edd16368
SC		 534 rlevel = RAID_UNKNOWN;
535 l = snprintf(buf, PAGE_SIZE, "RAID %s\n", raid_label[rlevel]);
536 return l;
537}
538
539static ssize_t lunid_show(struct device *dev,
540 struct device_attribute *attr, char *buf)
541{
542 struct ctlr_info *h;
543 struct scsi_device *sdev;
544 struct hpsa_scsi_dev_t *hdev;
545 unsigned long flags;
546 unsigned char lunid[8];
547
548 sdev = to_scsi_device(dev);
549 h = sdev_to_hba(sdev);
550 spin_lock_irqsave(&h->lock, flags);
551 hdev = sdev->hostdata;
552 if (!hdev) {
553 spin_unlock_irqrestore(&h->lock, flags);
554 return -ENODEV;
555 }
556 memcpy(lunid, hdev->scsi3addr, sizeof(lunid));
557 spin_unlock_irqrestore(&h->lock, flags);
558 return snprintf(buf, 20, "0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
559 lunid[0], lunid[1], lunid[2], lunid[3],
560 lunid[4], lunid[5], lunid[6], lunid[7]);
561}
562
563static ssize_t unique_id_show(struct device *dev,
564 struct device_attribute *attr, char *buf)
565{
566 struct ctlr_info *h;
567 struct scsi_device *sdev;
568 struct hpsa_scsi_dev_t *hdev;
569 unsigned long flags;
570 unsigned char sn[16];
571
572 sdev = to_scsi_device(dev);
573 h = sdev_to_hba(sdev);
574 spin_lock_irqsave(&h->lock, flags);
575 hdev = sdev->hostdata;
576 if (!hdev) {
577 spin_unlock_irqrestore(&h->lock, flags);
578 return -ENODEV;
579 }
580 memcpy(sn, hdev->device_id, sizeof(sn));
581 spin_unlock_irqrestore(&h->lock, flags);
582 return snprintf(buf, 16 * 2 + 2,
583 "%02X%02X%02X%02X%02X%02X%02X%02X"
584 "%02X%02X%02X%02X%02X%02X%02X%02X\n",
585 sn[0], sn[1], sn[2], sn[3],
586 sn[4], sn[5], sn[6], sn[7],
587 sn[8], sn[9], sn[10], sn[11],
588 sn[12], sn[13], sn[14], sn[15]);
589}
590
c1988684
ST		 591static ssize_t host_show_hp_ssd_smart_path_enabled(struct device *dev,
592 struct device_attribute *attr, char *buf)
593{
594 struct ctlr_info *h;
595 struct scsi_device *sdev;
596 struct hpsa_scsi_dev_t *hdev;
597 unsigned long flags;
598 int offload_enabled;
599
600 sdev = to_scsi_device(dev);
601 h = sdev_to_hba(sdev);
602 spin_lock_irqsave(&h->lock, flags);
603 hdev = sdev->hostdata;
604 if (!hdev) {
605 spin_unlock_irqrestore(&h->lock, flags);
606 return -ENODEV;
607 }
608 offload_enabled = hdev->offload_enabled;
609 spin_unlock_irqrestore(&h->lock, flags);
610 return snprintf(buf, 20, "%d\n", offload_enabled);
611}
612
3f5eac3a
SC		 613static DEVICE_ATTR(raid_level, S_IRUGO, raid_level_show, NULL);
614static DEVICE_ATTR(lunid, S_IRUGO, lunid_show, NULL);
615static DEVICE_ATTR(unique_id, S_IRUGO, unique_id_show, NULL);
616static DEVICE_ATTR(rescan, S_IWUSR, NULL, host_store_rescan);
c1988684
ST		 617static DEVICE_ATTR(hp_ssd_smart_path_enabled, S_IRUGO,
618 host_show_hp_ssd_smart_path_enabled, NULL);
da0697bd
ST		 619static DEVICE_ATTR(hp_ssd_smart_path_status, S_IWUSR|S_IRUGO|S_IROTH,
620 host_show_hp_ssd_smart_path_status,
621 host_store_hp_ssd_smart_path_status);
2ba8bfc8
SC		 622static DEVICE_ATTR(raid_offload_debug, S_IWUSR, NULL,
623 host_store_raid_offload_debug);
3f5eac3a
SC		 624static DEVICE_ATTR(firmware_revision, S_IRUGO,
625 host_show_firmware_revision, NULL);
626static DEVICE_ATTR(commands_outstanding, S_IRUGO,
627 host_show_commands_outstanding, NULL);
628static DEVICE_ATTR(transport_mode, S_IRUGO,
629 host_show_transport_mode, NULL);
941b1cda
SC		 630static DEVICE_ATTR(resettable, S_IRUGO,
631 host_show_resettable, NULL);
3f5eac3a
SC		 632
633static struct device_attribute *hpsa_sdev_attrs[] = {
634 &dev_attr_raid_level,
635 &dev_attr_lunid,
636 &dev_attr_unique_id,
c1988684 637 &dev_attr_hp_ssd_smart_path_enabled,
3f5eac3a
SC		 638 NULL,
639};
640
641static struct device_attribute *hpsa_shost_attrs[] = {
642 &dev_attr_rescan,
643 &dev_attr_firmware_revision,
644 &dev_attr_commands_outstanding,
645 &dev_attr_transport_mode,
941b1cda 646 &dev_attr_resettable,
da0697bd 647 &dev_attr_hp_ssd_smart_path_status,
2ba8bfc8 648 &dev_attr_raid_offload_debug,
3f5eac3a
SC		 649 NULL,
650};
651
652static struct scsi_host_template hpsa_driver_template = {
653 .module = THIS_MODULE,
f79cfec6
SC		 654 .name = HPSA,
655 .proc_name = HPSA,
3f5eac3a
SC		 656 .queuecommand = hpsa_scsi_queue_command,
657 .scan_start = hpsa_scan_start,
658 .scan_finished = hpsa_scan_finished,
659 .change_queue_depth = hpsa_change_queue_depth,
660 .this_id = -1,
661 .use_clustering = ENABLE_CLUSTERING,
75167d2c 662 .eh_abort_handler = hpsa_eh_abort_handler,
3f5eac3a
SC		 663 .eh_device_reset_handler = hpsa_eh_device_reset_handler,
664 .ioctl = hpsa_ioctl,
665 .slave_alloc = hpsa_slave_alloc,
666 .slave_destroy = hpsa_slave_destroy,
667#ifdef CONFIG_COMPAT
668 .compat_ioctl = hpsa_compat_ioctl,
669#endif
670 .sdev_attrs = hpsa_sdev_attrs,
671 .shost_attrs = hpsa_shost_attrs,
c0d6a4d1 672 .max_sectors = 8192,
54b2b50c 673 .no_write_same = 1,
3f5eac3a
SC		 674};
675
676
677/* Enqueuing and dequeuing functions for cmdlists. */
678static inline void addQ(struct list_head *list, struct CommandList *c)
679{
680 list_add_tail(&c->list, list);
681}
682
254f796b 683static inline u32 next_command(struct ctlr_info *h, u8 q)
3f5eac3a
SC		 684{
685 u32 a;
254f796b 686 struct reply_pool *rq = &h->reply_queue[q];
e16a33ad 687 unsigned long flags;
3f5eac3a 688
e1f7de0c
MG		 689 if (h->transMethod & CFGTBL_Trans_io_accel1)
690 return h->access.command_completed(h, q);
691
3f5eac3a 692 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
254f796b 693 return h->access.command_completed(h, q);
3f5eac3a 694
254f796b
MG		 695 if ((rq->head[rq->current_entry] & 1) == rq->wraparound) {
696 a = rq->head[rq->current_entry];
697 rq->current_entry++;
e16a33ad 698 spin_lock_irqsave(&h->lock, flags);
3f5eac3a 699 h->commands_outstanding--;
e16a33ad 700 spin_unlock_irqrestore(&h->lock, flags);
3f5eac3a
SC		 701 } else {
702 a = FIFO_EMPTY;
703 }
704 /* Check for wraparound */
254f796b
MG		 705 if (rq->current_entry == h->max_commands) {
706 rq->current_entry = 0;
707 rq->wraparound ^= 1;
3f5eac3a
SC		 708 }
709 return a;
710}
711
c349775e
ST		 712/*
713 * There are some special bits in the bus address of the
714 * command that we have to set for the controller to know
715 * how to process the command:
716 *
717 * Normal performant mode:
718 * bit 0: 1 means performant mode, 0 means simple mode.
719 * bits 1-3 = block fetch table entry
720 * bits 4-6 = command type (== 0)
721 *
722 * ioaccel1 mode:
723 * bit 0 = "performant mode" bit.
724 * bits 1-3 = block fetch table entry
725 * bits 4-6 = command type (== 110)
726 * (command type is needed because ioaccel1 mode
727 * commands are submitted through the same register as normal
728 * mode commands, so this is how the controller knows whether
729 * the command is normal mode or ioaccel1 mode.)
730 *
731 * ioaccel2 mode:
732 * bit 0 = "performant mode" bit.
733 * bits 1-4 = block fetch table entry (note extra bit)
734 * bits 4-6 = not needed, because ioaccel2 mode has
735 * a separate special register for submitting commands.
736 */
737
3f5eac3a
SC		 738/* set_performant_mode: Modify the tag for cciss performant
739 * set bit 0 for pull model, bits 3-1 for block fetch
740 * register number
741 */
742static void set_performant_mode(struct ctlr_info *h, struct CommandList *c)
743{
254f796b 744 if (likely(h->transMethod & CFGTBL_Trans_Performant)) {
3f5eac3a 745 c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1);
eee0f03a 746 if (likely(h->msix_vector > 0))
254f796b 747 c->Header.ReplyQueue =
804a5cb5 748 raw_smp_processor_id() % h->nreply_queues;
254f796b 749 }
3f5eac3a
SC		 750}
751
c349775e
ST		 752static void set_ioaccel1_performant_mode(struct ctlr_info *h,
753 struct CommandList *c)
754{
755 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
756
757 /* Tell the controller to post the reply to the queue for this
758 * processor. This seems to give the best I/O throughput.
759 */
760 cp->ReplyQueue = smp_processor_id() % h->nreply_queues;
761 /* Set the bits in the address sent down to include:
762 * - performant mode bit (bit 0)
763 * - pull count (bits 1-3)
764 * - command type (bits 4-6)
765 */
766 c->busaddr |= 1 | (h->ioaccel1_blockFetchTable[c->Header.SGList] << 1) |
767 IOACCEL1_BUSADDR_CMDTYPE;
768}
769
770static void set_ioaccel2_performant_mode(struct ctlr_info *h,
771 struct CommandList *c)
772{
773 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
774
775 /* Tell the controller to post the reply to the queue for this
776 * processor. This seems to give the best I/O throughput.
777 */
778 cp->reply_queue = smp_processor_id() % h->nreply_queues;
779 /* Set the bits in the address sent down to include:
780 * - performant mode bit not used in ioaccel mode 2
781 * - pull count (bits 0-3)
782 * - command type isn't needed for ioaccel2
783 */
784 c->busaddr |= (h->ioaccel2_blockFetchTable[cp->sg_count]);
785}
786
e85c5974
SC		 787static int is_firmware_flash_cmd(u8 *cdb)
788{
789 return cdb[0] == BMIC_WRITE && cdb[6] == BMIC_FLASH_FIRMWARE;
790}
791
792/*
793 * During firmware flash, the heartbeat register may not update as frequently
794 * as it should. So we dial down lockup detection during firmware flash. and
795 * dial it back up when firmware flash completes.
796 */
797#define HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH (240 * HZ)
798#define HEARTBEAT_SAMPLE_INTERVAL (30 * HZ)
799static void dial_down_lockup_detection_during_fw_flash(struct ctlr_info *h,
800 struct CommandList *c)
801{
802 if (!is_firmware_flash_cmd(c->Request.CDB))
803 return;
804 atomic_inc(&h->firmware_flash_in_progress);
805 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH;
806}
807
808static void dial_up_lockup_detection_on_fw_flash_complete(struct ctlr_info *h,
809 struct CommandList *c)
810{
811 if (is_firmware_flash_cmd(c->Request.CDB) &&
812 atomic_dec_and_test(&h->firmware_flash_in_progress))
813 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
814}
815
3f5eac3a
SC		 816static void enqueue_cmd_and_start_io(struct ctlr_info *h,
817 struct CommandList *c)
818{
819 unsigned long flags;
820
c349775e
ST		 821 switch (c->cmd_type) {
822 case CMD_IOACCEL1:
823 set_ioaccel1_performant_mode(h, c);
824 break;
825 case CMD_IOACCEL2:
826 set_ioaccel2_performant_mode(h, c);
827 break;
828 default:
829 set_performant_mode(h, c);
830 }
e85c5974 831 dial_down_lockup_detection_during_fw_flash(h, c);
3f5eac3a
SC		 832 spin_lock_irqsave(&h->lock, flags);
833 addQ(&h->reqQ, c);
834 h->Qdepth++;
3f5eac3a 835 spin_unlock_irqrestore(&h->lock, flags);
e16a33ad 836 start_io(h);
3f5eac3a
SC		 837}
838
839static inline void removeQ(struct CommandList *c)
840{
841 if (WARN_ON(list_empty(&c->list)))
842 return;
843 list_del_init(&c->list);
844}
845
846static inline int is_hba_lunid(unsigned char scsi3addr[])
847{
848 return memcmp(scsi3addr, RAID_CTLR_LUNID, 8) == 0;
849}
850
851static inline int is_scsi_rev_5(struct ctlr_info *h)
852{
853 if (!h->hba_inquiry_data)
854 return 0;
855 if ((h->hba_inquiry_data[2] & 0x07) == 5)
856 return 1;
857 return 0;
858}
859
edd16368
SC		 860static int hpsa_find_target_lun(struct ctlr_info *h,
861 unsigned char scsi3addr[], int bus, int *target, int *lun)
862{
863 /* finds an unused bus, target, lun for a new physical device
864 * assumes h->devlock is held
865 */
866 int i, found = 0;
cfe5badc 867 DECLARE_BITMAP(lun_taken, HPSA_MAX_DEVICES);
edd16368 868
263d9401 869 bitmap_zero(lun_taken, HPSA_MAX_DEVICES);
edd16368
SC		 870
871 for (i = 0; i < h->ndevices; i++) {
872 if (h->dev[i]->bus == bus && h->dev[i]->target != -1)
263d9401 873 __set_bit(h->dev[i]->target, lun_taken);
edd16368
SC		 874 }
875
263d9401
AM		 876 i = find_first_zero_bit(lun_taken, HPSA_MAX_DEVICES);
877 if (i < HPSA_MAX_DEVICES) {
878 /* *bus = 1; */
879 *target = i;
880 *lun = 0;
881 found = 1;
edd16368
SC		 882 }
883 return !found;
884}
885
886/* Add an entry into h->dev[] array. */
887static int hpsa_scsi_add_entry(struct ctlr_info *h, int hostno,
888 struct hpsa_scsi_dev_t *device,
889 struct hpsa_scsi_dev_t *added[], int *nadded)
890{
891 /* assumes h->devlock is held */
892 int n = h->ndevices;
893 int i;
894 unsigned char addr1[8], addr2[8];
895 struct hpsa_scsi_dev_t *sd;
896
cfe5badc 897 if (n >= HPSA_MAX_DEVICES) {
edd16368
SC		 898 dev_err(&h->pdev->dev, "too many devices, some will be "
899 "inaccessible.\n");
900 return -1;
901 }
902
903 /* physical devices do not have lun or target assigned until now. */
904 if (device->lun != -1)
905 /* Logical device, lun is already assigned. */
906 goto lun_assigned;
907
908 /* If this device a non-zero lun of a multi-lun device
909 * byte 4 of the 8-byte LUN addr will contain the logical
910 * unit no, zero otherise.
911 */
912 if (device->scsi3addr[4] == 0) {
913 /* This is not a non-zero lun of a multi-lun device */
914 if (hpsa_find_target_lun(h, device->scsi3addr,
915 device->bus, &device->target, &device->lun) != 0)
916 return -1;
917 goto lun_assigned;
918 }
919
920 /* This is a non-zero lun of a multi-lun device.
921 * Search through our list and find the device which
922 * has the same 8 byte LUN address, excepting byte 4.
923 * Assign the same bus and target for this new LUN.
924 * Use the logical unit number from the firmware.
925 */
926 memcpy(addr1, device->scsi3addr, 8);
927 addr1[4] = 0;
928 for (i = 0; i < n; i++) {
929 sd = h->dev[i];
930 memcpy(addr2, sd->scsi3addr, 8);
931 addr2[4] = 0;
932 /* differ only in byte 4? */
933 if (memcmp(addr1, addr2, 8) == 0) {
934 device->bus = sd->bus;
935 device->target = sd->target;
936 device->lun = device->scsi3addr[4];
937 break;
938 }
939 }
940 if (device->lun == -1) {
941 dev_warn(&h->pdev->dev, "physical device with no LUN=0,"
942 " suspect firmware bug or unsupported hardware "
943 "configuration.\n");
944 return -1;
945 }
946
947lun_assigned:
948
949 h->dev[n] = device;
950 h->ndevices++;
951 added[*nadded] = device;
952 (*nadded)++;
953
954 /* initially, (before registering with scsi layer) we don't
955 * know our hostno and we don't want to print anything first
956 * time anyway (the scsi layer's inquiries will show that info)
957 */
958 /* if (hostno != -1) */
959 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d added.\n",
960 scsi_device_type(device->devtype), hostno,
961 device->bus, device->target, device->lun);
962 return 0;
963}
964
bd9244f7
ST		 965/* Update an entry in h->dev[] array. */
966static void hpsa_scsi_update_entry(struct ctlr_info *h, int hostno,
967 int entry, struct hpsa_scsi_dev_t *new_entry)
968{
969 /* assumes h->devlock is held */
970 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
971
972 /* Raid level changed. */
973 h->dev[entry]->raid_level = new_entry->raid_level;
250fb125
SC		 974
975 /* Raid offload parameters changed. */
976 h->dev[entry]->offload_config = new_entry->offload_config;
977 h->dev[entry]->offload_enabled = new_entry->offload_enabled;
9fb0de2d
SC		 978 h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
979 h->dev[entry]->offload_to_mirror = new_entry->offload_to_mirror;
980 h->dev[entry]->raid_map = new_entry->raid_map;
250fb125 981
bd9244f7
ST		 982 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d updated.\n",
983 scsi_device_type(new_entry->devtype), hostno, new_entry->bus,
984 new_entry->target, new_entry->lun);
985}
986
2a8ccf31
SC		 987/* Replace an entry from h->dev[] array. */
988static void hpsa_scsi_replace_entry(struct ctlr_info *h, int hostno,
989 int entry, struct hpsa_scsi_dev_t *new_entry,
990 struct hpsa_scsi_dev_t *added[], int *nadded,
991 struct hpsa_scsi_dev_t *removed[], int *nremoved)
992{
993 /* assumes h->devlock is held */
cfe5badc 994 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
2a8ccf31
SC		 995 removed[*nremoved] = h->dev[entry];
996 (*nremoved)++;
01350d05
SC		 997
998 /*
999 * New physical devices won't have target/lun assigned yet
1000 * so we need to preserve the values in the slot we are replacing.
1001 */
1002 if (new_entry->target == -1) {
1003 new_entry->target = h->dev[entry]->target;
1004 new_entry->lun = h->dev[entry]->lun;
1005 }
1006
2a8ccf31
SC		 1007 h->dev[entry] = new_entry;
1008 added[*nadded] = new_entry;
1009 (*nadded)++;
1010 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d changed.\n",
1011 scsi_device_type(new_entry->devtype), hostno, new_entry->bus,
1012 new_entry->target, new_entry->lun);
1013}
1014
edd16368
SC		 1015/* Remove an entry from h->dev[] array. */
1016static void hpsa_scsi_remove_entry(struct ctlr_info *h, int hostno, int entry,
1017 struct hpsa_scsi_dev_t *removed[], int *nremoved)
1018{
1019 /* assumes h->devlock is held */
1020 int i;
1021 struct hpsa_scsi_dev_t *sd;
1022
cfe5badc 1023 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
edd16368
SC		 1024
1025 sd = h->dev[entry];
1026 removed[*nremoved] = h->dev[entry];
1027 (*nremoved)++;
1028
1029 for (i = entry; i < h->ndevices-1; i++)
1030 h->dev[i] = h->dev[i+1];
1031 h->ndevices--;
1032 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d removed.\n",
1033 scsi_device_type(sd->devtype), hostno, sd->bus, sd->target,
1034 sd->lun);
1035}
1036
1037#define SCSI3ADDR_EQ(a, b) ( \
1038 (a)[7] == (b)[7] && \
1039 (a)[6] == (b)[6] && \
1040 (a)[5] == (b)[5] && \
1041 (a)[4] == (b)[4] && \
1042 (a)[3] == (b)[3] && \
1043 (a)[2] == (b)[2] && \
1044 (a)[1] == (b)[1] && \
1045 (a)[0] == (b)[0])
1046
1047static void fixup_botched_add(struct ctlr_info *h,
1048 struct hpsa_scsi_dev_t *added)
1049{
1050 /* called when scsi_add_device fails in order to re-adjust
1051 * h->dev[] to match the mid layer's view.
1052 */
1053 unsigned long flags;
1054 int i, j;
1055
1056 spin_lock_irqsave(&h->lock, flags);
1057 for (i = 0; i < h->ndevices; i++) {
1058 if (h->dev[i] == added) {
1059 for (j = i; j < h->ndevices-1; j++)
1060 h->dev[j] = h->dev[j+1];
1061 h->ndevices--;
1062 break;
1063 }
1064 }
1065 spin_unlock_irqrestore(&h->lock, flags);
1066 kfree(added);
1067}
1068
1069static inline int device_is_the_same(struct hpsa_scsi_dev_t *dev1,
1070 struct hpsa_scsi_dev_t *dev2)
1071{
edd16368
SC		 1072 /* we compare everything except lun and target as these
1073 * are not yet assigned. Compare parts likely
1074 * to differ first
1075 */
1076 if (memcmp(dev1->scsi3addr, dev2->scsi3addr,
1077 sizeof(dev1->scsi3addr)) != 0)
1078 return 0;
1079 if (memcmp(dev1->device_id, dev2->device_id,
1080 sizeof(dev1->device_id)) != 0)
1081 return 0;
1082 if (memcmp(dev1->model, dev2->model, sizeof(dev1->model)) != 0)
1083 return 0;
1084 if (memcmp(dev1->vendor, dev2->vendor, sizeof(dev1->vendor)) != 0)
1085 return 0;
edd16368
SC		 1086 if (dev1->devtype != dev2->devtype)
1087 return 0;
edd16368
SC		 1088 if (dev1->bus != dev2->bus)
1089 return 0;
1090 return 1;
1091}
1092
bd9244f7
ST		 1093static inline int device_updated(struct hpsa_scsi_dev_t *dev1,
1094 struct hpsa_scsi_dev_t *dev2)
1095{
1096 /* Device attributes that can change, but don't mean
1097 * that the device is a different device, nor that the OS
1098 * needs to be told anything about the change.
1099 */
1100 if (dev1->raid_level != dev2->raid_level)
1101 return 1;
250fb125
SC		 1102 if (dev1->offload_config != dev2->offload_config)
1103 return 1;
1104 if (dev1->offload_enabled != dev2->offload_enabled)
1105 return 1;
bd9244f7
ST		 1106 return 0;
1107}
1108
edd16368
SC		 1109/* Find needle in haystack. If exact match found, return DEVICE_SAME,
1110 * and return needle location in *index. If scsi3addr matches, but not
1111 * vendor, model, serial num, etc. return DEVICE_CHANGED, and return needle
bd9244f7
ST		 1112 * location in *index.
1113 * In the case of a minor device attribute change, such as RAID level, just
1114 * return DEVICE_UPDATED, along with the updated device's location in index.
1115 * If needle not found, return DEVICE_NOT_FOUND.
edd16368
SC		 1116 */
1117static int hpsa_scsi_find_entry(struct hpsa_scsi_dev_t *needle,
1118 struct hpsa_scsi_dev_t *haystack[], int haystack_size,
1119 int *index)
1120{
1121 int i;
1122#define DEVICE_NOT_FOUND 0
1123#define DEVICE_CHANGED 1
1124#define DEVICE_SAME 2
bd9244f7 1125#define DEVICE_UPDATED 3
edd16368 1126 for (i = 0; i < haystack_size; i++) {
23231048
SC		 1127 if (haystack[i] == NULL) /* previously removed. */
1128 continue;
edd16368
SC		 1129 if (SCSI3ADDR_EQ(needle->scsi3addr, haystack[i]->scsi3addr)) {
1130 *index = i;
bd9244f7
ST		 1131 if (device_is_the_same(needle, haystack[i])) {
1132 if (device_updated(needle, haystack[i]))
1133 return DEVICE_UPDATED;
edd16368 1134 return DEVICE_SAME;
bd9244f7 1135 } else {
9846590e
SC		 1136 /* Keep offline devices offline */
1137 if (needle->volume_offline)
1138 return DEVICE_NOT_FOUND;
edd16368 1139 return DEVICE_CHANGED;
bd9244f7 1140 }
edd16368
SC		 1141 }
1142 }
1143 *index = -1;
1144 return DEVICE_NOT_FOUND;
1145}
1146
9846590e
SC		 1147static void hpsa_monitor_offline_device(struct ctlr_info *h,
1148 unsigned char scsi3addr[])
1149{
1150 struct offline_device_entry *device;
1151 unsigned long flags;
1152
1153 /* Check to see if device is already on the list */
1154 spin_lock_irqsave(&h->offline_device_lock, flags);
1155 list_for_each_entry(device, &h->offline_device_list, offline_list) {
1156 if (memcmp(device->scsi3addr, scsi3addr,
1157 sizeof(device->scsi3addr)) == 0) {
1158 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1159 return;
1160 }
1161 }
1162 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1163
1164 /* Device is not on the list, add it. */
1165 device = kmalloc(sizeof(*device), GFP_KERNEL);
1166 if (!device) {
1167 dev_warn(&h->pdev->dev, "out of memory in %s\n", __func__);
1168 return;
1169 }
1170 memcpy(device->scsi3addr, scsi3addr, sizeof(device->scsi3addr));
1171 spin_lock_irqsave(&h->offline_device_lock, flags);
1172 list_add_tail(&device->offline_list, &h->offline_device_list);
1173 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1174}
1175
1176/* Print a message explaining various offline volume states */
1177static void hpsa_show_volume_status(struct ctlr_info *h,
1178 struct hpsa_scsi_dev_t *sd)
1179{
1180 if (sd->volume_offline == HPSA_VPD_LV_STATUS_UNSUPPORTED)
1181 dev_info(&h->pdev->dev,
1182 "C%d:B%d:T%d:L%d Volume status is not available through vital product data pages.\n",
1183 h->scsi_host->host_no,
1184 sd->bus, sd->target, sd->lun);
1185 switch (sd->volume_offline) {
1186 case HPSA_LV_OK:
1187 break;
1188 case HPSA_LV_UNDERGOING_ERASE:
1189 dev_info(&h->pdev->dev,
1190 "C%d:B%d:T%d:L%d Volume is undergoing background erase process.\n",
1191 h->scsi_host->host_no,
1192 sd->bus, sd->target, sd->lun);
1193 break;
1194 case HPSA_LV_UNDERGOING_RPI:
1195 dev_info(&h->pdev->dev,
1196 "C%d:B%d:T%d:L%d Volume is undergoing rapid parity initialization process.\n",
1197 h->scsi_host->host_no,
1198 sd->bus, sd->target, sd->lun);
1199 break;
1200 case HPSA_LV_PENDING_RPI:
1201 dev_info(&h->pdev->dev,
1202 "C%d:B%d:T%d:L%d Volume is queued for rapid parity initialization process.\n",
1203 h->scsi_host->host_no,
1204 sd->bus, sd->target, sd->lun);
1205 break;
1206 case HPSA_LV_ENCRYPTED_NO_KEY:
1207 dev_info(&h->pdev->dev,
1208 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because key is not present.\n",
1209 h->scsi_host->host_no,
1210 sd->bus, sd->target, sd->lun);
1211 break;
1212 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
1213 dev_info(&h->pdev->dev,
1214 "C%d:B%d:T%d:L%d Volume is not encrypted and cannot be accessed because controller is in encryption-only mode.\n",
1215 h->scsi_host->host_no,
1216 sd->bus, sd->target, sd->lun);
1217 break;
1218 case HPSA_LV_UNDERGOING_ENCRYPTION:
1219 dev_info(&h->pdev->dev,
1220 "C%d:B%d:T%d:L%d Volume is undergoing encryption process.\n",
1221 h->scsi_host->host_no,
1222 sd->bus, sd->target, sd->lun);
1223 break;
1224 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
1225 dev_info(&h->pdev->dev,
1226 "C%d:B%d:T%d:L%d Volume is undergoing encryption re-keying process.\n",
1227 h->scsi_host->host_no,
1228 sd->bus, sd->target, sd->lun);
1229 break;
1230 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
1231 dev_info(&h->pdev->dev,
1232 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because controller does not have encryption enabled.\n",
1233 h->scsi_host->host_no,
1234 sd->bus, sd->target, sd->lun);
1235 break;
1236 case HPSA_LV_PENDING_ENCRYPTION:
1237 dev_info(&h->pdev->dev,
1238 "C%d:B%d:T%d:L%d Volume is pending migration to encrypted state, but process has not started.\n",
1239 h->scsi_host->host_no,
1240 sd->bus, sd->target, sd->lun);
1241 break;
1242 case HPSA_LV_PENDING_ENCRYPTION_REKEYING:
1243 dev_info(&h->pdev->dev,
1244 "C%d:B%d:T%d:L%d Volume is encrypted and is pending encryption rekeying.\n",
1245 h->scsi_host->host_no,
1246 sd->bus, sd->target, sd->lun);
1247 break;
1248 }
1249}
1250
4967bd3e 1251static void adjust_hpsa_scsi_table(struct ctlr_info *h, int hostno,
edd16368
SC		 1252 struct hpsa_scsi_dev_t *sd[], int nsds)
1253{
1254 /* sd contains scsi3 addresses and devtypes, and inquiry
1255 * data. This function takes what's in sd to be the current
1256 * reality and updates h->dev[] to reflect that reality.
1257 */
1258 int i, entry, device_change, changes = 0;
1259 struct hpsa_scsi_dev_t *csd;
1260 unsigned long flags;
1261 struct hpsa_scsi_dev_t **added, **removed;
1262 int nadded, nremoved;
1263 struct Scsi_Host *sh = NULL;
1264
cfe5badc
ST		 1265 added = kzalloc(sizeof(*added) * HPSA_MAX_DEVICES, GFP_KERNEL);
1266 removed = kzalloc(sizeof(*removed) * HPSA_MAX_DEVICES, GFP_KERNEL);
edd16368
SC		 1267
1268 if (!added || !removed) {
1269 dev_warn(&h->pdev->dev, "out of memory in "
1270 "adjust_hpsa_scsi_table\n");
1271 goto free_and_out;
1272 }
1273
1274 spin_lock_irqsave(&h->devlock, flags);
1275
1276 /* find any devices in h->dev[] that are not in
1277 * sd[] and remove them from h->dev[], and for any
1278 * devices which have changed, remove the old device
1279 * info and add the new device info.
bd9244f7
ST		 1280 * If minor device attributes change, just update
1281 * the existing device structure.
edd16368
SC		 1282 */
1283 i = 0;
1284 nremoved = 0;
1285 nadded = 0;
1286 while (i < h->ndevices) {
1287 csd = h->dev[i];
1288 device_change = hpsa_scsi_find_entry(csd, sd, nsds, &entry);
1289 if (device_change == DEVICE_NOT_FOUND) {
1290 changes++;
1291 hpsa_scsi_remove_entry(h, hostno, i,
1292 removed, &nremoved);
1293 continue; /* remove ^^^, hence i not incremented */
1294 } else if (device_change == DEVICE_CHANGED) {
1295 changes++;
2a8ccf31
SC		 1296 hpsa_scsi_replace_entry(h, hostno, i, sd[entry],
1297 added, &nadded, removed, &nremoved);
c7f172dc
SC		 1298 /* Set it to NULL to prevent it from being freed
1299 * at the bottom of hpsa_update_scsi_devices()
1300 */
1301 sd[entry] = NULL;
bd9244f7
ST		 1302 } else if (device_change == DEVICE_UPDATED) {
1303 hpsa_scsi_update_entry(h, hostno, i, sd[entry]);
edd16368
SC		 1304 }
1305 i++;
1306 }
1307
1308 /* Now, make sure every device listed in sd[] is also
1309 * listed in h->dev[], adding them if they aren't found
1310 */
1311
1312 for (i = 0; i < nsds; i++) {
1313 if (!sd[i]) /* if already added above. */
1314 continue;
9846590e
SC		 1315
1316 /* Don't add devices which are NOT READY, FORMAT IN PROGRESS
1317 * as the SCSI mid-layer does not handle such devices well.
1318 * It relentlessly loops sending TUR at 3Hz, then READ(10)
1319 * at 160Hz, and prevents the system from coming up.
1320 */
1321 if (sd[i]->volume_offline) {
1322 hpsa_show_volume_status(h, sd[i]);
1323 dev_info(&h->pdev->dev, "c%db%dt%dl%d: temporarily offline\n",
1324 h->scsi_host->host_no,
1325 sd[i]->bus, sd[i]->target, sd[i]->lun);
1326 continue;
1327 }
1328
edd16368
SC		 1329 device_change = hpsa_scsi_find_entry(sd[i], h->dev,
1330 h->ndevices, &entry);
1331 if (device_change == DEVICE_NOT_FOUND) {
1332 changes++;
1333 if (hpsa_scsi_add_entry(h, hostno, sd[i],
1334 added, &nadded) != 0)
1335 break;
1336 sd[i] = NULL; /* prevent from being freed later. */
1337 } else if (device_change == DEVICE_CHANGED) {
1338 /* should never happen... */
1339 changes++;
1340 dev_warn(&h->pdev->dev,
1341 "device unexpectedly changed.\n");
1342 /* but if it does happen, we just ignore that device */
1343 }
1344 }
1345 spin_unlock_irqrestore(&h->devlock, flags);
1346
9846590e
SC		 1347 /* Monitor devices which are in one of several NOT READY states to be
1348 * brought online later. This must be done without holding h->devlock,
1349 * so don't touch h->dev[]
1350 */
1351 for (i = 0; i < nsds; i++) {
1352 if (!sd[i]) /* if already added above. */
1353 continue;
1354 if (sd[i]->volume_offline)
1355 hpsa_monitor_offline_device(h, sd[i]->scsi3addr);
1356 }
1357
edd16368
SC		 1358 /* Don't notify scsi mid layer of any changes the first time through
1359 * (or if there are no changes) scsi_scan_host will do it later the
1360 * first time through.
1361 */
1362 if (hostno == -1 || !changes)
1363 goto free_and_out;
1364
1365 sh = h->scsi_host;
1366 /* Notify scsi mid layer of any removed devices */
1367 for (i = 0; i < nremoved; i++) {
1368 struct scsi_device *sdev =
1369 scsi_device_lookup(sh, removed[i]->bus,
1370 removed[i]->target, removed[i]->lun);
1371 if (sdev != NULL) {
1372 scsi_remove_device(sdev);
1373 scsi_device_put(sdev);
1374 } else {
1375 /* We don't expect to get here.
1376 * future cmds to this device will get selection
1377 * timeout as if the device was gone.
1378 */
1379 dev_warn(&h->pdev->dev, "didn't find c%db%dt%dl%d "
1380 " for removal.", hostno, removed[i]->bus,
1381 removed[i]->target, removed[i]->lun);
1382 }
1383 kfree(removed[i]);
1384 removed[i] = NULL;
1385 }
1386
1387 /* Notify scsi mid layer of any added devices */
1388 for (i = 0; i < nadded; i++) {
1389 if (scsi_add_device(sh, added[i]->bus,
1390 added[i]->target, added[i]->lun) == 0)
1391 continue;
1392 dev_warn(&h->pdev->dev, "scsi_add_device c%db%dt%dl%d failed, "
1393 "device not added.\n", hostno, added[i]->bus,
1394 added[i]->target, added[i]->lun);
1395 /* now we have to remove it from h->dev,
1396 * since it didn't get added to scsi mid layer
1397 */
1398 fixup_botched_add(h, added[i]);
1399 }
1400
1401free_and_out:
1402 kfree(added);
1403 kfree(removed);
edd16368
SC		 1404}
1405
1406/*
9e03aa2f 1407 * Lookup bus/target/lun and return corresponding struct hpsa_scsi_dev_t *
edd16368
SC		 1408 * Assume's h->devlock is held.
1409 */
1410static struct hpsa_scsi_dev_t *lookup_hpsa_scsi_dev(struct ctlr_info *h,
1411 int bus, int target, int lun)
1412{
1413 int i;
1414 struct hpsa_scsi_dev_t *sd;
1415
1416 for (i = 0; i < h->ndevices; i++) {
1417 sd = h->dev[i];
1418 if (sd->bus == bus && sd->target == target && sd->lun == lun)
1419 return sd;
1420 }
1421 return NULL;
1422}
1423
1424/* link sdev->hostdata to our per-device structure. */
1425static int hpsa_slave_alloc(struct scsi_device *sdev)
1426{
1427 struct hpsa_scsi_dev_t *sd;
1428 unsigned long flags;
1429 struct ctlr_info *h;
1430
1431 h = sdev_to_hba(sdev);
1432 spin_lock_irqsave(&h->devlock, flags);
1433 sd = lookup_hpsa_scsi_dev(h, sdev_channel(sdev),
1434 sdev_id(sdev), sdev->lun);
1435 if (sd != NULL)
1436 sdev->hostdata = sd;
1437 spin_unlock_irqrestore(&h->devlock, flags);
1438 return 0;
1439}
1440
1441static void hpsa_slave_destroy(struct scsi_device *sdev)
1442{
bcc44255 1443 /* nothing to do. */
edd16368
SC		 1444}
1445
33a2ffce
SC		 1446static void hpsa_free_sg_chain_blocks(struct ctlr_info *h)
1447{
1448 int i;
1449
1450 if (!h->cmd_sg_list)
1451 return;
1452 for (i = 0; i < h->nr_cmds; i++) {
1453 kfree(h->cmd_sg_list[i]);
1454 h->cmd_sg_list[i] = NULL;
1455 }
1456 kfree(h->cmd_sg_list);
1457 h->cmd_sg_list = NULL;
1458}
1459
1460static int hpsa_allocate_sg_chain_blocks(struct ctlr_info *h)
1461{
1462 int i;
1463
1464 if (h->chainsize <= 0)
1465 return 0;
1466
1467 h->cmd_sg_list = kzalloc(sizeof(*h->cmd_sg_list) * h->nr_cmds,
1468 GFP_KERNEL);
1469 if (!h->cmd_sg_list)
1470 return -ENOMEM;
1471 for (i = 0; i < h->nr_cmds; i++) {
1472 h->cmd_sg_list[i] = kmalloc(sizeof(*h->cmd_sg_list[i]) *
1473 h->chainsize, GFP_KERNEL);
1474 if (!h->cmd_sg_list[i])
1475 goto clean;
1476 }
1477 return 0;
1478
1479clean:
1480 hpsa_free_sg_chain_blocks(h);
1481 return -ENOMEM;
1482}
1483
e2bea6df 1484static int hpsa_map_sg_chain_block(struct ctlr_info *h,
33a2ffce
SC		 1485 struct CommandList *c)
1486{
1487 struct SGDescriptor *chain_sg, *chain_block;
1488 u64 temp64;
1489
1490 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
1491 chain_block = h->cmd_sg_list[c->cmdindex];
1492 chain_sg->Ext = HPSA_SG_CHAIN;
1493 chain_sg->Len = sizeof(*chain_sg) *
1494 (c->Header.SGTotal - h->max_cmd_sg_entries);
1495 temp64 = pci_map_single(h->pdev, chain_block, chain_sg->Len,
1496 PCI_DMA_TODEVICE);
e2bea6df
SC		 1497 if (dma_mapping_error(&h->pdev->dev, temp64)) {
1498 /* prevent subsequent unmapping */
1499 chain_sg->Addr.lower = 0;
1500 chain_sg->Addr.upper = 0;
1501 return -1;
1502 }
33a2ffce
SC		 1503 chain_sg->Addr.lower = (u32) (temp64 & 0x0FFFFFFFFULL);
1504 chain_sg->Addr.upper = (u32) ((temp64 >> 32) & 0x0FFFFFFFFULL);
e2bea6df 1505 return 0;
33a2ffce
SC		 1506}
1507
1508static void hpsa_unmap_sg_chain_block(struct ctlr_info *h,
1509 struct CommandList *c)
1510{
1511 struct SGDescriptor *chain_sg;
1512 union u64bit temp64;
1513
1514 if (c->Header.SGTotal <= h->max_cmd_sg_entries)
1515 return;
1516
1517 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
1518 temp64.val32.lower = chain_sg->Addr.lower;
1519 temp64.val32.upper = chain_sg->Addr.upper;
1520 pci_unmap_single(h->pdev, temp64.val, chain_sg->Len, PCI_DMA_TODEVICE);
1521}
1522
a09c1441
ST		 1523
1524/* Decode the various types of errors on ioaccel2 path.
1525 * Return 1 for any error that should generate a RAID path retry.
1526 * Return 0 for errors that don't require a RAID path retry.
1527 */
1528static int handle_ioaccel_mode2_error(struct ctlr_info *h,
c349775e
ST		 1529 struct CommandList *c,
1530 struct scsi_cmnd *cmd,
1531 struct io_accel2_cmd *c2)
1532{
1533 int data_len;
a09c1441 1534 int retry = 0;
c349775e
ST		 1535
1536 switch (c2->error_data.serv_response) {
1537 case IOACCEL2_SERV_RESPONSE_COMPLETE:
1538 switch (c2->error_data.status) {
1539 case IOACCEL2_STATUS_SR_TASK_COMP_GOOD:
1540 break;
1541 case IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND:
1542 dev_warn(&h->pdev->dev,
1543 "%s: task complete with check condition.\n",
1544 "HP SSD Smart Path");
1545 if (c2->error_data.data_present !=
1546 IOACCEL2_SENSE_DATA_PRESENT)
1547 break;
1548 /* copy the sense data */
1549 data_len = c2->error_data.sense_data_len;
1550 if (data_len > SCSI_SENSE_BUFFERSIZE)
1551 data_len = SCSI_SENSE_BUFFERSIZE;
1552 if (data_len > sizeof(c2->error_data.sense_data_buff))
1553 data_len =
1554 sizeof(c2->error_data.sense_data_buff);
1555 memcpy(cmd->sense_buffer,
1556 c2->error_data.sense_data_buff, data_len);
1557 cmd->result |= SAM_STAT_CHECK_CONDITION;
a09c1441 1558 retry = 1;
c349775e
ST		 1559 break;
1560 case IOACCEL2_STATUS_SR_TASK_COMP_BUSY:
1561 dev_warn(&h->pdev->dev,
1562 "%s: task complete with BUSY status.\n",
1563 "HP SSD Smart Path");
a09c1441 1564 retry = 1;
c349775e
ST		 1565 break;
1566 case IOACCEL2_STATUS_SR_TASK_COMP_RES_CON:
1567 dev_warn(&h->pdev->dev,
1568 "%s: task complete with reservation conflict.\n",
1569 "HP SSD Smart Path");
a09c1441 1570 retry = 1;
c349775e
ST		 1571 break;
1572 case IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL:
1573 /* Make scsi midlayer do unlimited retries */
1574 cmd->result = DID_IMM_RETRY << 16;
1575 break;
1576 case IOACCEL2_STATUS_SR_TASK_COMP_ABORTED:
1577 dev_warn(&h->pdev->dev,
1578 "%s: task complete with aborted status.\n",
1579 "HP SSD Smart Path");
a09c1441 1580 retry = 1;
c349775e
ST		 1581 break;
1582 default:
1583 dev_warn(&h->pdev->dev,
1584 "%s: task complete with unrecognized status: 0x%02x\n",
1585 "HP SSD Smart Path", c2->error_data.status);
a09c1441 1586 retry = 1;
c349775e
ST		 1587 break;
1588 }
1589 break;
1590 case IOACCEL2_SERV_RESPONSE_FAILURE:
1591 /* don't expect to get here. */
1592 dev_warn(&h->pdev->dev,
1593 "unexpected delivery or target failure, status = 0x%02x\n",
1594 c2->error_data.status);
a09c1441 1595 retry = 1;
c349775e
ST		 1596 break;
1597 case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE:
1598 break;
1599 case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS:
1600 break;
1601 case IOACCEL2_SERV_RESPONSE_TMF_REJECTED:
1602 dev_warn(&h->pdev->dev, "task management function rejected.\n");
a09c1441 1603 retry = 1;
c349775e
ST		 1604 break;
1605 case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN:
1606 dev_warn(&h->pdev->dev, "task management function invalid LUN\n");
1607 break;
1608 default:
1609 dev_warn(&h->pdev->dev,
1610 "%s: Unrecognized server response: 0x%02x\n",
a09c1441
ST		 1611 "HP SSD Smart Path",
1612 c2->error_data.serv_response);
1613 retry = 1;
c349775e
ST		 1614 break;
1615 }
a09c1441
ST		 1616
1617 return retry; /* retry on raid path? */
c349775e
ST		 1618}
1619
1620static void process_ioaccel2_completion(struct ctlr_info *h,
1621 struct CommandList *c, struct scsi_cmnd *cmd,
1622 struct hpsa_scsi_dev_t *dev)
1623{
1624 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
a09c1441 1625 int raid_retry = 0;
c349775e
ST		 1626
1627 /* check for good status */
1628 if (likely(c2->error_data.serv_response == 0 &&
1629 c2->error_data.status == 0)) {
1630 cmd_free(h, c);
1631 cmd->scsi_done(cmd);
1632 return;
1633 }
1634
1635 /* Any RAID offload error results in retry which will use
1636 * the normal I/O path so the controller can handle whatever's
1637 * wrong.
1638 */
1639 if (is_logical_dev_addr_mode(dev->scsi3addr) &&
1640 c2->error_data.serv_response ==
1641 IOACCEL2_SERV_RESPONSE_FAILURE) {
a09c1441
ST		 1642 if (c2->error_data.status ==
1643 IOACCEL2_STATUS_SR_IOACCEL_DISABLED)
1644 dev_warn(&h->pdev->dev,
1645 "%s: Path is unavailable, retrying on standard path.\n",
1646 "HP SSD Smart Path");
1647 else
c349775e 1648 dev_warn(&h->pdev->dev,
a09c1441 1649 "%s: Error 0x%02x, retrying on standard path.\n",
c349775e 1650 "HP SSD Smart Path", c2->error_data.status);
a09c1441 1651
c349775e 1652 dev->offload_enabled = 0;
e863d68e 1653 h->drv_req_rescan = 1; /* schedule controller for a rescan */
c349775e
ST		 1654 cmd->result = DID_SOFT_ERROR << 16;
1655 cmd_free(h, c);
1656 cmd->scsi_done(cmd);
1657 return;
1658 }
a09c1441
ST		 1659 raid_retry = handle_ioaccel_mode2_error(h, c, cmd, c2);
1660 /* If error found, disable Smart Path, schedule a rescan,
1661 * and force a retry on the standard path.
1662 */
1663 if (raid_retry) {
1664 dev_warn(&h->pdev->dev, "%s: Retrying on standard path.\n",
1665 "HP SSD Smart Path");
1666 dev->offload_enabled = 0; /* Disable Smart Path */
1667 h->drv_req_rescan = 1; /* schedule controller rescan */
1668 cmd->result = DID_SOFT_ERROR << 16;
1669 }
c349775e
ST		 1670 cmd_free(h, c);
1671 cmd->scsi_done(cmd);
1672}
1673
1fb011fb 1674static void complete_scsi_command(struct CommandList *cp)
edd16368
SC		 1675{
1676 struct scsi_cmnd *cmd;
1677 struct ctlr_info *h;
1678 struct ErrorInfo *ei;
283b4a9b 1679 struct hpsa_scsi_dev_t *dev;
edd16368
SC		 1680
1681 unsigned char sense_key;
1682 unsigned char asc; /* additional sense code */
1683 unsigned char ascq; /* additional sense code qualifier */
db111e18 1684 unsigned long sense_data_size;
edd16368
SC		 1685
1686 ei = cp->err_info;
1687 cmd = (struct scsi_cmnd *) cp->scsi_cmd;
1688 h = cp->h;
283b4a9b 1689 dev = cmd->device->hostdata;
edd16368
SC		 1690
1691 scsi_dma_unmap(cmd); /* undo the DMA mappings */
e1f7de0c
MG		 1692 if ((cp->cmd_type == CMD_SCSI) &&
1693 (cp->Header.SGTotal > h->max_cmd_sg_entries))
33a2ffce 1694 hpsa_unmap_sg_chain_block(h, cp);
edd16368
SC		 1695
1696 cmd->result = (DID_OK << 16); /* host byte */
1697 cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
c349775e
ST		 1698
1699 if (cp->cmd_type == CMD_IOACCEL2)
1700 return process_ioaccel2_completion(h, cp, cmd, dev);
1701
5512672f 1702 cmd->result |= ei->ScsiStatus;
edd16368
SC		 1703
1704 /* copy the sense data whether we need to or not. */
db111e18
SC		 1705 if (SCSI_SENSE_BUFFERSIZE < sizeof(ei->SenseInfo))
1706 sense_data_size = SCSI_SENSE_BUFFERSIZE;
1707 else
1708 sense_data_size = sizeof(ei->SenseInfo);
1709 if (ei->SenseLen < sense_data_size)
1710 sense_data_size = ei->SenseLen;
1711
1712 memcpy(cmd->sense_buffer, ei->SenseInfo, sense_data_size);
edd16368
SC		 1713 scsi_set_resid(cmd, ei->ResidualCnt);
1714
1715 if (ei->CommandStatus == 0) {
edd16368 1716 cmd_free(h, cp);
2cc5bfaf 1717 cmd->scsi_done(cmd);
edd16368
SC		 1718 return;
1719 }
1720
e1f7de0c
MG		 1721 /* For I/O accelerator commands, copy over some fields to the normal
1722 * CISS header used below for error handling.
1723 */
1724 if (cp->cmd_type == CMD_IOACCEL1) {
1725 struct io_accel1_cmd *c = &h->ioaccel_cmd_pool[cp->cmdindex];
1726 cp->Header.SGList = cp->Header.SGTotal = scsi_sg_count(cmd);
1727 cp->Request.CDBLen = c->io_flags & IOACCEL1_IOFLAGS_CDBLEN_MASK;
1728 cp->Header.Tag.lower = c->Tag.lower;
1729 cp->Header.Tag.upper = c->Tag.upper;
1730 memcpy(cp->Header.LUN.LunAddrBytes, c->CISS_LUN, 8);
1731 memcpy(cp->Request.CDB, c->CDB, cp->Request.CDBLen);
283b4a9b
SC		 1732
1733 /* Any RAID offload error results in retry which will use
1734 * the normal I/O path so the controller can handle whatever's
1735 * wrong.
1736 */
1737 if (is_logical_dev_addr_mode(dev->scsi3addr)) {
1738 if (ei->CommandStatus == CMD_IOACCEL_DISABLED)
1739 dev->offload_enabled = 0;
1740 cmd->result = DID_SOFT_ERROR << 16;
1741 cmd_free(h, cp);
1742 cmd->scsi_done(cmd);
1743 return;
1744 }
e1f7de0c
MG		 1745 }
1746
edd16368
SC		 1747 /* an error has occurred */
1748 switch (ei->CommandStatus) {
1749
1750 case CMD_TARGET_STATUS:
1751 if (ei->ScsiStatus) {
1752 /* Get sense key */
1753 sense_key = 0xf & ei->SenseInfo[2];
1754 /* Get additional sense code */
1755 asc = ei->SenseInfo[12];
1756 /* Get addition sense code qualifier */
1757 ascq = ei->SenseInfo[13];
1758 }
1759
1760 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION) {
3ce438df 1761 if (check_for_unit_attention(h, cp))
edd16368 1762 break;
edd16368
SC		 1763 if (sense_key == ILLEGAL_REQUEST) {
1764 /*
1765 * SCSI REPORT_LUNS is commonly unsupported on
1766 * Smart Array. Suppress noisy complaint.
1767 */
1768 if (cp->Request.CDB[0] == REPORT_LUNS)
1769 break;
1770
1771 /* If ASC/ASCQ indicate Logical Unit
1772 * Not Supported condition,
1773 */
1774 if ((asc == 0x25) && (ascq == 0x0)) {
1775 dev_warn(&h->pdev->dev, "cp %p "
1776 "has check condition\n", cp);
1777 break;
1778 }
1779 }
1780
1781 if (sense_key == NOT_READY) {
1782 /* If Sense is Not Ready, Logical Unit
1783 * Not ready, Manual Intervention
1784 * required
1785 */
1786 if ((asc == 0x04) && (ascq == 0x03)) {
edd16368
SC		 1787 dev_warn(&h->pdev->dev, "cp %p "
1788 "has check condition: unit "
1789 "not ready, manual "
1790 "intervention required\n", cp);
1791 break;
1792 }
1793 }
1d3b3609
MG		 1794 if (sense_key == ABORTED_COMMAND) {
1795 /* Aborted command is retryable */
1796 dev_warn(&h->pdev->dev, "cp %p "
1797 "has check condition: aborted command: "
1798 "ASC: 0x%x, ASCQ: 0x%x\n",
1799 cp, asc, ascq);
2e311fba 1800 cmd->result |= DID_SOFT_ERROR << 16;
1d3b3609
MG		 1801 break;
1802 }
edd16368 1803 /* Must be some other type of check condition */
21b8e4ef 1804 dev_dbg(&h->pdev->dev, "cp %p has check condition: "
edd16368
SC		 1805 "unknown type: "
1806 "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
1807 "Returning result: 0x%x, "
1808 "cmd=[%02x %02x %02x %02x %02x "
807be732 1809 "%02x %02x %02x %02x %02x %02x "
edd16368
SC		 1810 "%02x %02x %02x %02x %02x]\n",
1811 cp, sense_key, asc, ascq,
1812 cmd->result,
1813 cmd->cmnd[0], cmd->cmnd[1],
1814 cmd->cmnd[2], cmd->cmnd[3],
1815 cmd->cmnd[4], cmd->cmnd[5],
1816 cmd->cmnd[6], cmd->cmnd[7],
807be732
MM		 1817 cmd->cmnd[8], cmd->cmnd[9],
1818 cmd->cmnd[10], cmd->cmnd[11],
1819 cmd->cmnd[12], cmd->cmnd[13],
1820 cmd->cmnd[14], cmd->cmnd[15]);
edd16368
SC		 1821 break;
1822 }
1823
1824
1825 /* Problem was not a check condition
1826 * Pass it up to the upper layers...
1827 */
1828 if (ei->ScsiStatus) {
1829 dev_warn(&h->pdev->dev, "cp %p has status 0x%x "
1830 "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
1831 "Returning result: 0x%x\n",
1832 cp, ei->ScsiStatus,
1833 sense_key, asc, ascq,
1834 cmd->result);
1835 } else { /* scsi status is zero??? How??? */
1836 dev_warn(&h->pdev->dev, "cp %p SCSI status was 0. "
1837 "Returning no connection.\n", cp),
1838
1839 /* Ordinarily, this case should never happen,
1840 * but there is a bug in some released firmware
1841 * revisions that allows it to happen if, for
1842 * example, a 4100 backplane loses power and
1843 * the tape drive is in it. We assume that
1844 * it's a fatal error of some kind because we
1845 * can't show that it wasn't. We will make it
1846 * look like selection timeout since that is
1847 * the most common reason for this to occur,
1848 * and it's severe enough.
1849 */
1850
1851 cmd->result = DID_NO_CONNECT << 16;
1852 }
1853 break;
1854
1855 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
1856 break;
1857 case CMD_DATA_OVERRUN:
1858 dev_warn(&h->pdev->dev, "cp %p has"
1859 " completed with data overrun "
1860 "reported\n", cp);
1861 break;
1862 case CMD_INVALID: {
1863 /* print_bytes(cp, sizeof(*cp), 1, 0);
1864 print_cmd(cp); */
1865 /* We get CMD_INVALID if you address a non-existent device
1866 * instead of a selection timeout (no response). You will
1867 * see this if you yank out a drive, then try to access it.
1868 * This is kind of a shame because it means that any other
1869 * CMD_INVALID (e.g. driver bug) will get interpreted as a
1870 * missing target. */
1871 cmd->result = DID_NO_CONNECT << 16;
1872 }
1873 break;
1874 case CMD_PROTOCOL_ERR:
256d0eaa 1875 cmd->result = DID_ERROR << 16;
edd16368 1876 dev_warn(&h->pdev->dev, "cp %p has "
256d0eaa 1877 "protocol error\n", cp);
edd16368
SC		 1878 break;
1879 case CMD_HARDWARE_ERR:
1880 cmd->result = DID_ERROR << 16;
1881 dev_warn(&h->pdev->dev, "cp %p had hardware error\n", cp);
1882 break;
1883 case CMD_CONNECTION_LOST:
1884 cmd->result = DID_ERROR << 16;
1885 dev_warn(&h->pdev->dev, "cp %p had connection lost\n", cp);
1886 break;
1887 case CMD_ABORTED:
1888 cmd->result = DID_ABORT << 16;
1889 dev_warn(&h->pdev->dev, "cp %p was aborted with status 0x%x\n",
1890 cp, ei->ScsiStatus);
1891 break;
1892 case CMD_ABORT_FAILED:
1893 cmd->result = DID_ERROR << 16;
1894 dev_warn(&h->pdev->dev, "cp %p reports abort failed\n", cp);
1895 break;
1896 case CMD_UNSOLICITED_ABORT:
f6e76055
SC		 1897 cmd->result = DID_SOFT_ERROR << 16; /* retry the command */
1898 dev_warn(&h->pdev->dev, "cp %p aborted due to an unsolicited "
edd16368
SC		 1899 "abort\n", cp);
1900 break;
1901 case CMD_TIMEOUT:
1902 cmd->result = DID_TIME_OUT << 16;
1903 dev_warn(&h->pdev->dev, "cp %p timedout\n", cp);
1904 break;
1d5e2ed0
SC		 1905 case CMD_UNABORTABLE:
1906 cmd->result = DID_ERROR << 16;
1907 dev_warn(&h->pdev->dev, "Command unabortable\n");
1908 break;
283b4a9b
SC		 1909 case CMD_IOACCEL_DISABLED:
1910 /* This only handles the direct pass-through case since RAID
1911 * offload is handled above. Just attempt a retry.
1912 */
1913 cmd->result = DID_SOFT_ERROR << 16;
1914 dev_warn(&h->pdev->dev,
1915 "cp %p had HP SSD Smart Path error\n", cp);
1916 break;
edd16368
SC		 1917 default:
1918 cmd->result = DID_ERROR << 16;
1919 dev_warn(&h->pdev->dev, "cp %p returned unknown status %x\n",
1920 cp, ei->CommandStatus);
1921 }
edd16368 1922 cmd_free(h, cp);
2cc5bfaf 1923 cmd->scsi_done(cmd);
edd16368
SC		 1924}
1925
edd16368
SC		 1926static void hpsa_pci_unmap(struct pci_dev *pdev,
1927 struct CommandList *c, int sg_used, int data_direction)
1928{
1929 int i;
1930 union u64bit addr64;
1931
1932 for (i = 0; i < sg_used; i++) {
1933 addr64.val32.lower = c->SG[i].Addr.lower;
1934 addr64.val32.upper = c->SG[i].Addr.upper;
1935 pci_unmap_single(pdev, (dma_addr_t) addr64.val, c->SG[i].Len,
1936 data_direction);
1937 }
1938}
1939
a2dac136 1940static int hpsa_map_one(struct pci_dev *pdev,
edd16368
SC		 1941 struct CommandList *cp,
1942 unsigned char *buf,
1943 size_t buflen,
1944 int data_direction)
1945{
01a02ffc 1946 u64 addr64;
edd16368
SC		 1947
1948 if (buflen == 0 || data_direction == PCI_DMA_NONE) {
1949 cp->Header.SGList = 0;
1950 cp->Header.SGTotal = 0;
a2dac136 1951 return 0;
edd16368
SC		 1952 }
1953
01a02ffc 1954 addr64 = (u64) pci_map_single(pdev, buf, buflen, data_direction);
eceaae18 1955 if (dma_mapping_error(&pdev->dev, addr64)) {
a2dac136 1956 /* Prevent subsequent unmap of something never mapped */
eceaae18
SK		 1957 cp->Header.SGList = 0;
1958 cp->Header.SGTotal = 0;
a2dac136 1959 return -1;
eceaae18 1960 }
edd16368 1961 cp->SG[0].Addr.lower =
01a02ffc 1962 (u32) (addr64 & (u64) 0x00000000FFFFFFFF);
edd16368 1963 cp->SG[0].Addr.upper =
01a02ffc 1964 (u32) ((addr64 >> 32) & (u64) 0x00000000FFFFFFFF);
edd16368 1965 cp->SG[0].Len = buflen;
e1d9cbfa 1966 cp->SG[0].Ext = HPSA_SG_LAST; /* we are not chaining */
01a02ffc
SC		 1967 cp->Header.SGList = (u8) 1; /* no. SGs contig in this cmd */
1968 cp->Header.SGTotal = (u16) 1; /* total sgs in this cmd list */
a2dac136 1969 return 0;
edd16368
SC		 1970}
1971
1972static inline void hpsa_scsi_do_simple_cmd_core(struct ctlr_info *h,
1973 struct CommandList *c)
1974{
1975 DECLARE_COMPLETION_ONSTACK(wait);
1976
1977 c->waiting = &wait;
1978 enqueue_cmd_and_start_io(h, c);
1979 wait_for_completion(&wait);
1980}
1981
a0c12413
SC		 1982static void hpsa_scsi_do_simple_cmd_core_if_no_lockup(struct ctlr_info *h,
1983 struct CommandList *c)
1984{
1985 unsigned long flags;
1986
1987 /* If controller lockup detected, fake a hardware error. */
1988 spin_lock_irqsave(&h->lock, flags);
1989 if (unlikely(h->lockup_detected)) {
1990 spin_unlock_irqrestore(&h->lock, flags);
1991 c->err_info->CommandStatus = CMD_HARDWARE_ERR;
1992 } else {
1993 spin_unlock_irqrestore(&h->lock, flags);
1994 hpsa_scsi_do_simple_cmd_core(h, c);
1995 }
1996}
1997
9c2fc160 1998#define MAX_DRIVER_CMD_RETRIES 25
edd16368
SC		 1999static void hpsa_scsi_do_simple_cmd_with_retry(struct ctlr_info *h,
2000 struct CommandList *c, int data_direction)
2001{
9c2fc160 2002 int backoff_time = 10, retry_count = 0;
edd16368
SC		 2003
2004 do {
7630abd0 2005 memset(c->err_info, 0, sizeof(*c->err_info));
edd16368
SC		 2006 hpsa_scsi_do_simple_cmd_core(h, c);
2007 retry_count++;
9c2fc160
SC		 2008 if (retry_count > 3) {
2009 msleep(backoff_time);
2010 if (backoff_time < 1000)
2011 backoff_time *= 2;
2012 }
852af20a 2013 } while ((check_for_unit_attention(h, c) ||
9c2fc160
SC		 2014 check_for_busy(h, c)) &&
2015 retry_count <= MAX_DRIVER_CMD_RETRIES);
edd16368
SC		 2016 hpsa_pci_unmap(h->pdev, c, 1, data_direction);
2017}
2018
d1e8beac
SC		 2019static void hpsa_print_cmd(struct ctlr_info *h, char *txt,
2020 struct CommandList *c)
edd16368 2021{
d1e8beac
SC		 2022 const u8 *cdb = c->Request.CDB;
2023 const u8 *lun = c->Header.LUN.LunAddrBytes;
2024
2025 dev_warn(&h->pdev->dev, "%s: LUN:%02x%02x%02x%02x%02x%02x%02x%02x"
2026 " CDB:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\n",
2027 txt, lun[0], lun[1], lun[2], lun[3],
2028 lun[4], lun[5], lun[6], lun[7],
2029 cdb[0], cdb[1], cdb[2], cdb[3],
2030 cdb[4], cdb[5], cdb[6], cdb[7],
2031 cdb[8], cdb[9], cdb[10], cdb[11],
2032 cdb[12], cdb[13], cdb[14], cdb[15]);
2033}
2034
2035static void hpsa_scsi_interpret_error(struct ctlr_info *h,
2036 struct CommandList *cp)
2037{
2038 const struct ErrorInfo *ei = cp->err_info;
edd16368 2039 struct device *d = &cp->h->pdev->dev;
d1e8beac 2040 const u8 *sd = ei->SenseInfo;
edd16368 2041
edd16368
SC		 2042 switch (ei->CommandStatus) {
2043 case CMD_TARGET_STATUS:
d1e8beac
SC		 2044 hpsa_print_cmd(h, "SCSI status", cp);
2045 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION)
2046 dev_warn(d, "SCSI Status = 02, Sense key = %02x, ASC = %02x, ASCQ = %02x\n",
2047 sd[2] & 0x0f, sd[12], sd[13]);
2048 else
2049 dev_warn(d, "SCSI Status = %02x\n", ei->ScsiStatus);
edd16368
SC		 2050 if (ei->ScsiStatus == 0)
2051 dev_warn(d, "SCSI status is abnormally zero. "
2052 "(probably indicates selection timeout "
2053 "reported incorrectly due to a known "
2054 "firmware bug, circa July, 2001.)\n");
2055 break;
2056 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
edd16368
SC		 2057 break;
2058 case CMD_DATA_OVERRUN:
d1e8beac 2059 hpsa_print_cmd(h, "overrun condition", cp);
edd16368
SC		 2060 break;
2061 case CMD_INVALID: {
2062 /* controller unfortunately reports SCSI passthru's
2063 * to non-existent targets as invalid commands.
2064 */
d1e8beac
SC		 2065 hpsa_print_cmd(h, "invalid command", cp);
2066 dev_warn(d, "probably means device no longer present\n");
edd16368
SC		 2067 }
2068 break;
2069 case CMD_PROTOCOL_ERR:
d1e8beac 2070 hpsa_print_cmd(h, "protocol error", cp);
edd16368
SC		 2071 break;
2072 case CMD_HARDWARE_ERR:
d1e8beac 2073 hpsa_print_cmd(h, "hardware error", cp);
edd16368
SC		 2074 break;
2075 case CMD_CONNECTION_LOST:
d1e8beac 2076 hpsa_print_cmd(h, "connection lost", cp);
edd16368
SC		 2077 break;
2078 case CMD_ABORTED:
d1e8beac 2079 hpsa_print_cmd(h, "aborted", cp);
edd16368
SC		 2080 break;
2081 case CMD_ABORT_FAILED:
d1e8beac 2082 hpsa_print_cmd(h, "abort failed", cp);
edd16368
SC		 2083 break;
2084 case CMD_UNSOLICITED_ABORT:
d1e8beac 2085 hpsa_print_cmd(h, "unsolicited abort", cp);
edd16368
SC		 2086 break;
2087 case CMD_TIMEOUT:
d1e8beac 2088 hpsa_print_cmd(h, "timed out", cp);
edd16368 2089 break;
1d5e2ed0 2090 case CMD_UNABORTABLE:
d1e8beac 2091 hpsa_print_cmd(h, "unabortable", cp);
1d5e2ed0 2092 break;
edd16368 2093 default:
d1e8beac
SC		 2094 hpsa_print_cmd(h, "unknown status", cp);
2095 dev_warn(d, "Unknown command status %x\n",
edd16368
SC		 2096 ei->CommandStatus);
2097 }
2098}
2099
2100static int hpsa_scsi_do_inquiry(struct ctlr_info *h, unsigned char *scsi3addr,
b7bb24eb 2101 u16 page, unsigned char *buf,
edd16368
SC		 2102 unsigned char bufsize)
2103{
2104 int rc = IO_OK;
2105 struct CommandList *c;
2106 struct ErrorInfo *ei;
2107
2108 c = cmd_special_alloc(h);
2109
2110 if (c == NULL) { /* trouble... */
2111 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
ecd9aad4 2112 return -ENOMEM;
edd16368
SC		 2113 }
2114
a2dac136
SC		 2115 if (fill_cmd(c, HPSA_INQUIRY, h, buf, bufsize,
2116 page, scsi3addr, TYPE_CMD)) {
2117 rc = -1;
2118 goto out;
2119 }
edd16368
SC		 2120 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
2121 ei = c->err_info;
2122 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2123 hpsa_scsi_interpret_error(h, c);
edd16368
SC		 2124 rc = -1;
2125 }
a2dac136 2126out:
edd16368
SC		 2127 cmd_special_free(h, c);
2128 return rc;
2129}
2130
316b221a
SC		 2131static int hpsa_bmic_ctrl_mode_sense(struct ctlr_info *h,
2132 unsigned char *scsi3addr, unsigned char page,
2133 struct bmic_controller_parameters *buf, size_t bufsize)
2134{
2135 int rc = IO_OK;
2136 struct CommandList *c;
2137 struct ErrorInfo *ei;
2138
2139 c = cmd_special_alloc(h);
2140
2141 if (c == NULL) { /* trouble... */
2142 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
2143 return -ENOMEM;
2144 }
2145
2146 if (fill_cmd(c, BMIC_SENSE_CONTROLLER_PARAMETERS, h, buf, bufsize,
2147 page, scsi3addr, TYPE_CMD)) {
2148 rc = -1;
2149 goto out;
2150 }
2151 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
2152 ei = c->err_info;
2153 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
2154 hpsa_scsi_interpret_error(h, c);
2155 rc = -1;
2156 }
2157out:
2158 cmd_special_free(h, c);
2159 return rc;
2160 }
2161
bf711ac6
ST		 2162static int hpsa_send_reset(struct ctlr_info *h, unsigned char *scsi3addr,
2163 u8 reset_type)
edd16368
SC		 2164{
2165 int rc = IO_OK;
2166 struct CommandList *c;
2167 struct ErrorInfo *ei;
2168
2169 c = cmd_special_alloc(h);
2170
2171 if (c == NULL) { /* trouble... */
2172 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
e9ea04a6 2173 return -ENOMEM;
edd16368
SC		 2174 }
2175
a2dac136 2176 /* fill_cmd can't fail here, no data buffer to map. */
bf711ac6
ST		 2177 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
2178 scsi3addr, TYPE_MSG);
2179 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to LUN reset */
edd16368
SC		 2180 hpsa_scsi_do_simple_cmd_core(h, c);
2181 /* no unmap needed here because no data xfer. */
2182
2183 ei = c->err_info;
2184 if (ei->CommandStatus != 0) {
d1e8beac 2185 hpsa_scsi_interpret_error(h, c);
edd16368
SC		 2186 rc = -1;
2187 }
2188 cmd_special_free(h, c);
2189 return rc;
2190}
2191
2192static void hpsa_get_raid_level(struct ctlr_info *h,
2193 unsigned char *scsi3addr, unsigned char *raid_level)
2194{
2195 int rc;
2196 unsigned char *buf;
2197
2198 *raid_level = RAID_UNKNOWN;
2199 buf = kzalloc(64, GFP_KERNEL);
2200 if (!buf)
2201 return;
b7bb24eb 2202 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0xC1, buf, 64);
edd16368
SC		 2203 if (rc == 0)
2204 *raid_level = buf[8];
2205 if (*raid_level > RAID_UNKNOWN)
2206 *raid_level = RAID_UNKNOWN;
2207 kfree(buf);
2208 return;
2209}
2210
283b4a9b
SC		 2211#define HPSA_MAP_DEBUG
2212#ifdef HPSA_MAP_DEBUG
2213static void hpsa_debug_map_buff(struct ctlr_info *h, int rc,
2214 struct raid_map_data *map_buff)
2215{
2216 struct raid_map_disk_data *dd = &map_buff->data[0];
2217 int map, row, col;
2218 u16 map_cnt, row_cnt, disks_per_row;
2219
2220 if (rc != 0)
2221 return;
2222
2ba8bfc8
SC		 2223 /* Show details only if debugging has been activated. */
2224 if (h->raid_offload_debug < 2)
2225 return;
2226
283b4a9b
SC		 2227 dev_info(&h->pdev->dev, "structure_size = %u\n",
2228 le32_to_cpu(map_buff->structure_size));
2229 dev_info(&h->pdev->dev, "volume_blk_size = %u\n",
2230 le32_to_cpu(map_buff->volume_blk_size));
2231 dev_info(&h->pdev->dev, "volume_blk_cnt = 0x%llx\n",
2232 le64_to_cpu(map_buff->volume_blk_cnt));
2233 dev_info(&h->pdev->dev, "physicalBlockShift = %u\n",
2234 map_buff->phys_blk_shift);
2235 dev_info(&h->pdev->dev, "parity_rotation_shift = %u\n",
2236 map_buff->parity_rotation_shift);
2237 dev_info(&h->pdev->dev, "strip_size = %u\n",
2238 le16_to_cpu(map_buff->strip_size));
2239 dev_info(&h->pdev->dev, "disk_starting_blk = 0x%llx\n",
2240 le64_to_cpu(map_buff->disk_starting_blk));
2241 dev_info(&h->pdev->dev, "disk_blk_cnt = 0x%llx\n",
2242 le64_to_cpu(map_buff->disk_blk_cnt));
2243 dev_info(&h->pdev->dev, "data_disks_per_row = %u\n",
2244 le16_to_cpu(map_buff->data_disks_per_row));
2245 dev_info(&h->pdev->dev, "metadata_disks_per_row = %u\n",
2246 le16_to_cpu(map_buff->metadata_disks_per_row));
2247 dev_info(&h->pdev->dev, "row_cnt = %u\n",
2248 le16_to_cpu(map_buff->row_cnt));
2249 dev_info(&h->pdev->dev, "layout_map_count = %u\n",
2250 le16_to_cpu(map_buff->layout_map_count));
dd0e19f3
ST		 2251 dev_info(&h->pdev->dev, "flags = %u\n",
2252 le16_to_cpu(map_buff->flags));
2253 if (map_buff->flags & RAID_MAP_FLAG_ENCRYPT_ON)
2254 dev_info(&h->pdev->dev, "encrypytion = ON\n");
2255 else
2256 dev_info(&h->pdev->dev, "encrypytion = OFF\n");
2257 dev_info(&h->pdev->dev, "dekindex = %u\n",
2258 le16_to_cpu(map_buff->dekindex));
283b4a9b
SC		 2259
2260 map_cnt = le16_to_cpu(map_buff->layout_map_count);
2261 for (map = 0; map < map_cnt; map++) {
2262 dev_info(&h->pdev->dev, "Map%u:\n", map);
2263 row_cnt = le16_to_cpu(map_buff->row_cnt);
2264 for (row = 0; row < row_cnt; row++) {
2265 dev_info(&h->pdev->dev, " Row%u:\n", row);
2266 disks_per_row =
2267 le16_to_cpu(map_buff->data_disks_per_row);
2268 for (col = 0; col < disks_per_row; col++, dd++)
2269 dev_info(&h->pdev->dev,
2270 " D%02u: h=0x%04x xor=%u,%u\n",
2271 col, dd->ioaccel_handle,
2272 dd->xor_mult[0], dd->xor_mult[1]);
2273 disks_per_row =
2274 le16_to_cpu(map_buff->metadata_disks_per_row);
2275 for (col = 0; col < disks_per_row; col++, dd++)
2276 dev_info(&h->pdev->dev,
2277 " M%02u: h=0x%04x xor=%u,%u\n",
2278 col, dd->ioaccel_handle,
2279 dd->xor_mult[0], dd->xor_mult[1]);
2280 }
2281 }
2282}
2283#else
2284static void hpsa_debug_map_buff(__attribute__((unused)) struct ctlr_info *h,
2285 __attribute__((unused)) int rc,
2286 __attribute__((unused)) struct raid_map_data *map_buff)
2287{
2288}
2289#endif
2290
2291static int hpsa_get_raid_map(struct ctlr_info *h,
2292 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
2293{
2294 int rc = 0;
2295 struct CommandList *c;
2296 struct ErrorInfo *ei;
2297
2298 c = cmd_special_alloc(h);
2299 if (c == NULL) {
2300 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
2301 return -ENOMEM;
2302 }
2303 if (fill_cmd(c, HPSA_GET_RAID_MAP, h, &this_device->raid_map,
2304 sizeof(this_device->raid_map), 0,
2305 scsi3addr, TYPE_CMD)) {
2306 dev_warn(&h->pdev->dev, "Out of memory in hpsa_get_raid_map()\n");
2307 cmd_special_free(h, c);
2308 return -ENOMEM;
2309 }
2310 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
2311 ei = c->err_info;
2312 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2313 hpsa_scsi_interpret_error(h, c);
283b4a9b
SC		 2314 cmd_special_free(h, c);
2315 return -1;
2316 }
2317 cmd_special_free(h, c);
2318
2319 /* @todo in the future, dynamically allocate RAID map memory */
2320 if (le32_to_cpu(this_device->raid_map.structure_size) >
2321 sizeof(this_device->raid_map)) {
2322 dev_warn(&h->pdev->dev, "RAID map size is too large!\n");
2323 rc = -1;
2324 }
2325 hpsa_debug_map_buff(h, rc, &this_device->raid_map);
2326 return rc;
2327}
2328
1b70150a
SC		 2329static int hpsa_vpd_page_supported(struct ctlr_info *h,
2330 unsigned char scsi3addr[], u8 page)
2331{
2332 int rc;
2333 int i;
2334 int pages;
2335 unsigned char *buf, bufsize;
2336
2337 buf = kzalloc(256, GFP_KERNEL);
2338 if (!buf)
2339 return 0;
2340
2341 /* Get the size of the page list first */
2342 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
2343 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
2344 buf, HPSA_VPD_HEADER_SZ);
2345 if (rc != 0)
2346 goto exit_unsupported;
2347 pages = buf[3];
2348 if ((pages + HPSA_VPD_HEADER_SZ) <= 255)
2349 bufsize = pages + HPSA_VPD_HEADER_SZ;
2350 else
2351 bufsize = 255;
2352
2353 /* Get the whole VPD page list */
2354 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
2355 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
2356 buf, bufsize);
2357 if (rc != 0)
2358 goto exit_unsupported;
2359
2360 pages = buf[3];
2361 for (i = 1; i <= pages; i++)
2362 if (buf[3 + i] == page)
2363 goto exit_supported;
2364exit_unsupported:
2365 kfree(buf);
2366 return 0;
2367exit_supported:
2368 kfree(buf);
2369 return 1;
2370}
2371
283b4a9b
SC		 2372static void hpsa_get_ioaccel_status(struct ctlr_info *h,
2373 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
2374{
2375 int rc;
2376 unsigned char *buf;
2377 u8 ioaccel_status;
2378
2379 this_device->offload_config = 0;
2380 this_device->offload_enabled = 0;
2381
2382 buf = kzalloc(64, GFP_KERNEL);
2383 if (!buf)
2384 return;
1b70150a
SC		 2385 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_IOACCEL_STATUS))
2386 goto out;
283b4a9b 2387 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
b7bb24eb 2388 VPD_PAGE | HPSA_VPD_LV_IOACCEL_STATUS, buf, 64);
283b4a9b
SC		 2389 if (rc != 0)
2390 goto out;
2391
2392#define IOACCEL_STATUS_BYTE 4
2393#define OFFLOAD_CONFIGURED_BIT 0x01
2394#define OFFLOAD_ENABLED_BIT 0x02
2395 ioaccel_status = buf[IOACCEL_STATUS_BYTE];
2396 this_device->offload_config =
2397 !!(ioaccel_status & OFFLOAD_CONFIGURED_BIT);
2398 if (this_device->offload_config) {
2399 this_device->offload_enabled =
2400 !!(ioaccel_status & OFFLOAD_ENABLED_BIT);
2401 if (hpsa_get_raid_map(h, scsi3addr, this_device))
2402 this_device->offload_enabled = 0;
2403 }
2404out:
2405 kfree(buf);
2406 return;
2407}
2408
edd16368
SC		 2409/* Get the device id from inquiry page 0x83 */
2410static int hpsa_get_device_id(struct ctlr_info *h, unsigned char *scsi3addr,
2411 unsigned char *device_id, int buflen)
2412{
2413 int rc;
2414 unsigned char *buf;
2415
2416 if (buflen > 16)
2417 buflen = 16;
2418 buf = kzalloc(64, GFP_KERNEL);
2419 if (!buf)
2420 return -1;
b7bb24eb 2421 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0x83, buf, 64);
edd16368
SC		 2422 if (rc == 0)
2423 memcpy(device_id, &buf[8], buflen);
2424 kfree(buf);
2425 return rc != 0;
2426}
2427
2428static int hpsa_scsi_do_report_luns(struct ctlr_info *h, int logical,
2429 struct ReportLUNdata *buf, int bufsize,
2430 int extended_response)
2431{
2432 int rc = IO_OK;
2433 struct CommandList *c;
2434 unsigned char scsi3addr[8];
2435 struct ErrorInfo *ei;
2436
2437 c = cmd_special_alloc(h);
2438 if (c == NULL) { /* trouble... */
2439 dev_err(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
2440 return -1;
2441 }
e89c0ae7
SC		 2442 /* address the controller */
2443 memset(scsi3addr, 0, sizeof(scsi3addr));
a2dac136
SC		 2444 if (fill_cmd(c, logical ? HPSA_REPORT_LOG : HPSA_REPORT_PHYS, h,
2445 buf, bufsize, 0, scsi3addr, TYPE_CMD)) {
2446 rc = -1;
2447 goto out;
2448 }
edd16368
SC		 2449 if (extended_response)
2450 c->Request.CDB[1] = extended_response;
2451 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
2452 ei = c->err_info;
2453 if (ei->CommandStatus != 0 &&
2454 ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2455 hpsa_scsi_interpret_error(h, c);
edd16368 2456 rc = -1;
283b4a9b
SC		 2457 } else {
2458 if (buf->extended_response_flag != extended_response) {
2459 dev_err(&h->pdev->dev,
2460 "report luns requested format %u, got %u\n",
2461 extended_response,
2462 buf->extended_response_flag);
2463 rc = -1;
2464 }
edd16368 2465 }
a2dac136 2466out:
edd16368
SC		 2467 cmd_special_free(h, c);
2468 return rc;
2469}
2470
2471static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h,
2472 struct ReportLUNdata *buf,
2473 int bufsize, int extended_response)
2474{
2475 return hpsa_scsi_do_report_luns(h, 0, buf, bufsize, extended_response);
2476}
2477
2478static inline int hpsa_scsi_do_report_log_luns(struct ctlr_info *h,
2479 struct ReportLUNdata *buf, int bufsize)
2480{
2481 return hpsa_scsi_do_report_luns(h, 1, buf, bufsize, 0);
2482}
2483
2484static inline void hpsa_set_bus_target_lun(struct hpsa_scsi_dev_t *device,
2485 int bus, int target, int lun)
2486{
2487 device->bus = bus;
2488 device->target = target;
2489 device->lun = lun;
2490}
2491
9846590e
SC		 2492/* Use VPD inquiry to get details of volume status */
2493static int hpsa_get_volume_status(struct ctlr_info *h,
2494 unsigned char scsi3addr[])
2495{
2496 int rc;
2497 int status;
2498 int size;
2499 unsigned char *buf;
2500
2501 buf = kzalloc(64, GFP_KERNEL);
2502 if (!buf)
2503 return HPSA_VPD_LV_STATUS_UNSUPPORTED;
2504
2505 /* Does controller have VPD for logical volume status? */
2506 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_STATUS)) {
2507 dev_warn(&h->pdev->dev, "Logical volume status VPD page is unsupported.\n");
2508 goto exit_failed;
2509 }
2510
2511 /* Get the size of the VPD return buffer */
2512 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
2513 buf, HPSA_VPD_HEADER_SZ);
2514 if (rc != 0) {
2515 dev_warn(&h->pdev->dev, "Logical volume status VPD inquiry failed.\n");
2516 goto exit_failed;
2517 }
2518 size = buf[3];
2519
2520 /* Now get the whole VPD buffer */
2521 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
2522 buf, size + HPSA_VPD_HEADER_SZ);
2523 if (rc != 0) {
2524 dev_warn(&h->pdev->dev, "Logical volume status VPD inquiry failed.\n");
2525 goto exit_failed;
2526 }
2527 status = buf[4]; /* status byte */
2528
2529 kfree(buf);
2530 return status;
2531exit_failed:
2532 kfree(buf);
2533 return HPSA_VPD_LV_STATUS_UNSUPPORTED;
2534}
2535
2536/* Determine offline status of a volume.
2537 * Return either:
2538 * 0 (not offline)
2539 * -1 (offline for unknown reasons)
2540 * # (integer code indicating one of several NOT READY states
2541 * describing why a volume is to be kept offline)
2542 */
2543static unsigned char hpsa_volume_offline(struct ctlr_info *h,
2544 unsigned char scsi3addr[])
2545{
2546 struct CommandList *c;
2547 unsigned char *sense, sense_key, asc, ascq;
2548 int ldstat = 0;
2549 u16 cmd_status;
2550 u8 scsi_status;
2551#define ASC_LUN_NOT_READY 0x04
2552#define ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS 0x04
2553#define ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ 0x02
2554
2555 c = cmd_alloc(h);
2556 if (!c)
2557 return 0;
2558 (void) fill_cmd(c, TEST_UNIT_READY, h, NULL, 0, 0, scsi3addr, TYPE_CMD);
2559 hpsa_scsi_do_simple_cmd_core(h, c);
2560 sense = c->err_info->SenseInfo;
2561 sense_key = sense[2];
2562 asc = sense[12];
2563 ascq = sense[13];
2564 cmd_status = c->err_info->CommandStatus;
2565 scsi_status = c->err_info->ScsiStatus;
2566 cmd_free(h, c);
2567 /* Is the volume 'not ready'? */
2568 if (cmd_status != CMD_TARGET_STATUS ||
2569 scsi_status != SAM_STAT_CHECK_CONDITION ||
2570 sense_key != NOT_READY ||
2571 asc != ASC_LUN_NOT_READY) {
2572 return 0;
2573 }
2574
2575 /* Determine the reason for not ready state */
2576 ldstat = hpsa_get_volume_status(h, scsi3addr);
2577
2578 /* Keep volume offline in certain cases: */
2579 switch (ldstat) {
2580 case HPSA_LV_UNDERGOING_ERASE:
2581 case HPSA_LV_UNDERGOING_RPI:
2582 case HPSA_LV_PENDING_RPI:
2583 case HPSA_LV_ENCRYPTED_NO_KEY:
2584 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
2585 case HPSA_LV_UNDERGOING_ENCRYPTION:
2586 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
2587 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
2588 return ldstat;
2589 case HPSA_VPD_LV_STATUS_UNSUPPORTED:
2590 /* If VPD status page isn't available,
2591 * use ASC/ASCQ to determine state
2592 */
2593 if ((ascq == ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS) ||
2594 (ascq == ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ))
2595 return ldstat;
2596 break;
2597 default:
2598 break;
2599 }
2600 return 0;
2601}
2602
edd16368 2603static int hpsa_update_device_info(struct ctlr_info *h,
0b0e1d6c
SC		 2604 unsigned char scsi3addr[], struct hpsa_scsi_dev_t *this_device,
2605 unsigned char *is_OBDR_device)
edd16368 2606{
0b0e1d6c
SC		 2607
2608#define OBDR_SIG_OFFSET 43
2609#define OBDR_TAPE_SIG "$DR-10"
2610#define OBDR_SIG_LEN (sizeof(OBDR_TAPE_SIG) - 1)
2611#define OBDR_TAPE_INQ_SIZE (OBDR_SIG_OFFSET + OBDR_SIG_LEN)
2612
ea6d3bc3 2613 unsigned char *inq_buff;
0b0e1d6c 2614 unsigned char *obdr_sig;
edd16368 2615
ea6d3bc3 2616 inq_buff = kzalloc(OBDR_TAPE_INQ_SIZE, GFP_KERNEL);
edd16368
SC		 2617 if (!inq_buff)
2618 goto bail_out;
2619
edd16368
SC		 2620 /* Do an inquiry to the device to see what it is. */
2621 if (hpsa_scsi_do_inquiry(h, scsi3addr, 0, inq_buff,
2622 (unsigned char) OBDR_TAPE_INQ_SIZE) != 0) {
2623 /* Inquiry failed (msg printed already) */
2624 dev_err(&h->pdev->dev,
2625 "hpsa_update_device_info: inquiry failed\n");
2626 goto bail_out;
2627 }
2628
edd16368
SC		 2629 this_device->devtype = (inq_buff[0] & 0x1f);
2630 memcpy(this_device->scsi3addr, scsi3addr, 8);
2631 memcpy(this_device->vendor, &inq_buff[8],
2632 sizeof(this_device->vendor));
2633 memcpy(this_device->model, &inq_buff[16],
2634 sizeof(this_device->model));
edd16368
SC		 2635 memset(this_device->device_id, 0,
2636 sizeof(this_device->device_id));
2637 hpsa_get_device_id(h, scsi3addr, this_device->device_id,
2638 sizeof(this_device->device_id));
2639
2640 if (this_device->devtype == TYPE_DISK &&
283b4a9b 2641 is_logical_dev_addr_mode(scsi3addr)) {
edd16368 2642 hpsa_get_raid_level(h, scsi3addr, &this_device->raid_level);
283b4a9b
SC		 2643 if (h->fw_support & MISC_FW_RAID_OFFLOAD_BASIC)
2644 hpsa_get_ioaccel_status(h, scsi3addr, this_device);
9846590e
SC		 2645 this_device->volume_offline =
2646 hpsa_volume_offline(h, scsi3addr);
283b4a9b 2647 } else {
edd16368 2648 this_device->raid_level = RAID_UNKNOWN;
283b4a9b
SC		 2649 this_device->offload_config = 0;
2650 this_device->offload_enabled = 0;
9846590e 2651 this_device->volume_offline = 0;
283b4a9b 2652 }
edd16368 2653
0b0e1d6c
SC		 2654 if (is_OBDR_device) {
2655 /* See if this is a One-Button-Disaster-Recovery device
2656 * by looking for "$DR-10" at offset 43 in inquiry data.
2657 */
2658 obdr_sig = &inq_buff[OBDR_SIG_OFFSET];
2659 *is_OBDR_device = (this_device->devtype == TYPE_ROM &&
2660 strncmp(obdr_sig, OBDR_TAPE_SIG,
2661 OBDR_SIG_LEN) == 0);
2662 }
2663
edd16368
SC		 2664 kfree(inq_buff);
2665 return 0;
2666
2667bail_out:
2668 kfree(inq_buff);
2669 return 1;
2670}
2671
4f4eb9f1 2672static unsigned char *ext_target_model[] = {
edd16368
SC		 2673 "MSA2012",
2674 "MSA2024",
2675 "MSA2312",
2676 "MSA2324",
fda38518 2677 "P2000 G3 SAS",
e06c8e5c 2678 "MSA 2040 SAS",
edd16368
SC		 2679 NULL,
2680};
2681
4f4eb9f1 2682static int is_ext_target(struct ctlr_info *h, struct hpsa_scsi_dev_t *device)
edd16368
SC		 2683{
2684 int i;
2685
4f4eb9f1
ST		 2686 for (i = 0; ext_target_model[i]; i++)
2687 if (strncmp(device->model, ext_target_model[i],
2688 strlen(ext_target_model[i])) == 0)
edd16368
SC		 2689 return 1;
2690 return 0;
2691}
2692
2693/* Helper function to assign bus, target, lun mapping of devices.
4f4eb9f1 2694 * Puts non-external target logical volumes on bus 0, external target logical
edd16368
SC		 2695 * volumes on bus 1, physical devices on bus 2. and the hba on bus 3.
2696 * Logical drive target and lun are assigned at this time, but
2697 * physical device lun and target assignment are deferred (assigned
2698 * in hpsa_find_target_lun, called by hpsa_scsi_add_entry.)
2699 */
2700static void figure_bus_target_lun(struct ctlr_info *h,
1f310bde 2701 u8 *lunaddrbytes, struct hpsa_scsi_dev_t *device)
edd16368 2702{
1f310bde
SC		 2703 u32 lunid = le32_to_cpu(*((__le32 *) lunaddrbytes));
2704
2705 if (!is_logical_dev_addr_mode(lunaddrbytes)) {
2706 /* physical device, target and lun filled in later */
edd16368 2707 if (is_hba_lunid(lunaddrbytes))
1f310bde 2708 hpsa_set_bus_target_lun(device, 3, 0, lunid & 0x3fff);
edd16368 2709 else
1f310bde
SC		 2710 /* defer target, lun assignment for physical devices */
2711 hpsa_set_bus_target_lun(device, 2, -1, -1);
2712 return;
2713 }
2714 /* It's a logical device */
4f4eb9f1
ST		 2715 if (is_ext_target(h, device)) {
2716 /* external target way, put logicals on bus 1
1f310bde
SC		 2717 * and match target/lun numbers box
2718 * reports, other smart array, bus 0, target 0, match lunid
2719 */
2720 hpsa_set_bus_target_lun(device,
2721 1, (lunid >> 16) & 0x3fff, lunid & 0x00ff);
2722 return;
edd16368 2723 }
1f310bde 2724 hpsa_set_bus_target_lun(device, 0, 0, lunid & 0x3fff);
edd16368
SC		 2725}
2726
2727/*
2728 * If there is no lun 0 on a target, linux won't find any devices.
4f4eb9f1 2729 * For the external targets (arrays), we have to manually detect the enclosure
edd16368
SC		 2730 * which is at lun zero, as CCISS_REPORT_PHYSICAL_LUNS doesn't report
2731 * it for some reason. *tmpdevice is the target we're adding,
2732 * this_device is a pointer into the current element of currentsd[]
2733 * that we're building up in update_scsi_devices(), below.
2734 * lunzerobits is a bitmap that tracks which targets already have a
2735 * lun 0 assigned.
2736 * Returns 1 if an enclosure was added, 0 if not.
2737 */
4f4eb9f1 2738static int add_ext_target_dev(struct ctlr_info *h,
edd16368 2739 struct hpsa_scsi_dev_t *tmpdevice,
01a02ffc 2740 struct hpsa_scsi_dev_t *this_device, u8 *lunaddrbytes,
4f4eb9f1 2741 unsigned long lunzerobits[], int *n_ext_target_devs)
edd16368
SC		 2742{
2743 unsigned char scsi3addr[8];
2744
1f310bde 2745 if (test_bit(tmpdevice->target, lunzerobits))
edd16368
SC		 2746 return 0; /* There is already a lun 0 on this target. */
2747
2748 if (!is_logical_dev_addr_mode(lunaddrbytes))
2749 return 0; /* It's the logical targets that may lack lun 0. */
2750
4f4eb9f1
ST		 2751 if (!is_ext_target(h, tmpdevice))
2752 return 0; /* Only external target devices have this problem. */
edd16368 2753
1f310bde 2754 if (tmpdevice->lun == 0) /* if lun is 0, then we have a lun 0. */
edd16368
SC		 2755 return 0;
2756
c4f8a299 2757 memset(scsi3addr, 0, 8);
1f310bde 2758 scsi3addr[3] = tmpdevice->target;
edd16368
SC		 2759 if (is_hba_lunid(scsi3addr))
2760 return 0; /* Don't add the RAID controller here. */
2761
339b2b14
SC		 2762 if (is_scsi_rev_5(h))
2763 return 0; /* p1210m doesn't need to do this. */
2764
4f4eb9f1 2765 if (*n_ext_target_devs >= MAX_EXT_TARGETS) {
aca4a520
ST		 2766 dev_warn(&h->pdev->dev, "Maximum number of external "
2767 "target devices exceeded. Check your hardware "
edd16368
SC		 2768 "configuration.");
2769 return 0;
2770 }
2771
0b0e1d6c 2772 if (hpsa_update_device_info(h, scsi3addr, this_device, NULL))
edd16368 2773 return 0;
4f4eb9f1 2774 (*n_ext_target_devs)++;
1f310bde
SC		 2775 hpsa_set_bus_target_lun(this_device,
2776 tmpdevice->bus, tmpdevice->target, 0);
2777 set_bit(tmpdevice->target, lunzerobits);
edd16368
SC		 2778 return 1;
2779}
2780
54b6e9e9
ST		 2781/*
2782 * Get address of physical disk used for an ioaccel2 mode command:
2783 * 1. Extract ioaccel2 handle from the command.
2784 * 2. Find a matching ioaccel2 handle from list of physical disks.
2785 * 3. Return:
2786 * 1 and set scsi3addr to address of matching physical
2787 * 0 if no matching physical disk was found.
2788 */
2789static int hpsa_get_pdisk_of_ioaccel2(struct ctlr_info *h,
2790 struct CommandList *ioaccel2_cmd_to_abort, unsigned char *scsi3addr)
2791{
2792 struct ReportExtendedLUNdata *physicals = NULL;
2793 int responsesize = 24; /* size of physical extended response */
2794 int extended = 2; /* flag forces reporting 'other dev info'. */
2795 int reportsize = sizeof(*physicals) + HPSA_MAX_PHYS_LUN * responsesize;
2796 u32 nphysicals = 0; /* number of reported physical devs */
2797 int found = 0; /* found match (1) or not (0) */
2798 u32 find; /* handle we need to match */
2799 int i;
2800 struct scsi_cmnd *scmd; /* scsi command within request being aborted */
2801 struct hpsa_scsi_dev_t *d; /* device of request being aborted */
2802 struct io_accel2_cmd *c2a; /* ioaccel2 command to abort */
2803 u32 it_nexus; /* 4 byte device handle for the ioaccel2 cmd */
2804 u32 scsi_nexus; /* 4 byte device handle for the ioaccel2 cmd */
2805
2806 if (ioaccel2_cmd_to_abort->cmd_type != CMD_IOACCEL2)
2807 return 0; /* no match */
2808
2809 /* point to the ioaccel2 device handle */
2810 c2a = &h->ioaccel2_cmd_pool[ioaccel2_cmd_to_abort->cmdindex];
2811 if (c2a == NULL)
2812 return 0; /* no match */
2813
2814 scmd = (struct scsi_cmnd *) ioaccel2_cmd_to_abort->scsi_cmd;
2815 if (scmd == NULL)
2816 return 0; /* no match */
2817
2818 d = scmd->device->hostdata;
2819 if (d == NULL)
2820 return 0; /* no match */
2821
2822 it_nexus = cpu_to_le32((u32) d->ioaccel_handle);
2823 scsi_nexus = cpu_to_le32((u32) c2a->scsi_nexus);
2824 find = c2a->scsi_nexus;
2825
2ba8bfc8
SC		 2826 if (h->raid_offload_debug > 0)
2827 dev_info(&h->pdev->dev,
2828 "%s: scsi_nexus:0x%08x device id: 0x%02x%02x%02x%02x %02x%02x%02x%02x %02x%02x%02x%02x %02x%02x%02x%02x\n",
2829 __func__, scsi_nexus,
2830 d->device_id[0], d->device_id[1], d->device_id[2],
2831 d->device_id[3], d->device_id[4], d->device_id[5],
2832 d->device_id[6], d->device_id[7], d->device_id[8],
2833 d->device_id[9], d->device_id[10], d->device_id[11],
2834 d->device_id[12], d->device_id[13], d->device_id[14],
2835 d->device_id[15]);
2836
54b6e9e9
ST		 2837 /* Get the list of physical devices */
2838 physicals = kzalloc(reportsize, GFP_KERNEL);
3b51a7a3
JH		 2839 if (physicals == NULL)
2840 return 0;
54b6e9e9
ST		 2841 if (hpsa_scsi_do_report_phys_luns(h, (struct ReportLUNdata *) physicals,
2842 reportsize, extended)) {
2843 dev_err(&h->pdev->dev,
2844 "Can't lookup %s device handle: report physical LUNs failed.\n",
2845 "HP SSD Smart Path");
2846 kfree(physicals);
2847 return 0;
2848 }
2849 nphysicals = be32_to_cpu(*((__be32 *)physicals->LUNListLength)) /
2850 responsesize;
2851
2852
2853 /* find ioaccel2 handle in list of physicals: */
2854 for (i = 0; i < nphysicals; i++) {
2855 /* handle is in bytes 28-31 of each lun */
2856 if (memcmp(&((struct ReportExtendedLUNdata *)
2857 physicals)->LUN[i][20], &find, 4) != 0) {
2858 continue; /* didn't match */
2859 }
2860 found = 1;
2861 memcpy(scsi3addr, &((struct ReportExtendedLUNdata *)
2862 physicals)->LUN[i][0], 8);
2ba8bfc8
SC		 2863 if (h->raid_offload_debug > 0)
2864 dev_info(&h->pdev->dev,
2865 "%s: Searched h=0x%08x, Found h=0x%08x, scsiaddr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
2866 __func__, find,
2867 ((struct ReportExtendedLUNdata *)
2868 physicals)->LUN[i][20],
2869 scsi3addr[0], scsi3addr[1], scsi3addr[2],
2870 scsi3addr[3], scsi3addr[4], scsi3addr[5],
2871 scsi3addr[6], scsi3addr[7]);
54b6e9e9
ST		 2872 break; /* found it */
2873 }
2874
2875 kfree(physicals);
2876 if (found)
2877 return 1;
2878 else
2879 return 0;
2880
2881}
edd16368
SC		 2882/*
2883 * Do CISS_REPORT_PHYS and CISS_REPORT_LOG. Data is returned in physdev,
2884 * logdev. The number of luns in physdev and logdev are returned in
2885 * *nphysicals and *nlogicals, respectively.
2886 * Returns 0 on success, -1 otherwise.
2887 */
2888static int hpsa_gather_lun_info(struct ctlr_info *h,
2889 int reportlunsize,
283b4a9b 2890 struct ReportLUNdata *physdev, u32 *nphysicals, int *physical_mode,
01a02ffc 2891 struct ReportLUNdata *logdev, u32 *nlogicals)
edd16368 2892{
283b4a9b
SC		 2893 int physical_entry_size = 8;
2894
2895 *physical_mode = 0;
2896
2897 /* For I/O accelerator mode we need to read physical device handles */
317d4adf
MM		 2898 if (h->transMethod & CFGTBL_Trans_io_accel1 ||
2899 h->transMethod & CFGTBL_Trans_io_accel2) {
283b4a9b
SC		 2900 *physical_mode = HPSA_REPORT_PHYS_EXTENDED;
2901 physical_entry_size = 24;
2902 }
a93aa1fe 2903 if (hpsa_scsi_do_report_phys_luns(h, physdev, reportlunsize,
283b4a9b 2904 *physical_mode)) {
edd16368
SC		 2905 dev_err(&h->pdev->dev, "report physical LUNs failed.\n");
2906 return -1;
2907 }
283b4a9b
SC		 2908 *nphysicals = be32_to_cpu(*((__be32 *)physdev->LUNListLength)) /
2909 physical_entry_size;
edd16368
SC		 2910 if (*nphysicals > HPSA_MAX_PHYS_LUN) {
2911 dev_warn(&h->pdev->dev, "maximum physical LUNs (%d) exceeded."
2912 " %d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
2913 *nphysicals - HPSA_MAX_PHYS_LUN);
2914 *nphysicals = HPSA_MAX_PHYS_LUN;
2915 }
2916 if (hpsa_scsi_do_report_log_luns(h, logdev, reportlunsize)) {
2917 dev_err(&h->pdev->dev, "report logical LUNs failed.\n");
2918 return -1;
2919 }
6df1e954 2920 *nlogicals = be32_to_cpu(*((__be32 *) logdev->LUNListLength)) / 8;
edd16368
SC		 2921 /* Reject Logicals in excess of our max capability. */
2922 if (*nlogicals > HPSA_MAX_LUN) {
2923 dev_warn(&h->pdev->dev,
2924 "maximum logical LUNs (%d) exceeded. "
2925 "%d LUNs ignored.\n", HPSA_MAX_LUN,
2926 *nlogicals - HPSA_MAX_LUN);
2927 *nlogicals = HPSA_MAX_LUN;
2928 }
2929 if (*nlogicals + *nphysicals > HPSA_MAX_PHYS_LUN) {
2930 dev_warn(&h->pdev->dev,
2931 "maximum logical + physical LUNs (%d) exceeded. "
2932 "%d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
2933 *nphysicals + *nlogicals - HPSA_MAX_PHYS_LUN);
2934 *nlogicals = HPSA_MAX_PHYS_LUN - *nphysicals;
2935 }
2936 return 0;
2937}
2938
339b2b14 2939u8 *figure_lunaddrbytes(struct ctlr_info *h, int raid_ctlr_position, int i,
a93aa1fe
MG		 2940 int nphysicals, int nlogicals,
2941 struct ReportExtendedLUNdata *physdev_list,
339b2b14
SC		 2942 struct ReportLUNdata *logdev_list)
2943{
2944 /* Helper function, figure out where the LUN ID info is coming from
2945 * given index i, lists of physical and logical devices, where in
2946 * the list the raid controller is supposed to appear (first or last)
2947 */
2948
2949 int logicals_start = nphysicals + (raid_ctlr_position == 0);
2950 int last_device = nphysicals + nlogicals + (raid_ctlr_position == 0);
2951
2952 if (i == raid_ctlr_position)
2953 return RAID_CTLR_LUNID;
2954
2955 if (i < logicals_start)
2956 return &physdev_list->LUN[i - (raid_ctlr_position == 0)][0];
2957
2958 if (i < last_device)
2959 return &logdev_list->LUN[i - nphysicals -
2960 (raid_ctlr_position == 0)][0];
2961 BUG();
2962 return NULL;
2963}
2964
316b221a
SC		 2965static int hpsa_hba_mode_enabled(struct ctlr_info *h)
2966{
2967 int rc;
2968 struct bmic_controller_parameters *ctlr_params;
2969 ctlr_params = kzalloc(sizeof(struct bmic_controller_parameters),
2970 GFP_KERNEL);
2971
2972 if (!ctlr_params)
2973 return 0;
2974 rc = hpsa_bmic_ctrl_mode_sense(h, RAID_CTLR_LUNID, 0, ctlr_params,
2975 sizeof(struct bmic_controller_parameters));
2976 if (rc != 0) {
2977 kfree(ctlr_params);
2978 return 0;
2979 }
2980 return ctlr_params->nvram_flags & (1 << 3) ? 1 : 0;
2981}
2982
edd16368
SC		 2983static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno)
2984{
2985 /* the idea here is we could get notified
2986 * that some devices have changed, so we do a report
2987 * physical luns and report logical luns cmd, and adjust
2988 * our list of devices accordingly.
2989 *
2990 * The scsi3addr's of devices won't change so long as the
2991 * adapter is not reset. That means we can rescan and
2992 * tell which devices we already know about, vs. new
2993 * devices, vs. disappearing devices.
2994 */
a93aa1fe 2995 struct ReportExtendedLUNdata *physdev_list = NULL;
edd16368 2996 struct ReportLUNdata *logdev_list = NULL;
01a02ffc
SC		 2997 u32 nphysicals = 0;
2998 u32 nlogicals = 0;
283b4a9b 2999 int physical_mode = 0;
01a02ffc 3000 u32 ndev_allocated = 0;
edd16368
SC		 3001 struct hpsa_scsi_dev_t **currentsd, *this_device, *tmpdevice;
3002 int ncurrent = 0;
283b4a9b 3003 int reportlunsize = sizeof(*physdev_list) + HPSA_MAX_PHYS_LUN * 24;
4f4eb9f1 3004 int i, n_ext_target_devs, ndevs_to_allocate;
339b2b14 3005 int raid_ctlr_position;
316b221a 3006 u8 rescan_hba_mode;
aca4a520 3007 DECLARE_BITMAP(lunzerobits, MAX_EXT_TARGETS);
edd16368 3008
cfe5badc 3009 currentsd = kzalloc(sizeof(*currentsd) * HPSA_MAX_DEVICES, GFP_KERNEL);
edd16368
SC		 3010 physdev_list = kzalloc(reportlunsize, GFP_KERNEL);
3011 logdev_list = kzalloc(reportlunsize, GFP_KERNEL);
edd16368
SC		 3012 tmpdevice = kzalloc(sizeof(*tmpdevice), GFP_KERNEL);
3013
0b0e1d6c 3014 if (!currentsd || !physdev_list || !logdev_list || !tmpdevice) {
edd16368
SC		 3015 dev_err(&h->pdev->dev, "out of memory\n");
3016 goto out;
3017 }
3018 memset(lunzerobits, 0, sizeof(lunzerobits));
3019
316b221a
SC		 3020 rescan_hba_mode = hpsa_hba_mode_enabled(h);
3021
3022 if (!h->hba_mode_enabled && rescan_hba_mode)
3023 dev_warn(&h->pdev->dev, "HBA mode enabled\n");
3024 else if (h->hba_mode_enabled && !rescan_hba_mode)
3025 dev_warn(&h->pdev->dev, "HBA mode disabled\n");
3026
3027 h->hba_mode_enabled = rescan_hba_mode;
3028
a93aa1fe
MG		 3029 if (hpsa_gather_lun_info(h, reportlunsize,
3030 (struct ReportLUNdata *) physdev_list, &nphysicals,
283b4a9b 3031 &physical_mode, logdev_list, &nlogicals))
edd16368
SC		 3032 goto out;
3033
aca4a520
ST		 3034 /* We might see up to the maximum number of logical and physical disks
3035 * plus external target devices, and a device for the local RAID
3036 * controller.
edd16368 3037 */
aca4a520 3038 ndevs_to_allocate = nphysicals + nlogicals + MAX_EXT_TARGETS + 1;
edd16368
SC		 3039
3040 /* Allocate the per device structures */
3041 for (i = 0; i < ndevs_to_allocate; i++) {
b7ec021f
ST		 3042 if (i >= HPSA_MAX_DEVICES) {
3043 dev_warn(&h->pdev->dev, "maximum devices (%d) exceeded."
3044 " %d devices ignored.\n", HPSA_MAX_DEVICES,
3045 ndevs_to_allocate - HPSA_MAX_DEVICES);
3046 break;
3047 }
3048
edd16368
SC		 3049 currentsd[i] = kzalloc(sizeof(*currentsd[i]), GFP_KERNEL);
3050 if (!currentsd[i]) {
3051 dev_warn(&h->pdev->dev, "out of memory at %s:%d\n",
3052 __FILE__, __LINE__);
3053 goto out;
3054 }
3055 ndev_allocated++;
3056 }
3057
339b2b14
SC		 3058 if (unlikely(is_scsi_rev_5(h)))
3059 raid_ctlr_position = 0;
3060 else
3061 raid_ctlr_position = nphysicals + nlogicals;
3062
edd16368 3063 /* adjust our table of devices */
4f4eb9f1 3064 n_ext_target_devs = 0;
edd16368 3065 for (i = 0; i < nphysicals + nlogicals + 1; i++) {
0b0e1d6c 3066 u8 *lunaddrbytes, is_OBDR = 0;
edd16368
SC		 3067
3068 /* Figure out where the LUN ID info is coming from */
339b2b14
SC		 3069 lunaddrbytes = figure_lunaddrbytes(h, raid_ctlr_position,
3070 i, nphysicals, nlogicals, physdev_list, logdev_list);
edd16368 3071 /* skip masked physical devices. */
339b2b14
SC		 3072 if (lunaddrbytes[3] & 0xC0 &&
3073 i < nphysicals + (raid_ctlr_position == 0))
edd16368
SC		 3074 continue;
3075
3076 /* Get device type, vendor, model, device id */
0b0e1d6c
SC		 3077 if (hpsa_update_device_info(h, lunaddrbytes, tmpdevice,
3078 &is_OBDR))
edd16368 3079 continue; /* skip it if we can't talk to it. */
1f310bde 3080 figure_bus_target_lun(h, lunaddrbytes, tmpdevice);
edd16368
SC		 3081 this_device = currentsd[ncurrent];
3082
3083 /*
4f4eb9f1 3084 * For external target devices, we have to insert a LUN 0 which
edd16368
SC		 3085 * doesn't show up in CCISS_REPORT_PHYSICAL data, but there
3086 * is nonetheless an enclosure device there. We have to
3087 * present that otherwise linux won't find anything if
3088 * there is no lun 0.
3089 */
4f4eb9f1 3090 if (add_ext_target_dev(h, tmpdevice, this_device,
1f310bde 3091 lunaddrbytes, lunzerobits,
4f4eb9f1 3092 &n_ext_target_devs)) {
edd16368
SC		 3093 ncurrent++;
3094 this_device = currentsd[ncurrent];
3095 }
3096
3097 *this_device = *tmpdevice;
edd16368
SC		 3098
3099 switch (this_device->devtype) {
0b0e1d6c 3100 case TYPE_ROM:
edd16368
SC		 3101 /* We don't *really* support actual CD-ROM devices,
3102 * just "One Button Disaster Recovery" tape drive
3103 * which temporarily pretends to be a CD-ROM drive.
3104 * So we check that the device is really an OBDR tape
3105 * device by checking for "$DR-10" in bytes 43-48 of
3106 * the inquiry data.
3107 */
0b0e1d6c
SC		 3108 if (is_OBDR)
3109 ncurrent++;
edd16368
SC		 3110 break;
3111 case TYPE_DISK:
316b221a
SC		 3112 if (h->hba_mode_enabled) {
3113 /* never use raid mapper in HBA mode */
3114 this_device->offload_enabled = 0;
3115 ncurrent++;
3116 break;
3117 } else if (h->acciopath_status) {
3118 if (i >= nphysicals) {
3119 ncurrent++;
3120 break;
3121 }
3122 } else {
3123 if (i < nphysicals)
3124 break;
283b4a9b 3125 ncurrent++;
edd16368 3126 break;
283b4a9b
SC		 3127 }
3128 if (physical_mode == HPSA_REPORT_PHYS_EXTENDED) {
3129 memcpy(&this_device->ioaccel_handle,
3130 &lunaddrbytes[20],
3131 sizeof(this_device->ioaccel_handle));
3132 ncurrent++;
3133 }
edd16368
SC		 3134 break;
3135 case TYPE_TAPE:
3136 case TYPE_MEDIUM_CHANGER:
3137 ncurrent++;
3138 break;
3139 case TYPE_RAID:
3140 /* Only present the Smartarray HBA as a RAID controller.
3141 * If it's a RAID controller other than the HBA itself
3142 * (an external RAID controller, MSA500 or similar)
3143 * don't present it.
3144 */
3145 if (!is_hba_lunid(lunaddrbytes))
3146 break;
3147 ncurrent++;
3148 break;
3149 default:
3150 break;
3151 }
cfe5badc 3152 if (ncurrent >= HPSA_MAX_DEVICES)
edd16368
SC		 3153 break;
3154 }
3155 adjust_hpsa_scsi_table(h, hostno, currentsd, ncurrent);
3156out:
3157 kfree(tmpdevice);
3158 for (i = 0; i < ndev_allocated; i++)
3159 kfree(currentsd[i]);
3160 kfree(currentsd);
edd16368
SC		 3161 kfree(physdev_list);
3162 kfree(logdev_list);
edd16368
SC		 3163}
3164
3165/* hpsa_scatter_gather takes a struct scsi_cmnd, (cmd), and does the pci
3166 * dma mapping and fills in the scatter gather entries of the
3167 * hpsa command, cp.
3168 */
33a2ffce 3169static int hpsa_scatter_gather(struct ctlr_info *h,
edd16368
SC		 3170 struct CommandList *cp,
3171 struct scsi_cmnd *cmd)
3172{
3173 unsigned int len;
3174 struct scatterlist *sg;
01a02ffc 3175 u64 addr64;
33a2ffce
SC		 3176 int use_sg, i, sg_index, chained;
3177 struct SGDescriptor *curr_sg;
edd16368 3178
33a2ffce 3179 BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
edd16368
SC		 3180
3181 use_sg = scsi_dma_map(cmd);
3182 if (use_sg < 0)
3183 return use_sg;
3184
3185 if (!use_sg)
3186 goto sglist_finished;
3187
33a2ffce
SC		 3188 curr_sg = cp->SG;
3189 chained = 0;
3190 sg_index = 0;
edd16368 3191 scsi_for_each_sg(cmd, sg, use_sg, i) {
33a2ffce
SC		 3192 if (i == h->max_cmd_sg_entries - 1 &&
3193 use_sg > h->max_cmd_sg_entries) {
3194 chained = 1;
3195 curr_sg = h->cmd_sg_list[cp->cmdindex];
3196 sg_index = 0;
3197 }
01a02ffc 3198 addr64 = (u64) sg_dma_address(sg);
edd16368 3199 len = sg_dma_len(sg);
33a2ffce
SC		 3200 curr_sg->Addr.lower = (u32) (addr64 & 0x0FFFFFFFFULL);
3201 curr_sg->Addr.upper = (u32) ((addr64 >> 32) & 0x0FFFFFFFFULL);
3202 curr_sg->Len = len;
e1d9cbfa 3203 curr_sg->Ext = (i < scsi_sg_count(cmd) - 1) ? 0 : HPSA_SG_LAST;
33a2ffce
SC		 3204 curr_sg++;
3205 }
3206
3207 if (use_sg + chained > h->maxSG)
3208 h->maxSG = use_sg + chained;
3209
3210 if (chained) {
3211 cp->Header.SGList = h->max_cmd_sg_entries;
3212 cp->Header.SGTotal = (u16) (use_sg + 1);
e2bea6df
SC		 3213 if (hpsa_map_sg_chain_block(h, cp)) {
3214 scsi_dma_unmap(cmd);
3215 return -1;
3216 }
33a2ffce 3217 return 0;
edd16368
SC		 3218 }
3219
3220sglist_finished:
3221
01a02ffc
SC		 3222 cp->Header.SGList = (u8) use_sg; /* no. SGs contig in this cmd */
3223 cp->Header.SGTotal = (u16) use_sg; /* total sgs in this cmd list */
edd16368
SC		 3224 return 0;
3225}
3226
283b4a9b
SC		 3227#define IO_ACCEL_INELIGIBLE (1)
3228static int fixup_ioaccel_cdb(u8 *cdb, int *cdb_len)
3229{
3230 int is_write = 0;
3231 u32 block;
3232 u32 block_cnt;
3233
3234 /* Perform some CDB fixups if needed using 10 byte reads/writes only */
3235 switch (cdb[0]) {
3236 case WRITE_6:
3237 case WRITE_12:
3238 is_write = 1;
3239 case READ_6:
3240 case READ_12:
3241 if (*cdb_len == 6) {
3242 block = (((u32) cdb[2]) << 8) | cdb[3];
3243 block_cnt = cdb[4];
3244 } else {
3245 BUG_ON(*cdb_len != 12);
3246 block = (((u32) cdb[2]) << 24) |
3247 (((u32) cdb[3]) << 16) |
3248 (((u32) cdb[4]) << 8) |
3249 cdb[5];
3250 block_cnt =
3251 (((u32) cdb[6]) << 24) |
3252 (((u32) cdb[7]) << 16) |
3253 (((u32) cdb[8]) << 8) |
3254 cdb[9];
3255 }
3256 if (block_cnt > 0xffff)
3257 return IO_ACCEL_INELIGIBLE;
3258
3259 cdb[0] = is_write ? WRITE_10 : READ_10;
3260 cdb[1] = 0;
3261 cdb[2] = (u8) (block >> 24);
3262 cdb[3] = (u8) (block >> 16);
3263 cdb[4] = (u8) (block >> 8);
3264 cdb[5] = (u8) (block);
3265 cdb[6] = 0;
3266 cdb[7] = (u8) (block_cnt >> 8);
3267 cdb[8] = (u8) (block_cnt);
3268 cdb[9] = 0;
3269 *cdb_len = 10;
3270 break;
3271 }
3272 return 0;
3273}
3274
c349775e 3275static int hpsa_scsi_ioaccel1_queue_command(struct ctlr_info *h,
283b4a9b
SC		 3276 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
3277 u8 *scsi3addr)
e1f7de0c
MG		 3278{
3279 struct scsi_cmnd *cmd = c->scsi_cmd;
e1f7de0c
MG		 3280 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
3281 unsigned int len;
3282 unsigned int total_len = 0;
3283 struct scatterlist *sg;
3284 u64 addr64;
3285 int use_sg, i;
3286 struct SGDescriptor *curr_sg;
3287 u32 control = IOACCEL1_CONTROL_SIMPLEQUEUE;
3288
283b4a9b
SC		 3289 /* TODO: implement chaining support */
3290 if (scsi_sg_count(cmd) > h->ioaccel_maxsg)
3291 return IO_ACCEL_INELIGIBLE;
3292
e1f7de0c
MG		 3293 BUG_ON(cmd->cmd_len > IOACCEL1_IOFLAGS_CDBLEN_MAX);
3294
283b4a9b
SC		 3295 if (fixup_ioaccel_cdb(cdb, &cdb_len))
3296 return IO_ACCEL_INELIGIBLE;
3297
e1f7de0c
MG		 3298 c->cmd_type = CMD_IOACCEL1;
3299
3300 /* Adjust the DMA address to point to the accelerated command buffer */
3301 c->busaddr = (u32) h->ioaccel_cmd_pool_dhandle +
3302 (c->cmdindex * sizeof(*cp));
3303 BUG_ON(c->busaddr & 0x0000007F);
3304
3305 use_sg = scsi_dma_map(cmd);
3306 if (use_sg < 0)
3307 return use_sg;
3308
3309 if (use_sg) {
3310 curr_sg = cp->SG;
3311 scsi_for_each_sg(cmd, sg, use_sg, i) {
3312 addr64 = (u64) sg_dma_address(sg);
3313 len = sg_dma_len(sg);
3314 total_len += len;
3315 curr_sg->Addr.lower = (u32) (addr64 & 0x0FFFFFFFFULL);
3316 curr_sg->Addr.upper =
3317 (u32) ((addr64 >> 32) & 0x0FFFFFFFFULL);
3318 curr_sg->Len = len;
3319
3320 if (i == (scsi_sg_count(cmd) - 1))
3321 curr_sg->Ext = HPSA_SG_LAST;
3322 else
3323 curr_sg->Ext = 0; /* we are not chaining */
3324 curr_sg++;
3325 }
3326
3327 switch (cmd->sc_data_direction) {
3328 case DMA_TO_DEVICE:
3329 control |= IOACCEL1_CONTROL_DATA_OUT;
3330 break;
3331 case DMA_FROM_DEVICE:
3332 control |= IOACCEL1_CONTROL_DATA_IN;
3333 break;
3334 case DMA_NONE:
3335 control |= IOACCEL1_CONTROL_NODATAXFER;
3336 break;
3337 default:
3338 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
3339 cmd->sc_data_direction);
3340 BUG();
3341 break;
3342 }
3343 } else {
3344 control |= IOACCEL1_CONTROL_NODATAXFER;
3345 }
3346
c349775e 3347 c->Header.SGList = use_sg;
e1f7de0c 3348 /* Fill out the command structure to submit */
283b4a9b 3349 cp->dev_handle = ioaccel_handle & 0xFFFF;
e1f7de0c
MG		 3350 cp->transfer_len = total_len;
3351 cp->io_flags = IOACCEL1_IOFLAGS_IO_REQ |
283b4a9b 3352 (cdb_len & IOACCEL1_IOFLAGS_CDBLEN_MASK);
e1f7de0c 3353 cp->control = control;
283b4a9b
SC		 3354 memcpy(cp->CDB, cdb, cdb_len);
3355 memcpy(cp->CISS_LUN, scsi3addr, 8);
c349775e 3356 /* Tag was already set at init time. */
283b4a9b 3357 enqueue_cmd_and_start_io(h, c);
e1f7de0c
MG		 3358 return 0;
3359}
edd16368 3360
283b4a9b
SC		 3361/*
3362 * Queue a command directly to a device behind the controller using the
3363 * I/O accelerator path.
3364 */
3365static int hpsa_scsi_ioaccel_direct_map(struct ctlr_info *h,
3366 struct CommandList *c)
3367{
3368 struct scsi_cmnd *cmd = c->scsi_cmd;
3369 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
3370
3371 return hpsa_scsi_ioaccel_queue_command(h, c, dev->ioaccel_handle,
3372 cmd->cmnd, cmd->cmd_len, dev->scsi3addr);
3373}
3374
dd0e19f3
ST		 3375/*
3376 * Set encryption parameters for the ioaccel2 request
3377 */
3378static void set_encrypt_ioaccel2(struct ctlr_info *h,
3379 struct CommandList *c, struct io_accel2_cmd *cp)
3380{
3381 struct scsi_cmnd *cmd = c->scsi_cmd;
3382 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
3383 struct raid_map_data *map = &dev->raid_map;
3384 u64 first_block;
3385
3386 BUG_ON(!(dev->offload_config && dev->offload_enabled));
3387
3388 /* Are we doing encryption on this device */
3389 if (!(map->flags & RAID_MAP_FLAG_ENCRYPT_ON))
3390 return;
3391 /* Set the data encryption key index. */
3392 cp->dekindex = map->dekindex;
3393
3394 /* Set the encryption enable flag, encoded into direction field. */
3395 cp->direction |= IOACCEL2_DIRECTION_ENCRYPT_MASK;
3396
3397 /* Set encryption tweak values based on logical block address
3398 * If block size is 512, tweak value is LBA.
3399 * For other block sizes, tweak is (LBA * block size)/ 512)
3400 */
3401 switch (cmd->cmnd[0]) {
3402 /* Required? 6-byte cdbs eliminated by fixup_ioaccel_cdb */
3403 case WRITE_6:
3404 case READ_6:
3405 if (map->volume_blk_size == 512) {
3406 cp->tweak_lower =
3407 (((u32) cmd->cmnd[2]) << 8) |
3408 cmd->cmnd[3];
3409 cp->tweak_upper = 0;
3410 } else {
3411 first_block =
3412 (((u64) cmd->cmnd[2]) << 8) |
3413 cmd->cmnd[3];
3414 first_block = (first_block * map->volume_blk_size)/512;
3415 cp->tweak_lower = (u32)first_block;
3416 cp->tweak_upper = (u32)(first_block >> 32);
3417 }
3418 break;
3419 case WRITE_10:
3420 case READ_10:
3421 if (map->volume_blk_size == 512) {
3422 cp->tweak_lower =
3423 (((u32) cmd->cmnd[2]) << 24) |
3424 (((u32) cmd->cmnd[3]) << 16) |
3425 (((u32) cmd->cmnd[4]) << 8) |
3426 cmd->cmnd[5];
3427 cp->tweak_upper = 0;
3428 } else {
3429 first_block =
3430 (((u64) cmd->cmnd[2]) << 24) |
3431 (((u64) cmd->cmnd[3]) << 16) |
3432 (((u64) cmd->cmnd[4]) << 8) |
3433 cmd->cmnd[5];
3434 first_block = (first_block * map->volume_blk_size)/512;
3435 cp->tweak_lower = (u32)first_block;
3436 cp->tweak_upper = (u32)(first_block >> 32);
3437 }
3438 break;
3439 /* Required? 12-byte cdbs eliminated by fixup_ioaccel_cdb */
3440 case WRITE_12:
3441 case READ_12:
3442 if (map->volume_blk_size == 512) {
3443 cp->tweak_lower =
3444 (((u32) cmd->cmnd[2]) << 24) |
3445 (((u32) cmd->cmnd[3]) << 16) |
3446 (((u32) cmd->cmnd[4]) << 8) |
3447 cmd->cmnd[5];
3448 cp->tweak_upper = 0;
3449 } else {
3450 first_block =
3451 (((u64) cmd->cmnd[2]) << 24) |
3452 (((u64) cmd->cmnd[3]) << 16) |
3453 (((u64) cmd->cmnd[4]) << 8) |
3454 cmd->cmnd[5];
3455 first_block = (first_block * map->volume_blk_size)/512;
3456 cp->tweak_lower = (u32)first_block;
3457 cp->tweak_upper = (u32)(first_block >> 32);
3458 }
3459 break;
3460 case WRITE_16:
3461 case READ_16:
3462 if (map->volume_blk_size == 512) {
3463 cp->tweak_lower =
3464 (((u32) cmd->cmnd[6]) << 24) |
3465 (((u32) cmd->cmnd[7]) << 16) |
3466 (((u32) cmd->cmnd[8]) << 8) |
3467 cmd->cmnd[9];
3468 cp->tweak_upper =
3469 (((u32) cmd->cmnd[2]) << 24) |
3470 (((u32) cmd->cmnd[3]) << 16) |
3471 (((u32) cmd->cmnd[4]) << 8) |
3472 cmd->cmnd[5];
3473 } else {
3474 first_block =
3475 (((u64) cmd->cmnd[2]) << 56) |
3476 (((u64) cmd->cmnd[3]) << 48) |
3477 (((u64) cmd->cmnd[4]) << 40) |
3478 (((u64) cmd->cmnd[5]) << 32) |
3479 (((u64) cmd->cmnd[6]) << 24) |
3480 (((u64) cmd->cmnd[7]) << 16) |
3481 (((u64) cmd->cmnd[8]) << 8) |
3482 cmd->cmnd[9];
3483 first_block = (first_block * map->volume_blk_size)/512;
3484 cp->tweak_lower = (u32)first_block;
3485 cp->tweak_upper = (u32)(first_block >> 32);
3486 }
3487 break;
3488 default:
3489 dev_err(&h->pdev->dev,
3490 "ERROR: %s: IOACCEL request CDB size not supported for encryption\n",
3491 __func__);
3492 BUG();
3493 break;
3494 }
3495}
3496
c349775e
ST		 3497static int hpsa_scsi_ioaccel2_queue_command(struct ctlr_info *h,
3498 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
3499 u8 *scsi3addr)
3500{
3501 struct scsi_cmnd *cmd = c->scsi_cmd;
3502 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
3503 struct ioaccel2_sg_element *curr_sg;
3504 int use_sg, i;
3505 struct scatterlist *sg;
3506 u64 addr64;
3507 u32 len;
3508 u32 total_len = 0;
3509
3510 if (scsi_sg_count(cmd) > h->ioaccel_maxsg)
3511 return IO_ACCEL_INELIGIBLE;
3512
3513 if (fixup_ioaccel_cdb(cdb, &cdb_len))
3514 return IO_ACCEL_INELIGIBLE;
3515 c->cmd_type = CMD_IOACCEL2;
3516 /* Adjust the DMA address to point to the accelerated command buffer */
3517 c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle +
3518 (c->cmdindex * sizeof(*cp));
3519 BUG_ON(c->busaddr & 0x0000007F);
3520
3521 memset(cp, 0, sizeof(*cp));
3522 cp->IU_type = IOACCEL2_IU_TYPE;
3523
3524 use_sg = scsi_dma_map(cmd);
3525 if (use_sg < 0)
3526 return use_sg;
3527
3528 if (use_sg) {
3529 BUG_ON(use_sg > IOACCEL2_MAXSGENTRIES);
3530 curr_sg = cp->sg;
3531 scsi_for_each_sg(cmd, sg, use_sg, i) {
3532 addr64 = (u64) sg_dma_address(sg);
3533 len = sg_dma_len(sg);
3534 total_len += len;
3535 curr_sg->address = cpu_to_le64(addr64);
3536 curr_sg->length = cpu_to_le32(len);
3537 curr_sg->reserved[0] = 0;
3538 curr_sg->reserved[1] = 0;
3539 curr_sg->reserved[2] = 0;
3540 curr_sg->chain_indicator = 0;
3541 curr_sg++;
3542 }
3543
3544 switch (cmd->sc_data_direction) {
3545 case DMA_TO_DEVICE:
dd0e19f3
ST		 3546 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3547 cp->direction |= IOACCEL2_DIR_DATA_OUT;
c349775e
ST		 3548 break;
3549 case DMA_FROM_DEVICE:
dd0e19f3
ST		 3550 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3551 cp->direction |= IOACCEL2_DIR_DATA_IN;
c349775e
ST		 3552 break;
3553 case DMA_NONE:
dd0e19f3
ST		 3554 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3555 cp->direction |= IOACCEL2_DIR_NO_DATA;
c349775e
ST		 3556 break;
3557 default:
3558 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
3559 cmd->sc_data_direction);
3560 BUG();
3561 break;
3562 }
3563 } else {
dd0e19f3
ST		 3564 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3565 cp->direction |= IOACCEL2_DIR_NO_DATA;
c349775e 3566 }
dd0e19f3
ST		 3567
3568 /* Set encryption parameters, if necessary */
3569 set_encrypt_ioaccel2(h, c, cp);
3570
c349775e 3571 cp->scsi_nexus = ioaccel_handle;
dd0e19f3 3572 cp->Tag = (c->cmdindex << DIRECT_LOOKUP_SHIFT) |
c349775e
ST		 3573 DIRECT_LOOKUP_BIT;
3574 memcpy(cp->cdb, cdb, sizeof(cp->cdb));
c349775e
ST		 3575
3576 /* fill in sg elements */
3577 cp->sg_count = (u8) use_sg;
3578
3579 cp->data_len = cpu_to_le32(total_len);
3580 cp->err_ptr = cpu_to_le64(c->busaddr +
3581 offsetof(struct io_accel2_cmd, error_data));
3582 cp->err_len = cpu_to_le32((u32) sizeof(cp->error_data));
3583
3584 enqueue_cmd_and_start_io(h, c);
3585 return 0;
3586}
3587
3588/*
3589 * Queue a command to the correct I/O accelerator path.
3590 */
3591static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
3592 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
3593 u8 *scsi3addr)
3594{
3595 if (h->transMethod & CFGTBL_Trans_io_accel1)
3596 return hpsa_scsi_ioaccel1_queue_command(h, c, ioaccel_handle,
3597 cdb, cdb_len, scsi3addr);
3598 else
3599 return hpsa_scsi_ioaccel2_queue_command(h, c, ioaccel_handle,
3600 cdb, cdb_len, scsi3addr);
3601}
3602
6b80b18f
ST		 3603static void raid_map_helper(struct raid_map_data *map,
3604 int offload_to_mirror, u32 *map_index, u32 *current_group)
3605{
3606 if (offload_to_mirror == 0) {
3607 /* use physical disk in the first mirrored group. */
3608 *map_index %= map->data_disks_per_row;
3609 return;
3610 }
3611 do {
3612 /* determine mirror group that *map_index indicates */
3613 *current_group = *map_index / map->data_disks_per_row;
3614 if (offload_to_mirror == *current_group)
3615 continue;
3616 if (*current_group < (map->layout_map_count - 1)) {
3617 /* select map index from next group */
3618 *map_index += map->data_disks_per_row;
3619 (*current_group)++;
3620 } else {
3621 /* select map index from first group */
3622 *map_index %= map->data_disks_per_row;
3623 *current_group = 0;
3624 }
3625 } while (offload_to_mirror != *current_group);
3626}
3627
283b4a9b
SC		 3628/*
3629 * Attempt to perform offload RAID mapping for a logical volume I/O.
3630 */
3631static int hpsa_scsi_ioaccel_raid_map(struct ctlr_info *h,
3632 struct CommandList *c)
3633{
3634 struct scsi_cmnd *cmd = c->scsi_cmd;
3635 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
3636 struct raid_map_data *map = &dev->raid_map;
3637 struct raid_map_disk_data *dd = &map->data[0];
3638 int is_write = 0;
3639 u32 map_index;
3640 u64 first_block, last_block;
3641 u32 block_cnt;
3642 u32 blocks_per_row;
3643 u64 first_row, last_row;
3644 u32 first_row_offset, last_row_offset;
3645 u32 first_column, last_column;
6b80b18f
ST		 3646 u64 r0_first_row, r0_last_row;
3647 u32 r5or6_blocks_per_row;
3648 u64 r5or6_first_row, r5or6_last_row;
3649 u32 r5or6_first_row_offset, r5or6_last_row_offset;
3650 u32 r5or6_first_column, r5or6_last_column;
3651 u32 total_disks_per_row;
3652 u32 stripesize;
3653 u32 first_group, last_group, current_group;
283b4a9b
SC		 3654 u32 map_row;
3655 u32 disk_handle;
3656 u64 disk_block;
3657 u32 disk_block_cnt;
3658 u8 cdb[16];
3659 u8 cdb_len;
3660#if BITS_PER_LONG == 32
3661 u64 tmpdiv;
3662#endif
6b80b18f 3663 int offload_to_mirror;
283b4a9b
SC		 3664
3665 BUG_ON(!(dev->offload_config && dev->offload_enabled));
3666
3667 /* check for valid opcode, get LBA and block count */
3668 switch (cmd->cmnd[0]) {
3669 case WRITE_6:
3670 is_write = 1;
3671 case READ_6:
3672 first_block =
3673 (((u64) cmd->cmnd[2]) << 8) |
3674 cmd->cmnd[3];
3675 block_cnt = cmd->cmnd[4];
3676 break;
3677 case WRITE_10:
3678 is_write = 1;
3679 case READ_10:
3680 first_block =
3681 (((u64) cmd->cmnd[2]) << 24) |
3682 (((u64) cmd->cmnd[3]) << 16) |
3683 (((u64) cmd->cmnd[4]) << 8) |
3684 cmd->cmnd[5];
3685 block_cnt =
3686 (((u32) cmd->cmnd[7]) << 8) |
3687 cmd->cmnd[8];
3688 break;
3689 case WRITE_12:
3690 is_write = 1;
3691 case READ_12:
3692 first_block =
3693 (((u64) cmd->cmnd[2]) << 24) |
3694 (((u64) cmd->cmnd[3]) << 16) |
3695 (((u64) cmd->cmnd[4]) << 8) |
3696 cmd->cmnd[5];
3697 block_cnt =
3698 (((u32) cmd->cmnd[6]) << 24) |
3699 (((u32) cmd->cmnd[7]) << 16) |
3700 (((u32) cmd->cmnd[8]) << 8) |
3701 cmd->cmnd[9];
3702 break;
3703 case WRITE_16:
3704 is_write = 1;
3705 case READ_16:
3706 first_block =
3707 (((u64) cmd->cmnd[2]) << 56) |
3708 (((u64) cmd->cmnd[3]) << 48) |
3709 (((u64) cmd->cmnd[4]) << 40) |
3710 (((u64) cmd->cmnd[5]) << 32) |
3711 (((u64) cmd->cmnd[6]) << 24) |
3712 (((u64) cmd->cmnd[7]) << 16) |
3713 (((u64) cmd->cmnd[8]) << 8) |
3714 cmd->cmnd[9];
3715 block_cnt =
3716 (((u32) cmd->cmnd[10]) << 24) |
3717 (((u32) cmd->cmnd[11]) << 16) |
3718 (((u32) cmd->cmnd[12]) << 8) |
3719 cmd->cmnd[13];
3720 break;
3721 default:
3722 return IO_ACCEL_INELIGIBLE; /* process via normal I/O path */
3723 }
3724 BUG_ON(block_cnt == 0);
3725 last_block = first_block + block_cnt - 1;
3726
3727 /* check for write to non-RAID-0 */
3728 if (is_write && dev->raid_level != 0)
3729 return IO_ACCEL_INELIGIBLE;
3730
3731 /* check for invalid block or wraparound */
3732 if (last_block >= map->volume_blk_cnt || last_block < first_block)
3733 return IO_ACCEL_INELIGIBLE;
3734
3735 /* calculate stripe information for the request */
3736 blocks_per_row = map->data_disks_per_row * map->strip_size;
3737#if BITS_PER_LONG == 32
3738 tmpdiv = first_block;
3739 (void) do_div(tmpdiv, blocks_per_row);
3740 first_row = tmpdiv;
3741 tmpdiv = last_block;
3742 (void) do_div(tmpdiv, blocks_per_row);
3743 last_row = tmpdiv;
3744 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
3745 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
3746 tmpdiv = first_row_offset;
3747 (void) do_div(tmpdiv, map->strip_size);
3748 first_column = tmpdiv;
3749 tmpdiv = last_row_offset;
3750 (void) do_div(tmpdiv, map->strip_size);
3751 last_column = tmpdiv;
3752#else
3753 first_row = first_block / blocks_per_row;
3754 last_row = last_block / blocks_per_row;
3755 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
3756 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
3757 first_column = first_row_offset / map->strip_size;
3758 last_column = last_row_offset / map->strip_size;
3759#endif
3760
3761 /* if this isn't a single row/column then give to the controller */
3762 if ((first_row != last_row) || (first_column != last_column))
3763 return IO_ACCEL_INELIGIBLE;
3764
3765 /* proceeding with driver mapping */
6b80b18f
ST		 3766 total_disks_per_row = map->data_disks_per_row +
3767 map->metadata_disks_per_row;
283b4a9b
SC		 3768 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
3769 map->row_cnt;
6b80b18f
ST		 3770 map_index = (map_row * total_disks_per_row) + first_column;
3771
3772 switch (dev->raid_level) {
3773 case HPSA_RAID_0:
3774 break; /* nothing special to do */
3775 case HPSA_RAID_1:
3776 /* Handles load balance across RAID 1 members.
3777 * (2-drive R1 and R10 with even # of drives.)
3778 * Appropriate for SSDs, not optimal for HDDs
283b4a9b 3779 */
6b80b18f 3780 BUG_ON(map->layout_map_count != 2);
283b4a9b
SC		 3781 if (dev->offload_to_mirror)
3782 map_index += map->data_disks_per_row;
3783 dev->offload_to_mirror = !dev->offload_to_mirror;
6b80b18f
ST		 3784 break;
3785 case HPSA_RAID_ADM:
3786 /* Handles N-way mirrors (R1-ADM)
3787 * and R10 with # of drives divisible by 3.)
3788 */
3789 BUG_ON(map->layout_map_count != 3);
3790
3791 offload_to_mirror = dev->offload_to_mirror;
3792 raid_map_helper(map, offload_to_mirror,
3793 &map_index, &current_group);
3794 /* set mirror group to use next time */
3795 offload_to_mirror =
3796 (offload_to_mirror >= map->layout_map_count - 1)
3797 ? 0 : offload_to_mirror + 1;
3798 /* FIXME: remove after debug/dev */
3799 BUG_ON(offload_to_mirror >= map->layout_map_count);
3800 dev_warn(&h->pdev->dev,
3801 "DEBUG: Using physical disk map index %d from mirror group %d\n",
3802 map_index, offload_to_mirror);
3803 dev->offload_to_mirror = offload_to_mirror;
3804 /* Avoid direct use of dev->offload_to_mirror within this
3805 * function since multiple threads might simultaneously
3806 * increment it beyond the range of dev->layout_map_count -1.
3807 */
3808 break;
3809 case HPSA_RAID_5:
3810 case HPSA_RAID_6:
3811 if (map->layout_map_count <= 1)
3812 break;
3813
3814 /* Verify first and last block are in same RAID group */
3815 r5or6_blocks_per_row =
3816 map->strip_size * map->data_disks_per_row;
3817 BUG_ON(r5or6_blocks_per_row == 0);
3818 stripesize = r5or6_blocks_per_row * map->layout_map_count;
3819#if BITS_PER_LONG == 32
3820 tmpdiv = first_block;
3821 first_group = do_div(tmpdiv, stripesize);
3822 tmpdiv = first_group;
3823 (void) do_div(tmpdiv, r5or6_blocks_per_row);
3824 first_group = tmpdiv;
3825 tmpdiv = last_block;
3826 last_group = do_div(tmpdiv, stripesize);
3827 tmpdiv = last_group;
3828 (void) do_div(tmpdiv, r5or6_blocks_per_row);
3829 last_group = tmpdiv;
3830#else
3831 first_group = (first_block % stripesize) / r5or6_blocks_per_row;
3832 last_group = (last_block % stripesize) / r5or6_blocks_per_row;
6b80b18f 3833#endif
000ff7c2 3834 if (first_group != last_group)
6b80b18f
ST		 3835 return IO_ACCEL_INELIGIBLE;
3836
3837 /* Verify request is in a single row of RAID 5/6 */
3838#if BITS_PER_LONG == 32
3839 tmpdiv = first_block;
3840 (void) do_div(tmpdiv, stripesize);
3841 first_row = r5or6_first_row = r0_first_row = tmpdiv;
3842 tmpdiv = last_block;
3843 (void) do_div(tmpdiv, stripesize);
3844 r5or6_last_row = r0_last_row = tmpdiv;
3845#else
3846 first_row = r5or6_first_row = r0_first_row =
3847 first_block / stripesize;
3848 r5or6_last_row = r0_last_row = last_block / stripesize;
3849#endif
3850 if (r5or6_first_row != r5or6_last_row)
3851 return IO_ACCEL_INELIGIBLE;
3852
3853
3854 /* Verify request is in a single column */
3855#if BITS_PER_LONG == 32
3856 tmpdiv = first_block;
3857 first_row_offset = do_div(tmpdiv, stripesize);
3858 tmpdiv = first_row_offset;
3859 first_row_offset = (u32) do_div(tmpdiv, r5or6_blocks_per_row);
3860 r5or6_first_row_offset = first_row_offset;
3861 tmpdiv = last_block;
3862 r5or6_last_row_offset = do_div(tmpdiv, stripesize);
3863 tmpdiv = r5or6_last_row_offset;
3864 r5or6_last_row_offset = do_div(tmpdiv, r5or6_blocks_per_row);
3865 tmpdiv = r5or6_first_row_offset;
3866 (void) do_div(tmpdiv, map->strip_size);
3867 first_column = r5or6_first_column = tmpdiv;
3868 tmpdiv = r5or6_last_row_offset;
3869 (void) do_div(tmpdiv, map->strip_size);
3870 r5or6_last_column = tmpdiv;
3871#else
3872 first_row_offset = r5or6_first_row_offset =
3873 (u32)((first_block % stripesize) %
3874 r5or6_blocks_per_row);
3875
3876 r5or6_last_row_offset =
3877 (u32)((last_block % stripesize) %
3878 r5or6_blocks_per_row);
3879
3880 first_column = r5or6_first_column =
3881 r5or6_first_row_offset / map->strip_size;
3882 r5or6_last_column =
3883 r5or6_last_row_offset / map->strip_size;
3884#endif
3885 if (r5or6_first_column != r5or6_last_column)
3886 return IO_ACCEL_INELIGIBLE;
3887
3888 /* Request is eligible */
3889 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
3890 map->row_cnt;
3891
3892 map_index = (first_group *
3893 (map->row_cnt * total_disks_per_row)) +
3894 (map_row * total_disks_per_row) + first_column;
3895 break;
3896 default:
3897 return IO_ACCEL_INELIGIBLE;
283b4a9b 3898 }
6b80b18f 3899
283b4a9b
SC		 3900 disk_handle = dd[map_index].ioaccel_handle;
3901 disk_block = map->disk_starting_blk + (first_row * map->strip_size) +
3902 (first_row_offset - (first_column * map->strip_size));
3903 disk_block_cnt = block_cnt;
3904
3905 /* handle differing logical/physical block sizes */
3906 if (map->phys_blk_shift) {
3907 disk_block <<= map->phys_blk_shift;
3908 disk_block_cnt <<= map->phys_blk_shift;
3909 }
3910 BUG_ON(disk_block_cnt > 0xffff);
3911
3912 /* build the new CDB for the physical disk I/O */
3913 if (disk_block > 0xffffffff) {
3914 cdb[0] = is_write ? WRITE_16 : READ_16;
3915 cdb[1] = 0;
3916 cdb[2] = (u8) (disk_block >> 56);
3917 cdb[3] = (u8) (disk_block >> 48);
3918 cdb[4] = (u8) (disk_block >> 40);
3919 cdb[5] = (u8) (disk_block >> 32);
3920 cdb[6] = (u8) (disk_block >> 24);
3921 cdb[7] = (u8) (disk_block >> 16);
3922 cdb[8] = (u8) (disk_block >> 8);
3923 cdb[9] = (u8) (disk_block);
3924 cdb[10] = (u8) (disk_block_cnt >> 24);
3925 cdb[11] = (u8) (disk_block_cnt >> 16);
3926 cdb[12] = (u8) (disk_block_cnt >> 8);
3927 cdb[13] = (u8) (disk_block_cnt);
3928 cdb[14] = 0;
3929 cdb[15] = 0;
3930 cdb_len = 16;
3931 } else {
3932 cdb[0] = is_write ? WRITE_10 : READ_10;
3933 cdb[1] = 0;
3934 cdb[2] = (u8) (disk_block >> 24);
3935 cdb[3] = (u8) (disk_block >> 16);
3936 cdb[4] = (u8) (disk_block >> 8);
3937 cdb[5] = (u8) (disk_block);
3938 cdb[6] = 0;
3939 cdb[7] = (u8) (disk_block_cnt >> 8);
3940 cdb[8] = (u8) (disk_block_cnt);
3941 cdb[9] = 0;
3942 cdb_len = 10;
3943 }
3944 return hpsa_scsi_ioaccel_queue_command(h, c, disk_handle, cdb, cdb_len,
3945 dev->scsi3addr);
3946}
3947
f281233d 3948static int hpsa_scsi_queue_command_lck(struct scsi_cmnd *cmd,
edd16368
SC		 3949 void (*done)(struct scsi_cmnd *))
3950{
3951 struct ctlr_info *h;
3952 struct hpsa_scsi_dev_t *dev;
3953 unsigned char scsi3addr[8];
3954 struct CommandList *c;
3955 unsigned long flags;
283b4a9b 3956 int rc = 0;
edd16368
SC		 3957
3958 /* Get the ptr to our adapter structure out of cmd->host. */
3959 h = sdev_to_hba(cmd->device);
3960 dev = cmd->device->hostdata;
3961 if (!dev) {
3962 cmd->result = DID_NO_CONNECT << 16;
3963 done(cmd);
3964 return 0;
3965 }
3966 memcpy(scsi3addr, dev->scsi3addr, sizeof(scsi3addr));
3967
edd16368 3968 spin_lock_irqsave(&h->lock, flags);
a0c12413
SC		 3969 if (unlikely(h->lockup_detected)) {
3970 spin_unlock_irqrestore(&h->lock, flags);
3971 cmd->result = DID_ERROR << 16;
3972 done(cmd);
3973 return 0;
3974 }
edd16368 3975 spin_unlock_irqrestore(&h->lock, flags);
e16a33ad 3976 c = cmd_alloc(h);
edd16368
SC		 3977 if (c == NULL) { /* trouble... */
3978 dev_err(&h->pdev->dev, "cmd_alloc returned NULL!\n");
3979 return SCSI_MLQUEUE_HOST_BUSY;
3980 }
3981
3982 /* Fill in the command list header */
3983
3984 cmd->scsi_done = done; /* save this for use by completion code */
3985
3986 /* save c in case we have to abort it */
3987 cmd->host_scribble = (unsigned char *) c;
3988
3989 c->cmd_type = CMD_SCSI;
3990 c->scsi_cmd = cmd;
e1f7de0c 3991
283b4a9b
SC		 3992 /* Call alternate submit routine for I/O accelerated commands.
3993 * Retries always go down the normal I/O path.
3994 */
3995 if (likely(cmd->retries == 0 &&
da0697bd
ST		 3996 cmd->request->cmd_type == REQ_TYPE_FS &&
3997 h->acciopath_status)) {
283b4a9b
SC		 3998 if (dev->offload_enabled) {
3999 rc = hpsa_scsi_ioaccel_raid_map(h, c);
4000 if (rc == 0)
4001 return 0; /* Sent on ioaccel path */
4002 if (rc < 0) { /* scsi_dma_map failed. */
4003 cmd_free(h, c);
4004 return SCSI_MLQUEUE_HOST_BUSY;
4005 }
4006 } else if (dev->ioaccel_handle) {
4007 rc = hpsa_scsi_ioaccel_direct_map(h, c);
4008 if (rc == 0)
4009 return 0; /* Sent on direct map path */
4010 if (rc < 0) { /* scsi_dma_map failed. */
4011 cmd_free(h, c);
4012 return SCSI_MLQUEUE_HOST_BUSY;
4013 }
4014 }
4015 }
e1f7de0c 4016
edd16368
SC		 4017 c->Header.ReplyQueue = 0; /* unused in simple mode */
4018 memcpy(&c->Header.LUN.LunAddrBytes[0], &scsi3addr[0], 8);
303932fd
DB		 4019 c->Header.Tag.lower = (c->cmdindex << DIRECT_LOOKUP_SHIFT);
4020 c->Header.Tag.lower |= DIRECT_LOOKUP_BIT;
edd16368
SC		 4021
4022 /* Fill in the request block... */
4023
4024 c->Request.Timeout = 0;
4025 memset(c->Request.CDB, 0, sizeof(c->Request.CDB));
4026 BUG_ON(cmd->cmd_len > sizeof(c->Request.CDB));
4027 c->Request.CDBLen = cmd->cmd_len;
4028 memcpy(c->Request.CDB, cmd->cmnd, cmd->cmd_len);
4029 c->Request.Type.Type = TYPE_CMD;
4030 c->Request.Type.Attribute = ATTR_SIMPLE;
4031 switch (cmd->sc_data_direction) {
4032 case DMA_TO_DEVICE:
4033 c->Request.Type.Direction = XFER_WRITE;
4034 break;
4035 case DMA_FROM_DEVICE:
4036 c->Request.Type.Direction = XFER_READ;
4037 break;
4038 case DMA_NONE:
4039 c->Request.Type.Direction = XFER_NONE;
4040 break;
4041 case DMA_BIDIRECTIONAL:
4042 /* This can happen if a buggy application does a scsi passthru
4043 * and sets both inlen and outlen to non-zero. ( see
4044 * ../scsi/scsi_ioctl.c:scsi_ioctl_send_command() )
4045 */
4046
4047 c->Request.Type.Direction = XFER_RSVD;
4048 /* This is technically wrong, and hpsa controllers should
4049 * reject it with CMD_INVALID, which is the most correct
4050 * response, but non-fibre backends appear to let it
4051 * slide by, and give the same results as if this field
4052 * were set correctly. Either way is acceptable for
4053 * our purposes here.
4054 */
4055
4056 break;
4057
4058 default:
4059 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
4060 cmd->sc_data_direction);
4061 BUG();
4062 break;
4063 }
4064
33a2ffce 4065 if (hpsa_scatter_gather(h, c, cmd) < 0) { /* Fill SG list */
edd16368
SC		 4066 cmd_free(h, c);
4067 return SCSI_MLQUEUE_HOST_BUSY;
4068 }
4069 enqueue_cmd_and_start_io(h, c);
4070 /* the cmd'll come back via intr handler in complete_scsi_command() */
4071 return 0;
4072}
4073
f281233d
JG		 4074static DEF_SCSI_QCMD(hpsa_scsi_queue_command)
4075
5f389360
SC		 4076static int do_not_scan_if_controller_locked_up(struct ctlr_info *h)
4077{
4078 unsigned long flags;
4079
4080 /*
4081 * Don't let rescans be initiated on a controller known
4082 * to be locked up. If the controller locks up *during*
4083 * a rescan, that thread is probably hosed, but at least
4084 * we can prevent new rescan threads from piling up on a
4085 * locked up controller.
4086 */
4087 spin_lock_irqsave(&h->lock, flags);
4088 if (unlikely(h->lockup_detected)) {
4089 spin_unlock_irqrestore(&h->lock, flags);
4090 spin_lock_irqsave(&h->scan_lock, flags);
4091 h->scan_finished = 1;
4092 wake_up_all(&h->scan_wait_queue);
4093 spin_unlock_irqrestore(&h->scan_lock, flags);
4094 return 1;
4095 }
4096 spin_unlock_irqrestore(&h->lock, flags);
4097 return 0;
4098}
4099
a08a8471
SC		 4100static void hpsa_scan_start(struct Scsi_Host *sh)
4101{
4102 struct ctlr_info *h = shost_to_hba(sh);
4103 unsigned long flags;
4104
5f389360
SC		 4105 if (do_not_scan_if_controller_locked_up(h))
4106 return;
4107
a08a8471
SC		 4108 /* wait until any scan already in progress is finished. */
4109 while (1) {
4110 spin_lock_irqsave(&h->scan_lock, flags);
4111 if (h->scan_finished)
4112 break;
4113 spin_unlock_irqrestore(&h->scan_lock, flags);
4114 wait_event(h->scan_wait_queue, h->scan_finished);
4115 /* Note: We don't need to worry about a race between this
4116 * thread and driver unload because the midlayer will
4117 * have incremented the reference count, so unload won't
4118 * happen if we're in here.
4119 */
4120 }
4121 h->scan_finished = 0; /* mark scan as in progress */
4122 spin_unlock_irqrestore(&h->scan_lock, flags);
4123
5f389360
SC		 4124 if (do_not_scan_if_controller_locked_up(h))
4125 return;
4126
a08a8471
SC		 4127 hpsa_update_scsi_devices(h, h->scsi_host->host_no);
4128
4129 spin_lock_irqsave(&h->scan_lock, flags);
4130 h->scan_finished = 1; /* mark scan as finished. */
4131 wake_up_all(&h->scan_wait_queue);
4132 spin_unlock_irqrestore(&h->scan_lock, flags);
4133}
4134
4135static int hpsa_scan_finished(struct Scsi_Host *sh,
4136 unsigned long elapsed_time)
4137{
4138 struct ctlr_info *h = shost_to_hba(sh);
4139 unsigned long flags;
4140 int finished;
4141
4142 spin_lock_irqsave(&h->scan_lock, flags);
4143 finished = h->scan_finished;
4144 spin_unlock_irqrestore(&h->scan_lock, flags);
4145 return finished;
4146}
4147
667e23d4
SC		 4148static int hpsa_change_queue_depth(struct scsi_device *sdev,
4149 int qdepth, int reason)
4150{
4151 struct ctlr_info *h = sdev_to_hba(sdev);
4152
4153 if (reason != SCSI_QDEPTH_DEFAULT)
4154 return -ENOTSUPP;
4155
4156 if (qdepth < 1)
4157 qdepth = 1;
4158 else
4159 if (qdepth > h->nr_cmds)
4160 qdepth = h->nr_cmds;
4161 scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth);
4162 return sdev->queue_depth;
4163}
4164
edd16368
SC		 4165static void hpsa_unregister_scsi(struct ctlr_info *h)
4166{
4167 /* we are being forcibly unloaded, and may not refuse. */
4168 scsi_remove_host(h->scsi_host);
4169 scsi_host_put(h->scsi_host);
4170 h->scsi_host = NULL;
4171}
4172
4173static int hpsa_register_scsi(struct ctlr_info *h)
4174{
b705690d
SC		 4175 struct Scsi_Host *sh;
4176 int error;
edd16368 4177
b705690d
SC		 4178 sh = scsi_host_alloc(&hpsa_driver_template, sizeof(h));
4179 if (sh == NULL)
4180 goto fail;
4181
4182 sh->io_port = 0;
4183 sh->n_io_port = 0;
4184 sh->this_id = -1;
4185 sh->max_channel = 3;
4186 sh->max_cmd_len = MAX_COMMAND_SIZE;
4187 sh->max_lun = HPSA_MAX_LUN;
4188 sh->max_id = HPSA_MAX_LUN;
4189 sh->can_queue = h->nr_cmds;
316b221a
SC		 4190 if (h->hba_mode_enabled)
4191 sh->cmd_per_lun = 7;
4192 else
4193 sh->cmd_per_lun = h->nr_cmds;
b705690d
SC		 4194 sh->sg_tablesize = h->maxsgentries;
4195 h->scsi_host = sh;
4196 sh->hostdata[0] = (unsigned long) h;
4197 sh->irq = h->intr[h->intr_mode];
4198 sh->unique_id = sh->irq;
4199 error = scsi_add_host(sh, &h->pdev->dev);
4200 if (error)
4201 goto fail_host_put;
4202 scsi_scan_host(sh);
4203 return 0;
4204
4205 fail_host_put:
4206 dev_err(&h->pdev->dev, "%s: scsi_add_host"
4207 " failed for controller %d\n", __func__, h->ctlr);
4208 scsi_host_put(sh);
4209 return error;
4210 fail:
4211 dev_err(&h->pdev->dev, "%s: scsi_host_alloc"
4212 " failed for controller %d\n", __func__, h->ctlr);
4213 return -ENOMEM;
edd16368
SC		 4214}
4215
4216static int wait_for_device_to_become_ready(struct ctlr_info *h,
4217 unsigned char lunaddr[])
4218{
8919358e 4219 int rc;
edd16368
SC		 4220 int count = 0;
4221 int waittime = 1; /* seconds */
4222 struct CommandList *c;
4223
4224 c = cmd_special_alloc(h);
4225 if (!c) {
4226 dev_warn(&h->pdev->dev, "out of memory in "
4227 "wait_for_device_to_become_ready.\n");
4228 return IO_ERROR;
4229 }
4230
4231 /* Send test unit ready until device ready, or give up. */
4232 while (count < HPSA_TUR_RETRY_LIMIT) {
4233
4234 /* Wait for a bit. do this first, because if we send
4235 * the TUR right away, the reset will just abort it.
4236 */
4237 msleep(1000 * waittime);
4238 count++;
8919358e 4239 rc = 0; /* Device ready. */
edd16368
SC		 4240
4241 /* Increase wait time with each try, up to a point. */
4242 if (waittime < HPSA_MAX_WAIT_INTERVAL_SECS)
4243 waittime = waittime * 2;
4244
a2dac136
SC		 4245 /* Send the Test Unit Ready, fill_cmd can't fail, no mapping */
4246 (void) fill_cmd(c, TEST_UNIT_READY, h,
4247 NULL, 0, 0, lunaddr, TYPE_CMD);
edd16368
SC		 4248 hpsa_scsi_do_simple_cmd_core(h, c);
4249 /* no unmap needed here because no data xfer. */
4250
4251 if (c->err_info->CommandStatus == CMD_SUCCESS)
4252 break;
4253
4254 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
4255 c->err_info->ScsiStatus == SAM_STAT_CHECK_CONDITION &&
4256 (c->err_info->SenseInfo[2] == NO_SENSE ||
4257 c->err_info->SenseInfo[2] == UNIT_ATTENTION))
4258 break;
4259
4260 dev_warn(&h->pdev->dev, "waiting %d secs "
4261 "for device to become ready.\n", waittime);
4262 rc = 1; /* device not ready. */
4263 }
4264
4265 if (rc)
4266 dev_warn(&h->pdev->dev, "giving up on device.\n");
4267 else
4268 dev_warn(&h->pdev->dev, "device is ready.\n");
4269
4270 cmd_special_free(h, c);
4271 return rc;
4272}
4273
4274/* Need at least one of these error handlers to keep ../scsi/hosts.c from
4275 * complaining. Doing a host- or bus-reset can't do anything good here.
4276 */
4277static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd)
4278{
4279 int rc;
4280 struct ctlr_info *h;
4281 struct hpsa_scsi_dev_t *dev;
4282
4283 /* find the controller to which the command to be aborted was sent */
4284 h = sdev_to_hba(scsicmd->device);
4285 if (h == NULL) /* paranoia */
4286 return FAILED;
edd16368
SC		 4287 dev = scsicmd->device->hostdata;
4288 if (!dev) {
4289 dev_err(&h->pdev->dev, "hpsa_eh_device_reset_handler: "
4290 "device lookup failed.\n");
4291 return FAILED;
4292 }
d416b0c7
SC		 4293 dev_warn(&h->pdev->dev, "resetting device %d:%d:%d:%d\n",
4294 h->scsi_host->host_no, dev->bus, dev->target, dev->lun);
edd16368 4295 /* send a reset to the SCSI LUN which the command was sent to */
bf711ac6 4296 rc = hpsa_send_reset(h, dev->scsi3addr, HPSA_RESET_TYPE_LUN);
edd16368
SC		 4297 if (rc == 0 && wait_for_device_to_become_ready(h, dev->scsi3addr) == 0)
4298 return SUCCESS;
4299
4300 dev_warn(&h->pdev->dev, "resetting device failed.\n");
4301 return FAILED;
4302}
4303
6cba3f19
SC		 4304static void swizzle_abort_tag(u8 *tag)
4305{
4306 u8 original_tag[8];
4307
4308 memcpy(original_tag, tag, 8);
4309 tag[0] = original_tag[3];
4310 tag[1] = original_tag[2];
4311 tag[2] = original_tag[1];
4312 tag[3] = original_tag[0];
4313 tag[4] = original_tag[7];
4314 tag[5] = original_tag[6];
4315 tag[6] = original_tag[5];
4316 tag[7] = original_tag[4];
4317}
4318
17eb87d2
ST		 4319static void hpsa_get_tag(struct ctlr_info *h,
4320 struct CommandList *c, u32 *taglower, u32 *tagupper)
4321{
4322 if (c->cmd_type == CMD_IOACCEL1) {
4323 struct io_accel1_cmd *cm1 = (struct io_accel1_cmd *)
4324 &h->ioaccel_cmd_pool[c->cmdindex];
4325 *tagupper = cm1->Tag.upper;
4326 *taglower = cm1->Tag.lower;
54b6e9e9
ST		 4327 return;
4328 }
4329 if (c->cmd_type == CMD_IOACCEL2) {
4330 struct io_accel2_cmd *cm2 = (struct io_accel2_cmd *)
4331 &h->ioaccel2_cmd_pool[c->cmdindex];
dd0e19f3
ST		 4332 /* upper tag not used in ioaccel2 mode */
4333 memset(tagupper, 0, sizeof(*tagupper));
4334 *taglower = cm2->Tag;
54b6e9e9 4335 return;
17eb87d2 4336 }
54b6e9e9
ST		 4337 *tagupper = c->Header.Tag.upper;
4338 *taglower = c->Header.Tag.lower;
17eb87d2
ST		 4339}
4340
54b6e9e9 4341
75167d2c 4342static int hpsa_send_abort(struct ctlr_info *h, unsigned char *scsi3addr,
6cba3f19 4343 struct CommandList *abort, int swizzle)
75167d2c
SC		 4344{
4345 int rc = IO_OK;
4346 struct CommandList *c;
4347 struct ErrorInfo *ei;
17eb87d2 4348 u32 tagupper, taglower;
75167d2c
SC		 4349
4350 c = cmd_special_alloc(h);
4351 if (c == NULL) { /* trouble... */
4352 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
4353 return -ENOMEM;
4354 }
4355
a2dac136
SC		 4356 /* fill_cmd can't fail here, no buffer to map */
4357 (void) fill_cmd(c, HPSA_ABORT_MSG, h, abort,
4358 0, 0, scsi3addr, TYPE_MSG);
6cba3f19
SC		 4359 if (swizzle)
4360 swizzle_abort_tag(&c->Request.CDB[4]);
75167d2c 4361 hpsa_scsi_do_simple_cmd_core(h, c);
17eb87d2 4362 hpsa_get_tag(h, abort, &taglower, &tagupper);
75167d2c 4363 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: do_simple_cmd_core completed.\n",
17eb87d2 4364 __func__, tagupper, taglower);
75167d2c
SC		 4365 /* no unmap needed here because no data xfer. */
4366
4367 ei = c->err_info;
4368 switch (ei->CommandStatus) {
4369 case CMD_SUCCESS:
4370 break;
4371 case CMD_UNABORTABLE: /* Very common, don't make noise. */
4372 rc = -1;
4373 break;
4374 default:
4375 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: interpreting error.\n",
17eb87d2 4376 __func__, tagupper, taglower);
d1e8beac 4377 hpsa_scsi_interpret_error(h, c);
75167d2c
SC		 4378 rc = -1;
4379 break;
4380 }
4381 cmd_special_free(h, c);
dd0e19f3
ST		 4382 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n",
4383 __func__, tagupper, taglower);
75167d2c
SC		 4384 return rc;
4385}
4386
4387/*
4388 * hpsa_find_cmd_in_queue
4389 *
4390 * Used to determine whether a command (find) is still present
4391 * in queue_head. Optionally excludes the last element of queue_head.
4392 *
4393 * This is used to avoid unnecessary aborts. Commands in h->reqQ have
4394 * not yet been submitted, and so can be aborted by the driver without
4395 * sending an abort to the hardware.
4396 *
4397 * Returns pointer to command if found in queue, NULL otherwise.
4398 */
4399static struct CommandList *hpsa_find_cmd_in_queue(struct ctlr_info *h,
4400 struct scsi_cmnd *find, struct list_head *queue_head)
4401{
4402 unsigned long flags;
4403 struct CommandList *c = NULL; /* ptr into cmpQ */
4404
4405 if (!find)
4406 return 0;
4407 spin_lock_irqsave(&h->lock, flags);
4408 list_for_each_entry(c, queue_head, list) {
4409 if (c->scsi_cmd == NULL) /* e.g.: passthru ioctl */
4410 continue;
4411 if (c->scsi_cmd == find) {
4412 spin_unlock_irqrestore(&h->lock, flags);
4413 return c;
4414 }
4415 }
4416 spin_unlock_irqrestore(&h->lock, flags);
4417 return NULL;
4418}
4419
6cba3f19
SC		 4420static struct CommandList *hpsa_find_cmd_in_queue_by_tag(struct ctlr_info *h,
4421 u8 *tag, struct list_head *queue_head)
4422{
4423 unsigned long flags;
4424 struct CommandList *c;
4425
4426 spin_lock_irqsave(&h->lock, flags);
4427 list_for_each_entry(c, queue_head, list) {
4428 if (memcmp(&c->Header.Tag, tag, 8) != 0)
4429 continue;
4430 spin_unlock_irqrestore(&h->lock, flags);
4431 return c;
4432 }
4433 spin_unlock_irqrestore(&h->lock, flags);
4434 return NULL;
4435}
4436
54b6e9e9
ST		 4437/* ioaccel2 path firmware cannot handle abort task requests.
4438 * Change abort requests to physical target reset, and send to the
4439 * address of the physical disk used for the ioaccel 2 command.
4440 * Return 0 on success (IO_OK)
4441 * -1 on failure
4442 */
4443
4444static int hpsa_send_reset_as_abort_ioaccel2(struct ctlr_info *h,
4445 unsigned char *scsi3addr, struct CommandList *abort)
4446{
4447 int rc = IO_OK;
4448 struct scsi_cmnd *scmd; /* scsi command within request being aborted */
4449 struct hpsa_scsi_dev_t *dev; /* device to which scsi cmd was sent */
4450 unsigned char phys_scsi3addr[8]; /* addr of phys disk with volume */
4451 unsigned char *psa = &phys_scsi3addr[0];
4452
4453 /* Get a pointer to the hpsa logical device. */
4454 scmd = (struct scsi_cmnd *) abort->scsi_cmd;
4455 dev = (struct hpsa_scsi_dev_t *)(scmd->device->hostdata);
4456 if (dev == NULL) {
4457 dev_warn(&h->pdev->dev,
4458 "Cannot abort: no device pointer for command.\n");
4459 return -1; /* not abortable */
4460 }
4461
2ba8bfc8
SC		 4462 if (h->raid_offload_debug > 0)
4463 dev_info(&h->pdev->dev,
4464 "Reset as abort: Abort requested on C%d:B%d:T%d:L%d scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4465 h->scsi_host->host_no, dev->bus, dev->target, dev->lun,
4466 scsi3addr[0], scsi3addr[1], scsi3addr[2], scsi3addr[3],
4467 scsi3addr[4], scsi3addr[5], scsi3addr[6], scsi3addr[7]);
4468
54b6e9e9
ST		 4469 if (!dev->offload_enabled) {
4470 dev_warn(&h->pdev->dev,
4471 "Can't abort: device is not operating in HP SSD Smart Path mode.\n");
4472 return -1; /* not abortable */
4473 }
4474
4475 /* Incoming scsi3addr is logical addr. We need physical disk addr. */
4476 if (!hpsa_get_pdisk_of_ioaccel2(h, abort, psa)) {
4477 dev_warn(&h->pdev->dev, "Can't abort: Failed lookup of physical address.\n");
4478 return -1; /* not abortable */
4479 }
4480
4481 /* send the reset */
2ba8bfc8
SC		 4482 if (h->raid_offload_debug > 0)
4483 dev_info(&h->pdev->dev,
4484 "Reset as abort: Resetting physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4485 psa[0], psa[1], psa[2], psa[3],
4486 psa[4], psa[5], psa[6], psa[7]);
54b6e9e9
ST		 4487 rc = hpsa_send_reset(h, psa, HPSA_RESET_TYPE_TARGET);
4488 if (rc != 0) {
4489 dev_warn(&h->pdev->dev,
4490 "Reset as abort: Failed on physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4491 psa[0], psa[1], psa[2], psa[3],
4492 psa[4], psa[5], psa[6], psa[7]);
4493 return rc; /* failed to reset */
4494 }
4495
4496 /* wait for device to recover */
4497 if (wait_for_device_to_become_ready(h, psa) != 0) {
4498 dev_warn(&h->pdev->dev,
4499 "Reset as abort: Failed: Device never recovered from reset: 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4500 psa[0], psa[1], psa[2], psa[3],
4501 psa[4], psa[5], psa[6], psa[7]);
4502 return -1; /* failed to recover */
4503 }
4504
4505 /* device recovered */
4506 dev_info(&h->pdev->dev,
4507 "Reset as abort: Device recovered from reset: scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4508 psa[0], psa[1], psa[2], psa[3],
4509 psa[4], psa[5], psa[6], psa[7]);
4510
4511 return rc; /* success */
4512}
4513
6cba3f19
SC		 4514/* Some Smart Arrays need the abort tag swizzled, and some don't. It's hard to
4515 * tell which kind we're dealing with, so we send the abort both ways. There
4516 * shouldn't be any collisions between swizzled and unswizzled tags due to the
4517 * way we construct our tags but we check anyway in case the assumptions which
4518 * make this true someday become false.
4519 */
4520static int hpsa_send_abort_both_ways(struct ctlr_info *h,
4521 unsigned char *scsi3addr, struct CommandList *abort)
4522{
4523 u8 swizzled_tag[8];
4524 struct CommandList *c;
4525 int rc = 0, rc2 = 0;
4526
54b6e9e9
ST		 4527 /* ioccelerator mode 2 commands should be aborted via the
4528 * accelerated path, since RAID path is unaware of these commands,
4529 * but underlying firmware can't handle abort TMF.
4530 * Change abort to physical device reset.
4531 */
4532 if (abort->cmd_type == CMD_IOACCEL2)
4533 return hpsa_send_reset_as_abort_ioaccel2(h, scsi3addr, abort);
4534
6cba3f19
SC		 4535 /* we do not expect to find the swizzled tag in our queue, but
4536 * check anyway just to be sure the assumptions which make this
4537 * the case haven't become wrong.
4538 */
4539 memcpy(swizzled_tag, &abort->Request.CDB[4], 8);
4540 swizzle_abort_tag(swizzled_tag);
4541 c = hpsa_find_cmd_in_queue_by_tag(h, swizzled_tag, &h->cmpQ);
4542 if (c != NULL) {
4543 dev_warn(&h->pdev->dev, "Unexpectedly found byte-swapped tag in completion queue.\n");
4544 return hpsa_send_abort(h, scsi3addr, abort, 0);
4545 }
4546 rc = hpsa_send_abort(h, scsi3addr, abort, 0);
4547
4548 /* if the command is still in our queue, we can't conclude that it was
4549 * aborted (it might have just completed normally) but in any case
4550 * we don't need to try to abort it another way.
4551 */
4552 c = hpsa_find_cmd_in_queue(h, abort->scsi_cmd, &h->cmpQ);
4553 if (c)
4554 rc2 = hpsa_send_abort(h, scsi3addr, abort, 1);
4555 return rc && rc2;
4556}
4557
75167d2c
SC		 4558/* Send an abort for the specified command.
4559 * If the device and controller support it,
4560 * send a task abort request.
4561 */
4562static int hpsa_eh_abort_handler(struct scsi_cmnd *sc)
4563{
4564
4565 int i, rc;
4566 struct ctlr_info *h;
4567 struct hpsa_scsi_dev_t *dev;
4568 struct CommandList *abort; /* pointer to command to be aborted */
4569 struct CommandList *found;
4570 struct scsi_cmnd *as; /* ptr to scsi cmd inside aborted command. */
4571 char msg[256]; /* For debug messaging. */
4572 int ml = 0;
17eb87d2 4573 u32 tagupper, taglower;
75167d2c
SC		 4574
4575 /* Find the controller of the command to be aborted */
4576 h = sdev_to_hba(sc->device);
4577 if (WARN(h == NULL,
4578 "ABORT REQUEST FAILED, Controller lookup failed.\n"))
4579 return FAILED;
4580
4581 /* Check that controller supports some kind of task abort */
4582 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags) &&
4583 !(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
4584 return FAILED;
4585
4586 memset(msg, 0, sizeof(msg));
4587 ml += sprintf(msg+ml, "ABORT REQUEST on C%d:B%d:T%d:L%d ",
4588 h->scsi_host->host_no, sc->device->channel,
4589 sc->device->id, sc->device->lun);
4590
4591 /* Find the device of the command to be aborted */
4592 dev = sc->device->hostdata;
4593 if (!dev) {
4594 dev_err(&h->pdev->dev, "%s FAILED, Device lookup failed.\n",
4595 msg);
4596 return FAILED;
4597 }
4598
4599 /* Get SCSI command to be aborted */
4600 abort = (struct CommandList *) sc->host_scribble;
4601 if (abort == NULL) {
4602 dev_err(&h->pdev->dev, "%s FAILED, Command to abort is NULL.\n",
4603 msg);
4604 return FAILED;
4605 }
17eb87d2
ST		 4606 hpsa_get_tag(h, abort, &taglower, &tagupper);
4607 ml += sprintf(msg+ml, "Tag:0x%08x:%08x ", tagupper, taglower);
75167d2c
SC		 4608 as = (struct scsi_cmnd *) abort->scsi_cmd;
4609 if (as != NULL)
4610 ml += sprintf(msg+ml, "Command:0x%x SN:0x%lx ",
4611 as->cmnd[0], as->serial_number);
4612 dev_dbg(&h->pdev->dev, "%s\n", msg);
4613 dev_warn(&h->pdev->dev, "Abort request on C%d:B%d:T%d:L%d\n",
4614 h->scsi_host->host_no, dev->bus, dev->target, dev->lun);
4615
4616 /* Search reqQ to See if command is queued but not submitted,
4617 * if so, complete the command with aborted status and remove
4618 * it from the reqQ.
4619 */
4620 found = hpsa_find_cmd_in_queue(h, sc, &h->reqQ);
4621 if (found) {
4622 found->err_info->CommandStatus = CMD_ABORTED;
4623 finish_cmd(found);
4624 dev_info(&h->pdev->dev, "%s Request SUCCEEDED (driver queue).\n",
4625 msg);
4626 return SUCCESS;
4627 }
4628
4629 /* not in reqQ, if also not in cmpQ, must have already completed */
4630 found = hpsa_find_cmd_in_queue(h, sc, &h->cmpQ);
4631 if (!found) {
d6ebd0f7 4632 dev_dbg(&h->pdev->dev, "%s Request SUCCEEDED (not known to driver).\n",
75167d2c
SC		 4633 msg);
4634 return SUCCESS;
4635 }
4636
4637 /*
4638 * Command is in flight, or possibly already completed
4639 * by the firmware (but not to the scsi mid layer) but we can't
4640 * distinguish which. Send the abort down.
4641 */
6cba3f19 4642 rc = hpsa_send_abort_both_ways(h, dev->scsi3addr, abort);
75167d2c
SC		 4643 if (rc != 0) {
4644 dev_dbg(&h->pdev->dev, "%s Request FAILED.\n", msg);
4645 dev_warn(&h->pdev->dev, "FAILED abort on device C%d:B%d:T%d:L%d\n",
4646 h->scsi_host->host_no,
4647 dev->bus, dev->target, dev->lun);
4648 return FAILED;
4649 }
4650 dev_info(&h->pdev->dev, "%s REQUEST SUCCEEDED.\n", msg);
4651
4652 /* If the abort(s) above completed and actually aborted the
4653 * command, then the command to be aborted should already be
4654 * completed. If not, wait around a bit more to see if they
4655 * manage to complete normally.
4656 */
4657#define ABORT_COMPLETE_WAIT_SECS 30
4658 for (i = 0; i < ABORT_COMPLETE_WAIT_SECS * 10; i++) {
4659 found = hpsa_find_cmd_in_queue(h, sc, &h->cmpQ);
4660 if (!found)
4661 return SUCCESS;
4662 msleep(100);
4663 }
4664 dev_warn(&h->pdev->dev, "%s FAILED. Aborted command has not completed after %d seconds.\n",
4665 msg, ABORT_COMPLETE_WAIT_SECS);
4666 return FAILED;
4667}
4668
4669
edd16368
SC		 4670/*
4671 * For operations that cannot sleep, a command block is allocated at init,
4672 * and managed by cmd_alloc() and cmd_free() using a simple bitmap to track
4673 * which ones are free or in use. Lock must be held when calling this.
4674 * cmd_free() is the complement.
4675 */
4676static struct CommandList *cmd_alloc(struct ctlr_info *h)
4677{
4678 struct CommandList *c;
4679 int i;
4680 union u64bit temp64;
4681 dma_addr_t cmd_dma_handle, err_dma_handle;
e16a33ad 4682 unsigned long flags;
edd16368 4683
e16a33ad 4684 spin_lock_irqsave(&h->lock, flags);
edd16368
SC		 4685 do {
4686 i = find_first_zero_bit(h->cmd_pool_bits, h->nr_cmds);
e16a33ad
MG		 4687 if (i == h->nr_cmds) {
4688 spin_unlock_irqrestore(&h->lock, flags);
edd16368 4689 return NULL;
e16a33ad 4690 }
edd16368
SC		 4691 } while (test_and_set_bit
4692 (i & (BITS_PER_LONG - 1),
4693 h->cmd_pool_bits + (i / BITS_PER_LONG)) != 0);
e16a33ad
MG		 4694 spin_unlock_irqrestore(&h->lock, flags);
4695
edd16368
SC		 4696 c = h->cmd_pool + i;
4697 memset(c, 0, sizeof(*c));
4698 cmd_dma_handle = h->cmd_pool_dhandle
4699 + i * sizeof(*c);
4700 c->err_info = h->errinfo_pool + i;
4701 memset(c->err_info, 0, sizeof(*c->err_info));
4702 err_dma_handle = h->errinfo_pool_dhandle
4703 + i * sizeof(*c->err_info);
edd16368
SC		 4704
4705 c->cmdindex = i;
4706
9e0fc764 4707 INIT_LIST_HEAD(&c->list);
01a02ffc
SC		 4708 c->busaddr = (u32) cmd_dma_handle;
4709 temp64.val = (u64) err_dma_handle;
edd16368
SC		 4710 c->ErrDesc.Addr.lower = temp64.val32.lower;
4711 c->ErrDesc.Addr.upper = temp64.val32.upper;
4712 c->ErrDesc.Len = sizeof(*c->err_info);
4713
4714 c->h = h;
4715 return c;
4716}
4717
4718/* For operations that can wait for kmalloc to possibly sleep,
4719 * this routine can be called. Lock need not be held to call
4720 * cmd_special_alloc. cmd_special_free() is the complement.
4721 */
4722static struct CommandList *cmd_special_alloc(struct ctlr_info *h)
4723{
4724 struct CommandList *c;
4725 union u64bit temp64;
4726 dma_addr_t cmd_dma_handle, err_dma_handle;
4727
4728 c = pci_alloc_consistent(h->pdev, sizeof(*c), &cmd_dma_handle);
4729 if (c == NULL)
4730 return NULL;
4731 memset(c, 0, sizeof(*c));
4732
e1f7de0c 4733 c->cmd_type = CMD_SCSI;
edd16368
SC		 4734 c->cmdindex = -1;
4735
4736 c->err_info = pci_alloc_consistent(h->pdev, sizeof(*c->err_info),
4737 &err_dma_handle);
4738
4739 if (c->err_info == NULL) {
4740 pci_free_consistent(h->pdev,
4741 sizeof(*c), c, cmd_dma_handle);
4742 return NULL;
4743 }
4744 memset(c->err_info, 0, sizeof(*c->err_info));
4745
9e0fc764 4746 INIT_LIST_HEAD(&c->list);
01a02ffc
SC		 4747 c->busaddr = (u32) cmd_dma_handle;
4748 temp64.val = (u64) err_dma_handle;
edd16368
SC		 4749 c->ErrDesc.Addr.lower = temp64.val32.lower;
4750 c->ErrDesc.Addr.upper = temp64.val32.upper;
4751 c->ErrDesc.Len = sizeof(*c->err_info);
4752
4753 c->h = h;
4754 return c;
4755}
4756
4757static void cmd_free(struct ctlr_info *h, struct CommandList *c)
4758{
4759 int i;
e16a33ad 4760 unsigned long flags;
edd16368
SC		 4761
4762 i = c - h->cmd_pool;
e16a33ad 4763 spin_lock_irqsave(&h->lock, flags);
edd16368
SC		 4764 clear_bit(i & (BITS_PER_LONG - 1),
4765 h->cmd_pool_bits + (i / BITS_PER_LONG));
e16a33ad 4766 spin_unlock_irqrestore(&h->lock, flags);
edd16368
SC		 4767}
4768
4769static void cmd_special_free(struct ctlr_info *h, struct CommandList *c)
4770{
4771 union u64bit temp64;
4772
4773 temp64.val32.lower = c->ErrDesc.Addr.lower;
4774 temp64.val32.upper = c->ErrDesc.Addr.upper;
4775 pci_free_consistent(h->pdev, sizeof(*c->err_info),
4776 c->err_info, (dma_addr_t) temp64.val);
4777 pci_free_consistent(h->pdev, sizeof(*c),
d896f3f3 4778 c, (dma_addr_t) (c->busaddr & DIRECT_LOOKUP_MASK));
edd16368
SC		 4779}
4780
4781#ifdef CONFIG_COMPAT
4782
edd16368
SC		 4783static int hpsa_ioctl32_passthru(struct scsi_device *dev, int cmd, void *arg)
4784{
4785 IOCTL32_Command_struct __user *arg32 =
4786 (IOCTL32_Command_struct __user *) arg;
4787 IOCTL_Command_struct arg64;
4788 IOCTL_Command_struct __user *p = compat_alloc_user_space(sizeof(arg64));
4789 int err;
4790 u32 cp;
4791
938abd84 4792 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 4793 err = 0;
4794 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
4795 sizeof(arg64.LUN_info));
4796 err |= copy_from_user(&arg64.Request, &arg32->Request,
4797 sizeof(arg64.Request));
4798 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
4799 sizeof(arg64.error_info));
4800 err |= get_user(arg64.buf_size, &arg32->buf_size);
4801 err |= get_user(cp, &arg32->buf);
4802 arg64.buf = compat_ptr(cp);
4803 err |= copy_to_user(p, &arg64, sizeof(arg64));
4804
4805 if (err)
4806 return -EFAULT;
4807
e39eeaed 4808 err = hpsa_ioctl(dev, CCISS_PASSTHRU, (void *)p);
edd16368
SC		 4809 if (err)
4810 return err;
4811 err |= copy_in_user(&arg32->error_info, &p->error_info,
4812 sizeof(arg32->error_info));
4813 if (err)
4814 return -EFAULT;
4815 return err;
4816}
4817
4818static int hpsa_ioctl32_big_passthru(struct scsi_device *dev,
4819 int cmd, void *arg)
4820{
4821 BIG_IOCTL32_Command_struct __user *arg32 =
4822 (BIG_IOCTL32_Command_struct __user *) arg;
4823 BIG_IOCTL_Command_struct arg64;
4824 BIG_IOCTL_Command_struct __user *p =
4825 compat_alloc_user_space(sizeof(arg64));
4826 int err;
4827 u32 cp;
4828
938abd84 4829 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 4830 err = 0;
4831 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
4832 sizeof(arg64.LUN_info));
4833 err |= copy_from_user(&arg64.Request, &arg32->Request,
4834 sizeof(arg64.Request));
4835 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
4836 sizeof(arg64.error_info));
4837 err |= get_user(arg64.buf_size, &arg32->buf_size);
4838 err |= get_user(arg64.malloc_size, &arg32->malloc_size);
4839 err |= get_user(cp, &arg32->buf);
4840 arg64.buf = compat_ptr(cp);
4841 err |= copy_to_user(p, &arg64, sizeof(arg64));
4842
4843 if (err)
4844 return -EFAULT;
4845
e39eeaed 4846 err = hpsa_ioctl(dev, CCISS_BIG_PASSTHRU, (void *)p);
edd16368
SC		 4847 if (err)
4848 return err;
4849 err |= copy_in_user(&arg32->error_info, &p->error_info,
4850 sizeof(arg32->error_info));
4851 if (err)
4852 return -EFAULT;
4853 return err;
4854}
71fe75a7
SC		 4855
4856static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void *arg)
4857{
4858 switch (cmd) {
4859 case CCISS_GETPCIINFO:
4860 case CCISS_GETINTINFO:
4861 case CCISS_SETINTINFO:
4862 case CCISS_GETNODENAME:
4863 case CCISS_SETNODENAME:
4864 case CCISS_GETHEARTBEAT:
4865 case CCISS_GETBUSTYPES:
4866 case CCISS_GETFIRMVER:
4867 case CCISS_GETDRIVVER:
4868 case CCISS_REVALIDVOLS:
4869 case CCISS_DEREGDISK:
4870 case CCISS_REGNEWDISK:
4871 case CCISS_REGNEWD:
4872 case CCISS_RESCANDISK:
4873 case CCISS_GETLUNINFO:
4874 return hpsa_ioctl(dev, cmd, arg);
4875
4876 case CCISS_PASSTHRU32:
4877 return hpsa_ioctl32_passthru(dev, cmd, arg);
4878 case CCISS_BIG_PASSTHRU32:
4879 return hpsa_ioctl32_big_passthru(dev, cmd, arg);
4880
4881 default:
4882 return -ENOIOCTLCMD;
4883 }
4884}
edd16368
SC		 4885#endif
4886
4887static int hpsa_getpciinfo_ioctl(struct ctlr_info *h, void __user *argp)
4888{
4889 struct hpsa_pci_info pciinfo;
4890
4891 if (!argp)
4892 return -EINVAL;
4893 pciinfo.domain = pci_domain_nr(h->pdev->bus);
4894 pciinfo.bus = h->pdev->bus->number;
4895 pciinfo.dev_fn = h->pdev->devfn;
4896 pciinfo.board_id = h->board_id;
4897 if (copy_to_user(argp, &pciinfo, sizeof(pciinfo)))
4898 return -EFAULT;
4899 return 0;
4900}
4901
4902static int hpsa_getdrivver_ioctl(struct ctlr_info *h, void __user *argp)
4903{
4904 DriverVer_type DriverVer;
4905 unsigned char vmaj, vmin, vsubmin;
4906 int rc;
4907
4908 rc = sscanf(HPSA_DRIVER_VERSION, "%hhu.%hhu.%hhu",
4909 &vmaj, &vmin, &vsubmin);
4910 if (rc != 3) {
4911 dev_info(&h->pdev->dev, "driver version string '%s' "
4912 "unrecognized.", HPSA_DRIVER_VERSION);
4913 vmaj = 0;
4914 vmin = 0;
4915 vsubmin = 0;
4916 }
4917 DriverVer = (vmaj << 16) | (vmin << 8) | vsubmin;
4918 if (!argp)
4919 return -EINVAL;
4920 if (copy_to_user(argp, &DriverVer, sizeof(DriverVer_type)))
4921 return -EFAULT;
4922 return 0;
4923}
4924
4925static int hpsa_passthru_ioctl(struct ctlr_info *h, void __user *argp)
4926{
4927 IOCTL_Command_struct iocommand;
4928 struct CommandList *c;
4929 char *buff = NULL;
4930 union u64bit temp64;
c1f63c8f 4931 int rc = 0;
edd16368
SC		 4932
4933 if (!argp)
4934 return -EINVAL;
4935 if (!capable(CAP_SYS_RAWIO))
4936 return -EPERM;
4937 if (copy_from_user(&iocommand, argp, sizeof(iocommand)))
4938 return -EFAULT;
4939 if ((iocommand.buf_size < 1) &&
4940 (iocommand.Request.Type.Direction != XFER_NONE)) {
4941 return -EINVAL;
4942 }
4943 if (iocommand.buf_size > 0) {
4944 buff = kmalloc(iocommand.buf_size, GFP_KERNEL);
4945 if (buff == NULL)
4946 return -EFAULT;
b03a7771
SC		 4947 if (iocommand.Request.Type.Direction == XFER_WRITE) {
4948 /* Copy the data into the buffer we created */
4949 if (copy_from_user(buff, iocommand.buf,
4950 iocommand.buf_size)) {
c1f63c8f
SC		 4951 rc = -EFAULT;
4952 goto out_kfree;
b03a7771
SC		 4953 }
4954 } else {
4955 memset(buff, 0, iocommand.buf_size);
edd16368 4956 }
b03a7771 4957 }
edd16368
SC		 4958 c = cmd_special_alloc(h);
4959 if (c == NULL) {
c1f63c8f
SC		 4960 rc = -ENOMEM;
4961 goto out_kfree;
edd16368
SC		 4962 }
4963 /* Fill in the command type */
4964 c->cmd_type = CMD_IOCTL_PEND;
4965 /* Fill in Command Header */
4966 c->Header.ReplyQueue = 0; /* unused in simple mode */
4967 if (iocommand.buf_size > 0) { /* buffer to fill */
4968 c->Header.SGList = 1;
4969 c->Header.SGTotal = 1;
4970 } else { /* no buffers to fill */
4971 c->Header.SGList = 0;
4972 c->Header.SGTotal = 0;
4973 }
4974 memcpy(&c->Header.LUN, &iocommand.LUN_info, sizeof(c->Header.LUN));
4975 /* use the kernel address the cmd block for tag */
4976 c->Header.Tag.lower = c->busaddr;
4977
4978 /* Fill in Request block */
4979 memcpy(&c->Request, &iocommand.Request,
4980 sizeof(c->Request));
4981
4982 /* Fill in the scatter gather information */
4983 if (iocommand.buf_size > 0) {
4984 temp64.val = pci_map_single(h->pdev, buff,
4985 iocommand.buf_size, PCI_DMA_BIDIRECTIONAL);
bcc48ffa
SC		 4986 if (dma_mapping_error(&h->pdev->dev, temp64.val)) {
4987 c->SG[0].Addr.lower = 0;
4988 c->SG[0].Addr.upper = 0;
4989 c->SG[0].Len = 0;
4990 rc = -ENOMEM;
4991 goto out;
4992 }
edd16368
SC		 4993 c->SG[0].Addr.lower = temp64.val32.lower;
4994 c->SG[0].Addr.upper = temp64.val32.upper;
4995 c->SG[0].Len = iocommand.buf_size;
e1d9cbfa 4996 c->SG[0].Ext = HPSA_SG_LAST; /* we are not chaining*/
edd16368 4997 }
a0c12413 4998 hpsa_scsi_do_simple_cmd_core_if_no_lockup(h, c);
c2dd32e0
SC		 4999 if (iocommand.buf_size > 0)
5000 hpsa_pci_unmap(h->pdev, c, 1, PCI_DMA_BIDIRECTIONAL);
edd16368
SC		 5001 check_ioctl_unit_attention(h, c);
5002
5003 /* Copy the error information out */
5004 memcpy(&iocommand.error_info, c->err_info,
5005 sizeof(iocommand.error_info));
5006 if (copy_to_user(argp, &iocommand, sizeof(iocommand))) {
c1f63c8f
SC		 5007 rc = -EFAULT;
5008 goto out;
edd16368 5009 }
b03a7771
SC		 5010 if (iocommand.Request.Type.Direction == XFER_READ &&
5011 iocommand.buf_size > 0) {
edd16368
SC		 5012 /* Copy the data out of the buffer we created */
5013 if (copy_to_user(iocommand.buf, buff, iocommand.buf_size)) {
c1f63c8f
SC		 5014 rc = -EFAULT;
5015 goto out;
edd16368
SC		 5016 }
5017 }
c1f63c8f 5018out:
edd16368 5019 cmd_special_free(h, c);
c1f63c8f
SC		 5020out_kfree:
5021 kfree(buff);
5022 return rc;
edd16368
SC		 5023}
5024
5025static int hpsa_big_passthru_ioctl(struct ctlr_info *h, void __user *argp)
5026{
5027 BIG_IOCTL_Command_struct *ioc;
5028 struct CommandList *c;
5029 unsigned char **buff = NULL;
5030 int *buff_size = NULL;
5031 union u64bit temp64;
5032 BYTE sg_used = 0;
5033 int status = 0;
5034 int i;
01a02ffc
SC		 5035 u32 left;
5036 u32 sz;
edd16368
SC		 5037 BYTE __user *data_ptr;
5038
5039 if (!argp)
5040 return -EINVAL;
5041 if (!capable(CAP_SYS_RAWIO))
5042 return -EPERM;
5043 ioc = (BIG_IOCTL_Command_struct *)
5044 kmalloc(sizeof(*ioc), GFP_KERNEL);
5045 if (!ioc) {
5046 status = -ENOMEM;
5047 goto cleanup1;
5048 }
5049 if (copy_from_user(ioc, argp, sizeof(*ioc))) {
5050 status = -EFAULT;
5051 goto cleanup1;
5052 }
5053 if ((ioc->buf_size < 1) &&
5054 (ioc->Request.Type.Direction != XFER_NONE)) {
5055 status = -EINVAL;
5056 goto cleanup1;
5057 }
5058 /* Check kmalloc limits using all SGs */
5059 if (ioc->malloc_size > MAX_KMALLOC_SIZE) {
5060 status = -EINVAL;
5061 goto cleanup1;
5062 }
d66ae08b 5063 if (ioc->buf_size > ioc->malloc_size * SG_ENTRIES_IN_CMD) {
edd16368
SC		 5064 status = -EINVAL;
5065 goto cleanup1;
5066 }
d66ae08b 5067 buff = kzalloc(SG_ENTRIES_IN_CMD * sizeof(char *), GFP_KERNEL);
edd16368
SC		 5068 if (!buff) {
5069 status = -ENOMEM;
5070 goto cleanup1;
5071 }
d66ae08b 5072 buff_size = kmalloc(SG_ENTRIES_IN_CMD * sizeof(int), GFP_KERNEL);
edd16368
SC		 5073 if (!buff_size) {
5074 status = -ENOMEM;
5075 goto cleanup1;
5076 }
5077 left = ioc->buf_size;
5078 data_ptr = ioc->buf;
5079 while (left) {
5080 sz = (left > ioc->malloc_size) ? ioc->malloc_size : left;
5081 buff_size[sg_used] = sz;
5082 buff[sg_used] = kmalloc(sz, GFP_KERNEL);
5083 if (buff[sg_used] == NULL) {
5084 status = -ENOMEM;
5085 goto cleanup1;
5086 }
5087 if (ioc->Request.Type.Direction == XFER_WRITE) {
5088 if (copy_from_user(buff[sg_used], data_ptr, sz)) {
5089 status = -ENOMEM;
5090 goto cleanup1;
5091 }
5092 } else
5093 memset(buff[sg_used], 0, sz);
5094 left -= sz;
5095 data_ptr += sz;
5096 sg_used++;
5097 }
5098 c = cmd_special_alloc(h);
5099 if (c == NULL) {
5100 status = -ENOMEM;
5101 goto cleanup1;
5102 }
5103 c->cmd_type = CMD_IOCTL_PEND;
5104 c->Header.ReplyQueue = 0;
b03a7771 5105 c->Header.SGList = c->Header.SGTotal = sg_used;
edd16368
SC		 5106 memcpy(&c->Header.LUN, &ioc->LUN_info, sizeof(c->Header.LUN));
5107 c->Header.Tag.lower = c->busaddr;
5108 memcpy(&c->Request, &ioc->Request, sizeof(c->Request));
5109 if (ioc->buf_size > 0) {
5110 int i;
5111 for (i = 0; i < sg_used; i++) {
5112 temp64.val = pci_map_single(h->pdev, buff[i],
5113 buff_size[i], PCI_DMA_BIDIRECTIONAL);
bcc48ffa
SC		 5114 if (dma_mapping_error(&h->pdev->dev, temp64.val)) {
5115 c->SG[i].Addr.lower = 0;
5116 c->SG[i].Addr.upper = 0;
5117 c->SG[i].Len = 0;
5118 hpsa_pci_unmap(h->pdev, c, i,
5119 PCI_DMA_BIDIRECTIONAL);
5120 status = -ENOMEM;
e2d4a1f6 5121 goto cleanup0;
bcc48ffa 5122 }
edd16368
SC		 5123 c->SG[i].Addr.lower = temp64.val32.lower;
5124 c->SG[i].Addr.upper = temp64.val32.upper;
5125 c->SG[i].Len = buff_size[i];
e1d9cbfa 5126 c->SG[i].Ext = i < sg_used - 1 ? 0 : HPSA_SG_LAST;
edd16368
SC		 5127 }
5128 }
a0c12413 5129 hpsa_scsi_do_simple_cmd_core_if_no_lockup(h, c);
b03a7771
SC		 5130 if (sg_used)
5131 hpsa_pci_unmap(h->pdev, c, sg_used, PCI_DMA_BIDIRECTIONAL);
edd16368
SC		 5132 check_ioctl_unit_attention(h, c);
5133 /* Copy the error information out */
5134 memcpy(&ioc->error_info, c->err_info, sizeof(ioc->error_info));
5135 if (copy_to_user(argp, ioc, sizeof(*ioc))) {
edd16368 5136 status = -EFAULT;
e2d4a1f6 5137 goto cleanup0;
edd16368 5138 }
b03a7771 5139 if (ioc->Request.Type.Direction == XFER_READ && ioc->buf_size > 0) {
edd16368
SC		 5140 /* Copy the data out of the buffer we created */
5141 BYTE __user *ptr = ioc->buf;
5142 for (i = 0; i < sg_used; i++) {
5143 if (copy_to_user(ptr, buff[i], buff_size[i])) {
edd16368 5144 status = -EFAULT;
e2d4a1f6 5145 goto cleanup0;
edd16368
SC		 5146 }
5147 ptr += buff_size[i];
5148 }
5149 }
edd16368 5150 status = 0;
e2d4a1f6
SC		 5151cleanup0:
5152 cmd_special_free(h, c);
edd16368
SC		 5153cleanup1:
5154 if (buff) {
5155 for (i = 0; i < sg_used; i++)
5156 kfree(buff[i]);
5157 kfree(buff);
5158 }
5159 kfree(buff_size);
5160 kfree(ioc);
5161 return status;
5162}
5163
5164static void check_ioctl_unit_attention(struct ctlr_info *h,
5165 struct CommandList *c)
5166{
5167 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
5168 c->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION)
5169 (void) check_for_unit_attention(h, c);
5170}
0390f0c0
SC		 5171
5172static int increment_passthru_count(struct ctlr_info *h)
5173{
5174 unsigned long flags;
5175
5176 spin_lock_irqsave(&h->passthru_count_lock, flags);
5177 if (h->passthru_count >= HPSA_MAX_CONCURRENT_PASSTHRUS) {
5178 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
5179 return -1;
5180 }
5181 h->passthru_count++;
5182 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
5183 return 0;
5184}
5185
5186static void decrement_passthru_count(struct ctlr_info *h)
5187{
5188 unsigned long flags;
5189
5190 spin_lock_irqsave(&h->passthru_count_lock, flags);
5191 if (h->passthru_count <= 0) {
5192 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
5193 /* not expecting to get here. */
5194 dev_warn(&h->pdev->dev, "Bug detected, passthru_count seems to be incorrect.\n");
5195 return;
5196 }
5197 h->passthru_count--;
5198 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
5199}
5200
edd16368
SC		 5201/*
5202 * ioctl
5203 */
5204static int hpsa_ioctl(struct scsi_device *dev, int cmd, void *arg)
5205{
5206 struct ctlr_info *h;
5207 void __user *argp = (void __user *)arg;
0390f0c0 5208 int rc;
edd16368
SC		 5209
5210 h = sdev_to_hba(dev);
5211
5212 switch (cmd) {
5213 case CCISS_DEREGDISK:
5214 case CCISS_REGNEWDISK:
5215 case CCISS_REGNEWD:
a08a8471 5216 hpsa_scan_start(h->scsi_host);
edd16368
SC		 5217 return 0;
5218 case CCISS_GETPCIINFO:
5219 return hpsa_getpciinfo_ioctl(h, argp);
5220 case CCISS_GETDRIVVER:
5221 return hpsa_getdrivver_ioctl(h, argp);
5222 case CCISS_PASSTHRU:
0390f0c0
SC		 5223 if (increment_passthru_count(h))
5224 return -EAGAIN;
5225 rc = hpsa_passthru_ioctl(h, argp);
5226 decrement_passthru_count(h);
5227 return rc;
edd16368 5228 case CCISS_BIG_PASSTHRU:
0390f0c0
SC		 5229 if (increment_passthru_count(h))
5230 return -EAGAIN;
5231 rc = hpsa_big_passthru_ioctl(h, argp);
5232 decrement_passthru_count(h);
5233 return rc;
edd16368
SC		 5234 default:
5235 return -ENOTTY;
5236 }
5237}
5238
6f039790
GKH		 5239static int hpsa_send_host_reset(struct ctlr_info *h, unsigned char *scsi3addr,
5240 u8 reset_type)
64670ac8
SC		 5241{
5242 struct CommandList *c;
5243
5244 c = cmd_alloc(h);
5245 if (!c)
5246 return -ENOMEM;
a2dac136
SC		 5247 /* fill_cmd can't fail here, no data buffer to map */
5248 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
64670ac8
SC		 5249 RAID_CTLR_LUNID, TYPE_MSG);
5250 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to target reset */
5251 c->waiting = NULL;
5252 enqueue_cmd_and_start_io(h, c);
5253 /* Don't wait for completion, the reset won't complete. Don't free
5254 * the command either. This is the last command we will send before
5255 * re-initializing everything, so it doesn't matter and won't leak.
5256 */
5257 return 0;
5258}
5259
a2dac136 5260static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
b7bb24eb 5261 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
edd16368
SC		 5262 int cmd_type)
5263{
5264 int pci_dir = XFER_NONE;
75167d2c 5265 struct CommandList *a; /* for commands to be aborted */
edd16368
SC		 5266
5267 c->cmd_type = CMD_IOCTL_PEND;
5268 c->Header.ReplyQueue = 0;
5269 if (buff != NULL && size > 0) {
5270 c->Header.SGList = 1;
5271 c->Header.SGTotal = 1;
5272 } else {
5273 c->Header.SGList = 0;
5274 c->Header.SGTotal = 0;
5275 }
5276 c->Header.Tag.lower = c->busaddr;
5277 memcpy(c->Header.LUN.LunAddrBytes, scsi3addr, 8);
5278
5279 c->Request.Type.Type = cmd_type;
5280 if (cmd_type == TYPE_CMD) {
5281 switch (cmd) {
5282 case HPSA_INQUIRY:
5283 /* are we trying to read a vital product page */
b7bb24eb 5284 if (page_code & VPD_PAGE) {
edd16368 5285 c->Request.CDB[1] = 0x01;
b7bb24eb 5286 c->Request.CDB[2] = (page_code & 0xff);
edd16368
SC		 5287 }
5288 c->Request.CDBLen = 6;
5289 c->Request.Type.Attribute = ATTR_SIMPLE;
5290 c->Request.Type.Direction = XFER_READ;
5291 c->Request.Timeout = 0;
5292 c->Request.CDB[0] = HPSA_INQUIRY;
5293 c->Request.CDB[4] = size & 0xFF;
5294 break;
5295 case HPSA_REPORT_LOG:
5296 case HPSA_REPORT_PHYS:
5297 /* Talking to controller so It's a physical command
5298 mode = 00 target = 0. Nothing to write.
5299 */
5300 c->Request.CDBLen = 12;
5301 c->Request.Type.Attribute = ATTR_SIMPLE;
5302 c->Request.Type.Direction = XFER_READ;
5303 c->Request.Timeout = 0;
5304 c->Request.CDB[0] = cmd;
5305 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
5306 c->Request.CDB[7] = (size >> 16) & 0xFF;
5307 c->Request.CDB[8] = (size >> 8) & 0xFF;
5308 c->Request.CDB[9] = size & 0xFF;
5309 break;
edd16368
SC		 5310 case HPSA_CACHE_FLUSH:
5311 c->Request.CDBLen = 12;
5312 c->Request.Type.Attribute = ATTR_SIMPLE;
5313 c->Request.Type.Direction = XFER_WRITE;
5314 c->Request.Timeout = 0;
5315 c->Request.CDB[0] = BMIC_WRITE;
5316 c->Request.CDB[6] = BMIC_CACHE_FLUSH;
bb158eab
SC		 5317 c->Request.CDB[7] = (size >> 8) & 0xFF;
5318 c->Request.CDB[8] = size & 0xFF;
edd16368
SC		 5319 break;
5320 case TEST_UNIT_READY:
5321 c->Request.CDBLen = 6;
5322 c->Request.Type.Attribute = ATTR_SIMPLE;
5323 c->Request.Type.Direction = XFER_NONE;
5324 c->Request.Timeout = 0;
5325 break;
283b4a9b
SC		 5326 case HPSA_GET_RAID_MAP:
5327 c->Request.CDBLen = 12;
5328 c->Request.Type.Attribute = ATTR_SIMPLE;
5329 c->Request.Type.Direction = XFER_READ;
5330 c->Request.Timeout = 0;
5331 c->Request.CDB[0] = HPSA_CISS_READ;
5332 c->Request.CDB[1] = cmd;
5333 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
5334 c->Request.CDB[7] = (size >> 16) & 0xFF;
5335 c->Request.CDB[8] = (size >> 8) & 0xFF;
5336 c->Request.CDB[9] = size & 0xFF;
5337 break;
316b221a
SC		 5338 case BMIC_SENSE_CONTROLLER_PARAMETERS:
5339 c->Request.CDBLen = 10;
5340 c->Request.Type.Attribute = ATTR_SIMPLE;
5341 c->Request.Type.Direction = XFER_READ;
5342 c->Request.Timeout = 0;
5343 c->Request.CDB[0] = BMIC_READ;
5344 c->Request.CDB[6] = BMIC_SENSE_CONTROLLER_PARAMETERS;
5345 c->Request.CDB[7] = (size >> 16) & 0xFF;
5346 c->Request.CDB[8] = (size >> 8) & 0xFF;
5347 break;
edd16368
SC		 5348 default:
5349 dev_warn(&h->pdev->dev, "unknown command 0x%c\n", cmd);
5350 BUG();
a2dac136 5351 return -1;
edd16368
SC		 5352 }
5353 } else if (cmd_type == TYPE_MSG) {
5354 switch (cmd) {
5355
5356 case HPSA_DEVICE_RESET_MSG:
5357 c->Request.CDBLen = 16;
5358 c->Request.Type.Type = 1; /* It is a MSG not a CMD */
5359 c->Request.Type.Attribute = ATTR_SIMPLE;
5360 c->Request.Type.Direction = XFER_NONE;
5361 c->Request.Timeout = 0; /* Don't time out */
64670ac8
SC		 5362 memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
5363 c->Request.CDB[0] = cmd;
21e89afd 5364 c->Request.CDB[1] = HPSA_RESET_TYPE_LUN;
edd16368
SC		 5365 /* If bytes 4-7 are zero, it means reset the */
5366 /* LunID device */
5367 c->Request.CDB[4] = 0x00;
5368 c->Request.CDB[5] = 0x00;
5369 c->Request.CDB[6] = 0x00;
5370 c->Request.CDB[7] = 0x00;
75167d2c
SC		 5371 break;
5372 case HPSA_ABORT_MSG:
5373 a = buff; /* point to command to be aborted */
5374 dev_dbg(&h->pdev->dev, "Abort Tag:0x%08x:%08x using request Tag:0x%08x:%08x\n",
5375 a->Header.Tag.upper, a->Header.Tag.lower,
5376 c->Header.Tag.upper, c->Header.Tag.lower);
5377 c->Request.CDBLen = 16;
5378 c->Request.Type.Type = TYPE_MSG;
5379 c->Request.Type.Attribute = ATTR_SIMPLE;
5380 c->Request.Type.Direction = XFER_WRITE;
5381 c->Request.Timeout = 0; /* Don't time out */
5382 c->Request.CDB[0] = HPSA_TASK_MANAGEMENT;
5383 c->Request.CDB[1] = HPSA_TMF_ABORT_TASK;
5384 c->Request.CDB[2] = 0x00; /* reserved */
5385 c->Request.CDB[3] = 0x00; /* reserved */
5386 /* Tag to abort goes in CDB[4]-CDB[11] */
5387 c->Request.CDB[4] = a->Header.Tag.lower & 0xFF;
5388 c->Request.CDB[5] = (a->Header.Tag.lower >> 8) & 0xFF;
5389 c->Request.CDB[6] = (a->Header.Tag.lower >> 16) & 0xFF;
5390 c->Request.CDB[7] = (a->Header.Tag.lower >> 24) & 0xFF;
5391 c->Request.CDB[8] = a->Header.Tag.upper & 0xFF;
5392 c->Request.CDB[9] = (a->Header.Tag.upper >> 8) & 0xFF;
5393 c->Request.CDB[10] = (a->Header.Tag.upper >> 16) & 0xFF;
5394 c->Request.CDB[11] = (a->Header.Tag.upper >> 24) & 0xFF;
5395 c->Request.CDB[12] = 0x00; /* reserved */
5396 c->Request.CDB[13] = 0x00; /* reserved */
5397 c->Request.CDB[14] = 0x00; /* reserved */
5398 c->Request.CDB[15] = 0x00; /* reserved */
edd16368 5399 break;
edd16368
SC		 5400 default:
5401 dev_warn(&h->pdev->dev, "unknown message type %d\n",
5402 cmd);
5403 BUG();
5404 }
5405 } else {
5406 dev_warn(&h->pdev->dev, "unknown command type %d\n", cmd_type);
5407 BUG();
5408 }
5409
5410 switch (c->Request.Type.Direction) {
5411 case XFER_READ:
5412 pci_dir = PCI_DMA_FROMDEVICE;
5413 break;
5414 case XFER_WRITE:
5415 pci_dir = PCI_DMA_TODEVICE;
5416 break;
5417 case XFER_NONE:
5418 pci_dir = PCI_DMA_NONE;
5419 break;
5420 default:
5421 pci_dir = PCI_DMA_BIDIRECTIONAL;
5422 }
a2dac136
SC		 5423 if (hpsa_map_one(h->pdev, c, buff, size, pci_dir))
5424 return -1;
5425 return 0;
edd16368
SC		 5426}
5427
5428/*
5429 * Map (physical) PCI mem into (virtual) kernel space
5430 */
5431static void __iomem *remap_pci_mem(ulong base, ulong size)
5432{
5433 ulong page_base = ((ulong) base) & PAGE_MASK;
5434 ulong page_offs = ((ulong) base) - page_base;
088ba34c
SC		 5435 void __iomem *page_remapped = ioremap_nocache(page_base,
5436 page_offs + size);
edd16368
SC		 5437
5438 return page_remapped ? (page_remapped + page_offs) : NULL;
5439}
5440
5441/* Takes cmds off the submission queue and sends them to the hardware,
5442 * then puts them on the queue of cmds waiting for completion.
5443 */
5444static void start_io(struct ctlr_info *h)
5445{
5446 struct CommandList *c;
e16a33ad 5447 unsigned long flags;
edd16368 5448
e16a33ad 5449 spin_lock_irqsave(&h->lock, flags);
9e0fc764
SC		 5450 while (!list_empty(&h->reqQ)) {
5451 c = list_entry(h->reqQ.next, struct CommandList, list);
edd16368
SC		 5452 /* can't do anything if fifo is full */
5453 if ((h->access.fifo_full(h))) {
396883e2 5454 h->fifo_recently_full = 1;
edd16368
SC		 5455 dev_warn(&h->pdev->dev, "fifo full\n");
5456 break;
5457 }
396883e2 5458 h->fifo_recently_full = 0;
edd16368
SC		 5459
5460 /* Get the first entry from the Request Q */
5461 removeQ(c);
5462 h->Qdepth--;
5463
edd16368
SC		 5464 /* Put job onto the completed Q */
5465 addQ(&h->cmpQ, c);
e16a33ad
MG		 5466
5467 /* Must increment commands_outstanding before unlocking
5468 * and submitting to avoid race checking for fifo full
5469 * condition.
5470 */
5471 h->commands_outstanding++;
5472 if (h->commands_outstanding > h->max_outstanding)
5473 h->max_outstanding = h->commands_outstanding;
5474
5475 /* Tell the controller execute command */
5476 spin_unlock_irqrestore(&h->lock, flags);
5477 h->access.submit_command(h, c);
5478 spin_lock_irqsave(&h->lock, flags);
edd16368 5479 }
e16a33ad 5480 spin_unlock_irqrestore(&h->lock, flags);
edd16368
SC		 5481}
5482
254f796b 5483static inline unsigned long get_next_completion(struct ctlr_info *h, u8 q)
edd16368 5484{
254f796b 5485 return h->access.command_completed(h, q);
edd16368
SC		 5486}
5487
900c5440 5488static inline bool interrupt_pending(struct ctlr_info *h)
edd16368
SC		 5489{
5490 return h->access.intr_pending(h);
5491}
5492
5493static inline long interrupt_not_for_us(struct ctlr_info *h)
5494{
10f66018
SC		 5495 return (h->access.intr_pending(h) == 0) ||
5496 (h->interrupts_enabled == 0);
edd16368
SC		 5497}
5498
01a02ffc
SC		 5499static inline int bad_tag(struct ctlr_info *h, u32 tag_index,
5500 u32 raw_tag)
edd16368
SC		 5501{
5502 if (unlikely(tag_index >= h->nr_cmds)) {
5503 dev_warn(&h->pdev->dev, "bad tag 0x%08x ignored.\n", raw_tag);
5504 return 1;
5505 }
5506 return 0;
5507}
5508
5a3d16f5 5509static inline void finish_cmd(struct CommandList *c)
edd16368 5510{
e16a33ad 5511 unsigned long flags;
396883e2
SC		 5512 int io_may_be_stalled = 0;
5513 struct ctlr_info *h = c->h;
e16a33ad 5514
396883e2 5515 spin_lock_irqsave(&h->lock, flags);
edd16368 5516 removeQ(c);
396883e2
SC		 5517
5518 /*
5519 * Check for possibly stalled i/o.
5520 *
5521 * If a fifo_full condition is encountered, requests will back up
5522 * in h->reqQ. This queue is only emptied out by start_io which is
5523 * only called when a new i/o request comes in. If no i/o's are
5524 * forthcoming, the i/o's in h->reqQ can get stuck. So we call
5525 * start_io from here if we detect such a danger.
5526 *
5527 * Normally, we shouldn't hit this case, but pounding on the
5528 * CCISS_PASSTHRU ioctl can provoke it. Only call start_io if
5529 * commands_outstanding is low. We want to avoid calling
5530 * start_io from in here as much as possible, and esp. don't
5531 * want to get in a cycle where we call start_io every time
5532 * through here.
5533 */
5534 if (unlikely(h->fifo_recently_full) &&
5535 h->commands_outstanding < 5)
5536 io_may_be_stalled = 1;
5537
5538 spin_unlock_irqrestore(&h->lock, flags);
5539
e85c5974 5540 dial_up_lockup_detection_on_fw_flash_complete(c->h, c);
c349775e
ST		 5541 if (likely(c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_SCSI
5542 || c->cmd_type == CMD_IOACCEL2))
1fb011fb 5543 complete_scsi_command(c);
edd16368
SC		 5544 else if (c->cmd_type == CMD_IOCTL_PEND)
5545 complete(c->waiting);
396883e2
SC		 5546 if (unlikely(io_may_be_stalled))
5547 start_io(h);
edd16368
SC		 5548}
5549
a104c99f
SC		 5550static inline u32 hpsa_tag_contains_index(u32 tag)
5551{
a104c99f
SC		 5552 return tag & DIRECT_LOOKUP_BIT;
5553}
5554
5555static inline u32 hpsa_tag_to_index(u32 tag)
5556{
a104c99f
SC		 5557 return tag >> DIRECT_LOOKUP_SHIFT;
5558}
5559
a9a3a273
SC		 5560
5561static inline u32 hpsa_tag_discard_error_bits(struct ctlr_info *h, u32 tag)
a104c99f 5562{
a9a3a273
SC		 5563#define HPSA_PERF_ERROR_BITS ((1 << DIRECT_LOOKUP_SHIFT) - 1)
5564#define HPSA_SIMPLE_ERROR_BITS 0x03
960a30e7 5565 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
a9a3a273
SC		 5566 return tag & ~HPSA_SIMPLE_ERROR_BITS;
5567 return tag & ~HPSA_PERF_ERROR_BITS;
a104c99f
SC		 5568}
5569
303932fd 5570/* process completion of an indexed ("direct lookup") command */
1d94f94d 5571static inline void process_indexed_cmd(struct ctlr_info *h,
303932fd
DB		 5572 u32 raw_tag)
5573{
5574 u32 tag_index;
5575 struct CommandList *c;
5576
5577 tag_index = hpsa_tag_to_index(raw_tag);
1d94f94d
SC		 5578 if (!bad_tag(h, tag_index, raw_tag)) {
5579 c = h->cmd_pool + tag_index;
5580 finish_cmd(c);
5581 }
303932fd
DB		 5582}
5583
5584/* process completion of a non-indexed command */
1d94f94d 5585static inline void process_nonindexed_cmd(struct ctlr_info *h,
303932fd
DB		 5586 u32 raw_tag)
5587{
5588 u32 tag;
5589 struct CommandList *c = NULL;
e16a33ad 5590 unsigned long flags;
303932fd 5591
a9a3a273 5592 tag = hpsa_tag_discard_error_bits(h, raw_tag);
e16a33ad 5593 spin_lock_irqsave(&h->lock, flags);
9e0fc764 5594 list_for_each_entry(c, &h->cmpQ, list) {
303932fd 5595 if ((c->busaddr & 0xFFFFFFE0) == (tag & 0xFFFFFFE0)) {
e16a33ad 5596 spin_unlock_irqrestore(&h->lock, flags);
5a3d16f5 5597 finish_cmd(c);
1d94f94d 5598 return;
303932fd
DB		 5599 }
5600 }
e16a33ad 5601 spin_unlock_irqrestore(&h->lock, flags);
303932fd 5602 bad_tag(h, h->nr_cmds + 1, raw_tag);
303932fd
DB		 5603}
5604
64670ac8
SC		 5605/* Some controllers, like p400, will give us one interrupt
5606 * after a soft reset, even if we turned interrupts off.
5607 * Only need to check for this in the hpsa_xxx_discard_completions
5608 * functions.
5609 */
5610static int ignore_bogus_interrupt(struct ctlr_info *h)
5611{
5612 if (likely(!reset_devices))
5613 return 0;
5614
5615 if (likely(h->interrupts_enabled))
5616 return 0;
5617
5618 dev_info(&h->pdev->dev, "Received interrupt while interrupts disabled "
5619 "(known firmware bug.) Ignoring.\n");
5620
5621 return 1;
5622}
5623
254f796b
MG		 5624/*
5625 * Convert &h->q[x] (passed to interrupt handlers) back to h.
5626 * Relies on (h-q[x] == x) being true for x such that
5627 * 0 <= x < MAX_REPLY_QUEUES.
5628 */
5629static struct ctlr_info *queue_to_hba(u8 *queue)
64670ac8 5630{
254f796b
MG		 5631 return container_of((queue - *queue), struct ctlr_info, q[0]);
5632}
5633
5634static irqreturn_t hpsa_intx_discard_completions(int irq, void *queue)
5635{
5636 struct ctlr_info *h = queue_to_hba(queue);
5637 u8 q = *(u8 *) queue;
64670ac8
SC		 5638 u32 raw_tag;
5639
5640 if (ignore_bogus_interrupt(h))
5641 return IRQ_NONE;
5642
5643 if (interrupt_not_for_us(h))
5644 return IRQ_NONE;
a0c12413 5645 h->last_intr_timestamp = get_jiffies_64();
64670ac8 5646 while (interrupt_pending(h)) {
254f796b 5647 raw_tag = get_next_completion(h, q);
64670ac8 5648 while (raw_tag != FIFO_EMPTY)
254f796b 5649 raw_tag = next_command(h, q);
64670ac8 5650 }
64670ac8
SC		 5651 return IRQ_HANDLED;
5652}
5653
254f796b 5654static irqreturn_t hpsa_msix_discard_completions(int irq, void *queue)
64670ac8 5655{
254f796b 5656 struct ctlr_info *h = queue_to_hba(queue);
64670ac8 5657 u32 raw_tag;
254f796b 5658 u8 q = *(u8 *) queue;
64670ac8
SC		 5659
5660 if (ignore_bogus_interrupt(h))
5661 return IRQ_NONE;
5662
a0c12413 5663 h->last_intr_timestamp = get_jiffies_64();
254f796b 5664 raw_tag = get_next_completion(h, q);
64670ac8 5665 while (raw_tag != FIFO_EMPTY)
254f796b 5666 raw_tag = next_command(h, q);
64670ac8
SC		 5667 return IRQ_HANDLED;
5668}
5669
254f796b 5670static irqreturn_t do_hpsa_intr_intx(int irq, void *queue)
edd16368 5671{
254f796b 5672 struct ctlr_info *h = queue_to_hba((u8 *) queue);
303932fd 5673 u32 raw_tag;
254f796b 5674 u8 q = *(u8 *) queue;
edd16368
SC		 5675
5676 if (interrupt_not_for_us(h))
5677 return IRQ_NONE;
a0c12413 5678 h->last_intr_timestamp = get_jiffies_64();
10f66018 5679 while (interrupt_pending(h)) {
254f796b 5680 raw_tag = get_next_completion(h, q);
10f66018 5681 while (raw_tag != FIFO_EMPTY) {
1d94f94d
SC		 5682 if (likely(hpsa_tag_contains_index(raw_tag)))
5683 process_indexed_cmd(h, raw_tag);
10f66018 5684 else
1d94f94d 5685 process_nonindexed_cmd(h, raw_tag);
254f796b 5686 raw_tag = next_command(h, q);
10f66018
SC		 5687 }
5688 }
10f66018
SC		 5689 return IRQ_HANDLED;
5690}
5691
254f796b 5692static irqreturn_t do_hpsa_intr_msi(int irq, void *queue)
10f66018 5693{
254f796b 5694 struct ctlr_info *h = queue_to_hba(queue);
10f66018 5695 u32 raw_tag;
254f796b 5696 u8 q = *(u8 *) queue;
10f66018 5697
a0c12413 5698 h->last_intr_timestamp = get_jiffies_64();
254f796b 5699 raw_tag = get_next_completion(h, q);
303932fd 5700 while (raw_tag != FIFO_EMPTY) {
1d94f94d
SC		 5701 if (likely(hpsa_tag_contains_index(raw_tag)))
5702 process_indexed_cmd(h, raw_tag);
303932fd 5703 else
1d94f94d 5704 process_nonindexed_cmd(h, raw_tag);
254f796b 5705 raw_tag = next_command(h, q);
edd16368 5706 }
edd16368
SC		 5707 return IRQ_HANDLED;
5708}
5709
a9a3a273
SC		 5710/* Send a message CDB to the firmware. Careful, this only works
5711 * in simple mode, not performant mode due to the tag lookup.
5712 * We only ever use this immediately after a controller reset.
5713 */
6f039790
GKH		 5714static int hpsa_message(struct pci_dev *pdev, unsigned char opcode,
5715 unsigned char type)
edd16368
SC		 5716{
5717 struct Command {
5718 struct CommandListHeader CommandHeader;
5719 struct RequestBlock Request;
5720 struct ErrDescriptor ErrorDescriptor;
5721 };
5722 struct Command *cmd;
5723 static const size_t cmd_sz = sizeof(*cmd) +
5724 sizeof(cmd->ErrorDescriptor);
5725 dma_addr_t paddr64;
5726 uint32_t paddr32, tag;
5727 void __iomem *vaddr;
5728 int i, err;
5729
5730 vaddr = pci_ioremap_bar(pdev, 0);
5731 if (vaddr == NULL)
5732 return -ENOMEM;
5733
5734 /* The Inbound Post Queue only accepts 32-bit physical addresses for the
5735 * CCISS commands, so they must be allocated from the lower 4GiB of
5736 * memory.
5737 */
5738 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
5739 if (err) {
5740 iounmap(vaddr);
5741 return -ENOMEM;
5742 }
5743
5744 cmd = pci_alloc_consistent(pdev, cmd_sz, &paddr64);
5745 if (cmd == NULL) {
5746 iounmap(vaddr);
5747 return -ENOMEM;
5748 }
5749
5750 /* This must fit, because of the 32-bit consistent DMA mask. Also,
5751 * although there's no guarantee, we assume that the address is at
5752 * least 4-byte aligned (most likely, it's page-aligned).
5753 */
5754 paddr32 = paddr64;
5755
5756 cmd->CommandHeader.ReplyQueue = 0;
5757 cmd->CommandHeader.SGList = 0;
5758 cmd->CommandHeader.SGTotal = 0;
5759 cmd->CommandHeader.Tag.lower = paddr32;
5760 cmd->CommandHeader.Tag.upper = 0;
5761 memset(&cmd->CommandHeader.LUN.LunAddrBytes, 0, 8);
5762
5763 cmd->Request.CDBLen = 16;
5764 cmd->Request.Type.Type = TYPE_MSG;
5765 cmd->Request.Type.Attribute = ATTR_HEADOFQUEUE;
5766 cmd->Request.Type.Direction = XFER_NONE;
5767 cmd->Request.Timeout = 0; /* Don't time out */
5768 cmd->Request.CDB[0] = opcode;
5769 cmd->Request.CDB[1] = type;
5770 memset(&cmd->Request.CDB[2], 0, 14); /* rest of the CDB is reserved */
5771 cmd->ErrorDescriptor.Addr.lower = paddr32 + sizeof(*cmd);
5772 cmd->ErrorDescriptor.Addr.upper = 0;
5773 cmd->ErrorDescriptor.Len = sizeof(struct ErrorInfo);
5774
5775 writel(paddr32, vaddr + SA5_REQUEST_PORT_OFFSET);
5776
5777 for (i = 0; i < HPSA_MSG_SEND_RETRY_LIMIT; i++) {
5778 tag = readl(vaddr + SA5_REPLY_PORT_OFFSET);
a9a3a273 5779 if ((tag & ~HPSA_SIMPLE_ERROR_BITS) == paddr32)
edd16368
SC		 5780 break;
5781 msleep(HPSA_MSG_SEND_RETRY_INTERVAL_MSECS);
5782 }
5783
5784 iounmap(vaddr);
5785
5786 /* we leak the DMA buffer here ... no choice since the controller could
5787 * still complete the command.
5788 */
5789 if (i == HPSA_MSG_SEND_RETRY_LIMIT) {
5790 dev_err(&pdev->dev, "controller message %02x:%02x timed out\n",
5791 opcode, type);
5792 return -ETIMEDOUT;
5793 }
5794
5795 pci_free_consistent(pdev, cmd_sz, cmd, paddr64);
5796
5797 if (tag & HPSA_ERROR_BIT) {
5798 dev_err(&pdev->dev, "controller message %02x:%02x failed\n",
5799 opcode, type);
5800 return -EIO;
5801 }
5802
5803 dev_info(&pdev->dev, "controller message %02x:%02x succeeded\n",
5804 opcode, type);
5805 return 0;
5806}
5807
edd16368
SC		 5808#define hpsa_noop(p) hpsa_message(p, 3, 0)
5809
1df8552a 5810static int hpsa_controller_hard_reset(struct pci_dev *pdev,
cf0b08d0 5811 void * __iomem vaddr, u32 use_doorbell)
1df8552a
SC		 5812{
5813 u16 pmcsr;
5814 int pos;
5815
5816 if (use_doorbell) {
5817 /* For everything after the P600, the PCI power state method
5818 * of resetting the controller doesn't work, so we have this
5819 * other way using the doorbell register.
5820 */
5821 dev_info(&pdev->dev, "using doorbell to reset controller\n");
cf0b08d0 5822 writel(use_doorbell, vaddr + SA5_DOORBELL);
85009239
SC		 5823
5824 /* PMC hardware guys tell us we need a 5 second delay after
5825 * doorbell reset and before any attempt to talk to the board
5826 * at all to ensure that this actually works and doesn't fall
5827 * over in some weird corner cases.
5828 */
5829 msleep(5000);
1df8552a
SC		 5830 } else { /* Try to do it the PCI power state way */
5831
5832 /* Quoting from the Open CISS Specification: "The Power
5833 * Management Control/Status Register (CSR) controls the power
5834 * state of the device. The normal operating state is D0,
5835 * CSR=00h. The software off state is D3, CSR=03h. To reset
5836 * the controller, place the interface device in D3 then to D0,
5837 * this causes a secondary PCI reset which will reset the
5838 * controller." */
5839
5840 pos = pci_find_capability(pdev, PCI_CAP_ID_PM);
5841 if (pos == 0) {
5842 dev_err(&pdev->dev,
5843 "hpsa_reset_controller: "
5844 "PCI PM not supported\n");
5845 return -ENODEV;
5846 }
5847 dev_info(&pdev->dev, "using PCI PM to reset controller\n");
5848 /* enter the D3hot power management state */
5849 pci_read_config_word(pdev, pos + PCI_PM_CTRL, &pmcsr);
5850 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
5851 pmcsr |= PCI_D3hot;
5852 pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr);
5853
5854 msleep(500);
5855
5856 /* enter the D0 power management state */
5857 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
5858 pmcsr |= PCI_D0;
5859 pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr);
c4853efe
MM		 5860
5861 /*
5862 * The P600 requires a small delay when changing states.
5863 * Otherwise we may think the board did not reset and we bail.
5864 * This for kdump only and is particular to the P600.
5865 */
5866 msleep(500);
1df8552a
SC		 5867 }
5868 return 0;
5869}
5870
6f039790 5871static void init_driver_version(char *driver_version, int len)
580ada3c
SC		 5872{
5873 memset(driver_version, 0, len);
f79cfec6 5874 strncpy(driver_version, HPSA " " HPSA_DRIVER_VERSION, len - 1);
580ada3c
SC		 5875}
5876
6f039790 5877static int write_driver_ver_to_cfgtable(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 5878{
5879 char *driver_version;
5880 int i, size = sizeof(cfgtable->driver_version);
5881
5882 driver_version = kmalloc(size, GFP_KERNEL);
5883 if (!driver_version)
5884 return -ENOMEM;
5885
5886 init_driver_version(driver_version, size);
5887 for (i = 0; i < size; i++)
5888 writeb(driver_version[i], &cfgtable->driver_version[i]);
5889 kfree(driver_version);
5890 return 0;
5891}
5892
6f039790
GKH		 5893static void read_driver_ver_from_cfgtable(struct CfgTable __iomem *cfgtable,
5894 unsigned char *driver_ver)
580ada3c
SC		 5895{
5896 int i;
5897
5898 for (i = 0; i < sizeof(cfgtable->driver_version); i++)
5899 driver_ver[i] = readb(&cfgtable->driver_version[i]);
5900}
5901
6f039790 5902static int controller_reset_failed(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 5903{
5904
5905 char *driver_ver, *old_driver_ver;
5906 int rc, size = sizeof(cfgtable->driver_version);
5907
5908 old_driver_ver = kmalloc(2 * size, GFP_KERNEL);
5909 if (!old_driver_ver)
5910 return -ENOMEM;
5911 driver_ver = old_driver_ver + size;
5912
5913 /* After a reset, the 32 bytes of "driver version" in the cfgtable
5914 * should have been changed, otherwise we know the reset failed.
5915 */
5916 init_driver_version(old_driver_ver, size);
5917 read_driver_ver_from_cfgtable(cfgtable, driver_ver);
5918 rc = !memcmp(driver_ver, old_driver_ver, size);
5919 kfree(old_driver_ver);
5920 return rc;
5921}
edd16368 5922/* This does a hard reset of the controller using PCI power management
1df8552a 5923 * states or the using the doorbell register.
edd16368 5924 */
6f039790 5925static int hpsa_kdump_hard_reset_controller(struct pci_dev *pdev)
edd16368 5926{
1df8552a
SC		 5927 u64 cfg_offset;
5928 u32 cfg_base_addr;
5929 u64 cfg_base_addr_index;
5930 void __iomem *vaddr;
5931 unsigned long paddr;
580ada3c 5932 u32 misc_fw_support;
270d05de 5933 int rc;
1df8552a 5934 struct CfgTable __iomem *cfgtable;
cf0b08d0 5935 u32 use_doorbell;
18867659 5936 u32 board_id;
270d05de 5937 u16 command_register;
edd16368 5938
1df8552a
SC		 5939 /* For controllers as old as the P600, this is very nearly
5940 * the same thing as
edd16368
SC		 5941 *
5942 * pci_save_state(pci_dev);
5943 * pci_set_power_state(pci_dev, PCI_D3hot);
5944 * pci_set_power_state(pci_dev, PCI_D0);
5945 * pci_restore_state(pci_dev);
5946 *
1df8552a
SC		 5947 * For controllers newer than the P600, the pci power state
5948 * method of resetting doesn't work so we have another way
5949 * using the doorbell register.
edd16368 5950 */
18867659 5951
25c1e56a 5952 rc = hpsa_lookup_board_id(pdev, &board_id);
46380786 5953 if (rc < 0 || !ctlr_is_resettable(board_id)) {
25c1e56a
SC		 5954 dev_warn(&pdev->dev, "Not resetting device.\n");
5955 return -ENODEV;
5956 }
46380786
SC		 5957
5958 /* if controller is soft- but not hard resettable... */
5959 if (!ctlr_is_hard_resettable(board_id))
5960 return -ENOTSUPP; /* try soft reset later. */
18867659 5961
270d05de
SC		 5962 /* Save the PCI command register */
5963 pci_read_config_word(pdev, 4, &command_register);
5964 /* Turn the board off. This is so that later pci_restore_state()
5965 * won't turn the board on before the rest of config space is ready.
5966 */
5967 pci_disable_device(pdev);
5968 pci_save_state(pdev);
edd16368 5969
1df8552a
SC		 5970 /* find the first memory BAR, so we can find the cfg table */
5971 rc = hpsa_pci_find_memory_BAR(pdev, &paddr);
5972 if (rc)
5973 return rc;
5974 vaddr = remap_pci_mem(paddr, 0x250);
5975 if (!vaddr)
5976 return -ENOMEM;
edd16368 5977
1df8552a
SC		 5978 /* find cfgtable in order to check if reset via doorbell is supported */
5979 rc = hpsa_find_cfg_addrs(pdev, vaddr, &cfg_base_addr,
5980 &cfg_base_addr_index, &cfg_offset);
5981 if (rc)
5982 goto unmap_vaddr;
5983 cfgtable = remap_pci_mem(pci_resource_start(pdev,
5984 cfg_base_addr_index) + cfg_offset, sizeof(*cfgtable));
5985 if (!cfgtable) {
5986 rc = -ENOMEM;
5987 goto unmap_vaddr;
5988 }
580ada3c
SC		 5989 rc = write_driver_ver_to_cfgtable(cfgtable);
5990 if (rc)
5991 goto unmap_vaddr;
edd16368 5992
cf0b08d0
SC		 5993 /* If reset via doorbell register is supported, use that.
5994 * There are two such methods. Favor the newest method.
5995 */
1df8552a 5996 misc_fw_support = readl(&cfgtable->misc_fw_support);
cf0b08d0
SC		 5997 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET2;
5998 if (use_doorbell) {
5999 use_doorbell = DOORBELL_CTLR_RESET2;
6000 } else {
6001 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET;
6002 if (use_doorbell) {
fba63097
MM		 6003 dev_warn(&pdev->dev, "Soft reset not supported. "
6004 "Firmware update is required.\n");
64670ac8 6005 rc = -ENOTSUPP; /* try soft reset */
cf0b08d0
SC		 6006 goto unmap_cfgtable;
6007 }
6008 }
edd16368 6009
1df8552a
SC		 6010 rc = hpsa_controller_hard_reset(pdev, vaddr, use_doorbell);
6011 if (rc)
6012 goto unmap_cfgtable;
edd16368 6013
270d05de
SC		 6014 pci_restore_state(pdev);
6015 rc = pci_enable_device(pdev);
6016 if (rc) {
6017 dev_warn(&pdev->dev, "failed to enable device.\n");
6018 goto unmap_cfgtable;
edd16368 6019 }
270d05de 6020 pci_write_config_word(pdev, 4, command_register);
edd16368 6021
1df8552a
SC		 6022 /* Some devices (notably the HP Smart Array 5i Controller)
6023 need a little pause here */
6024 msleep(HPSA_POST_RESET_PAUSE_MSECS);
6025
fe5389c8
SC		 6026 rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_READY);
6027 if (rc) {
6028 dev_warn(&pdev->dev,
64670ac8
SC		 6029 "failed waiting for board to become ready "
6030 "after hard reset\n");
fe5389c8
SC		 6031 goto unmap_cfgtable;
6032 }
fe5389c8 6033
580ada3c
SC		 6034 rc = controller_reset_failed(vaddr);
6035 if (rc < 0)
6036 goto unmap_cfgtable;
6037 if (rc) {
64670ac8
SC		 6038 dev_warn(&pdev->dev, "Unable to successfully reset "
6039 "controller. Will try soft reset.\n");
6040 rc = -ENOTSUPP;
580ada3c 6041 } else {
64670ac8 6042 dev_info(&pdev->dev, "board ready after hard reset.\n");
1df8552a
SC		 6043 }
6044
6045unmap_cfgtable:
6046 iounmap(cfgtable);
6047
6048unmap_vaddr:
6049 iounmap(vaddr);
6050 return rc;
edd16368
SC		 6051}
6052
6053/*
6054 * We cannot read the structure directly, for portability we must use
6055 * the io functions.
6056 * This is for debug only.
6057 */
edd16368
SC		 6058static void print_cfg_table(struct device *dev, struct CfgTable *tb)
6059{
58f8665c 6060#ifdef HPSA_DEBUG
edd16368
SC		 6061 int i;
6062 char temp_name[17];
6063
6064 dev_info(dev, "Controller Configuration information\n");
6065 dev_info(dev, "------------------------------------\n");
6066 for (i = 0; i < 4; i++)
6067 temp_name[i] = readb(&(tb->Signature[i]));
6068 temp_name[4] = '\0';
6069 dev_info(dev, " Signature = %s\n", temp_name);
6070 dev_info(dev, " Spec Number = %d\n", readl(&(tb->SpecValence)));
6071 dev_info(dev, " Transport methods supported = 0x%x\n",
6072 readl(&(tb->TransportSupport)));
6073 dev_info(dev, " Transport methods active = 0x%x\n",
6074 readl(&(tb->TransportActive)));
6075 dev_info(dev, " Requested transport Method = 0x%x\n",
6076 readl(&(tb->HostWrite.TransportRequest)));
6077 dev_info(dev, " Coalesce Interrupt Delay = 0x%x\n",
6078 readl(&(tb->HostWrite.CoalIntDelay)));
6079 dev_info(dev, " Coalesce Interrupt Count = 0x%x\n",
6080 readl(&(tb->HostWrite.CoalIntCount)));
6081 dev_info(dev, " Max outstanding commands = 0x%d\n",
6082 readl(&(tb->CmdsOutMax)));
6083 dev_info(dev, " Bus Types = 0x%x\n", readl(&(tb->BusTypes)));
6084 for (i = 0; i < 16; i++)
6085 temp_name[i] = readb(&(tb->ServerName[i]));
6086 temp_name[16] = '\0';
6087 dev_info(dev, " Server Name = %s\n", temp_name);
6088 dev_info(dev, " Heartbeat Counter = 0x%x\n\n\n",
6089 readl(&(tb->HeartBeat)));
edd16368 6090#endif /* HPSA_DEBUG */
58f8665c 6091}
edd16368
SC		 6092
6093static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr)
6094{
6095 int i, offset, mem_type, bar_type;
6096
6097 if (pci_bar_addr == PCI_BASE_ADDRESS_0) /* looking for BAR zero? */
6098 return 0;
6099 offset = 0;
6100 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
6101 bar_type = pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE;
6102 if (bar_type == PCI_BASE_ADDRESS_SPACE_IO)
6103 offset += 4;
6104 else {
6105 mem_type = pci_resource_flags(pdev, i) &
6106 PCI_BASE_ADDRESS_MEM_TYPE_MASK;
6107 switch (mem_type) {
6108 case PCI_BASE_ADDRESS_MEM_TYPE_32:
6109 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
6110 offset += 4; /* 32 bit */
6111 break;
6112 case PCI_BASE_ADDRESS_MEM_TYPE_64:
6113 offset += 8;
6114 break;
6115 default: /* reserved in PCI 2.2 */
6116 dev_warn(&pdev->dev,
6117 "base address is invalid\n");
6118 return -1;
6119 break;
6120 }
6121 }
6122 if (offset == pci_bar_addr - PCI_BASE_ADDRESS_0)
6123 return i + 1;
6124 }
6125 return -1;
6126}
6127
6128/* If MSI/MSI-X is supported by the kernel we will try to enable it on
6129 * controllers that are capable. If not, we use IO-APIC mode.
6130 */
6131
6f039790 6132static void hpsa_interrupt_mode(struct ctlr_info *h)
edd16368
SC		 6133{
6134#ifdef CONFIG_PCI_MSI
254f796b
MG		 6135 int err, i;
6136 struct msix_entry hpsa_msix_entries[MAX_REPLY_QUEUES];
6137
6138 for (i = 0; i < MAX_REPLY_QUEUES; i++) {
6139 hpsa_msix_entries[i].vector = 0;
6140 hpsa_msix_entries[i].entry = i;
6141 }
edd16368
SC		 6142
6143 /* Some boards advertise MSI but don't really support it */
6b3f4c52
SC		 6144 if ((h->board_id == 0x40700E11) || (h->board_id == 0x40800E11) ||
6145 (h->board_id == 0x40820E11) || (h->board_id == 0x40830E11))
edd16368 6146 goto default_int_mode;
55c06c71
SC		 6147 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSIX)) {
6148 dev_info(&h->pdev->dev, "MSIX\n");
eee0f03a 6149 h->msix_vector = MAX_REPLY_QUEUES;
254f796b 6150 err = pci_enable_msix(h->pdev, hpsa_msix_entries,
eee0f03a 6151 h->msix_vector);
edd16368 6152 if (err > 0) {
55c06c71 6153 dev_warn(&h->pdev->dev, "only %d MSI-X vectors "
edd16368 6154 "available\n", err);
eee0f03a
HR		 6155 h->msix_vector = err;
6156 err = pci_enable_msix(h->pdev, hpsa_msix_entries,
6157 h->msix_vector);
6158 }
6159 if (!err) {
6160 for (i = 0; i < h->msix_vector; i++)
6161 h->intr[i] = hpsa_msix_entries[i].vector;
6162 return;
edd16368 6163 } else {
55c06c71 6164 dev_warn(&h->pdev->dev, "MSI-X init failed %d\n",
edd16368 6165 err);
eee0f03a 6166 h->msix_vector = 0;
edd16368
SC		 6167 goto default_int_mode;
6168 }
6169 }
55c06c71
SC		 6170 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSI)) {
6171 dev_info(&h->pdev->dev, "MSI\n");
6172 if (!pci_enable_msi(h->pdev))
edd16368
SC		 6173 h->msi_vector = 1;
6174 else
55c06c71 6175 dev_warn(&h->pdev->dev, "MSI init failed\n");
edd16368
SC		 6176 }
6177default_int_mode:
6178#endif /* CONFIG_PCI_MSI */
6179 /* if we get here we're going to use the default interrupt mode */
a9a3a273 6180 h->intr[h->intr_mode] = h->pdev->irq;
edd16368
SC		 6181}
6182
6f039790 6183static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id)
e5c880d1
SC		 6184{
6185 int i;
6186 u32 subsystem_vendor_id, subsystem_device_id;
6187
6188 subsystem_vendor_id = pdev->subsystem_vendor;
6189 subsystem_device_id = pdev->subsystem_device;
6190 *board_id = ((subsystem_device_id << 16) & 0xffff0000) |
6191 subsystem_vendor_id;
6192
6193 for (i = 0; i < ARRAY_SIZE(products); i++)
6194 if (*board_id == products[i].board_id)
6195 return i;
6196
6798cc0a
SC		 6197 if ((subsystem_vendor_id != PCI_VENDOR_ID_HP &&
6198 subsystem_vendor_id != PCI_VENDOR_ID_COMPAQ) ||
6199 !hpsa_allow_any) {
e5c880d1
SC		 6200 dev_warn(&pdev->dev, "unrecognized board ID: "
6201 "0x%08x, ignoring.\n", *board_id);
6202 return -ENODEV;
6203 }
6204 return ARRAY_SIZE(products) - 1; /* generic unknown smart array */
6205}
6206
6f039790
GKH		 6207static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
6208 unsigned long *memory_bar)
3a7774ce
SC		 6209{
6210 int i;
6211
6212 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
12d2cd47 6213 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
3a7774ce 6214 /* addressing mode bits already removed */
12d2cd47
SC		 6215 *memory_bar = pci_resource_start(pdev, i);
6216 dev_dbg(&pdev->dev, "memory BAR = %lx\n",
3a7774ce
SC		 6217 *memory_bar);
6218 return 0;
6219 }
12d2cd47 6220 dev_warn(&pdev->dev, "no memory BAR found\n");
3a7774ce
SC		 6221 return -ENODEV;
6222}
6223
6f039790
GKH		 6224static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
6225 int wait_for_ready)
2c4c8c8b 6226{
fe5389c8 6227 int i, iterations;
2c4c8c8b 6228 u32 scratchpad;
fe5389c8
SC		 6229 if (wait_for_ready)
6230 iterations = HPSA_BOARD_READY_ITERATIONS;
6231 else
6232 iterations = HPSA_BOARD_NOT_READY_ITERATIONS;
2c4c8c8b 6233
fe5389c8
SC		 6234 for (i = 0; i < iterations; i++) {
6235 scratchpad = readl(vaddr + SA5_SCRATCHPAD_OFFSET);
6236 if (wait_for_ready) {
6237 if (scratchpad == HPSA_FIRMWARE_READY)
6238 return 0;
6239 } else {
6240 if (scratchpad != HPSA_FIRMWARE_READY)
6241 return 0;
6242 }
2c4c8c8b
SC		 6243 msleep(HPSA_BOARD_READY_POLL_INTERVAL_MSECS);
6244 }
fe5389c8 6245 dev_warn(&pdev->dev, "board not ready, timed out.\n");
2c4c8c8b
SC		 6246 return -ENODEV;
6247}
6248
6f039790
GKH		 6249static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
6250 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
6251 u64 *cfg_offset)
a51fd47f
SC		 6252{
6253 *cfg_base_addr = readl(vaddr + SA5_CTCFG_OFFSET);
6254 *cfg_offset = readl(vaddr + SA5_CTMEM_OFFSET);
6255 *cfg_base_addr &= (u32) 0x0000ffff;
6256 *cfg_base_addr_index = find_PCI_BAR_index(pdev, *cfg_base_addr);
6257 if (*cfg_base_addr_index == -1) {
6258 dev_warn(&pdev->dev, "cannot find cfg_base_addr_index\n");
6259 return -ENODEV;
6260 }
6261 return 0;
6262}
6263
6f039790 6264static int hpsa_find_cfgtables(struct ctlr_info *h)
edd16368 6265{
01a02ffc
SC		 6266 u64 cfg_offset;
6267 u32 cfg_base_addr;
6268 u64 cfg_base_addr_index;
303932fd 6269 u32 trans_offset;
a51fd47f 6270 int rc;
77c4495c 6271
a51fd47f
SC		 6272 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
6273 &cfg_base_addr_index, &cfg_offset);
6274 if (rc)
6275 return rc;
77c4495c 6276 h->cfgtable = remap_pci_mem(pci_resource_start(h->pdev,
a51fd47f 6277 cfg_base_addr_index) + cfg_offset, sizeof(*h->cfgtable));
77c4495c
SC		 6278 if (!h->cfgtable)
6279 return -ENOMEM;
580ada3c
SC		 6280 rc = write_driver_ver_to_cfgtable(h->cfgtable);
6281 if (rc)
6282 return rc;
77c4495c 6283 /* Find performant mode table. */
a51fd47f 6284 trans_offset = readl(&h->cfgtable->TransMethodOffset);
77c4495c
SC		 6285 h->transtable = remap_pci_mem(pci_resource_start(h->pdev,
6286 cfg_base_addr_index)+cfg_offset+trans_offset,
6287 sizeof(*h->transtable));
6288 if (!h->transtable)
6289 return -ENOMEM;
6290 return 0;
6291}
6292
6f039790 6293static void hpsa_get_max_perf_mode_cmds(struct ctlr_info *h)
cba3d38b
SC		 6294{
6295 h->max_commands = readl(&(h->cfgtable->MaxPerformantModeCommands));
72ceeaec
SC		 6296
6297 /* Limit commands in memory limited kdump scenario. */
6298 if (reset_devices && h->max_commands > 32)
6299 h->max_commands = 32;
6300
cba3d38b
SC		 6301 if (h->max_commands < 16) {
6302 dev_warn(&h->pdev->dev, "Controller reports "
6303 "max supported commands of %d, an obvious lie. "
6304 "Using 16. Ensure that firmware is up to date.\n",
6305 h->max_commands);
6306 h->max_commands = 16;
6307 }
6308}
6309
b93d7536
SC		 6310/* Interrogate the hardware for some limits:
6311 * max commands, max SG elements without chaining, and with chaining,
6312 * SG chain block size, etc.
6313 */
6f039790 6314static void hpsa_find_board_params(struct ctlr_info *h)
b93d7536 6315{
cba3d38b 6316 hpsa_get_max_perf_mode_cmds(h);
b93d7536
SC		 6317 h->nr_cmds = h->max_commands - 4; /* Allow room for some ioctls */
6318 h->maxsgentries = readl(&(h->cfgtable->MaxScatterGatherElements));
283b4a9b 6319 h->fw_support = readl(&(h->cfgtable->misc_fw_support));
b93d7536
SC		 6320 /*
6321 * Limit in-command s/g elements to 32 save dma'able memory.
6322 * Howvever spec says if 0, use 31
6323 */
6324 h->max_cmd_sg_entries = 31;
6325 if (h->maxsgentries > 512) {
6326 h->max_cmd_sg_entries = 32;
6327 h->chainsize = h->maxsgentries - h->max_cmd_sg_entries + 1;
6328 h->maxsgentries--; /* save one for chain pointer */
6329 } else {
6330 h->maxsgentries = 31; /* default to traditional values */
6331 h->chainsize = 0;
6332 }
75167d2c
SC		 6333
6334 /* Find out what task management functions are supported and cache */
6335 h->TMFSupportFlags = readl(&(h->cfgtable->TMFSupportFlags));
0e7a7fce
ST		 6336 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags))
6337 dev_warn(&h->pdev->dev, "Physical aborts not supported\n");
6338 if (!(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
6339 dev_warn(&h->pdev->dev, "Logical aborts not supported\n");
b93d7536
SC		 6340}
6341
76c46e49
SC		 6342static inline bool hpsa_CISS_signature_present(struct ctlr_info *h)
6343{
0fc9fd40 6344 if (!check_signature(h->cfgtable->Signature, "CISS", 4)) {
76c46e49
SC		 6345 dev_warn(&h->pdev->dev, "not a valid CISS config table\n");
6346 return false;
6347 }
6348 return true;
6349}
6350
97a5e98c 6351static inline void hpsa_set_driver_support_bits(struct ctlr_info *h)
f7c39101 6352{
97a5e98c 6353 u32 driver_support;
f7c39101 6354
28e13446
SC		 6355#ifdef CONFIG_X86
6356 /* Need to enable prefetch in the SCSI core for 6400 in x86 */
97a5e98c
SC		 6357 driver_support = readl(&(h->cfgtable->driver_support));
6358 driver_support |= ENABLE_SCSI_PREFETCH;
f7c39101 6359#endif
28e13446
SC		 6360 driver_support |= ENABLE_UNIT_ATTN;
6361 writel(driver_support, &(h->cfgtable->driver_support));
f7c39101
SC		 6362}
6363
3d0eab67
SC		 6364/* Disable DMA prefetch for the P600. Otherwise an ASIC bug may result
6365 * in a prefetch beyond physical memory.
6366 */
6367static inline void hpsa_p600_dma_prefetch_quirk(struct ctlr_info *h)
6368{
6369 u32 dma_prefetch;
6370
6371 if (h->board_id != 0x3225103C)
6372 return;
6373 dma_prefetch = readl(h->vaddr + I2O_DMA1_CFG);
6374 dma_prefetch |= 0x8000;
6375 writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG);
6376}
6377
76438d08
SC		 6378static void hpsa_wait_for_clear_event_notify_ack(struct ctlr_info *h)
6379{
6380 int i;
6381 u32 doorbell_value;
6382 unsigned long flags;
6383 /* wait until the clear_event_notify bit 6 is cleared by controller. */
6384 for (i = 0; i < MAX_CONFIG_WAIT; i++) {
6385 spin_lock_irqsave(&h->lock, flags);
6386 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
6387 spin_unlock_irqrestore(&h->lock, flags);
6388 if (!(doorbell_value & DOORBELL_CLEAR_EVENTS))
6389 break;
6390 /* delay and try again */
6391 msleep(20);
6392 }
6393}
6394
6f039790 6395static void hpsa_wait_for_mode_change_ack(struct ctlr_info *h)
eb6b2ae9
SC		 6396{
6397 int i;
6eaf46fd
SC		 6398 u32 doorbell_value;
6399 unsigned long flags;
eb6b2ae9
SC		 6400
6401 /* under certain very rare conditions, this can take awhile.
6402 * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right
6403 * as we enter this code.)
6404 */
6405 for (i = 0; i < MAX_CONFIG_WAIT; i++) {
6eaf46fd
SC		 6406 spin_lock_irqsave(&h->lock, flags);
6407 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
6408 spin_unlock_irqrestore(&h->lock, flags);
382be668 6409 if (!(doorbell_value & CFGTBL_ChangeReq))
eb6b2ae9
SC		 6410 break;
6411 /* delay and try again */
60d3f5b0 6412 usleep_range(10000, 20000);
eb6b2ae9 6413 }
3f4336f3
SC		 6414}
6415
6f039790 6416static int hpsa_enter_simple_mode(struct ctlr_info *h)
3f4336f3
SC		 6417{
6418 u32 trans_support;
6419
6420 trans_support = readl(&(h->cfgtable->TransportSupport));
6421 if (!(trans_support & SIMPLE_MODE))
6422 return -ENOTSUPP;
6423
6424 h->max_commands = readl(&(h->cfgtable->CmdsOutMax));
283b4a9b 6425
3f4336f3
SC		 6426 /* Update the field, and then ring the doorbell */
6427 writel(CFGTBL_Trans_Simple, &(h->cfgtable->HostWrite.TransportRequest));
b9af4937 6428 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
3f4336f3
SC		 6429 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
6430 hpsa_wait_for_mode_change_ack(h);
eb6b2ae9 6431 print_cfg_table(&h->pdev->dev, h->cfgtable);
283b4a9b
SC		 6432 if (!(readl(&(h->cfgtable->TransportActive)) & CFGTBL_Trans_Simple))
6433 goto error;
960a30e7 6434 h->transMethod = CFGTBL_Trans_Simple;
eb6b2ae9 6435 return 0;
283b4a9b
SC		 6436error:
6437 dev_warn(&h->pdev->dev, "unable to get board into simple mode\n");
6438 return -ENODEV;
eb6b2ae9
SC		 6439}
6440
6f039790 6441static int hpsa_pci_init(struct ctlr_info *h)
77c4495c 6442{
eb6b2ae9 6443 int prod_index, err;
edd16368 6444
e5c880d1
SC		 6445 prod_index = hpsa_lookup_board_id(h->pdev, &h->board_id);
6446 if (prod_index < 0)
6447 return -ENODEV;
6448 h->product_name = products[prod_index].product_name;
6449 h->access = *(products[prod_index].access);
edd16368 6450
e5a44df8
MG		 6451 pci_disable_link_state(h->pdev, PCIE_LINK_STATE_L0S |
6452 PCIE_LINK_STATE_L1 | PCIE_LINK_STATE_CLKPM);
6453
55c06c71 6454 err = pci_enable_device(h->pdev);
edd16368 6455 if (err) {
55c06c71 6456 dev_warn(&h->pdev->dev, "unable to enable PCI device\n");
edd16368
SC		 6457 return err;
6458 }
6459
5cb460a6
SC		 6460 /* Enable bus mastering (pci_disable_device may disable this) */
6461 pci_set_master(h->pdev);
6462
f79cfec6 6463 err = pci_request_regions(h->pdev, HPSA);
edd16368 6464 if (err) {
55c06c71
SC		 6465 dev_err(&h->pdev->dev,
6466 "cannot obtain PCI resources, aborting\n");
edd16368
SC		 6467 return err;
6468 }
6b3f4c52 6469 hpsa_interrupt_mode(h);
12d2cd47 6470 err = hpsa_pci_find_memory_BAR(h->pdev, &h->paddr);
3a7774ce 6471 if (err)
edd16368 6472 goto err_out_free_res;
edd16368 6473 h->vaddr = remap_pci_mem(h->paddr, 0x250);
204892e9
SC		 6474 if (!h->vaddr) {
6475 err = -ENOMEM;
6476 goto err_out_free_res;
6477 }
fe5389c8 6478 err = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
2c4c8c8b 6479 if (err)
edd16368 6480 goto err_out_free_res;
77c4495c
SC		 6481 err = hpsa_find_cfgtables(h);
6482 if (err)
edd16368 6483 goto err_out_free_res;
b93d7536 6484 hpsa_find_board_params(h);
edd16368 6485
76c46e49 6486 if (!hpsa_CISS_signature_present(h)) {
edd16368
SC		 6487 err = -ENODEV;
6488 goto err_out_free_res;
6489 }
97a5e98c 6490 hpsa_set_driver_support_bits(h);
3d0eab67 6491 hpsa_p600_dma_prefetch_quirk(h);
eb6b2ae9
SC		 6492 err = hpsa_enter_simple_mode(h);
6493 if (err)
edd16368 6494 goto err_out_free_res;
edd16368
SC		 6495 return 0;
6496
6497err_out_free_res:
204892e9
SC		 6498 if (h->transtable)
6499 iounmap(h->transtable);
6500 if (h->cfgtable)
6501 iounmap(h->cfgtable);
6502 if (h->vaddr)
6503 iounmap(h->vaddr);
f0bd0b68 6504 pci_disable_device(h->pdev);
55c06c71 6505 pci_release_regions(h->pdev);
edd16368
SC		 6506 return err;
6507}
6508
6f039790 6509static void hpsa_hba_inquiry(struct ctlr_info *h)
339b2b14
SC		 6510{
6511 int rc;
6512
6513#define HBA_INQUIRY_BYTE_COUNT 64
6514 h->hba_inquiry_data = kmalloc(HBA_INQUIRY_BYTE_COUNT, GFP_KERNEL);
6515 if (!h->hba_inquiry_data)
6516 return;
6517 rc = hpsa_scsi_do_inquiry(h, RAID_CTLR_LUNID, 0,
6518 h->hba_inquiry_data, HBA_INQUIRY_BYTE_COUNT);
6519 if (rc != 0) {
6520 kfree(h->hba_inquiry_data);
6521 h->hba_inquiry_data = NULL;
6522 }
6523}
6524
6f039790 6525static int hpsa_init_reset_devices(struct pci_dev *pdev)
4c2a8c40 6526{
1df8552a 6527 int rc, i;
4c2a8c40
SC		 6528
6529 if (!reset_devices)
6530 return 0;
6531
1df8552a
SC		 6532 /* Reset the controller with a PCI power-cycle or via doorbell */
6533 rc = hpsa_kdump_hard_reset_controller(pdev);
4c2a8c40 6534
1df8552a
SC		 6535 /* -ENOTSUPP here means we cannot reset the controller
6536 * but it's already (and still) up and running in
18867659
SC		 6537 * "performant mode". Or, it might be 640x, which can't reset
6538 * due to concerns about shared bbwc between 6402/6404 pair.
1df8552a
SC		 6539 */
6540 if (rc == -ENOTSUPP)
64670ac8 6541 return rc; /* just try to do the kdump anyhow. */
1df8552a
SC		 6542 if (rc)
6543 return -ENODEV;
4c2a8c40
SC		 6544
6545 /* Now try to get the controller to respond to a no-op */
2b870cb3 6546 dev_warn(&pdev->dev, "Waiting for controller to respond to no-op\n");
4c2a8c40
SC		 6547 for (i = 0; i < HPSA_POST_RESET_NOOP_RETRIES; i++) {
6548 if (hpsa_noop(pdev) == 0)
6549 break;
6550 else
6551 dev_warn(&pdev->dev, "no-op failed%s\n",
6552 (i < 11 ? "; re-trying" : ""));
6553 }
6554 return 0;
6555}
6556
6f039790 6557static int hpsa_allocate_cmd_pool(struct ctlr_info *h)
2e9d1b36
SC		 6558{
6559 h->cmd_pool_bits = kzalloc(
6560 DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG) *
6561 sizeof(unsigned long), GFP_KERNEL);
6562 h->cmd_pool = pci_alloc_consistent(h->pdev,
6563 h->nr_cmds * sizeof(*h->cmd_pool),
6564 &(h->cmd_pool_dhandle));
6565 h->errinfo_pool = pci_alloc_consistent(h->pdev,
6566 h->nr_cmds * sizeof(*h->errinfo_pool),
6567 &(h->errinfo_pool_dhandle));
6568 if ((h->cmd_pool_bits == NULL)
6569 || (h->cmd_pool == NULL)
6570 || (h->errinfo_pool == NULL)) {
6571 dev_err(&h->pdev->dev, "out of memory in %s", __func__);
6572 return -ENOMEM;
6573 }
6574 return 0;
6575}
6576
6577static void hpsa_free_cmd_pool(struct ctlr_info *h)
6578{
6579 kfree(h->cmd_pool_bits);
6580 if (h->cmd_pool)
6581 pci_free_consistent(h->pdev,
6582 h->nr_cmds * sizeof(struct CommandList),
6583 h->cmd_pool, h->cmd_pool_dhandle);
aca9012a
SC		 6584 if (h->ioaccel2_cmd_pool)
6585 pci_free_consistent(h->pdev,
6586 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
6587 h->ioaccel2_cmd_pool, h->ioaccel2_cmd_pool_dhandle);
2e9d1b36
SC		 6588 if (h->errinfo_pool)
6589 pci_free_consistent(h->pdev,
6590 h->nr_cmds * sizeof(struct ErrorInfo),
6591 h->errinfo_pool,
6592 h->errinfo_pool_dhandle);
e1f7de0c
MG		 6593 if (h->ioaccel_cmd_pool)
6594 pci_free_consistent(h->pdev,
6595 h->nr_cmds * sizeof(struct io_accel1_cmd),
6596 h->ioaccel_cmd_pool, h->ioaccel_cmd_pool_dhandle);
2e9d1b36
SC		 6597}
6598
0ae01a32
SC		 6599static int hpsa_request_irq(struct ctlr_info *h,
6600 irqreturn_t (*msixhandler)(int, void *),
6601 irqreturn_t (*intxhandler)(int, void *))
6602{
254f796b 6603 int rc, i;
0ae01a32 6604
254f796b
MG		 6605 /*
6606 * initialize h->q[x] = x so that interrupt handlers know which
6607 * queue to process.
6608 */
6609 for (i = 0; i < MAX_REPLY_QUEUES; i++)
6610 h->q[i] = (u8) i;
6611
eee0f03a 6612 if (h->intr_mode == PERF_MODE_INT && h->msix_vector > 0) {
254f796b 6613 /* If performant mode and MSI-X, use multiple reply queues */
eee0f03a 6614 for (i = 0; i < h->msix_vector; i++)
254f796b
MG		 6615 rc = request_irq(h->intr[i], msixhandler,
6616 0, h->devname,
6617 &h->q[i]);
6618 } else {
6619 /* Use single reply pool */
eee0f03a 6620 if (h->msix_vector > 0 || h->msi_vector) {
254f796b
MG		 6621 rc = request_irq(h->intr[h->intr_mode],
6622 msixhandler, 0, h->devname,
6623 &h->q[h->intr_mode]);
6624 } else {
6625 rc = request_irq(h->intr[h->intr_mode],
6626 intxhandler, IRQF_SHARED, h->devname,
6627 &h->q[h->intr_mode]);
6628 }
6629 }
0ae01a32
SC		 6630 if (rc) {
6631 dev_err(&h->pdev->dev, "unable to get irq %d for %s\n",
6632 h->intr[h->intr_mode], h->devname);
6633 return -ENODEV;
6634 }
6635 return 0;
6636}
6637
6f039790 6638static int hpsa_kdump_soft_reset(struct ctlr_info *h)
64670ac8
SC		 6639{
6640 if (hpsa_send_host_reset(h, RAID_CTLR_LUNID,
6641 HPSA_RESET_TYPE_CONTROLLER)) {
6642 dev_warn(&h->pdev->dev, "Resetting array controller failed.\n");
6643 return -EIO;
6644 }
6645
6646 dev_info(&h->pdev->dev, "Waiting for board to soft reset.\n");
6647 if (hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_NOT_READY)) {
6648 dev_warn(&h->pdev->dev, "Soft reset had no effect.\n");
6649 return -1;
6650 }
6651
6652 dev_info(&h->pdev->dev, "Board reset, awaiting READY status.\n");
6653 if (hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY)) {
6654 dev_warn(&h->pdev->dev, "Board failed to become ready "
6655 "after soft reset.\n");
6656 return -1;
6657 }
6658
6659 return 0;
6660}
6661
254f796b
MG		 6662static void free_irqs(struct ctlr_info *h)
6663{
6664 int i;
6665
6666 if (!h->msix_vector || h->intr_mode != PERF_MODE_INT) {
6667 /* Single reply queue, only one irq to free */
6668 i = h->intr_mode;
6669 free_irq(h->intr[i], &h->q[i]);
6670 return;
6671 }
6672
eee0f03a 6673 for (i = 0; i < h->msix_vector; i++)
254f796b
MG		 6674 free_irq(h->intr[i], &h->q[i]);
6675}
6676
0097f0f4 6677static void hpsa_free_irqs_and_disable_msix(struct ctlr_info *h)
64670ac8 6678{
254f796b 6679 free_irqs(h);
64670ac8 6680#ifdef CONFIG_PCI_MSI
0097f0f4
SC		 6681 if (h->msix_vector) {
6682 if (h->pdev->msix_enabled)
6683 pci_disable_msix(h->pdev);
6684 } else if (h->msi_vector) {
6685 if (h->pdev->msi_enabled)
6686 pci_disable_msi(h->pdev);
6687 }
64670ac8 6688#endif /* CONFIG_PCI_MSI */
0097f0f4
SC		 6689}
6690
6691static void hpsa_undo_allocations_after_kdump_soft_reset(struct ctlr_info *h)
6692{
6693 hpsa_free_irqs_and_disable_msix(h);
64670ac8
SC		 6694 hpsa_free_sg_chain_blocks(h);
6695 hpsa_free_cmd_pool(h);
e1f7de0c 6696 kfree(h->ioaccel1_blockFetchTable);
64670ac8
SC		 6697 kfree(h->blockFetchTable);
6698 pci_free_consistent(h->pdev, h->reply_pool_size,
6699 h->reply_pool, h->reply_pool_dhandle);
6700 if (h->vaddr)
6701 iounmap(h->vaddr);
6702 if (h->transtable)
6703 iounmap(h->transtable);
6704 if (h->cfgtable)
6705 iounmap(h->cfgtable);
6706 pci_release_regions(h->pdev);
6707 kfree(h);
6708}
6709
a0c12413
SC		 6710/* Called when controller lockup detected. */
6711static void fail_all_cmds_on_list(struct ctlr_info *h, struct list_head *list)
6712{
6713 struct CommandList *c = NULL;
6714
6715 assert_spin_locked(&h->lock);
6716 /* Mark all outstanding commands as failed and complete them. */
6717 while (!list_empty(list)) {
6718 c = list_entry(list->next, struct CommandList, list);
6719 c->err_info->CommandStatus = CMD_HARDWARE_ERR;
5a3d16f5 6720 finish_cmd(c);
a0c12413
SC		 6721 }
6722}
6723
6724static void controller_lockup_detected(struct ctlr_info *h)
6725{
6726 unsigned long flags;
6727
a0c12413
SC		 6728 h->access.set_intr_mask(h, HPSA_INTR_OFF);
6729 spin_lock_irqsave(&h->lock, flags);
6730 h->lockup_detected = readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
6731 spin_unlock_irqrestore(&h->lock, flags);
6732 dev_warn(&h->pdev->dev, "Controller lockup detected: 0x%08x\n",
6733 h->lockup_detected);
6734 pci_disable_device(h->pdev);
6735 spin_lock_irqsave(&h->lock, flags);
6736 fail_all_cmds_on_list(h, &h->cmpQ);
6737 fail_all_cmds_on_list(h, &h->reqQ);
6738 spin_unlock_irqrestore(&h->lock, flags);
6739}
6740
a0c12413
SC		 6741static void detect_controller_lockup(struct ctlr_info *h)
6742{
6743 u64 now;
6744 u32 heartbeat;
6745 unsigned long flags;
6746
a0c12413
SC		 6747 now = get_jiffies_64();
6748 /* If we've received an interrupt recently, we're ok. */
6749 if (time_after64(h->last_intr_timestamp +
e85c5974 6750 (h->heartbeat_sample_interval), now))
a0c12413
SC		 6751 return;
6752
6753 /*
6754 * If we've already checked the heartbeat recently, we're ok.
6755 * This could happen if someone sends us a signal. We
6756 * otherwise don't care about signals in this thread.
6757 */
6758 if (time_after64(h->last_heartbeat_timestamp +
e85c5974 6759 (h->heartbeat_sample_interval), now))
a0c12413
SC		 6760 return;
6761
6762 /* If heartbeat has not changed since we last looked, we're not ok. */
6763 spin_lock_irqsave(&h->lock, flags);
6764 heartbeat = readl(&h->cfgtable->HeartBeat);
6765 spin_unlock_irqrestore(&h->lock, flags);
6766 if (h->last_heartbeat == heartbeat) {
6767 controller_lockup_detected(h);
6768 return;
6769 }
6770
6771 /* We're ok. */
6772 h->last_heartbeat = heartbeat;
6773 h->last_heartbeat_timestamp = now;
6774}
6775
9846590e 6776static void hpsa_ack_ctlr_events(struct ctlr_info *h)
76438d08
SC		 6777{
6778 int i;
6779 char *event_type;
6780
e863d68e
ST		 6781 /* Clear the driver-requested rescan flag */
6782 h->drv_req_rescan = 0;
6783
76438d08 6784 /* Ask the controller to clear the events we're handling. */
1f7cee8c
SC		 6785 if ((h->transMethod & (CFGTBL_Trans_io_accel1
6786 | CFGTBL_Trans_io_accel2)) &&
76438d08
SC		 6787 (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE ||
6788 h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)) {
6789
6790 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE)
6791 event_type = "state change";
6792 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)
6793 event_type = "configuration change";
6794 /* Stop sending new RAID offload reqs via the IO accelerator */
6795 scsi_block_requests(h->scsi_host);
6796 for (i = 0; i < h->ndevices; i++)
6797 h->dev[i]->offload_enabled = 0;
23100dd9 6798 hpsa_drain_accel_commands(h);
76438d08
SC		 6799 /* Set 'accelerator path config change' bit */
6800 dev_warn(&h->pdev->dev,
6801 "Acknowledging event: 0x%08x (HP SSD Smart Path %s)\n",
6802 h->events, event_type);
6803 writel(h->events, &(h->cfgtable->clear_event_notify));
6804 /* Set the "clear event notify field update" bit 6 */
6805 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
6806 /* Wait until ctlr clears 'clear event notify field', bit 6 */
6807 hpsa_wait_for_clear_event_notify_ack(h);
6808 scsi_unblock_requests(h->scsi_host);
6809 } else {
6810 /* Acknowledge controller notification events. */
6811 writel(h->events, &(h->cfgtable->clear_event_notify));
6812 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
6813 hpsa_wait_for_clear_event_notify_ack(h);
6814#if 0
6815 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
6816 hpsa_wait_for_mode_change_ack(h);
6817#endif
6818 }
9846590e 6819 return;
76438d08
SC		 6820}
6821
6822/* Check a register on the controller to see if there are configuration
6823 * changes (added/changed/removed logical drives, etc.) which mean that
e863d68e
ST		 6824 * we should rescan the controller for devices.
6825 * Also check flag for driver-initiated rescan.
76438d08 6826 */
9846590e 6827static int hpsa_ctlr_needs_rescan(struct ctlr_info *h)
76438d08 6828{
9846590e
SC		 6829 if (h->drv_req_rescan)
6830 return 1;
6831
76438d08 6832 if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
9846590e 6833 return 0;
76438d08
SC		 6834
6835 h->events = readl(&(h->cfgtable->event_notify));
9846590e
SC		 6836 return h->events & RESCAN_REQUIRED_EVENT_BITS;
6837}
76438d08 6838
9846590e
SC		 6839/*
6840 * Check if any of the offline devices have become ready
6841 */
6842static int hpsa_offline_devices_ready(struct ctlr_info *h)
6843{
6844 unsigned long flags;
6845 struct offline_device_entry *d;
6846 struct list_head *this, *tmp;
6847
6848 spin_lock_irqsave(&h->offline_device_lock, flags);
6849 list_for_each_safe(this, tmp, &h->offline_device_list) {
6850 d = list_entry(this, struct offline_device_entry,
6851 offline_list);
6852 spin_unlock_irqrestore(&h->offline_device_lock, flags);
6853 if (!hpsa_volume_offline(h, d->scsi3addr))
6854 return 1;
6855 spin_lock_irqsave(&h->offline_device_lock, flags);
6856 }
6857 spin_unlock_irqrestore(&h->offline_device_lock, flags);
6858 return 0;
76438d08
SC		 6859}
6860
9846590e 6861
8a98db73 6862static void hpsa_monitor_ctlr_worker(struct work_struct *work)
a0c12413
SC		 6863{
6864 unsigned long flags;
8a98db73
SC		 6865 struct ctlr_info *h = container_of(to_delayed_work(work),
6866 struct ctlr_info, monitor_ctlr_work);
6867 detect_controller_lockup(h);
6868 if (h->lockup_detected)
6869 return;
9846590e
SC		 6870
6871 if (hpsa_ctlr_needs_rescan(h) || hpsa_offline_devices_ready(h)) {
6872 scsi_host_get(h->scsi_host);
6873 h->drv_req_rescan = 0;
6874 hpsa_ack_ctlr_events(h);
6875 hpsa_scan_start(h->scsi_host);
6876 scsi_host_put(h->scsi_host);
6877 }
6878
8a98db73
SC		 6879 spin_lock_irqsave(&h->lock, flags);
6880 if (h->remove_in_progress) {
6881 spin_unlock_irqrestore(&h->lock, flags);
a0c12413
SC		 6882 return;
6883 }
8a98db73
SC		 6884 schedule_delayed_work(&h->monitor_ctlr_work,
6885 h->heartbeat_sample_interval);
6886 spin_unlock_irqrestore(&h->lock, flags);
a0c12413
SC		 6887}
6888
6f039790 6889static int hpsa_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
edd16368 6890{
4c2a8c40 6891 int dac, rc;
edd16368 6892 struct ctlr_info *h;
64670ac8
SC		 6893 int try_soft_reset = 0;
6894 unsigned long flags;
edd16368
SC		 6895
6896 if (number_of_controllers == 0)
6897 printk(KERN_INFO DRIVER_NAME "\n");
edd16368 6898
4c2a8c40 6899 rc = hpsa_init_reset_devices(pdev);
64670ac8
SC		 6900 if (rc) {
6901 if (rc != -ENOTSUPP)
6902 return rc;
6903 /* If the reset fails in a particular way (it has no way to do
6904 * a proper hard reset, so returns -ENOTSUPP) we can try to do
6905 * a soft reset once we get the controller configured up to the
6906 * point that it can accept a command.
6907 */
6908 try_soft_reset = 1;
6909 rc = 0;
6910 }
6911
6912reinit_after_soft_reset:
edd16368 6913
303932fd
DB		 6914 /* Command structures must be aligned on a 32-byte boundary because
6915 * the 5 lower bits of the address are used by the hardware. and by
6916 * the driver. See comments in hpsa.h for more info.
6917 */
283b4a9b 6918#define COMMANDLIST_ALIGNMENT 128
303932fd 6919 BUILD_BUG_ON(sizeof(struct CommandList) % COMMANDLIST_ALIGNMENT);
edd16368
SC		 6920 h = kzalloc(sizeof(*h), GFP_KERNEL);
6921 if (!h)
ecd9aad4 6922 return -ENOMEM;
edd16368 6923
55c06c71 6924 h->pdev = pdev;
a9a3a273 6925 h->intr_mode = hpsa_simple_mode ? SIMPLE_MODE_INT : PERF_MODE_INT;
9e0fc764
SC		 6926 INIT_LIST_HEAD(&h->cmpQ);
6927 INIT_LIST_HEAD(&h->reqQ);
9846590e 6928 INIT_LIST_HEAD(&h->offline_device_list);
6eaf46fd 6929 spin_lock_init(&h->lock);
9846590e 6930 spin_lock_init(&h->offline_device_lock);
6eaf46fd 6931 spin_lock_init(&h->scan_lock);
0390f0c0 6932 spin_lock_init(&h->passthru_count_lock);
55c06c71 6933 rc = hpsa_pci_init(h);
ecd9aad4 6934 if (rc != 0)
edd16368
SC		 6935 goto clean1;
6936
f79cfec6 6937 sprintf(h->devname, HPSA "%d", number_of_controllers);
edd16368
SC		 6938 h->ctlr = number_of_controllers;
6939 number_of_controllers++;
edd16368
SC		 6940
6941 /* configure PCI DMA stuff */
ecd9aad4
SC		 6942 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
6943 if (rc == 0) {
edd16368 6944 dac = 1;
ecd9aad4
SC		 6945 } else {
6946 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6947 if (rc == 0) {
6948 dac = 0;
6949 } else {
6950 dev_err(&pdev->dev, "no suitable DMA available\n");
6951 goto clean1;
6952 }
edd16368
SC		 6953 }
6954
6955 /* make sure the board interrupts are off */
6956 h->access.set_intr_mask(h, HPSA_INTR_OFF);
10f66018 6957
0ae01a32 6958 if (hpsa_request_irq(h, do_hpsa_intr_msi, do_hpsa_intr_intx))
edd16368 6959 goto clean2;
303932fd
DB		 6960 dev_info(&pdev->dev, "%s: <0x%x> at IRQ %d%s using DAC\n",
6961 h->devname, pdev->device,
a9a3a273 6962 h->intr[h->intr_mode], dac ? "" : " not");
2e9d1b36 6963 if (hpsa_allocate_cmd_pool(h))
edd16368 6964 goto clean4;
33a2ffce
SC		 6965 if (hpsa_allocate_sg_chain_blocks(h))
6966 goto clean4;
a08a8471
SC		 6967 init_waitqueue_head(&h->scan_wait_queue);
6968 h->scan_finished = 1; /* no scan currently in progress */
edd16368
SC		 6969
6970 pci_set_drvdata(pdev, h);
9a41338e 6971 h->ndevices = 0;
316b221a 6972 h->hba_mode_enabled = 0;
9a41338e
SC		 6973 h->scsi_host = NULL;
6974 spin_lock_init(&h->devlock);
64670ac8
SC		 6975 hpsa_put_ctlr_into_performant_mode(h);
6976
6977 /* At this point, the controller is ready to take commands.
6978 * Now, if reset_devices and the hard reset didn't work, try
6979 * the soft reset and see if that works.
6980 */
6981 if (try_soft_reset) {
6982
6983 /* This is kind of gross. We may or may not get a completion
6984 * from the soft reset command, and if we do, then the value
6985 * from the fifo may or may not be valid. So, we wait 10 secs
6986 * after the reset throwing away any completions we get during
6987 * that time. Unregister the interrupt handler and register
6988 * fake ones to scoop up any residual completions.
6989 */
6990 spin_lock_irqsave(&h->lock, flags);
6991 h->access.set_intr_mask(h, HPSA_INTR_OFF);
6992 spin_unlock_irqrestore(&h->lock, flags);
254f796b 6993 free_irqs(h);
64670ac8
SC		 6994 rc = hpsa_request_irq(h, hpsa_msix_discard_completions,
6995 hpsa_intx_discard_completions);
6996 if (rc) {
6997 dev_warn(&h->pdev->dev, "Failed to request_irq after "
6998 "soft reset.\n");
6999 goto clean4;
7000 }
7001
7002 rc = hpsa_kdump_soft_reset(h);
7003 if (rc)
7004 /* Neither hard nor soft reset worked, we're hosed. */
7005 goto clean4;
7006
7007 dev_info(&h->pdev->dev, "Board READY.\n");
7008 dev_info(&h->pdev->dev,
7009 "Waiting for stale completions to drain.\n");
7010 h->access.set_intr_mask(h, HPSA_INTR_ON);
7011 msleep(10000);
7012 h->access.set_intr_mask(h, HPSA_INTR_OFF);
7013
7014 rc = controller_reset_failed(h->cfgtable);
7015 if (rc)
7016 dev_info(&h->pdev->dev,
7017 "Soft reset appears to have failed.\n");
7018
7019 /* since the controller's reset, we have to go back and re-init
7020 * everything. Easiest to just forget what we've done and do it
7021 * all over again.
7022 */
7023 hpsa_undo_allocations_after_kdump_soft_reset(h);
7024 try_soft_reset = 0;
7025 if (rc)
7026 /* don't go to clean4, we already unallocated */
7027 return -ENODEV;
7028
7029 goto reinit_after_soft_reset;
7030 }
edd16368 7031
316b221a
SC		 7032 /* Enable Accelerated IO path at driver layer */
7033 h->acciopath_status = 1;
da0697bd 7034
e863d68e
ST		 7035 h->drv_req_rescan = 0;
7036
edd16368
SC		 7037 /* Turn the interrupts on so we can service requests */
7038 h->access.set_intr_mask(h, HPSA_INTR_ON);
7039
339b2b14 7040 hpsa_hba_inquiry(h);
edd16368 7041 hpsa_register_scsi(h); /* hook ourselves into SCSI subsystem */
8a98db73
SC		 7042
7043 /* Monitor the controller for firmware lockups */
7044 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
7045 INIT_DELAYED_WORK(&h->monitor_ctlr_work, hpsa_monitor_ctlr_worker);
7046 schedule_delayed_work(&h->monitor_ctlr_work,
7047 h->heartbeat_sample_interval);
88bf6d62 7048 return 0;
edd16368
SC		 7049
7050clean4:
33a2ffce 7051 hpsa_free_sg_chain_blocks(h);
2e9d1b36 7052 hpsa_free_cmd_pool(h);
254f796b 7053 free_irqs(h);
edd16368
SC		 7054clean2:
7055clean1:
edd16368 7056 kfree(h);
ecd9aad4 7057 return rc;
edd16368
SC		 7058}
7059
7060static void hpsa_flush_cache(struct ctlr_info *h)
7061{
7062 char *flush_buf;
7063 struct CommandList *c;
702890e3
SC		 7064 unsigned long flags;
7065
7066 /* Don't bother trying to flush the cache if locked up */
7067 spin_lock_irqsave(&h->lock, flags);
7068 if (unlikely(h->lockup_detected)) {
7069 spin_unlock_irqrestore(&h->lock, flags);
7070 return;
7071 }
7072 spin_unlock_irqrestore(&h->lock, flags);
edd16368
SC		 7073
7074 flush_buf = kzalloc(4, GFP_KERNEL);
7075 if (!flush_buf)
7076 return;
7077
7078 c = cmd_special_alloc(h);
7079 if (!c) {
7080 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
7081 goto out_of_memory;
7082 }
a2dac136
SC		 7083 if (fill_cmd(c, HPSA_CACHE_FLUSH, h, flush_buf, 4, 0,
7084 RAID_CTLR_LUNID, TYPE_CMD)) {
7085 goto out;
7086 }
edd16368
SC		 7087 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_TODEVICE);
7088 if (c->err_info->CommandStatus != 0)
a2dac136 7089out:
edd16368
SC		 7090 dev_warn(&h->pdev->dev,
7091 "error flushing cache on controller\n");
7092 cmd_special_free(h, c);
7093out_of_memory:
7094 kfree(flush_buf);
7095}
7096
7097static void hpsa_shutdown(struct pci_dev *pdev)
7098{
7099 struct ctlr_info *h;
7100
7101 h = pci_get_drvdata(pdev);
7102 /* Turn board interrupts off and send the flush cache command
7103 * sendcmd will turn off interrupt, and send the flush...
7104 * To write all data in the battery backed cache to disks
7105 */
7106 hpsa_flush_cache(h);
7107 h->access.set_intr_mask(h, HPSA_INTR_OFF);
0097f0f4 7108 hpsa_free_irqs_and_disable_msix(h);
edd16368
SC		 7109}
7110
6f039790 7111static void hpsa_free_device_info(struct ctlr_info *h)
55e14e76
SC		 7112{
7113 int i;
7114
7115 for (i = 0; i < h->ndevices; i++)
7116 kfree(h->dev[i]);
7117}
7118
6f039790 7119static void hpsa_remove_one(struct pci_dev *pdev)
edd16368
SC		 7120{
7121 struct ctlr_info *h;
8a98db73 7122 unsigned long flags;
edd16368
SC		 7123
7124 if (pci_get_drvdata(pdev) == NULL) {
a0c12413 7125 dev_err(&pdev->dev, "unable to remove device\n");
edd16368
SC		 7126 return;
7127 }
7128 h = pci_get_drvdata(pdev);
8a98db73
SC		 7129
7130 /* Get rid of any controller monitoring work items */
7131 spin_lock_irqsave(&h->lock, flags);
7132 h->remove_in_progress = 1;
7133 cancel_delayed_work(&h->monitor_ctlr_work);
7134 spin_unlock_irqrestore(&h->lock, flags);
7135
edd16368
SC		 7136 hpsa_unregister_scsi(h); /* unhook from SCSI subsystem */
7137 hpsa_shutdown(pdev);
7138 iounmap(h->vaddr);
204892e9
SC		 7139 iounmap(h->transtable);
7140 iounmap(h->cfgtable);
55e14e76 7141 hpsa_free_device_info(h);
33a2ffce 7142 hpsa_free_sg_chain_blocks(h);
edd16368
SC		 7143 pci_free_consistent(h->pdev,
7144 h->nr_cmds * sizeof(struct CommandList),
7145 h->cmd_pool, h->cmd_pool_dhandle);
7146 pci_free_consistent(h->pdev,
7147 h->nr_cmds * sizeof(struct ErrorInfo),
7148 h->errinfo_pool, h->errinfo_pool_dhandle);
303932fd
DB		 7149 pci_free_consistent(h->pdev, h->reply_pool_size,
7150 h->reply_pool, h->reply_pool_dhandle);
edd16368 7151 kfree(h->cmd_pool_bits);
303932fd 7152 kfree(h->blockFetchTable);
e1f7de0c 7153 kfree(h->ioaccel1_blockFetchTable);
aca9012a 7154 kfree(h->ioaccel2_blockFetchTable);
339b2b14 7155 kfree(h->hba_inquiry_data);
f0bd0b68 7156 pci_disable_device(pdev);
edd16368 7157 pci_release_regions(pdev);
edd16368
SC		 7158 kfree(h);
7159}
7160
7161static int hpsa_suspend(__attribute__((unused)) struct pci_dev *pdev,
7162 __attribute__((unused)) pm_message_t state)
7163{
7164 return -ENOSYS;
7165}
7166
7167static int hpsa_resume(__attribute__((unused)) struct pci_dev *pdev)
7168{
7169 return -ENOSYS;
7170}
7171
7172static struct pci_driver hpsa_pci_driver = {
f79cfec6 7173 .name = HPSA,
edd16368 7174 .probe = hpsa_init_one,
6f039790 7175 .remove = hpsa_remove_one,
edd16368
SC		 7176 .id_table = hpsa_pci_device_id, /* id_table */
7177 .shutdown = hpsa_shutdown,
7178 .suspend = hpsa_suspend,
7179 .resume = hpsa_resume,
7180};
7181
303932fd
DB		 7182/* Fill in bucket_map[], given nsgs (the max number of
7183 * scatter gather elements supported) and bucket[],
7184 * which is an array of 8 integers. The bucket[] array
7185 * contains 8 different DMA transfer sizes (in 16
7186 * byte increments) which the controller uses to fetch
7187 * commands. This function fills in bucket_map[], which
7188 * maps a given number of scatter gather elements to one of
7189 * the 8 DMA transfer sizes. The point of it is to allow the
7190 * controller to only do as much DMA as needed to fetch the
7191 * command, with the DMA transfer size encoded in the lower
7192 * bits of the command address.
7193 */
7194static void calc_bucket_map(int bucket[], int num_buckets,
e1f7de0c 7195 int nsgs, int min_blocks, int *bucket_map)
303932fd
DB		 7196{
7197 int i, j, b, size;
7198
303932fd
DB		 7199 /* Note, bucket_map must have nsgs+1 entries. */
7200 for (i = 0; i <= nsgs; i++) {
7201 /* Compute size of a command with i SG entries */
e1f7de0c 7202 size = i + min_blocks;
303932fd
DB		 7203 b = num_buckets; /* Assume the biggest bucket */
7204 /* Find the bucket that is just big enough */
e1f7de0c 7205 for (j = 0; j < num_buckets; j++) {
303932fd
DB		 7206 if (bucket[j] >= size) {
7207 b = j;
7208 break;
7209 }
7210 }
7211 /* for a command with i SG entries, use bucket b. */
7212 bucket_map[i] = b;
7213 }
7214}
7215
e1f7de0c 7216static void hpsa_enter_performant_mode(struct ctlr_info *h, u32 trans_support)
303932fd 7217{
6c311b57
SC		 7218 int i;
7219 unsigned long register_value;
e1f7de0c
MG		 7220 unsigned long transMethod = CFGTBL_Trans_Performant |
7221 (trans_support & CFGTBL_Trans_use_short_tags) |
b9af4937
SC		 7222 CFGTBL_Trans_enable_directed_msix |
7223 (trans_support & (CFGTBL_Trans_io_accel1 |
7224 CFGTBL_Trans_io_accel2));
e1f7de0c 7225 struct access_method access = SA5_performant_access;
def342bd
SC		 7226
7227 /* This is a bit complicated. There are 8 registers on
7228 * the controller which we write to to tell it 8 different
7229 * sizes of commands which there may be. It's a way of
7230 * reducing the DMA done to fetch each command. Encoded into
7231 * each command's tag are 3 bits which communicate to the controller
7232 * which of the eight sizes that command fits within. The size of
7233 * each command depends on how many scatter gather entries there are.
7234 * Each SG entry requires 16 bytes. The eight registers are programmed
7235 * with the number of 16-byte blocks a command of that size requires.
7236 * The smallest command possible requires 5 such 16 byte blocks.
d66ae08b 7237 * the largest command possible requires SG_ENTRIES_IN_CMD + 4 16-byte
def342bd
SC		 7238 * blocks. Note, this only extends to the SG entries contained
7239 * within the command block, and does not extend to chained blocks
7240 * of SG elements. bft[] contains the eight values we write to
7241 * the registers. They are not evenly distributed, but have more
7242 * sizes for small commands, and fewer sizes for larger commands.
7243 */
d66ae08b 7244 int bft[8] = {5, 6, 8, 10, 12, 20, 28, SG_ENTRIES_IN_CMD + 4};
b9af4937
SC		 7245#define MIN_IOACCEL2_BFT_ENTRY 5
7246#define HPSA_IOACCEL2_HEADER_SZ 4
7247 int bft2[16] = {MIN_IOACCEL2_BFT_ENTRY, 6, 7, 8, 9, 10, 11, 12,
7248 13, 14, 15, 16, 17, 18, 19,
7249 HPSA_IOACCEL2_HEADER_SZ + IOACCEL2_MAXSGENTRIES};
7250 BUILD_BUG_ON(ARRAY_SIZE(bft2) != 16);
7251 BUILD_BUG_ON(ARRAY_SIZE(bft) != 8);
7252 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) >
7253 16 * MIN_IOACCEL2_BFT_ENTRY);
7254 BUILD_BUG_ON(sizeof(struct ioaccel2_sg_element) != 16);
d66ae08b 7255 BUILD_BUG_ON(28 > SG_ENTRIES_IN_CMD + 4);
303932fd
DB		 7256 /* 5 = 1 s/g entry or 4k
7257 * 6 = 2 s/g entry or 8k
7258 * 8 = 4 s/g entry or 16k
7259 * 10 = 6 s/g entry or 24k
7260 */
303932fd 7261
303932fd
DB		 7262 /* Controller spec: zero out this buffer. */
7263 memset(h->reply_pool, 0, h->reply_pool_size);
303932fd 7264
d66ae08b
SC		 7265 bft[7] = SG_ENTRIES_IN_CMD + 4;
7266 calc_bucket_map(bft, ARRAY_SIZE(bft),
e1f7de0c 7267 SG_ENTRIES_IN_CMD, 4, h->blockFetchTable);
303932fd
DB		 7268 for (i = 0; i < 8; i++)
7269 writel(bft[i], &h->transtable->BlockFetch[i]);
7270
7271 /* size of controller ring buffer */
7272 writel(h->max_commands, &h->transtable->RepQSize);
254f796b 7273 writel(h->nreply_queues, &h->transtable->RepQCount);
303932fd
DB		 7274 writel(0, &h->transtable->RepQCtrAddrLow32);
7275 writel(0, &h->transtable->RepQCtrAddrHigh32);
254f796b
MG		 7276
7277 for (i = 0; i < h->nreply_queues; i++) {
7278 writel(0, &h->transtable->RepQAddr[i].upper);
7279 writel(h->reply_pool_dhandle +
7280 (h->max_commands * sizeof(u64) * i),
7281 &h->transtable->RepQAddr[i].lower);
7282 }
7283
b9af4937 7284 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
e1f7de0c
MG		 7285 writel(transMethod, &(h->cfgtable->HostWrite.TransportRequest));
7286 /*
7287 * enable outbound interrupt coalescing in accelerator mode;
7288 */
7289 if (trans_support & CFGTBL_Trans_io_accel1) {
7290 access = SA5_ioaccel_mode1_access;
7291 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
7292 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
c349775e
ST		 7293 } else {
7294 if (trans_support & CFGTBL_Trans_io_accel2) {
7295 access = SA5_ioaccel_mode2_access;
7296 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
7297 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
7298 }
e1f7de0c 7299 }
303932fd 7300 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
3f4336f3 7301 hpsa_wait_for_mode_change_ack(h);
303932fd
DB		 7302 register_value = readl(&(h->cfgtable->TransportActive));
7303 if (!(register_value & CFGTBL_Trans_Performant)) {
7304 dev_warn(&h->pdev->dev, "unable to get board into"
7305 " performant mode\n");
7306 return;
7307 }
960a30e7 7308 /* Change the access methods to the performant access methods */
e1f7de0c
MG		 7309 h->access = access;
7310 h->transMethod = transMethod;
7311
b9af4937
SC		 7312 if (!((trans_support & CFGTBL_Trans_io_accel1) ||
7313 (trans_support & CFGTBL_Trans_io_accel2)))
e1f7de0c
MG		 7314 return;
7315
b9af4937
SC		 7316 if (trans_support & CFGTBL_Trans_io_accel1) {
7317 /* Set up I/O accelerator mode */
7318 for (i = 0; i < h->nreply_queues; i++) {
7319 writel(i, h->vaddr + IOACCEL_MODE1_REPLY_QUEUE_INDEX);
7320 h->reply_queue[i].current_entry =
7321 readl(h->vaddr + IOACCEL_MODE1_PRODUCER_INDEX);
7322 }
7323 bft[7] = h->ioaccel_maxsg + 8;
7324 calc_bucket_map(bft, ARRAY_SIZE(bft), h->ioaccel_maxsg, 8,
7325 h->ioaccel1_blockFetchTable);
e1f7de0c 7326
b9af4937
SC		 7327 /* initialize all reply queue entries to unused */
7328 memset(h->reply_pool, (u8) IOACCEL_MODE1_REPLY_UNUSED,
7329 h->reply_pool_size);
e1f7de0c 7330
b9af4937
SC		 7331 /* set all the constant fields in the accelerator command
7332 * frames once at init time to save CPU cycles later.
7333 */
7334 for (i = 0; i < h->nr_cmds; i++) {
7335 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[i];
7336
7337 cp->function = IOACCEL1_FUNCTION_SCSIIO;
7338 cp->err_info = (u32) (h->errinfo_pool_dhandle +
7339 (i * sizeof(struct ErrorInfo)));
7340 cp->err_info_len = sizeof(struct ErrorInfo);
7341 cp->sgl_offset = IOACCEL1_SGLOFFSET;
7342 cp->host_context_flags = IOACCEL1_HCFLAGS_CISS_FORMAT;
7343 cp->timeout_sec = 0;
7344 cp->ReplyQueue = 0;
7345 cp->Tag.lower = (i << DIRECT_LOOKUP_SHIFT) |
7346 DIRECT_LOOKUP_BIT;
7347 cp->Tag.upper = 0;
7348 cp->host_addr.lower =
7349 (u32) (h->ioaccel_cmd_pool_dhandle +
7350 (i * sizeof(struct io_accel1_cmd)));
7351 cp->host_addr.upper = 0;
7352 }
7353 } else if (trans_support & CFGTBL_Trans_io_accel2) {
7354 u64 cfg_offset, cfg_base_addr_index;
7355 u32 bft2_offset, cfg_base_addr;
7356 int rc;
7357
7358 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
7359 &cfg_base_addr_index, &cfg_offset);
7360 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) != 64);
7361 bft2[15] = h->ioaccel_maxsg + HPSA_IOACCEL2_HEADER_SZ;
7362 calc_bucket_map(bft2, ARRAY_SIZE(bft2), h->ioaccel_maxsg,
7363 4, h->ioaccel2_blockFetchTable);
7364 bft2_offset = readl(&h->cfgtable->io_accel_request_size_offset);
7365 BUILD_BUG_ON(offsetof(struct CfgTable,
7366 io_accel_request_size_offset) != 0xb8);
7367 h->ioaccel2_bft2_regs =
7368 remap_pci_mem(pci_resource_start(h->pdev,
7369 cfg_base_addr_index) +
7370 cfg_offset + bft2_offset,
7371 ARRAY_SIZE(bft2) *
7372 sizeof(*h->ioaccel2_bft2_regs));
7373 for (i = 0; i < ARRAY_SIZE(bft2); i++)
7374 writel(bft2[i], &h->ioaccel2_bft2_regs[i]);
e1f7de0c 7375 }
b9af4937
SC		 7376 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
7377 hpsa_wait_for_mode_change_ack(h);
e1f7de0c
MG		 7378}
7379
7380static int hpsa_alloc_ioaccel_cmd_and_bft(struct ctlr_info *h)
7381{
283b4a9b
SC		 7382 h->ioaccel_maxsg =
7383 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
7384 if (h->ioaccel_maxsg > IOACCEL1_MAXSGENTRIES)
7385 h->ioaccel_maxsg = IOACCEL1_MAXSGENTRIES;
7386
e1f7de0c
MG		 7387 /* Command structures must be aligned on a 128-byte boundary
7388 * because the 7 lower bits of the address are used by the
7389 * hardware.
7390 */
7391#define IOACCEL1_COMMANDLIST_ALIGNMENT 128
7392 BUILD_BUG_ON(sizeof(struct io_accel1_cmd) %
7393 IOACCEL1_COMMANDLIST_ALIGNMENT);
7394 h->ioaccel_cmd_pool =
7395 pci_alloc_consistent(h->pdev,
7396 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
7397 &(h->ioaccel_cmd_pool_dhandle));
7398
7399 h->ioaccel1_blockFetchTable =
283b4a9b 7400 kmalloc(((h->ioaccel_maxsg + 1) *
e1f7de0c
MG		 7401 sizeof(u32)), GFP_KERNEL);
7402
7403 if ((h->ioaccel_cmd_pool == NULL) ||
7404 (h->ioaccel1_blockFetchTable == NULL))
7405 goto clean_up;
7406
7407 memset(h->ioaccel_cmd_pool, 0,
7408 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool));
7409 return 0;
7410
7411clean_up:
7412 if (h->ioaccel_cmd_pool)
7413 pci_free_consistent(h->pdev,
7414 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
7415 h->ioaccel_cmd_pool, h->ioaccel_cmd_pool_dhandle);
7416 kfree(h->ioaccel1_blockFetchTable);
7417 return 1;
6c311b57
SC		 7418}
7419
aca9012a
SC		 7420static int ioaccel2_alloc_cmds_and_bft(struct ctlr_info *h)
7421{
7422 /* Allocate ioaccel2 mode command blocks and block fetch table */
7423
7424 h->ioaccel_maxsg =
7425 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
7426 if (h->ioaccel_maxsg > IOACCEL2_MAXSGENTRIES)
7427 h->ioaccel_maxsg = IOACCEL2_MAXSGENTRIES;
7428
7429#define IOACCEL2_COMMANDLIST_ALIGNMENT 128
7430 BUILD_BUG_ON(sizeof(struct io_accel2_cmd) %
7431 IOACCEL2_COMMANDLIST_ALIGNMENT);
7432 h->ioaccel2_cmd_pool =
7433 pci_alloc_consistent(h->pdev,
7434 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
7435 &(h->ioaccel2_cmd_pool_dhandle));
7436
7437 h->ioaccel2_blockFetchTable =
7438 kmalloc(((h->ioaccel_maxsg + 1) *
7439 sizeof(u32)), GFP_KERNEL);
7440
7441 if ((h->ioaccel2_cmd_pool == NULL) ||
7442 (h->ioaccel2_blockFetchTable == NULL))
7443 goto clean_up;
7444
7445 memset(h->ioaccel2_cmd_pool, 0,
7446 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool));
7447 return 0;
7448
7449clean_up:
7450 if (h->ioaccel2_cmd_pool)
7451 pci_free_consistent(h->pdev,
7452 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
7453 h->ioaccel2_cmd_pool, h->ioaccel2_cmd_pool_dhandle);
7454 kfree(h->ioaccel2_blockFetchTable);
7455 return 1;
7456}
7457
6f039790 7458static void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h)
6c311b57
SC		 7459{
7460 u32 trans_support;
e1f7de0c
MG		 7461 unsigned long transMethod = CFGTBL_Trans_Performant |
7462 CFGTBL_Trans_use_short_tags;
254f796b 7463 int i;
6c311b57 7464
02ec19c8
SC		 7465 if (hpsa_simple_mode)
7466 return;
7467
67c99a72 7468 trans_support = readl(&(h->cfgtable->TransportSupport));
7469 if (!(trans_support & PERFORMANT_MODE))
7470 return;
7471
e1f7de0c
MG		 7472 /* Check for I/O accelerator mode support */
7473 if (trans_support & CFGTBL_Trans_io_accel1) {
7474 transMethod |= CFGTBL_Trans_io_accel1 |
7475 CFGTBL_Trans_enable_directed_msix;
7476 if (hpsa_alloc_ioaccel_cmd_and_bft(h))
7477 goto clean_up;
aca9012a
SC		 7478 } else {
7479 if (trans_support & CFGTBL_Trans_io_accel2) {
7480 transMethod |= CFGTBL_Trans_io_accel2 |
7481 CFGTBL_Trans_enable_directed_msix;
7482 if (ioaccel2_alloc_cmds_and_bft(h))
7483 goto clean_up;
7484 }
e1f7de0c
MG		 7485 }
7486
7487 /* TODO, check that this next line h->nreply_queues is correct */
eee0f03a 7488 h->nreply_queues = h->msix_vector > 0 ? h->msix_vector : 1;
cba3d38b 7489 hpsa_get_max_perf_mode_cmds(h);
6c311b57 7490 /* Performant mode ring buffer and supporting data structures */
254f796b 7491 h->reply_pool_size = h->max_commands * sizeof(u64) * h->nreply_queues;
6c311b57
SC		 7492 h->reply_pool = pci_alloc_consistent(h->pdev, h->reply_pool_size,
7493 &(h->reply_pool_dhandle));
7494
254f796b
MG		 7495 for (i = 0; i < h->nreply_queues; i++) {
7496 h->reply_queue[i].head = &h->reply_pool[h->max_commands * i];
7497 h->reply_queue[i].size = h->max_commands;
7498 h->reply_queue[i].wraparound = 1; /* spec: init to 1 */
7499 h->reply_queue[i].current_entry = 0;
7500 }
7501
6c311b57 7502 /* Need a block fetch table for performant mode */
d66ae08b 7503 h->blockFetchTable = kmalloc(((SG_ENTRIES_IN_CMD + 1) *
6c311b57
SC		 7504 sizeof(u32)), GFP_KERNEL);
7505
7506 if ((h->reply_pool == NULL)
7507 || (h->blockFetchTable == NULL))
7508 goto clean_up;
7509
e1f7de0c 7510 hpsa_enter_performant_mode(h, trans_support);
303932fd
DB		 7511 return;
7512
7513clean_up:
7514 if (h->reply_pool)
7515 pci_free_consistent(h->pdev, h->reply_pool_size,
7516 h->reply_pool, h->reply_pool_dhandle);
7517 kfree(h->blockFetchTable);
7518}
7519
23100dd9 7520static int is_accelerated_cmd(struct CommandList *c)
76438d08 7521{
23100dd9
SC		 7522 return c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_IOACCEL2;
7523}
7524
7525static void hpsa_drain_accel_commands(struct ctlr_info *h)
7526{
7527 struct CommandList *c = NULL;
76438d08 7528 unsigned long flags;
23100dd9 7529 int accel_cmds_out;
76438d08
SC		 7530
7531 do { /* wait for all outstanding commands to drain out */
23100dd9 7532 accel_cmds_out = 0;
76438d08 7533 spin_lock_irqsave(&h->lock, flags);
23100dd9
SC		 7534 list_for_each_entry(c, &h->cmpQ, list)
7535 accel_cmds_out += is_accelerated_cmd(c);
7536 list_for_each_entry(c, &h->reqQ, list)
7537 accel_cmds_out += is_accelerated_cmd(c);
76438d08 7538 spin_unlock_irqrestore(&h->lock, flags);
23100dd9 7539 if (accel_cmds_out <= 0)
76438d08
SC		 7540 break;
7541 msleep(100);
7542 } while (1);
7543}
7544
edd16368
SC		 7545/*
7546 * This is it. Register the PCI driver information for the cards we control
7547 * the OS will call our registered routines when it finds one of our cards.
7548 */
7549static int __init hpsa_init(void)
7550{
31468401 7551 return pci_register_driver(&hpsa_pci_driver);
edd16368
SC		 7552}
7553
7554static void __exit hpsa_cleanup(void)
7555{
7556 pci_unregister_driver(&hpsa_pci_driver);
edd16368
SC		 7557}
7558
e1f7de0c
MG		 7559static void __attribute__((unused)) verify_offsets(void)
7560{
dd0e19f3
ST		 7561#define VERIFY_OFFSET(member, offset) \
7562 BUILD_BUG_ON(offsetof(struct raid_map_data, member) != offset)
7563
7564 VERIFY_OFFSET(structure_size, 0);
7565 VERIFY_OFFSET(volume_blk_size, 4);
7566 VERIFY_OFFSET(volume_blk_cnt, 8);
7567 VERIFY_OFFSET(phys_blk_shift, 16);
7568 VERIFY_OFFSET(parity_rotation_shift, 17);
7569 VERIFY_OFFSET(strip_size, 18);
7570 VERIFY_OFFSET(disk_starting_blk, 20);
7571 VERIFY_OFFSET(disk_blk_cnt, 28);
7572 VERIFY_OFFSET(data_disks_per_row, 36);
7573 VERIFY_OFFSET(metadata_disks_per_row, 38);
7574 VERIFY_OFFSET(row_cnt, 40);
7575 VERIFY_OFFSET(layout_map_count, 42);
7576 VERIFY_OFFSET(flags, 44);
7577 VERIFY_OFFSET(dekindex, 46);
7578 /* VERIFY_OFFSET(reserved, 48 */
7579 VERIFY_OFFSET(data, 64);
7580
7581#undef VERIFY_OFFSET
7582
b66cc250
MM		 7583#define VERIFY_OFFSET(member, offset) \
7584 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, member) != offset)
7585
7586 VERIFY_OFFSET(IU_type, 0);
7587 VERIFY_OFFSET(direction, 1);
7588 VERIFY_OFFSET(reply_queue, 2);
7589 /* VERIFY_OFFSET(reserved1, 3); */
7590 VERIFY_OFFSET(scsi_nexus, 4);
7591 VERIFY_OFFSET(Tag, 8);
7592 VERIFY_OFFSET(cdb, 16);
7593 VERIFY_OFFSET(cciss_lun, 32);
7594 VERIFY_OFFSET(data_len, 40);
7595 VERIFY_OFFSET(cmd_priority_task_attr, 44);
7596 VERIFY_OFFSET(sg_count, 45);
7597 /* VERIFY_OFFSET(reserved3 */
7598 VERIFY_OFFSET(err_ptr, 48);
7599 VERIFY_OFFSET(err_len, 56);
7600 /* VERIFY_OFFSET(reserved4 */
7601 VERIFY_OFFSET(sg, 64);
7602
7603#undef VERIFY_OFFSET
7604
e1f7de0c
MG		 7605#define VERIFY_OFFSET(member, offset) \
7606 BUILD_BUG_ON(offsetof(struct io_accel1_cmd, member) != offset)
7607
7608 VERIFY_OFFSET(dev_handle, 0x00);
7609 VERIFY_OFFSET(reserved1, 0x02);
7610 VERIFY_OFFSET(function, 0x03);
7611 VERIFY_OFFSET(reserved2, 0x04);
7612 VERIFY_OFFSET(err_info, 0x0C);
7613 VERIFY_OFFSET(reserved3, 0x10);
7614 VERIFY_OFFSET(err_info_len, 0x12);
7615 VERIFY_OFFSET(reserved4, 0x13);
7616 VERIFY_OFFSET(sgl_offset, 0x14);
7617 VERIFY_OFFSET(reserved5, 0x15);
7618 VERIFY_OFFSET(transfer_len, 0x1C);
7619 VERIFY_OFFSET(reserved6, 0x20);
7620 VERIFY_OFFSET(io_flags, 0x24);
7621 VERIFY_OFFSET(reserved7, 0x26);
7622 VERIFY_OFFSET(LUN, 0x34);
7623 VERIFY_OFFSET(control, 0x3C);
7624 VERIFY_OFFSET(CDB, 0x40);
7625 VERIFY_OFFSET(reserved8, 0x50);
7626 VERIFY_OFFSET(host_context_flags, 0x60);
7627 VERIFY_OFFSET(timeout_sec, 0x62);
7628 VERIFY_OFFSET(ReplyQueue, 0x64);
7629 VERIFY_OFFSET(reserved9, 0x65);
7630 VERIFY_OFFSET(Tag, 0x68);
7631 VERIFY_OFFSET(host_addr, 0x70);
7632 VERIFY_OFFSET(CISS_LUN, 0x78);
7633 VERIFY_OFFSET(SG, 0x78 + 8);
7634#undef VERIFY_OFFSET
7635}
7636
edd16368
SC		 7637module_init(hpsa_init);
7638module_exit(hpsa_cleanup);
Linux kernel - Deliverables
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