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hpsa: get rid of cmd_special_alloc and cmd_special_free
[deliverable/linux.git] / drivers / scsi / hpsa.c
CommitLineData
edd16368
SC		 1/*
2 * Disk Array driver for HP Smart Array SAS controllers
51c35139 3 * Copyright 2000, 2014 Hewlett-Packard Development Company, L.P.
edd16368
SC		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
12 * NON INFRINGEMENT. See the GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 *
18 * Questions/Comments/Bugfixes to iss_storagedev@hp.com
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/interrupt.h>
24#include <linux/types.h>
25#include <linux/pci.h>
e5a44df8 26#include <linux/pci-aspm.h>
edd16368
SC		 27#include <linux/kernel.h>
28#include <linux/slab.h>
29#include <linux/delay.h>
30#include <linux/fs.h>
31#include <linux/timer.h>
edd16368
SC		 32#include <linux/init.h>
33#include <linux/spinlock.h>
edd16368
SC		 34#include <linux/compat.h>
35#include <linux/blktrace_api.h>
36#include <linux/uaccess.h>
37#include <linux/io.h>
38#include <linux/dma-mapping.h>
39#include <linux/completion.h>
40#include <linux/moduleparam.h>
41#include <scsi/scsi.h>
42#include <scsi/scsi_cmnd.h>
43#include <scsi/scsi_device.h>
44#include <scsi/scsi_host.h>
667e23d4 45#include <scsi/scsi_tcq.h>
edd16368
SC		 46#include <linux/cciss_ioctl.h>
47#include <linux/string.h>
48#include <linux/bitmap.h>
60063497 49#include <linux/atomic.h>
a0c12413 50#include <linux/jiffies.h>
42a91641 51#include <linux/percpu-defs.h>
094963da 52#include <linux/percpu.h>
2b08b3e9 53#include <asm/unaligned.h>
283b4a9b 54#include <asm/div64.h>
edd16368
SC		 55#include "hpsa_cmd.h"
56#include "hpsa.h"
57
58/* HPSA_DRIVER_VERSION must be 3 byte values (0-255) separated by '.' */
9a993302 59#define HPSA_DRIVER_VERSION "3.4.4-1"
edd16368 60#define DRIVER_NAME "HP HPSA Driver (v " HPSA_DRIVER_VERSION ")"
f79cfec6 61#define HPSA "hpsa"
edd16368
SC		 62
63/* How long to wait (in milliseconds) for board to go into simple mode */
64#define MAX_CONFIG_WAIT 30000
65#define MAX_IOCTL_CONFIG_WAIT 1000
66
67/*define how many times we will try a command because of bus resets */
68#define MAX_CMD_RETRIES 3
69
70/* Embedded module documentation macros - see modules.h */
71MODULE_AUTHOR("Hewlett-Packard Company");
72MODULE_DESCRIPTION("Driver for HP Smart Array Controller version " \
73 HPSA_DRIVER_VERSION);
74MODULE_SUPPORTED_DEVICE("HP Smart Array Controllers");
75MODULE_VERSION(HPSA_DRIVER_VERSION);
76MODULE_LICENSE("GPL");
77
78static int hpsa_allow_any;
79module_param(hpsa_allow_any, int, S_IRUGO|S_IWUSR);
80MODULE_PARM_DESC(hpsa_allow_any,
81 "Allow hpsa driver to access unknown HP Smart Array hardware");
02ec19c8
SC		 82static int hpsa_simple_mode;
83module_param(hpsa_simple_mode, int, S_IRUGO|S_IWUSR);
84MODULE_PARM_DESC(hpsa_simple_mode,
85 "Use 'simple mode' rather than 'performant mode'");
edd16368
SC		 86
87/* define the PCI info for the cards we can control */
88static const struct pci_device_id hpsa_pci_device_id[] = {
edd16368
SC		 89 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3241},
90 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3243},
91 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3245},
92 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3247},
93 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3249},
163dbcd8
MM		 94 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324A},
95 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324B},
f8b01eb9 96 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3233},
9143a961 97 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3350},
98 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3351},
99 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3352},
100 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3353},
101 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3354},
102 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3355},
103 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3356},
fe0c9610
MM		 104 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1921},
105 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1922},
106 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1923},
107 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1924},
fe0c9610
MM		 108 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1926},
109 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1928},
97b9f53d
MM		 110 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1929},
111 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BD},
112 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BE},
113 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BF},
114 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C0},
115 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C1},
116 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C2},
117 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C3},
118 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C4},
119 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C5},
3b7a45e5 120 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C6},
97b9f53d
MM		 121 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C7},
122 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C8},
123 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C9},
3b7a45e5
JH		 124 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CA},
125 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CB},
126 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CC},
127 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CD},
128 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CE},
8e616a5e
SC		 129 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0076},
130 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0087},
131 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x007D},
132 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0088},
133 {PCI_VENDOR_ID_HP, 0x333f, 0x103c, 0x333f},
7c03b870 134 {PCI_VENDOR_ID_HP, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
6798cc0a 135 PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0},
edd16368
SC		 136 {0,}
137};
138
139MODULE_DEVICE_TABLE(pci, hpsa_pci_device_id);
140
141/* board_id = Subsystem Device ID & Vendor ID
142 * product = Marketing Name for the board
143 * access = Address of the struct of function pointers
144 */
145static struct board_type products[] = {
edd16368
SC		 146 {0x3241103C, "Smart Array P212", &SA5_access},
147 {0x3243103C, "Smart Array P410", &SA5_access},
148 {0x3245103C, "Smart Array P410i", &SA5_access},
149 {0x3247103C, "Smart Array P411", &SA5_access},
150 {0x3249103C, "Smart Array P812", &SA5_access},
163dbcd8
MM		 151 {0x324A103C, "Smart Array P712m", &SA5_access},
152 {0x324B103C, "Smart Array P711m", &SA5_access},
7d2cce58 153 {0x3233103C, "HP StorageWorks 1210m", &SA5_access}, /* alias of 333f */
fe0c9610
MM		 154 {0x3350103C, "Smart Array P222", &SA5_access},
155 {0x3351103C, "Smart Array P420", &SA5_access},
156 {0x3352103C, "Smart Array P421", &SA5_access},
157 {0x3353103C, "Smart Array P822", &SA5_access},
158 {0x3354103C, "Smart Array P420i", &SA5_access},
159 {0x3355103C, "Smart Array P220i", &SA5_access},
160 {0x3356103C, "Smart Array P721m", &SA5_access},
1fd6c8e3
MM		 161 {0x1921103C, "Smart Array P830i", &SA5_access},
162 {0x1922103C, "Smart Array P430", &SA5_access},
163 {0x1923103C, "Smart Array P431", &SA5_access},
164 {0x1924103C, "Smart Array P830", &SA5_access},
165 {0x1926103C, "Smart Array P731m", &SA5_access},
166 {0x1928103C, "Smart Array P230i", &SA5_access},
167 {0x1929103C, "Smart Array P530", &SA5_access},
97b9f53d
MM		 168 {0x21BD103C, "Smart Array", &SA5_access},
169 {0x21BE103C, "Smart Array", &SA5_access},
170 {0x21BF103C, "Smart Array", &SA5_access},
171 {0x21C0103C, "Smart Array", &SA5_access},
172 {0x21C1103C, "Smart Array", &SA5_access},
173 {0x21C2103C, "Smart Array", &SA5_access},
174 {0x21C3103C, "Smart Array", &SA5_access},
175 {0x21C4103C, "Smart Array", &SA5_access},
176 {0x21C5103C, "Smart Array", &SA5_access},
3b7a45e5 177 {0x21C6103C, "Smart Array", &SA5_access},
97b9f53d
MM		 178 {0x21C7103C, "Smart Array", &SA5_access},
179 {0x21C8103C, "Smart Array", &SA5_access},
180 {0x21C9103C, "Smart Array", &SA5_access},
3b7a45e5
JH		 181 {0x21CA103C, "Smart Array", &SA5_access},
182 {0x21CB103C, "Smart Array", &SA5_access},
183 {0x21CC103C, "Smart Array", &SA5_access},
184 {0x21CD103C, "Smart Array", &SA5_access},
185 {0x21CE103C, "Smart Array", &SA5_access},
8e616a5e
SC		 186 {0x00761590, "HP Storage P1224 Array Controller", &SA5_access},
187 {0x00871590, "HP Storage P1224e Array Controller", &SA5_access},
188 {0x007D1590, "HP Storage P1228 Array Controller", &SA5_access},
189 {0x00881590, "HP Storage P1228e Array Controller", &SA5_access},
190 {0x333f103c, "HP StorageWorks 1210m Array Controller", &SA5_access},
edd16368
SC		 191 {0xFFFF103C, "Unknown Smart Array", &SA5_access},
192};
193
194static int number_of_controllers;
195
10f66018
SC		 196static irqreturn_t do_hpsa_intr_intx(int irq, void *dev_id);
197static irqreturn_t do_hpsa_intr_msi(int irq, void *dev_id);
42a91641 198static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg);
0b57075d
SC		 199static void lock_and_start_io(struct ctlr_info *h);
200static void start_io(struct ctlr_info *h, unsigned long *flags);
edd16368
SC		 201
202#ifdef CONFIG_COMPAT
42a91641
DB		 203static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd,
204 void __user *arg);
edd16368
SC		 205#endif
206
207static void cmd_free(struct ctlr_info *h, struct CommandList *c);
edd16368 208static struct CommandList *cmd_alloc(struct ctlr_info *h);
a2dac136 209static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
b7bb24eb 210 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
edd16368 211 int cmd_type);
2c143342 212static void hpsa_free_cmd_pool(struct ctlr_info *h);
b7bb24eb 213#define VPD_PAGE (1 << 8)
edd16368 214
f281233d 215static int hpsa_scsi_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd);
a08a8471
SC		 216static void hpsa_scan_start(struct Scsi_Host *);
217static int hpsa_scan_finished(struct Scsi_Host *sh,
218 unsigned long elapsed_time);
7c0a0229 219static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth);
edd16368
SC		 220
221static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd);
75167d2c 222static int hpsa_eh_abort_handler(struct scsi_cmnd *scsicmd);
edd16368
SC		 223static int hpsa_slave_alloc(struct scsi_device *sdev);
224static void hpsa_slave_destroy(struct scsi_device *sdev);
225
edd16368 226static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno);
edd16368
SC		 227static int check_for_unit_attention(struct ctlr_info *h,
228 struct CommandList *c);
229static void check_ioctl_unit_attention(struct ctlr_info *h,
230 struct CommandList *c);
303932fd
DB		 231/* performant mode helper functions */
232static void calc_bucket_map(int *bucket, int num_buckets,
2b08b3e9 233 int nsgs, int min_blocks, u32 *bucket_map);
6f039790 234static void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h);
254f796b 235static inline u32 next_command(struct ctlr_info *h, u8 q);
6f039790
GKH		 236static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
237 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
238 u64 *cfg_offset);
239static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
240 unsigned long *memory_bar);
241static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id);
242static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
243 int wait_for_ready);
75167d2c 244static inline void finish_cmd(struct CommandList *c);
283b4a9b 245static void hpsa_wait_for_mode_change_ack(struct ctlr_info *h);
fe5389c8
SC		 246#define BOARD_NOT_READY 0
247#define BOARD_READY 1
23100dd9 248static void hpsa_drain_accel_commands(struct ctlr_info *h);
76438d08 249static void hpsa_flush_cache(struct ctlr_info *h);
c349775e
ST		 250static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
251 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
252 u8 *scsi3addr);
edd16368 253
edd16368
SC		 254static inline struct ctlr_info *sdev_to_hba(struct scsi_device *sdev)
255{
256 unsigned long *priv = shost_priv(sdev->host);
257 return (struct ctlr_info *) *priv;
258}
259
a23513e8
SC		 260static inline struct ctlr_info *shost_to_hba(struct Scsi_Host *sh)
261{
262 unsigned long *priv = shost_priv(sh);
263 return (struct ctlr_info *) *priv;
264}
265
edd16368
SC		 266static int check_for_unit_attention(struct ctlr_info *h,
267 struct CommandList *c)
268{
269 if (c->err_info->SenseInfo[2] != UNIT_ATTENTION)
270 return 0;
271
272 switch (c->err_info->SenseInfo[12]) {
273 case STATE_CHANGED:
f79cfec6 274 dev_warn(&h->pdev->dev, HPSA "%d: a state change "
edd16368
SC		 275 "detected, command retried\n", h->ctlr);
276 break;
277 case LUN_FAILED:
7f73695a
SC		 278 dev_warn(&h->pdev->dev,
279 HPSA "%d: LUN failure detected\n", h->ctlr);
edd16368
SC		 280 break;
281 case REPORT_LUNS_CHANGED:
7f73695a
SC		 282 dev_warn(&h->pdev->dev,
283 HPSA "%d: report LUN data changed\n", h->ctlr);
edd16368 284 /*
4f4eb9f1
ST		 285 * Note: this REPORT_LUNS_CHANGED condition only occurs on the external
286 * target (array) devices.
edd16368
SC		 287 */
288 break;
289 case POWER_OR_RESET:
f79cfec6 290 dev_warn(&h->pdev->dev, HPSA "%d: a power on "
edd16368
SC		 291 "or device reset detected\n", h->ctlr);
292 break;
293 case UNIT_ATTENTION_CLEARED:
f79cfec6 294 dev_warn(&h->pdev->dev, HPSA "%d: unit attention "
edd16368
SC		 295 "cleared by another initiator\n", h->ctlr);
296 break;
297 default:
f79cfec6 298 dev_warn(&h->pdev->dev, HPSA "%d: unknown "
edd16368
SC		 299 "unit attention detected\n", h->ctlr);
300 break;
301 }
302 return 1;
303}
304
852af20a
MB		 305static int check_for_busy(struct ctlr_info *h, struct CommandList *c)
306{
307 if (c->err_info->CommandStatus != CMD_TARGET_STATUS ||
308 (c->err_info->ScsiStatus != SAM_STAT_BUSY &&
309 c->err_info->ScsiStatus != SAM_STAT_TASK_SET_FULL))
310 return 0;
311 dev_warn(&h->pdev->dev, HPSA "device busy");
312 return 1;
313}
314
da0697bd
ST		 315static ssize_t host_store_hp_ssd_smart_path_status(struct device *dev,
316 struct device_attribute *attr,
317 const char *buf, size_t count)
318{
319 int status, len;
320 struct ctlr_info *h;
321 struct Scsi_Host *shost = class_to_shost(dev);
322 char tmpbuf[10];
323
324 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
325 return -EACCES;
326 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
327 strncpy(tmpbuf, buf, len);
328 tmpbuf[len] = '\0';
329 if (sscanf(tmpbuf, "%d", &status) != 1)
330 return -EINVAL;
331 h = shost_to_hba(shost);
332 h->acciopath_status = !!status;
333 dev_warn(&h->pdev->dev,
334 "hpsa: HP SSD Smart Path %s via sysfs update.\n",
335 h->acciopath_status ? "enabled" : "disabled");
336 return count;
337}
338
2ba8bfc8
SC		 339static ssize_t host_store_raid_offload_debug(struct device *dev,
340 struct device_attribute *attr,
341 const char *buf, size_t count)
342{
343 int debug_level, len;
344 struct ctlr_info *h;
345 struct Scsi_Host *shost = class_to_shost(dev);
346 char tmpbuf[10];
347
348 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
349 return -EACCES;
350 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
351 strncpy(tmpbuf, buf, len);
352 tmpbuf[len] = '\0';
353 if (sscanf(tmpbuf, "%d", &debug_level) != 1)
354 return -EINVAL;
355 if (debug_level < 0)
356 debug_level = 0;
357 h = shost_to_hba(shost);
358 h->raid_offload_debug = debug_level;
359 dev_warn(&h->pdev->dev, "hpsa: Set raid_offload_debug level = %d\n",
360 h->raid_offload_debug);
361 return count;
362}
363
edd16368
SC		 364static ssize_t host_store_rescan(struct device *dev,
365 struct device_attribute *attr,
366 const char *buf, size_t count)
367{
368 struct ctlr_info *h;
369 struct Scsi_Host *shost = class_to_shost(dev);
a23513e8 370 h = shost_to_hba(shost);
31468401 371 hpsa_scan_start(h->scsi_host);
edd16368
SC		 372 return count;
373}
374
d28ce020
SC		 375static ssize_t host_show_firmware_revision(struct device *dev,
376 struct device_attribute *attr, char *buf)
377{
378 struct ctlr_info *h;
379 struct Scsi_Host *shost = class_to_shost(dev);
380 unsigned char *fwrev;
381
382 h = shost_to_hba(shost);
383 if (!h->hba_inquiry_data)
384 return 0;
385 fwrev = &h->hba_inquiry_data[32];
386 return snprintf(buf, 20, "%c%c%c%c\n",
387 fwrev[0], fwrev[1], fwrev[2], fwrev[3]);
388}
389
94a13649
SC		 390static ssize_t host_show_commands_outstanding(struct device *dev,
391 struct device_attribute *attr, char *buf)
392{
393 struct Scsi_Host *shost = class_to_shost(dev);
394 struct ctlr_info *h = shost_to_hba(shost);
395
0cbf768e
SC		 396 return snprintf(buf, 20, "%d\n",
397 atomic_read(&h->commands_outstanding));
94a13649
SC		 398}
399
745a7a25
SC		 400static ssize_t host_show_transport_mode(struct device *dev,
401 struct device_attribute *attr, char *buf)
402{
403 struct ctlr_info *h;
404 struct Scsi_Host *shost = class_to_shost(dev);
405
406 h = shost_to_hba(shost);
407 return snprintf(buf, 20, "%s\n",
960a30e7 408 h->transMethod & CFGTBL_Trans_Performant ?
745a7a25
SC		 409 "performant" : "simple");
410}
411
da0697bd
ST		 412static ssize_t host_show_hp_ssd_smart_path_status(struct device *dev,
413 struct device_attribute *attr, char *buf)
414{
415 struct ctlr_info *h;
416 struct Scsi_Host *shost = class_to_shost(dev);
417
418 h = shost_to_hba(shost);
419 return snprintf(buf, 30, "HP SSD Smart Path %s\n",
420 (h->acciopath_status == 1) ? "enabled" : "disabled");
421}
422
46380786 423/* List of controllers which cannot be hard reset on kexec with reset_devices */
941b1cda
SC		 424static u32 unresettable_controller[] = {
425 0x324a103C, /* Smart Array P712m */
426 0x324b103C, /* SmartArray P711m */
427 0x3223103C, /* Smart Array P800 */
428 0x3234103C, /* Smart Array P400 */
429 0x3235103C, /* Smart Array P400i */
430 0x3211103C, /* Smart Array E200i */
431 0x3212103C, /* Smart Array E200 */
432 0x3213103C, /* Smart Array E200i */
433 0x3214103C, /* Smart Array E200i */
434 0x3215103C, /* Smart Array E200i */
435 0x3237103C, /* Smart Array E500 */
436 0x323D103C, /* Smart Array P700m */
7af0abbc 437 0x40800E11, /* Smart Array 5i */
941b1cda
SC		 438 0x409C0E11, /* Smart Array 6400 */
439 0x409D0E11, /* Smart Array 6400 EM */
5a4f934e
TH		 440 0x40700E11, /* Smart Array 5300 */
441 0x40820E11, /* Smart Array 532 */
442 0x40830E11, /* Smart Array 5312 */
443 0x409A0E11, /* Smart Array 641 */
444 0x409B0E11, /* Smart Array 642 */
445 0x40910E11, /* Smart Array 6i */
941b1cda
SC		 446};
447
46380786
SC		 448/* List of controllers which cannot even be soft reset */
449static u32 soft_unresettable_controller[] = {
7af0abbc 450 0x40800E11, /* Smart Array 5i */
5a4f934e
TH		 451 0x40700E11, /* Smart Array 5300 */
452 0x40820E11, /* Smart Array 532 */
453 0x40830E11, /* Smart Array 5312 */
454 0x409A0E11, /* Smart Array 641 */
455 0x409B0E11, /* Smart Array 642 */
456 0x40910E11, /* Smart Array 6i */
46380786
SC		 457 /* Exclude 640x boards. These are two pci devices in one slot
458 * which share a battery backed cache module. One controls the
459 * cache, the other accesses the cache through the one that controls
460 * it. If we reset the one controlling the cache, the other will
461 * likely not be happy. Just forbid resetting this conjoined mess.
462 * The 640x isn't really supported by hpsa anyway.
463 */
464 0x409C0E11, /* Smart Array 6400 */
465 0x409D0E11, /* Smart Array 6400 EM */
466};
467
468static int ctlr_is_hard_resettable(u32 board_id)
941b1cda
SC		 469{
470 int i;
471
472 for (i = 0; i < ARRAY_SIZE(unresettable_controller); i++)
46380786
SC		 473 if (unresettable_controller[i] == board_id)
474 return 0;
475 return 1;
476}
477
478static int ctlr_is_soft_resettable(u32 board_id)
479{
480 int i;
481
482 for (i = 0; i < ARRAY_SIZE(soft_unresettable_controller); i++)
483 if (soft_unresettable_controller[i] == board_id)
941b1cda
SC		 484 return 0;
485 return 1;
486}
487
46380786
SC		 488static int ctlr_is_resettable(u32 board_id)
489{
490 return ctlr_is_hard_resettable(board_id) ||
491 ctlr_is_soft_resettable(board_id);
492}
493
941b1cda
SC		 494static ssize_t host_show_resettable(struct device *dev,
495 struct device_attribute *attr, char *buf)
496{
497 struct ctlr_info *h;
498 struct Scsi_Host *shost = class_to_shost(dev);
499
500 h = shost_to_hba(shost);
46380786 501 return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h->board_id));
941b1cda
SC		 502}
503
edd16368
SC		 504static inline int is_logical_dev_addr_mode(unsigned char scsi3addr[])
505{
506 return (scsi3addr[3] & 0xC0) == 0x40;
507}
508
f2ef0ce7
RE		 509static const char * const raid_label[] = { "0", "4", "1(+0)", "5", "5+1", "6",
510 "1(+0)ADM", "UNKNOWN"
edd16368 511};
6b80b18f
ST		 512#define HPSA_RAID_0 0
513#define HPSA_RAID_4 1
514#define HPSA_RAID_1 2 /* also used for RAID 10 */
515#define HPSA_RAID_5 3 /* also used for RAID 50 */
516#define HPSA_RAID_51 4
517#define HPSA_RAID_6 5 /* also used for RAID 60 */
518#define HPSA_RAID_ADM 6 /* also used for RAID 1+0 ADM */
edd16368
SC		 519#define RAID_UNKNOWN (ARRAY_SIZE(raid_label) - 1)
520
521static ssize_t raid_level_show(struct device *dev,
522 struct device_attribute *attr, char *buf)
523{
524 ssize_t l = 0;
82a72c0a 525 unsigned char rlevel;
edd16368
SC		 526 struct ctlr_info *h;
527 struct scsi_device *sdev;
528 struct hpsa_scsi_dev_t *hdev;
529 unsigned long flags;
530
531 sdev = to_scsi_device(dev);
532 h = sdev_to_hba(sdev);
533 spin_lock_irqsave(&h->lock, flags);
534 hdev = sdev->hostdata;
535 if (!hdev) {
536 spin_unlock_irqrestore(&h->lock, flags);
537 return -ENODEV;
538 }
539
540 /* Is this even a logical drive? */
541 if (!is_logical_dev_addr_mode(hdev->scsi3addr)) {
542 spin_unlock_irqrestore(&h->lock, flags);
543 l = snprintf(buf, PAGE_SIZE, "N/A\n");
544 return l;
545 }
546
547 rlevel = hdev->raid_level;
548 spin_unlock_irqrestore(&h->lock, flags);
82a72c0a 549 if (rlevel > RAID_UNKNOWN)
edd16368
SC		 550 rlevel = RAID_UNKNOWN;
551 l = snprintf(buf, PAGE_SIZE, "RAID %s\n", raid_label[rlevel]);
552 return l;
553}
554
555static ssize_t lunid_show(struct device *dev,
556 struct device_attribute *attr, char *buf)
557{
558 struct ctlr_info *h;
559 struct scsi_device *sdev;
560 struct hpsa_scsi_dev_t *hdev;
561 unsigned long flags;
562 unsigned char lunid[8];
563
564 sdev = to_scsi_device(dev);
565 h = sdev_to_hba(sdev);
566 spin_lock_irqsave(&h->lock, flags);
567 hdev = sdev->hostdata;
568 if (!hdev) {
569 spin_unlock_irqrestore(&h->lock, flags);
570 return -ENODEV;
571 }
572 memcpy(lunid, hdev->scsi3addr, sizeof(lunid));
573 spin_unlock_irqrestore(&h->lock, flags);
574 return snprintf(buf, 20, "0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
575 lunid[0], lunid[1], lunid[2], lunid[3],
576 lunid[4], lunid[5], lunid[6], lunid[7]);
577}
578
579static ssize_t unique_id_show(struct device *dev,
580 struct device_attribute *attr, char *buf)
581{
582 struct ctlr_info *h;
583 struct scsi_device *sdev;
584 struct hpsa_scsi_dev_t *hdev;
585 unsigned long flags;
586 unsigned char sn[16];
587
588 sdev = to_scsi_device(dev);
589 h = sdev_to_hba(sdev);
590 spin_lock_irqsave(&h->lock, flags);
591 hdev = sdev->hostdata;
592 if (!hdev) {
593 spin_unlock_irqrestore(&h->lock, flags);
594 return -ENODEV;
595 }
596 memcpy(sn, hdev->device_id, sizeof(sn));
597 spin_unlock_irqrestore(&h->lock, flags);
598 return snprintf(buf, 16 * 2 + 2,
599 "%02X%02X%02X%02X%02X%02X%02X%02X"
600 "%02X%02X%02X%02X%02X%02X%02X%02X\n",
601 sn[0], sn[1], sn[2], sn[3],
602 sn[4], sn[5], sn[6], sn[7],
603 sn[8], sn[9], sn[10], sn[11],
604 sn[12], sn[13], sn[14], sn[15]);
605}
606
c1988684
ST		 607static ssize_t host_show_hp_ssd_smart_path_enabled(struct device *dev,
608 struct device_attribute *attr, char *buf)
609{
610 struct ctlr_info *h;
611 struct scsi_device *sdev;
612 struct hpsa_scsi_dev_t *hdev;
613 unsigned long flags;
614 int offload_enabled;
615
616 sdev = to_scsi_device(dev);
617 h = sdev_to_hba(sdev);
618 spin_lock_irqsave(&h->lock, flags);
619 hdev = sdev->hostdata;
620 if (!hdev) {
621 spin_unlock_irqrestore(&h->lock, flags);
622 return -ENODEV;
623 }
624 offload_enabled = hdev->offload_enabled;
625 spin_unlock_irqrestore(&h->lock, flags);
626 return snprintf(buf, 20, "%d\n", offload_enabled);
627}
628
3f5eac3a
SC		 629static DEVICE_ATTR(raid_level, S_IRUGO, raid_level_show, NULL);
630static DEVICE_ATTR(lunid, S_IRUGO, lunid_show, NULL);
631static DEVICE_ATTR(unique_id, S_IRUGO, unique_id_show, NULL);
632static DEVICE_ATTR(rescan, S_IWUSR, NULL, host_store_rescan);
c1988684
ST		 633static DEVICE_ATTR(hp_ssd_smart_path_enabled, S_IRUGO,
634 host_show_hp_ssd_smart_path_enabled, NULL);
da0697bd
ST		 635static DEVICE_ATTR(hp_ssd_smart_path_status, S_IWUSR|S_IRUGO|S_IROTH,
636 host_show_hp_ssd_smart_path_status,
637 host_store_hp_ssd_smart_path_status);
2ba8bfc8
SC		 638static DEVICE_ATTR(raid_offload_debug, S_IWUSR, NULL,
639 host_store_raid_offload_debug);
3f5eac3a
SC		 640static DEVICE_ATTR(firmware_revision, S_IRUGO,
641 host_show_firmware_revision, NULL);
642static DEVICE_ATTR(commands_outstanding, S_IRUGO,
643 host_show_commands_outstanding, NULL);
644static DEVICE_ATTR(transport_mode, S_IRUGO,
645 host_show_transport_mode, NULL);
941b1cda
SC		 646static DEVICE_ATTR(resettable, S_IRUGO,
647 host_show_resettable, NULL);
3f5eac3a
SC		 648
649static struct device_attribute *hpsa_sdev_attrs[] = {
650 &dev_attr_raid_level,
651 &dev_attr_lunid,
652 &dev_attr_unique_id,
c1988684 653 &dev_attr_hp_ssd_smart_path_enabled,
3f5eac3a
SC		 654 NULL,
655};
656
657static struct device_attribute *hpsa_shost_attrs[] = {
658 &dev_attr_rescan,
659 &dev_attr_firmware_revision,
660 &dev_attr_commands_outstanding,
661 &dev_attr_transport_mode,
941b1cda 662 &dev_attr_resettable,
da0697bd 663 &dev_attr_hp_ssd_smart_path_status,
2ba8bfc8 664 &dev_attr_raid_offload_debug,
3f5eac3a
SC		 665 NULL,
666};
667
668static struct scsi_host_template hpsa_driver_template = {
669 .module = THIS_MODULE,
f79cfec6
SC		 670 .name = HPSA,
671 .proc_name = HPSA,
3f5eac3a
SC		 672 .queuecommand = hpsa_scsi_queue_command,
673 .scan_start = hpsa_scan_start,
674 .scan_finished = hpsa_scan_finished,
7c0a0229 675 .change_queue_depth = hpsa_change_queue_depth,
3f5eac3a
SC		 676 .this_id = -1,
677 .use_clustering = ENABLE_CLUSTERING,
75167d2c 678 .eh_abort_handler = hpsa_eh_abort_handler,
3f5eac3a
SC		 679 .eh_device_reset_handler = hpsa_eh_device_reset_handler,
680 .ioctl = hpsa_ioctl,
681 .slave_alloc = hpsa_slave_alloc,
682 .slave_destroy = hpsa_slave_destroy,
683#ifdef CONFIG_COMPAT
684 .compat_ioctl = hpsa_compat_ioctl,
685#endif
686 .sdev_attrs = hpsa_sdev_attrs,
687 .shost_attrs = hpsa_shost_attrs,
c0d6a4d1 688 .max_sectors = 8192,
54b2b50c 689 .no_write_same = 1,
3f5eac3a
SC		 690};
691
692
693/* Enqueuing and dequeuing functions for cmdlists. */
694static inline void addQ(struct list_head *list, struct CommandList *c)
695{
696 list_add_tail(&c->list, list);
697}
698
254f796b 699static inline u32 next_command(struct ctlr_info *h, u8 q)
3f5eac3a
SC		 700{
701 u32 a;
072b0518 702 struct reply_queue_buffer *rq = &h->reply_queue[q];
3f5eac3a 703
e1f7de0c
MG		 704 if (h->transMethod & CFGTBL_Trans_io_accel1)
705 return h->access.command_completed(h, q);
706
3f5eac3a 707 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
254f796b 708 return h->access.command_completed(h, q);
3f5eac3a 709
254f796b
MG		 710 if ((rq->head[rq->current_entry] & 1) == rq->wraparound) {
711 a = rq->head[rq->current_entry];
712 rq->current_entry++;
0cbf768e 713 atomic_dec(&h->commands_outstanding);
3f5eac3a
SC		 714 } else {
715 a = FIFO_EMPTY;
716 }
717 /* Check for wraparound */
254f796b
MG		 718 if (rq->current_entry == h->max_commands) {
719 rq->current_entry = 0;
720 rq->wraparound ^= 1;
3f5eac3a
SC		 721 }
722 return a;
723}
724
c349775e
ST		 725/*
726 * There are some special bits in the bus address of the
727 * command that we have to set for the controller to know
728 * how to process the command:
729 *
730 * Normal performant mode:
731 * bit 0: 1 means performant mode, 0 means simple mode.
732 * bits 1-3 = block fetch table entry
733 * bits 4-6 = command type (== 0)
734 *
735 * ioaccel1 mode:
736 * bit 0 = "performant mode" bit.
737 * bits 1-3 = block fetch table entry
738 * bits 4-6 = command type (== 110)
739 * (command type is needed because ioaccel1 mode
740 * commands are submitted through the same register as normal
741 * mode commands, so this is how the controller knows whether
742 * the command is normal mode or ioaccel1 mode.)
743 *
744 * ioaccel2 mode:
745 * bit 0 = "performant mode" bit.
746 * bits 1-4 = block fetch table entry (note extra bit)
747 * bits 4-6 = not needed, because ioaccel2 mode has
748 * a separate special register for submitting commands.
749 */
750
3f5eac3a
SC		 751/* set_performant_mode: Modify the tag for cciss performant
752 * set bit 0 for pull model, bits 3-1 for block fetch
753 * register number
754 */
755static void set_performant_mode(struct ctlr_info *h, struct CommandList *c)
756{
254f796b 757 if (likely(h->transMethod & CFGTBL_Trans_Performant)) {
3f5eac3a 758 c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1);
eee0f03a 759 if (likely(h->msix_vector > 0))
254f796b 760 c->Header.ReplyQueue =
804a5cb5 761 raw_smp_processor_id() % h->nreply_queues;
254f796b 762 }
3f5eac3a
SC		 763}
764
c349775e
ST		 765static void set_ioaccel1_performant_mode(struct ctlr_info *h,
766 struct CommandList *c)
767{
768 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
769
770 /* Tell the controller to post the reply to the queue for this
771 * processor. This seems to give the best I/O throughput.
772 */
773 cp->ReplyQueue = smp_processor_id() % h->nreply_queues;
774 /* Set the bits in the address sent down to include:
775 * - performant mode bit (bit 0)
776 * - pull count (bits 1-3)
777 * - command type (bits 4-6)
778 */
779 c->busaddr |= 1 | (h->ioaccel1_blockFetchTable[c->Header.SGList] << 1) |
780 IOACCEL1_BUSADDR_CMDTYPE;
781}
782
783static void set_ioaccel2_performant_mode(struct ctlr_info *h,
784 struct CommandList *c)
785{
786 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
787
788 /* Tell the controller to post the reply to the queue for this
789 * processor. This seems to give the best I/O throughput.
790 */
791 cp->reply_queue = smp_processor_id() % h->nreply_queues;
792 /* Set the bits in the address sent down to include:
793 * - performant mode bit not used in ioaccel mode 2
794 * - pull count (bits 0-3)
795 * - command type isn't needed for ioaccel2
796 */
797 c->busaddr |= (h->ioaccel2_blockFetchTable[cp->sg_count]);
798}
799
e85c5974
SC		 800static int is_firmware_flash_cmd(u8 *cdb)
801{
802 return cdb[0] == BMIC_WRITE && cdb[6] == BMIC_FLASH_FIRMWARE;
803}
804
805/*
806 * During firmware flash, the heartbeat register may not update as frequently
807 * as it should. So we dial down lockup detection during firmware flash. and
808 * dial it back up when firmware flash completes.
809 */
810#define HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH (240 * HZ)
811#define HEARTBEAT_SAMPLE_INTERVAL (30 * HZ)
812static void dial_down_lockup_detection_during_fw_flash(struct ctlr_info *h,
813 struct CommandList *c)
814{
815 if (!is_firmware_flash_cmd(c->Request.CDB))
816 return;
817 atomic_inc(&h->firmware_flash_in_progress);
818 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH;
819}
820
821static void dial_up_lockup_detection_on_fw_flash_complete(struct ctlr_info *h,
822 struct CommandList *c)
823{
824 if (is_firmware_flash_cmd(c->Request.CDB) &&
825 atomic_dec_and_test(&h->firmware_flash_in_progress))
826 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
827}
828
3f5eac3a
SC		 829static void enqueue_cmd_and_start_io(struct ctlr_info *h,
830 struct CommandList *c)
831{
832 unsigned long flags;
833
c349775e
ST		 834 switch (c->cmd_type) {
835 case CMD_IOACCEL1:
836 set_ioaccel1_performant_mode(h, c);
837 break;
838 case CMD_IOACCEL2:
839 set_ioaccel2_performant_mode(h, c);
840 break;
841 default:
842 set_performant_mode(h, c);
843 }
e85c5974 844 dial_down_lockup_detection_during_fw_flash(h, c);
3f5eac3a
SC		 845 spin_lock_irqsave(&h->lock, flags);
846 addQ(&h->reqQ, c);
847 h->Qdepth++;
0b57075d 848 start_io(h, &flags);
3f5eac3a
SC		 849 spin_unlock_irqrestore(&h->lock, flags);
850}
851
852static inline void removeQ(struct CommandList *c)
853{
854 if (WARN_ON(list_empty(&c->list)))
855 return;
856 list_del_init(&c->list);
857}
858
859static inline int is_hba_lunid(unsigned char scsi3addr[])
860{
861 return memcmp(scsi3addr, RAID_CTLR_LUNID, 8) == 0;
862}
863
864static inline int is_scsi_rev_5(struct ctlr_info *h)
865{
866 if (!h->hba_inquiry_data)
867 return 0;
868 if ((h->hba_inquiry_data[2] & 0x07) == 5)
869 return 1;
870 return 0;
871}
872
edd16368
SC		 873static int hpsa_find_target_lun(struct ctlr_info *h,
874 unsigned char scsi3addr[], int bus, int *target, int *lun)
875{
876 /* finds an unused bus, target, lun for a new physical device
877 * assumes h->devlock is held
878 */
879 int i, found = 0;
cfe5badc 880 DECLARE_BITMAP(lun_taken, HPSA_MAX_DEVICES);
edd16368 881
263d9401 882 bitmap_zero(lun_taken, HPSA_MAX_DEVICES);
edd16368
SC		 883
884 for (i = 0; i < h->ndevices; i++) {
885 if (h->dev[i]->bus == bus && h->dev[i]->target != -1)
263d9401 886 __set_bit(h->dev[i]->target, lun_taken);
edd16368
SC		 887 }
888
263d9401
AM		 889 i = find_first_zero_bit(lun_taken, HPSA_MAX_DEVICES);
890 if (i < HPSA_MAX_DEVICES) {
891 /* *bus = 1; */
892 *target = i;
893 *lun = 0;
894 found = 1;
edd16368
SC		 895 }
896 return !found;
897}
898
899/* Add an entry into h->dev[] array. */
900static int hpsa_scsi_add_entry(struct ctlr_info *h, int hostno,
901 struct hpsa_scsi_dev_t *device,
902 struct hpsa_scsi_dev_t *added[], int *nadded)
903{
904 /* assumes h->devlock is held */
905 int n = h->ndevices;
906 int i;
907 unsigned char addr1[8], addr2[8];
908 struct hpsa_scsi_dev_t *sd;
909
cfe5badc 910 if (n >= HPSA_MAX_DEVICES) {
edd16368
SC		 911 dev_err(&h->pdev->dev, "too many devices, some will be "
912 "inaccessible.\n");
913 return -1;
914 }
915
916 /* physical devices do not have lun or target assigned until now. */
917 if (device->lun != -1)
918 /* Logical device, lun is already assigned. */
919 goto lun_assigned;
920
921 /* If this device a non-zero lun of a multi-lun device
922 * byte 4 of the 8-byte LUN addr will contain the logical
2b08b3e9 923 * unit no, zero otherwise.
edd16368
SC		 924 */
925 if (device->scsi3addr[4] == 0) {
926 /* This is not a non-zero lun of a multi-lun device */
927 if (hpsa_find_target_lun(h, device->scsi3addr,
928 device->bus, &device->target, &device->lun) != 0)
929 return -1;
930 goto lun_assigned;
931 }
932
933 /* This is a non-zero lun of a multi-lun device.
934 * Search through our list and find the device which
935 * has the same 8 byte LUN address, excepting byte 4.
936 * Assign the same bus and target for this new LUN.
937 * Use the logical unit number from the firmware.
938 */
939 memcpy(addr1, device->scsi3addr, 8);
940 addr1[4] = 0;
941 for (i = 0; i < n; i++) {
942 sd = h->dev[i];
943 memcpy(addr2, sd->scsi3addr, 8);
944 addr2[4] = 0;
945 /* differ only in byte 4? */
946 if (memcmp(addr1, addr2, 8) == 0) {
947 device->bus = sd->bus;
948 device->target = sd->target;
949 device->lun = device->scsi3addr[4];
950 break;
951 }
952 }
953 if (device->lun == -1) {
954 dev_warn(&h->pdev->dev, "physical device with no LUN=0,"
955 " suspect firmware bug or unsupported hardware "
956 "configuration.\n");
957 return -1;
958 }
959
960lun_assigned:
961
962 h->dev[n] = device;
963 h->ndevices++;
964 added[*nadded] = device;
965 (*nadded)++;
966
967 /* initially, (before registering with scsi layer) we don't
968 * know our hostno and we don't want to print anything first
969 * time anyway (the scsi layer's inquiries will show that info)
970 */
971 /* if (hostno != -1) */
972 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d added.\n",
973 scsi_device_type(device->devtype), hostno,
974 device->bus, device->target, device->lun);
975 return 0;
976}
977
bd9244f7
ST		 978/* Update an entry in h->dev[] array. */
979static void hpsa_scsi_update_entry(struct ctlr_info *h, int hostno,
980 int entry, struct hpsa_scsi_dev_t *new_entry)
981{
982 /* assumes h->devlock is held */
983 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
984
985 /* Raid level changed. */
986 h->dev[entry]->raid_level = new_entry->raid_level;
250fb125
SC		 987
988 /* Raid offload parameters changed. */
989 h->dev[entry]->offload_config = new_entry->offload_config;
990 h->dev[entry]->offload_enabled = new_entry->offload_enabled;
9fb0de2d
SC		 991 h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
992 h->dev[entry]->offload_to_mirror = new_entry->offload_to_mirror;
993 h->dev[entry]->raid_map = new_entry->raid_map;
250fb125 994
bd9244f7
ST		 995 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d updated.\n",
996 scsi_device_type(new_entry->devtype), hostno, new_entry->bus,
997 new_entry->target, new_entry->lun);
998}
999
2a8ccf31
SC		 1000/* Replace an entry from h->dev[] array. */
1001static void hpsa_scsi_replace_entry(struct ctlr_info *h, int hostno,
1002 int entry, struct hpsa_scsi_dev_t *new_entry,
1003 struct hpsa_scsi_dev_t *added[], int *nadded,
1004 struct hpsa_scsi_dev_t *removed[], int *nremoved)
1005{
1006 /* assumes h->devlock is held */
cfe5badc 1007 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
2a8ccf31
SC		 1008 removed[*nremoved] = h->dev[entry];
1009 (*nremoved)++;
01350d05
SC		 1010
1011 /*
1012 * New physical devices won't have target/lun assigned yet
1013 * so we need to preserve the values in the slot we are replacing.
1014 */
1015 if (new_entry->target == -1) {
1016 new_entry->target = h->dev[entry]->target;
1017 new_entry->lun = h->dev[entry]->lun;
1018 }
1019
2a8ccf31
SC		 1020 h->dev[entry] = new_entry;
1021 added[*nadded] = new_entry;
1022 (*nadded)++;
1023 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d changed.\n",
1024 scsi_device_type(new_entry->devtype), hostno, new_entry->bus,
1025 new_entry->target, new_entry->lun);
1026}
1027
edd16368
SC		 1028/* Remove an entry from h->dev[] array. */
1029static void hpsa_scsi_remove_entry(struct ctlr_info *h, int hostno, int entry,
1030 struct hpsa_scsi_dev_t *removed[], int *nremoved)
1031{
1032 /* assumes h->devlock is held */
1033 int i;
1034 struct hpsa_scsi_dev_t *sd;
1035
cfe5badc 1036 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
edd16368
SC		 1037
1038 sd = h->dev[entry];
1039 removed[*nremoved] = h->dev[entry];
1040 (*nremoved)++;
1041
1042 for (i = entry; i < h->ndevices-1; i++)
1043 h->dev[i] = h->dev[i+1];
1044 h->ndevices--;
1045 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d removed.\n",
1046 scsi_device_type(sd->devtype), hostno, sd->bus, sd->target,
1047 sd->lun);
1048}
1049
1050#define SCSI3ADDR_EQ(a, b) ( \
1051 (a)[7] == (b)[7] && \
1052 (a)[6] == (b)[6] && \
1053 (a)[5] == (b)[5] && \
1054 (a)[4] == (b)[4] && \
1055 (a)[3] == (b)[3] && \
1056 (a)[2] == (b)[2] && \
1057 (a)[1] == (b)[1] && \
1058 (a)[0] == (b)[0])
1059
1060static void fixup_botched_add(struct ctlr_info *h,
1061 struct hpsa_scsi_dev_t *added)
1062{
1063 /* called when scsi_add_device fails in order to re-adjust
1064 * h->dev[] to match the mid layer's view.
1065 */
1066 unsigned long flags;
1067 int i, j;
1068
1069 spin_lock_irqsave(&h->lock, flags);
1070 for (i = 0; i < h->ndevices; i++) {
1071 if (h->dev[i] == added) {
1072 for (j = i; j < h->ndevices-1; j++)
1073 h->dev[j] = h->dev[j+1];
1074 h->ndevices--;
1075 break;
1076 }
1077 }
1078 spin_unlock_irqrestore(&h->lock, flags);
1079 kfree(added);
1080}
1081
1082static inline int device_is_the_same(struct hpsa_scsi_dev_t *dev1,
1083 struct hpsa_scsi_dev_t *dev2)
1084{
edd16368
SC		 1085 /* we compare everything except lun and target as these
1086 * are not yet assigned. Compare parts likely
1087 * to differ first
1088 */
1089 if (memcmp(dev1->scsi3addr, dev2->scsi3addr,
1090 sizeof(dev1->scsi3addr)) != 0)
1091 return 0;
1092 if (memcmp(dev1->device_id, dev2->device_id,
1093 sizeof(dev1->device_id)) != 0)
1094 return 0;
1095 if (memcmp(dev1->model, dev2->model, sizeof(dev1->model)) != 0)
1096 return 0;
1097 if (memcmp(dev1->vendor, dev2->vendor, sizeof(dev1->vendor)) != 0)
1098 return 0;
edd16368
SC		 1099 if (dev1->devtype != dev2->devtype)
1100 return 0;
edd16368
SC		 1101 if (dev1->bus != dev2->bus)
1102 return 0;
1103 return 1;
1104}
1105
bd9244f7
ST		 1106static inline int device_updated(struct hpsa_scsi_dev_t *dev1,
1107 struct hpsa_scsi_dev_t *dev2)
1108{
1109 /* Device attributes that can change, but don't mean
1110 * that the device is a different device, nor that the OS
1111 * needs to be told anything about the change.
1112 */
1113 if (dev1->raid_level != dev2->raid_level)
1114 return 1;
250fb125
SC		 1115 if (dev1->offload_config != dev2->offload_config)
1116 return 1;
1117 if (dev1->offload_enabled != dev2->offload_enabled)
1118 return 1;
bd9244f7
ST		 1119 return 0;
1120}
1121
edd16368
SC		 1122/* Find needle in haystack. If exact match found, return DEVICE_SAME,
1123 * and return needle location in *index. If scsi3addr matches, but not
1124 * vendor, model, serial num, etc. return DEVICE_CHANGED, and return needle
bd9244f7
ST		 1125 * location in *index.
1126 * In the case of a minor device attribute change, such as RAID level, just
1127 * return DEVICE_UPDATED, along with the updated device's location in index.
1128 * If needle not found, return DEVICE_NOT_FOUND.
edd16368
SC		 1129 */
1130static int hpsa_scsi_find_entry(struct hpsa_scsi_dev_t *needle,
1131 struct hpsa_scsi_dev_t *haystack[], int haystack_size,
1132 int *index)
1133{
1134 int i;
1135#define DEVICE_NOT_FOUND 0
1136#define DEVICE_CHANGED 1
1137#define DEVICE_SAME 2
bd9244f7 1138#define DEVICE_UPDATED 3
edd16368 1139 for (i = 0; i < haystack_size; i++) {
23231048
SC		 1140 if (haystack[i] == NULL) /* previously removed. */
1141 continue;
edd16368
SC		 1142 if (SCSI3ADDR_EQ(needle->scsi3addr, haystack[i]->scsi3addr)) {
1143 *index = i;
bd9244f7
ST		 1144 if (device_is_the_same(needle, haystack[i])) {
1145 if (device_updated(needle, haystack[i]))
1146 return DEVICE_UPDATED;
edd16368 1147 return DEVICE_SAME;
bd9244f7 1148 } else {
9846590e
SC		 1149 /* Keep offline devices offline */
1150 if (needle->volume_offline)
1151 return DEVICE_NOT_FOUND;
edd16368 1152 return DEVICE_CHANGED;
bd9244f7 1153 }
edd16368
SC		 1154 }
1155 }
1156 *index = -1;
1157 return DEVICE_NOT_FOUND;
1158}
1159
9846590e
SC		 1160static void hpsa_monitor_offline_device(struct ctlr_info *h,
1161 unsigned char scsi3addr[])
1162{
1163 struct offline_device_entry *device;
1164 unsigned long flags;
1165
1166 /* Check to see if device is already on the list */
1167 spin_lock_irqsave(&h->offline_device_lock, flags);
1168 list_for_each_entry(device, &h->offline_device_list, offline_list) {
1169 if (memcmp(device->scsi3addr, scsi3addr,
1170 sizeof(device->scsi3addr)) == 0) {
1171 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1172 return;
1173 }
1174 }
1175 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1176
1177 /* Device is not on the list, add it. */
1178 device = kmalloc(sizeof(*device), GFP_KERNEL);
1179 if (!device) {
1180 dev_warn(&h->pdev->dev, "out of memory in %s\n", __func__);
1181 return;
1182 }
1183 memcpy(device->scsi3addr, scsi3addr, sizeof(device->scsi3addr));
1184 spin_lock_irqsave(&h->offline_device_lock, flags);
1185 list_add_tail(&device->offline_list, &h->offline_device_list);
1186 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1187}
1188
1189/* Print a message explaining various offline volume states */
1190static void hpsa_show_volume_status(struct ctlr_info *h,
1191 struct hpsa_scsi_dev_t *sd)
1192{
1193 if (sd->volume_offline == HPSA_VPD_LV_STATUS_UNSUPPORTED)
1194 dev_info(&h->pdev->dev,
1195 "C%d:B%d:T%d:L%d Volume status is not available through vital product data pages.\n",
1196 h->scsi_host->host_no,
1197 sd->bus, sd->target, sd->lun);
1198 switch (sd->volume_offline) {
1199 case HPSA_LV_OK:
1200 break;
1201 case HPSA_LV_UNDERGOING_ERASE:
1202 dev_info(&h->pdev->dev,
1203 "C%d:B%d:T%d:L%d Volume is undergoing background erase process.\n",
1204 h->scsi_host->host_no,
1205 sd->bus, sd->target, sd->lun);
1206 break;
1207 case HPSA_LV_UNDERGOING_RPI:
1208 dev_info(&h->pdev->dev,
1209 "C%d:B%d:T%d:L%d Volume is undergoing rapid parity initialization process.\n",
1210 h->scsi_host->host_no,
1211 sd->bus, sd->target, sd->lun);
1212 break;
1213 case HPSA_LV_PENDING_RPI:
1214 dev_info(&h->pdev->dev,
1215 "C%d:B%d:T%d:L%d Volume is queued for rapid parity initialization process.\n",
1216 h->scsi_host->host_no,
1217 sd->bus, sd->target, sd->lun);
1218 break;
1219 case HPSA_LV_ENCRYPTED_NO_KEY:
1220 dev_info(&h->pdev->dev,
1221 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because key is not present.\n",
1222 h->scsi_host->host_no,
1223 sd->bus, sd->target, sd->lun);
1224 break;
1225 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
1226 dev_info(&h->pdev->dev,
1227 "C%d:B%d:T%d:L%d Volume is not encrypted and cannot be accessed because controller is in encryption-only mode.\n",
1228 h->scsi_host->host_no,
1229 sd->bus, sd->target, sd->lun);
1230 break;
1231 case HPSA_LV_UNDERGOING_ENCRYPTION:
1232 dev_info(&h->pdev->dev,
1233 "C%d:B%d:T%d:L%d Volume is undergoing encryption process.\n",
1234 h->scsi_host->host_no,
1235 sd->bus, sd->target, sd->lun);
1236 break;
1237 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
1238 dev_info(&h->pdev->dev,
1239 "C%d:B%d:T%d:L%d Volume is undergoing encryption re-keying process.\n",
1240 h->scsi_host->host_no,
1241 sd->bus, sd->target, sd->lun);
1242 break;
1243 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
1244 dev_info(&h->pdev->dev,
1245 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because controller does not have encryption enabled.\n",
1246 h->scsi_host->host_no,
1247 sd->bus, sd->target, sd->lun);
1248 break;
1249 case HPSA_LV_PENDING_ENCRYPTION:
1250 dev_info(&h->pdev->dev,
1251 "C%d:B%d:T%d:L%d Volume is pending migration to encrypted state, but process has not started.\n",
1252 h->scsi_host->host_no,
1253 sd->bus, sd->target, sd->lun);
1254 break;
1255 case HPSA_LV_PENDING_ENCRYPTION_REKEYING:
1256 dev_info(&h->pdev->dev,
1257 "C%d:B%d:T%d:L%d Volume is encrypted and is pending encryption rekeying.\n",
1258 h->scsi_host->host_no,
1259 sd->bus, sd->target, sd->lun);
1260 break;
1261 }
1262}
1263
4967bd3e 1264static void adjust_hpsa_scsi_table(struct ctlr_info *h, int hostno,
edd16368
SC		 1265 struct hpsa_scsi_dev_t *sd[], int nsds)
1266{
1267 /* sd contains scsi3 addresses and devtypes, and inquiry
1268 * data. This function takes what's in sd to be the current
1269 * reality and updates h->dev[] to reflect that reality.
1270 */
1271 int i, entry, device_change, changes = 0;
1272 struct hpsa_scsi_dev_t *csd;
1273 unsigned long flags;
1274 struct hpsa_scsi_dev_t **added, **removed;
1275 int nadded, nremoved;
1276 struct Scsi_Host *sh = NULL;
1277
cfe5badc
ST		 1278 added = kzalloc(sizeof(*added) * HPSA_MAX_DEVICES, GFP_KERNEL);
1279 removed = kzalloc(sizeof(*removed) * HPSA_MAX_DEVICES, GFP_KERNEL);
edd16368
SC		 1280
1281 if (!added || !removed) {
1282 dev_warn(&h->pdev->dev, "out of memory in "
1283 "adjust_hpsa_scsi_table\n");
1284 goto free_and_out;
1285 }
1286
1287 spin_lock_irqsave(&h->devlock, flags);
1288
1289 /* find any devices in h->dev[] that are not in
1290 * sd[] and remove them from h->dev[], and for any
1291 * devices which have changed, remove the old device
1292 * info and add the new device info.
bd9244f7
ST		 1293 * If minor device attributes change, just update
1294 * the existing device structure.
edd16368
SC		 1295 */
1296 i = 0;
1297 nremoved = 0;
1298 nadded = 0;
1299 while (i < h->ndevices) {
1300 csd = h->dev[i];
1301 device_change = hpsa_scsi_find_entry(csd, sd, nsds, &entry);
1302 if (device_change == DEVICE_NOT_FOUND) {
1303 changes++;
1304 hpsa_scsi_remove_entry(h, hostno, i,
1305 removed, &nremoved);
1306 continue; /* remove ^^^, hence i not incremented */
1307 } else if (device_change == DEVICE_CHANGED) {
1308 changes++;
2a8ccf31
SC		 1309 hpsa_scsi_replace_entry(h, hostno, i, sd[entry],
1310 added, &nadded, removed, &nremoved);
c7f172dc
SC		 1311 /* Set it to NULL to prevent it from being freed
1312 * at the bottom of hpsa_update_scsi_devices()
1313 */
1314 sd[entry] = NULL;
bd9244f7
ST		 1315 } else if (device_change == DEVICE_UPDATED) {
1316 hpsa_scsi_update_entry(h, hostno, i, sd[entry]);
edd16368
SC		 1317 }
1318 i++;
1319 }
1320
1321 /* Now, make sure every device listed in sd[] is also
1322 * listed in h->dev[], adding them if they aren't found
1323 */
1324
1325 for (i = 0; i < nsds; i++) {
1326 if (!sd[i]) /* if already added above. */
1327 continue;
9846590e
SC		 1328
1329 /* Don't add devices which are NOT READY, FORMAT IN PROGRESS
1330 * as the SCSI mid-layer does not handle such devices well.
1331 * It relentlessly loops sending TUR at 3Hz, then READ(10)
1332 * at 160Hz, and prevents the system from coming up.
1333 */
1334 if (sd[i]->volume_offline) {
1335 hpsa_show_volume_status(h, sd[i]);
1336 dev_info(&h->pdev->dev, "c%db%dt%dl%d: temporarily offline\n",
1337 h->scsi_host->host_no,
1338 sd[i]->bus, sd[i]->target, sd[i]->lun);
1339 continue;
1340 }
1341
edd16368
SC		 1342 device_change = hpsa_scsi_find_entry(sd[i], h->dev,
1343 h->ndevices, &entry);
1344 if (device_change == DEVICE_NOT_FOUND) {
1345 changes++;
1346 if (hpsa_scsi_add_entry(h, hostno, sd[i],
1347 added, &nadded) != 0)
1348 break;
1349 sd[i] = NULL; /* prevent from being freed later. */
1350 } else if (device_change == DEVICE_CHANGED) {
1351 /* should never happen... */
1352 changes++;
1353 dev_warn(&h->pdev->dev,
1354 "device unexpectedly changed.\n");
1355 /* but if it does happen, we just ignore that device */
1356 }
1357 }
1358 spin_unlock_irqrestore(&h->devlock, flags);
1359
9846590e
SC		 1360 /* Monitor devices which are in one of several NOT READY states to be
1361 * brought online later. This must be done without holding h->devlock,
1362 * so don't touch h->dev[]
1363 */
1364 for (i = 0; i < nsds; i++) {
1365 if (!sd[i]) /* if already added above. */
1366 continue;
1367 if (sd[i]->volume_offline)
1368 hpsa_monitor_offline_device(h, sd[i]->scsi3addr);
1369 }
1370
edd16368
SC		 1371 /* Don't notify scsi mid layer of any changes the first time through
1372 * (or if there are no changes) scsi_scan_host will do it later the
1373 * first time through.
1374 */
1375 if (hostno == -1 || !changes)
1376 goto free_and_out;
1377
1378 sh = h->scsi_host;
1379 /* Notify scsi mid layer of any removed devices */
1380 for (i = 0; i < nremoved; i++) {
1381 struct scsi_device *sdev =
1382 scsi_device_lookup(sh, removed[i]->bus,
1383 removed[i]->target, removed[i]->lun);
1384 if (sdev != NULL) {
1385 scsi_remove_device(sdev);
1386 scsi_device_put(sdev);
1387 } else {
1388 /* We don't expect to get here.
1389 * future cmds to this device will get selection
1390 * timeout as if the device was gone.
1391 */
1392 dev_warn(&h->pdev->dev, "didn't find c%db%dt%dl%d "
1393 " for removal.", hostno, removed[i]->bus,
1394 removed[i]->target, removed[i]->lun);
1395 }
1396 kfree(removed[i]);
1397 removed[i] = NULL;
1398 }
1399
1400 /* Notify scsi mid layer of any added devices */
1401 for (i = 0; i < nadded; i++) {
1402 if (scsi_add_device(sh, added[i]->bus,
1403 added[i]->target, added[i]->lun) == 0)
1404 continue;
1405 dev_warn(&h->pdev->dev, "scsi_add_device c%db%dt%dl%d failed, "
1406 "device not added.\n", hostno, added[i]->bus,
1407 added[i]->target, added[i]->lun);
1408 /* now we have to remove it from h->dev,
1409 * since it didn't get added to scsi mid layer
1410 */
1411 fixup_botched_add(h, added[i]);
1412 }
1413
1414free_and_out:
1415 kfree(added);
1416 kfree(removed);
edd16368
SC		 1417}
1418
1419/*
9e03aa2f 1420 * Lookup bus/target/lun and return corresponding struct hpsa_scsi_dev_t *
edd16368
SC		 1421 * Assume's h->devlock is held.
1422 */
1423static struct hpsa_scsi_dev_t *lookup_hpsa_scsi_dev(struct ctlr_info *h,
1424 int bus, int target, int lun)
1425{
1426 int i;
1427 struct hpsa_scsi_dev_t *sd;
1428
1429 for (i = 0; i < h->ndevices; i++) {
1430 sd = h->dev[i];
1431 if (sd->bus == bus && sd->target == target && sd->lun == lun)
1432 return sd;
1433 }
1434 return NULL;
1435}
1436
1437/* link sdev->hostdata to our per-device structure. */
1438static int hpsa_slave_alloc(struct scsi_device *sdev)
1439{
1440 struct hpsa_scsi_dev_t *sd;
1441 unsigned long flags;
1442 struct ctlr_info *h;
1443
1444 h = sdev_to_hba(sdev);
1445 spin_lock_irqsave(&h->devlock, flags);
1446 sd = lookup_hpsa_scsi_dev(h, sdev_channel(sdev),
1447 sdev_id(sdev), sdev->lun);
1448 if (sd != NULL)
1449 sdev->hostdata = sd;
1450 spin_unlock_irqrestore(&h->devlock, flags);
1451 return 0;
1452}
1453
1454static void hpsa_slave_destroy(struct scsi_device *sdev)
1455{
bcc44255 1456 /* nothing to do. */
edd16368
SC		 1457}
1458
33a2ffce
SC		 1459static void hpsa_free_sg_chain_blocks(struct ctlr_info *h)
1460{
1461 int i;
1462
1463 if (!h->cmd_sg_list)
1464 return;
1465 for (i = 0; i < h->nr_cmds; i++) {
1466 kfree(h->cmd_sg_list[i]);
1467 h->cmd_sg_list[i] = NULL;
1468 }
1469 kfree(h->cmd_sg_list);
1470 h->cmd_sg_list = NULL;
1471}
1472
1473static int hpsa_allocate_sg_chain_blocks(struct ctlr_info *h)
1474{
1475 int i;
1476
1477 if (h->chainsize <= 0)
1478 return 0;
1479
1480 h->cmd_sg_list = kzalloc(sizeof(*h->cmd_sg_list) * h->nr_cmds,
1481 GFP_KERNEL);
3d4e6af8
RE		 1482 if (!h->cmd_sg_list) {
1483 dev_err(&h->pdev->dev, "Failed to allocate SG list\n");
33a2ffce 1484 return -ENOMEM;
3d4e6af8 1485 }
33a2ffce
SC		 1486 for (i = 0; i < h->nr_cmds; i++) {
1487 h->cmd_sg_list[i] = kmalloc(sizeof(*h->cmd_sg_list[i]) *
1488 h->chainsize, GFP_KERNEL);
3d4e6af8
RE		 1489 if (!h->cmd_sg_list[i]) {
1490 dev_err(&h->pdev->dev, "Failed to allocate cmd SG\n");
33a2ffce 1491 goto clean;
3d4e6af8 1492 }
33a2ffce
SC		 1493 }
1494 return 0;
1495
1496clean:
1497 hpsa_free_sg_chain_blocks(h);
1498 return -ENOMEM;
1499}
1500
e2bea6df 1501static int hpsa_map_sg_chain_block(struct ctlr_info *h,
33a2ffce
SC		 1502 struct CommandList *c)
1503{
1504 struct SGDescriptor *chain_sg, *chain_block;
1505 u64 temp64;
50a0decf 1506 u32 chain_len;
33a2ffce
SC		 1507
1508 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
1509 chain_block = h->cmd_sg_list[c->cmdindex];
50a0decf
SC		 1510 chain_sg->Ext = cpu_to_le32(HPSA_SG_CHAIN);
1511 chain_len = sizeof(*chain_sg) *
2b08b3e9 1512 (le16_to_cpu(c->Header.SGTotal) - h->max_cmd_sg_entries);
50a0decf
SC		 1513 chain_sg->Len = cpu_to_le32(chain_len);
1514 temp64 = pci_map_single(h->pdev, chain_block, chain_len,
33a2ffce 1515 PCI_DMA_TODEVICE);
e2bea6df
SC		 1516 if (dma_mapping_error(&h->pdev->dev, temp64)) {
1517 /* prevent subsequent unmapping */
50a0decf 1518 chain_sg->Addr = cpu_to_le64(0);
e2bea6df
SC		 1519 return -1;
1520 }
50a0decf 1521 chain_sg->Addr = cpu_to_le64(temp64);
e2bea6df 1522 return 0;
33a2ffce
SC		 1523}
1524
1525static void hpsa_unmap_sg_chain_block(struct ctlr_info *h,
1526 struct CommandList *c)
1527{
1528 struct SGDescriptor *chain_sg;
33a2ffce 1529
50a0decf 1530 if (le16_to_cpu(c->Header.SGTotal) <= h->max_cmd_sg_entries)
33a2ffce
SC		 1531 return;
1532
1533 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
50a0decf
SC		 1534 pci_unmap_single(h->pdev, le64_to_cpu(chain_sg->Addr),
1535 le32_to_cpu(chain_sg->Len), PCI_DMA_TODEVICE);
33a2ffce
SC		 1536}
1537
a09c1441
ST		 1538
1539/* Decode the various types of errors on ioaccel2 path.
1540 * Return 1 for any error that should generate a RAID path retry.
1541 * Return 0 for errors that don't require a RAID path retry.
1542 */
1543static int handle_ioaccel_mode2_error(struct ctlr_info *h,
c349775e
ST		 1544 struct CommandList *c,
1545 struct scsi_cmnd *cmd,
1546 struct io_accel2_cmd *c2)
1547{
1548 int data_len;
a09c1441 1549 int retry = 0;
c349775e
ST		 1550
1551 switch (c2->error_data.serv_response) {
1552 case IOACCEL2_SERV_RESPONSE_COMPLETE:
1553 switch (c2->error_data.status) {
1554 case IOACCEL2_STATUS_SR_TASK_COMP_GOOD:
1555 break;
1556 case IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND:
1557 dev_warn(&h->pdev->dev,
1558 "%s: task complete with check condition.\n",
1559 "HP SSD Smart Path");
ee6b1889 1560 cmd->result |= SAM_STAT_CHECK_CONDITION;
c349775e 1561 if (c2->error_data.data_present !=
ee6b1889
SC		 1562 IOACCEL2_SENSE_DATA_PRESENT) {
1563 memset(cmd->sense_buffer, 0,
1564 SCSI_SENSE_BUFFERSIZE);
c349775e 1565 break;
ee6b1889 1566 }
c349775e
ST		 1567 /* copy the sense data */
1568 data_len = c2->error_data.sense_data_len;
1569 if (data_len > SCSI_SENSE_BUFFERSIZE)
1570 data_len = SCSI_SENSE_BUFFERSIZE;
1571 if (data_len > sizeof(c2->error_data.sense_data_buff))
1572 data_len =
1573 sizeof(c2->error_data.sense_data_buff);
1574 memcpy(cmd->sense_buffer,
1575 c2->error_data.sense_data_buff, data_len);
a09c1441 1576 retry = 1;
c349775e
ST		 1577 break;
1578 case IOACCEL2_STATUS_SR_TASK_COMP_BUSY:
1579 dev_warn(&h->pdev->dev,
1580 "%s: task complete with BUSY status.\n",
1581 "HP SSD Smart Path");
a09c1441 1582 retry = 1;
c349775e
ST		 1583 break;
1584 case IOACCEL2_STATUS_SR_TASK_COMP_RES_CON:
1585 dev_warn(&h->pdev->dev,
1586 "%s: task complete with reservation conflict.\n",
1587 "HP SSD Smart Path");
a09c1441 1588 retry = 1;
c349775e
ST		 1589 break;
1590 case IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL:
1591 /* Make scsi midlayer do unlimited retries */
1592 cmd->result = DID_IMM_RETRY << 16;
1593 break;
1594 case IOACCEL2_STATUS_SR_TASK_COMP_ABORTED:
1595 dev_warn(&h->pdev->dev,
1596 "%s: task complete with aborted status.\n",
1597 "HP SSD Smart Path");
a09c1441 1598 retry = 1;
c349775e
ST		 1599 break;
1600 default:
1601 dev_warn(&h->pdev->dev,
1602 "%s: task complete with unrecognized status: 0x%02x\n",
1603 "HP SSD Smart Path", c2->error_data.status);
a09c1441 1604 retry = 1;
c349775e
ST		 1605 break;
1606 }
1607 break;
1608 case IOACCEL2_SERV_RESPONSE_FAILURE:
1609 /* don't expect to get here. */
1610 dev_warn(&h->pdev->dev,
1611 "unexpected delivery or target failure, status = 0x%02x\n",
1612 c2->error_data.status);
a09c1441 1613 retry = 1;
c349775e
ST		 1614 break;
1615 case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE:
1616 break;
1617 case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS:
1618 break;
1619 case IOACCEL2_SERV_RESPONSE_TMF_REJECTED:
1620 dev_warn(&h->pdev->dev, "task management function rejected.\n");
a09c1441 1621 retry = 1;
c349775e
ST		 1622 break;
1623 case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN:
1624 dev_warn(&h->pdev->dev, "task management function invalid LUN\n");
1625 break;
1626 default:
1627 dev_warn(&h->pdev->dev,
1628 "%s: Unrecognized server response: 0x%02x\n",
a09c1441
ST		 1629 "HP SSD Smart Path",
1630 c2->error_data.serv_response);
1631 retry = 1;
c349775e
ST		 1632 break;
1633 }
a09c1441
ST		 1634
1635 return retry; /* retry on raid path? */
c349775e
ST		 1636}
1637
1638static void process_ioaccel2_completion(struct ctlr_info *h,
1639 struct CommandList *c, struct scsi_cmnd *cmd,
1640 struct hpsa_scsi_dev_t *dev)
1641{
1642 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
a09c1441 1643 int raid_retry = 0;
c349775e
ST		 1644
1645 /* check for good status */
1646 if (likely(c2->error_data.serv_response == 0 &&
1647 c2->error_data.status == 0)) {
1648 cmd_free(h, c);
1649 cmd->scsi_done(cmd);
1650 return;
1651 }
1652
1653 /* Any RAID offload error results in retry which will use
1654 * the normal I/O path so the controller can handle whatever's
1655 * wrong.
1656 */
1657 if (is_logical_dev_addr_mode(dev->scsi3addr) &&
1658 c2->error_data.serv_response ==
1659 IOACCEL2_SERV_RESPONSE_FAILURE) {
c349775e 1660 dev->offload_enabled = 0;
e863d68e 1661 h->drv_req_rescan = 1; /* schedule controller for a rescan */
c349775e
ST		 1662 cmd->result = DID_SOFT_ERROR << 16;
1663 cmd_free(h, c);
1664 cmd->scsi_done(cmd);
1665 return;
1666 }
a09c1441
ST		 1667 raid_retry = handle_ioaccel_mode2_error(h, c, cmd, c2);
1668 /* If error found, disable Smart Path, schedule a rescan,
1669 * and force a retry on the standard path.
1670 */
1671 if (raid_retry) {
1672 dev_warn(&h->pdev->dev, "%s: Retrying on standard path.\n",
1673 "HP SSD Smart Path");
1674 dev->offload_enabled = 0; /* Disable Smart Path */
1675 h->drv_req_rescan = 1; /* schedule controller rescan */
1676 cmd->result = DID_SOFT_ERROR << 16;
1677 }
c349775e
ST		 1678 cmd_free(h, c);
1679 cmd->scsi_done(cmd);
1680}
1681
1fb011fb 1682static void complete_scsi_command(struct CommandList *cp)
edd16368
SC		 1683{
1684 struct scsi_cmnd *cmd;
1685 struct ctlr_info *h;
1686 struct ErrorInfo *ei;
283b4a9b 1687 struct hpsa_scsi_dev_t *dev;
edd16368
SC		 1688
1689 unsigned char sense_key;
1690 unsigned char asc; /* additional sense code */
1691 unsigned char ascq; /* additional sense code qualifier */
db111e18 1692 unsigned long sense_data_size;
edd16368
SC		 1693
1694 ei = cp->err_info;
1695 cmd = (struct scsi_cmnd *) cp->scsi_cmd;
1696 h = cp->h;
283b4a9b 1697 dev = cmd->device->hostdata;
edd16368
SC		 1698
1699 scsi_dma_unmap(cmd); /* undo the DMA mappings */
e1f7de0c 1700 if ((cp->cmd_type == CMD_SCSI) &&
2b08b3e9 1701 (le16_to_cpu(cp->Header.SGTotal) > h->max_cmd_sg_entries))
33a2ffce 1702 hpsa_unmap_sg_chain_block(h, cp);
edd16368
SC		 1703
1704 cmd->result = (DID_OK << 16); /* host byte */
1705 cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
c349775e
ST		 1706
1707 if (cp->cmd_type == CMD_IOACCEL2)
1708 return process_ioaccel2_completion(h, cp, cmd, dev);
1709
5512672f 1710 cmd->result |= ei->ScsiStatus;
edd16368 1711
6aa4c361
RE		 1712 scsi_set_resid(cmd, ei->ResidualCnt);
1713 if (ei->CommandStatus == 0) {
1714 cmd_free(h, cp);
1715 cmd->scsi_done(cmd);
1716 return;
1717 }
1718
1719 /* copy the sense data */
db111e18
SC		 1720 if (SCSI_SENSE_BUFFERSIZE < sizeof(ei->SenseInfo))
1721 sense_data_size = SCSI_SENSE_BUFFERSIZE;
1722 else
1723 sense_data_size = sizeof(ei->SenseInfo);
1724 if (ei->SenseLen < sense_data_size)
1725 sense_data_size = ei->SenseLen;
1726
1727 memcpy(cmd->sense_buffer, ei->SenseInfo, sense_data_size);
edd16368 1728
e1f7de0c
MG		 1729 /* For I/O accelerator commands, copy over some fields to the normal
1730 * CISS header used below for error handling.
1731 */
1732 if (cp->cmd_type == CMD_IOACCEL1) {
1733 struct io_accel1_cmd *c = &h->ioaccel_cmd_pool[cp->cmdindex];
2b08b3e9
DB		 1734 cp->Header.SGList = scsi_sg_count(cmd);
1735 cp->Header.SGTotal = cpu_to_le16(cp->Header.SGList);
1736 cp->Request.CDBLen = le16_to_cpu(c->io_flags) &
1737 IOACCEL1_IOFLAGS_CDBLEN_MASK;
50a0decf 1738 cp->Header.tag = c->tag;
e1f7de0c
MG		 1739 memcpy(cp->Header.LUN.LunAddrBytes, c->CISS_LUN, 8);
1740 memcpy(cp->Request.CDB, c->CDB, cp->Request.CDBLen);
283b4a9b
SC		 1741
1742 /* Any RAID offload error results in retry which will use
1743 * the normal I/O path so the controller can handle whatever's
1744 * wrong.
1745 */
1746 if (is_logical_dev_addr_mode(dev->scsi3addr)) {
1747 if (ei->CommandStatus == CMD_IOACCEL_DISABLED)
1748 dev->offload_enabled = 0;
1749 cmd->result = DID_SOFT_ERROR << 16;
1750 cmd_free(h, cp);
1751 cmd->scsi_done(cmd);
1752 return;
1753 }
e1f7de0c
MG		 1754 }
1755
edd16368
SC		 1756 /* an error has occurred */
1757 switch (ei->CommandStatus) {
1758
1759 case CMD_TARGET_STATUS:
1760 if (ei->ScsiStatus) {
1761 /* Get sense key */
1762 sense_key = 0xf & ei->SenseInfo[2];
1763 /* Get additional sense code */
1764 asc = ei->SenseInfo[12];
1765 /* Get addition sense code qualifier */
1766 ascq = ei->SenseInfo[13];
1767 }
edd16368 1768 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION) {
1d3b3609 1769 if (sense_key == ABORTED_COMMAND) {
2e311fba 1770 cmd->result |= DID_SOFT_ERROR << 16;
1d3b3609
MG		 1771 break;
1772 }
edd16368
SC		 1773 break;
1774 }
edd16368
SC		 1775 /* Problem was not a check condition
1776 * Pass it up to the upper layers...
1777 */
1778 if (ei->ScsiStatus) {
1779 dev_warn(&h->pdev->dev, "cp %p has status 0x%x "
1780 "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
1781 "Returning result: 0x%x\n",
1782 cp, ei->ScsiStatus,
1783 sense_key, asc, ascq,
1784 cmd->result);
1785 } else { /* scsi status is zero??? How??? */
1786 dev_warn(&h->pdev->dev, "cp %p SCSI status was 0. "
1787 "Returning no connection.\n", cp),
1788
1789 /* Ordinarily, this case should never happen,
1790 * but there is a bug in some released firmware
1791 * revisions that allows it to happen if, for
1792 * example, a 4100 backplane loses power and
1793 * the tape drive is in it. We assume that
1794 * it's a fatal error of some kind because we
1795 * can't show that it wasn't. We will make it
1796 * look like selection timeout since that is
1797 * the most common reason for this to occur,
1798 * and it's severe enough.
1799 */
1800
1801 cmd->result = DID_NO_CONNECT << 16;
1802 }
1803 break;
1804
1805 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
1806 break;
1807 case CMD_DATA_OVERRUN:
1808 dev_warn(&h->pdev->dev, "cp %p has"
1809 " completed with data overrun "
1810 "reported\n", cp);
1811 break;
1812 case CMD_INVALID: {
1813 /* print_bytes(cp, sizeof(*cp), 1, 0);
1814 print_cmd(cp); */
1815 /* We get CMD_INVALID if you address a non-existent device
1816 * instead of a selection timeout (no response). You will
1817 * see this if you yank out a drive, then try to access it.
1818 * This is kind of a shame because it means that any other
1819 * CMD_INVALID (e.g. driver bug) will get interpreted as a
1820 * missing target. */
1821 cmd->result = DID_NO_CONNECT << 16;
1822 }
1823 break;
1824 case CMD_PROTOCOL_ERR:
256d0eaa 1825 cmd->result = DID_ERROR << 16;
edd16368 1826 dev_warn(&h->pdev->dev, "cp %p has "
256d0eaa 1827 "protocol error\n", cp);
edd16368
SC		 1828 break;
1829 case CMD_HARDWARE_ERR:
1830 cmd->result = DID_ERROR << 16;
1831 dev_warn(&h->pdev->dev, "cp %p had hardware error\n", cp);
1832 break;
1833 case CMD_CONNECTION_LOST:
1834 cmd->result = DID_ERROR << 16;
1835 dev_warn(&h->pdev->dev, "cp %p had connection lost\n", cp);
1836 break;
1837 case CMD_ABORTED:
1838 cmd->result = DID_ABORT << 16;
1839 dev_warn(&h->pdev->dev, "cp %p was aborted with status 0x%x\n",
1840 cp, ei->ScsiStatus);
1841 break;
1842 case CMD_ABORT_FAILED:
1843 cmd->result = DID_ERROR << 16;
1844 dev_warn(&h->pdev->dev, "cp %p reports abort failed\n", cp);
1845 break;
1846 case CMD_UNSOLICITED_ABORT:
f6e76055
SC		 1847 cmd->result = DID_SOFT_ERROR << 16; /* retry the command */
1848 dev_warn(&h->pdev->dev, "cp %p aborted due to an unsolicited "
edd16368
SC		 1849 "abort\n", cp);
1850 break;
1851 case CMD_TIMEOUT:
1852 cmd->result = DID_TIME_OUT << 16;
1853 dev_warn(&h->pdev->dev, "cp %p timedout\n", cp);
1854 break;
1d5e2ed0
SC		 1855 case CMD_UNABORTABLE:
1856 cmd->result = DID_ERROR << 16;
1857 dev_warn(&h->pdev->dev, "Command unabortable\n");
1858 break;
283b4a9b
SC		 1859 case CMD_IOACCEL_DISABLED:
1860 /* This only handles the direct pass-through case since RAID
1861 * offload is handled above. Just attempt a retry.
1862 */
1863 cmd->result = DID_SOFT_ERROR << 16;
1864 dev_warn(&h->pdev->dev,
1865 "cp %p had HP SSD Smart Path error\n", cp);
1866 break;
edd16368
SC		 1867 default:
1868 cmd->result = DID_ERROR << 16;
1869 dev_warn(&h->pdev->dev, "cp %p returned unknown status %x\n",
1870 cp, ei->CommandStatus);
1871 }
edd16368 1872 cmd_free(h, cp);
2cc5bfaf 1873 cmd->scsi_done(cmd);
edd16368
SC		 1874}
1875
edd16368
SC		 1876static void hpsa_pci_unmap(struct pci_dev *pdev,
1877 struct CommandList *c, int sg_used, int data_direction)
1878{
1879 int i;
edd16368 1880
50a0decf
SC		 1881 for (i = 0; i < sg_used; i++)
1882 pci_unmap_single(pdev, (dma_addr_t) le64_to_cpu(c->SG[i].Addr),
1883 le32_to_cpu(c->SG[i].Len),
1884 data_direction);
edd16368
SC		 1885}
1886
a2dac136 1887static int hpsa_map_one(struct pci_dev *pdev,
edd16368
SC		 1888 struct CommandList *cp,
1889 unsigned char *buf,
1890 size_t buflen,
1891 int data_direction)
1892{
01a02ffc 1893 u64 addr64;
edd16368
SC		 1894
1895 if (buflen == 0 || data_direction == PCI_DMA_NONE) {
1896 cp->Header.SGList = 0;
50a0decf 1897 cp->Header.SGTotal = cpu_to_le16(0);
a2dac136 1898 return 0;
edd16368
SC		 1899 }
1900
50a0decf 1901 addr64 = pci_map_single(pdev, buf, buflen, data_direction);
eceaae18 1902 if (dma_mapping_error(&pdev->dev, addr64)) {
a2dac136 1903 /* Prevent subsequent unmap of something never mapped */
eceaae18 1904 cp->Header.SGList = 0;
50a0decf 1905 cp->Header.SGTotal = cpu_to_le16(0);
a2dac136 1906 return -1;
eceaae18 1907 }
50a0decf
SC		 1908 cp->SG[0].Addr = cpu_to_le64(addr64);
1909 cp->SG[0].Len = cpu_to_le32(buflen);
1910 cp->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* we are not chaining */
1911 cp->Header.SGList = 1; /* no. SGs contig in this cmd */
1912 cp->Header.SGTotal = cpu_to_le16(1); /* total sgs in cmd list */
a2dac136 1913 return 0;
edd16368
SC		 1914}
1915
1916static inline void hpsa_scsi_do_simple_cmd_core(struct ctlr_info *h,
1917 struct CommandList *c)
1918{
1919 DECLARE_COMPLETION_ONSTACK(wait);
1920
1921 c->waiting = &wait;
1922 enqueue_cmd_and_start_io(h, c);
1923 wait_for_completion(&wait);
1924}
1925
094963da
SC		 1926static u32 lockup_detected(struct ctlr_info *h)
1927{
1928 int cpu;
1929 u32 rc, *lockup_detected;
1930
1931 cpu = get_cpu();
1932 lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
1933 rc = *lockup_detected;
1934 put_cpu();
1935 return rc;
1936}
1937
a0c12413
SC		 1938static void hpsa_scsi_do_simple_cmd_core_if_no_lockup(struct ctlr_info *h,
1939 struct CommandList *c)
1940{
a0c12413 1941 /* If controller lockup detected, fake a hardware error. */
094963da 1942 if (unlikely(lockup_detected(h)))
a0c12413 1943 c->err_info->CommandStatus = CMD_HARDWARE_ERR;
094963da 1944 else
a0c12413 1945 hpsa_scsi_do_simple_cmd_core(h, c);
a0c12413
SC		 1946}
1947
9c2fc160 1948#define MAX_DRIVER_CMD_RETRIES 25
edd16368
SC		 1949static void hpsa_scsi_do_simple_cmd_with_retry(struct ctlr_info *h,
1950 struct CommandList *c, int data_direction)
1951{
9c2fc160 1952 int backoff_time = 10, retry_count = 0;
edd16368
SC		 1953
1954 do {
7630abd0 1955 memset(c->err_info, 0, sizeof(*c->err_info));
edd16368
SC		 1956 hpsa_scsi_do_simple_cmd_core(h, c);
1957 retry_count++;
9c2fc160
SC		 1958 if (retry_count > 3) {
1959 msleep(backoff_time);
1960 if (backoff_time < 1000)
1961 backoff_time *= 2;
1962 }
852af20a 1963 } while ((check_for_unit_attention(h, c) ||
9c2fc160
SC		 1964 check_for_busy(h, c)) &&
1965 retry_count <= MAX_DRIVER_CMD_RETRIES);
edd16368
SC		 1966 hpsa_pci_unmap(h->pdev, c, 1, data_direction);
1967}
1968
d1e8beac
SC		 1969static void hpsa_print_cmd(struct ctlr_info *h, char *txt,
1970 struct CommandList *c)
edd16368 1971{
d1e8beac
SC		 1972 const u8 *cdb = c->Request.CDB;
1973 const u8 *lun = c->Header.LUN.LunAddrBytes;
1974
1975 dev_warn(&h->pdev->dev, "%s: LUN:%02x%02x%02x%02x%02x%02x%02x%02x"
1976 " CDB:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\n",
1977 txt, lun[0], lun[1], lun[2], lun[3],
1978 lun[4], lun[5], lun[6], lun[7],
1979 cdb[0], cdb[1], cdb[2], cdb[3],
1980 cdb[4], cdb[5], cdb[6], cdb[7],
1981 cdb[8], cdb[9], cdb[10], cdb[11],
1982 cdb[12], cdb[13], cdb[14], cdb[15]);
1983}
1984
1985static void hpsa_scsi_interpret_error(struct ctlr_info *h,
1986 struct CommandList *cp)
1987{
1988 const struct ErrorInfo *ei = cp->err_info;
edd16368 1989 struct device *d = &cp->h->pdev->dev;
d1e8beac 1990 const u8 *sd = ei->SenseInfo;
edd16368 1991
edd16368
SC		 1992 switch (ei->CommandStatus) {
1993 case CMD_TARGET_STATUS:
d1e8beac
SC		 1994 hpsa_print_cmd(h, "SCSI status", cp);
1995 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION)
1996 dev_warn(d, "SCSI Status = 02, Sense key = %02x, ASC = %02x, ASCQ = %02x\n",
1997 sd[2] & 0x0f, sd[12], sd[13]);
1998 else
1999 dev_warn(d, "SCSI Status = %02x\n", ei->ScsiStatus);
edd16368
SC		 2000 if (ei->ScsiStatus == 0)
2001 dev_warn(d, "SCSI status is abnormally zero. "
2002 "(probably indicates selection timeout "
2003 "reported incorrectly due to a known "
2004 "firmware bug, circa July, 2001.)\n");
2005 break;
2006 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
edd16368
SC		 2007 break;
2008 case CMD_DATA_OVERRUN:
d1e8beac 2009 hpsa_print_cmd(h, "overrun condition", cp);
edd16368
SC		 2010 break;
2011 case CMD_INVALID: {
2012 /* controller unfortunately reports SCSI passthru's
2013 * to non-existent targets as invalid commands.
2014 */
d1e8beac
SC		 2015 hpsa_print_cmd(h, "invalid command", cp);
2016 dev_warn(d, "probably means device no longer present\n");
edd16368
SC		 2017 }
2018 break;
2019 case CMD_PROTOCOL_ERR:
d1e8beac 2020 hpsa_print_cmd(h, "protocol error", cp);
edd16368
SC		 2021 break;
2022 case CMD_HARDWARE_ERR:
d1e8beac 2023 hpsa_print_cmd(h, "hardware error", cp);
edd16368
SC		 2024 break;
2025 case CMD_CONNECTION_LOST:
d1e8beac 2026 hpsa_print_cmd(h, "connection lost", cp);
edd16368
SC		 2027 break;
2028 case CMD_ABORTED:
d1e8beac 2029 hpsa_print_cmd(h, "aborted", cp);
edd16368
SC		 2030 break;
2031 case CMD_ABORT_FAILED:
d1e8beac 2032 hpsa_print_cmd(h, "abort failed", cp);
edd16368
SC		 2033 break;
2034 case CMD_UNSOLICITED_ABORT:
d1e8beac 2035 hpsa_print_cmd(h, "unsolicited abort", cp);
edd16368
SC		 2036 break;
2037 case CMD_TIMEOUT:
d1e8beac 2038 hpsa_print_cmd(h, "timed out", cp);
edd16368 2039 break;
1d5e2ed0 2040 case CMD_UNABORTABLE:
d1e8beac 2041 hpsa_print_cmd(h, "unabortable", cp);
1d5e2ed0 2042 break;
edd16368 2043 default:
d1e8beac
SC		 2044 hpsa_print_cmd(h, "unknown status", cp);
2045 dev_warn(d, "Unknown command status %x\n",
edd16368
SC		 2046 ei->CommandStatus);
2047 }
2048}
2049
2050static int hpsa_scsi_do_inquiry(struct ctlr_info *h, unsigned char *scsi3addr,
b7bb24eb 2051 u16 page, unsigned char *buf,
edd16368
SC		 2052 unsigned char bufsize)
2053{
2054 int rc = IO_OK;
2055 struct CommandList *c;
2056 struct ErrorInfo *ei;
2057
45fcb86e 2058 c = cmd_alloc(h);
edd16368
SC		 2059
2060 if (c == NULL) { /* trouble... */
45fcb86e 2061 dev_warn(&h->pdev->dev, "cmd_alloc returned NULL!\n");
ecd9aad4 2062 return -ENOMEM;
edd16368
SC		 2063 }
2064
a2dac136
SC		 2065 if (fill_cmd(c, HPSA_INQUIRY, h, buf, bufsize,
2066 page, scsi3addr, TYPE_CMD)) {
2067 rc = -1;
2068 goto out;
2069 }
edd16368
SC		 2070 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
2071 ei = c->err_info;
2072 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2073 hpsa_scsi_interpret_error(h, c);
edd16368
SC		 2074 rc = -1;
2075 }
a2dac136 2076out:
45fcb86e 2077 cmd_free(h, c);
edd16368
SC		 2078 return rc;
2079}
2080
316b221a
SC		 2081static int hpsa_bmic_ctrl_mode_sense(struct ctlr_info *h,
2082 unsigned char *scsi3addr, unsigned char page,
2083 struct bmic_controller_parameters *buf, size_t bufsize)
2084{
2085 int rc = IO_OK;
2086 struct CommandList *c;
2087 struct ErrorInfo *ei;
2088
45fcb86e 2089 c = cmd_alloc(h);
316b221a 2090 if (c == NULL) { /* trouble... */
45fcb86e 2091 dev_warn(&h->pdev->dev, "cmd_alloc returned NULL!\n");
316b221a
SC		 2092 return -ENOMEM;
2093 }
2094
2095 if (fill_cmd(c, BMIC_SENSE_CONTROLLER_PARAMETERS, h, buf, bufsize,
2096 page, scsi3addr, TYPE_CMD)) {
2097 rc = -1;
2098 goto out;
2099 }
2100 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
2101 ei = c->err_info;
2102 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
2103 hpsa_scsi_interpret_error(h, c);
2104 rc = -1;
2105 }
2106out:
45fcb86e 2107 cmd_free(h, c);
316b221a
SC		 2108 return rc;
2109 }
2110
bf711ac6
ST		 2111static int hpsa_send_reset(struct ctlr_info *h, unsigned char *scsi3addr,
2112 u8 reset_type)
edd16368
SC		 2113{
2114 int rc = IO_OK;
2115 struct CommandList *c;
2116 struct ErrorInfo *ei;
2117
45fcb86e 2118 c = cmd_alloc(h);
edd16368
SC		 2119
2120 if (c == NULL) { /* trouble... */
45fcb86e 2121 dev_warn(&h->pdev->dev, "cmd_alloc returned NULL!\n");
e9ea04a6 2122 return -ENOMEM;
edd16368
SC		 2123 }
2124
a2dac136 2125 /* fill_cmd can't fail here, no data buffer to map. */
bf711ac6
ST		 2126 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
2127 scsi3addr, TYPE_MSG);
2128 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to LUN reset */
edd16368
SC		 2129 hpsa_scsi_do_simple_cmd_core(h, c);
2130 /* no unmap needed here because no data xfer. */
2131
2132 ei = c->err_info;
2133 if (ei->CommandStatus != 0) {
d1e8beac 2134 hpsa_scsi_interpret_error(h, c);
edd16368
SC		 2135 rc = -1;
2136 }
45fcb86e 2137 cmd_free(h, c);
edd16368
SC		 2138 return rc;
2139}
2140
2141static void hpsa_get_raid_level(struct ctlr_info *h,
2142 unsigned char *scsi3addr, unsigned char *raid_level)
2143{
2144 int rc;
2145 unsigned char *buf;
2146
2147 *raid_level = RAID_UNKNOWN;
2148 buf = kzalloc(64, GFP_KERNEL);
2149 if (!buf)
2150 return;
b7bb24eb 2151 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0xC1, buf, 64);
edd16368
SC		 2152 if (rc == 0)
2153 *raid_level = buf[8];
2154 if (*raid_level > RAID_UNKNOWN)
2155 *raid_level = RAID_UNKNOWN;
2156 kfree(buf);
2157 return;
2158}
2159
283b4a9b
SC		 2160#define HPSA_MAP_DEBUG
2161#ifdef HPSA_MAP_DEBUG
2162static void hpsa_debug_map_buff(struct ctlr_info *h, int rc,
2163 struct raid_map_data *map_buff)
2164{
2165 struct raid_map_disk_data *dd = &map_buff->data[0];
2166 int map, row, col;
2167 u16 map_cnt, row_cnt, disks_per_row;
2168
2169 if (rc != 0)
2170 return;
2171
2ba8bfc8
SC		 2172 /* Show details only if debugging has been activated. */
2173 if (h->raid_offload_debug < 2)
2174 return;
2175
283b4a9b
SC		 2176 dev_info(&h->pdev->dev, "structure_size = %u\n",
2177 le32_to_cpu(map_buff->structure_size));
2178 dev_info(&h->pdev->dev, "volume_blk_size = %u\n",
2179 le32_to_cpu(map_buff->volume_blk_size));
2180 dev_info(&h->pdev->dev, "volume_blk_cnt = 0x%llx\n",
2181 le64_to_cpu(map_buff->volume_blk_cnt));
2182 dev_info(&h->pdev->dev, "physicalBlockShift = %u\n",
2183 map_buff->phys_blk_shift);
2184 dev_info(&h->pdev->dev, "parity_rotation_shift = %u\n",
2185 map_buff->parity_rotation_shift);
2186 dev_info(&h->pdev->dev, "strip_size = %u\n",
2187 le16_to_cpu(map_buff->strip_size));
2188 dev_info(&h->pdev->dev, "disk_starting_blk = 0x%llx\n",
2189 le64_to_cpu(map_buff->disk_starting_blk));
2190 dev_info(&h->pdev->dev, "disk_blk_cnt = 0x%llx\n",
2191 le64_to_cpu(map_buff->disk_blk_cnt));
2192 dev_info(&h->pdev->dev, "data_disks_per_row = %u\n",
2193 le16_to_cpu(map_buff->data_disks_per_row));
2194 dev_info(&h->pdev->dev, "metadata_disks_per_row = %u\n",
2195 le16_to_cpu(map_buff->metadata_disks_per_row));
2196 dev_info(&h->pdev->dev, "row_cnt = %u\n",
2197 le16_to_cpu(map_buff->row_cnt));
2198 dev_info(&h->pdev->dev, "layout_map_count = %u\n",
2199 le16_to_cpu(map_buff->layout_map_count));
2b08b3e9 2200 dev_info(&h->pdev->dev, "flags = 0x%x\n",
dd0e19f3 2201 le16_to_cpu(map_buff->flags));
2b08b3e9
DB		 2202 dev_info(&h->pdev->dev, "encrypytion = %s\n",
2203 le16_to_cpu(map_buff->flags) &
2204 RAID_MAP_FLAG_ENCRYPT_ON ? "ON" : "OFF");
dd0e19f3
ST		 2205 dev_info(&h->pdev->dev, "dekindex = %u\n",
2206 le16_to_cpu(map_buff->dekindex));
283b4a9b
SC		 2207 map_cnt = le16_to_cpu(map_buff->layout_map_count);
2208 for (map = 0; map < map_cnt; map++) {
2209 dev_info(&h->pdev->dev, "Map%u:\n", map);
2210 row_cnt = le16_to_cpu(map_buff->row_cnt);
2211 for (row = 0; row < row_cnt; row++) {
2212 dev_info(&h->pdev->dev, " Row%u:\n", row);
2213 disks_per_row =
2214 le16_to_cpu(map_buff->data_disks_per_row);
2215 for (col = 0; col < disks_per_row; col++, dd++)
2216 dev_info(&h->pdev->dev,
2217 " D%02u: h=0x%04x xor=%u,%u\n",
2218 col, dd->ioaccel_handle,
2219 dd->xor_mult[0], dd->xor_mult[1]);
2220 disks_per_row =
2221 le16_to_cpu(map_buff->metadata_disks_per_row);
2222 for (col = 0; col < disks_per_row; col++, dd++)
2223 dev_info(&h->pdev->dev,
2224 " M%02u: h=0x%04x xor=%u,%u\n",
2225 col, dd->ioaccel_handle,
2226 dd->xor_mult[0], dd->xor_mult[1]);
2227 }
2228 }
2229}
2230#else
2231static void hpsa_debug_map_buff(__attribute__((unused)) struct ctlr_info *h,
2232 __attribute__((unused)) int rc,
2233 __attribute__((unused)) struct raid_map_data *map_buff)
2234{
2235}
2236#endif
2237
2238static int hpsa_get_raid_map(struct ctlr_info *h,
2239 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
2240{
2241 int rc = 0;
2242 struct CommandList *c;
2243 struct ErrorInfo *ei;
2244
45fcb86e 2245 c = cmd_alloc(h);
283b4a9b 2246 if (c == NULL) {
45fcb86e 2247 dev_warn(&h->pdev->dev, "cmd_alloc returned NULL!\n");
283b4a9b
SC		 2248 return -ENOMEM;
2249 }
2250 if (fill_cmd(c, HPSA_GET_RAID_MAP, h, &this_device->raid_map,
2251 sizeof(this_device->raid_map), 0,
2252 scsi3addr, TYPE_CMD)) {
2253 dev_warn(&h->pdev->dev, "Out of memory in hpsa_get_raid_map()\n");
45fcb86e 2254 cmd_free(h, c);
283b4a9b
SC		 2255 return -ENOMEM;
2256 }
2257 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
2258 ei = c->err_info;
2259 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2260 hpsa_scsi_interpret_error(h, c);
45fcb86e 2261 cmd_free(h, c);
283b4a9b
SC		 2262 return -1;
2263 }
45fcb86e 2264 cmd_free(h, c);
283b4a9b
SC		 2265
2266 /* @todo in the future, dynamically allocate RAID map memory */
2267 if (le32_to_cpu(this_device->raid_map.structure_size) >
2268 sizeof(this_device->raid_map)) {
2269 dev_warn(&h->pdev->dev, "RAID map size is too large!\n");
2270 rc = -1;
2271 }
2272 hpsa_debug_map_buff(h, rc, &this_device->raid_map);
2273 return rc;
2274}
2275
1b70150a
SC		 2276static int hpsa_vpd_page_supported(struct ctlr_info *h,
2277 unsigned char scsi3addr[], u8 page)
2278{
2279 int rc;
2280 int i;
2281 int pages;
2282 unsigned char *buf, bufsize;
2283
2284 buf = kzalloc(256, GFP_KERNEL);
2285 if (!buf)
2286 return 0;
2287
2288 /* Get the size of the page list first */
2289 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
2290 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
2291 buf, HPSA_VPD_HEADER_SZ);
2292 if (rc != 0)
2293 goto exit_unsupported;
2294 pages = buf[3];
2295 if ((pages + HPSA_VPD_HEADER_SZ) <= 255)
2296 bufsize = pages + HPSA_VPD_HEADER_SZ;
2297 else
2298 bufsize = 255;
2299
2300 /* Get the whole VPD page list */
2301 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
2302 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
2303 buf, bufsize);
2304 if (rc != 0)
2305 goto exit_unsupported;
2306
2307 pages = buf[3];
2308 for (i = 1; i <= pages; i++)
2309 if (buf[3 + i] == page)
2310 goto exit_supported;
2311exit_unsupported:
2312 kfree(buf);
2313 return 0;
2314exit_supported:
2315 kfree(buf);
2316 return 1;
2317}
2318
283b4a9b
SC		 2319static void hpsa_get_ioaccel_status(struct ctlr_info *h,
2320 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
2321{
2322 int rc;
2323 unsigned char *buf;
2324 u8 ioaccel_status;
2325
2326 this_device->offload_config = 0;
2327 this_device->offload_enabled = 0;
2328
2329 buf = kzalloc(64, GFP_KERNEL);
2330 if (!buf)
2331 return;
1b70150a
SC		 2332 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_IOACCEL_STATUS))
2333 goto out;
283b4a9b 2334 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
b7bb24eb 2335 VPD_PAGE | HPSA_VPD_LV_IOACCEL_STATUS, buf, 64);
283b4a9b
SC		 2336 if (rc != 0)
2337 goto out;
2338
2339#define IOACCEL_STATUS_BYTE 4
2340#define OFFLOAD_CONFIGURED_BIT 0x01
2341#define OFFLOAD_ENABLED_BIT 0x02
2342 ioaccel_status = buf[IOACCEL_STATUS_BYTE];
2343 this_device->offload_config =
2344 !!(ioaccel_status & OFFLOAD_CONFIGURED_BIT);
2345 if (this_device->offload_config) {
2346 this_device->offload_enabled =
2347 !!(ioaccel_status & OFFLOAD_ENABLED_BIT);
2348 if (hpsa_get_raid_map(h, scsi3addr, this_device))
2349 this_device->offload_enabled = 0;
2350 }
2351out:
2352 kfree(buf);
2353 return;
2354}
2355
edd16368
SC		 2356/* Get the device id from inquiry page 0x83 */
2357static int hpsa_get_device_id(struct ctlr_info *h, unsigned char *scsi3addr,
2358 unsigned char *device_id, int buflen)
2359{
2360 int rc;
2361 unsigned char *buf;
2362
2363 if (buflen > 16)
2364 buflen = 16;
2365 buf = kzalloc(64, GFP_KERNEL);
2366 if (!buf)
a84d794d 2367 return -ENOMEM;
b7bb24eb 2368 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0x83, buf, 64);
edd16368
SC		 2369 if (rc == 0)
2370 memcpy(device_id, &buf[8], buflen);
2371 kfree(buf);
2372 return rc != 0;
2373}
2374
2375static int hpsa_scsi_do_report_luns(struct ctlr_info *h, int logical,
2376 struct ReportLUNdata *buf, int bufsize,
2377 int extended_response)
2378{
2379 int rc = IO_OK;
2380 struct CommandList *c;
2381 unsigned char scsi3addr[8];
2382 struct ErrorInfo *ei;
2383
45fcb86e 2384 c = cmd_alloc(h);
edd16368 2385 if (c == NULL) { /* trouble... */
45fcb86e 2386 dev_err(&h->pdev->dev, "cmd_alloc returned NULL!\n");
edd16368
SC		 2387 return -1;
2388 }
e89c0ae7
SC		 2389 /* address the controller */
2390 memset(scsi3addr, 0, sizeof(scsi3addr));
a2dac136
SC		 2391 if (fill_cmd(c, logical ? HPSA_REPORT_LOG : HPSA_REPORT_PHYS, h,
2392 buf, bufsize, 0, scsi3addr, TYPE_CMD)) {
2393 rc = -1;
2394 goto out;
2395 }
edd16368
SC		 2396 if (extended_response)
2397 c->Request.CDB[1] = extended_response;
2398 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
2399 ei = c->err_info;
2400 if (ei->CommandStatus != 0 &&
2401 ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2402 hpsa_scsi_interpret_error(h, c);
edd16368 2403 rc = -1;
283b4a9b
SC		 2404 } else {
2405 if (buf->extended_response_flag != extended_response) {
2406 dev_err(&h->pdev->dev,
2407 "report luns requested format %u, got %u\n",
2408 extended_response,
2409 buf->extended_response_flag);
2410 rc = -1;
2411 }
edd16368 2412 }
a2dac136 2413out:
45fcb86e 2414 cmd_free(h, c);
edd16368
SC		 2415 return rc;
2416}
2417
2418static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h,
2419 struct ReportLUNdata *buf,
2420 int bufsize, int extended_response)
2421{
2422 return hpsa_scsi_do_report_luns(h, 0, buf, bufsize, extended_response);
2423}
2424
2425static inline int hpsa_scsi_do_report_log_luns(struct ctlr_info *h,
2426 struct ReportLUNdata *buf, int bufsize)
2427{
2428 return hpsa_scsi_do_report_luns(h, 1, buf, bufsize, 0);
2429}
2430
2431static inline void hpsa_set_bus_target_lun(struct hpsa_scsi_dev_t *device,
2432 int bus, int target, int lun)
2433{
2434 device->bus = bus;
2435 device->target = target;
2436 device->lun = lun;
2437}
2438
9846590e
SC		 2439/* Use VPD inquiry to get details of volume status */
2440static int hpsa_get_volume_status(struct ctlr_info *h,
2441 unsigned char scsi3addr[])
2442{
2443 int rc;
2444 int status;
2445 int size;
2446 unsigned char *buf;
2447
2448 buf = kzalloc(64, GFP_KERNEL);
2449 if (!buf)
2450 return HPSA_VPD_LV_STATUS_UNSUPPORTED;
2451
2452 /* Does controller have VPD for logical volume status? */
24a4b078 2453 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_STATUS))
9846590e 2454 goto exit_failed;
9846590e
SC		 2455
2456 /* Get the size of the VPD return buffer */
2457 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
2458 buf, HPSA_VPD_HEADER_SZ);
24a4b078 2459 if (rc != 0)
9846590e 2460 goto exit_failed;
9846590e
SC		 2461 size = buf[3];
2462
2463 /* Now get the whole VPD buffer */
2464 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
2465 buf, size + HPSA_VPD_HEADER_SZ);
24a4b078 2466 if (rc != 0)
9846590e 2467 goto exit_failed;
9846590e
SC		 2468 status = buf[4]; /* status byte */
2469
2470 kfree(buf);
2471 return status;
2472exit_failed:
2473 kfree(buf);
2474 return HPSA_VPD_LV_STATUS_UNSUPPORTED;
2475}
2476
2477/* Determine offline status of a volume.
2478 * Return either:
2479 * 0 (not offline)
67955ba3 2480 * 0xff (offline for unknown reasons)
9846590e
SC		 2481 * # (integer code indicating one of several NOT READY states
2482 * describing why a volume is to be kept offline)
2483 */
67955ba3 2484static int hpsa_volume_offline(struct ctlr_info *h,
9846590e
SC		 2485 unsigned char scsi3addr[])
2486{
2487 struct CommandList *c;
2488 unsigned char *sense, sense_key, asc, ascq;
2489 int ldstat = 0;
2490 u16 cmd_status;
2491 u8 scsi_status;
2492#define ASC_LUN_NOT_READY 0x04
2493#define ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS 0x04
2494#define ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ 0x02
2495
2496 c = cmd_alloc(h);
2497 if (!c)
2498 return 0;
2499 (void) fill_cmd(c, TEST_UNIT_READY, h, NULL, 0, 0, scsi3addr, TYPE_CMD);
2500 hpsa_scsi_do_simple_cmd_core(h, c);
2501 sense = c->err_info->SenseInfo;
2502 sense_key = sense[2];
2503 asc = sense[12];
2504 ascq = sense[13];
2505 cmd_status = c->err_info->CommandStatus;
2506 scsi_status = c->err_info->ScsiStatus;
2507 cmd_free(h, c);
2508 /* Is the volume 'not ready'? */
2509 if (cmd_status != CMD_TARGET_STATUS ||
2510 scsi_status != SAM_STAT_CHECK_CONDITION ||
2511 sense_key != NOT_READY ||
2512 asc != ASC_LUN_NOT_READY) {
2513 return 0;
2514 }
2515
2516 /* Determine the reason for not ready state */
2517 ldstat = hpsa_get_volume_status(h, scsi3addr);
2518
2519 /* Keep volume offline in certain cases: */
2520 switch (ldstat) {
2521 case HPSA_LV_UNDERGOING_ERASE:
2522 case HPSA_LV_UNDERGOING_RPI:
2523 case HPSA_LV_PENDING_RPI:
2524 case HPSA_LV_ENCRYPTED_NO_KEY:
2525 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
2526 case HPSA_LV_UNDERGOING_ENCRYPTION:
2527 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
2528 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
2529 return ldstat;
2530 case HPSA_VPD_LV_STATUS_UNSUPPORTED:
2531 /* If VPD status page isn't available,
2532 * use ASC/ASCQ to determine state
2533 */
2534 if ((ascq == ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS) ||
2535 (ascq == ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ))
2536 return ldstat;
2537 break;
2538 default:
2539 break;
2540 }
2541 return 0;
2542}
2543
edd16368 2544static int hpsa_update_device_info(struct ctlr_info *h,
0b0e1d6c
SC		 2545 unsigned char scsi3addr[], struct hpsa_scsi_dev_t *this_device,
2546 unsigned char *is_OBDR_device)
edd16368 2547{
0b0e1d6c
SC		 2548
2549#define OBDR_SIG_OFFSET 43
2550#define OBDR_TAPE_SIG "$DR-10"
2551#define OBDR_SIG_LEN (sizeof(OBDR_TAPE_SIG) - 1)
2552#define OBDR_TAPE_INQ_SIZE (OBDR_SIG_OFFSET + OBDR_SIG_LEN)
2553
ea6d3bc3 2554 unsigned char *inq_buff;
0b0e1d6c 2555 unsigned char *obdr_sig;
edd16368 2556
ea6d3bc3 2557 inq_buff = kzalloc(OBDR_TAPE_INQ_SIZE, GFP_KERNEL);
edd16368
SC		 2558 if (!inq_buff)
2559 goto bail_out;
2560
edd16368
SC		 2561 /* Do an inquiry to the device to see what it is. */
2562 if (hpsa_scsi_do_inquiry(h, scsi3addr, 0, inq_buff,
2563 (unsigned char) OBDR_TAPE_INQ_SIZE) != 0) {
2564 /* Inquiry failed (msg printed already) */
2565 dev_err(&h->pdev->dev,
2566 "hpsa_update_device_info: inquiry failed\n");
2567 goto bail_out;
2568 }
2569
edd16368
SC		 2570 this_device->devtype = (inq_buff[0] & 0x1f);
2571 memcpy(this_device->scsi3addr, scsi3addr, 8);
2572 memcpy(this_device->vendor, &inq_buff[8],
2573 sizeof(this_device->vendor));
2574 memcpy(this_device->model, &inq_buff[16],
2575 sizeof(this_device->model));
edd16368
SC		 2576 memset(this_device->device_id, 0,
2577 sizeof(this_device->device_id));
2578 hpsa_get_device_id(h, scsi3addr, this_device->device_id,
2579 sizeof(this_device->device_id));
2580
2581 if (this_device->devtype == TYPE_DISK &&
283b4a9b 2582 is_logical_dev_addr_mode(scsi3addr)) {
67955ba3
SC		 2583 int volume_offline;
2584
edd16368 2585 hpsa_get_raid_level(h, scsi3addr, &this_device->raid_level);
283b4a9b
SC		 2586 if (h->fw_support & MISC_FW_RAID_OFFLOAD_BASIC)
2587 hpsa_get_ioaccel_status(h, scsi3addr, this_device);
67955ba3
SC		 2588 volume_offline = hpsa_volume_offline(h, scsi3addr);
2589 if (volume_offline < 0 || volume_offline > 0xff)
2590 volume_offline = HPSA_VPD_LV_STATUS_UNSUPPORTED;
2591 this_device->volume_offline = volume_offline & 0xff;
283b4a9b 2592 } else {
edd16368 2593 this_device->raid_level = RAID_UNKNOWN;
283b4a9b
SC		 2594 this_device->offload_config = 0;
2595 this_device->offload_enabled = 0;
9846590e 2596 this_device->volume_offline = 0;
283b4a9b 2597 }
edd16368 2598
0b0e1d6c
SC		 2599 if (is_OBDR_device) {
2600 /* See if this is a One-Button-Disaster-Recovery device
2601 * by looking for "$DR-10" at offset 43 in inquiry data.
2602 */
2603 obdr_sig = &inq_buff[OBDR_SIG_OFFSET];
2604 *is_OBDR_device = (this_device->devtype == TYPE_ROM &&
2605 strncmp(obdr_sig, OBDR_TAPE_SIG,
2606 OBDR_SIG_LEN) == 0);
2607 }
2608
edd16368
SC		 2609 kfree(inq_buff);
2610 return 0;
2611
2612bail_out:
2613 kfree(inq_buff);
2614 return 1;
2615}
2616
4f4eb9f1 2617static unsigned char *ext_target_model[] = {
edd16368
SC		 2618 "MSA2012",
2619 "MSA2024",
2620 "MSA2312",
2621 "MSA2324",
fda38518 2622 "P2000 G3 SAS",
e06c8e5c 2623 "MSA 2040 SAS",
edd16368
SC		 2624 NULL,
2625};
2626
4f4eb9f1 2627static int is_ext_target(struct ctlr_info *h, struct hpsa_scsi_dev_t *device)
edd16368
SC		 2628{
2629 int i;
2630
4f4eb9f1
ST		 2631 for (i = 0; ext_target_model[i]; i++)
2632 if (strncmp(device->model, ext_target_model[i],
2633 strlen(ext_target_model[i])) == 0)
edd16368
SC		 2634 return 1;
2635 return 0;
2636}
2637
2638/* Helper function to assign bus, target, lun mapping of devices.
4f4eb9f1 2639 * Puts non-external target logical volumes on bus 0, external target logical
edd16368
SC		 2640 * volumes on bus 1, physical devices on bus 2. and the hba on bus 3.
2641 * Logical drive target and lun are assigned at this time, but
2642 * physical device lun and target assignment are deferred (assigned
2643 * in hpsa_find_target_lun, called by hpsa_scsi_add_entry.)
2644 */
2645static void figure_bus_target_lun(struct ctlr_info *h,
1f310bde 2646 u8 *lunaddrbytes, struct hpsa_scsi_dev_t *device)
edd16368 2647{
1f310bde
SC		 2648 u32 lunid = le32_to_cpu(*((__le32 *) lunaddrbytes));
2649
2650 if (!is_logical_dev_addr_mode(lunaddrbytes)) {
2651 /* physical device, target and lun filled in later */
edd16368 2652 if (is_hba_lunid(lunaddrbytes))
1f310bde 2653 hpsa_set_bus_target_lun(device, 3, 0, lunid & 0x3fff);
edd16368 2654 else
1f310bde
SC		 2655 /* defer target, lun assignment for physical devices */
2656 hpsa_set_bus_target_lun(device, 2, -1, -1);
2657 return;
2658 }
2659 /* It's a logical device */
4f4eb9f1
ST		 2660 if (is_ext_target(h, device)) {
2661 /* external target way, put logicals on bus 1
1f310bde
SC		 2662 * and match target/lun numbers box
2663 * reports, other smart array, bus 0, target 0, match lunid
2664 */
2665 hpsa_set_bus_target_lun(device,
2666 1, (lunid >> 16) & 0x3fff, lunid & 0x00ff);
2667 return;
edd16368 2668 }
1f310bde 2669 hpsa_set_bus_target_lun(device, 0, 0, lunid & 0x3fff);
edd16368
SC		 2670}
2671
2672/*
2673 * If there is no lun 0 on a target, linux won't find any devices.
4f4eb9f1 2674 * For the external targets (arrays), we have to manually detect the enclosure
edd16368
SC		 2675 * which is at lun zero, as CCISS_REPORT_PHYSICAL_LUNS doesn't report
2676 * it for some reason. *tmpdevice is the target we're adding,
2677 * this_device is a pointer into the current element of currentsd[]
2678 * that we're building up in update_scsi_devices(), below.
2679 * lunzerobits is a bitmap that tracks which targets already have a
2680 * lun 0 assigned.
2681 * Returns 1 if an enclosure was added, 0 if not.
2682 */
4f4eb9f1 2683static int add_ext_target_dev(struct ctlr_info *h,
edd16368 2684 struct hpsa_scsi_dev_t *tmpdevice,
01a02ffc 2685 struct hpsa_scsi_dev_t *this_device, u8 *lunaddrbytes,
4f4eb9f1 2686 unsigned long lunzerobits[], int *n_ext_target_devs)
edd16368
SC		 2687{
2688 unsigned char scsi3addr[8];
2689
1f310bde 2690 if (test_bit(tmpdevice->target, lunzerobits))
edd16368
SC		 2691 return 0; /* There is already a lun 0 on this target. */
2692
2693 if (!is_logical_dev_addr_mode(lunaddrbytes))
2694 return 0; /* It's the logical targets that may lack lun 0. */
2695
4f4eb9f1
ST		 2696 if (!is_ext_target(h, tmpdevice))
2697 return 0; /* Only external target devices have this problem. */
edd16368 2698
1f310bde 2699 if (tmpdevice->lun == 0) /* if lun is 0, then we have a lun 0. */
edd16368
SC		 2700 return 0;
2701
c4f8a299 2702 memset(scsi3addr, 0, 8);
1f310bde 2703 scsi3addr[3] = tmpdevice->target;
edd16368
SC		 2704 if (is_hba_lunid(scsi3addr))
2705 return 0; /* Don't add the RAID controller here. */
2706
339b2b14
SC		 2707 if (is_scsi_rev_5(h))
2708 return 0; /* p1210m doesn't need to do this. */
2709
4f4eb9f1 2710 if (*n_ext_target_devs >= MAX_EXT_TARGETS) {
aca4a520
ST		 2711 dev_warn(&h->pdev->dev, "Maximum number of external "
2712 "target devices exceeded. Check your hardware "
edd16368
SC		 2713 "configuration.");
2714 return 0;
2715 }
2716
0b0e1d6c 2717 if (hpsa_update_device_info(h, scsi3addr, this_device, NULL))
edd16368 2718 return 0;
4f4eb9f1 2719 (*n_ext_target_devs)++;
1f310bde
SC		 2720 hpsa_set_bus_target_lun(this_device,
2721 tmpdevice->bus, tmpdevice->target, 0);
2722 set_bit(tmpdevice->target, lunzerobits);
edd16368
SC		 2723 return 1;
2724}
2725
54b6e9e9
ST		 2726/*
2727 * Get address of physical disk used for an ioaccel2 mode command:
2728 * 1. Extract ioaccel2 handle from the command.
2729 * 2. Find a matching ioaccel2 handle from list of physical disks.
2730 * 3. Return:
2731 * 1 and set scsi3addr to address of matching physical
2732 * 0 if no matching physical disk was found.
2733 */
2734static int hpsa_get_pdisk_of_ioaccel2(struct ctlr_info *h,
2735 struct CommandList *ioaccel2_cmd_to_abort, unsigned char *scsi3addr)
2736{
2737 struct ReportExtendedLUNdata *physicals = NULL;
2738 int responsesize = 24; /* size of physical extended response */
2739 int extended = 2; /* flag forces reporting 'other dev info'. */
2740 int reportsize = sizeof(*physicals) + HPSA_MAX_PHYS_LUN * responsesize;
2741 u32 nphysicals = 0; /* number of reported physical devs */
2742 int found = 0; /* found match (1) or not (0) */
2743 u32 find; /* handle we need to match */
2744 int i;
2745 struct scsi_cmnd *scmd; /* scsi command within request being aborted */
2746 struct hpsa_scsi_dev_t *d; /* device of request being aborted */
2747 struct io_accel2_cmd *c2a; /* ioaccel2 command to abort */
2b08b3e9
DB		 2748 __le32 it_nexus; /* 4 byte device handle for the ioaccel2 cmd */
2749 __le32 scsi_nexus; /* 4 byte device handle for the ioaccel2 cmd */
54b6e9e9
ST		 2750
2751 if (ioaccel2_cmd_to_abort->cmd_type != CMD_IOACCEL2)
2752 return 0; /* no match */
2753
2754 /* point to the ioaccel2 device handle */
2755 c2a = &h->ioaccel2_cmd_pool[ioaccel2_cmd_to_abort->cmdindex];
2756 if (c2a == NULL)
2757 return 0; /* no match */
2758
2759 scmd = (struct scsi_cmnd *) ioaccel2_cmd_to_abort->scsi_cmd;
2760 if (scmd == NULL)
2761 return 0; /* no match */
2762
2763 d = scmd->device->hostdata;
2764 if (d == NULL)
2765 return 0; /* no match */
2766
50a0decf 2767 it_nexus = cpu_to_le32(d->ioaccel_handle);
2b08b3e9
DB		 2768 scsi_nexus = c2a->scsi_nexus;
2769 find = le32_to_cpu(c2a->scsi_nexus);
54b6e9e9 2770
2ba8bfc8
SC		 2771 if (h->raid_offload_debug > 0)
2772 dev_info(&h->pdev->dev,
2773 "%s: scsi_nexus:0x%08x device id: 0x%02x%02x%02x%02x %02x%02x%02x%02x %02x%02x%02x%02x %02x%02x%02x%02x\n",
2774 __func__, scsi_nexus,
2775 d->device_id[0], d->device_id[1], d->device_id[2],
2776 d->device_id[3], d->device_id[4], d->device_id[5],
2777 d->device_id[6], d->device_id[7], d->device_id[8],
2778 d->device_id[9], d->device_id[10], d->device_id[11],
2779 d->device_id[12], d->device_id[13], d->device_id[14],
2780 d->device_id[15]);
2781
54b6e9e9
ST		 2782 /* Get the list of physical devices */
2783 physicals = kzalloc(reportsize, GFP_KERNEL);
3b51a7a3
JH		 2784 if (physicals == NULL)
2785 return 0;
54b6e9e9
ST		 2786 if (hpsa_scsi_do_report_phys_luns(h, (struct ReportLUNdata *) physicals,
2787 reportsize, extended)) {
2788 dev_err(&h->pdev->dev,
2789 "Can't lookup %s device handle: report physical LUNs failed.\n",
2790 "HP SSD Smart Path");
2791 kfree(physicals);
2792 return 0;
2793 }
2794 nphysicals = be32_to_cpu(*((__be32 *)physicals->LUNListLength)) /
2795 responsesize;
2796
54b6e9e9
ST		 2797 /* find ioaccel2 handle in list of physicals: */
2798 for (i = 0; i < nphysicals; i++) {
d5b5d964
SC		 2799 struct ext_report_lun_entry *entry = &physicals->LUN[i];
2800
54b6e9e9 2801 /* handle is in bytes 28-31 of each lun */
d5b5d964 2802 if (entry->ioaccel_handle != find)
54b6e9e9 2803 continue; /* didn't match */
54b6e9e9 2804 found = 1;
d5b5d964 2805 memcpy(scsi3addr, entry->lunid, 8);
2ba8bfc8
SC		 2806 if (h->raid_offload_debug > 0)
2807 dev_info(&h->pdev->dev,
d5b5d964 2808 "%s: Searched h=0x%08x, Found h=0x%08x, scsiaddr 0x%8phN\n",
2ba8bfc8 2809 __func__, find,
d5b5d964 2810 entry->ioaccel_handle, scsi3addr);
54b6e9e9
ST		 2811 break; /* found it */
2812 }
2813
2814 kfree(physicals);
2815 if (found)
2816 return 1;
2817 else
2818 return 0;
2819
2820}
edd16368
SC		 2821/*
2822 * Do CISS_REPORT_PHYS and CISS_REPORT_LOG. Data is returned in physdev,
2823 * logdev. The number of luns in physdev and logdev are returned in
2824 * *nphysicals and *nlogicals, respectively.
2825 * Returns 0 on success, -1 otherwise.
2826 */
2827static int hpsa_gather_lun_info(struct ctlr_info *h,
92084715 2828 int reportphyslunsize, int reportloglunsize,
283b4a9b 2829 struct ReportLUNdata *physdev, u32 *nphysicals, int *physical_mode,
01a02ffc 2830 struct ReportLUNdata *logdev, u32 *nlogicals)
edd16368 2831{
283b4a9b
SC		 2832 int physical_entry_size = 8;
2833
2834 *physical_mode = 0;
2835
2836 /* For I/O accelerator mode we need to read physical device handles */
317d4adf
MM		 2837 if (h->transMethod & CFGTBL_Trans_io_accel1 ||
2838 h->transMethod & CFGTBL_Trans_io_accel2) {
283b4a9b
SC		 2839 *physical_mode = HPSA_REPORT_PHYS_EXTENDED;
2840 physical_entry_size = 24;
2841 }
92084715 2842 if (hpsa_scsi_do_report_phys_luns(h, physdev, reportphyslunsize,
283b4a9b 2843 *physical_mode)) {
edd16368
SC		 2844 dev_err(&h->pdev->dev, "report physical LUNs failed.\n");
2845 return -1;
2846 }
283b4a9b
SC		 2847 *nphysicals = be32_to_cpu(*((__be32 *)physdev->LUNListLength)) /
2848 physical_entry_size;
edd16368
SC		 2849 if (*nphysicals > HPSA_MAX_PHYS_LUN) {
2850 dev_warn(&h->pdev->dev, "maximum physical LUNs (%d) exceeded."
2851 " %d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
2852 *nphysicals - HPSA_MAX_PHYS_LUN);
2853 *nphysicals = HPSA_MAX_PHYS_LUN;
2854 }
92084715 2855 if (hpsa_scsi_do_report_log_luns(h, logdev, reportloglunsize)) {
edd16368
SC		 2856 dev_err(&h->pdev->dev, "report logical LUNs failed.\n");
2857 return -1;
2858 }
6df1e954 2859 *nlogicals = be32_to_cpu(*((__be32 *) logdev->LUNListLength)) / 8;
edd16368
SC		 2860 /* Reject Logicals in excess of our max capability. */
2861 if (*nlogicals > HPSA_MAX_LUN) {
2862 dev_warn(&h->pdev->dev,
2863 "maximum logical LUNs (%d) exceeded. "
2864 "%d LUNs ignored.\n", HPSA_MAX_LUN,
2865 *nlogicals - HPSA_MAX_LUN);
2866 *nlogicals = HPSA_MAX_LUN;
2867 }
2868 if (*nlogicals + *nphysicals > HPSA_MAX_PHYS_LUN) {
2869 dev_warn(&h->pdev->dev,
2870 "maximum logical + physical LUNs (%d) exceeded. "
2871 "%d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
2872 *nphysicals + *nlogicals - HPSA_MAX_PHYS_LUN);
2873 *nlogicals = HPSA_MAX_PHYS_LUN - *nphysicals;
2874 }
2875 return 0;
2876}
2877
42a91641
DB		 2878static u8 *figure_lunaddrbytes(struct ctlr_info *h, int raid_ctlr_position,
2879 int i, int nphysicals, int nlogicals,
a93aa1fe 2880 struct ReportExtendedLUNdata *physdev_list,
339b2b14
SC		 2881 struct ReportLUNdata *logdev_list)
2882{
2883 /* Helper function, figure out where the LUN ID info is coming from
2884 * given index i, lists of physical and logical devices, where in
2885 * the list the raid controller is supposed to appear (first or last)
2886 */
2887
2888 int logicals_start = nphysicals + (raid_ctlr_position == 0);
2889 int last_device = nphysicals + nlogicals + (raid_ctlr_position == 0);
2890
2891 if (i == raid_ctlr_position)
2892 return RAID_CTLR_LUNID;
2893
2894 if (i < logicals_start)
d5b5d964
SC		 2895 return &physdev_list->LUN[i -
2896 (raid_ctlr_position == 0)].lunid[0];
339b2b14
SC		 2897
2898 if (i < last_device)
2899 return &logdev_list->LUN[i - nphysicals -
2900 (raid_ctlr_position == 0)][0];
2901 BUG();
2902 return NULL;
2903}
2904
316b221a
SC		 2905static int hpsa_hba_mode_enabled(struct ctlr_info *h)
2906{
2907 int rc;
6e8e8088 2908 int hba_mode_enabled;
316b221a
SC		 2909 struct bmic_controller_parameters *ctlr_params;
2910 ctlr_params = kzalloc(sizeof(struct bmic_controller_parameters),
2911 GFP_KERNEL);
2912
2913 if (!ctlr_params)
96444fbb 2914 return -ENOMEM;
316b221a
SC		 2915 rc = hpsa_bmic_ctrl_mode_sense(h, RAID_CTLR_LUNID, 0, ctlr_params,
2916 sizeof(struct bmic_controller_parameters));
96444fbb 2917 if (rc) {
316b221a 2918 kfree(ctlr_params);
96444fbb 2919 return rc;
316b221a 2920 }
6e8e8088
JH		 2921
2922 hba_mode_enabled =
2923 ((ctlr_params->nvram_flags & HBA_MODE_ENABLED_FLAG) != 0);
2924 kfree(ctlr_params);
2925 return hba_mode_enabled;
316b221a
SC		 2926}
2927
edd16368
SC		 2928static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno)
2929{
2930 /* the idea here is we could get notified
2931 * that some devices have changed, so we do a report
2932 * physical luns and report logical luns cmd, and adjust
2933 * our list of devices accordingly.
2934 *
2935 * The scsi3addr's of devices won't change so long as the
2936 * adapter is not reset. That means we can rescan and
2937 * tell which devices we already know about, vs. new
2938 * devices, vs. disappearing devices.
2939 */
a93aa1fe 2940 struct ReportExtendedLUNdata *physdev_list = NULL;
edd16368 2941 struct ReportLUNdata *logdev_list = NULL;
01a02ffc
SC		 2942 u32 nphysicals = 0;
2943 u32 nlogicals = 0;
283b4a9b 2944 int physical_mode = 0;
01a02ffc 2945 u32 ndev_allocated = 0;
edd16368
SC		 2946 struct hpsa_scsi_dev_t **currentsd, *this_device, *tmpdevice;
2947 int ncurrent = 0;
4f4eb9f1 2948 int i, n_ext_target_devs, ndevs_to_allocate;
339b2b14 2949 int raid_ctlr_position;
2bbf5c7f 2950 int rescan_hba_mode;
aca4a520 2951 DECLARE_BITMAP(lunzerobits, MAX_EXT_TARGETS);
edd16368 2952
cfe5badc 2953 currentsd = kzalloc(sizeof(*currentsd) * HPSA_MAX_DEVICES, GFP_KERNEL);
92084715
SC		 2954 physdev_list = kzalloc(sizeof(*physdev_list), GFP_KERNEL);
2955 logdev_list = kzalloc(sizeof(*logdev_list), GFP_KERNEL);
edd16368
SC		 2956 tmpdevice = kzalloc(sizeof(*tmpdevice), GFP_KERNEL);
2957
0b0e1d6c 2958 if (!currentsd || !physdev_list || !logdev_list || !tmpdevice) {
edd16368
SC		 2959 dev_err(&h->pdev->dev, "out of memory\n");
2960 goto out;
2961 }
2962 memset(lunzerobits, 0, sizeof(lunzerobits));
2963
316b221a 2964 rescan_hba_mode = hpsa_hba_mode_enabled(h);
96444fbb
JH		 2965 if (rescan_hba_mode < 0)
2966 goto out;
316b221a
SC		 2967
2968 if (!h->hba_mode_enabled && rescan_hba_mode)
2969 dev_warn(&h->pdev->dev, "HBA mode enabled\n");
2970 else if (h->hba_mode_enabled && !rescan_hba_mode)
2971 dev_warn(&h->pdev->dev, "HBA mode disabled\n");
2972
2973 h->hba_mode_enabled = rescan_hba_mode;
2974
92084715
SC		 2975 if (hpsa_gather_lun_info(h,
2976 sizeof(*physdev_list), sizeof(*logdev_list),
a93aa1fe 2977 (struct ReportLUNdata *) physdev_list, &nphysicals,
283b4a9b 2978 &physical_mode, logdev_list, &nlogicals))
edd16368
SC		 2979 goto out;
2980
aca4a520
ST		 2981 /* We might see up to the maximum number of logical and physical disks
2982 * plus external target devices, and a device for the local RAID
2983 * controller.
edd16368 2984 */
aca4a520 2985 ndevs_to_allocate = nphysicals + nlogicals + MAX_EXT_TARGETS + 1;
edd16368
SC		 2986
2987 /* Allocate the per device structures */
2988 for (i = 0; i < ndevs_to_allocate; i++) {
b7ec021f
ST		 2989 if (i >= HPSA_MAX_DEVICES) {
2990 dev_warn(&h->pdev->dev, "maximum devices (%d) exceeded."
2991 " %d devices ignored.\n", HPSA_MAX_DEVICES,
2992 ndevs_to_allocate - HPSA_MAX_DEVICES);
2993 break;
2994 }
2995
edd16368
SC		 2996 currentsd[i] = kzalloc(sizeof(*currentsd[i]), GFP_KERNEL);
2997 if (!currentsd[i]) {
2998 dev_warn(&h->pdev->dev, "out of memory at %s:%d\n",
2999 __FILE__, __LINE__);
3000 goto out;
3001 }
3002 ndev_allocated++;
3003 }
3004
8645291b 3005 if (is_scsi_rev_5(h))
339b2b14
SC		 3006 raid_ctlr_position = 0;
3007 else
3008 raid_ctlr_position = nphysicals + nlogicals;
3009
edd16368 3010 /* adjust our table of devices */
4f4eb9f1 3011 n_ext_target_devs = 0;
edd16368 3012 for (i = 0; i < nphysicals + nlogicals + 1; i++) {
0b0e1d6c 3013 u8 *lunaddrbytes, is_OBDR = 0;
edd16368
SC		 3014
3015 /* Figure out where the LUN ID info is coming from */
339b2b14
SC		 3016 lunaddrbytes = figure_lunaddrbytes(h, raid_ctlr_position,
3017 i, nphysicals, nlogicals, physdev_list, logdev_list);
edd16368 3018 /* skip masked physical devices. */
339b2b14
SC		 3019 if (lunaddrbytes[3] & 0xC0 &&
3020 i < nphysicals + (raid_ctlr_position == 0))
edd16368
SC		 3021 continue;
3022
3023 /* Get device type, vendor, model, device id */
0b0e1d6c
SC		 3024 if (hpsa_update_device_info(h, lunaddrbytes, tmpdevice,
3025 &is_OBDR))
edd16368 3026 continue; /* skip it if we can't talk to it. */
1f310bde 3027 figure_bus_target_lun(h, lunaddrbytes, tmpdevice);
edd16368
SC		 3028 this_device = currentsd[ncurrent];
3029
3030 /*
4f4eb9f1 3031 * For external target devices, we have to insert a LUN 0 which
edd16368
SC		 3032 * doesn't show up in CCISS_REPORT_PHYSICAL data, but there
3033 * is nonetheless an enclosure device there. We have to
3034 * present that otherwise linux won't find anything if
3035 * there is no lun 0.
3036 */
4f4eb9f1 3037 if (add_ext_target_dev(h, tmpdevice, this_device,
1f310bde 3038 lunaddrbytes, lunzerobits,
4f4eb9f1 3039 &n_ext_target_devs)) {
edd16368
SC		 3040 ncurrent++;
3041 this_device = currentsd[ncurrent];
3042 }
3043
3044 *this_device = *tmpdevice;
edd16368
SC		 3045
3046 switch (this_device->devtype) {
0b0e1d6c 3047 case TYPE_ROM:
edd16368
SC		 3048 /* We don't *really* support actual CD-ROM devices,
3049 * just "One Button Disaster Recovery" tape drive
3050 * which temporarily pretends to be a CD-ROM drive.
3051 * So we check that the device is really an OBDR tape
3052 * device by checking for "$DR-10" in bytes 43-48 of
3053 * the inquiry data.
3054 */
0b0e1d6c
SC		 3055 if (is_OBDR)
3056 ncurrent++;
edd16368
SC		 3057 break;
3058 case TYPE_DISK:
316b221a
SC		 3059 if (h->hba_mode_enabled) {
3060 /* never use raid mapper in HBA mode */
3061 this_device->offload_enabled = 0;
3062 ncurrent++;
3063 break;
3064 } else if (h->acciopath_status) {
3065 if (i >= nphysicals) {
3066 ncurrent++;
3067 break;
3068 }
3069 } else {
3070 if (i < nphysicals)
3071 break;
283b4a9b 3072 ncurrent++;
edd16368 3073 break;
283b4a9b
SC		 3074 }
3075 if (physical_mode == HPSA_REPORT_PHYS_EXTENDED) {
3076 memcpy(&this_device->ioaccel_handle,
3077 &lunaddrbytes[20],
3078 sizeof(this_device->ioaccel_handle));
3079 ncurrent++;
3080 }
edd16368
SC		 3081 break;
3082 case TYPE_TAPE:
3083 case TYPE_MEDIUM_CHANGER:
3084 ncurrent++;
3085 break;
3086 case TYPE_RAID:
3087 /* Only present the Smartarray HBA as a RAID controller.
3088 * If it's a RAID controller other than the HBA itself
3089 * (an external RAID controller, MSA500 or similar)
3090 * don't present it.
3091 */
3092 if (!is_hba_lunid(lunaddrbytes))
3093 break;
3094 ncurrent++;
3095 break;
3096 default:
3097 break;
3098 }
cfe5badc 3099 if (ncurrent >= HPSA_MAX_DEVICES)
edd16368
SC		 3100 break;
3101 }
3102 adjust_hpsa_scsi_table(h, hostno, currentsd, ncurrent);
3103out:
3104 kfree(tmpdevice);
3105 for (i = 0; i < ndev_allocated; i++)
3106 kfree(currentsd[i]);
3107 kfree(currentsd);
edd16368
SC		 3108 kfree(physdev_list);
3109 kfree(logdev_list);
edd16368
SC		 3110}
3111
c7ee65b3
WS		 3112/*
3113 * hpsa_scatter_gather takes a struct scsi_cmnd, (cmd), and does the pci
edd16368
SC		 3114 * dma mapping and fills in the scatter gather entries of the
3115 * hpsa command, cp.
3116 */
33a2ffce 3117static int hpsa_scatter_gather(struct ctlr_info *h,
edd16368
SC		 3118 struct CommandList *cp,
3119 struct scsi_cmnd *cmd)
3120{
3121 unsigned int len;
3122 struct scatterlist *sg;
01a02ffc 3123 u64 addr64;
33a2ffce
SC		 3124 int use_sg, i, sg_index, chained;
3125 struct SGDescriptor *curr_sg;
edd16368 3126
33a2ffce 3127 BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
edd16368
SC		 3128
3129 use_sg = scsi_dma_map(cmd);
3130 if (use_sg < 0)
3131 return use_sg;
3132
3133 if (!use_sg)
3134 goto sglist_finished;
3135
33a2ffce
SC		 3136 curr_sg = cp->SG;
3137 chained = 0;
3138 sg_index = 0;
edd16368 3139 scsi_for_each_sg(cmd, sg, use_sg, i) {
33a2ffce
SC		 3140 if (i == h->max_cmd_sg_entries - 1 &&
3141 use_sg > h->max_cmd_sg_entries) {
3142 chained = 1;
3143 curr_sg = h->cmd_sg_list[cp->cmdindex];
3144 sg_index = 0;
3145 }
01a02ffc 3146 addr64 = (u64) sg_dma_address(sg);
edd16368 3147 len = sg_dma_len(sg);
50a0decf
SC		 3148 curr_sg->Addr = cpu_to_le64(addr64);
3149 curr_sg->Len = cpu_to_le32(len);
3150 curr_sg->Ext = cpu_to_le32(0);
33a2ffce
SC		 3151 curr_sg++;
3152 }
50a0decf 3153 (--curr_sg)->Ext = cpu_to_le32(HPSA_SG_LAST);
33a2ffce
SC		 3154
3155 if (use_sg + chained > h->maxSG)
3156 h->maxSG = use_sg + chained;
3157
3158 if (chained) {
3159 cp->Header.SGList = h->max_cmd_sg_entries;
50a0decf 3160 cp->Header.SGTotal = cpu_to_le16(use_sg + 1);
e2bea6df
SC		 3161 if (hpsa_map_sg_chain_block(h, cp)) {
3162 scsi_dma_unmap(cmd);
3163 return -1;
3164 }
33a2ffce 3165 return 0;
edd16368
SC		 3166 }
3167
3168sglist_finished:
3169
01a02ffc 3170 cp->Header.SGList = (u8) use_sg; /* no. SGs contig in this cmd */
c7ee65b3 3171 cp->Header.SGTotal = cpu_to_le16(use_sg); /* total sgs in cmd list */
edd16368
SC		 3172 return 0;
3173}
3174
283b4a9b
SC		 3175#define IO_ACCEL_INELIGIBLE (1)
3176static int fixup_ioaccel_cdb(u8 *cdb, int *cdb_len)
3177{
3178 int is_write = 0;
3179 u32 block;
3180 u32 block_cnt;
3181
3182 /* Perform some CDB fixups if needed using 10 byte reads/writes only */
3183 switch (cdb[0]) {
3184 case WRITE_6:
3185 case WRITE_12:
3186 is_write = 1;
3187 case READ_6:
3188 case READ_12:
3189 if (*cdb_len == 6) {
3190 block = (((u32) cdb[2]) << 8) | cdb[3];
3191 block_cnt = cdb[4];
3192 } else {
3193 BUG_ON(*cdb_len != 12);
3194 block = (((u32) cdb[2]) << 24) |
3195 (((u32) cdb[3]) << 16) |
3196 (((u32) cdb[4]) << 8) |
3197 cdb[5];
3198 block_cnt =
3199 (((u32) cdb[6]) << 24) |
3200 (((u32) cdb[7]) << 16) |
3201 (((u32) cdb[8]) << 8) |
3202 cdb[9];
3203 }
3204 if (block_cnt > 0xffff)
3205 return IO_ACCEL_INELIGIBLE;
3206
3207 cdb[0] = is_write ? WRITE_10 : READ_10;
3208 cdb[1] = 0;
3209 cdb[2] = (u8) (block >> 24);
3210 cdb[3] = (u8) (block >> 16);
3211 cdb[4] = (u8) (block >> 8);
3212 cdb[5] = (u8) (block);
3213 cdb[6] = 0;
3214 cdb[7] = (u8) (block_cnt >> 8);
3215 cdb[8] = (u8) (block_cnt);
3216 cdb[9] = 0;
3217 *cdb_len = 10;
3218 break;
3219 }
3220 return 0;
3221}
3222
c349775e 3223static int hpsa_scsi_ioaccel1_queue_command(struct ctlr_info *h,
283b4a9b
SC		 3224 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
3225 u8 *scsi3addr)
e1f7de0c
MG		 3226{
3227 struct scsi_cmnd *cmd = c->scsi_cmd;
e1f7de0c
MG		 3228 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
3229 unsigned int len;
3230 unsigned int total_len = 0;
3231 struct scatterlist *sg;
3232 u64 addr64;
3233 int use_sg, i;
3234 struct SGDescriptor *curr_sg;
3235 u32 control = IOACCEL1_CONTROL_SIMPLEQUEUE;
3236
283b4a9b
SC		 3237 /* TODO: implement chaining support */
3238 if (scsi_sg_count(cmd) > h->ioaccel_maxsg)
3239 return IO_ACCEL_INELIGIBLE;
3240
e1f7de0c
MG		 3241 BUG_ON(cmd->cmd_len > IOACCEL1_IOFLAGS_CDBLEN_MAX);
3242
283b4a9b
SC		 3243 if (fixup_ioaccel_cdb(cdb, &cdb_len))
3244 return IO_ACCEL_INELIGIBLE;
3245
e1f7de0c
MG		 3246 c->cmd_type = CMD_IOACCEL1;
3247
3248 /* Adjust the DMA address to point to the accelerated command buffer */
3249 c->busaddr = (u32) h->ioaccel_cmd_pool_dhandle +
3250 (c->cmdindex * sizeof(*cp));
3251 BUG_ON(c->busaddr & 0x0000007F);
3252
3253 use_sg = scsi_dma_map(cmd);
3254 if (use_sg < 0)
3255 return use_sg;
3256
3257 if (use_sg) {
3258 curr_sg = cp->SG;
3259 scsi_for_each_sg(cmd, sg, use_sg, i) {
3260 addr64 = (u64) sg_dma_address(sg);
3261 len = sg_dma_len(sg);
3262 total_len += len;
50a0decf
SC		 3263 curr_sg->Addr = cpu_to_le64(addr64);
3264 curr_sg->Len = cpu_to_le32(len);
3265 curr_sg->Ext = cpu_to_le32(0);
e1f7de0c
MG		 3266 curr_sg++;
3267 }
50a0decf 3268 (--curr_sg)->Ext = cpu_to_le32(HPSA_SG_LAST);
e1f7de0c
MG		 3269
3270 switch (cmd->sc_data_direction) {
3271 case DMA_TO_DEVICE:
3272 control |= IOACCEL1_CONTROL_DATA_OUT;
3273 break;
3274 case DMA_FROM_DEVICE:
3275 control |= IOACCEL1_CONTROL_DATA_IN;
3276 break;
3277 case DMA_NONE:
3278 control |= IOACCEL1_CONTROL_NODATAXFER;
3279 break;
3280 default:
3281 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
3282 cmd->sc_data_direction);
3283 BUG();
3284 break;
3285 }
3286 } else {
3287 control |= IOACCEL1_CONTROL_NODATAXFER;
3288 }
3289
c349775e 3290 c->Header.SGList = use_sg;
e1f7de0c 3291 /* Fill out the command structure to submit */
2b08b3e9
DB		 3292 cp->dev_handle = cpu_to_le16(ioaccel_handle & 0xFFFF);
3293 cp->transfer_len = cpu_to_le32(total_len);
3294 cp->io_flags = cpu_to_le16(IOACCEL1_IOFLAGS_IO_REQ |
3295 (cdb_len & IOACCEL1_IOFLAGS_CDBLEN_MASK));
3296 cp->control = cpu_to_le32(control);
283b4a9b
SC		 3297 memcpy(cp->CDB, cdb, cdb_len);
3298 memcpy(cp->CISS_LUN, scsi3addr, 8);
c349775e 3299 /* Tag was already set at init time. */
283b4a9b 3300 enqueue_cmd_and_start_io(h, c);
e1f7de0c
MG		 3301 return 0;
3302}
edd16368 3303
283b4a9b
SC		 3304/*
3305 * Queue a command directly to a device behind the controller using the
3306 * I/O accelerator path.
3307 */
3308static int hpsa_scsi_ioaccel_direct_map(struct ctlr_info *h,
3309 struct CommandList *c)
3310{
3311 struct scsi_cmnd *cmd = c->scsi_cmd;
3312 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
3313
3314 return hpsa_scsi_ioaccel_queue_command(h, c, dev->ioaccel_handle,
3315 cmd->cmnd, cmd->cmd_len, dev->scsi3addr);
3316}
3317
dd0e19f3
ST		 3318/*
3319 * Set encryption parameters for the ioaccel2 request
3320 */
3321static void set_encrypt_ioaccel2(struct ctlr_info *h,
3322 struct CommandList *c, struct io_accel2_cmd *cp)
3323{
3324 struct scsi_cmnd *cmd = c->scsi_cmd;
3325 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
3326 struct raid_map_data *map = &dev->raid_map;
3327 u64 first_block;
3328
3329 BUG_ON(!(dev->offload_config && dev->offload_enabled));
3330
3331 /* Are we doing encryption on this device */
2b08b3e9 3332 if (!(le16_to_cpu(map->flags) & RAID_MAP_FLAG_ENCRYPT_ON))
dd0e19f3
ST		 3333 return;
3334 /* Set the data encryption key index. */
3335 cp->dekindex = map->dekindex;
3336
3337 /* Set the encryption enable flag, encoded into direction field. */
3338 cp->direction |= IOACCEL2_DIRECTION_ENCRYPT_MASK;
3339
3340 /* Set encryption tweak values based on logical block address
3341 * If block size is 512, tweak value is LBA.
3342 * For other block sizes, tweak is (LBA * block size)/ 512)
3343 */
3344 switch (cmd->cmnd[0]) {
3345 /* Required? 6-byte cdbs eliminated by fixup_ioaccel_cdb */
3346 case WRITE_6:
3347 case READ_6:
2b08b3e9 3348 first_block = get_unaligned_be16(&cmd->cmnd[2]);
dd0e19f3
ST		 3349 break;
3350 case WRITE_10:
3351 case READ_10:
dd0e19f3
ST		 3352 /* Required? 12-byte cdbs eliminated by fixup_ioaccel_cdb */
3353 case WRITE_12:
3354 case READ_12:
2b08b3e9 3355 first_block = get_unaligned_be32(&cmd->cmnd[2]);
dd0e19f3
ST		 3356 break;
3357 case WRITE_16:
3358 case READ_16:
2b08b3e9 3359 first_block = get_unaligned_be64(&cmd->cmnd[2]);
dd0e19f3
ST		 3360 break;
3361 default:
3362 dev_err(&h->pdev->dev,
2b08b3e9
DB		 3363 "ERROR: %s: size (0x%x) not supported for encryption\n",
3364 __func__, cmd->cmnd[0]);
dd0e19f3
ST		 3365 BUG();
3366 break;
3367 }
2b08b3e9
DB		 3368
3369 if (le32_to_cpu(map->volume_blk_size) != 512)
3370 first_block = first_block *
3371 le32_to_cpu(map->volume_blk_size)/512;
3372
3373 cp->tweak_lower = cpu_to_le32(first_block);
3374 cp->tweak_upper = cpu_to_le32(first_block >> 32);
dd0e19f3
ST		 3375}
3376
c349775e
ST		 3377static int hpsa_scsi_ioaccel2_queue_command(struct ctlr_info *h,
3378 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
3379 u8 *scsi3addr)
3380{
3381 struct scsi_cmnd *cmd = c->scsi_cmd;
3382 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
3383 struct ioaccel2_sg_element *curr_sg;
3384 int use_sg, i;
3385 struct scatterlist *sg;
3386 u64 addr64;
3387 u32 len;
3388 u32 total_len = 0;
3389
3390 if (scsi_sg_count(cmd) > h->ioaccel_maxsg)
3391 return IO_ACCEL_INELIGIBLE;
3392
3393 if (fixup_ioaccel_cdb(cdb, &cdb_len))
3394 return IO_ACCEL_INELIGIBLE;
3395 c->cmd_type = CMD_IOACCEL2;
3396 /* Adjust the DMA address to point to the accelerated command buffer */
3397 c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle +
3398 (c->cmdindex * sizeof(*cp));
3399 BUG_ON(c->busaddr & 0x0000007F);
3400
3401 memset(cp, 0, sizeof(*cp));
3402 cp->IU_type = IOACCEL2_IU_TYPE;
3403
3404 use_sg = scsi_dma_map(cmd);
3405 if (use_sg < 0)
3406 return use_sg;
3407
3408 if (use_sg) {
3409 BUG_ON(use_sg > IOACCEL2_MAXSGENTRIES);
3410 curr_sg = cp->sg;
3411 scsi_for_each_sg(cmd, sg, use_sg, i) {
3412 addr64 = (u64) sg_dma_address(sg);
3413 len = sg_dma_len(sg);
3414 total_len += len;
3415 curr_sg->address = cpu_to_le64(addr64);
3416 curr_sg->length = cpu_to_le32(len);
3417 curr_sg->reserved[0] = 0;
3418 curr_sg->reserved[1] = 0;
3419 curr_sg->reserved[2] = 0;
3420 curr_sg->chain_indicator = 0;
3421 curr_sg++;
3422 }
3423
3424 switch (cmd->sc_data_direction) {
3425 case DMA_TO_DEVICE:
dd0e19f3
ST		 3426 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3427 cp->direction |= IOACCEL2_DIR_DATA_OUT;
c349775e
ST		 3428 break;
3429 case DMA_FROM_DEVICE:
dd0e19f3
ST		 3430 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3431 cp->direction |= IOACCEL2_DIR_DATA_IN;
c349775e
ST		 3432 break;
3433 case DMA_NONE:
dd0e19f3
ST		 3434 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3435 cp->direction |= IOACCEL2_DIR_NO_DATA;
c349775e
ST		 3436 break;
3437 default:
3438 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
3439 cmd->sc_data_direction);
3440 BUG();
3441 break;
3442 }
3443 } else {
dd0e19f3
ST		 3444 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3445 cp->direction |= IOACCEL2_DIR_NO_DATA;
c349775e 3446 }
dd0e19f3
ST		 3447
3448 /* Set encryption parameters, if necessary */
3449 set_encrypt_ioaccel2(h, c, cp);
3450
2b08b3e9
DB		 3451 cp->scsi_nexus = cpu_to_le32(ioaccel_handle);
3452 cp->Tag = cpu_to_le32(c->cmdindex << DIRECT_LOOKUP_SHIFT |
3453 DIRECT_LOOKUP_BIT);
c349775e 3454 memcpy(cp->cdb, cdb, sizeof(cp->cdb));
c349775e
ST		 3455
3456 /* fill in sg elements */
3457 cp->sg_count = (u8) use_sg;
3458
3459 cp->data_len = cpu_to_le32(total_len);
3460 cp->err_ptr = cpu_to_le64(c->busaddr +
3461 offsetof(struct io_accel2_cmd, error_data));
50a0decf 3462 cp->err_len = cpu_to_le32(sizeof(cp->error_data));
c349775e
ST		 3463
3464 enqueue_cmd_and_start_io(h, c);
3465 return 0;
3466}
3467
3468/*
3469 * Queue a command to the correct I/O accelerator path.
3470 */
3471static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
3472 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
3473 u8 *scsi3addr)
3474{
3475 if (h->transMethod & CFGTBL_Trans_io_accel1)
3476 return hpsa_scsi_ioaccel1_queue_command(h, c, ioaccel_handle,
3477 cdb, cdb_len, scsi3addr);
3478 else
3479 return hpsa_scsi_ioaccel2_queue_command(h, c, ioaccel_handle,
3480 cdb, cdb_len, scsi3addr);
3481}
3482
6b80b18f
ST		 3483static void raid_map_helper(struct raid_map_data *map,
3484 int offload_to_mirror, u32 *map_index, u32 *current_group)
3485{
3486 if (offload_to_mirror == 0) {
3487 /* use physical disk in the first mirrored group. */
2b08b3e9 3488 *map_index %= le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 3489 return;
3490 }
3491 do {
3492 /* determine mirror group that *map_index indicates */
2b08b3e9
DB		 3493 *current_group = *map_index /
3494 le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 3495 if (offload_to_mirror == *current_group)
3496 continue;
2b08b3e9 3497 if (*current_group < le16_to_cpu(map->layout_map_count) - 1) {
6b80b18f 3498 /* select map index from next group */
2b08b3e9 3499 *map_index += le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 3500 (*current_group)++;
3501 } else {
3502 /* select map index from first group */
2b08b3e9 3503 *map_index %= le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 3504 *current_group = 0;
3505 }
3506 } while (offload_to_mirror != *current_group);
3507}
3508
283b4a9b
SC		 3509/*
3510 * Attempt to perform offload RAID mapping for a logical volume I/O.
3511 */
3512static int hpsa_scsi_ioaccel_raid_map(struct ctlr_info *h,
3513 struct CommandList *c)
3514{
3515 struct scsi_cmnd *cmd = c->scsi_cmd;
3516 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
3517 struct raid_map_data *map = &dev->raid_map;
3518 struct raid_map_disk_data *dd = &map->data[0];
3519 int is_write = 0;
3520 u32 map_index;
3521 u64 first_block, last_block;
3522 u32 block_cnt;
3523 u32 blocks_per_row;
3524 u64 first_row, last_row;
3525 u32 first_row_offset, last_row_offset;
3526 u32 first_column, last_column;
6b80b18f
ST		 3527 u64 r0_first_row, r0_last_row;
3528 u32 r5or6_blocks_per_row;
3529 u64 r5or6_first_row, r5or6_last_row;
3530 u32 r5or6_first_row_offset, r5or6_last_row_offset;
3531 u32 r5or6_first_column, r5or6_last_column;
3532 u32 total_disks_per_row;
3533 u32 stripesize;
3534 u32 first_group, last_group, current_group;
283b4a9b
SC		 3535 u32 map_row;
3536 u32 disk_handle;
3537 u64 disk_block;
3538 u32 disk_block_cnt;
3539 u8 cdb[16];
3540 u8 cdb_len;
2b08b3e9 3541 u16 strip_size;
283b4a9b
SC		 3542#if BITS_PER_LONG == 32
3543 u64 tmpdiv;
3544#endif
6b80b18f 3545 int offload_to_mirror;
283b4a9b
SC		 3546
3547 BUG_ON(!(dev->offload_config && dev->offload_enabled));
3548
3549 /* check for valid opcode, get LBA and block count */
3550 switch (cmd->cmnd[0]) {
3551 case WRITE_6:
3552 is_write = 1;
3553 case READ_6:
3554 first_block =
3555 (((u64) cmd->cmnd[2]) << 8) |
3556 cmd->cmnd[3];
3557 block_cnt = cmd->cmnd[4];
3fa89a04
SC		 3558 if (block_cnt == 0)
3559 block_cnt = 256;
283b4a9b
SC		 3560 break;
3561 case WRITE_10:
3562 is_write = 1;
3563 case READ_10:
3564 first_block =
3565 (((u64) cmd->cmnd[2]) << 24) |
3566 (((u64) cmd->cmnd[3]) << 16) |
3567 (((u64) cmd->cmnd[4]) << 8) |
3568 cmd->cmnd[5];
3569 block_cnt =
3570 (((u32) cmd->cmnd[7]) << 8) |
3571 cmd->cmnd[8];
3572 break;
3573 case WRITE_12:
3574 is_write = 1;
3575 case READ_12:
3576 first_block =
3577 (((u64) cmd->cmnd[2]) << 24) |
3578 (((u64) cmd->cmnd[3]) << 16) |
3579 (((u64) cmd->cmnd[4]) << 8) |
3580 cmd->cmnd[5];
3581 block_cnt =
3582 (((u32) cmd->cmnd[6]) << 24) |
3583 (((u32) cmd->cmnd[7]) << 16) |
3584 (((u32) cmd->cmnd[8]) << 8) |
3585 cmd->cmnd[9];
3586 break;
3587 case WRITE_16:
3588 is_write = 1;
3589 case READ_16:
3590 first_block =
3591 (((u64) cmd->cmnd[2]) << 56) |
3592 (((u64) cmd->cmnd[3]) << 48) |
3593 (((u64) cmd->cmnd[4]) << 40) |
3594 (((u64) cmd->cmnd[5]) << 32) |
3595 (((u64) cmd->cmnd[6]) << 24) |
3596 (((u64) cmd->cmnd[7]) << 16) |
3597 (((u64) cmd->cmnd[8]) << 8) |
3598 cmd->cmnd[9];
3599 block_cnt =
3600 (((u32) cmd->cmnd[10]) << 24) |
3601 (((u32) cmd->cmnd[11]) << 16) |
3602 (((u32) cmd->cmnd[12]) << 8) |
3603 cmd->cmnd[13];
3604 break;
3605 default:
3606 return IO_ACCEL_INELIGIBLE; /* process via normal I/O path */
3607 }
283b4a9b
SC		 3608 last_block = first_block + block_cnt - 1;
3609
3610 /* check for write to non-RAID-0 */
3611 if (is_write && dev->raid_level != 0)
3612 return IO_ACCEL_INELIGIBLE;
3613
3614 /* check for invalid block or wraparound */
2b08b3e9
DB		 3615 if (last_block >= le64_to_cpu(map->volume_blk_cnt) ||
3616 last_block < first_block)
283b4a9b
SC		 3617 return IO_ACCEL_INELIGIBLE;
3618
3619 /* calculate stripe information for the request */
2b08b3e9
DB		 3620 blocks_per_row = le16_to_cpu(map->data_disks_per_row) *
3621 le16_to_cpu(map->strip_size);
3622 strip_size = le16_to_cpu(map->strip_size);
283b4a9b
SC		 3623#if BITS_PER_LONG == 32
3624 tmpdiv = first_block;
3625 (void) do_div(tmpdiv, blocks_per_row);
3626 first_row = tmpdiv;
3627 tmpdiv = last_block;
3628 (void) do_div(tmpdiv, blocks_per_row);
3629 last_row = tmpdiv;
3630 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
3631 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
3632 tmpdiv = first_row_offset;
2b08b3e9 3633 (void) do_div(tmpdiv, strip_size);
283b4a9b
SC		 3634 first_column = tmpdiv;
3635 tmpdiv = last_row_offset;
2b08b3e9 3636 (void) do_div(tmpdiv, strip_size);
283b4a9b
SC		 3637 last_column = tmpdiv;
3638#else
3639 first_row = first_block / blocks_per_row;
3640 last_row = last_block / blocks_per_row;
3641 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
3642 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
2b08b3e9
DB		 3643 first_column = first_row_offset / strip_size;
3644 last_column = last_row_offset / strip_size;
283b4a9b
SC		 3645#endif
3646
3647 /* if this isn't a single row/column then give to the controller */
3648 if ((first_row != last_row) || (first_column != last_column))
3649 return IO_ACCEL_INELIGIBLE;
3650
3651 /* proceeding with driver mapping */
2b08b3e9
DB		 3652 total_disks_per_row = le16_to_cpu(map->data_disks_per_row) +
3653 le16_to_cpu(map->metadata_disks_per_row);
283b4a9b 3654 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
2b08b3e9 3655 le16_to_cpu(map->row_cnt);
6b80b18f
ST		 3656 map_index = (map_row * total_disks_per_row) + first_column;
3657
3658 switch (dev->raid_level) {
3659 case HPSA_RAID_0:
3660 break; /* nothing special to do */
3661 case HPSA_RAID_1:
3662 /* Handles load balance across RAID 1 members.
3663 * (2-drive R1 and R10 with even # of drives.)
3664 * Appropriate for SSDs, not optimal for HDDs
283b4a9b 3665 */
2b08b3e9 3666 BUG_ON(le16_to_cpu(map->layout_map_count) != 2);
283b4a9b 3667 if (dev->offload_to_mirror)
2b08b3e9 3668 map_index += le16_to_cpu(map->data_disks_per_row);
283b4a9b 3669 dev->offload_to_mirror = !dev->offload_to_mirror;
6b80b18f
ST		 3670 break;
3671 case HPSA_RAID_ADM:
3672 /* Handles N-way mirrors (R1-ADM)
3673 * and R10 with # of drives divisible by 3.)
3674 */
2b08b3e9 3675 BUG_ON(le16_to_cpu(map->layout_map_count) != 3);
6b80b18f
ST		 3676
3677 offload_to_mirror = dev->offload_to_mirror;
3678 raid_map_helper(map, offload_to_mirror,
3679 &map_index, &current_group);
3680 /* set mirror group to use next time */
3681 offload_to_mirror =
2b08b3e9
DB		 3682 (offload_to_mirror >=
3683 le16_to_cpu(map->layout_map_count) - 1)
6b80b18f 3684 ? 0 : offload_to_mirror + 1;
6b80b18f
ST		 3685 dev->offload_to_mirror = offload_to_mirror;
3686 /* Avoid direct use of dev->offload_to_mirror within this
3687 * function since multiple threads might simultaneously
3688 * increment it beyond the range of dev->layout_map_count -1.
3689 */
3690 break;
3691 case HPSA_RAID_5:
3692 case HPSA_RAID_6:
2b08b3e9 3693 if (le16_to_cpu(map->layout_map_count) <= 1)
6b80b18f
ST		 3694 break;
3695
3696 /* Verify first and last block are in same RAID group */
3697 r5or6_blocks_per_row =
2b08b3e9
DB		 3698 le16_to_cpu(map->strip_size) *
3699 le16_to_cpu(map->data_disks_per_row);
6b80b18f 3700 BUG_ON(r5or6_blocks_per_row == 0);
2b08b3e9
DB		 3701 stripesize = r5or6_blocks_per_row *
3702 le16_to_cpu(map->layout_map_count);
6b80b18f
ST		 3703#if BITS_PER_LONG == 32
3704 tmpdiv = first_block;
3705 first_group = do_div(tmpdiv, stripesize);
3706 tmpdiv = first_group;
3707 (void) do_div(tmpdiv, r5or6_blocks_per_row);
3708 first_group = tmpdiv;
3709 tmpdiv = last_block;
3710 last_group = do_div(tmpdiv, stripesize);
3711 tmpdiv = last_group;
3712 (void) do_div(tmpdiv, r5or6_blocks_per_row);
3713 last_group = tmpdiv;
3714#else
3715 first_group = (first_block % stripesize) / r5or6_blocks_per_row;
3716 last_group = (last_block % stripesize) / r5or6_blocks_per_row;
6b80b18f 3717#endif
000ff7c2 3718 if (first_group != last_group)
6b80b18f
ST		 3719 return IO_ACCEL_INELIGIBLE;
3720
3721 /* Verify request is in a single row of RAID 5/6 */
3722#if BITS_PER_LONG == 32
3723 tmpdiv = first_block;
3724 (void) do_div(tmpdiv, stripesize);
3725 first_row = r5or6_first_row = r0_first_row = tmpdiv;
3726 tmpdiv = last_block;
3727 (void) do_div(tmpdiv, stripesize);
3728 r5or6_last_row = r0_last_row = tmpdiv;
3729#else
3730 first_row = r5or6_first_row = r0_first_row =
3731 first_block / stripesize;
3732 r5or6_last_row = r0_last_row = last_block / stripesize;
3733#endif
3734 if (r5or6_first_row != r5or6_last_row)
3735 return IO_ACCEL_INELIGIBLE;
3736
3737
3738 /* Verify request is in a single column */
3739#if BITS_PER_LONG == 32
3740 tmpdiv = first_block;
3741 first_row_offset = do_div(tmpdiv, stripesize);
3742 tmpdiv = first_row_offset;
3743 first_row_offset = (u32) do_div(tmpdiv, r5or6_blocks_per_row);
3744 r5or6_first_row_offset = first_row_offset;
3745 tmpdiv = last_block;
3746 r5or6_last_row_offset = do_div(tmpdiv, stripesize);
3747 tmpdiv = r5or6_last_row_offset;
3748 r5or6_last_row_offset = do_div(tmpdiv, r5or6_blocks_per_row);
3749 tmpdiv = r5or6_first_row_offset;
3750 (void) do_div(tmpdiv, map->strip_size);
3751 first_column = r5or6_first_column = tmpdiv;
3752 tmpdiv = r5or6_last_row_offset;
3753 (void) do_div(tmpdiv, map->strip_size);
3754 r5or6_last_column = tmpdiv;
3755#else
3756 first_row_offset = r5or6_first_row_offset =
3757 (u32)((first_block % stripesize) %
3758 r5or6_blocks_per_row);
3759
3760 r5or6_last_row_offset =
3761 (u32)((last_block % stripesize) %
3762 r5or6_blocks_per_row);
3763
3764 first_column = r5or6_first_column =
2b08b3e9 3765 r5or6_first_row_offset / le16_to_cpu(map->strip_size);
6b80b18f 3766 r5or6_last_column =
2b08b3e9 3767 r5or6_last_row_offset / le16_to_cpu(map->strip_size);
6b80b18f
ST		 3768#endif
3769 if (r5or6_first_column != r5or6_last_column)
3770 return IO_ACCEL_INELIGIBLE;
3771
3772 /* Request is eligible */
3773 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
2b08b3e9 3774 le16_to_cpu(map->row_cnt);
6b80b18f
ST		 3775
3776 map_index = (first_group *
2b08b3e9 3777 (le16_to_cpu(map->row_cnt) * total_disks_per_row)) +
6b80b18f
ST		 3778 (map_row * total_disks_per_row) + first_column;
3779 break;
3780 default:
3781 return IO_ACCEL_INELIGIBLE;
283b4a9b 3782 }
6b80b18f 3783
283b4a9b 3784 disk_handle = dd[map_index].ioaccel_handle;
2b08b3e9
DB		 3785 disk_block = le64_to_cpu(map->disk_starting_blk) +
3786 first_row * le16_to_cpu(map->strip_size) +
3787 (first_row_offset - first_column *
3788 le16_to_cpu(map->strip_size));
283b4a9b
SC		 3789 disk_block_cnt = block_cnt;
3790
3791 /* handle differing logical/physical block sizes */
3792 if (map->phys_blk_shift) {
3793 disk_block <<= map->phys_blk_shift;
3794 disk_block_cnt <<= map->phys_blk_shift;
3795 }
3796 BUG_ON(disk_block_cnt > 0xffff);
3797
3798 /* build the new CDB for the physical disk I/O */
3799 if (disk_block > 0xffffffff) {
3800 cdb[0] = is_write ? WRITE_16 : READ_16;
3801 cdb[1] = 0;
3802 cdb[2] = (u8) (disk_block >> 56);
3803 cdb[3] = (u8) (disk_block >> 48);
3804 cdb[4] = (u8) (disk_block >> 40);
3805 cdb[5] = (u8) (disk_block >> 32);
3806 cdb[6] = (u8) (disk_block >> 24);
3807 cdb[7] = (u8) (disk_block >> 16);
3808 cdb[8] = (u8) (disk_block >> 8);
3809 cdb[9] = (u8) (disk_block);
3810 cdb[10] = (u8) (disk_block_cnt >> 24);
3811 cdb[11] = (u8) (disk_block_cnt >> 16);
3812 cdb[12] = (u8) (disk_block_cnt >> 8);
3813 cdb[13] = (u8) (disk_block_cnt);
3814 cdb[14] = 0;
3815 cdb[15] = 0;
3816 cdb_len = 16;
3817 } else {
3818 cdb[0] = is_write ? WRITE_10 : READ_10;
3819 cdb[1] = 0;
3820 cdb[2] = (u8) (disk_block >> 24);
3821 cdb[3] = (u8) (disk_block >> 16);
3822 cdb[4] = (u8) (disk_block >> 8);
3823 cdb[5] = (u8) (disk_block);
3824 cdb[6] = 0;
3825 cdb[7] = (u8) (disk_block_cnt >> 8);
3826 cdb[8] = (u8) (disk_block_cnt);
3827 cdb[9] = 0;
3828 cdb_len = 10;
3829 }
3830 return hpsa_scsi_ioaccel_queue_command(h, c, disk_handle, cdb, cdb_len,
3831 dev->scsi3addr);
3832}
3833
763aadbf
NB		 3834/*
3835 * Running in struct Scsi_Host->host_lock less mode using LLD internal
3836 * struct ctlr_info *h->lock w/ spin_lock_irqsave() protection.
3837 */
3838static int hpsa_scsi_queue_command(struct Scsi_Host *sh, struct scsi_cmnd *cmd)
edd16368
SC		 3839{
3840 struct ctlr_info *h;
3841 struct hpsa_scsi_dev_t *dev;
3842 unsigned char scsi3addr[8];
3843 struct CommandList *c;
283b4a9b 3844 int rc = 0;
edd16368
SC		 3845
3846 /* Get the ptr to our adapter structure out of cmd->host. */
3847 h = sdev_to_hba(cmd->device);
3848 dev = cmd->device->hostdata;
3849 if (!dev) {
3850 cmd->result = DID_NO_CONNECT << 16;
763aadbf 3851 cmd->scsi_done(cmd);
edd16368
SC		 3852 return 0;
3853 }
3854 memcpy(scsi3addr, dev->scsi3addr, sizeof(scsi3addr));
3855
094963da 3856 if (unlikely(lockup_detected(h))) {
a0c12413 3857 cmd->result = DID_ERROR << 16;
763aadbf 3858 cmd->scsi_done(cmd);
a0c12413
SC		 3859 return 0;
3860 }
e16a33ad 3861 c = cmd_alloc(h);
edd16368
SC		 3862 if (c == NULL) { /* trouble... */
3863 dev_err(&h->pdev->dev, "cmd_alloc returned NULL!\n");
3864 return SCSI_MLQUEUE_HOST_BUSY;
3865 }
3866
3867 /* Fill in the command list header */
edd16368
SC		 3868 /* save c in case we have to abort it */
3869 cmd->host_scribble = (unsigned char *) c;
3870
3871 c->cmd_type = CMD_SCSI;
3872 c->scsi_cmd = cmd;
e1f7de0c 3873
283b4a9b
SC		 3874 /* Call alternate submit routine for I/O accelerated commands.
3875 * Retries always go down the normal I/O path.
3876 */
3877 if (likely(cmd->retries == 0 &&
da0697bd
ST		 3878 cmd->request->cmd_type == REQ_TYPE_FS &&
3879 h->acciopath_status)) {
283b4a9b
SC		 3880 if (dev->offload_enabled) {
3881 rc = hpsa_scsi_ioaccel_raid_map(h, c);
3882 if (rc == 0)
3883 return 0; /* Sent on ioaccel path */
3884 if (rc < 0) { /* scsi_dma_map failed. */
3885 cmd_free(h, c);
3886 return SCSI_MLQUEUE_HOST_BUSY;
3887 }
3888 } else if (dev->ioaccel_handle) {
3889 rc = hpsa_scsi_ioaccel_direct_map(h, c);
3890 if (rc == 0)
3891 return 0; /* Sent on direct map path */
3892 if (rc < 0) { /* scsi_dma_map failed. */
3893 cmd_free(h, c);
3894 return SCSI_MLQUEUE_HOST_BUSY;
3895 }
3896 }
3897 }
e1f7de0c 3898
edd16368
SC		 3899 c->Header.ReplyQueue = 0; /* unused in simple mode */
3900 memcpy(&c->Header.LUN.LunAddrBytes[0], &scsi3addr[0], 8);
50a0decf
SC		 3901 c->Header.tag = cpu_to_le64((c->cmdindex << DIRECT_LOOKUP_SHIFT) |
3902 DIRECT_LOOKUP_BIT);
edd16368
SC		 3903
3904 /* Fill in the request block... */
3905
3906 c->Request.Timeout = 0;
3907 memset(c->Request.CDB, 0, sizeof(c->Request.CDB));
3908 BUG_ON(cmd->cmd_len > sizeof(c->Request.CDB));
3909 c->Request.CDBLen = cmd->cmd_len;
3910 memcpy(c->Request.CDB, cmd->cmnd, cmd->cmd_len);
edd16368
SC		 3911 switch (cmd->sc_data_direction) {
3912 case DMA_TO_DEVICE:
a505b86f
SC		 3913 c->Request.type_attr_dir =
3914 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_WRITE);
edd16368
SC		 3915 break;
3916 case DMA_FROM_DEVICE:
a505b86f
SC		 3917 c->Request.type_attr_dir =
3918 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 3919 break;
3920 case DMA_NONE:
a505b86f
SC		 3921 c->Request.type_attr_dir =
3922 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_NONE);
edd16368
SC		 3923 break;
3924 case DMA_BIDIRECTIONAL:
3925 /* This can happen if a buggy application does a scsi passthru
3926 * and sets both inlen and outlen to non-zero. ( see
3927 * ../scsi/scsi_ioctl.c:scsi_ioctl_send_command() )
3928 */
3929
a505b86f
SC		 3930 c->Request.type_attr_dir =
3931 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_RSVD);
edd16368
SC		 3932 /* This is technically wrong, and hpsa controllers should
3933 * reject it with CMD_INVALID, which is the most correct
3934 * response, but non-fibre backends appear to let it
3935 * slide by, and give the same results as if this field
3936 * were set correctly. Either way is acceptable for
3937 * our purposes here.
3938 */
3939
3940 break;
3941
3942 default:
3943 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
3944 cmd->sc_data_direction);
3945 BUG();
3946 break;
3947 }
3948
33a2ffce 3949 if (hpsa_scatter_gather(h, c, cmd) < 0) { /* Fill SG list */
edd16368
SC		 3950 cmd_free(h, c);
3951 return SCSI_MLQUEUE_HOST_BUSY;
3952 }
3953 enqueue_cmd_and_start_io(h, c);
3954 /* the cmd'll come back via intr handler in complete_scsi_command() */
3955 return 0;
3956}
3957
5f389360
SC		 3958static int do_not_scan_if_controller_locked_up(struct ctlr_info *h)
3959{
3960 unsigned long flags;
3961
3962 /*
3963 * Don't let rescans be initiated on a controller known
3964 * to be locked up. If the controller locks up *during*
3965 * a rescan, that thread is probably hosed, but at least
3966 * we can prevent new rescan threads from piling up on a
3967 * locked up controller.
3968 */
094963da 3969 if (unlikely(lockup_detected(h))) {
5f389360
SC		 3970 spin_lock_irqsave(&h->scan_lock, flags);
3971 h->scan_finished = 1;
3972 wake_up_all(&h->scan_wait_queue);
3973 spin_unlock_irqrestore(&h->scan_lock, flags);
3974 return 1;
3975 }
5f389360
SC		 3976 return 0;
3977}
3978
a08a8471
SC		 3979static void hpsa_scan_start(struct Scsi_Host *sh)
3980{
3981 struct ctlr_info *h = shost_to_hba(sh);
3982 unsigned long flags;
3983
5f389360
SC		 3984 if (do_not_scan_if_controller_locked_up(h))
3985 return;
3986
a08a8471
SC		 3987 /* wait until any scan already in progress is finished. */
3988 while (1) {
3989 spin_lock_irqsave(&h->scan_lock, flags);
3990 if (h->scan_finished)
3991 break;
3992 spin_unlock_irqrestore(&h->scan_lock, flags);
3993 wait_event(h->scan_wait_queue, h->scan_finished);
3994 /* Note: We don't need to worry about a race between this
3995 * thread and driver unload because the midlayer will
3996 * have incremented the reference count, so unload won't
3997 * happen if we're in here.
3998 */
3999 }
4000 h->scan_finished = 0; /* mark scan as in progress */
4001 spin_unlock_irqrestore(&h->scan_lock, flags);
4002
5f389360
SC		 4003 if (do_not_scan_if_controller_locked_up(h))
4004 return;
4005
a08a8471
SC		 4006 hpsa_update_scsi_devices(h, h->scsi_host->host_no);
4007
4008 spin_lock_irqsave(&h->scan_lock, flags);
4009 h->scan_finished = 1; /* mark scan as finished. */
4010 wake_up_all(&h->scan_wait_queue);
4011 spin_unlock_irqrestore(&h->scan_lock, flags);
4012}
4013
7c0a0229
DB		 4014static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth)
4015{
4016 struct ctlr_info *h = sdev_to_hba(sdev);
4017
4018 if (qdepth < 1)
4019 qdepth = 1;
4020 else
4021 if (qdepth > h->nr_cmds)
4022 qdepth = h->nr_cmds;
4023 scsi_change_queue_depth(sdev, qdepth);
4024 return sdev->queue_depth;
4025}
4026
a08a8471
SC		 4027static int hpsa_scan_finished(struct Scsi_Host *sh,
4028 unsigned long elapsed_time)
4029{
4030 struct ctlr_info *h = shost_to_hba(sh);
4031 unsigned long flags;
4032 int finished;
4033
4034 spin_lock_irqsave(&h->scan_lock, flags);
4035 finished = h->scan_finished;
4036 spin_unlock_irqrestore(&h->scan_lock, flags);
4037 return finished;
4038}
4039
edd16368
SC		 4040static void hpsa_unregister_scsi(struct ctlr_info *h)
4041{
4042 /* we are being forcibly unloaded, and may not refuse. */
4043 scsi_remove_host(h->scsi_host);
4044 scsi_host_put(h->scsi_host);
4045 h->scsi_host = NULL;
4046}
4047
4048static int hpsa_register_scsi(struct ctlr_info *h)
4049{
b705690d
SC		 4050 struct Scsi_Host *sh;
4051 int error;
edd16368 4052
b705690d
SC		 4053 sh = scsi_host_alloc(&hpsa_driver_template, sizeof(h));
4054 if (sh == NULL)
4055 goto fail;
4056
4057 sh->io_port = 0;
4058 sh->n_io_port = 0;
4059 sh->this_id = -1;
4060 sh->max_channel = 3;
4061 sh->max_cmd_len = MAX_COMMAND_SIZE;
4062 sh->max_lun = HPSA_MAX_LUN;
4063 sh->max_id = HPSA_MAX_LUN;
d54c5c24
SC		 4064 sh->can_queue = h->nr_cmds -
4065 HPSA_CMDS_RESERVED_FOR_ABORTS -
4066 HPSA_CMDS_RESERVED_FOR_DRIVER -
4067 HPSA_MAX_CONCURRENT_PASSTHRUS;
316b221a
SC		 4068 if (h->hba_mode_enabled)
4069 sh->cmd_per_lun = 7;
4070 else
d54c5c24 4071 sh->cmd_per_lun = sh->can_queue;
b705690d
SC		 4072 sh->sg_tablesize = h->maxsgentries;
4073 h->scsi_host = sh;
4074 sh->hostdata[0] = (unsigned long) h;
4075 sh->irq = h->intr[h->intr_mode];
4076 sh->unique_id = sh->irq;
4077 error = scsi_add_host(sh, &h->pdev->dev);
4078 if (error)
4079 goto fail_host_put;
4080 scsi_scan_host(sh);
4081 return 0;
4082
4083 fail_host_put:
4084 dev_err(&h->pdev->dev, "%s: scsi_add_host"
4085 " failed for controller %d\n", __func__, h->ctlr);
4086 scsi_host_put(sh);
4087 return error;
4088 fail:
4089 dev_err(&h->pdev->dev, "%s: scsi_host_alloc"
4090 " failed for controller %d\n", __func__, h->ctlr);
4091 return -ENOMEM;
edd16368
SC		 4092}
4093
4094static int wait_for_device_to_become_ready(struct ctlr_info *h,
4095 unsigned char lunaddr[])
4096{
8919358e 4097 int rc;
edd16368
SC		 4098 int count = 0;
4099 int waittime = 1; /* seconds */
4100 struct CommandList *c;
4101
45fcb86e 4102 c = cmd_alloc(h);
edd16368
SC		 4103 if (!c) {
4104 dev_warn(&h->pdev->dev, "out of memory in "
4105 "wait_for_device_to_become_ready.\n");
4106 return IO_ERROR;
4107 }
4108
4109 /* Send test unit ready until device ready, or give up. */
4110 while (count < HPSA_TUR_RETRY_LIMIT) {
4111
4112 /* Wait for a bit. do this first, because if we send
4113 * the TUR right away, the reset will just abort it.
4114 */
4115 msleep(1000 * waittime);
4116 count++;
8919358e 4117 rc = 0; /* Device ready. */
edd16368
SC		 4118
4119 /* Increase wait time with each try, up to a point. */
4120 if (waittime < HPSA_MAX_WAIT_INTERVAL_SECS)
4121 waittime = waittime * 2;
4122
a2dac136
SC		 4123 /* Send the Test Unit Ready, fill_cmd can't fail, no mapping */
4124 (void) fill_cmd(c, TEST_UNIT_READY, h,
4125 NULL, 0, 0, lunaddr, TYPE_CMD);
edd16368
SC		 4126 hpsa_scsi_do_simple_cmd_core(h, c);
4127 /* no unmap needed here because no data xfer. */
4128
4129 if (c->err_info->CommandStatus == CMD_SUCCESS)
4130 break;
4131
4132 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
4133 c->err_info->ScsiStatus == SAM_STAT_CHECK_CONDITION &&
4134 (c->err_info->SenseInfo[2] == NO_SENSE ||
4135 c->err_info->SenseInfo[2] == UNIT_ATTENTION))
4136 break;
4137
4138 dev_warn(&h->pdev->dev, "waiting %d secs "
4139 "for device to become ready.\n", waittime);
4140 rc = 1; /* device not ready. */
4141 }
4142
4143 if (rc)
4144 dev_warn(&h->pdev->dev, "giving up on device.\n");
4145 else
4146 dev_warn(&h->pdev->dev, "device is ready.\n");
4147
45fcb86e 4148 cmd_free(h, c);
edd16368
SC		 4149 return rc;
4150}
4151
4152/* Need at least one of these error handlers to keep ../scsi/hosts.c from
4153 * complaining. Doing a host- or bus-reset can't do anything good here.
4154 */
4155static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd)
4156{
4157 int rc;
4158 struct ctlr_info *h;
4159 struct hpsa_scsi_dev_t *dev;
4160
4161 /* find the controller to which the command to be aborted was sent */
4162 h = sdev_to_hba(scsicmd->device);
4163 if (h == NULL) /* paranoia */
4164 return FAILED;
edd16368
SC		 4165 dev = scsicmd->device->hostdata;
4166 if (!dev) {
4167 dev_err(&h->pdev->dev, "hpsa_eh_device_reset_handler: "
4168 "device lookup failed.\n");
4169 return FAILED;
4170 }
d416b0c7
SC		 4171 dev_warn(&h->pdev->dev, "resetting device %d:%d:%d:%d\n",
4172 h->scsi_host->host_no, dev->bus, dev->target, dev->lun);
edd16368 4173 /* send a reset to the SCSI LUN which the command was sent to */
bf711ac6 4174 rc = hpsa_send_reset(h, dev->scsi3addr, HPSA_RESET_TYPE_LUN);
edd16368
SC		 4175 if (rc == 0 && wait_for_device_to_become_ready(h, dev->scsi3addr) == 0)
4176 return SUCCESS;
4177
4178 dev_warn(&h->pdev->dev, "resetting device failed.\n");
4179 return FAILED;
4180}
4181
6cba3f19
SC		 4182static void swizzle_abort_tag(u8 *tag)
4183{
4184 u8 original_tag[8];
4185
4186 memcpy(original_tag, tag, 8);
4187 tag[0] = original_tag[3];
4188 tag[1] = original_tag[2];
4189 tag[2] = original_tag[1];
4190 tag[3] = original_tag[0];
4191 tag[4] = original_tag[7];
4192 tag[5] = original_tag[6];
4193 tag[6] = original_tag[5];
4194 tag[7] = original_tag[4];
4195}
4196
17eb87d2 4197static void hpsa_get_tag(struct ctlr_info *h,
2b08b3e9 4198 struct CommandList *c, __le32 *taglower, __le32 *tagupper)
17eb87d2 4199{
2b08b3e9 4200 u64 tag;
17eb87d2
ST		 4201 if (c->cmd_type == CMD_IOACCEL1) {
4202 struct io_accel1_cmd *cm1 = (struct io_accel1_cmd *)
4203 &h->ioaccel_cmd_pool[c->cmdindex];
2b08b3e9
DB		 4204 tag = le64_to_cpu(cm1->tag);
4205 *tagupper = cpu_to_le32(tag >> 32);
4206 *taglower = cpu_to_le32(tag);
54b6e9e9
ST		 4207 return;
4208 }
4209 if (c->cmd_type == CMD_IOACCEL2) {
4210 struct io_accel2_cmd *cm2 = (struct io_accel2_cmd *)
4211 &h->ioaccel2_cmd_pool[c->cmdindex];
dd0e19f3
ST		 4212 /* upper tag not used in ioaccel2 mode */
4213 memset(tagupper, 0, sizeof(*tagupper));
4214 *taglower = cm2->Tag;
54b6e9e9 4215 return;
17eb87d2 4216 }
2b08b3e9
DB		 4217 tag = le64_to_cpu(c->Header.tag);
4218 *tagupper = cpu_to_le32(tag >> 32);
4219 *taglower = cpu_to_le32(tag);
17eb87d2
ST		 4220}
4221
75167d2c 4222static int hpsa_send_abort(struct ctlr_info *h, unsigned char *scsi3addr,
6cba3f19 4223 struct CommandList *abort, int swizzle)
75167d2c
SC		 4224{
4225 int rc = IO_OK;
4226 struct CommandList *c;
4227 struct ErrorInfo *ei;
2b08b3e9 4228 __le32 tagupper, taglower;
75167d2c 4229
45fcb86e 4230 c = cmd_alloc(h);
75167d2c 4231 if (c == NULL) { /* trouble... */
45fcb86e 4232 dev_warn(&h->pdev->dev, "cmd_alloc returned NULL!\n");
75167d2c
SC		 4233 return -ENOMEM;
4234 }
4235
a2dac136
SC		 4236 /* fill_cmd can't fail here, no buffer to map */
4237 (void) fill_cmd(c, HPSA_ABORT_MSG, h, abort,
4238 0, 0, scsi3addr, TYPE_MSG);
6cba3f19
SC		 4239 if (swizzle)
4240 swizzle_abort_tag(&c->Request.CDB[4]);
75167d2c 4241 hpsa_scsi_do_simple_cmd_core(h, c);
17eb87d2 4242 hpsa_get_tag(h, abort, &taglower, &tagupper);
75167d2c 4243 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: do_simple_cmd_core completed.\n",
17eb87d2 4244 __func__, tagupper, taglower);
75167d2c
SC		 4245 /* no unmap needed here because no data xfer. */
4246
4247 ei = c->err_info;
4248 switch (ei->CommandStatus) {
4249 case CMD_SUCCESS:
4250 break;
4251 case CMD_UNABORTABLE: /* Very common, don't make noise. */
4252 rc = -1;
4253 break;
4254 default:
4255 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: interpreting error.\n",
17eb87d2 4256 __func__, tagupper, taglower);
d1e8beac 4257 hpsa_scsi_interpret_error(h, c);
75167d2c
SC		 4258 rc = -1;
4259 break;
4260 }
45fcb86e 4261 cmd_free(h, c);
dd0e19f3
ST		 4262 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n",
4263 __func__, tagupper, taglower);
75167d2c
SC		 4264 return rc;
4265}
4266
4267/*
4268 * hpsa_find_cmd_in_queue
4269 *
4270 * Used to determine whether a command (find) is still present
4271 * in queue_head. Optionally excludes the last element of queue_head.
4272 *
4273 * This is used to avoid unnecessary aborts. Commands in h->reqQ have
4274 * not yet been submitted, and so can be aborted by the driver without
4275 * sending an abort to the hardware.
4276 *
4277 * Returns pointer to command if found in queue, NULL otherwise.
4278 */
4279static struct CommandList *hpsa_find_cmd_in_queue(struct ctlr_info *h,
4280 struct scsi_cmnd *find, struct list_head *queue_head)
4281{
4282 unsigned long flags;
4283 struct CommandList *c = NULL; /* ptr into cmpQ */
4284
4285 if (!find)
42a91641 4286 return NULL;
75167d2c
SC		 4287 spin_lock_irqsave(&h->lock, flags);
4288 list_for_each_entry(c, queue_head, list) {
4289 if (c->scsi_cmd == NULL) /* e.g.: passthru ioctl */
4290 continue;
4291 if (c->scsi_cmd == find) {
4292 spin_unlock_irqrestore(&h->lock, flags);
4293 return c;
4294 }
4295 }
4296 spin_unlock_irqrestore(&h->lock, flags);
4297 return NULL;
4298}
4299
6cba3f19
SC		 4300static struct CommandList *hpsa_find_cmd_in_queue_by_tag(struct ctlr_info *h,
4301 u8 *tag, struct list_head *queue_head)
4302{
4303 unsigned long flags;
4304 struct CommandList *c;
4305
4306 spin_lock_irqsave(&h->lock, flags);
4307 list_for_each_entry(c, queue_head, list) {
50a0decf 4308 if (memcmp(&c->Header.tag, tag, 8) != 0)
6cba3f19
SC		 4309 continue;
4310 spin_unlock_irqrestore(&h->lock, flags);
4311 return c;
4312 }
4313 spin_unlock_irqrestore(&h->lock, flags);
4314 return NULL;
4315}
4316
54b6e9e9
ST		 4317/* ioaccel2 path firmware cannot handle abort task requests.
4318 * Change abort requests to physical target reset, and send to the
4319 * address of the physical disk used for the ioaccel 2 command.
4320 * Return 0 on success (IO_OK)
4321 * -1 on failure
4322 */
4323
4324static int hpsa_send_reset_as_abort_ioaccel2(struct ctlr_info *h,
4325 unsigned char *scsi3addr, struct CommandList *abort)
4326{
4327 int rc = IO_OK;
4328 struct scsi_cmnd *scmd; /* scsi command within request being aborted */
4329 struct hpsa_scsi_dev_t *dev; /* device to which scsi cmd was sent */
4330 unsigned char phys_scsi3addr[8]; /* addr of phys disk with volume */
4331 unsigned char *psa = &phys_scsi3addr[0];
4332
4333 /* Get a pointer to the hpsa logical device. */
4334 scmd = (struct scsi_cmnd *) abort->scsi_cmd;
4335 dev = (struct hpsa_scsi_dev_t *)(scmd->device->hostdata);
4336 if (dev == NULL) {
4337 dev_warn(&h->pdev->dev,
4338 "Cannot abort: no device pointer for command.\n");
4339 return -1; /* not abortable */
4340 }
4341
2ba8bfc8
SC		 4342 if (h->raid_offload_debug > 0)
4343 dev_info(&h->pdev->dev,
4344 "Reset as abort: Abort requested on C%d:B%d:T%d:L%d scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4345 h->scsi_host->host_no, dev->bus, dev->target, dev->lun,
4346 scsi3addr[0], scsi3addr[1], scsi3addr[2], scsi3addr[3],
4347 scsi3addr[4], scsi3addr[5], scsi3addr[6], scsi3addr[7]);
4348
54b6e9e9
ST		 4349 if (!dev->offload_enabled) {
4350 dev_warn(&h->pdev->dev,
4351 "Can't abort: device is not operating in HP SSD Smart Path mode.\n");
4352 return -1; /* not abortable */
4353 }
4354
4355 /* Incoming scsi3addr is logical addr. We need physical disk addr. */
4356 if (!hpsa_get_pdisk_of_ioaccel2(h, abort, psa)) {
4357 dev_warn(&h->pdev->dev, "Can't abort: Failed lookup of physical address.\n");
4358 return -1; /* not abortable */
4359 }
4360
4361 /* send the reset */
2ba8bfc8
SC		 4362 if (h->raid_offload_debug > 0)
4363 dev_info(&h->pdev->dev,
4364 "Reset as abort: Resetting physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4365 psa[0], psa[1], psa[2], psa[3],
4366 psa[4], psa[5], psa[6], psa[7]);
54b6e9e9
ST		 4367 rc = hpsa_send_reset(h, psa, HPSA_RESET_TYPE_TARGET);
4368 if (rc != 0) {
4369 dev_warn(&h->pdev->dev,
4370 "Reset as abort: Failed on physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4371 psa[0], psa[1], psa[2], psa[3],
4372 psa[4], psa[5], psa[6], psa[7]);
4373 return rc; /* failed to reset */
4374 }
4375
4376 /* wait for device to recover */
4377 if (wait_for_device_to_become_ready(h, psa) != 0) {
4378 dev_warn(&h->pdev->dev,
4379 "Reset as abort: Failed: Device never recovered from reset: 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4380 psa[0], psa[1], psa[2], psa[3],
4381 psa[4], psa[5], psa[6], psa[7]);
4382 return -1; /* failed to recover */
4383 }
4384
4385 /* device recovered */
4386 dev_info(&h->pdev->dev,
4387 "Reset as abort: Device recovered from reset: scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4388 psa[0], psa[1], psa[2], psa[3],
4389 psa[4], psa[5], psa[6], psa[7]);
4390
4391 return rc; /* success */
4392}
4393
6cba3f19
SC		 4394/* Some Smart Arrays need the abort tag swizzled, and some don't. It's hard to
4395 * tell which kind we're dealing with, so we send the abort both ways. There
4396 * shouldn't be any collisions between swizzled and unswizzled tags due to the
4397 * way we construct our tags but we check anyway in case the assumptions which
4398 * make this true someday become false.
4399 */
4400static int hpsa_send_abort_both_ways(struct ctlr_info *h,
4401 unsigned char *scsi3addr, struct CommandList *abort)
4402{
4403 u8 swizzled_tag[8];
4404 struct CommandList *c;
4405 int rc = 0, rc2 = 0;
4406
54b6e9e9
ST		 4407 /* ioccelerator mode 2 commands should be aborted via the
4408 * accelerated path, since RAID path is unaware of these commands,
4409 * but underlying firmware can't handle abort TMF.
4410 * Change abort to physical device reset.
4411 */
4412 if (abort->cmd_type == CMD_IOACCEL2)
4413 return hpsa_send_reset_as_abort_ioaccel2(h, scsi3addr, abort);
4414
6cba3f19
SC		 4415 /* we do not expect to find the swizzled tag in our queue, but
4416 * check anyway just to be sure the assumptions which make this
4417 * the case haven't become wrong.
4418 */
4419 memcpy(swizzled_tag, &abort->Request.CDB[4], 8);
4420 swizzle_abort_tag(swizzled_tag);
4421 c = hpsa_find_cmd_in_queue_by_tag(h, swizzled_tag, &h->cmpQ);
4422 if (c != NULL) {
4423 dev_warn(&h->pdev->dev, "Unexpectedly found byte-swapped tag in completion queue.\n");
4424 return hpsa_send_abort(h, scsi3addr, abort, 0);
4425 }
4426 rc = hpsa_send_abort(h, scsi3addr, abort, 0);
4427
4428 /* if the command is still in our queue, we can't conclude that it was
4429 * aborted (it might have just completed normally) but in any case
4430 * we don't need to try to abort it another way.
4431 */
4432 c = hpsa_find_cmd_in_queue(h, abort->scsi_cmd, &h->cmpQ);
4433 if (c)
4434 rc2 = hpsa_send_abort(h, scsi3addr, abort, 1);
4435 return rc && rc2;
4436}
4437
75167d2c
SC		 4438/* Send an abort for the specified command.
4439 * If the device and controller support it,
4440 * send a task abort request.
4441 */
4442static int hpsa_eh_abort_handler(struct scsi_cmnd *sc)
4443{
4444
4445 int i, rc;
4446 struct ctlr_info *h;
4447 struct hpsa_scsi_dev_t *dev;
4448 struct CommandList *abort; /* pointer to command to be aborted */
4449 struct CommandList *found;
4450 struct scsi_cmnd *as; /* ptr to scsi cmd inside aborted command. */
4451 char msg[256]; /* For debug messaging. */
4452 int ml = 0;
2b08b3e9 4453 __le32 tagupper, taglower;
75167d2c
SC		 4454
4455 /* Find the controller of the command to be aborted */
4456 h = sdev_to_hba(sc->device);
4457 if (WARN(h == NULL,
4458 "ABORT REQUEST FAILED, Controller lookup failed.\n"))
4459 return FAILED;
4460
4461 /* Check that controller supports some kind of task abort */
4462 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags) &&
4463 !(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
4464 return FAILED;
4465
4466 memset(msg, 0, sizeof(msg));
9cb78c16 4467 ml += sprintf(msg+ml, "ABORT REQUEST on C%d:B%d:T%d:L%llu ",
75167d2c
SC		 4468 h->scsi_host->host_no, sc->device->channel,
4469 sc->device->id, sc->device->lun);
4470
4471 /* Find the device of the command to be aborted */
4472 dev = sc->device->hostdata;
4473 if (!dev) {
4474 dev_err(&h->pdev->dev, "%s FAILED, Device lookup failed.\n",
4475 msg);
4476 return FAILED;
4477 }
4478
4479 /* Get SCSI command to be aborted */
4480 abort = (struct CommandList *) sc->host_scribble;
4481 if (abort == NULL) {
4482 dev_err(&h->pdev->dev, "%s FAILED, Command to abort is NULL.\n",
4483 msg);
4484 return FAILED;
4485 }
17eb87d2
ST		 4486 hpsa_get_tag(h, abort, &taglower, &tagupper);
4487 ml += sprintf(msg+ml, "Tag:0x%08x:%08x ", tagupper, taglower);
75167d2c
SC		 4488 as = (struct scsi_cmnd *) abort->scsi_cmd;
4489 if (as != NULL)
4490 ml += sprintf(msg+ml, "Command:0x%x SN:0x%lx ",
4491 as->cmnd[0], as->serial_number);
4492 dev_dbg(&h->pdev->dev, "%s\n", msg);
4493 dev_warn(&h->pdev->dev, "Abort request on C%d:B%d:T%d:L%d\n",
4494 h->scsi_host->host_no, dev->bus, dev->target, dev->lun);
4495
4496 /* Search reqQ to See if command is queued but not submitted,
4497 * if so, complete the command with aborted status and remove
4498 * it from the reqQ.
4499 */
4500 found = hpsa_find_cmd_in_queue(h, sc, &h->reqQ);
4501 if (found) {
4502 found->err_info->CommandStatus = CMD_ABORTED;
4503 finish_cmd(found);
4504 dev_info(&h->pdev->dev, "%s Request SUCCEEDED (driver queue).\n",
4505 msg);
4506 return SUCCESS;
4507 }
4508
4509 /* not in reqQ, if also not in cmpQ, must have already completed */
4510 found = hpsa_find_cmd_in_queue(h, sc, &h->cmpQ);
4511 if (!found) {
d6ebd0f7 4512 dev_dbg(&h->pdev->dev, "%s Request SUCCEEDED (not known to driver).\n",
75167d2c
SC		 4513 msg);
4514 return SUCCESS;
4515 }
4516
4517 /*
4518 * Command is in flight, or possibly already completed
4519 * by the firmware (but not to the scsi mid layer) but we can't
4520 * distinguish which. Send the abort down.
4521 */
6cba3f19 4522 rc = hpsa_send_abort_both_ways(h, dev->scsi3addr, abort);
75167d2c
SC		 4523 if (rc != 0) {
4524 dev_dbg(&h->pdev->dev, "%s Request FAILED.\n", msg);
4525 dev_warn(&h->pdev->dev, "FAILED abort on device C%d:B%d:T%d:L%d\n",
4526 h->scsi_host->host_no,
4527 dev->bus, dev->target, dev->lun);
4528 return FAILED;
4529 }
4530 dev_info(&h->pdev->dev, "%s REQUEST SUCCEEDED.\n", msg);
4531
4532 /* If the abort(s) above completed and actually aborted the
4533 * command, then the command to be aborted should already be
4534 * completed. If not, wait around a bit more to see if they
4535 * manage to complete normally.
4536 */
4537#define ABORT_COMPLETE_WAIT_SECS 30
4538 for (i = 0; i < ABORT_COMPLETE_WAIT_SECS * 10; i++) {
4539 found = hpsa_find_cmd_in_queue(h, sc, &h->cmpQ);
4540 if (!found)
4541 return SUCCESS;
4542 msleep(100);
4543 }
4544 dev_warn(&h->pdev->dev, "%s FAILED. Aborted command has not completed after %d seconds.\n",
4545 msg, ABORT_COMPLETE_WAIT_SECS);
4546 return FAILED;
4547}
4548
4549
edd16368
SC		 4550/*
4551 * For operations that cannot sleep, a command block is allocated at init,
4552 * and managed by cmd_alloc() and cmd_free() using a simple bitmap to track
4553 * which ones are free or in use. Lock must be held when calling this.
4554 * cmd_free() is the complement.
4555 */
4556static struct CommandList *cmd_alloc(struct ctlr_info *h)
4557{
4558 struct CommandList *c;
4559 int i;
4560 union u64bit temp64;
4561 dma_addr_t cmd_dma_handle, err_dma_handle;
4c413128
SC		 4562 int loopcount;
4563
4564 /* There is some *extremely* small but non-zero chance that that
4565 * multiple threads could get in here, and one thread could
4566 * be scanning through the list of bits looking for a free
4567 * one, but the free ones are always behind him, and other
4568 * threads sneak in behind him and eat them before he can
4569 * get to them, so that while there is always a free one, a
4570 * very unlucky thread might be starved anyway, never able to
4571 * beat the other threads. In reality, this happens so
4572 * infrequently as to be indistinguishable from never.
4573 */
edd16368 4574
4c413128 4575 loopcount = 0;
edd16368
SC		 4576 do {
4577 i = find_first_zero_bit(h->cmd_pool_bits, h->nr_cmds);
4c413128
SC		 4578 if (i == h->nr_cmds)
4579 i = 0;
4580 loopcount++;
4581 } while (test_and_set_bit(i & (BITS_PER_LONG - 1),
4582 h->cmd_pool_bits + (i / BITS_PER_LONG)) != 0 &&
4583 loopcount < 10);
4584
4585 /* Thread got starved? We do not expect this to ever happen. */
4586 if (loopcount >= 10)
4587 return NULL;
e16a33ad 4588
edd16368
SC		 4589 c = h->cmd_pool + i;
4590 memset(c, 0, sizeof(*c));
4591 cmd_dma_handle = h->cmd_pool_dhandle
4592 + i * sizeof(*c);
4593 c->err_info = h->errinfo_pool + i;
4594 memset(c->err_info, 0, sizeof(*c->err_info));
4595 err_dma_handle = h->errinfo_pool_dhandle
4596 + i * sizeof(*c->err_info);
edd16368
SC		 4597
4598 c->cmdindex = i;
4599
9e0fc764 4600 INIT_LIST_HEAD(&c->list);
01a02ffc
SC		 4601 c->busaddr = (u32) cmd_dma_handle;
4602 temp64.val = (u64) err_dma_handle;
50a0decf
SC		 4603 c->ErrDesc.Addr = cpu_to_le64(err_dma_handle);
4604 c->ErrDesc.Len = cpu_to_le32(sizeof(*c->err_info));
edd16368
SC		 4605
4606 c->h = h;
4607 return c;
4608}
4609
edd16368
SC		 4610static void cmd_free(struct ctlr_info *h, struct CommandList *c)
4611{
4612 int i;
4613
4614 i = c - h->cmd_pool;
4615 clear_bit(i & (BITS_PER_LONG - 1),
4616 h->cmd_pool_bits + (i / BITS_PER_LONG));
edd16368
SC		 4617}
4618
edd16368
SC		 4619#ifdef CONFIG_COMPAT
4620
42a91641
DB		 4621static int hpsa_ioctl32_passthru(struct scsi_device *dev, int cmd,
4622 void __user *arg)
edd16368
SC		 4623{
4624 IOCTL32_Command_struct __user *arg32 =
4625 (IOCTL32_Command_struct __user *) arg;
4626 IOCTL_Command_struct arg64;
4627 IOCTL_Command_struct __user *p = compat_alloc_user_space(sizeof(arg64));
4628 int err;
4629 u32 cp;
4630
938abd84 4631 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 4632 err = 0;
4633 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
4634 sizeof(arg64.LUN_info));
4635 err |= copy_from_user(&arg64.Request, &arg32->Request,
4636 sizeof(arg64.Request));
4637 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
4638 sizeof(arg64.error_info));
4639 err |= get_user(arg64.buf_size, &arg32->buf_size);
4640 err |= get_user(cp, &arg32->buf);
4641 arg64.buf = compat_ptr(cp);
4642 err |= copy_to_user(p, &arg64, sizeof(arg64));
4643
4644 if (err)
4645 return -EFAULT;
4646
42a91641 4647 err = hpsa_ioctl(dev, CCISS_PASSTHRU, p);
edd16368
SC		 4648 if (err)
4649 return err;
4650 err |= copy_in_user(&arg32->error_info, &p->error_info,
4651 sizeof(arg32->error_info));
4652 if (err)
4653 return -EFAULT;
4654 return err;
4655}
4656
4657static int hpsa_ioctl32_big_passthru(struct scsi_device *dev,
42a91641 4658 int cmd, void __user *arg)
edd16368
SC		 4659{
4660 BIG_IOCTL32_Command_struct __user *arg32 =
4661 (BIG_IOCTL32_Command_struct __user *) arg;
4662 BIG_IOCTL_Command_struct arg64;
4663 BIG_IOCTL_Command_struct __user *p =
4664 compat_alloc_user_space(sizeof(arg64));
4665 int err;
4666 u32 cp;
4667
938abd84 4668 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 4669 err = 0;
4670 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
4671 sizeof(arg64.LUN_info));
4672 err |= copy_from_user(&arg64.Request, &arg32->Request,
4673 sizeof(arg64.Request));
4674 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
4675 sizeof(arg64.error_info));
4676 err |= get_user(arg64.buf_size, &arg32->buf_size);
4677 err |= get_user(arg64.malloc_size, &arg32->malloc_size);
4678 err |= get_user(cp, &arg32->buf);
4679 arg64.buf = compat_ptr(cp);
4680 err |= copy_to_user(p, &arg64, sizeof(arg64));
4681
4682 if (err)
4683 return -EFAULT;
4684
42a91641 4685 err = hpsa_ioctl(dev, CCISS_BIG_PASSTHRU, p);
edd16368
SC		 4686 if (err)
4687 return err;
4688 err |= copy_in_user(&arg32->error_info, &p->error_info,
4689 sizeof(arg32->error_info));
4690 if (err)
4691 return -EFAULT;
4692 return err;
4693}
71fe75a7 4694
42a91641 4695static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void __user *arg)
71fe75a7
SC		 4696{
4697 switch (cmd) {
4698 case CCISS_GETPCIINFO:
4699 case CCISS_GETINTINFO:
4700 case CCISS_SETINTINFO:
4701 case CCISS_GETNODENAME:
4702 case CCISS_SETNODENAME:
4703 case CCISS_GETHEARTBEAT:
4704 case CCISS_GETBUSTYPES:
4705 case CCISS_GETFIRMVER:
4706 case CCISS_GETDRIVVER:
4707 case CCISS_REVALIDVOLS:
4708 case CCISS_DEREGDISK:
4709 case CCISS_REGNEWDISK:
4710 case CCISS_REGNEWD:
4711 case CCISS_RESCANDISK:
4712 case CCISS_GETLUNINFO:
4713 return hpsa_ioctl(dev, cmd, arg);
4714
4715 case CCISS_PASSTHRU32:
4716 return hpsa_ioctl32_passthru(dev, cmd, arg);
4717 case CCISS_BIG_PASSTHRU32:
4718 return hpsa_ioctl32_big_passthru(dev, cmd, arg);
4719
4720 default:
4721 return -ENOIOCTLCMD;
4722 }
4723}
edd16368
SC		 4724#endif
4725
4726static int hpsa_getpciinfo_ioctl(struct ctlr_info *h, void __user *argp)
4727{
4728 struct hpsa_pci_info pciinfo;
4729
4730 if (!argp)
4731 return -EINVAL;
4732 pciinfo.domain = pci_domain_nr(h->pdev->bus);
4733 pciinfo.bus = h->pdev->bus->number;
4734 pciinfo.dev_fn = h->pdev->devfn;
4735 pciinfo.board_id = h->board_id;
4736 if (copy_to_user(argp, &pciinfo, sizeof(pciinfo)))
4737 return -EFAULT;
4738 return 0;
4739}
4740
4741static int hpsa_getdrivver_ioctl(struct ctlr_info *h, void __user *argp)
4742{
4743 DriverVer_type DriverVer;
4744 unsigned char vmaj, vmin, vsubmin;
4745 int rc;
4746
4747 rc = sscanf(HPSA_DRIVER_VERSION, "%hhu.%hhu.%hhu",
4748 &vmaj, &vmin, &vsubmin);
4749 if (rc != 3) {
4750 dev_info(&h->pdev->dev, "driver version string '%s' "
4751 "unrecognized.", HPSA_DRIVER_VERSION);
4752 vmaj = 0;
4753 vmin = 0;
4754 vsubmin = 0;
4755 }
4756 DriverVer = (vmaj << 16) | (vmin << 8) | vsubmin;
4757 if (!argp)
4758 return -EINVAL;
4759 if (copy_to_user(argp, &DriverVer, sizeof(DriverVer_type)))
4760 return -EFAULT;
4761 return 0;
4762}
4763
4764static int hpsa_passthru_ioctl(struct ctlr_info *h, void __user *argp)
4765{
4766 IOCTL_Command_struct iocommand;
4767 struct CommandList *c;
4768 char *buff = NULL;
50a0decf 4769 u64 temp64;
c1f63c8f 4770 int rc = 0;
edd16368
SC		 4771
4772 if (!argp)
4773 return -EINVAL;
4774 if (!capable(CAP_SYS_RAWIO))
4775 return -EPERM;
4776 if (copy_from_user(&iocommand, argp, sizeof(iocommand)))
4777 return -EFAULT;
4778 if ((iocommand.buf_size < 1) &&
4779 (iocommand.Request.Type.Direction != XFER_NONE)) {
4780 return -EINVAL;
4781 }
4782 if (iocommand.buf_size > 0) {
4783 buff = kmalloc(iocommand.buf_size, GFP_KERNEL);
4784 if (buff == NULL)
4785 return -EFAULT;
9233fb10 4786 if (iocommand.Request.Type.Direction & XFER_WRITE) {
b03a7771
SC		 4787 /* Copy the data into the buffer we created */
4788 if (copy_from_user(buff, iocommand.buf,
4789 iocommand.buf_size)) {
c1f63c8f
SC		 4790 rc = -EFAULT;
4791 goto out_kfree;
b03a7771
SC		 4792 }
4793 } else {
4794 memset(buff, 0, iocommand.buf_size);
edd16368 4795 }
b03a7771 4796 }
45fcb86e 4797 c = cmd_alloc(h);
edd16368 4798 if (c == NULL) {
c1f63c8f
SC		 4799 rc = -ENOMEM;
4800 goto out_kfree;
edd16368
SC		 4801 }
4802 /* Fill in the command type */
4803 c->cmd_type = CMD_IOCTL_PEND;
4804 /* Fill in Command Header */
4805 c->Header.ReplyQueue = 0; /* unused in simple mode */
4806 if (iocommand.buf_size > 0) { /* buffer to fill */
4807 c->Header.SGList = 1;
50a0decf 4808 c->Header.SGTotal = cpu_to_le16(1);
edd16368
SC		 4809 } else { /* no buffers to fill */
4810 c->Header.SGList = 0;
50a0decf 4811 c->Header.SGTotal = cpu_to_le16(0);
edd16368
SC		 4812 }
4813 memcpy(&c->Header.LUN, &iocommand.LUN_info, sizeof(c->Header.LUN));
4814 /* use the kernel address the cmd block for tag */
2b08b3e9 4815 c->Header.tag = cpu_to_le64(c->busaddr);
edd16368
SC		 4816
4817 /* Fill in Request block */
4818 memcpy(&c->Request, &iocommand.Request,
4819 sizeof(c->Request));
4820
4821 /* Fill in the scatter gather information */
4822 if (iocommand.buf_size > 0) {
50a0decf 4823 temp64 = pci_map_single(h->pdev, buff,
edd16368 4824 iocommand.buf_size, PCI_DMA_BIDIRECTIONAL);
50a0decf
SC		 4825 if (dma_mapping_error(&h->pdev->dev, (dma_addr_t) temp64)) {
4826 c->SG[0].Addr = cpu_to_le64(0);
4827 c->SG[0].Len = cpu_to_le32(0);
bcc48ffa
SC		 4828 rc = -ENOMEM;
4829 goto out;
4830 }
50a0decf
SC		 4831 c->SG[0].Addr = cpu_to_le64(temp64);
4832 c->SG[0].Len = cpu_to_le32(iocommand.buf_size);
4833 c->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* not chaining */
edd16368 4834 }
a0c12413 4835 hpsa_scsi_do_simple_cmd_core_if_no_lockup(h, c);
c2dd32e0
SC		 4836 if (iocommand.buf_size > 0)
4837 hpsa_pci_unmap(h->pdev, c, 1, PCI_DMA_BIDIRECTIONAL);
edd16368
SC		 4838 check_ioctl_unit_attention(h, c);
4839
4840 /* Copy the error information out */
4841 memcpy(&iocommand.error_info, c->err_info,
4842 sizeof(iocommand.error_info));
4843 if (copy_to_user(argp, &iocommand, sizeof(iocommand))) {
c1f63c8f
SC		 4844 rc = -EFAULT;
4845 goto out;
edd16368 4846 }
9233fb10 4847 if ((iocommand.Request.Type.Direction & XFER_READ) &&
b03a7771 4848 iocommand.buf_size > 0) {
edd16368
SC		 4849 /* Copy the data out of the buffer we created */
4850 if (copy_to_user(iocommand.buf, buff, iocommand.buf_size)) {
c1f63c8f
SC		 4851 rc = -EFAULT;
4852 goto out;
edd16368
SC		 4853 }
4854 }
c1f63c8f 4855out:
45fcb86e 4856 cmd_free(h, c);
c1f63c8f
SC		 4857out_kfree:
4858 kfree(buff);
4859 return rc;
edd16368
SC		 4860}
4861
4862static int hpsa_big_passthru_ioctl(struct ctlr_info *h, void __user *argp)
4863{
4864 BIG_IOCTL_Command_struct *ioc;
4865 struct CommandList *c;
4866 unsigned char **buff = NULL;
4867 int *buff_size = NULL;
50a0decf 4868 u64 temp64;
edd16368
SC		 4869 BYTE sg_used = 0;
4870 int status = 0;
01a02ffc
SC		 4871 u32 left;
4872 u32 sz;
edd16368
SC		 4873 BYTE __user *data_ptr;
4874
4875 if (!argp)
4876 return -EINVAL;
4877 if (!capable(CAP_SYS_RAWIO))
4878 return -EPERM;
4879 ioc = (BIG_IOCTL_Command_struct *)
4880 kmalloc(sizeof(*ioc), GFP_KERNEL);
4881 if (!ioc) {
4882 status = -ENOMEM;
4883 goto cleanup1;
4884 }
4885 if (copy_from_user(ioc, argp, sizeof(*ioc))) {
4886 status = -EFAULT;
4887 goto cleanup1;
4888 }
4889 if ((ioc->buf_size < 1) &&
4890 (ioc->Request.Type.Direction != XFER_NONE)) {
4891 status = -EINVAL;
4892 goto cleanup1;
4893 }
4894 /* Check kmalloc limits using all SGs */
4895 if (ioc->malloc_size > MAX_KMALLOC_SIZE) {
4896 status = -EINVAL;
4897 goto cleanup1;
4898 }
d66ae08b 4899 if (ioc->buf_size > ioc->malloc_size * SG_ENTRIES_IN_CMD) {
edd16368
SC		 4900 status = -EINVAL;
4901 goto cleanup1;
4902 }
d66ae08b 4903 buff = kzalloc(SG_ENTRIES_IN_CMD * sizeof(char *), GFP_KERNEL);
edd16368
SC		 4904 if (!buff) {
4905 status = -ENOMEM;
4906 goto cleanup1;
4907 }
d66ae08b 4908 buff_size = kmalloc(SG_ENTRIES_IN_CMD * sizeof(int), GFP_KERNEL);
edd16368
SC		 4909 if (!buff_size) {
4910 status = -ENOMEM;
4911 goto cleanup1;
4912 }
4913 left = ioc->buf_size;
4914 data_ptr = ioc->buf;
4915 while (left) {
4916 sz = (left > ioc->malloc_size) ? ioc->malloc_size : left;
4917 buff_size[sg_used] = sz;
4918 buff[sg_used] = kmalloc(sz, GFP_KERNEL);
4919 if (buff[sg_used] == NULL) {
4920 status = -ENOMEM;
4921 goto cleanup1;
4922 }
9233fb10 4923 if (ioc->Request.Type.Direction & XFER_WRITE) {
edd16368 4924 if (copy_from_user(buff[sg_used], data_ptr, sz)) {
0758f4f7 4925 status = -EFAULT;
edd16368
SC		 4926 goto cleanup1;
4927 }
4928 } else
4929 memset(buff[sg_used], 0, sz);
4930 left -= sz;
4931 data_ptr += sz;
4932 sg_used++;
4933 }
45fcb86e 4934 c = cmd_alloc(h);
edd16368
SC		 4935 if (c == NULL) {
4936 status = -ENOMEM;
4937 goto cleanup1;
4938 }
4939 c->cmd_type = CMD_IOCTL_PEND;
4940 c->Header.ReplyQueue = 0;
50a0decf
SC		 4941 c->Header.SGList = (u8) sg_used;
4942 c->Header.SGTotal = cpu_to_le16(sg_used);
edd16368 4943 memcpy(&c->Header.LUN, &ioc->LUN_info, sizeof(c->Header.LUN));
2b08b3e9 4944 c->Header.tag = cpu_to_le64(c->busaddr);
edd16368
SC		 4945 memcpy(&c->Request, &ioc->Request, sizeof(c->Request));
4946 if (ioc->buf_size > 0) {
4947 int i;
4948 for (i = 0; i < sg_used; i++) {
50a0decf 4949 temp64 = pci_map_single(h->pdev, buff[i],
edd16368 4950 buff_size[i], PCI_DMA_BIDIRECTIONAL);
50a0decf
SC		 4951 if (dma_mapping_error(&h->pdev->dev,
4952 (dma_addr_t) temp64)) {
4953 c->SG[i].Addr = cpu_to_le64(0);
4954 c->SG[i].Len = cpu_to_le32(0);
bcc48ffa
SC		 4955 hpsa_pci_unmap(h->pdev, c, i,
4956 PCI_DMA_BIDIRECTIONAL);
4957 status = -ENOMEM;
e2d4a1f6 4958 goto cleanup0;
bcc48ffa 4959 }
50a0decf
SC		 4960 c->SG[i].Addr = cpu_to_le64(temp64);
4961 c->SG[i].Len = cpu_to_le32(buff_size[i]);
4962 c->SG[i].Ext = cpu_to_le32(0);
edd16368 4963 }
50a0decf 4964 c->SG[--i].Ext = cpu_to_le32(HPSA_SG_LAST);
edd16368 4965 }
a0c12413 4966 hpsa_scsi_do_simple_cmd_core_if_no_lockup(h, c);
b03a7771
SC		 4967 if (sg_used)
4968 hpsa_pci_unmap(h->pdev, c, sg_used, PCI_DMA_BIDIRECTIONAL);
edd16368
SC		 4969 check_ioctl_unit_attention(h, c);
4970 /* Copy the error information out */
4971 memcpy(&ioc->error_info, c->err_info, sizeof(ioc->error_info));
4972 if (copy_to_user(argp, ioc, sizeof(*ioc))) {
edd16368 4973 status = -EFAULT;
e2d4a1f6 4974 goto cleanup0;
edd16368 4975 }
9233fb10 4976 if ((ioc->Request.Type.Direction & XFER_READ) && ioc->buf_size > 0) {
2b08b3e9
DB		 4977 int i;
4978
edd16368
SC		 4979 /* Copy the data out of the buffer we created */
4980 BYTE __user *ptr = ioc->buf;
4981 for (i = 0; i < sg_used; i++) {
4982 if (copy_to_user(ptr, buff[i], buff_size[i])) {
edd16368 4983 status = -EFAULT;
e2d4a1f6 4984 goto cleanup0;
edd16368
SC		 4985 }
4986 ptr += buff_size[i];
4987 }
4988 }
edd16368 4989 status = 0;
e2d4a1f6 4990cleanup0:
45fcb86e 4991 cmd_free(h, c);
edd16368
SC		 4992cleanup1:
4993 if (buff) {
2b08b3e9
DB		 4994 int i;
4995
edd16368
SC		 4996 for (i = 0; i < sg_used; i++)
4997 kfree(buff[i]);
4998 kfree(buff);
4999 }
5000 kfree(buff_size);
5001 kfree(ioc);
5002 return status;
5003}
5004
5005static void check_ioctl_unit_attention(struct ctlr_info *h,
5006 struct CommandList *c)
5007{
5008 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
5009 c->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION)
5010 (void) check_for_unit_attention(h, c);
5011}
0390f0c0
SC		 5012
5013static int increment_passthru_count(struct ctlr_info *h)
5014{
5015 unsigned long flags;
5016
5017 spin_lock_irqsave(&h->passthru_count_lock, flags);
5018 if (h->passthru_count >= HPSA_MAX_CONCURRENT_PASSTHRUS) {
5019 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
5020 return -1;
5021 }
5022 h->passthru_count++;
5023 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
5024 return 0;
5025}
5026
5027static void decrement_passthru_count(struct ctlr_info *h)
5028{
5029 unsigned long flags;
5030
5031 spin_lock_irqsave(&h->passthru_count_lock, flags);
5032 if (h->passthru_count <= 0) {
5033 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
5034 /* not expecting to get here. */
5035 dev_warn(&h->pdev->dev, "Bug detected, passthru_count seems to be incorrect.\n");
5036 return;
5037 }
5038 h->passthru_count--;
5039 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
5040}
5041
edd16368
SC		 5042/*
5043 * ioctl
5044 */
42a91641 5045static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg)
edd16368
SC		 5046{
5047 struct ctlr_info *h;
5048 void __user *argp = (void __user *)arg;
0390f0c0 5049 int rc;
edd16368
SC		 5050
5051 h = sdev_to_hba(dev);
5052
5053 switch (cmd) {
5054 case CCISS_DEREGDISK:
5055 case CCISS_REGNEWDISK:
5056 case CCISS_REGNEWD:
a08a8471 5057 hpsa_scan_start(h->scsi_host);
edd16368
SC		 5058 return 0;
5059 case CCISS_GETPCIINFO:
5060 return hpsa_getpciinfo_ioctl(h, argp);
5061 case CCISS_GETDRIVVER:
5062 return hpsa_getdrivver_ioctl(h, argp);
5063 case CCISS_PASSTHRU:
0390f0c0
SC		 5064 if (increment_passthru_count(h))
5065 return -EAGAIN;
5066 rc = hpsa_passthru_ioctl(h, argp);
5067 decrement_passthru_count(h);
5068 return rc;
edd16368 5069 case CCISS_BIG_PASSTHRU:
0390f0c0
SC		 5070 if (increment_passthru_count(h))
5071 return -EAGAIN;
5072 rc = hpsa_big_passthru_ioctl(h, argp);
5073 decrement_passthru_count(h);
5074 return rc;
edd16368
SC		 5075 default:
5076 return -ENOTTY;
5077 }
5078}
5079
6f039790
GKH		 5080static int hpsa_send_host_reset(struct ctlr_info *h, unsigned char *scsi3addr,
5081 u8 reset_type)
64670ac8
SC		 5082{
5083 struct CommandList *c;
5084
5085 c = cmd_alloc(h);
5086 if (!c)
5087 return -ENOMEM;
a2dac136
SC		 5088 /* fill_cmd can't fail here, no data buffer to map */
5089 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
64670ac8
SC		 5090 RAID_CTLR_LUNID, TYPE_MSG);
5091 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to target reset */
5092 c->waiting = NULL;
5093 enqueue_cmd_and_start_io(h, c);
5094 /* Don't wait for completion, the reset won't complete. Don't free
5095 * the command either. This is the last command we will send before
5096 * re-initializing everything, so it doesn't matter and won't leak.
5097 */
5098 return 0;
5099}
5100
a2dac136 5101static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
b7bb24eb 5102 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
edd16368
SC		 5103 int cmd_type)
5104{
5105 int pci_dir = XFER_NONE;
75167d2c 5106 struct CommandList *a; /* for commands to be aborted */
edd16368
SC		 5107
5108 c->cmd_type = CMD_IOCTL_PEND;
5109 c->Header.ReplyQueue = 0;
5110 if (buff != NULL && size > 0) {
5111 c->Header.SGList = 1;
50a0decf 5112 c->Header.SGTotal = cpu_to_le16(1);
edd16368
SC		 5113 } else {
5114 c->Header.SGList = 0;
50a0decf 5115 c->Header.SGTotal = cpu_to_le16(0);
edd16368 5116 }
2b08b3e9 5117 c->Header.tag = cpu_to_le64(c->busaddr);
edd16368
SC		 5118 memcpy(c->Header.LUN.LunAddrBytes, scsi3addr, 8);
5119
edd16368
SC		 5120 if (cmd_type == TYPE_CMD) {
5121 switch (cmd) {
5122 case HPSA_INQUIRY:
5123 /* are we trying to read a vital product page */
b7bb24eb 5124 if (page_code & VPD_PAGE) {
edd16368 5125 c->Request.CDB[1] = 0x01;
b7bb24eb 5126 c->Request.CDB[2] = (page_code & 0xff);
edd16368
SC		 5127 }
5128 c->Request.CDBLen = 6;
a505b86f
SC		 5129 c->Request.type_attr_dir =
5130 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 5131 c->Request.Timeout = 0;
5132 c->Request.CDB[0] = HPSA_INQUIRY;
5133 c->Request.CDB[4] = size & 0xFF;
5134 break;
5135 case HPSA_REPORT_LOG:
5136 case HPSA_REPORT_PHYS:
5137 /* Talking to controller so It's a physical command
5138 mode = 00 target = 0. Nothing to write.
5139 */
5140 c->Request.CDBLen = 12;
a505b86f
SC		 5141 c->Request.type_attr_dir =
5142 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 5143 c->Request.Timeout = 0;
5144 c->Request.CDB[0] = cmd;
5145 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
5146 c->Request.CDB[7] = (size >> 16) & 0xFF;
5147 c->Request.CDB[8] = (size >> 8) & 0xFF;
5148 c->Request.CDB[9] = size & 0xFF;
5149 break;
edd16368
SC		 5150 case HPSA_CACHE_FLUSH:
5151 c->Request.CDBLen = 12;
a505b86f
SC		 5152 c->Request.type_attr_dir =
5153 TYPE_ATTR_DIR(cmd_type,
5154 ATTR_SIMPLE, XFER_WRITE);
edd16368
SC		 5155 c->Request.Timeout = 0;
5156 c->Request.CDB[0] = BMIC_WRITE;
5157 c->Request.CDB[6] = BMIC_CACHE_FLUSH;
bb158eab
SC		 5158 c->Request.CDB[7] = (size >> 8) & 0xFF;
5159 c->Request.CDB[8] = size & 0xFF;
edd16368
SC		 5160 break;
5161 case TEST_UNIT_READY:
5162 c->Request.CDBLen = 6;
a505b86f
SC		 5163 c->Request.type_attr_dir =
5164 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
edd16368
SC		 5165 c->Request.Timeout = 0;
5166 break;
283b4a9b
SC		 5167 case HPSA_GET_RAID_MAP:
5168 c->Request.CDBLen = 12;
a505b86f
SC		 5169 c->Request.type_attr_dir =
5170 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
283b4a9b
SC		 5171 c->Request.Timeout = 0;
5172 c->Request.CDB[0] = HPSA_CISS_READ;
5173 c->Request.CDB[1] = cmd;
5174 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
5175 c->Request.CDB[7] = (size >> 16) & 0xFF;
5176 c->Request.CDB[8] = (size >> 8) & 0xFF;
5177 c->Request.CDB[9] = size & 0xFF;
5178 break;
316b221a
SC		 5179 case BMIC_SENSE_CONTROLLER_PARAMETERS:
5180 c->Request.CDBLen = 10;
a505b86f
SC		 5181 c->Request.type_attr_dir =
5182 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
316b221a
SC		 5183 c->Request.Timeout = 0;
5184 c->Request.CDB[0] = BMIC_READ;
5185 c->Request.CDB[6] = BMIC_SENSE_CONTROLLER_PARAMETERS;
5186 c->Request.CDB[7] = (size >> 16) & 0xFF;
5187 c->Request.CDB[8] = (size >> 8) & 0xFF;
5188 break;
edd16368
SC		 5189 default:
5190 dev_warn(&h->pdev->dev, "unknown command 0x%c\n", cmd);
5191 BUG();
a2dac136 5192 return -1;
edd16368
SC		 5193 }
5194 } else if (cmd_type == TYPE_MSG) {
5195 switch (cmd) {
5196
5197 case HPSA_DEVICE_RESET_MSG:
5198 c->Request.CDBLen = 16;
a505b86f
SC		 5199 c->Request.type_attr_dir =
5200 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
edd16368 5201 c->Request.Timeout = 0; /* Don't time out */
64670ac8
SC		 5202 memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
5203 c->Request.CDB[0] = cmd;
21e89afd 5204 c->Request.CDB[1] = HPSA_RESET_TYPE_LUN;
edd16368
SC		 5205 /* If bytes 4-7 are zero, it means reset the */
5206 /* LunID device */
5207 c->Request.CDB[4] = 0x00;
5208 c->Request.CDB[5] = 0x00;
5209 c->Request.CDB[6] = 0x00;
5210 c->Request.CDB[7] = 0x00;
75167d2c
SC		 5211 break;
5212 case HPSA_ABORT_MSG:
5213 a = buff; /* point to command to be aborted */
2b08b3e9
DB		 5214 dev_dbg(&h->pdev->dev,
5215 "Abort Tag:0x%016llx request Tag:0x%016llx",
50a0decf 5216 a->Header.tag, c->Header.tag);
75167d2c 5217 c->Request.CDBLen = 16;
a505b86f
SC		 5218 c->Request.type_attr_dir =
5219 TYPE_ATTR_DIR(cmd_type,
5220 ATTR_SIMPLE, XFER_WRITE);
75167d2c
SC		 5221 c->Request.Timeout = 0; /* Don't time out */
5222 c->Request.CDB[0] = HPSA_TASK_MANAGEMENT;
5223 c->Request.CDB[1] = HPSA_TMF_ABORT_TASK;
5224 c->Request.CDB[2] = 0x00; /* reserved */
5225 c->Request.CDB[3] = 0x00; /* reserved */
5226 /* Tag to abort goes in CDB[4]-CDB[11] */
2b08b3e9
DB		 5227 memcpy(&c->Request.CDB[4], &a->Header.tag,
5228 sizeof(a->Header.tag));
75167d2c
SC		 5229 c->Request.CDB[12] = 0x00; /* reserved */
5230 c->Request.CDB[13] = 0x00; /* reserved */
5231 c->Request.CDB[14] = 0x00; /* reserved */
5232 c->Request.CDB[15] = 0x00; /* reserved */
edd16368 5233 break;
edd16368
SC		 5234 default:
5235 dev_warn(&h->pdev->dev, "unknown message type %d\n",
5236 cmd);
5237 BUG();
5238 }
5239 } else {
5240 dev_warn(&h->pdev->dev, "unknown command type %d\n", cmd_type);
5241 BUG();
5242 }
5243
a505b86f 5244 switch (GET_DIR(c->Request.type_attr_dir)) {
edd16368
SC		 5245 case XFER_READ:
5246 pci_dir = PCI_DMA_FROMDEVICE;
5247 break;
5248 case XFER_WRITE:
5249 pci_dir = PCI_DMA_TODEVICE;
5250 break;
5251 case XFER_NONE:
5252 pci_dir = PCI_DMA_NONE;
5253 break;
5254 default:
5255 pci_dir = PCI_DMA_BIDIRECTIONAL;
5256 }
a2dac136
SC		 5257 if (hpsa_map_one(h->pdev, c, buff, size, pci_dir))
5258 return -1;
5259 return 0;
edd16368
SC		 5260}
5261
5262/*
5263 * Map (physical) PCI mem into (virtual) kernel space
5264 */
5265static void __iomem *remap_pci_mem(ulong base, ulong size)
5266{
5267 ulong page_base = ((ulong) base) & PAGE_MASK;
5268 ulong page_offs = ((ulong) base) - page_base;
088ba34c
SC		 5269 void __iomem *page_remapped = ioremap_nocache(page_base,
5270 page_offs + size);
edd16368
SC		 5271
5272 return page_remapped ? (page_remapped + page_offs) : NULL;
5273}
5274
5275/* Takes cmds off the submission queue and sends them to the hardware,
5276 * then puts them on the queue of cmds waiting for completion.
0b57075d 5277 * Assumes h->lock is held
edd16368 5278 */
0b57075d 5279static void start_io(struct ctlr_info *h, unsigned long *flags)
edd16368
SC		 5280{
5281 struct CommandList *c;
5282
9e0fc764
SC		 5283 while (!list_empty(&h->reqQ)) {
5284 c = list_entry(h->reqQ.next, struct CommandList, list);
edd16368
SC		 5285 /* can't do anything if fifo is full */
5286 if ((h->access.fifo_full(h))) {
396883e2 5287 h->fifo_recently_full = 1;
edd16368
SC		 5288 dev_warn(&h->pdev->dev, "fifo full\n");
5289 break;
5290 }
396883e2 5291 h->fifo_recently_full = 0;
edd16368
SC		 5292
5293 /* Get the first entry from the Request Q */
5294 removeQ(c);
5295 h->Qdepth--;
5296
edd16368
SC		 5297 /* Put job onto the completed Q */
5298 addQ(&h->cmpQ, c);
0cbf768e 5299 atomic_inc(&h->commands_outstanding);
0b57075d 5300 spin_unlock_irqrestore(&h->lock, *flags);
0cbf768e 5301 /* Tell the controller execute command */
e16a33ad 5302 h->access.submit_command(h, c);
0b57075d 5303 spin_lock_irqsave(&h->lock, *flags);
edd16368 5304 }
0b57075d
SC		 5305}
5306
5307static void lock_and_start_io(struct ctlr_info *h)
5308{
5309 unsigned long flags;
5310
5311 spin_lock_irqsave(&h->lock, flags);
5312 start_io(h, &flags);
e16a33ad 5313 spin_unlock_irqrestore(&h->lock, flags);
edd16368
SC		 5314}
5315
254f796b 5316static inline unsigned long get_next_completion(struct ctlr_info *h, u8 q)
edd16368 5317{
254f796b 5318 return h->access.command_completed(h, q);
edd16368
SC		 5319}
5320
900c5440 5321static inline bool interrupt_pending(struct ctlr_info *h)
edd16368
SC		 5322{
5323 return h->access.intr_pending(h);
5324}
5325
5326static inline long interrupt_not_for_us(struct ctlr_info *h)
5327{
10f66018
SC		 5328 return (h->access.intr_pending(h) == 0) ||
5329 (h->interrupts_enabled == 0);
edd16368
SC		 5330}
5331
01a02ffc
SC		 5332static inline int bad_tag(struct ctlr_info *h, u32 tag_index,
5333 u32 raw_tag)
edd16368
SC		 5334{
5335 if (unlikely(tag_index >= h->nr_cmds)) {
5336 dev_warn(&h->pdev->dev, "bad tag 0x%08x ignored.\n", raw_tag);
5337 return 1;
5338 }
5339 return 0;
5340}
5341
5a3d16f5 5342static inline void finish_cmd(struct CommandList *c)
edd16368 5343{
e16a33ad 5344 unsigned long flags;
396883e2
SC		 5345 int io_may_be_stalled = 0;
5346 struct ctlr_info *h = c->h;
0cbf768e 5347 int count;
e16a33ad 5348
396883e2 5349 spin_lock_irqsave(&h->lock, flags);
edd16368 5350 removeQ(c);
396883e2
SC		 5351
5352 /*
5353 * Check for possibly stalled i/o.
5354 *
5355 * If a fifo_full condition is encountered, requests will back up
5356 * in h->reqQ. This queue is only emptied out by start_io which is
5357 * only called when a new i/o request comes in. If no i/o's are
5358 * forthcoming, the i/o's in h->reqQ can get stuck. So we call
5359 * start_io from here if we detect such a danger.
5360 *
5361 * Normally, we shouldn't hit this case, but pounding on the
5362 * CCISS_PASSTHRU ioctl can provoke it. Only call start_io if
5363 * commands_outstanding is low. We want to avoid calling
5364 * start_io from in here as much as possible, and esp. don't
5365 * want to get in a cycle where we call start_io every time
5366 * through here.
5367 */
0cbf768e 5368 count = atomic_read(&h->commands_outstanding);
396883e2 5369 spin_unlock_irqrestore(&h->lock, flags);
0cbf768e
SC		 5370 if (unlikely(h->fifo_recently_full) && count < 5)
5371 io_may_be_stalled = 1;
396883e2 5372
e85c5974 5373 dial_up_lockup_detection_on_fw_flash_complete(c->h, c);
c349775e
ST		 5374 if (likely(c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_SCSI
5375 || c->cmd_type == CMD_IOACCEL2))
1fb011fb 5376 complete_scsi_command(c);
edd16368
SC		 5377 else if (c->cmd_type == CMD_IOCTL_PEND)
5378 complete(c->waiting);
396883e2 5379 if (unlikely(io_may_be_stalled))
0b57075d 5380 lock_and_start_io(h);
edd16368
SC		 5381}
5382
a104c99f
SC		 5383static inline u32 hpsa_tag_contains_index(u32 tag)
5384{
a104c99f
SC		 5385 return tag & DIRECT_LOOKUP_BIT;
5386}
5387
5388static inline u32 hpsa_tag_to_index(u32 tag)
5389{
a104c99f
SC		 5390 return tag >> DIRECT_LOOKUP_SHIFT;
5391}
5392
a9a3a273
SC		 5393
5394static inline u32 hpsa_tag_discard_error_bits(struct ctlr_info *h, u32 tag)
a104c99f 5395{
a9a3a273
SC		 5396#define HPSA_PERF_ERROR_BITS ((1 << DIRECT_LOOKUP_SHIFT) - 1)
5397#define HPSA_SIMPLE_ERROR_BITS 0x03
960a30e7 5398 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
a9a3a273
SC		 5399 return tag & ~HPSA_SIMPLE_ERROR_BITS;
5400 return tag & ~HPSA_PERF_ERROR_BITS;
a104c99f
SC		 5401}
5402
303932fd 5403/* process completion of an indexed ("direct lookup") command */
1d94f94d 5404static inline void process_indexed_cmd(struct ctlr_info *h,
303932fd
DB		 5405 u32 raw_tag)
5406{
5407 u32 tag_index;
5408 struct CommandList *c;
5409
5410 tag_index = hpsa_tag_to_index(raw_tag);
1d94f94d
SC		 5411 if (!bad_tag(h, tag_index, raw_tag)) {
5412 c = h->cmd_pool + tag_index;
5413 finish_cmd(c);
5414 }
303932fd
DB		 5415}
5416
5417/* process completion of a non-indexed command */
1d94f94d 5418static inline void process_nonindexed_cmd(struct ctlr_info *h,
303932fd
DB		 5419 u32 raw_tag)
5420{
5421 u32 tag;
5422 struct CommandList *c = NULL;
e16a33ad 5423 unsigned long flags;
303932fd 5424
a9a3a273 5425 tag = hpsa_tag_discard_error_bits(h, raw_tag);
e16a33ad 5426 spin_lock_irqsave(&h->lock, flags);
9e0fc764 5427 list_for_each_entry(c, &h->cmpQ, list) {
303932fd 5428 if ((c->busaddr & 0xFFFFFFE0) == (tag & 0xFFFFFFE0)) {
e16a33ad 5429 spin_unlock_irqrestore(&h->lock, flags);
5a3d16f5 5430 finish_cmd(c);
1d94f94d 5431 return;
303932fd
DB		 5432 }
5433 }
e16a33ad 5434 spin_unlock_irqrestore(&h->lock, flags);
303932fd 5435 bad_tag(h, h->nr_cmds + 1, raw_tag);
303932fd
DB		 5436}
5437
64670ac8
SC		 5438/* Some controllers, like p400, will give us one interrupt
5439 * after a soft reset, even if we turned interrupts off.
5440 * Only need to check for this in the hpsa_xxx_discard_completions
5441 * functions.
5442 */
5443static int ignore_bogus_interrupt(struct ctlr_info *h)
5444{
5445 if (likely(!reset_devices))
5446 return 0;
5447
5448 if (likely(h->interrupts_enabled))
5449 return 0;
5450
5451 dev_info(&h->pdev->dev, "Received interrupt while interrupts disabled "
5452 "(known firmware bug.) Ignoring.\n");
5453
5454 return 1;
5455}
5456
254f796b
MG		 5457/*
5458 * Convert &h->q[x] (passed to interrupt handlers) back to h.
5459 * Relies on (h-q[x] == x) being true for x such that
5460 * 0 <= x < MAX_REPLY_QUEUES.
5461 */
5462static struct ctlr_info *queue_to_hba(u8 *queue)
64670ac8 5463{
254f796b
MG		 5464 return container_of((queue - *queue), struct ctlr_info, q[0]);
5465}
5466
5467static irqreturn_t hpsa_intx_discard_completions(int irq, void *queue)
5468{
5469 struct ctlr_info *h = queue_to_hba(queue);
5470 u8 q = *(u8 *) queue;
64670ac8
SC		 5471 u32 raw_tag;
5472
5473 if (ignore_bogus_interrupt(h))
5474 return IRQ_NONE;
5475
5476 if (interrupt_not_for_us(h))
5477 return IRQ_NONE;
a0c12413 5478 h->last_intr_timestamp = get_jiffies_64();
64670ac8 5479 while (interrupt_pending(h)) {
254f796b 5480 raw_tag = get_next_completion(h, q);
64670ac8 5481 while (raw_tag != FIFO_EMPTY)
254f796b 5482 raw_tag = next_command(h, q);
64670ac8 5483 }
64670ac8
SC		 5484 return IRQ_HANDLED;
5485}
5486
254f796b 5487static irqreturn_t hpsa_msix_discard_completions(int irq, void *queue)
64670ac8 5488{
254f796b 5489 struct ctlr_info *h = queue_to_hba(queue);
64670ac8 5490 u32 raw_tag;
254f796b 5491 u8 q = *(u8 *) queue;
64670ac8
SC		 5492
5493 if (ignore_bogus_interrupt(h))
5494 return IRQ_NONE;
5495
a0c12413 5496 h->last_intr_timestamp = get_jiffies_64();
254f796b 5497 raw_tag = get_next_completion(h, q);
64670ac8 5498 while (raw_tag != FIFO_EMPTY)
254f796b 5499 raw_tag = next_command(h, q);
64670ac8
SC		 5500 return IRQ_HANDLED;
5501}
5502
254f796b 5503static irqreturn_t do_hpsa_intr_intx(int irq, void *queue)
edd16368 5504{
254f796b 5505 struct ctlr_info *h = queue_to_hba((u8 *) queue);
303932fd 5506 u32 raw_tag;
254f796b 5507 u8 q = *(u8 *) queue;
edd16368
SC		 5508
5509 if (interrupt_not_for_us(h))
5510 return IRQ_NONE;
a0c12413 5511 h->last_intr_timestamp = get_jiffies_64();
10f66018 5512 while (interrupt_pending(h)) {
254f796b 5513 raw_tag = get_next_completion(h, q);
10f66018 5514 while (raw_tag != FIFO_EMPTY) {
1d94f94d
SC		 5515 if (likely(hpsa_tag_contains_index(raw_tag)))
5516 process_indexed_cmd(h, raw_tag);
10f66018 5517 else
1d94f94d 5518 process_nonindexed_cmd(h, raw_tag);
254f796b 5519 raw_tag = next_command(h, q);
10f66018
SC		 5520 }
5521 }
10f66018
SC		 5522 return IRQ_HANDLED;
5523}
5524
254f796b 5525static irqreturn_t do_hpsa_intr_msi(int irq, void *queue)
10f66018 5526{
254f796b 5527 struct ctlr_info *h = queue_to_hba(queue);
10f66018 5528 u32 raw_tag;
254f796b 5529 u8 q = *(u8 *) queue;
10f66018 5530
a0c12413 5531 h->last_intr_timestamp = get_jiffies_64();
254f796b 5532 raw_tag = get_next_completion(h, q);
303932fd 5533 while (raw_tag != FIFO_EMPTY) {
1d94f94d
SC		 5534 if (likely(hpsa_tag_contains_index(raw_tag)))
5535 process_indexed_cmd(h, raw_tag);
303932fd 5536 else
1d94f94d 5537 process_nonindexed_cmd(h, raw_tag);
254f796b 5538 raw_tag = next_command(h, q);
edd16368 5539 }
edd16368
SC		 5540 return IRQ_HANDLED;
5541}
5542
a9a3a273
SC		 5543/* Send a message CDB to the firmware. Careful, this only works
5544 * in simple mode, not performant mode due to the tag lookup.
5545 * We only ever use this immediately after a controller reset.
5546 */
6f039790
GKH		 5547static int hpsa_message(struct pci_dev *pdev, unsigned char opcode,
5548 unsigned char type)
edd16368
SC		 5549{
5550 struct Command {
5551 struct CommandListHeader CommandHeader;
5552 struct RequestBlock Request;
5553 struct ErrDescriptor ErrorDescriptor;
5554 };
5555 struct Command *cmd;
5556 static const size_t cmd_sz = sizeof(*cmd) +
5557 sizeof(cmd->ErrorDescriptor);
5558 dma_addr_t paddr64;
2b08b3e9
DB		 5559 __le32 paddr32;
5560 u32 tag;
edd16368
SC		 5561 void __iomem *vaddr;
5562 int i, err;
5563
5564 vaddr = pci_ioremap_bar(pdev, 0);
5565 if (vaddr == NULL)
5566 return -ENOMEM;
5567
5568 /* The Inbound Post Queue only accepts 32-bit physical addresses for the
5569 * CCISS commands, so they must be allocated from the lower 4GiB of
5570 * memory.
5571 */
5572 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
5573 if (err) {
5574 iounmap(vaddr);
1eaec8f3 5575 return err;
edd16368
SC		 5576 }
5577
5578 cmd = pci_alloc_consistent(pdev, cmd_sz, &paddr64);
5579 if (cmd == NULL) {
5580 iounmap(vaddr);
5581 return -ENOMEM;
5582 }
5583
5584 /* This must fit, because of the 32-bit consistent DMA mask. Also,
5585 * although there's no guarantee, we assume that the address is at
5586 * least 4-byte aligned (most likely, it's page-aligned).
5587 */
2b08b3e9 5588 paddr32 = cpu_to_le32(paddr64);
edd16368
SC		 5589
5590 cmd->CommandHeader.ReplyQueue = 0;
5591 cmd->CommandHeader.SGList = 0;
50a0decf 5592 cmd->CommandHeader.SGTotal = cpu_to_le16(0);
2b08b3e9 5593 cmd->CommandHeader.tag = cpu_to_le64(paddr64);
edd16368
SC		 5594 memset(&cmd->CommandHeader.LUN.LunAddrBytes, 0, 8);
5595
5596 cmd->Request.CDBLen = 16;
a505b86f
SC		 5597 cmd->Request.type_attr_dir =
5598 TYPE_ATTR_DIR(TYPE_MSG, ATTR_HEADOFQUEUE, XFER_NONE);
edd16368
SC		 5599 cmd->Request.Timeout = 0; /* Don't time out */
5600 cmd->Request.CDB[0] = opcode;
5601 cmd->Request.CDB[1] = type;
5602 memset(&cmd->Request.CDB[2], 0, 14); /* rest of the CDB is reserved */
50a0decf 5603 cmd->ErrorDescriptor.Addr =
2b08b3e9 5604 cpu_to_le64((le32_to_cpu(paddr32) + sizeof(*cmd)));
50a0decf 5605 cmd->ErrorDescriptor.Len = cpu_to_le32(sizeof(struct ErrorInfo));
edd16368 5606
2b08b3e9 5607 writel(le32_to_cpu(paddr32), vaddr + SA5_REQUEST_PORT_OFFSET);
edd16368
SC		 5608
5609 for (i = 0; i < HPSA_MSG_SEND_RETRY_LIMIT; i++) {
5610 tag = readl(vaddr + SA5_REPLY_PORT_OFFSET);
2b08b3e9 5611 if ((tag & ~HPSA_SIMPLE_ERROR_BITS) == paddr64)
edd16368
SC		 5612 break;
5613 msleep(HPSA_MSG_SEND_RETRY_INTERVAL_MSECS);
5614 }
5615
5616 iounmap(vaddr);
5617
5618 /* we leak the DMA buffer here ... no choice since the controller could
5619 * still complete the command.
5620 */
5621 if (i == HPSA_MSG_SEND_RETRY_LIMIT) {
5622 dev_err(&pdev->dev, "controller message %02x:%02x timed out\n",
5623 opcode, type);
5624 return -ETIMEDOUT;
5625 }
5626
5627 pci_free_consistent(pdev, cmd_sz, cmd, paddr64);
5628
5629 if (tag & HPSA_ERROR_BIT) {
5630 dev_err(&pdev->dev, "controller message %02x:%02x failed\n",
5631 opcode, type);
5632 return -EIO;
5633 }
5634
5635 dev_info(&pdev->dev, "controller message %02x:%02x succeeded\n",
5636 opcode, type);
5637 return 0;
5638}
5639
edd16368
SC		 5640#define hpsa_noop(p) hpsa_message(p, 3, 0)
5641
1df8552a 5642static int hpsa_controller_hard_reset(struct pci_dev *pdev,
42a91641 5643 void __iomem *vaddr, u32 use_doorbell)
1df8552a 5644{
1df8552a
SC		 5645
5646 if (use_doorbell) {
5647 /* For everything after the P600, the PCI power state method
5648 * of resetting the controller doesn't work, so we have this
5649 * other way using the doorbell register.
5650 */
5651 dev_info(&pdev->dev, "using doorbell to reset controller\n");
cf0b08d0 5652 writel(use_doorbell, vaddr + SA5_DOORBELL);
85009239 5653
00701a96 5654 /* PMC hardware guys tell us we need a 10 second delay after
85009239
SC		 5655 * doorbell reset and before any attempt to talk to the board
5656 * at all to ensure that this actually works and doesn't fall
5657 * over in some weird corner cases.
5658 */
00701a96 5659 msleep(10000);
1df8552a
SC		 5660 } else { /* Try to do it the PCI power state way */
5661
5662 /* Quoting from the Open CISS Specification: "The Power
5663 * Management Control/Status Register (CSR) controls the power
5664 * state of the device. The normal operating state is D0,
5665 * CSR=00h. The software off state is D3, CSR=03h. To reset
5666 * the controller, place the interface device in D3 then to D0,
5667 * this causes a secondary PCI reset which will reset the
5668 * controller." */
2662cab8
DB		 5669
5670 int rc = 0;
5671
1df8552a 5672 dev_info(&pdev->dev, "using PCI PM to reset controller\n");
2662cab8 5673
1df8552a 5674 /* enter the D3hot power management state */
2662cab8
DB		 5675 rc = pci_set_power_state(pdev, PCI_D3hot);
5676 if (rc)
5677 return rc;
1df8552a
SC		 5678
5679 msleep(500);
5680
5681 /* enter the D0 power management state */
2662cab8
DB		 5682 rc = pci_set_power_state(pdev, PCI_D0);
5683 if (rc)
5684 return rc;
c4853efe
MM		 5685
5686 /*
5687 * The P600 requires a small delay when changing states.
5688 * Otherwise we may think the board did not reset and we bail.
5689 * This for kdump only and is particular to the P600.
5690 */
5691 msleep(500);
1df8552a
SC		 5692 }
5693 return 0;
5694}
5695
6f039790 5696static void init_driver_version(char *driver_version, int len)
580ada3c
SC		 5697{
5698 memset(driver_version, 0, len);
f79cfec6 5699 strncpy(driver_version, HPSA " " HPSA_DRIVER_VERSION, len - 1);
580ada3c
SC		 5700}
5701
6f039790 5702static int write_driver_ver_to_cfgtable(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 5703{
5704 char *driver_version;
5705 int i, size = sizeof(cfgtable->driver_version);
5706
5707 driver_version = kmalloc(size, GFP_KERNEL);
5708 if (!driver_version)
5709 return -ENOMEM;
5710
5711 init_driver_version(driver_version, size);
5712 for (i = 0; i < size; i++)
5713 writeb(driver_version[i], &cfgtable->driver_version[i]);
5714 kfree(driver_version);
5715 return 0;
5716}
5717
6f039790
GKH		 5718static void read_driver_ver_from_cfgtable(struct CfgTable __iomem *cfgtable,
5719 unsigned char *driver_ver)
580ada3c
SC		 5720{
5721 int i;
5722
5723 for (i = 0; i < sizeof(cfgtable->driver_version); i++)
5724 driver_ver[i] = readb(&cfgtable->driver_version[i]);
5725}
5726
6f039790 5727static int controller_reset_failed(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 5728{
5729
5730 char *driver_ver, *old_driver_ver;
5731 int rc, size = sizeof(cfgtable->driver_version);
5732
5733 old_driver_ver = kmalloc(2 * size, GFP_KERNEL);
5734 if (!old_driver_ver)
5735 return -ENOMEM;
5736 driver_ver = old_driver_ver + size;
5737
5738 /* After a reset, the 32 bytes of "driver version" in the cfgtable
5739 * should have been changed, otherwise we know the reset failed.
5740 */
5741 init_driver_version(old_driver_ver, size);
5742 read_driver_ver_from_cfgtable(cfgtable, driver_ver);
5743 rc = !memcmp(driver_ver, old_driver_ver, size);
5744 kfree(old_driver_ver);
5745 return rc;
5746}
edd16368 5747/* This does a hard reset of the controller using PCI power management
1df8552a 5748 * states or the using the doorbell register.
edd16368 5749 */
6f039790 5750static int hpsa_kdump_hard_reset_controller(struct pci_dev *pdev)
edd16368 5751{
1df8552a
SC		 5752 u64 cfg_offset;
5753 u32 cfg_base_addr;
5754 u64 cfg_base_addr_index;
5755 void __iomem *vaddr;
5756 unsigned long paddr;
580ada3c 5757 u32 misc_fw_support;
270d05de 5758 int rc;
1df8552a 5759 struct CfgTable __iomem *cfgtable;
cf0b08d0 5760 u32 use_doorbell;
18867659 5761 u32 board_id;
270d05de 5762 u16 command_register;
edd16368 5763
1df8552a
SC		 5764 /* For controllers as old as the P600, this is very nearly
5765 * the same thing as
edd16368
SC		 5766 *
5767 * pci_save_state(pci_dev);
5768 * pci_set_power_state(pci_dev, PCI_D3hot);
5769 * pci_set_power_state(pci_dev, PCI_D0);
5770 * pci_restore_state(pci_dev);
5771 *
1df8552a
SC		 5772 * For controllers newer than the P600, the pci power state
5773 * method of resetting doesn't work so we have another way
5774 * using the doorbell register.
edd16368 5775 */
18867659 5776
25c1e56a 5777 rc = hpsa_lookup_board_id(pdev, &board_id);
60f923b9
RE		 5778 if (rc < 0) {
5779 dev_warn(&pdev->dev, "Board ID not found\n");
5780 return rc;
5781 }
5782 if (!ctlr_is_resettable(board_id)) {
5783 dev_warn(&pdev->dev, "Controller not resettable\n");
25c1e56a
SC		 5784 return -ENODEV;
5785 }
46380786
SC		 5786
5787 /* if controller is soft- but not hard resettable... */
5788 if (!ctlr_is_hard_resettable(board_id))
5789 return -ENOTSUPP; /* try soft reset later. */
18867659 5790
270d05de
SC		 5791 /* Save the PCI command register */
5792 pci_read_config_word(pdev, 4, &command_register);
270d05de 5793 pci_save_state(pdev);
edd16368 5794
1df8552a
SC		 5795 /* find the first memory BAR, so we can find the cfg table */
5796 rc = hpsa_pci_find_memory_BAR(pdev, &paddr);
5797 if (rc)
5798 return rc;
5799 vaddr = remap_pci_mem(paddr, 0x250);
5800 if (!vaddr)
5801 return -ENOMEM;
edd16368 5802
1df8552a
SC		 5803 /* find cfgtable in order to check if reset via doorbell is supported */
5804 rc = hpsa_find_cfg_addrs(pdev, vaddr, &cfg_base_addr,
5805 &cfg_base_addr_index, &cfg_offset);
5806 if (rc)
5807 goto unmap_vaddr;
5808 cfgtable = remap_pci_mem(pci_resource_start(pdev,
5809 cfg_base_addr_index) + cfg_offset, sizeof(*cfgtable));
5810 if (!cfgtable) {
5811 rc = -ENOMEM;
5812 goto unmap_vaddr;
5813 }
580ada3c
SC		 5814 rc = write_driver_ver_to_cfgtable(cfgtable);
5815 if (rc)
03741d95 5816 goto unmap_cfgtable;
edd16368 5817
cf0b08d0
SC		 5818 /* If reset via doorbell register is supported, use that.
5819 * There are two such methods. Favor the newest method.
5820 */
1df8552a 5821 misc_fw_support = readl(&cfgtable->misc_fw_support);
cf0b08d0
SC		 5822 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET2;
5823 if (use_doorbell) {
5824 use_doorbell = DOORBELL_CTLR_RESET2;
5825 } else {
5826 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET;
5827 if (use_doorbell) {
050f7147
SC		 5828 dev_warn(&pdev->dev,
5829 "Soft reset not supported. Firmware update is required.\n");
64670ac8 5830 rc = -ENOTSUPP; /* try soft reset */
cf0b08d0
SC		 5831 goto unmap_cfgtable;
5832 }
5833 }
edd16368 5834
1df8552a
SC		 5835 rc = hpsa_controller_hard_reset(pdev, vaddr, use_doorbell);
5836 if (rc)
5837 goto unmap_cfgtable;
edd16368 5838
270d05de 5839 pci_restore_state(pdev);
270d05de 5840 pci_write_config_word(pdev, 4, command_register);
edd16368 5841
1df8552a
SC		 5842 /* Some devices (notably the HP Smart Array 5i Controller)
5843 need a little pause here */
5844 msleep(HPSA_POST_RESET_PAUSE_MSECS);
5845
fe5389c8
SC		 5846 rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_READY);
5847 if (rc) {
5848 dev_warn(&pdev->dev,
050f7147 5849 "Failed waiting for board to become ready after hard reset\n");
fe5389c8
SC		 5850 goto unmap_cfgtable;
5851 }
fe5389c8 5852
580ada3c
SC		 5853 rc = controller_reset_failed(vaddr);
5854 if (rc < 0)
5855 goto unmap_cfgtable;
5856 if (rc) {
64670ac8
SC		 5857 dev_warn(&pdev->dev, "Unable to successfully reset "
5858 "controller. Will try soft reset.\n");
5859 rc = -ENOTSUPP;
580ada3c 5860 } else {
64670ac8 5861 dev_info(&pdev->dev, "board ready after hard reset.\n");
1df8552a
SC		 5862 }
5863
5864unmap_cfgtable:
5865 iounmap(cfgtable);
5866
5867unmap_vaddr:
5868 iounmap(vaddr);
5869 return rc;
edd16368
SC		 5870}
5871
5872/*
5873 * We cannot read the structure directly, for portability we must use
5874 * the io functions.
5875 * This is for debug only.
5876 */
42a91641 5877static void print_cfg_table(struct device *dev, struct CfgTable __iomem *tb)
edd16368 5878{
58f8665c 5879#ifdef HPSA_DEBUG
edd16368
SC		 5880 int i;
5881 char temp_name[17];
5882
5883 dev_info(dev, "Controller Configuration information\n");
5884 dev_info(dev, "------------------------------------\n");
5885 for (i = 0; i < 4; i++)
5886 temp_name[i] = readb(&(tb->Signature[i]));
5887 temp_name[4] = '\0';
5888 dev_info(dev, " Signature = %s\n", temp_name);
5889 dev_info(dev, " Spec Number = %d\n", readl(&(tb->SpecValence)));
5890 dev_info(dev, " Transport methods supported = 0x%x\n",
5891 readl(&(tb->TransportSupport)));
5892 dev_info(dev, " Transport methods active = 0x%x\n",
5893 readl(&(tb->TransportActive)));
5894 dev_info(dev, " Requested transport Method = 0x%x\n",
5895 readl(&(tb->HostWrite.TransportRequest)));
5896 dev_info(dev, " Coalesce Interrupt Delay = 0x%x\n",
5897 readl(&(tb->HostWrite.CoalIntDelay)));
5898 dev_info(dev, " Coalesce Interrupt Count = 0x%x\n",
5899 readl(&(tb->HostWrite.CoalIntCount)));
69d6e33d 5900 dev_info(dev, " Max outstanding commands = %d\n",
edd16368
SC		 5901 readl(&(tb->CmdsOutMax)));
5902 dev_info(dev, " Bus Types = 0x%x\n", readl(&(tb->BusTypes)));
5903 for (i = 0; i < 16; i++)
5904 temp_name[i] = readb(&(tb->ServerName[i]));
5905 temp_name[16] = '\0';
5906 dev_info(dev, " Server Name = %s\n", temp_name);
5907 dev_info(dev, " Heartbeat Counter = 0x%x\n\n\n",
5908 readl(&(tb->HeartBeat)));
edd16368 5909#endif /* HPSA_DEBUG */
58f8665c 5910}
edd16368
SC		 5911
5912static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr)
5913{
5914 int i, offset, mem_type, bar_type;
5915
5916 if (pci_bar_addr == PCI_BASE_ADDRESS_0) /* looking for BAR zero? */
5917 return 0;
5918 offset = 0;
5919 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
5920 bar_type = pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE;
5921 if (bar_type == PCI_BASE_ADDRESS_SPACE_IO)
5922 offset += 4;
5923 else {
5924 mem_type = pci_resource_flags(pdev, i) &
5925 PCI_BASE_ADDRESS_MEM_TYPE_MASK;
5926 switch (mem_type) {
5927 case PCI_BASE_ADDRESS_MEM_TYPE_32:
5928 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
5929 offset += 4; /* 32 bit */
5930 break;
5931 case PCI_BASE_ADDRESS_MEM_TYPE_64:
5932 offset += 8;
5933 break;
5934 default: /* reserved in PCI 2.2 */
5935 dev_warn(&pdev->dev,
5936 "base address is invalid\n");
5937 return -1;
5938 break;
5939 }
5940 }
5941 if (offset == pci_bar_addr - PCI_BASE_ADDRESS_0)
5942 return i + 1;
5943 }
5944 return -1;
5945}
5946
5947/* If MSI/MSI-X is supported by the kernel we will try to enable it on
050f7147 5948 * controllers that are capable. If not, we use legacy INTx mode.
edd16368
SC		 5949 */
5950
6f039790 5951static void hpsa_interrupt_mode(struct ctlr_info *h)
edd16368
SC		 5952{
5953#ifdef CONFIG_PCI_MSI
254f796b
MG		 5954 int err, i;
5955 struct msix_entry hpsa_msix_entries[MAX_REPLY_QUEUES];
5956
5957 for (i = 0; i < MAX_REPLY_QUEUES; i++) {
5958 hpsa_msix_entries[i].vector = 0;
5959 hpsa_msix_entries[i].entry = i;
5960 }
edd16368
SC		 5961
5962 /* Some boards advertise MSI but don't really support it */
6b3f4c52
SC		 5963 if ((h->board_id == 0x40700E11) || (h->board_id == 0x40800E11) ||
5964 (h->board_id == 0x40820E11) || (h->board_id == 0x40830E11))
edd16368 5965 goto default_int_mode;
55c06c71 5966 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSIX)) {
050f7147 5967 dev_info(&h->pdev->dev, "MSI-X capable controller\n");
eee0f03a 5968 h->msix_vector = MAX_REPLY_QUEUES;
f89439bc
SC		 5969 if (h->msix_vector > num_online_cpus())
5970 h->msix_vector = num_online_cpus();
18fce3c4
AG		 5971 err = pci_enable_msix_range(h->pdev, hpsa_msix_entries,
5972 1, h->msix_vector);
5973 if (err < 0) {
5974 dev_warn(&h->pdev->dev, "MSI-X init failed %d\n", err);
5975 h->msix_vector = 0;
5976 goto single_msi_mode;
5977 } else if (err < h->msix_vector) {
55c06c71 5978 dev_warn(&h->pdev->dev, "only %d MSI-X vectors "
edd16368 5979 "available\n", err);
edd16368 5980 }
18fce3c4
AG		 5981 h->msix_vector = err;
5982 for (i = 0; i < h->msix_vector; i++)
5983 h->intr[i] = hpsa_msix_entries[i].vector;
5984 return;
edd16368 5985 }
18fce3c4 5986single_msi_mode:
55c06c71 5987 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSI)) {
050f7147 5988 dev_info(&h->pdev->dev, "MSI capable controller\n");
55c06c71 5989 if (!pci_enable_msi(h->pdev))
edd16368
SC		 5990 h->msi_vector = 1;
5991 else
55c06c71 5992 dev_warn(&h->pdev->dev, "MSI init failed\n");
edd16368
SC		 5993 }
5994default_int_mode:
5995#endif /* CONFIG_PCI_MSI */
5996 /* if we get here we're going to use the default interrupt mode */
a9a3a273 5997 h->intr[h->intr_mode] = h->pdev->irq;
edd16368
SC		 5998}
5999
6f039790 6000static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id)
e5c880d1
SC		 6001{
6002 int i;
6003 u32 subsystem_vendor_id, subsystem_device_id;
6004
6005 subsystem_vendor_id = pdev->subsystem_vendor;
6006 subsystem_device_id = pdev->subsystem_device;
6007 *board_id = ((subsystem_device_id << 16) & 0xffff0000) |
6008 subsystem_vendor_id;
6009
6010 for (i = 0; i < ARRAY_SIZE(products); i++)
6011 if (*board_id == products[i].board_id)
6012 return i;
6013
6798cc0a
SC		 6014 if ((subsystem_vendor_id != PCI_VENDOR_ID_HP &&
6015 subsystem_vendor_id != PCI_VENDOR_ID_COMPAQ) ||
6016 !hpsa_allow_any) {
e5c880d1
SC		 6017 dev_warn(&pdev->dev, "unrecognized board ID: "
6018 "0x%08x, ignoring.\n", *board_id);
6019 return -ENODEV;
6020 }
6021 return ARRAY_SIZE(products) - 1; /* generic unknown smart array */
6022}
6023
6f039790
GKH		 6024static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
6025 unsigned long *memory_bar)
3a7774ce
SC		 6026{
6027 int i;
6028
6029 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
12d2cd47 6030 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
3a7774ce 6031 /* addressing mode bits already removed */
12d2cd47
SC		 6032 *memory_bar = pci_resource_start(pdev, i);
6033 dev_dbg(&pdev->dev, "memory BAR = %lx\n",
3a7774ce
SC		 6034 *memory_bar);
6035 return 0;
6036 }
12d2cd47 6037 dev_warn(&pdev->dev, "no memory BAR found\n");
3a7774ce
SC		 6038 return -ENODEV;
6039}
6040
6f039790
GKH		 6041static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
6042 int wait_for_ready)
2c4c8c8b 6043{
fe5389c8 6044 int i, iterations;
2c4c8c8b 6045 u32 scratchpad;
fe5389c8
SC		 6046 if (wait_for_ready)
6047 iterations = HPSA_BOARD_READY_ITERATIONS;
6048 else
6049 iterations = HPSA_BOARD_NOT_READY_ITERATIONS;
2c4c8c8b 6050
fe5389c8
SC		 6051 for (i = 0; i < iterations; i++) {
6052 scratchpad = readl(vaddr + SA5_SCRATCHPAD_OFFSET);
6053 if (wait_for_ready) {
6054 if (scratchpad == HPSA_FIRMWARE_READY)
6055 return 0;
6056 } else {
6057 if (scratchpad != HPSA_FIRMWARE_READY)
6058 return 0;
6059 }
2c4c8c8b
SC		 6060 msleep(HPSA_BOARD_READY_POLL_INTERVAL_MSECS);
6061 }
fe5389c8 6062 dev_warn(&pdev->dev, "board not ready, timed out.\n");
2c4c8c8b
SC		 6063 return -ENODEV;
6064}
6065
6f039790
GKH		 6066static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
6067 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
6068 u64 *cfg_offset)
a51fd47f
SC		 6069{
6070 *cfg_base_addr = readl(vaddr + SA5_CTCFG_OFFSET);
6071 *cfg_offset = readl(vaddr + SA5_CTMEM_OFFSET);
6072 *cfg_base_addr &= (u32) 0x0000ffff;
6073 *cfg_base_addr_index = find_PCI_BAR_index(pdev, *cfg_base_addr);
6074 if (*cfg_base_addr_index == -1) {
6075 dev_warn(&pdev->dev, "cannot find cfg_base_addr_index\n");
6076 return -ENODEV;
6077 }
6078 return 0;
6079}
6080
6f039790 6081static int hpsa_find_cfgtables(struct ctlr_info *h)
edd16368 6082{
01a02ffc
SC		 6083 u64 cfg_offset;
6084 u32 cfg_base_addr;
6085 u64 cfg_base_addr_index;
303932fd 6086 u32 trans_offset;
a51fd47f 6087 int rc;
77c4495c 6088
a51fd47f
SC		 6089 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
6090 &cfg_base_addr_index, &cfg_offset);
6091 if (rc)
6092 return rc;
77c4495c 6093 h->cfgtable = remap_pci_mem(pci_resource_start(h->pdev,
a51fd47f 6094 cfg_base_addr_index) + cfg_offset, sizeof(*h->cfgtable));
cd3c81c4
RE		 6095 if (!h->cfgtable) {
6096 dev_err(&h->pdev->dev, "Failed mapping cfgtable\n");
77c4495c 6097 return -ENOMEM;
cd3c81c4 6098 }
580ada3c
SC		 6099 rc = write_driver_ver_to_cfgtable(h->cfgtable);
6100 if (rc)
6101 return rc;
77c4495c 6102 /* Find performant mode table. */
a51fd47f 6103 trans_offset = readl(&h->cfgtable->TransMethodOffset);
77c4495c
SC		 6104 h->transtable = remap_pci_mem(pci_resource_start(h->pdev,
6105 cfg_base_addr_index)+cfg_offset+trans_offset,
6106 sizeof(*h->transtable));
6107 if (!h->transtable)
6108 return -ENOMEM;
6109 return 0;
6110}
6111
6f039790 6112static void hpsa_get_max_perf_mode_cmds(struct ctlr_info *h)
cba3d38b
SC		 6113{
6114 h->max_commands = readl(&(h->cfgtable->MaxPerformantModeCommands));
72ceeaec
SC		 6115
6116 /* Limit commands in memory limited kdump scenario. */
6117 if (reset_devices && h->max_commands > 32)
6118 h->max_commands = 32;
6119
cba3d38b
SC		 6120 if (h->max_commands < 16) {
6121 dev_warn(&h->pdev->dev, "Controller reports "
6122 "max supported commands of %d, an obvious lie. "
6123 "Using 16. Ensure that firmware is up to date.\n",
6124 h->max_commands);
6125 h->max_commands = 16;
6126 }
6127}
6128
c7ee65b3
WS		 6129/* If the controller reports that the total max sg entries is greater than 512,
6130 * then we know that chained SG blocks work. (Original smart arrays did not
6131 * support chained SG blocks and would return zero for max sg entries.)
6132 */
6133static int hpsa_supports_chained_sg_blocks(struct ctlr_info *h)
6134{
6135 return h->maxsgentries > 512;
6136}
6137
b93d7536
SC		 6138/* Interrogate the hardware for some limits:
6139 * max commands, max SG elements without chaining, and with chaining,
6140 * SG chain block size, etc.
6141 */
6f039790 6142static void hpsa_find_board_params(struct ctlr_info *h)
b93d7536 6143{
cba3d38b 6144 hpsa_get_max_perf_mode_cmds(h);
45fcb86e 6145 h->nr_cmds = h->max_commands;
b93d7536 6146 h->maxsgentries = readl(&(h->cfgtable->MaxScatterGatherElements));
283b4a9b 6147 h->fw_support = readl(&(h->cfgtable->misc_fw_support));
c7ee65b3
WS		 6148 if (hpsa_supports_chained_sg_blocks(h)) {
6149 /* Limit in-command s/g elements to 32 save dma'able memory. */
b93d7536 6150 h->max_cmd_sg_entries = 32;
1a63ea6f 6151 h->chainsize = h->maxsgentries - h->max_cmd_sg_entries;
b93d7536
SC		 6152 h->maxsgentries--; /* save one for chain pointer */
6153 } else {
c7ee65b3
WS		 6154 /*
6155 * Original smart arrays supported at most 31 s/g entries
6156 * embedded inline in the command (trying to use more
6157 * would lock up the controller)
6158 */
6159 h->max_cmd_sg_entries = 31;
1a63ea6f 6160 h->maxsgentries = 31; /* default to traditional values */
c7ee65b3 6161 h->chainsize = 0;
b93d7536 6162 }
75167d2c
SC		 6163
6164 /* Find out what task management functions are supported and cache */
6165 h->TMFSupportFlags = readl(&(h->cfgtable->TMFSupportFlags));
0e7a7fce
ST		 6166 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags))
6167 dev_warn(&h->pdev->dev, "Physical aborts not supported\n");
6168 if (!(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
6169 dev_warn(&h->pdev->dev, "Logical aborts not supported\n");
b93d7536
SC		 6170}
6171
76c46e49
SC		 6172static inline bool hpsa_CISS_signature_present(struct ctlr_info *h)
6173{
0fc9fd40 6174 if (!check_signature(h->cfgtable->Signature, "CISS", 4)) {
050f7147 6175 dev_err(&h->pdev->dev, "not a valid CISS config table\n");
76c46e49
SC		 6176 return false;
6177 }
6178 return true;
6179}
6180
97a5e98c 6181static inline void hpsa_set_driver_support_bits(struct ctlr_info *h)
f7c39101 6182{
97a5e98c 6183 u32 driver_support;
f7c39101 6184
97a5e98c 6185 driver_support = readl(&(h->cfgtable->driver_support));
0b9e7b74
AB		 6186 /* Need to enable prefetch in the SCSI core for 6400 in x86 */
6187#ifdef CONFIG_X86
97a5e98c 6188 driver_support |= ENABLE_SCSI_PREFETCH;
f7c39101 6189#endif
28e13446
SC		 6190 driver_support |= ENABLE_UNIT_ATTN;
6191 writel(driver_support, &(h->cfgtable->driver_support));
f7c39101
SC		 6192}
6193
3d0eab67
SC		 6194/* Disable DMA prefetch for the P600. Otherwise an ASIC bug may result
6195 * in a prefetch beyond physical memory.
6196 */
6197static inline void hpsa_p600_dma_prefetch_quirk(struct ctlr_info *h)
6198{
6199 u32 dma_prefetch;
6200
6201 if (h->board_id != 0x3225103C)
6202 return;
6203 dma_prefetch = readl(h->vaddr + I2O_DMA1_CFG);
6204 dma_prefetch |= 0x8000;
6205 writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG);
6206}
6207
76438d08
SC		 6208static void hpsa_wait_for_clear_event_notify_ack(struct ctlr_info *h)
6209{
6210 int i;
6211 u32 doorbell_value;
6212 unsigned long flags;
6213 /* wait until the clear_event_notify bit 6 is cleared by controller. */
6214 for (i = 0; i < MAX_CONFIG_WAIT; i++) {
6215 spin_lock_irqsave(&h->lock, flags);
6216 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
6217 spin_unlock_irqrestore(&h->lock, flags);
6218 if (!(doorbell_value & DOORBELL_CLEAR_EVENTS))
6219 break;
6220 /* delay and try again */
6221 msleep(20);
6222 }
6223}
6224
6f039790 6225static void hpsa_wait_for_mode_change_ack(struct ctlr_info *h)
eb6b2ae9
SC		 6226{
6227 int i;
6eaf46fd
SC		 6228 u32 doorbell_value;
6229 unsigned long flags;
eb6b2ae9
SC		 6230
6231 /* under certain very rare conditions, this can take awhile.
6232 * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right
6233 * as we enter this code.)
6234 */
6235 for (i = 0; i < MAX_CONFIG_WAIT; i++) {
6eaf46fd
SC		 6236 spin_lock_irqsave(&h->lock, flags);
6237 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
6238 spin_unlock_irqrestore(&h->lock, flags);
382be668 6239 if (!(doorbell_value & CFGTBL_ChangeReq))
eb6b2ae9
SC		 6240 break;
6241 /* delay and try again */
60d3f5b0 6242 usleep_range(10000, 20000);
eb6b2ae9 6243 }
3f4336f3
SC		 6244}
6245
6f039790 6246static int hpsa_enter_simple_mode(struct ctlr_info *h)
3f4336f3
SC		 6247{
6248 u32 trans_support;
6249
6250 trans_support = readl(&(h->cfgtable->TransportSupport));
6251 if (!(trans_support & SIMPLE_MODE))
6252 return -ENOTSUPP;
6253
6254 h->max_commands = readl(&(h->cfgtable->CmdsOutMax));
283b4a9b 6255
3f4336f3
SC		 6256 /* Update the field, and then ring the doorbell */
6257 writel(CFGTBL_Trans_Simple, &(h->cfgtable->HostWrite.TransportRequest));
b9af4937 6258 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
3f4336f3
SC		 6259 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
6260 hpsa_wait_for_mode_change_ack(h);
eb6b2ae9 6261 print_cfg_table(&h->pdev->dev, h->cfgtable);
283b4a9b
SC		 6262 if (!(readl(&(h->cfgtable->TransportActive)) & CFGTBL_Trans_Simple))
6263 goto error;
960a30e7 6264 h->transMethod = CFGTBL_Trans_Simple;
eb6b2ae9 6265 return 0;
283b4a9b 6266error:
050f7147 6267 dev_err(&h->pdev->dev, "failed to enter simple mode\n");
283b4a9b 6268 return -ENODEV;
eb6b2ae9
SC		 6269}
6270
6f039790 6271static int hpsa_pci_init(struct ctlr_info *h)
77c4495c 6272{
eb6b2ae9 6273 int prod_index, err;
edd16368 6274
e5c880d1
SC		 6275 prod_index = hpsa_lookup_board_id(h->pdev, &h->board_id);
6276 if (prod_index < 0)
60f923b9 6277 return prod_index;
e5c880d1
SC		 6278 h->product_name = products[prod_index].product_name;
6279 h->access = *(products[prod_index].access);
edd16368 6280
e5a44df8
MG		 6281 pci_disable_link_state(h->pdev, PCIE_LINK_STATE_L0S |
6282 PCIE_LINK_STATE_L1 | PCIE_LINK_STATE_CLKPM);
6283
55c06c71 6284 err = pci_enable_device(h->pdev);
edd16368 6285 if (err) {
55c06c71 6286 dev_warn(&h->pdev->dev, "unable to enable PCI device\n");
edd16368
SC		 6287 return err;
6288 }
6289
f79cfec6 6290 err = pci_request_regions(h->pdev, HPSA);
edd16368 6291 if (err) {
55c06c71
SC		 6292 dev_err(&h->pdev->dev,
6293 "cannot obtain PCI resources, aborting\n");
edd16368
SC		 6294 return err;
6295 }
4fa604e1
RE		 6296
6297 pci_set_master(h->pdev);
6298
6b3f4c52 6299 hpsa_interrupt_mode(h);
12d2cd47 6300 err = hpsa_pci_find_memory_BAR(h->pdev, &h->paddr);
3a7774ce 6301 if (err)
edd16368 6302 goto err_out_free_res;
edd16368 6303 h->vaddr = remap_pci_mem(h->paddr, 0x250);
204892e9
SC		 6304 if (!h->vaddr) {
6305 err = -ENOMEM;
6306 goto err_out_free_res;
6307 }
fe5389c8 6308 err = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
2c4c8c8b 6309 if (err)
edd16368 6310 goto err_out_free_res;
77c4495c
SC		 6311 err = hpsa_find_cfgtables(h);
6312 if (err)
edd16368 6313 goto err_out_free_res;
b93d7536 6314 hpsa_find_board_params(h);
edd16368 6315
76c46e49 6316 if (!hpsa_CISS_signature_present(h)) {
edd16368
SC		 6317 err = -ENODEV;
6318 goto err_out_free_res;
6319 }
97a5e98c 6320 hpsa_set_driver_support_bits(h);
3d0eab67 6321 hpsa_p600_dma_prefetch_quirk(h);
eb6b2ae9
SC		 6322 err = hpsa_enter_simple_mode(h);
6323 if (err)
edd16368 6324 goto err_out_free_res;
edd16368
SC		 6325 return 0;
6326
6327err_out_free_res:
204892e9
SC		 6328 if (h->transtable)
6329 iounmap(h->transtable);
6330 if (h->cfgtable)
6331 iounmap(h->cfgtable);
6332 if (h->vaddr)
6333 iounmap(h->vaddr);
f0bd0b68 6334 pci_disable_device(h->pdev);
55c06c71 6335 pci_release_regions(h->pdev);
edd16368
SC		 6336 return err;
6337}
6338
6f039790 6339static void hpsa_hba_inquiry(struct ctlr_info *h)
339b2b14
SC		 6340{
6341 int rc;
6342
6343#define HBA_INQUIRY_BYTE_COUNT 64
6344 h->hba_inquiry_data = kmalloc(HBA_INQUIRY_BYTE_COUNT, GFP_KERNEL);
6345 if (!h->hba_inquiry_data)
6346 return;
6347 rc = hpsa_scsi_do_inquiry(h, RAID_CTLR_LUNID, 0,
6348 h->hba_inquiry_data, HBA_INQUIRY_BYTE_COUNT);
6349 if (rc != 0) {
6350 kfree(h->hba_inquiry_data);
6351 h->hba_inquiry_data = NULL;
6352 }
6353}
6354
6f039790 6355static int hpsa_init_reset_devices(struct pci_dev *pdev)
4c2a8c40 6356{
1df8552a 6357 int rc, i;
3b747298 6358 void __iomem *vaddr;
4c2a8c40
SC		 6359
6360 if (!reset_devices)
6361 return 0;
6362
132aa220
TH		 6363 /* kdump kernel is loading, we don't know in which state is
6364 * the pci interface. The dev->enable_cnt is equal zero
6365 * so we call enable+disable, wait a while and switch it on.
6366 */
6367 rc = pci_enable_device(pdev);
6368 if (rc) {
6369 dev_warn(&pdev->dev, "Failed to enable PCI device\n");
6370 return -ENODEV;
6371 }
6372 pci_disable_device(pdev);
6373 msleep(260); /* a randomly chosen number */
6374 rc = pci_enable_device(pdev);
6375 if (rc) {
6376 dev_warn(&pdev->dev, "failed to enable device.\n");
6377 return -ENODEV;
6378 }
4fa604e1 6379
859c75ab 6380 pci_set_master(pdev);
4fa604e1 6381
3b747298
TH		 6382 vaddr = pci_ioremap_bar(pdev, 0);
6383 if (vaddr == NULL) {
6384 rc = -ENOMEM;
6385 goto out_disable;
6386 }
6387 writel(SA5_INTR_OFF, vaddr + SA5_REPLY_INTR_MASK_OFFSET);
6388 iounmap(vaddr);
6389
1df8552a
SC		 6390 /* Reset the controller with a PCI power-cycle or via doorbell */
6391 rc = hpsa_kdump_hard_reset_controller(pdev);
4c2a8c40 6392
1df8552a
SC		 6393 /* -ENOTSUPP here means we cannot reset the controller
6394 * but it's already (and still) up and running in
18867659
SC		 6395 * "performant mode". Or, it might be 640x, which can't reset
6396 * due to concerns about shared bbwc between 6402/6404 pair.
1df8552a 6397 */
adf1b3a3 6398 if (rc)
132aa220 6399 goto out_disable;
4c2a8c40
SC		 6400
6401 /* Now try to get the controller to respond to a no-op */
1ba66c9c 6402 dev_info(&pdev->dev, "Waiting for controller to respond to no-op\n");
4c2a8c40
SC		 6403 for (i = 0; i < HPSA_POST_RESET_NOOP_RETRIES; i++) {
6404 if (hpsa_noop(pdev) == 0)
6405 break;
6406 else
6407 dev_warn(&pdev->dev, "no-op failed%s\n",
6408 (i < 11 ? "; re-trying" : ""));
6409 }
132aa220
TH		 6410
6411out_disable:
6412
6413 pci_disable_device(pdev);
6414 return rc;
4c2a8c40
SC		 6415}
6416
6f039790 6417static int hpsa_allocate_cmd_pool(struct ctlr_info *h)
2e9d1b36
SC		 6418{
6419 h->cmd_pool_bits = kzalloc(
6420 DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG) *
6421 sizeof(unsigned long), GFP_KERNEL);
6422 h->cmd_pool = pci_alloc_consistent(h->pdev,
6423 h->nr_cmds * sizeof(*h->cmd_pool),
6424 &(h->cmd_pool_dhandle));
6425 h->errinfo_pool = pci_alloc_consistent(h->pdev,
6426 h->nr_cmds * sizeof(*h->errinfo_pool),
6427 &(h->errinfo_pool_dhandle));
6428 if ((h->cmd_pool_bits == NULL)
6429 || (h->cmd_pool == NULL)
6430 || (h->errinfo_pool == NULL)) {
6431 dev_err(&h->pdev->dev, "out of memory in %s", __func__);
2c143342 6432 goto clean_up;
2e9d1b36
SC		 6433 }
6434 return 0;
2c143342
RE		 6435clean_up:
6436 hpsa_free_cmd_pool(h);
6437 return -ENOMEM;
2e9d1b36
SC		 6438}
6439
6440static void hpsa_free_cmd_pool(struct ctlr_info *h)
6441{
6442 kfree(h->cmd_pool_bits);
6443 if (h->cmd_pool)
6444 pci_free_consistent(h->pdev,
6445 h->nr_cmds * sizeof(struct CommandList),
6446 h->cmd_pool, h->cmd_pool_dhandle);
aca9012a
SC		 6447 if (h->ioaccel2_cmd_pool)
6448 pci_free_consistent(h->pdev,
6449 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
6450 h->ioaccel2_cmd_pool, h->ioaccel2_cmd_pool_dhandle);
2e9d1b36
SC		 6451 if (h->errinfo_pool)
6452 pci_free_consistent(h->pdev,
6453 h->nr_cmds * sizeof(struct ErrorInfo),
6454 h->errinfo_pool,
6455 h->errinfo_pool_dhandle);
e1f7de0c
MG		 6456 if (h->ioaccel_cmd_pool)
6457 pci_free_consistent(h->pdev,
6458 h->nr_cmds * sizeof(struct io_accel1_cmd),
6459 h->ioaccel_cmd_pool, h->ioaccel_cmd_pool_dhandle);
2e9d1b36
SC		 6460}
6461
41b3cf08
SC		 6462static void hpsa_irq_affinity_hints(struct ctlr_info *h)
6463{
ec429952 6464 int i, cpu;
41b3cf08
SC		 6465
6466 cpu = cpumask_first(cpu_online_mask);
6467 for (i = 0; i < h->msix_vector; i++) {
ec429952 6468 irq_set_affinity_hint(h->intr[i], get_cpu_mask(cpu));
41b3cf08
SC		 6469 cpu = cpumask_next(cpu, cpu_online_mask);
6470 }
6471}
6472
ec501a18
RE		 6473/* clear affinity hints and free MSI-X, MSI, or legacy INTx vectors */
6474static void hpsa_free_irqs(struct ctlr_info *h)
6475{
6476 int i;
6477
6478 if (!h->msix_vector || h->intr_mode != PERF_MODE_INT) {
6479 /* Single reply queue, only one irq to free */
6480 i = h->intr_mode;
6481 irq_set_affinity_hint(h->intr[i], NULL);
6482 free_irq(h->intr[i], &h->q[i]);
6483 return;
6484 }
6485
6486 for (i = 0; i < h->msix_vector; i++) {
6487 irq_set_affinity_hint(h->intr[i], NULL);
6488 free_irq(h->intr[i], &h->q[i]);
6489 }
a4e17fc1
RE		 6490 for (; i < MAX_REPLY_QUEUES; i++)
6491 h->q[i] = 0;
ec501a18
RE		 6492}
6493
9ee61794
RE		 6494/* returns 0 on success; cleans up and returns -Enn on error */
6495static int hpsa_request_irqs(struct ctlr_info *h,
0ae01a32
SC		 6496 irqreturn_t (*msixhandler)(int, void *),
6497 irqreturn_t (*intxhandler)(int, void *))
6498{
254f796b 6499 int rc, i;
0ae01a32 6500
254f796b
MG		 6501 /*
6502 * initialize h->q[x] = x so that interrupt handlers know which
6503 * queue to process.
6504 */
6505 for (i = 0; i < MAX_REPLY_QUEUES; i++)
6506 h->q[i] = (u8) i;
6507
eee0f03a 6508 if (h->intr_mode == PERF_MODE_INT && h->msix_vector > 0) {
254f796b 6509 /* If performant mode and MSI-X, use multiple reply queues */
a4e17fc1 6510 for (i = 0; i < h->msix_vector; i++) {
254f796b
MG		 6511 rc = request_irq(h->intr[i], msixhandler,
6512 0, h->devname,
6513 &h->q[i]);
a4e17fc1
RE		 6514 if (rc) {
6515 int j;
6516
6517 dev_err(&h->pdev->dev,
6518 "failed to get irq %d for %s\n",
6519 h->intr[i], h->devname);
6520 for (j = 0; j < i; j++) {
6521 free_irq(h->intr[j], &h->q[j]);
6522 h->q[j] = 0;
6523 }
6524 for (; j < MAX_REPLY_QUEUES; j++)
6525 h->q[j] = 0;
6526 return rc;
6527 }
6528 }
41b3cf08 6529 hpsa_irq_affinity_hints(h);
254f796b
MG		 6530 } else {
6531 /* Use single reply pool */
eee0f03a 6532 if (h->msix_vector > 0 || h->msi_vector) {
254f796b
MG		 6533 rc = request_irq(h->intr[h->intr_mode],
6534 msixhandler, 0, h->devname,
6535 &h->q[h->intr_mode]);
6536 } else {
6537 rc = request_irq(h->intr[h->intr_mode],
6538 intxhandler, IRQF_SHARED, h->devname,
6539 &h->q[h->intr_mode]);
6540 }
6541 }
0ae01a32
SC		 6542 if (rc) {
6543 dev_err(&h->pdev->dev, "unable to get irq %d for %s\n",
6544 h->intr[h->intr_mode], h->devname);
6545 return -ENODEV;
6546 }
6547 return 0;
6548}
6549
6f039790 6550static int hpsa_kdump_soft_reset(struct ctlr_info *h)
64670ac8
SC		 6551{
6552 if (hpsa_send_host_reset(h, RAID_CTLR_LUNID,
6553 HPSA_RESET_TYPE_CONTROLLER)) {
6554 dev_warn(&h->pdev->dev, "Resetting array controller failed.\n");
6555 return -EIO;
6556 }
6557
6558 dev_info(&h->pdev->dev, "Waiting for board to soft reset.\n");
6559 if (hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_NOT_READY)) {
6560 dev_warn(&h->pdev->dev, "Soft reset had no effect.\n");
6561 return -1;
6562 }
6563
6564 dev_info(&h->pdev->dev, "Board reset, awaiting READY status.\n");
6565 if (hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY)) {
6566 dev_warn(&h->pdev->dev, "Board failed to become ready "
6567 "after soft reset.\n");
6568 return -1;
6569 }
6570
6571 return 0;
6572}
6573
0097f0f4 6574static void hpsa_free_irqs_and_disable_msix(struct ctlr_info *h)
64670ac8 6575{
ec501a18 6576 hpsa_free_irqs(h);
64670ac8 6577#ifdef CONFIG_PCI_MSI
0097f0f4
SC		 6578 if (h->msix_vector) {
6579 if (h->pdev->msix_enabled)
6580 pci_disable_msix(h->pdev);
6581 } else if (h->msi_vector) {
6582 if (h->pdev->msi_enabled)
6583 pci_disable_msi(h->pdev);
6584 }
64670ac8 6585#endif /* CONFIG_PCI_MSI */
0097f0f4
SC		 6586}
6587
072b0518
SC		 6588static void hpsa_free_reply_queues(struct ctlr_info *h)
6589{
6590 int i;
6591
6592 for (i = 0; i < h->nreply_queues; i++) {
6593 if (!h->reply_queue[i].head)
6594 continue;
6595 pci_free_consistent(h->pdev, h->reply_queue_size,
6596 h->reply_queue[i].head, h->reply_queue[i].busaddr);
6597 h->reply_queue[i].head = NULL;
6598 h->reply_queue[i].busaddr = 0;
6599 }
6600}
6601
0097f0f4
SC		 6602static void hpsa_undo_allocations_after_kdump_soft_reset(struct ctlr_info *h)
6603{
6604 hpsa_free_irqs_and_disable_msix(h);
64670ac8
SC		 6605 hpsa_free_sg_chain_blocks(h);
6606 hpsa_free_cmd_pool(h);
e1f7de0c 6607 kfree(h->ioaccel1_blockFetchTable);
64670ac8 6608 kfree(h->blockFetchTable);
072b0518 6609 hpsa_free_reply_queues(h);
64670ac8
SC		 6610 if (h->vaddr)
6611 iounmap(h->vaddr);
6612 if (h->transtable)
6613 iounmap(h->transtable);
6614 if (h->cfgtable)
6615 iounmap(h->cfgtable);
132aa220 6616 pci_disable_device(h->pdev);
64670ac8
SC		 6617 pci_release_regions(h->pdev);
6618 kfree(h);
6619}
6620
a0c12413
SC		 6621/* Called when controller lockup detected. */
6622static void fail_all_cmds_on_list(struct ctlr_info *h, struct list_head *list)
6623{
6624 struct CommandList *c = NULL;
6625
6626 assert_spin_locked(&h->lock);
6627 /* Mark all outstanding commands as failed and complete them. */
6628 while (!list_empty(list)) {
6629 c = list_entry(list->next, struct CommandList, list);
6630 c->err_info->CommandStatus = CMD_HARDWARE_ERR;
5a3d16f5 6631 finish_cmd(c);
a0c12413
SC		 6632 }
6633}
6634
094963da
SC		 6635static void set_lockup_detected_for_all_cpus(struct ctlr_info *h, u32 value)
6636{
6637 int i, cpu;
6638
6639 cpu = cpumask_first(cpu_online_mask);
6640 for (i = 0; i < num_online_cpus(); i++) {
6641 u32 *lockup_detected;
6642 lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
6643 *lockup_detected = value;
6644 cpu = cpumask_next(cpu, cpu_online_mask);
6645 }
6646 wmb(); /* be sure the per-cpu variables are out to memory */
6647}
6648
a0c12413
SC		 6649static void controller_lockup_detected(struct ctlr_info *h)
6650{
6651 unsigned long flags;
094963da 6652 u32 lockup_detected;
a0c12413 6653
a0c12413
SC		 6654 h->access.set_intr_mask(h, HPSA_INTR_OFF);
6655 spin_lock_irqsave(&h->lock, flags);
094963da
SC		 6656 lockup_detected = readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
6657 if (!lockup_detected) {
6658 /* no heartbeat, but controller gave us a zero. */
6659 dev_warn(&h->pdev->dev,
6660 "lockup detected but scratchpad register is zero\n");
6661 lockup_detected = 0xffffffff;
6662 }
6663 set_lockup_detected_for_all_cpus(h, lockup_detected);
a0c12413
SC		 6664 spin_unlock_irqrestore(&h->lock, flags);
6665 dev_warn(&h->pdev->dev, "Controller lockup detected: 0x%08x\n",
094963da 6666 lockup_detected);
a0c12413
SC		 6667 pci_disable_device(h->pdev);
6668 spin_lock_irqsave(&h->lock, flags);
6669 fail_all_cmds_on_list(h, &h->cmpQ);
6670 fail_all_cmds_on_list(h, &h->reqQ);
6671 spin_unlock_irqrestore(&h->lock, flags);
6672}
6673
a0c12413
SC		 6674static void detect_controller_lockup(struct ctlr_info *h)
6675{
6676 u64 now;
6677 u32 heartbeat;
6678 unsigned long flags;
6679
a0c12413
SC		 6680 now = get_jiffies_64();
6681 /* If we've received an interrupt recently, we're ok. */
6682 if (time_after64(h->last_intr_timestamp +
e85c5974 6683 (h->heartbeat_sample_interval), now))
a0c12413
SC		 6684 return;
6685
6686 /*
6687 * If we've already checked the heartbeat recently, we're ok.
6688 * This could happen if someone sends us a signal. We
6689 * otherwise don't care about signals in this thread.
6690 */
6691 if (time_after64(h->last_heartbeat_timestamp +
e85c5974 6692 (h->heartbeat_sample_interval), now))
a0c12413
SC		 6693 return;
6694
6695 /* If heartbeat has not changed since we last looked, we're not ok. */
6696 spin_lock_irqsave(&h->lock, flags);
6697 heartbeat = readl(&h->cfgtable->HeartBeat);
6698 spin_unlock_irqrestore(&h->lock, flags);
6699 if (h->last_heartbeat == heartbeat) {
6700 controller_lockup_detected(h);
6701 return;
6702 }
6703
6704 /* We're ok. */
6705 h->last_heartbeat = heartbeat;
6706 h->last_heartbeat_timestamp = now;
6707}
6708
9846590e 6709static void hpsa_ack_ctlr_events(struct ctlr_info *h)
76438d08
SC		 6710{
6711 int i;
6712 char *event_type;
6713
e863d68e
ST		 6714 /* Clear the driver-requested rescan flag */
6715 h->drv_req_rescan = 0;
6716
76438d08 6717 /* Ask the controller to clear the events we're handling. */
1f7cee8c
SC		 6718 if ((h->transMethod & (CFGTBL_Trans_io_accel1
6719 | CFGTBL_Trans_io_accel2)) &&
76438d08
SC		 6720 (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE ||
6721 h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)) {
6722
6723 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE)
6724 event_type = "state change";
6725 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)
6726 event_type = "configuration change";
6727 /* Stop sending new RAID offload reqs via the IO accelerator */
6728 scsi_block_requests(h->scsi_host);
6729 for (i = 0; i < h->ndevices; i++)
6730 h->dev[i]->offload_enabled = 0;
23100dd9 6731 hpsa_drain_accel_commands(h);
76438d08
SC		 6732 /* Set 'accelerator path config change' bit */
6733 dev_warn(&h->pdev->dev,
6734 "Acknowledging event: 0x%08x (HP SSD Smart Path %s)\n",
6735 h->events, event_type);
6736 writel(h->events, &(h->cfgtable->clear_event_notify));
6737 /* Set the "clear event notify field update" bit 6 */
6738 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
6739 /* Wait until ctlr clears 'clear event notify field', bit 6 */
6740 hpsa_wait_for_clear_event_notify_ack(h);
6741 scsi_unblock_requests(h->scsi_host);
6742 } else {
6743 /* Acknowledge controller notification events. */
6744 writel(h->events, &(h->cfgtable->clear_event_notify));
6745 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
6746 hpsa_wait_for_clear_event_notify_ack(h);
6747#if 0
6748 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
6749 hpsa_wait_for_mode_change_ack(h);
6750#endif
6751 }
9846590e 6752 return;
76438d08
SC		 6753}
6754
6755/* Check a register on the controller to see if there are configuration
6756 * changes (added/changed/removed logical drives, etc.) which mean that
e863d68e
ST		 6757 * we should rescan the controller for devices.
6758 * Also check flag for driver-initiated rescan.
76438d08 6759 */
9846590e 6760static int hpsa_ctlr_needs_rescan(struct ctlr_info *h)
76438d08 6761{
9846590e
SC		 6762 if (h->drv_req_rescan)
6763 return 1;
6764
76438d08 6765 if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
9846590e 6766 return 0;
76438d08
SC		 6767
6768 h->events = readl(&(h->cfgtable->event_notify));
9846590e
SC		 6769 return h->events & RESCAN_REQUIRED_EVENT_BITS;
6770}
76438d08 6771
9846590e
SC		 6772/*
6773 * Check if any of the offline devices have become ready
6774 */
6775static int hpsa_offline_devices_ready(struct ctlr_info *h)
6776{
6777 unsigned long flags;
6778 struct offline_device_entry *d;
6779 struct list_head *this, *tmp;
6780
6781 spin_lock_irqsave(&h->offline_device_lock, flags);
6782 list_for_each_safe(this, tmp, &h->offline_device_list) {
6783 d = list_entry(this, struct offline_device_entry,
6784 offline_list);
6785 spin_unlock_irqrestore(&h->offline_device_lock, flags);
d1fea47c
SC		 6786 if (!hpsa_volume_offline(h, d->scsi3addr)) {
6787 spin_lock_irqsave(&h->offline_device_lock, flags);
6788 list_del(&d->offline_list);
6789 spin_unlock_irqrestore(&h->offline_device_lock, flags);
9846590e 6790 return 1;
d1fea47c 6791 }
9846590e
SC		 6792 spin_lock_irqsave(&h->offline_device_lock, flags);
6793 }
6794 spin_unlock_irqrestore(&h->offline_device_lock, flags);
6795 return 0;
76438d08
SC		 6796}
6797
9846590e 6798
8a98db73 6799static void hpsa_monitor_ctlr_worker(struct work_struct *work)
a0c12413
SC		 6800{
6801 unsigned long flags;
8a98db73
SC		 6802 struct ctlr_info *h = container_of(to_delayed_work(work),
6803 struct ctlr_info, monitor_ctlr_work);
6804 detect_controller_lockup(h);
094963da 6805 if (lockup_detected(h))
8a98db73 6806 return;
9846590e
SC		 6807
6808 if (hpsa_ctlr_needs_rescan(h) || hpsa_offline_devices_ready(h)) {
6809 scsi_host_get(h->scsi_host);
6810 h->drv_req_rescan = 0;
6811 hpsa_ack_ctlr_events(h);
6812 hpsa_scan_start(h->scsi_host);
6813 scsi_host_put(h->scsi_host);
6814 }
6815
8a98db73
SC		 6816 spin_lock_irqsave(&h->lock, flags);
6817 if (h->remove_in_progress) {
6818 spin_unlock_irqrestore(&h->lock, flags);
a0c12413
SC		 6819 return;
6820 }
8a98db73
SC		 6821 schedule_delayed_work(&h->monitor_ctlr_work,
6822 h->heartbeat_sample_interval);
6823 spin_unlock_irqrestore(&h->lock, flags);
a0c12413
SC		 6824}
6825
6f039790 6826static int hpsa_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
edd16368 6827{
4c2a8c40 6828 int dac, rc;
edd16368 6829 struct ctlr_info *h;
64670ac8
SC		 6830 int try_soft_reset = 0;
6831 unsigned long flags;
edd16368
SC		 6832
6833 if (number_of_controllers == 0)
6834 printk(KERN_INFO DRIVER_NAME "\n");
edd16368 6835
4c2a8c40 6836 rc = hpsa_init_reset_devices(pdev);
64670ac8
SC		 6837 if (rc) {
6838 if (rc != -ENOTSUPP)
6839 return rc;
6840 /* If the reset fails in a particular way (it has no way to do
6841 * a proper hard reset, so returns -ENOTSUPP) we can try to do
6842 * a soft reset once we get the controller configured up to the
6843 * point that it can accept a command.
6844 */
6845 try_soft_reset = 1;
6846 rc = 0;
6847 }
6848
6849reinit_after_soft_reset:
edd16368 6850
303932fd
DB		 6851 /* Command structures must be aligned on a 32-byte boundary because
6852 * the 5 lower bits of the address are used by the hardware. and by
6853 * the driver. See comments in hpsa.h for more info.
6854 */
303932fd 6855 BUILD_BUG_ON(sizeof(struct CommandList) % COMMANDLIST_ALIGNMENT);
edd16368
SC		 6856 h = kzalloc(sizeof(*h), GFP_KERNEL);
6857 if (!h)
ecd9aad4 6858 return -ENOMEM;
edd16368 6859
55c06c71 6860 h->pdev = pdev;
a9a3a273 6861 h->intr_mode = hpsa_simple_mode ? SIMPLE_MODE_INT : PERF_MODE_INT;
9e0fc764
SC		 6862 INIT_LIST_HEAD(&h->cmpQ);
6863 INIT_LIST_HEAD(&h->reqQ);
9846590e 6864 INIT_LIST_HEAD(&h->offline_device_list);
6eaf46fd 6865 spin_lock_init(&h->lock);
9846590e 6866 spin_lock_init(&h->offline_device_lock);
6eaf46fd 6867 spin_lock_init(&h->scan_lock);
0390f0c0 6868 spin_lock_init(&h->passthru_count_lock);
094963da
SC		 6869
6870 /* Allocate and clear per-cpu variable lockup_detected */
6871 h->lockup_detected = alloc_percpu(u32);
2a5ac326
SC		 6872 if (!h->lockup_detected) {
6873 rc = -ENOMEM;
094963da 6874 goto clean1;
2a5ac326 6875 }
094963da
SC		 6876 set_lockup_detected_for_all_cpus(h, 0);
6877
55c06c71 6878 rc = hpsa_pci_init(h);
ecd9aad4 6879 if (rc != 0)
edd16368
SC		 6880 goto clean1;
6881
f79cfec6 6882 sprintf(h->devname, HPSA "%d", number_of_controllers);
edd16368
SC		 6883 h->ctlr = number_of_controllers;
6884 number_of_controllers++;
edd16368
SC		 6885
6886 /* configure PCI DMA stuff */
ecd9aad4
SC		 6887 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
6888 if (rc == 0) {
edd16368 6889 dac = 1;
ecd9aad4
SC		 6890 } else {
6891 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6892 if (rc == 0) {
6893 dac = 0;
6894 } else {
6895 dev_err(&pdev->dev, "no suitable DMA available\n");
6896 goto clean1;
6897 }
edd16368
SC		 6898 }
6899
6900 /* make sure the board interrupts are off */
6901 h->access.set_intr_mask(h, HPSA_INTR_OFF);
10f66018 6902
9ee61794 6903 if (hpsa_request_irqs(h, do_hpsa_intr_msi, do_hpsa_intr_intx))
edd16368 6904 goto clean2;
303932fd
DB		 6905 dev_info(&pdev->dev, "%s: <0x%x> at IRQ %d%s using DAC\n",
6906 h->devname, pdev->device,
a9a3a273 6907 h->intr[h->intr_mode], dac ? "" : " not");
8947fd10
RE		 6908 rc = hpsa_allocate_cmd_pool(h);
6909 if (rc)
6910 goto clean2_and_free_irqs;
33a2ffce
SC		 6911 if (hpsa_allocate_sg_chain_blocks(h))
6912 goto clean4;
a08a8471
SC		 6913 init_waitqueue_head(&h->scan_wait_queue);
6914 h->scan_finished = 1; /* no scan currently in progress */
edd16368
SC		 6915
6916 pci_set_drvdata(pdev, h);
9a41338e 6917 h->ndevices = 0;
316b221a 6918 h->hba_mode_enabled = 0;
9a41338e
SC		 6919 h->scsi_host = NULL;
6920 spin_lock_init(&h->devlock);
64670ac8
SC		 6921 hpsa_put_ctlr_into_performant_mode(h);
6922
6923 /* At this point, the controller is ready to take commands.
6924 * Now, if reset_devices and the hard reset didn't work, try
6925 * the soft reset and see if that works.
6926 */
6927 if (try_soft_reset) {
6928
6929 /* This is kind of gross. We may or may not get a completion
6930 * from the soft reset command, and if we do, then the value
6931 * from the fifo may or may not be valid. So, we wait 10 secs
6932 * after the reset throwing away any completions we get during
6933 * that time. Unregister the interrupt handler and register
6934 * fake ones to scoop up any residual completions.
6935 */
6936 spin_lock_irqsave(&h->lock, flags);
6937 h->access.set_intr_mask(h, HPSA_INTR_OFF);
6938 spin_unlock_irqrestore(&h->lock, flags);
ec501a18 6939 hpsa_free_irqs(h);
9ee61794 6940 rc = hpsa_request_irqs(h, hpsa_msix_discard_completions,
64670ac8
SC		 6941 hpsa_intx_discard_completions);
6942 if (rc) {
9ee61794
RE		 6943 dev_warn(&h->pdev->dev,
6944 "Failed to request_irq after soft reset.\n");
64670ac8
SC		 6945 goto clean4;
6946 }
6947
6948 rc = hpsa_kdump_soft_reset(h);
6949 if (rc)
6950 /* Neither hard nor soft reset worked, we're hosed. */
6951 goto clean4;
6952
6953 dev_info(&h->pdev->dev, "Board READY.\n");
6954 dev_info(&h->pdev->dev,
6955 "Waiting for stale completions to drain.\n");
6956 h->access.set_intr_mask(h, HPSA_INTR_ON);
6957 msleep(10000);
6958 h->access.set_intr_mask(h, HPSA_INTR_OFF);
6959
6960 rc = controller_reset_failed(h->cfgtable);
6961 if (rc)
6962 dev_info(&h->pdev->dev,
6963 "Soft reset appears to have failed.\n");
6964
6965 /* since the controller's reset, we have to go back and re-init
6966 * everything. Easiest to just forget what we've done and do it
6967 * all over again.
6968 */
6969 hpsa_undo_allocations_after_kdump_soft_reset(h);
6970 try_soft_reset = 0;
6971 if (rc)
6972 /* don't go to clean4, we already unallocated */
6973 return -ENODEV;
6974
6975 goto reinit_after_soft_reset;
6976 }
edd16368 6977
316b221a
SC		 6978 /* Enable Accelerated IO path at driver layer */
6979 h->acciopath_status = 1;
da0697bd 6980
e863d68e
ST		 6981 h->drv_req_rescan = 0;
6982
edd16368
SC		 6983 /* Turn the interrupts on so we can service requests */
6984 h->access.set_intr_mask(h, HPSA_INTR_ON);
6985
339b2b14 6986 hpsa_hba_inquiry(h);
edd16368 6987 hpsa_register_scsi(h); /* hook ourselves into SCSI subsystem */
8a98db73
SC		 6988
6989 /* Monitor the controller for firmware lockups */
6990 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
6991 INIT_DELAYED_WORK(&h->monitor_ctlr_work, hpsa_monitor_ctlr_worker);
6992 schedule_delayed_work(&h->monitor_ctlr_work,
6993 h->heartbeat_sample_interval);
88bf6d62 6994 return 0;
edd16368
SC		 6995
6996clean4:
33a2ffce 6997 hpsa_free_sg_chain_blocks(h);
2e9d1b36 6998 hpsa_free_cmd_pool(h);
8947fd10 6999clean2_and_free_irqs:
ec501a18 7000 hpsa_free_irqs(h);
edd16368
SC		 7001clean2:
7002clean1:
094963da
SC		 7003 if (h->lockup_detected)
7004 free_percpu(h->lockup_detected);
edd16368 7005 kfree(h);
ecd9aad4 7006 return rc;
edd16368
SC		 7007}
7008
7009static void hpsa_flush_cache(struct ctlr_info *h)
7010{
7011 char *flush_buf;
7012 struct CommandList *c;
702890e3
SC		 7013
7014 /* Don't bother trying to flush the cache if locked up */
094963da 7015 if (unlikely(lockup_detected(h)))
702890e3 7016 return;
edd16368
SC		 7017 flush_buf = kzalloc(4, GFP_KERNEL);
7018 if (!flush_buf)
7019 return;
7020
45fcb86e 7021 c = cmd_alloc(h);
edd16368 7022 if (!c) {
45fcb86e 7023 dev_warn(&h->pdev->dev, "cmd_alloc returned NULL!\n");
edd16368
SC		 7024 goto out_of_memory;
7025 }
a2dac136
SC		 7026 if (fill_cmd(c, HPSA_CACHE_FLUSH, h, flush_buf, 4, 0,
7027 RAID_CTLR_LUNID, TYPE_CMD)) {
7028 goto out;
7029 }
edd16368
SC		 7030 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_TODEVICE);
7031 if (c->err_info->CommandStatus != 0)
a2dac136 7032out:
edd16368
SC		 7033 dev_warn(&h->pdev->dev,
7034 "error flushing cache on controller\n");
45fcb86e 7035 cmd_free(h, c);
edd16368
SC		 7036out_of_memory:
7037 kfree(flush_buf);
7038}
7039
7040static void hpsa_shutdown(struct pci_dev *pdev)
7041{
7042 struct ctlr_info *h;
7043
7044 h = pci_get_drvdata(pdev);
7045 /* Turn board interrupts off and send the flush cache command
7046 * sendcmd will turn off interrupt, and send the flush...
7047 * To write all data in the battery backed cache to disks
7048 */
7049 hpsa_flush_cache(h);
7050 h->access.set_intr_mask(h, HPSA_INTR_OFF);
0097f0f4 7051 hpsa_free_irqs_and_disable_msix(h);
edd16368
SC		 7052}
7053
6f039790 7054static void hpsa_free_device_info(struct ctlr_info *h)
55e14e76
SC		 7055{
7056 int i;
7057
7058 for (i = 0; i < h->ndevices; i++)
7059 kfree(h->dev[i]);
7060}
7061
6f039790 7062static void hpsa_remove_one(struct pci_dev *pdev)
edd16368
SC		 7063{
7064 struct ctlr_info *h;
8a98db73 7065 unsigned long flags;
edd16368
SC		 7066
7067 if (pci_get_drvdata(pdev) == NULL) {
a0c12413 7068 dev_err(&pdev->dev, "unable to remove device\n");
edd16368
SC		 7069 return;
7070 }
7071 h = pci_get_drvdata(pdev);
8a98db73
SC		 7072
7073 /* Get rid of any controller monitoring work items */
7074 spin_lock_irqsave(&h->lock, flags);
7075 h->remove_in_progress = 1;
7076 cancel_delayed_work(&h->monitor_ctlr_work);
7077 spin_unlock_irqrestore(&h->lock, flags);
7078
edd16368
SC		 7079 hpsa_unregister_scsi(h); /* unhook from SCSI subsystem */
7080 hpsa_shutdown(pdev);
7081 iounmap(h->vaddr);
204892e9
SC		 7082 iounmap(h->transtable);
7083 iounmap(h->cfgtable);
55e14e76 7084 hpsa_free_device_info(h);
33a2ffce 7085 hpsa_free_sg_chain_blocks(h);
edd16368
SC		 7086 pci_free_consistent(h->pdev,
7087 h->nr_cmds * sizeof(struct CommandList),
7088 h->cmd_pool, h->cmd_pool_dhandle);
7089 pci_free_consistent(h->pdev,
7090 h->nr_cmds * sizeof(struct ErrorInfo),
7091 h->errinfo_pool, h->errinfo_pool_dhandle);
072b0518 7092 hpsa_free_reply_queues(h);
edd16368 7093 kfree(h->cmd_pool_bits);
303932fd 7094 kfree(h->blockFetchTable);
e1f7de0c 7095 kfree(h->ioaccel1_blockFetchTable);
aca9012a 7096 kfree(h->ioaccel2_blockFetchTable);
339b2b14 7097 kfree(h->hba_inquiry_data);
f0bd0b68 7098 pci_disable_device(pdev);
edd16368 7099 pci_release_regions(pdev);
094963da 7100 free_percpu(h->lockup_detected);
edd16368
SC		 7101 kfree(h);
7102}
7103
7104static int hpsa_suspend(__attribute__((unused)) struct pci_dev *pdev,
7105 __attribute__((unused)) pm_message_t state)
7106{
7107 return -ENOSYS;
7108}
7109
7110static int hpsa_resume(__attribute__((unused)) struct pci_dev *pdev)
7111{
7112 return -ENOSYS;
7113}
7114
7115static struct pci_driver hpsa_pci_driver = {
f79cfec6 7116 .name = HPSA,
edd16368 7117 .probe = hpsa_init_one,
6f039790 7118 .remove = hpsa_remove_one,
edd16368
SC		 7119 .id_table = hpsa_pci_device_id, /* id_table */
7120 .shutdown = hpsa_shutdown,
7121 .suspend = hpsa_suspend,
7122 .resume = hpsa_resume,
7123};
7124
303932fd
DB		 7125/* Fill in bucket_map[], given nsgs (the max number of
7126 * scatter gather elements supported) and bucket[],
7127 * which is an array of 8 integers. The bucket[] array
7128 * contains 8 different DMA transfer sizes (in 16
7129 * byte increments) which the controller uses to fetch
7130 * commands. This function fills in bucket_map[], which
7131 * maps a given number of scatter gather elements to one of
7132 * the 8 DMA transfer sizes. The point of it is to allow the
7133 * controller to only do as much DMA as needed to fetch the
7134 * command, with the DMA transfer size encoded in the lower
7135 * bits of the command address.
7136 */
7137static void calc_bucket_map(int bucket[], int num_buckets,
2b08b3e9 7138 int nsgs, int min_blocks, u32 *bucket_map)
303932fd
DB		 7139{
7140 int i, j, b, size;
7141
303932fd
DB		 7142 /* Note, bucket_map must have nsgs+1 entries. */
7143 for (i = 0; i <= nsgs; i++) {
7144 /* Compute size of a command with i SG entries */
e1f7de0c 7145 size = i + min_blocks;
303932fd
DB		 7146 b = num_buckets; /* Assume the biggest bucket */
7147 /* Find the bucket that is just big enough */
e1f7de0c 7148 for (j = 0; j < num_buckets; j++) {
303932fd
DB		 7149 if (bucket[j] >= size) {
7150 b = j;
7151 break;
7152 }
7153 }
7154 /* for a command with i SG entries, use bucket b. */
7155 bucket_map[i] = b;
7156 }
7157}
7158
e1f7de0c 7159static void hpsa_enter_performant_mode(struct ctlr_info *h, u32 trans_support)
303932fd 7160{
6c311b57
SC		 7161 int i;
7162 unsigned long register_value;
e1f7de0c
MG		 7163 unsigned long transMethod = CFGTBL_Trans_Performant |
7164 (trans_support & CFGTBL_Trans_use_short_tags) |
b9af4937
SC		 7165 CFGTBL_Trans_enable_directed_msix |
7166 (trans_support & (CFGTBL_Trans_io_accel1 |
7167 CFGTBL_Trans_io_accel2));
e1f7de0c 7168 struct access_method access = SA5_performant_access;
def342bd
SC		 7169
7170 /* This is a bit complicated. There are 8 registers on
7171 * the controller which we write to to tell it 8 different
7172 * sizes of commands which there may be. It's a way of
7173 * reducing the DMA done to fetch each command. Encoded into
7174 * each command's tag are 3 bits which communicate to the controller
7175 * which of the eight sizes that command fits within. The size of
7176 * each command depends on how many scatter gather entries there are.
7177 * Each SG entry requires 16 bytes. The eight registers are programmed
7178 * with the number of 16-byte blocks a command of that size requires.
7179 * The smallest command possible requires 5 such 16 byte blocks.
d66ae08b 7180 * the largest command possible requires SG_ENTRIES_IN_CMD + 4 16-byte
def342bd
SC		 7181 * blocks. Note, this only extends to the SG entries contained
7182 * within the command block, and does not extend to chained blocks
7183 * of SG elements. bft[] contains the eight values we write to
7184 * the registers. They are not evenly distributed, but have more
7185 * sizes for small commands, and fewer sizes for larger commands.
7186 */
d66ae08b 7187 int bft[8] = {5, 6, 8, 10, 12, 20, 28, SG_ENTRIES_IN_CMD + 4};
b9af4937
SC		 7188#define MIN_IOACCEL2_BFT_ENTRY 5
7189#define HPSA_IOACCEL2_HEADER_SZ 4
7190 int bft2[16] = {MIN_IOACCEL2_BFT_ENTRY, 6, 7, 8, 9, 10, 11, 12,
7191 13, 14, 15, 16, 17, 18, 19,
7192 HPSA_IOACCEL2_HEADER_SZ + IOACCEL2_MAXSGENTRIES};
7193 BUILD_BUG_ON(ARRAY_SIZE(bft2) != 16);
7194 BUILD_BUG_ON(ARRAY_SIZE(bft) != 8);
7195 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) >
7196 16 * MIN_IOACCEL2_BFT_ENTRY);
7197 BUILD_BUG_ON(sizeof(struct ioaccel2_sg_element) != 16);
d66ae08b 7198 BUILD_BUG_ON(28 > SG_ENTRIES_IN_CMD + 4);
303932fd
DB		 7199 /* 5 = 1 s/g entry or 4k
7200 * 6 = 2 s/g entry or 8k
7201 * 8 = 4 s/g entry or 16k
7202 * 10 = 6 s/g entry or 24k
7203 */
303932fd 7204
b3a52e79
SC		 7205 /* If the controller supports either ioaccel method then
7206 * we can also use the RAID stack submit path that does not
7207 * perform the superfluous readl() after each command submission.
7208 */
7209 if (trans_support & (CFGTBL_Trans_io_accel1 | CFGTBL_Trans_io_accel2))
7210 access = SA5_performant_access_no_read;
7211
303932fd 7212 /* Controller spec: zero out this buffer. */
072b0518
SC		 7213 for (i = 0; i < h->nreply_queues; i++)
7214 memset(h->reply_queue[i].head, 0, h->reply_queue_size);
303932fd 7215
d66ae08b
SC		 7216 bft[7] = SG_ENTRIES_IN_CMD + 4;
7217 calc_bucket_map(bft, ARRAY_SIZE(bft),
e1f7de0c 7218 SG_ENTRIES_IN_CMD, 4, h->blockFetchTable);
303932fd
DB		 7219 for (i = 0; i < 8; i++)
7220 writel(bft[i], &h->transtable->BlockFetch[i]);
7221
7222 /* size of controller ring buffer */
7223 writel(h->max_commands, &h->transtable->RepQSize);
254f796b 7224 writel(h->nreply_queues, &h->transtable->RepQCount);
303932fd
DB		 7225 writel(0, &h->transtable->RepQCtrAddrLow32);
7226 writel(0, &h->transtable->RepQCtrAddrHigh32);
254f796b
MG		 7227
7228 for (i = 0; i < h->nreply_queues; i++) {
7229 writel(0, &h->transtable->RepQAddr[i].upper);
072b0518 7230 writel(h->reply_queue[i].busaddr,
254f796b
MG		 7231 &h->transtable->RepQAddr[i].lower);
7232 }
7233
b9af4937 7234 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
e1f7de0c
MG		 7235 writel(transMethod, &(h->cfgtable->HostWrite.TransportRequest));
7236 /*
7237 * enable outbound interrupt coalescing in accelerator mode;
7238 */
7239 if (trans_support & CFGTBL_Trans_io_accel1) {
7240 access = SA5_ioaccel_mode1_access;
7241 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
7242 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
c349775e
ST		 7243 } else {
7244 if (trans_support & CFGTBL_Trans_io_accel2) {
7245 access = SA5_ioaccel_mode2_access;
7246 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
7247 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
7248 }
e1f7de0c 7249 }
303932fd 7250 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
3f4336f3 7251 hpsa_wait_for_mode_change_ack(h);
303932fd
DB		 7252 register_value = readl(&(h->cfgtable->TransportActive));
7253 if (!(register_value & CFGTBL_Trans_Performant)) {
050f7147
SC		 7254 dev_err(&h->pdev->dev,
7255 "performant mode problem - transport not active\n");
303932fd
DB		 7256 return;
7257 }
960a30e7 7258 /* Change the access methods to the performant access methods */
e1f7de0c
MG		 7259 h->access = access;
7260 h->transMethod = transMethod;
7261
b9af4937
SC		 7262 if (!((trans_support & CFGTBL_Trans_io_accel1) ||
7263 (trans_support & CFGTBL_Trans_io_accel2)))
e1f7de0c
MG		 7264 return;
7265
b9af4937
SC		 7266 if (trans_support & CFGTBL_Trans_io_accel1) {
7267 /* Set up I/O accelerator mode */
7268 for (i = 0; i < h->nreply_queues; i++) {
7269 writel(i, h->vaddr + IOACCEL_MODE1_REPLY_QUEUE_INDEX);
7270 h->reply_queue[i].current_entry =
7271 readl(h->vaddr + IOACCEL_MODE1_PRODUCER_INDEX);
7272 }
7273 bft[7] = h->ioaccel_maxsg + 8;
7274 calc_bucket_map(bft, ARRAY_SIZE(bft), h->ioaccel_maxsg, 8,
7275 h->ioaccel1_blockFetchTable);
e1f7de0c 7276
b9af4937 7277 /* initialize all reply queue entries to unused */
072b0518
SC		 7278 for (i = 0; i < h->nreply_queues; i++)
7279 memset(h->reply_queue[i].head,
7280 (u8) IOACCEL_MODE1_REPLY_UNUSED,
7281 h->reply_queue_size);
e1f7de0c 7282
b9af4937
SC		 7283 /* set all the constant fields in the accelerator command
7284 * frames once at init time to save CPU cycles later.
7285 */
7286 for (i = 0; i < h->nr_cmds; i++) {
7287 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[i];
7288
7289 cp->function = IOACCEL1_FUNCTION_SCSIIO;
7290 cp->err_info = (u32) (h->errinfo_pool_dhandle +
7291 (i * sizeof(struct ErrorInfo)));
7292 cp->err_info_len = sizeof(struct ErrorInfo);
7293 cp->sgl_offset = IOACCEL1_SGLOFFSET;
2b08b3e9
DB		 7294 cp->host_context_flags =
7295 cpu_to_le16(IOACCEL1_HCFLAGS_CISS_FORMAT);
b9af4937
SC		 7296 cp->timeout_sec = 0;
7297 cp->ReplyQueue = 0;
50a0decf
SC		 7298 cp->tag =
7299 cpu_to_le64((i << DIRECT_LOOKUP_SHIFT) |
7300 DIRECT_LOOKUP_BIT);
7301 cp->host_addr =
7302 cpu_to_le64(h->ioaccel_cmd_pool_dhandle +
b9af4937 7303 (i * sizeof(struct io_accel1_cmd)));
b9af4937
SC		 7304 }
7305 } else if (trans_support & CFGTBL_Trans_io_accel2) {
7306 u64 cfg_offset, cfg_base_addr_index;
7307 u32 bft2_offset, cfg_base_addr;
7308 int rc;
7309
7310 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
7311 &cfg_base_addr_index, &cfg_offset);
7312 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) != 64);
7313 bft2[15] = h->ioaccel_maxsg + HPSA_IOACCEL2_HEADER_SZ;
7314 calc_bucket_map(bft2, ARRAY_SIZE(bft2), h->ioaccel_maxsg,
7315 4, h->ioaccel2_blockFetchTable);
7316 bft2_offset = readl(&h->cfgtable->io_accel_request_size_offset);
7317 BUILD_BUG_ON(offsetof(struct CfgTable,
7318 io_accel_request_size_offset) != 0xb8);
7319 h->ioaccel2_bft2_regs =
7320 remap_pci_mem(pci_resource_start(h->pdev,
7321 cfg_base_addr_index) +
7322 cfg_offset + bft2_offset,
7323 ARRAY_SIZE(bft2) *
7324 sizeof(*h->ioaccel2_bft2_regs));
7325 for (i = 0; i < ARRAY_SIZE(bft2); i++)
7326 writel(bft2[i], &h->ioaccel2_bft2_regs[i]);
e1f7de0c 7327 }
b9af4937
SC		 7328 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
7329 hpsa_wait_for_mode_change_ack(h);
e1f7de0c
MG		 7330}
7331
7332static int hpsa_alloc_ioaccel_cmd_and_bft(struct ctlr_info *h)
7333{
283b4a9b
SC		 7334 h->ioaccel_maxsg =
7335 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
7336 if (h->ioaccel_maxsg > IOACCEL1_MAXSGENTRIES)
7337 h->ioaccel_maxsg = IOACCEL1_MAXSGENTRIES;
7338
e1f7de0c
MG		 7339 /* Command structures must be aligned on a 128-byte boundary
7340 * because the 7 lower bits of the address are used by the
7341 * hardware.
7342 */
e1f7de0c
MG		 7343 BUILD_BUG_ON(sizeof(struct io_accel1_cmd) %
7344 IOACCEL1_COMMANDLIST_ALIGNMENT);
7345 h->ioaccel_cmd_pool =
7346 pci_alloc_consistent(h->pdev,
7347 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
7348 &(h->ioaccel_cmd_pool_dhandle));
7349
7350 h->ioaccel1_blockFetchTable =
283b4a9b 7351 kmalloc(((h->ioaccel_maxsg + 1) *
e1f7de0c
MG		 7352 sizeof(u32)), GFP_KERNEL);
7353
7354 if ((h->ioaccel_cmd_pool == NULL) ||
7355 (h->ioaccel1_blockFetchTable == NULL))
7356 goto clean_up;
7357
7358 memset(h->ioaccel_cmd_pool, 0,
7359 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool));
7360 return 0;
7361
7362clean_up:
7363 if (h->ioaccel_cmd_pool)
7364 pci_free_consistent(h->pdev,
7365 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
7366 h->ioaccel_cmd_pool, h->ioaccel_cmd_pool_dhandle);
7367 kfree(h->ioaccel1_blockFetchTable);
7368 return 1;
6c311b57
SC		 7369}
7370
aca9012a
SC		 7371static int ioaccel2_alloc_cmds_and_bft(struct ctlr_info *h)
7372{
7373 /* Allocate ioaccel2 mode command blocks and block fetch table */
7374
7375 h->ioaccel_maxsg =
7376 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
7377 if (h->ioaccel_maxsg > IOACCEL2_MAXSGENTRIES)
7378 h->ioaccel_maxsg = IOACCEL2_MAXSGENTRIES;
7379
aca9012a
SC		 7380 BUILD_BUG_ON(sizeof(struct io_accel2_cmd) %
7381 IOACCEL2_COMMANDLIST_ALIGNMENT);
7382 h->ioaccel2_cmd_pool =
7383 pci_alloc_consistent(h->pdev,
7384 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
7385 &(h->ioaccel2_cmd_pool_dhandle));
7386
7387 h->ioaccel2_blockFetchTable =
7388 kmalloc(((h->ioaccel_maxsg + 1) *
7389 sizeof(u32)), GFP_KERNEL);
7390
7391 if ((h->ioaccel2_cmd_pool == NULL) ||
7392 (h->ioaccel2_blockFetchTable == NULL))
7393 goto clean_up;
7394
7395 memset(h->ioaccel2_cmd_pool, 0,
7396 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool));
7397 return 0;
7398
7399clean_up:
7400 if (h->ioaccel2_cmd_pool)
7401 pci_free_consistent(h->pdev,
7402 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
7403 h->ioaccel2_cmd_pool, h->ioaccel2_cmd_pool_dhandle);
7404 kfree(h->ioaccel2_blockFetchTable);
7405 return 1;
7406}
7407
6f039790 7408static void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h)
6c311b57
SC		 7409{
7410 u32 trans_support;
e1f7de0c
MG		 7411 unsigned long transMethod = CFGTBL_Trans_Performant |
7412 CFGTBL_Trans_use_short_tags;
254f796b 7413 int i;
6c311b57 7414
02ec19c8
SC		 7415 if (hpsa_simple_mode)
7416 return;
7417
67c99a72 7418 trans_support = readl(&(h->cfgtable->TransportSupport));
7419 if (!(trans_support & PERFORMANT_MODE))
7420 return;
7421
e1f7de0c
MG		 7422 /* Check for I/O accelerator mode support */
7423 if (trans_support & CFGTBL_Trans_io_accel1) {
7424 transMethod |= CFGTBL_Trans_io_accel1 |
7425 CFGTBL_Trans_enable_directed_msix;
7426 if (hpsa_alloc_ioaccel_cmd_and_bft(h))
7427 goto clean_up;
aca9012a
SC		 7428 } else {
7429 if (trans_support & CFGTBL_Trans_io_accel2) {
7430 transMethod |= CFGTBL_Trans_io_accel2 |
7431 CFGTBL_Trans_enable_directed_msix;
7432 if (ioaccel2_alloc_cmds_and_bft(h))
7433 goto clean_up;
7434 }
e1f7de0c
MG		 7435 }
7436
eee0f03a 7437 h->nreply_queues = h->msix_vector > 0 ? h->msix_vector : 1;
cba3d38b 7438 hpsa_get_max_perf_mode_cmds(h);
6c311b57 7439 /* Performant mode ring buffer and supporting data structures */
072b0518 7440 h->reply_queue_size = h->max_commands * sizeof(u64);
6c311b57 7441
254f796b 7442 for (i = 0; i < h->nreply_queues; i++) {
072b0518
SC		 7443 h->reply_queue[i].head = pci_alloc_consistent(h->pdev,
7444 h->reply_queue_size,
7445 &(h->reply_queue[i].busaddr));
7446 if (!h->reply_queue[i].head)
7447 goto clean_up;
254f796b
MG		 7448 h->reply_queue[i].size = h->max_commands;
7449 h->reply_queue[i].wraparound = 1; /* spec: init to 1 */
7450 h->reply_queue[i].current_entry = 0;
7451 }
7452
6c311b57 7453 /* Need a block fetch table for performant mode */
d66ae08b 7454 h->blockFetchTable = kmalloc(((SG_ENTRIES_IN_CMD + 1) *
6c311b57 7455 sizeof(u32)), GFP_KERNEL);
072b0518 7456 if (!h->blockFetchTable)
6c311b57
SC		 7457 goto clean_up;
7458
e1f7de0c 7459 hpsa_enter_performant_mode(h, trans_support);
303932fd
DB		 7460 return;
7461
7462clean_up:
072b0518 7463 hpsa_free_reply_queues(h);
303932fd
DB		 7464 kfree(h->blockFetchTable);
7465}
7466
23100dd9 7467static int is_accelerated_cmd(struct CommandList *c)
76438d08 7468{
23100dd9
SC		 7469 return c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_IOACCEL2;
7470}
7471
7472static void hpsa_drain_accel_commands(struct ctlr_info *h)
7473{
7474 struct CommandList *c = NULL;
76438d08 7475 unsigned long flags;
23100dd9 7476 int accel_cmds_out;
76438d08
SC		 7477
7478 do { /* wait for all outstanding commands to drain out */
23100dd9 7479 accel_cmds_out = 0;
76438d08 7480 spin_lock_irqsave(&h->lock, flags);
23100dd9
SC		 7481 list_for_each_entry(c, &h->cmpQ, list)
7482 accel_cmds_out += is_accelerated_cmd(c);
7483 list_for_each_entry(c, &h->reqQ, list)
7484 accel_cmds_out += is_accelerated_cmd(c);
76438d08 7485 spin_unlock_irqrestore(&h->lock, flags);
23100dd9 7486 if (accel_cmds_out <= 0)
76438d08
SC		 7487 break;
7488 msleep(100);
7489 } while (1);
7490}
7491
edd16368
SC		 7492/*
7493 * This is it. Register the PCI driver information for the cards we control
7494 * the OS will call our registered routines when it finds one of our cards.
7495 */
7496static int __init hpsa_init(void)
7497{
31468401 7498 return pci_register_driver(&hpsa_pci_driver);
edd16368
SC		 7499}
7500
7501static void __exit hpsa_cleanup(void)
7502{
7503 pci_unregister_driver(&hpsa_pci_driver);
edd16368
SC		 7504}
7505
e1f7de0c
MG		 7506static void __attribute__((unused)) verify_offsets(void)
7507{
dd0e19f3
ST		 7508#define VERIFY_OFFSET(member, offset) \
7509 BUILD_BUG_ON(offsetof(struct raid_map_data, member) != offset)
7510
7511 VERIFY_OFFSET(structure_size, 0);
7512 VERIFY_OFFSET(volume_blk_size, 4);
7513 VERIFY_OFFSET(volume_blk_cnt, 8);
7514 VERIFY_OFFSET(phys_blk_shift, 16);
7515 VERIFY_OFFSET(parity_rotation_shift, 17);
7516 VERIFY_OFFSET(strip_size, 18);
7517 VERIFY_OFFSET(disk_starting_blk, 20);
7518 VERIFY_OFFSET(disk_blk_cnt, 28);
7519 VERIFY_OFFSET(data_disks_per_row, 36);
7520 VERIFY_OFFSET(metadata_disks_per_row, 38);
7521 VERIFY_OFFSET(row_cnt, 40);
7522 VERIFY_OFFSET(layout_map_count, 42);
7523 VERIFY_OFFSET(flags, 44);
7524 VERIFY_OFFSET(dekindex, 46);
7525 /* VERIFY_OFFSET(reserved, 48 */
7526 VERIFY_OFFSET(data, 64);
7527
7528#undef VERIFY_OFFSET
7529
b66cc250
MM		 7530#define VERIFY_OFFSET(member, offset) \
7531 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, member) != offset)
7532
7533 VERIFY_OFFSET(IU_type, 0);
7534 VERIFY_OFFSET(direction, 1);
7535 VERIFY_OFFSET(reply_queue, 2);
7536 /* VERIFY_OFFSET(reserved1, 3); */
7537 VERIFY_OFFSET(scsi_nexus, 4);
7538 VERIFY_OFFSET(Tag, 8);
7539 VERIFY_OFFSET(cdb, 16);
7540 VERIFY_OFFSET(cciss_lun, 32);
7541 VERIFY_OFFSET(data_len, 40);
7542 VERIFY_OFFSET(cmd_priority_task_attr, 44);
7543 VERIFY_OFFSET(sg_count, 45);
7544 /* VERIFY_OFFSET(reserved3 */
7545 VERIFY_OFFSET(err_ptr, 48);
7546 VERIFY_OFFSET(err_len, 56);
7547 /* VERIFY_OFFSET(reserved4 */
7548 VERIFY_OFFSET(sg, 64);
7549
7550#undef VERIFY_OFFSET
7551
e1f7de0c
MG		 7552#define VERIFY_OFFSET(member, offset) \
7553 BUILD_BUG_ON(offsetof(struct io_accel1_cmd, member) != offset)
7554
7555 VERIFY_OFFSET(dev_handle, 0x00);
7556 VERIFY_OFFSET(reserved1, 0x02);
7557 VERIFY_OFFSET(function, 0x03);
7558 VERIFY_OFFSET(reserved2, 0x04);
7559 VERIFY_OFFSET(err_info, 0x0C);
7560 VERIFY_OFFSET(reserved3, 0x10);
7561 VERIFY_OFFSET(err_info_len, 0x12);
7562 VERIFY_OFFSET(reserved4, 0x13);
7563 VERIFY_OFFSET(sgl_offset, 0x14);
7564 VERIFY_OFFSET(reserved5, 0x15);
7565 VERIFY_OFFSET(transfer_len, 0x1C);
7566 VERIFY_OFFSET(reserved6, 0x20);
7567 VERIFY_OFFSET(io_flags, 0x24);
7568 VERIFY_OFFSET(reserved7, 0x26);
7569 VERIFY_OFFSET(LUN, 0x34);
7570 VERIFY_OFFSET(control, 0x3C);
7571 VERIFY_OFFSET(CDB, 0x40);
7572 VERIFY_OFFSET(reserved8, 0x50);
7573 VERIFY_OFFSET(host_context_flags, 0x60);
7574 VERIFY_OFFSET(timeout_sec, 0x62);
7575 VERIFY_OFFSET(ReplyQueue, 0x64);
7576 VERIFY_OFFSET(reserved9, 0x65);
50a0decf 7577 VERIFY_OFFSET(tag, 0x68);
e1f7de0c
MG		 7578 VERIFY_OFFSET(host_addr, 0x70);
7579 VERIFY_OFFSET(CISS_LUN, 0x78);
7580 VERIFY_OFFSET(SG, 0x78 + 8);
7581#undef VERIFY_OFFSET
7582}
7583
edd16368
SC		 7584module_init(hpsa_init);
7585module_exit(hpsa_cleanup);
Linux kernel - Deliverables
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