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hpsa: do not queue commands internally in driver
[deliverable/linux.git] / drivers / scsi / hpsa.c
CommitLineData
edd16368
SC		 1/*
2 * Disk Array driver for HP Smart Array SAS controllers
51c35139 3 * Copyright 2000, 2014 Hewlett-Packard Development Company, L.P.
edd16368
SC		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
12 * NON INFRINGEMENT. See the GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 *
18 * Questions/Comments/Bugfixes to iss_storagedev@hp.com
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/interrupt.h>
24#include <linux/types.h>
25#include <linux/pci.h>
e5a44df8 26#include <linux/pci-aspm.h>
edd16368
SC		 27#include <linux/kernel.h>
28#include <linux/slab.h>
29#include <linux/delay.h>
30#include <linux/fs.h>
31#include <linux/timer.h>
edd16368
SC		 32#include <linux/init.h>
33#include <linux/spinlock.h>
edd16368
SC		 34#include <linux/compat.h>
35#include <linux/blktrace_api.h>
36#include <linux/uaccess.h>
37#include <linux/io.h>
38#include <linux/dma-mapping.h>
39#include <linux/completion.h>
40#include <linux/moduleparam.h>
41#include <scsi/scsi.h>
42#include <scsi/scsi_cmnd.h>
43#include <scsi/scsi_device.h>
44#include <scsi/scsi_host.h>
667e23d4 45#include <scsi/scsi_tcq.h>
edd16368
SC		 46#include <linux/cciss_ioctl.h>
47#include <linux/string.h>
48#include <linux/bitmap.h>
60063497 49#include <linux/atomic.h>
a0c12413 50#include <linux/jiffies.h>
42a91641 51#include <linux/percpu-defs.h>
094963da 52#include <linux/percpu.h>
2b08b3e9 53#include <asm/unaligned.h>
283b4a9b 54#include <asm/div64.h>
edd16368
SC		 55#include "hpsa_cmd.h"
56#include "hpsa.h"
57
58/* HPSA_DRIVER_VERSION must be 3 byte values (0-255) separated by '.' */
9a993302 59#define HPSA_DRIVER_VERSION "3.4.4-1"
edd16368 60#define DRIVER_NAME "HP HPSA Driver (v " HPSA_DRIVER_VERSION ")"
f79cfec6 61#define HPSA "hpsa"
edd16368
SC		 62
63/* How long to wait (in milliseconds) for board to go into simple mode */
64#define MAX_CONFIG_WAIT 30000
65#define MAX_IOCTL_CONFIG_WAIT 1000
66
67/*define how many times we will try a command because of bus resets */
68#define MAX_CMD_RETRIES 3
69
70/* Embedded module documentation macros - see modules.h */
71MODULE_AUTHOR("Hewlett-Packard Company");
72MODULE_DESCRIPTION("Driver for HP Smart Array Controller version " \
73 HPSA_DRIVER_VERSION);
74MODULE_SUPPORTED_DEVICE("HP Smart Array Controllers");
75MODULE_VERSION(HPSA_DRIVER_VERSION);
76MODULE_LICENSE("GPL");
77
78static int hpsa_allow_any;
79module_param(hpsa_allow_any, int, S_IRUGO|S_IWUSR);
80MODULE_PARM_DESC(hpsa_allow_any,
81 "Allow hpsa driver to access unknown HP Smart Array hardware");
02ec19c8
SC		 82static int hpsa_simple_mode;
83module_param(hpsa_simple_mode, int, S_IRUGO|S_IWUSR);
84MODULE_PARM_DESC(hpsa_simple_mode,
85 "Use 'simple mode' rather than 'performant mode'");
edd16368
SC		 86
87/* define the PCI info for the cards we can control */
88static const struct pci_device_id hpsa_pci_device_id[] = {
edd16368
SC		 89 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3241},
90 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3243},
91 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3245},
92 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3247},
93 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3249},
163dbcd8
MM		 94 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324A},
95 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324B},
f8b01eb9 96 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3233},
9143a961 97 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3350},
98 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3351},
99 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3352},
100 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3353},
101 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3354},
102 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3355},
103 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3356},
fe0c9610
MM		 104 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1921},
105 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1922},
106 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1923},
107 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1924},
fe0c9610
MM		 108 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1926},
109 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1928},
97b9f53d
MM		 110 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1929},
111 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BD},
112 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BE},
113 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BF},
114 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C0},
115 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C1},
116 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C2},
117 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C3},
118 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C4},
119 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C5},
3b7a45e5 120 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C6},
97b9f53d
MM		 121 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C7},
122 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C8},
123 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C9},
3b7a45e5
JH		 124 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CA},
125 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CB},
126 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CC},
127 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CD},
128 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CE},
8e616a5e
SC		 129 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0076},
130 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0087},
131 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x007D},
132 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0088},
133 {PCI_VENDOR_ID_HP, 0x333f, 0x103c, 0x333f},
7c03b870 134 {PCI_VENDOR_ID_HP, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
6798cc0a 135 PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0},
edd16368
SC		 136 {0,}
137};
138
139MODULE_DEVICE_TABLE(pci, hpsa_pci_device_id);
140
141/* board_id = Subsystem Device ID & Vendor ID
142 * product = Marketing Name for the board
143 * access = Address of the struct of function pointers
144 */
145static struct board_type products[] = {
edd16368
SC		 146 {0x3241103C, "Smart Array P212", &SA5_access},
147 {0x3243103C, "Smart Array P410", &SA5_access},
148 {0x3245103C, "Smart Array P410i", &SA5_access},
149 {0x3247103C, "Smart Array P411", &SA5_access},
150 {0x3249103C, "Smart Array P812", &SA5_access},
163dbcd8
MM		 151 {0x324A103C, "Smart Array P712m", &SA5_access},
152 {0x324B103C, "Smart Array P711m", &SA5_access},
7d2cce58 153 {0x3233103C, "HP StorageWorks 1210m", &SA5_access}, /* alias of 333f */
fe0c9610
MM		 154 {0x3350103C, "Smart Array P222", &SA5_access},
155 {0x3351103C, "Smart Array P420", &SA5_access},
156 {0x3352103C, "Smart Array P421", &SA5_access},
157 {0x3353103C, "Smart Array P822", &SA5_access},
158 {0x3354103C, "Smart Array P420i", &SA5_access},
159 {0x3355103C, "Smart Array P220i", &SA5_access},
160 {0x3356103C, "Smart Array P721m", &SA5_access},
1fd6c8e3
MM		 161 {0x1921103C, "Smart Array P830i", &SA5_access},
162 {0x1922103C, "Smart Array P430", &SA5_access},
163 {0x1923103C, "Smart Array P431", &SA5_access},
164 {0x1924103C, "Smart Array P830", &SA5_access},
165 {0x1926103C, "Smart Array P731m", &SA5_access},
166 {0x1928103C, "Smart Array P230i", &SA5_access},
167 {0x1929103C, "Smart Array P530", &SA5_access},
97b9f53d
MM		 168 {0x21BD103C, "Smart Array", &SA5_access},
169 {0x21BE103C, "Smart Array", &SA5_access},
170 {0x21BF103C, "Smart Array", &SA5_access},
171 {0x21C0103C, "Smart Array", &SA5_access},
172 {0x21C1103C, "Smart Array", &SA5_access},
173 {0x21C2103C, "Smart Array", &SA5_access},
174 {0x21C3103C, "Smart Array", &SA5_access},
175 {0x21C4103C, "Smart Array", &SA5_access},
176 {0x21C5103C, "Smart Array", &SA5_access},
3b7a45e5 177 {0x21C6103C, "Smart Array", &SA5_access},
97b9f53d
MM		 178 {0x21C7103C, "Smart Array", &SA5_access},
179 {0x21C8103C, "Smart Array", &SA5_access},
180 {0x21C9103C, "Smart Array", &SA5_access},
3b7a45e5
JH		 181 {0x21CA103C, "Smart Array", &SA5_access},
182 {0x21CB103C, "Smart Array", &SA5_access},
183 {0x21CC103C, "Smart Array", &SA5_access},
184 {0x21CD103C, "Smart Array", &SA5_access},
185 {0x21CE103C, "Smart Array", &SA5_access},
8e616a5e
SC		 186 {0x00761590, "HP Storage P1224 Array Controller", &SA5_access},
187 {0x00871590, "HP Storage P1224e Array Controller", &SA5_access},
188 {0x007D1590, "HP Storage P1228 Array Controller", &SA5_access},
189 {0x00881590, "HP Storage P1228e Array Controller", &SA5_access},
190 {0x333f103c, "HP StorageWorks 1210m Array Controller", &SA5_access},
edd16368
SC		 191 {0xFFFF103C, "Unknown Smart Array", &SA5_access},
192};
193
194static int number_of_controllers;
195
10f66018
SC		 196static irqreturn_t do_hpsa_intr_intx(int irq, void *dev_id);
197static irqreturn_t do_hpsa_intr_msi(int irq, void *dev_id);
42a91641 198static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg);
edd16368
SC		 199
200#ifdef CONFIG_COMPAT
42a91641
DB		 201static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd,
202 void __user *arg);
edd16368
SC		 203#endif
204
205static void cmd_free(struct ctlr_info *h, struct CommandList *c);
edd16368 206static struct CommandList *cmd_alloc(struct ctlr_info *h);
a2dac136 207static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
b7bb24eb 208 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
edd16368 209 int cmd_type);
2c143342 210static void hpsa_free_cmd_pool(struct ctlr_info *h);
b7bb24eb 211#define VPD_PAGE (1 << 8)
edd16368 212
f281233d 213static int hpsa_scsi_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd);
a08a8471
SC		 214static void hpsa_scan_start(struct Scsi_Host *);
215static int hpsa_scan_finished(struct Scsi_Host *sh,
216 unsigned long elapsed_time);
7c0a0229 217static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth);
edd16368
SC		 218
219static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd);
75167d2c 220static int hpsa_eh_abort_handler(struct scsi_cmnd *scsicmd);
edd16368
SC		 221static int hpsa_slave_alloc(struct scsi_device *sdev);
222static void hpsa_slave_destroy(struct scsi_device *sdev);
223
edd16368 224static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno);
edd16368
SC		 225static int check_for_unit_attention(struct ctlr_info *h,
226 struct CommandList *c);
227static void check_ioctl_unit_attention(struct ctlr_info *h,
228 struct CommandList *c);
303932fd
DB		 229/* performant mode helper functions */
230static void calc_bucket_map(int *bucket, int num_buckets,
2b08b3e9 231 int nsgs, int min_blocks, u32 *bucket_map);
6f039790 232static void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h);
254f796b 233static inline u32 next_command(struct ctlr_info *h, u8 q);
6f039790
GKH		 234static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
235 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
236 u64 *cfg_offset);
237static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
238 unsigned long *memory_bar);
239static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id);
240static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
241 int wait_for_ready);
75167d2c 242static inline void finish_cmd(struct CommandList *c);
283b4a9b 243static void hpsa_wait_for_mode_change_ack(struct ctlr_info *h);
fe5389c8
SC		 244#define BOARD_NOT_READY 0
245#define BOARD_READY 1
23100dd9 246static void hpsa_drain_accel_commands(struct ctlr_info *h);
76438d08 247static void hpsa_flush_cache(struct ctlr_info *h);
c349775e
ST		 248static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
249 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
250 u8 *scsi3addr);
edd16368 251
edd16368
SC		 252static inline struct ctlr_info *sdev_to_hba(struct scsi_device *sdev)
253{
254 unsigned long *priv = shost_priv(sdev->host);
255 return (struct ctlr_info *) *priv;
256}
257
a23513e8
SC		 258static inline struct ctlr_info *shost_to_hba(struct Scsi_Host *sh)
259{
260 unsigned long *priv = shost_priv(sh);
261 return (struct ctlr_info *) *priv;
262}
263
edd16368
SC		 264static int check_for_unit_attention(struct ctlr_info *h,
265 struct CommandList *c)
266{
267 if (c->err_info->SenseInfo[2] != UNIT_ATTENTION)
268 return 0;
269
270 switch (c->err_info->SenseInfo[12]) {
271 case STATE_CHANGED:
f79cfec6 272 dev_warn(&h->pdev->dev, HPSA "%d: a state change "
edd16368
SC		 273 "detected, command retried\n", h->ctlr);
274 break;
275 case LUN_FAILED:
7f73695a
SC		 276 dev_warn(&h->pdev->dev,
277 HPSA "%d: LUN failure detected\n", h->ctlr);
edd16368
SC		 278 break;
279 case REPORT_LUNS_CHANGED:
7f73695a
SC		 280 dev_warn(&h->pdev->dev,
281 HPSA "%d: report LUN data changed\n", h->ctlr);
edd16368 282 /*
4f4eb9f1
ST		 283 * Note: this REPORT_LUNS_CHANGED condition only occurs on the external
284 * target (array) devices.
edd16368
SC		 285 */
286 break;
287 case POWER_OR_RESET:
f79cfec6 288 dev_warn(&h->pdev->dev, HPSA "%d: a power on "
edd16368
SC		 289 "or device reset detected\n", h->ctlr);
290 break;
291 case UNIT_ATTENTION_CLEARED:
f79cfec6 292 dev_warn(&h->pdev->dev, HPSA "%d: unit attention "
edd16368
SC		 293 "cleared by another initiator\n", h->ctlr);
294 break;
295 default:
f79cfec6 296 dev_warn(&h->pdev->dev, HPSA "%d: unknown "
edd16368
SC		 297 "unit attention detected\n", h->ctlr);
298 break;
299 }
300 return 1;
301}
302
852af20a
MB		 303static int check_for_busy(struct ctlr_info *h, struct CommandList *c)
304{
305 if (c->err_info->CommandStatus != CMD_TARGET_STATUS ||
306 (c->err_info->ScsiStatus != SAM_STAT_BUSY &&
307 c->err_info->ScsiStatus != SAM_STAT_TASK_SET_FULL))
308 return 0;
309 dev_warn(&h->pdev->dev, HPSA "device busy");
310 return 1;
311}
312
da0697bd
ST		 313static ssize_t host_store_hp_ssd_smart_path_status(struct device *dev,
314 struct device_attribute *attr,
315 const char *buf, size_t count)
316{
317 int status, len;
318 struct ctlr_info *h;
319 struct Scsi_Host *shost = class_to_shost(dev);
320 char tmpbuf[10];
321
322 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
323 return -EACCES;
324 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
325 strncpy(tmpbuf, buf, len);
326 tmpbuf[len] = '\0';
327 if (sscanf(tmpbuf, "%d", &status) != 1)
328 return -EINVAL;
329 h = shost_to_hba(shost);
330 h->acciopath_status = !!status;
331 dev_warn(&h->pdev->dev,
332 "hpsa: HP SSD Smart Path %s via sysfs update.\n",
333 h->acciopath_status ? "enabled" : "disabled");
334 return count;
335}
336
2ba8bfc8
SC		 337static ssize_t host_store_raid_offload_debug(struct device *dev,
338 struct device_attribute *attr,
339 const char *buf, size_t count)
340{
341 int debug_level, len;
342 struct ctlr_info *h;
343 struct Scsi_Host *shost = class_to_shost(dev);
344 char tmpbuf[10];
345
346 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
347 return -EACCES;
348 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
349 strncpy(tmpbuf, buf, len);
350 tmpbuf[len] = '\0';
351 if (sscanf(tmpbuf, "%d", &debug_level) != 1)
352 return -EINVAL;
353 if (debug_level < 0)
354 debug_level = 0;
355 h = shost_to_hba(shost);
356 h->raid_offload_debug = debug_level;
357 dev_warn(&h->pdev->dev, "hpsa: Set raid_offload_debug level = %d\n",
358 h->raid_offload_debug);
359 return count;
360}
361
edd16368
SC		 362static ssize_t host_store_rescan(struct device *dev,
363 struct device_attribute *attr,
364 const char *buf, size_t count)
365{
366 struct ctlr_info *h;
367 struct Scsi_Host *shost = class_to_shost(dev);
a23513e8 368 h = shost_to_hba(shost);
31468401 369 hpsa_scan_start(h->scsi_host);
edd16368
SC		 370 return count;
371}
372
d28ce020
SC		 373static ssize_t host_show_firmware_revision(struct device *dev,
374 struct device_attribute *attr, char *buf)
375{
376 struct ctlr_info *h;
377 struct Scsi_Host *shost = class_to_shost(dev);
378 unsigned char *fwrev;
379
380 h = shost_to_hba(shost);
381 if (!h->hba_inquiry_data)
382 return 0;
383 fwrev = &h->hba_inquiry_data[32];
384 return snprintf(buf, 20, "%c%c%c%c\n",
385 fwrev[0], fwrev[1], fwrev[2], fwrev[3]);
386}
387
94a13649
SC		 388static ssize_t host_show_commands_outstanding(struct device *dev,
389 struct device_attribute *attr, char *buf)
390{
391 struct Scsi_Host *shost = class_to_shost(dev);
392 struct ctlr_info *h = shost_to_hba(shost);
393
0cbf768e
SC		 394 return snprintf(buf, 20, "%d\n",
395 atomic_read(&h->commands_outstanding));
94a13649
SC		 396}
397
745a7a25
SC		 398static ssize_t host_show_transport_mode(struct device *dev,
399 struct device_attribute *attr, char *buf)
400{
401 struct ctlr_info *h;
402 struct Scsi_Host *shost = class_to_shost(dev);
403
404 h = shost_to_hba(shost);
405 return snprintf(buf, 20, "%s\n",
960a30e7 406 h->transMethod & CFGTBL_Trans_Performant ?
745a7a25
SC		 407 "performant" : "simple");
408}
409
da0697bd
ST		 410static ssize_t host_show_hp_ssd_smart_path_status(struct device *dev,
411 struct device_attribute *attr, char *buf)
412{
413 struct ctlr_info *h;
414 struct Scsi_Host *shost = class_to_shost(dev);
415
416 h = shost_to_hba(shost);
417 return snprintf(buf, 30, "HP SSD Smart Path %s\n",
418 (h->acciopath_status == 1) ? "enabled" : "disabled");
419}
420
46380786 421/* List of controllers which cannot be hard reset on kexec with reset_devices */
941b1cda
SC		 422static u32 unresettable_controller[] = {
423 0x324a103C, /* Smart Array P712m */
424 0x324b103C, /* SmartArray P711m */
425 0x3223103C, /* Smart Array P800 */
426 0x3234103C, /* Smart Array P400 */
427 0x3235103C, /* Smart Array P400i */
428 0x3211103C, /* Smart Array E200i */
429 0x3212103C, /* Smart Array E200 */
430 0x3213103C, /* Smart Array E200i */
431 0x3214103C, /* Smart Array E200i */
432 0x3215103C, /* Smart Array E200i */
433 0x3237103C, /* Smart Array E500 */
434 0x323D103C, /* Smart Array P700m */
7af0abbc 435 0x40800E11, /* Smart Array 5i */
941b1cda
SC		 436 0x409C0E11, /* Smart Array 6400 */
437 0x409D0E11, /* Smart Array 6400 EM */
5a4f934e
TH		 438 0x40700E11, /* Smart Array 5300 */
439 0x40820E11, /* Smart Array 532 */
440 0x40830E11, /* Smart Array 5312 */
441 0x409A0E11, /* Smart Array 641 */
442 0x409B0E11, /* Smart Array 642 */
443 0x40910E11, /* Smart Array 6i */
941b1cda
SC		 444};
445
46380786
SC		 446/* List of controllers which cannot even be soft reset */
447static u32 soft_unresettable_controller[] = {
7af0abbc 448 0x40800E11, /* Smart Array 5i */
5a4f934e
TH		 449 0x40700E11, /* Smart Array 5300 */
450 0x40820E11, /* Smart Array 532 */
451 0x40830E11, /* Smart Array 5312 */
452 0x409A0E11, /* Smart Array 641 */
453 0x409B0E11, /* Smart Array 642 */
454 0x40910E11, /* Smart Array 6i */
46380786
SC		 455 /* Exclude 640x boards. These are two pci devices in one slot
456 * which share a battery backed cache module. One controls the
457 * cache, the other accesses the cache through the one that controls
458 * it. If we reset the one controlling the cache, the other will
459 * likely not be happy. Just forbid resetting this conjoined mess.
460 * The 640x isn't really supported by hpsa anyway.
461 */
462 0x409C0E11, /* Smart Array 6400 */
463 0x409D0E11, /* Smart Array 6400 EM */
464};
465
466static int ctlr_is_hard_resettable(u32 board_id)
941b1cda
SC		 467{
468 int i;
469
470 for (i = 0; i < ARRAY_SIZE(unresettable_controller); i++)
46380786
SC		 471 if (unresettable_controller[i] == board_id)
472 return 0;
473 return 1;
474}
475
476static int ctlr_is_soft_resettable(u32 board_id)
477{
478 int i;
479
480 for (i = 0; i < ARRAY_SIZE(soft_unresettable_controller); i++)
481 if (soft_unresettable_controller[i] == board_id)
941b1cda
SC		 482 return 0;
483 return 1;
484}
485
46380786
SC		 486static int ctlr_is_resettable(u32 board_id)
487{
488 return ctlr_is_hard_resettable(board_id) ||
489 ctlr_is_soft_resettable(board_id);
490}
491
941b1cda
SC		 492static ssize_t host_show_resettable(struct device *dev,
493 struct device_attribute *attr, char *buf)
494{
495 struct ctlr_info *h;
496 struct Scsi_Host *shost = class_to_shost(dev);
497
498 h = shost_to_hba(shost);
46380786 499 return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h->board_id));
941b1cda
SC		 500}
501
edd16368
SC		 502static inline int is_logical_dev_addr_mode(unsigned char scsi3addr[])
503{
504 return (scsi3addr[3] & 0xC0) == 0x40;
505}
506
f2ef0ce7
RE		 507static const char * const raid_label[] = { "0", "4", "1(+0)", "5", "5+1", "6",
508 "1(+0)ADM", "UNKNOWN"
edd16368 509};
6b80b18f
ST		 510#define HPSA_RAID_0 0
511#define HPSA_RAID_4 1
512#define HPSA_RAID_1 2 /* also used for RAID 10 */
513#define HPSA_RAID_5 3 /* also used for RAID 50 */
514#define HPSA_RAID_51 4
515#define HPSA_RAID_6 5 /* also used for RAID 60 */
516#define HPSA_RAID_ADM 6 /* also used for RAID 1+0 ADM */
edd16368
SC		 517#define RAID_UNKNOWN (ARRAY_SIZE(raid_label) - 1)
518
519static ssize_t raid_level_show(struct device *dev,
520 struct device_attribute *attr, char *buf)
521{
522 ssize_t l = 0;
82a72c0a 523 unsigned char rlevel;
edd16368
SC		 524 struct ctlr_info *h;
525 struct scsi_device *sdev;
526 struct hpsa_scsi_dev_t *hdev;
527 unsigned long flags;
528
529 sdev = to_scsi_device(dev);
530 h = sdev_to_hba(sdev);
531 spin_lock_irqsave(&h->lock, flags);
532 hdev = sdev->hostdata;
533 if (!hdev) {
534 spin_unlock_irqrestore(&h->lock, flags);
535 return -ENODEV;
536 }
537
538 /* Is this even a logical drive? */
539 if (!is_logical_dev_addr_mode(hdev->scsi3addr)) {
540 spin_unlock_irqrestore(&h->lock, flags);
541 l = snprintf(buf, PAGE_SIZE, "N/A\n");
542 return l;
543 }
544
545 rlevel = hdev->raid_level;
546 spin_unlock_irqrestore(&h->lock, flags);
82a72c0a 547 if (rlevel > RAID_UNKNOWN)
edd16368
SC		 548 rlevel = RAID_UNKNOWN;
549 l = snprintf(buf, PAGE_SIZE, "RAID %s\n", raid_label[rlevel]);
550 return l;
551}
552
553static ssize_t lunid_show(struct device *dev,
554 struct device_attribute *attr, char *buf)
555{
556 struct ctlr_info *h;
557 struct scsi_device *sdev;
558 struct hpsa_scsi_dev_t *hdev;
559 unsigned long flags;
560 unsigned char lunid[8];
561
562 sdev = to_scsi_device(dev);
563 h = sdev_to_hba(sdev);
564 spin_lock_irqsave(&h->lock, flags);
565 hdev = sdev->hostdata;
566 if (!hdev) {
567 spin_unlock_irqrestore(&h->lock, flags);
568 return -ENODEV;
569 }
570 memcpy(lunid, hdev->scsi3addr, sizeof(lunid));
571 spin_unlock_irqrestore(&h->lock, flags);
572 return snprintf(buf, 20, "0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
573 lunid[0], lunid[1], lunid[2], lunid[3],
574 lunid[4], lunid[5], lunid[6], lunid[7]);
575}
576
577static ssize_t unique_id_show(struct device *dev,
578 struct device_attribute *attr, char *buf)
579{
580 struct ctlr_info *h;
581 struct scsi_device *sdev;
582 struct hpsa_scsi_dev_t *hdev;
583 unsigned long flags;
584 unsigned char sn[16];
585
586 sdev = to_scsi_device(dev);
587 h = sdev_to_hba(sdev);
588 spin_lock_irqsave(&h->lock, flags);
589 hdev = sdev->hostdata;
590 if (!hdev) {
591 spin_unlock_irqrestore(&h->lock, flags);
592 return -ENODEV;
593 }
594 memcpy(sn, hdev->device_id, sizeof(sn));
595 spin_unlock_irqrestore(&h->lock, flags);
596 return snprintf(buf, 16 * 2 + 2,
597 "%02X%02X%02X%02X%02X%02X%02X%02X"
598 "%02X%02X%02X%02X%02X%02X%02X%02X\n",
599 sn[0], sn[1], sn[2], sn[3],
600 sn[4], sn[5], sn[6], sn[7],
601 sn[8], sn[9], sn[10], sn[11],
602 sn[12], sn[13], sn[14], sn[15]);
603}
604
c1988684
ST		 605static ssize_t host_show_hp_ssd_smart_path_enabled(struct device *dev,
606 struct device_attribute *attr, char *buf)
607{
608 struct ctlr_info *h;
609 struct scsi_device *sdev;
610 struct hpsa_scsi_dev_t *hdev;
611 unsigned long flags;
612 int offload_enabled;
613
614 sdev = to_scsi_device(dev);
615 h = sdev_to_hba(sdev);
616 spin_lock_irqsave(&h->lock, flags);
617 hdev = sdev->hostdata;
618 if (!hdev) {
619 spin_unlock_irqrestore(&h->lock, flags);
620 return -ENODEV;
621 }
622 offload_enabled = hdev->offload_enabled;
623 spin_unlock_irqrestore(&h->lock, flags);
624 return snprintf(buf, 20, "%d\n", offload_enabled);
625}
626
3f5eac3a
SC		 627static DEVICE_ATTR(raid_level, S_IRUGO, raid_level_show, NULL);
628static DEVICE_ATTR(lunid, S_IRUGO, lunid_show, NULL);
629static DEVICE_ATTR(unique_id, S_IRUGO, unique_id_show, NULL);
630static DEVICE_ATTR(rescan, S_IWUSR, NULL, host_store_rescan);
c1988684
ST		 631static DEVICE_ATTR(hp_ssd_smart_path_enabled, S_IRUGO,
632 host_show_hp_ssd_smart_path_enabled, NULL);
da0697bd
ST		 633static DEVICE_ATTR(hp_ssd_smart_path_status, S_IWUSR|S_IRUGO|S_IROTH,
634 host_show_hp_ssd_smart_path_status,
635 host_store_hp_ssd_smart_path_status);
2ba8bfc8
SC		 636static DEVICE_ATTR(raid_offload_debug, S_IWUSR, NULL,
637 host_store_raid_offload_debug);
3f5eac3a
SC		 638static DEVICE_ATTR(firmware_revision, S_IRUGO,
639 host_show_firmware_revision, NULL);
640static DEVICE_ATTR(commands_outstanding, S_IRUGO,
641 host_show_commands_outstanding, NULL);
642static DEVICE_ATTR(transport_mode, S_IRUGO,
643 host_show_transport_mode, NULL);
941b1cda
SC		 644static DEVICE_ATTR(resettable, S_IRUGO,
645 host_show_resettable, NULL);
3f5eac3a
SC		 646
647static struct device_attribute *hpsa_sdev_attrs[] = {
648 &dev_attr_raid_level,
649 &dev_attr_lunid,
650 &dev_attr_unique_id,
c1988684 651 &dev_attr_hp_ssd_smart_path_enabled,
3f5eac3a
SC		 652 NULL,
653};
654
655static struct device_attribute *hpsa_shost_attrs[] = {
656 &dev_attr_rescan,
657 &dev_attr_firmware_revision,
658 &dev_attr_commands_outstanding,
659 &dev_attr_transport_mode,
941b1cda 660 &dev_attr_resettable,
da0697bd 661 &dev_attr_hp_ssd_smart_path_status,
2ba8bfc8 662 &dev_attr_raid_offload_debug,
3f5eac3a
SC		 663 NULL,
664};
665
666static struct scsi_host_template hpsa_driver_template = {
667 .module = THIS_MODULE,
f79cfec6
SC		 668 .name = HPSA,
669 .proc_name = HPSA,
3f5eac3a
SC		 670 .queuecommand = hpsa_scsi_queue_command,
671 .scan_start = hpsa_scan_start,
672 .scan_finished = hpsa_scan_finished,
7c0a0229 673 .change_queue_depth = hpsa_change_queue_depth,
3f5eac3a
SC		 674 .this_id = -1,
675 .use_clustering = ENABLE_CLUSTERING,
75167d2c 676 .eh_abort_handler = hpsa_eh_abort_handler,
3f5eac3a
SC		 677 .eh_device_reset_handler = hpsa_eh_device_reset_handler,
678 .ioctl = hpsa_ioctl,
679 .slave_alloc = hpsa_slave_alloc,
680 .slave_destroy = hpsa_slave_destroy,
681#ifdef CONFIG_COMPAT
682 .compat_ioctl = hpsa_compat_ioctl,
683#endif
684 .sdev_attrs = hpsa_sdev_attrs,
685 .shost_attrs = hpsa_shost_attrs,
c0d6a4d1 686 .max_sectors = 8192,
54b2b50c 687 .no_write_same = 1,
3f5eac3a
SC		 688};
689
254f796b 690static inline u32 next_command(struct ctlr_info *h, u8 q)
3f5eac3a
SC		 691{
692 u32 a;
072b0518 693 struct reply_queue_buffer *rq = &h->reply_queue[q];
3f5eac3a 694
e1f7de0c
MG		 695 if (h->transMethod & CFGTBL_Trans_io_accel1)
696 return h->access.command_completed(h, q);
697
3f5eac3a 698 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
254f796b 699 return h->access.command_completed(h, q);
3f5eac3a 700
254f796b
MG		 701 if ((rq->head[rq->current_entry] & 1) == rq->wraparound) {
702 a = rq->head[rq->current_entry];
703 rq->current_entry++;
0cbf768e 704 atomic_dec(&h->commands_outstanding);
3f5eac3a
SC		 705 } else {
706 a = FIFO_EMPTY;
707 }
708 /* Check for wraparound */
254f796b
MG		 709 if (rq->current_entry == h->max_commands) {
710 rq->current_entry = 0;
711 rq->wraparound ^= 1;
3f5eac3a
SC		 712 }
713 return a;
714}
715
c349775e
ST		 716/*
717 * There are some special bits in the bus address of the
718 * command that we have to set for the controller to know
719 * how to process the command:
720 *
721 * Normal performant mode:
722 * bit 0: 1 means performant mode, 0 means simple mode.
723 * bits 1-3 = block fetch table entry
724 * bits 4-6 = command type (== 0)
725 *
726 * ioaccel1 mode:
727 * bit 0 = "performant mode" bit.
728 * bits 1-3 = block fetch table entry
729 * bits 4-6 = command type (== 110)
730 * (command type is needed because ioaccel1 mode
731 * commands are submitted through the same register as normal
732 * mode commands, so this is how the controller knows whether
733 * the command is normal mode or ioaccel1 mode.)
734 *
735 * ioaccel2 mode:
736 * bit 0 = "performant mode" bit.
737 * bits 1-4 = block fetch table entry (note extra bit)
738 * bits 4-6 = not needed, because ioaccel2 mode has
739 * a separate special register for submitting commands.
740 */
741
3f5eac3a
SC		 742/* set_performant_mode: Modify the tag for cciss performant
743 * set bit 0 for pull model, bits 3-1 for block fetch
744 * register number
745 */
746static void set_performant_mode(struct ctlr_info *h, struct CommandList *c)
747{
254f796b 748 if (likely(h->transMethod & CFGTBL_Trans_Performant)) {
3f5eac3a 749 c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1);
eee0f03a 750 if (likely(h->msix_vector > 0))
254f796b 751 c->Header.ReplyQueue =
804a5cb5 752 raw_smp_processor_id() % h->nreply_queues;
254f796b 753 }
3f5eac3a
SC		 754}
755
c349775e
ST		 756static void set_ioaccel1_performant_mode(struct ctlr_info *h,
757 struct CommandList *c)
758{
759 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
760
761 /* Tell the controller to post the reply to the queue for this
762 * processor. This seems to give the best I/O throughput.
763 */
764 cp->ReplyQueue = smp_processor_id() % h->nreply_queues;
765 /* Set the bits in the address sent down to include:
766 * - performant mode bit (bit 0)
767 * - pull count (bits 1-3)
768 * - command type (bits 4-6)
769 */
770 c->busaddr |= 1 | (h->ioaccel1_blockFetchTable[c->Header.SGList] << 1) |
771 IOACCEL1_BUSADDR_CMDTYPE;
772}
773
774static void set_ioaccel2_performant_mode(struct ctlr_info *h,
775 struct CommandList *c)
776{
777 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
778
779 /* Tell the controller to post the reply to the queue for this
780 * processor. This seems to give the best I/O throughput.
781 */
782 cp->reply_queue = smp_processor_id() % h->nreply_queues;
783 /* Set the bits in the address sent down to include:
784 * - performant mode bit not used in ioaccel mode 2
785 * - pull count (bits 0-3)
786 * - command type isn't needed for ioaccel2
787 */
788 c->busaddr |= (h->ioaccel2_blockFetchTable[cp->sg_count]);
789}
790
e85c5974
SC		 791static int is_firmware_flash_cmd(u8 *cdb)
792{
793 return cdb[0] == BMIC_WRITE && cdb[6] == BMIC_FLASH_FIRMWARE;
794}
795
796/*
797 * During firmware flash, the heartbeat register may not update as frequently
798 * as it should. So we dial down lockup detection during firmware flash. and
799 * dial it back up when firmware flash completes.
800 */
801#define HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH (240 * HZ)
802#define HEARTBEAT_SAMPLE_INTERVAL (30 * HZ)
803static void dial_down_lockup_detection_during_fw_flash(struct ctlr_info *h,
804 struct CommandList *c)
805{
806 if (!is_firmware_flash_cmd(c->Request.CDB))
807 return;
808 atomic_inc(&h->firmware_flash_in_progress);
809 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH;
810}
811
812static void dial_up_lockup_detection_on_fw_flash_complete(struct ctlr_info *h,
813 struct CommandList *c)
814{
815 if (is_firmware_flash_cmd(c->Request.CDB) &&
816 atomic_dec_and_test(&h->firmware_flash_in_progress))
817 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
818}
819
3f5eac3a
SC		 820static void enqueue_cmd_and_start_io(struct ctlr_info *h,
821 struct CommandList *c)
822{
c349775e
ST		 823 switch (c->cmd_type) {
824 case CMD_IOACCEL1:
825 set_ioaccel1_performant_mode(h, c);
826 break;
827 case CMD_IOACCEL2:
828 set_ioaccel2_performant_mode(h, c);
829 break;
830 default:
831 set_performant_mode(h, c);
832 }
e85c5974 833 dial_down_lockup_detection_during_fw_flash(h, c);
f2405db8
DB		 834 atomic_inc(&h->commands_outstanding);
835 h->access.submit_command(h, c);
3f5eac3a
SC		 836}
837
838static inline int is_hba_lunid(unsigned char scsi3addr[])
839{
840 return memcmp(scsi3addr, RAID_CTLR_LUNID, 8) == 0;
841}
842
843static inline int is_scsi_rev_5(struct ctlr_info *h)
844{
845 if (!h->hba_inquiry_data)
846 return 0;
847 if ((h->hba_inquiry_data[2] & 0x07) == 5)
848 return 1;
849 return 0;
850}
851
edd16368
SC		 852static int hpsa_find_target_lun(struct ctlr_info *h,
853 unsigned char scsi3addr[], int bus, int *target, int *lun)
854{
855 /* finds an unused bus, target, lun for a new physical device
856 * assumes h->devlock is held
857 */
858 int i, found = 0;
cfe5badc 859 DECLARE_BITMAP(lun_taken, HPSA_MAX_DEVICES);
edd16368 860
263d9401 861 bitmap_zero(lun_taken, HPSA_MAX_DEVICES);
edd16368
SC		 862
863 for (i = 0; i < h->ndevices; i++) {
864 if (h->dev[i]->bus == bus && h->dev[i]->target != -1)
263d9401 865 __set_bit(h->dev[i]->target, lun_taken);
edd16368
SC		 866 }
867
263d9401
AM		 868 i = find_first_zero_bit(lun_taken, HPSA_MAX_DEVICES);
869 if (i < HPSA_MAX_DEVICES) {
870 /* *bus = 1; */
871 *target = i;
872 *lun = 0;
873 found = 1;
edd16368
SC		 874 }
875 return !found;
876}
877
878/* Add an entry into h->dev[] array. */
879static int hpsa_scsi_add_entry(struct ctlr_info *h, int hostno,
880 struct hpsa_scsi_dev_t *device,
881 struct hpsa_scsi_dev_t *added[], int *nadded)
882{
883 /* assumes h->devlock is held */
884 int n = h->ndevices;
885 int i;
886 unsigned char addr1[8], addr2[8];
887 struct hpsa_scsi_dev_t *sd;
888
cfe5badc 889 if (n >= HPSA_MAX_DEVICES) {
edd16368
SC		 890 dev_err(&h->pdev->dev, "too many devices, some will be "
891 "inaccessible.\n");
892 return -1;
893 }
894
895 /* physical devices do not have lun or target assigned until now. */
896 if (device->lun != -1)
897 /* Logical device, lun is already assigned. */
898 goto lun_assigned;
899
900 /* If this device a non-zero lun of a multi-lun device
901 * byte 4 of the 8-byte LUN addr will contain the logical
2b08b3e9 902 * unit no, zero otherwise.
edd16368
SC		 903 */
904 if (device->scsi3addr[4] == 0) {
905 /* This is not a non-zero lun of a multi-lun device */
906 if (hpsa_find_target_lun(h, device->scsi3addr,
907 device->bus, &device->target, &device->lun) != 0)
908 return -1;
909 goto lun_assigned;
910 }
911
912 /* This is a non-zero lun of a multi-lun device.
913 * Search through our list and find the device which
914 * has the same 8 byte LUN address, excepting byte 4.
915 * Assign the same bus and target for this new LUN.
916 * Use the logical unit number from the firmware.
917 */
918 memcpy(addr1, device->scsi3addr, 8);
919 addr1[4] = 0;
920 for (i = 0; i < n; i++) {
921 sd = h->dev[i];
922 memcpy(addr2, sd->scsi3addr, 8);
923 addr2[4] = 0;
924 /* differ only in byte 4? */
925 if (memcmp(addr1, addr2, 8) == 0) {
926 device->bus = sd->bus;
927 device->target = sd->target;
928 device->lun = device->scsi3addr[4];
929 break;
930 }
931 }
932 if (device->lun == -1) {
933 dev_warn(&h->pdev->dev, "physical device with no LUN=0,"
934 " suspect firmware bug or unsupported hardware "
935 "configuration.\n");
936 return -1;
937 }
938
939lun_assigned:
940
941 h->dev[n] = device;
942 h->ndevices++;
943 added[*nadded] = device;
944 (*nadded)++;
945
946 /* initially, (before registering with scsi layer) we don't
947 * know our hostno and we don't want to print anything first
948 * time anyway (the scsi layer's inquiries will show that info)
949 */
950 /* if (hostno != -1) */
951 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d added.\n",
952 scsi_device_type(device->devtype), hostno,
953 device->bus, device->target, device->lun);
954 return 0;
955}
956
bd9244f7
ST		 957/* Update an entry in h->dev[] array. */
958static void hpsa_scsi_update_entry(struct ctlr_info *h, int hostno,
959 int entry, struct hpsa_scsi_dev_t *new_entry)
960{
961 /* assumes h->devlock is held */
962 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
963
964 /* Raid level changed. */
965 h->dev[entry]->raid_level = new_entry->raid_level;
250fb125
SC		 966
967 /* Raid offload parameters changed. */
968 h->dev[entry]->offload_config = new_entry->offload_config;
969 h->dev[entry]->offload_enabled = new_entry->offload_enabled;
9fb0de2d
SC		 970 h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
971 h->dev[entry]->offload_to_mirror = new_entry->offload_to_mirror;
972 h->dev[entry]->raid_map = new_entry->raid_map;
250fb125 973
bd9244f7
ST		 974 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d updated.\n",
975 scsi_device_type(new_entry->devtype), hostno, new_entry->bus,
976 new_entry->target, new_entry->lun);
977}
978
2a8ccf31
SC		 979/* Replace an entry from h->dev[] array. */
980static void hpsa_scsi_replace_entry(struct ctlr_info *h, int hostno,
981 int entry, struct hpsa_scsi_dev_t *new_entry,
982 struct hpsa_scsi_dev_t *added[], int *nadded,
983 struct hpsa_scsi_dev_t *removed[], int *nremoved)
984{
985 /* assumes h->devlock is held */
cfe5badc 986 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
2a8ccf31
SC		 987 removed[*nremoved] = h->dev[entry];
988 (*nremoved)++;
01350d05
SC		 989
990 /*
991 * New physical devices won't have target/lun assigned yet
992 * so we need to preserve the values in the slot we are replacing.
993 */
994 if (new_entry->target == -1) {
995 new_entry->target = h->dev[entry]->target;
996 new_entry->lun = h->dev[entry]->lun;
997 }
998
2a8ccf31
SC		 999 h->dev[entry] = new_entry;
1000 added[*nadded] = new_entry;
1001 (*nadded)++;
1002 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d changed.\n",
1003 scsi_device_type(new_entry->devtype), hostno, new_entry->bus,
1004 new_entry->target, new_entry->lun);
1005}
1006
edd16368
SC		 1007/* Remove an entry from h->dev[] array. */
1008static void hpsa_scsi_remove_entry(struct ctlr_info *h, int hostno, int entry,
1009 struct hpsa_scsi_dev_t *removed[], int *nremoved)
1010{
1011 /* assumes h->devlock is held */
1012 int i;
1013 struct hpsa_scsi_dev_t *sd;
1014
cfe5badc 1015 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
edd16368
SC		 1016
1017 sd = h->dev[entry];
1018 removed[*nremoved] = h->dev[entry];
1019 (*nremoved)++;
1020
1021 for (i = entry; i < h->ndevices-1; i++)
1022 h->dev[i] = h->dev[i+1];
1023 h->ndevices--;
1024 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d removed.\n",
1025 scsi_device_type(sd->devtype), hostno, sd->bus, sd->target,
1026 sd->lun);
1027}
1028
1029#define SCSI3ADDR_EQ(a, b) ( \
1030 (a)[7] == (b)[7] && \
1031 (a)[6] == (b)[6] && \
1032 (a)[5] == (b)[5] && \
1033 (a)[4] == (b)[4] && \
1034 (a)[3] == (b)[3] && \
1035 (a)[2] == (b)[2] && \
1036 (a)[1] == (b)[1] && \
1037 (a)[0] == (b)[0])
1038
1039static void fixup_botched_add(struct ctlr_info *h,
1040 struct hpsa_scsi_dev_t *added)
1041{
1042 /* called when scsi_add_device fails in order to re-adjust
1043 * h->dev[] to match the mid layer's view.
1044 */
1045 unsigned long flags;
1046 int i, j;
1047
1048 spin_lock_irqsave(&h->lock, flags);
1049 for (i = 0; i < h->ndevices; i++) {
1050 if (h->dev[i] == added) {
1051 for (j = i; j < h->ndevices-1; j++)
1052 h->dev[j] = h->dev[j+1];
1053 h->ndevices--;
1054 break;
1055 }
1056 }
1057 spin_unlock_irqrestore(&h->lock, flags);
1058 kfree(added);
1059}
1060
1061static inline int device_is_the_same(struct hpsa_scsi_dev_t *dev1,
1062 struct hpsa_scsi_dev_t *dev2)
1063{
edd16368
SC		 1064 /* we compare everything except lun and target as these
1065 * are not yet assigned. Compare parts likely
1066 * to differ first
1067 */
1068 if (memcmp(dev1->scsi3addr, dev2->scsi3addr,
1069 sizeof(dev1->scsi3addr)) != 0)
1070 return 0;
1071 if (memcmp(dev1->device_id, dev2->device_id,
1072 sizeof(dev1->device_id)) != 0)
1073 return 0;
1074 if (memcmp(dev1->model, dev2->model, sizeof(dev1->model)) != 0)
1075 return 0;
1076 if (memcmp(dev1->vendor, dev2->vendor, sizeof(dev1->vendor)) != 0)
1077 return 0;
edd16368
SC		 1078 if (dev1->devtype != dev2->devtype)
1079 return 0;
edd16368
SC		 1080 if (dev1->bus != dev2->bus)
1081 return 0;
1082 return 1;
1083}
1084
bd9244f7
ST		 1085static inline int device_updated(struct hpsa_scsi_dev_t *dev1,
1086 struct hpsa_scsi_dev_t *dev2)
1087{
1088 /* Device attributes that can change, but don't mean
1089 * that the device is a different device, nor that the OS
1090 * needs to be told anything about the change.
1091 */
1092 if (dev1->raid_level != dev2->raid_level)
1093 return 1;
250fb125
SC		 1094 if (dev1->offload_config != dev2->offload_config)
1095 return 1;
1096 if (dev1->offload_enabled != dev2->offload_enabled)
1097 return 1;
bd9244f7
ST		 1098 return 0;
1099}
1100
edd16368
SC		 1101/* Find needle in haystack. If exact match found, return DEVICE_SAME,
1102 * and return needle location in *index. If scsi3addr matches, but not
1103 * vendor, model, serial num, etc. return DEVICE_CHANGED, and return needle
bd9244f7
ST		 1104 * location in *index.
1105 * In the case of a minor device attribute change, such as RAID level, just
1106 * return DEVICE_UPDATED, along with the updated device's location in index.
1107 * If needle not found, return DEVICE_NOT_FOUND.
edd16368
SC		 1108 */
1109static int hpsa_scsi_find_entry(struct hpsa_scsi_dev_t *needle,
1110 struct hpsa_scsi_dev_t *haystack[], int haystack_size,
1111 int *index)
1112{
1113 int i;
1114#define DEVICE_NOT_FOUND 0
1115#define DEVICE_CHANGED 1
1116#define DEVICE_SAME 2
bd9244f7 1117#define DEVICE_UPDATED 3
edd16368 1118 for (i = 0; i < haystack_size; i++) {
23231048
SC		 1119 if (haystack[i] == NULL) /* previously removed. */
1120 continue;
edd16368
SC		 1121 if (SCSI3ADDR_EQ(needle->scsi3addr, haystack[i]->scsi3addr)) {
1122 *index = i;
bd9244f7
ST		 1123 if (device_is_the_same(needle, haystack[i])) {
1124 if (device_updated(needle, haystack[i]))
1125 return DEVICE_UPDATED;
edd16368 1126 return DEVICE_SAME;
bd9244f7 1127 } else {
9846590e
SC		 1128 /* Keep offline devices offline */
1129 if (needle->volume_offline)
1130 return DEVICE_NOT_FOUND;
edd16368 1131 return DEVICE_CHANGED;
bd9244f7 1132 }
edd16368
SC		 1133 }
1134 }
1135 *index = -1;
1136 return DEVICE_NOT_FOUND;
1137}
1138
9846590e
SC		 1139static void hpsa_monitor_offline_device(struct ctlr_info *h,
1140 unsigned char scsi3addr[])
1141{
1142 struct offline_device_entry *device;
1143 unsigned long flags;
1144
1145 /* Check to see if device is already on the list */
1146 spin_lock_irqsave(&h->offline_device_lock, flags);
1147 list_for_each_entry(device, &h->offline_device_list, offline_list) {
1148 if (memcmp(device->scsi3addr, scsi3addr,
1149 sizeof(device->scsi3addr)) == 0) {
1150 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1151 return;
1152 }
1153 }
1154 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1155
1156 /* Device is not on the list, add it. */
1157 device = kmalloc(sizeof(*device), GFP_KERNEL);
1158 if (!device) {
1159 dev_warn(&h->pdev->dev, "out of memory in %s\n", __func__);
1160 return;
1161 }
1162 memcpy(device->scsi3addr, scsi3addr, sizeof(device->scsi3addr));
1163 spin_lock_irqsave(&h->offline_device_lock, flags);
1164 list_add_tail(&device->offline_list, &h->offline_device_list);
1165 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1166}
1167
1168/* Print a message explaining various offline volume states */
1169static void hpsa_show_volume_status(struct ctlr_info *h,
1170 struct hpsa_scsi_dev_t *sd)
1171{
1172 if (sd->volume_offline == HPSA_VPD_LV_STATUS_UNSUPPORTED)
1173 dev_info(&h->pdev->dev,
1174 "C%d:B%d:T%d:L%d Volume status is not available through vital product data pages.\n",
1175 h->scsi_host->host_no,
1176 sd->bus, sd->target, sd->lun);
1177 switch (sd->volume_offline) {
1178 case HPSA_LV_OK:
1179 break;
1180 case HPSA_LV_UNDERGOING_ERASE:
1181 dev_info(&h->pdev->dev,
1182 "C%d:B%d:T%d:L%d Volume is undergoing background erase process.\n",
1183 h->scsi_host->host_no,
1184 sd->bus, sd->target, sd->lun);
1185 break;
1186 case HPSA_LV_UNDERGOING_RPI:
1187 dev_info(&h->pdev->dev,
1188 "C%d:B%d:T%d:L%d Volume is undergoing rapid parity initialization process.\n",
1189 h->scsi_host->host_no,
1190 sd->bus, sd->target, sd->lun);
1191 break;
1192 case HPSA_LV_PENDING_RPI:
1193 dev_info(&h->pdev->dev,
1194 "C%d:B%d:T%d:L%d Volume is queued for rapid parity initialization process.\n",
1195 h->scsi_host->host_no,
1196 sd->bus, sd->target, sd->lun);
1197 break;
1198 case HPSA_LV_ENCRYPTED_NO_KEY:
1199 dev_info(&h->pdev->dev,
1200 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because key is not present.\n",
1201 h->scsi_host->host_no,
1202 sd->bus, sd->target, sd->lun);
1203 break;
1204 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
1205 dev_info(&h->pdev->dev,
1206 "C%d:B%d:T%d:L%d Volume is not encrypted and cannot be accessed because controller is in encryption-only mode.\n",
1207 h->scsi_host->host_no,
1208 sd->bus, sd->target, sd->lun);
1209 break;
1210 case HPSA_LV_UNDERGOING_ENCRYPTION:
1211 dev_info(&h->pdev->dev,
1212 "C%d:B%d:T%d:L%d Volume is undergoing encryption process.\n",
1213 h->scsi_host->host_no,
1214 sd->bus, sd->target, sd->lun);
1215 break;
1216 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
1217 dev_info(&h->pdev->dev,
1218 "C%d:B%d:T%d:L%d Volume is undergoing encryption re-keying process.\n",
1219 h->scsi_host->host_no,
1220 sd->bus, sd->target, sd->lun);
1221 break;
1222 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
1223 dev_info(&h->pdev->dev,
1224 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because controller does not have encryption enabled.\n",
1225 h->scsi_host->host_no,
1226 sd->bus, sd->target, sd->lun);
1227 break;
1228 case HPSA_LV_PENDING_ENCRYPTION:
1229 dev_info(&h->pdev->dev,
1230 "C%d:B%d:T%d:L%d Volume is pending migration to encrypted state, but process has not started.\n",
1231 h->scsi_host->host_no,
1232 sd->bus, sd->target, sd->lun);
1233 break;
1234 case HPSA_LV_PENDING_ENCRYPTION_REKEYING:
1235 dev_info(&h->pdev->dev,
1236 "C%d:B%d:T%d:L%d Volume is encrypted and is pending encryption rekeying.\n",
1237 h->scsi_host->host_no,
1238 sd->bus, sd->target, sd->lun);
1239 break;
1240 }
1241}
1242
4967bd3e 1243static void adjust_hpsa_scsi_table(struct ctlr_info *h, int hostno,
edd16368
SC		 1244 struct hpsa_scsi_dev_t *sd[], int nsds)
1245{
1246 /* sd contains scsi3 addresses and devtypes, and inquiry
1247 * data. This function takes what's in sd to be the current
1248 * reality and updates h->dev[] to reflect that reality.
1249 */
1250 int i, entry, device_change, changes = 0;
1251 struct hpsa_scsi_dev_t *csd;
1252 unsigned long flags;
1253 struct hpsa_scsi_dev_t **added, **removed;
1254 int nadded, nremoved;
1255 struct Scsi_Host *sh = NULL;
1256
cfe5badc
ST		 1257 added = kzalloc(sizeof(*added) * HPSA_MAX_DEVICES, GFP_KERNEL);
1258 removed = kzalloc(sizeof(*removed) * HPSA_MAX_DEVICES, GFP_KERNEL);
edd16368
SC		 1259
1260 if (!added || !removed) {
1261 dev_warn(&h->pdev->dev, "out of memory in "
1262 "adjust_hpsa_scsi_table\n");
1263 goto free_and_out;
1264 }
1265
1266 spin_lock_irqsave(&h->devlock, flags);
1267
1268 /* find any devices in h->dev[] that are not in
1269 * sd[] and remove them from h->dev[], and for any
1270 * devices which have changed, remove the old device
1271 * info and add the new device info.
bd9244f7
ST		 1272 * If minor device attributes change, just update
1273 * the existing device structure.
edd16368
SC		 1274 */
1275 i = 0;
1276 nremoved = 0;
1277 nadded = 0;
1278 while (i < h->ndevices) {
1279 csd = h->dev[i];
1280 device_change = hpsa_scsi_find_entry(csd, sd, nsds, &entry);
1281 if (device_change == DEVICE_NOT_FOUND) {
1282 changes++;
1283 hpsa_scsi_remove_entry(h, hostno, i,
1284 removed, &nremoved);
1285 continue; /* remove ^^^, hence i not incremented */
1286 } else if (device_change == DEVICE_CHANGED) {
1287 changes++;
2a8ccf31
SC		 1288 hpsa_scsi_replace_entry(h, hostno, i, sd[entry],
1289 added, &nadded, removed, &nremoved);
c7f172dc
SC		 1290 /* Set it to NULL to prevent it from being freed
1291 * at the bottom of hpsa_update_scsi_devices()
1292 */
1293 sd[entry] = NULL;
bd9244f7
ST		 1294 } else if (device_change == DEVICE_UPDATED) {
1295 hpsa_scsi_update_entry(h, hostno, i, sd[entry]);
edd16368
SC		 1296 }
1297 i++;
1298 }
1299
1300 /* Now, make sure every device listed in sd[] is also
1301 * listed in h->dev[], adding them if they aren't found
1302 */
1303
1304 for (i = 0; i < nsds; i++) {
1305 if (!sd[i]) /* if already added above. */
1306 continue;
9846590e
SC		 1307
1308 /* Don't add devices which are NOT READY, FORMAT IN PROGRESS
1309 * as the SCSI mid-layer does not handle such devices well.
1310 * It relentlessly loops sending TUR at 3Hz, then READ(10)
1311 * at 160Hz, and prevents the system from coming up.
1312 */
1313 if (sd[i]->volume_offline) {
1314 hpsa_show_volume_status(h, sd[i]);
1315 dev_info(&h->pdev->dev, "c%db%dt%dl%d: temporarily offline\n",
1316 h->scsi_host->host_no,
1317 sd[i]->bus, sd[i]->target, sd[i]->lun);
1318 continue;
1319 }
1320
edd16368
SC		 1321 device_change = hpsa_scsi_find_entry(sd[i], h->dev,
1322 h->ndevices, &entry);
1323 if (device_change == DEVICE_NOT_FOUND) {
1324 changes++;
1325 if (hpsa_scsi_add_entry(h, hostno, sd[i],
1326 added, &nadded) != 0)
1327 break;
1328 sd[i] = NULL; /* prevent from being freed later. */
1329 } else if (device_change == DEVICE_CHANGED) {
1330 /* should never happen... */
1331 changes++;
1332 dev_warn(&h->pdev->dev,
1333 "device unexpectedly changed.\n");
1334 /* but if it does happen, we just ignore that device */
1335 }
1336 }
1337 spin_unlock_irqrestore(&h->devlock, flags);
1338
9846590e
SC		 1339 /* Monitor devices which are in one of several NOT READY states to be
1340 * brought online later. This must be done without holding h->devlock,
1341 * so don't touch h->dev[]
1342 */
1343 for (i = 0; i < nsds; i++) {
1344 if (!sd[i]) /* if already added above. */
1345 continue;
1346 if (sd[i]->volume_offline)
1347 hpsa_monitor_offline_device(h, sd[i]->scsi3addr);
1348 }
1349
edd16368
SC		 1350 /* Don't notify scsi mid layer of any changes the first time through
1351 * (or if there are no changes) scsi_scan_host will do it later the
1352 * first time through.
1353 */
1354 if (hostno == -1 || !changes)
1355 goto free_and_out;
1356
1357 sh = h->scsi_host;
1358 /* Notify scsi mid layer of any removed devices */
1359 for (i = 0; i < nremoved; i++) {
1360 struct scsi_device *sdev =
1361 scsi_device_lookup(sh, removed[i]->bus,
1362 removed[i]->target, removed[i]->lun);
1363 if (sdev != NULL) {
1364 scsi_remove_device(sdev);
1365 scsi_device_put(sdev);
1366 } else {
1367 /* We don't expect to get here.
1368 * future cmds to this device will get selection
1369 * timeout as if the device was gone.
1370 */
1371 dev_warn(&h->pdev->dev, "didn't find c%db%dt%dl%d "
1372 " for removal.", hostno, removed[i]->bus,
1373 removed[i]->target, removed[i]->lun);
1374 }
1375 kfree(removed[i]);
1376 removed[i] = NULL;
1377 }
1378
1379 /* Notify scsi mid layer of any added devices */
1380 for (i = 0; i < nadded; i++) {
1381 if (scsi_add_device(sh, added[i]->bus,
1382 added[i]->target, added[i]->lun) == 0)
1383 continue;
1384 dev_warn(&h->pdev->dev, "scsi_add_device c%db%dt%dl%d failed, "
1385 "device not added.\n", hostno, added[i]->bus,
1386 added[i]->target, added[i]->lun);
1387 /* now we have to remove it from h->dev,
1388 * since it didn't get added to scsi mid layer
1389 */
1390 fixup_botched_add(h, added[i]);
1391 }
1392
1393free_and_out:
1394 kfree(added);
1395 kfree(removed);
edd16368
SC		 1396}
1397
1398/*
9e03aa2f 1399 * Lookup bus/target/lun and return corresponding struct hpsa_scsi_dev_t *
edd16368
SC		 1400 * Assume's h->devlock is held.
1401 */
1402static struct hpsa_scsi_dev_t *lookup_hpsa_scsi_dev(struct ctlr_info *h,
1403 int bus, int target, int lun)
1404{
1405 int i;
1406 struct hpsa_scsi_dev_t *sd;
1407
1408 for (i = 0; i < h->ndevices; i++) {
1409 sd = h->dev[i];
1410 if (sd->bus == bus && sd->target == target && sd->lun == lun)
1411 return sd;
1412 }
1413 return NULL;
1414}
1415
1416/* link sdev->hostdata to our per-device structure. */
1417static int hpsa_slave_alloc(struct scsi_device *sdev)
1418{
1419 struct hpsa_scsi_dev_t *sd;
1420 unsigned long flags;
1421 struct ctlr_info *h;
1422
1423 h = sdev_to_hba(sdev);
1424 spin_lock_irqsave(&h->devlock, flags);
1425 sd = lookup_hpsa_scsi_dev(h, sdev_channel(sdev),
1426 sdev_id(sdev), sdev->lun);
1427 if (sd != NULL)
1428 sdev->hostdata = sd;
1429 spin_unlock_irqrestore(&h->devlock, flags);
1430 return 0;
1431}
1432
1433static void hpsa_slave_destroy(struct scsi_device *sdev)
1434{
bcc44255 1435 /* nothing to do. */
edd16368
SC		 1436}
1437
33a2ffce
SC		 1438static void hpsa_free_sg_chain_blocks(struct ctlr_info *h)
1439{
1440 int i;
1441
1442 if (!h->cmd_sg_list)
1443 return;
1444 for (i = 0; i < h->nr_cmds; i++) {
1445 kfree(h->cmd_sg_list[i]);
1446 h->cmd_sg_list[i] = NULL;
1447 }
1448 kfree(h->cmd_sg_list);
1449 h->cmd_sg_list = NULL;
1450}
1451
1452static int hpsa_allocate_sg_chain_blocks(struct ctlr_info *h)
1453{
1454 int i;
1455
1456 if (h->chainsize <= 0)
1457 return 0;
1458
1459 h->cmd_sg_list = kzalloc(sizeof(*h->cmd_sg_list) * h->nr_cmds,
1460 GFP_KERNEL);
3d4e6af8
RE		 1461 if (!h->cmd_sg_list) {
1462 dev_err(&h->pdev->dev, "Failed to allocate SG list\n");
33a2ffce 1463 return -ENOMEM;
3d4e6af8 1464 }
33a2ffce
SC		 1465 for (i = 0; i < h->nr_cmds; i++) {
1466 h->cmd_sg_list[i] = kmalloc(sizeof(*h->cmd_sg_list[i]) *
1467 h->chainsize, GFP_KERNEL);
3d4e6af8
RE		 1468 if (!h->cmd_sg_list[i]) {
1469 dev_err(&h->pdev->dev, "Failed to allocate cmd SG\n");
33a2ffce 1470 goto clean;
3d4e6af8 1471 }
33a2ffce
SC		 1472 }
1473 return 0;
1474
1475clean:
1476 hpsa_free_sg_chain_blocks(h);
1477 return -ENOMEM;
1478}
1479
e2bea6df 1480static int hpsa_map_sg_chain_block(struct ctlr_info *h,
33a2ffce
SC		 1481 struct CommandList *c)
1482{
1483 struct SGDescriptor *chain_sg, *chain_block;
1484 u64 temp64;
50a0decf 1485 u32 chain_len;
33a2ffce
SC		 1486
1487 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
1488 chain_block = h->cmd_sg_list[c->cmdindex];
50a0decf
SC		 1489 chain_sg->Ext = cpu_to_le32(HPSA_SG_CHAIN);
1490 chain_len = sizeof(*chain_sg) *
2b08b3e9 1491 (le16_to_cpu(c->Header.SGTotal) - h->max_cmd_sg_entries);
50a0decf
SC		 1492 chain_sg->Len = cpu_to_le32(chain_len);
1493 temp64 = pci_map_single(h->pdev, chain_block, chain_len,
33a2ffce 1494 PCI_DMA_TODEVICE);
e2bea6df
SC		 1495 if (dma_mapping_error(&h->pdev->dev, temp64)) {
1496 /* prevent subsequent unmapping */
50a0decf 1497 chain_sg->Addr = cpu_to_le64(0);
e2bea6df
SC		 1498 return -1;
1499 }
50a0decf 1500 chain_sg->Addr = cpu_to_le64(temp64);
e2bea6df 1501 return 0;
33a2ffce
SC		 1502}
1503
1504static void hpsa_unmap_sg_chain_block(struct ctlr_info *h,
1505 struct CommandList *c)
1506{
1507 struct SGDescriptor *chain_sg;
33a2ffce 1508
50a0decf 1509 if (le16_to_cpu(c->Header.SGTotal) <= h->max_cmd_sg_entries)
33a2ffce
SC		 1510 return;
1511
1512 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
50a0decf
SC		 1513 pci_unmap_single(h->pdev, le64_to_cpu(chain_sg->Addr),
1514 le32_to_cpu(chain_sg->Len), PCI_DMA_TODEVICE);
33a2ffce
SC		 1515}
1516
a09c1441
ST		 1517
1518/* Decode the various types of errors on ioaccel2 path.
1519 * Return 1 for any error that should generate a RAID path retry.
1520 * Return 0 for errors that don't require a RAID path retry.
1521 */
1522static int handle_ioaccel_mode2_error(struct ctlr_info *h,
c349775e
ST		 1523 struct CommandList *c,
1524 struct scsi_cmnd *cmd,
1525 struct io_accel2_cmd *c2)
1526{
1527 int data_len;
a09c1441 1528 int retry = 0;
c349775e
ST		 1529
1530 switch (c2->error_data.serv_response) {
1531 case IOACCEL2_SERV_RESPONSE_COMPLETE:
1532 switch (c2->error_data.status) {
1533 case IOACCEL2_STATUS_SR_TASK_COMP_GOOD:
1534 break;
1535 case IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND:
1536 dev_warn(&h->pdev->dev,
1537 "%s: task complete with check condition.\n",
1538 "HP SSD Smart Path");
ee6b1889 1539 cmd->result |= SAM_STAT_CHECK_CONDITION;
c349775e 1540 if (c2->error_data.data_present !=
ee6b1889
SC		 1541 IOACCEL2_SENSE_DATA_PRESENT) {
1542 memset(cmd->sense_buffer, 0,
1543 SCSI_SENSE_BUFFERSIZE);
c349775e 1544 break;
ee6b1889 1545 }
c349775e
ST		 1546 /* copy the sense data */
1547 data_len = c2->error_data.sense_data_len;
1548 if (data_len > SCSI_SENSE_BUFFERSIZE)
1549 data_len = SCSI_SENSE_BUFFERSIZE;
1550 if (data_len > sizeof(c2->error_data.sense_data_buff))
1551 data_len =
1552 sizeof(c2->error_data.sense_data_buff);
1553 memcpy(cmd->sense_buffer,
1554 c2->error_data.sense_data_buff, data_len);
a09c1441 1555 retry = 1;
c349775e
ST		 1556 break;
1557 case IOACCEL2_STATUS_SR_TASK_COMP_BUSY:
1558 dev_warn(&h->pdev->dev,
1559 "%s: task complete with BUSY status.\n",
1560 "HP SSD Smart Path");
a09c1441 1561 retry = 1;
c349775e
ST		 1562 break;
1563 case IOACCEL2_STATUS_SR_TASK_COMP_RES_CON:
1564 dev_warn(&h->pdev->dev,
1565 "%s: task complete with reservation conflict.\n",
1566 "HP SSD Smart Path");
a09c1441 1567 retry = 1;
c349775e
ST		 1568 break;
1569 case IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL:
1570 /* Make scsi midlayer do unlimited retries */
1571 cmd->result = DID_IMM_RETRY << 16;
1572 break;
1573 case IOACCEL2_STATUS_SR_TASK_COMP_ABORTED:
1574 dev_warn(&h->pdev->dev,
1575 "%s: task complete with aborted status.\n",
1576 "HP SSD Smart Path");
a09c1441 1577 retry = 1;
c349775e
ST		 1578 break;
1579 default:
1580 dev_warn(&h->pdev->dev,
1581 "%s: task complete with unrecognized status: 0x%02x\n",
1582 "HP SSD Smart Path", c2->error_data.status);
a09c1441 1583 retry = 1;
c349775e
ST		 1584 break;
1585 }
1586 break;
1587 case IOACCEL2_SERV_RESPONSE_FAILURE:
1588 /* don't expect to get here. */
1589 dev_warn(&h->pdev->dev,
1590 "unexpected delivery or target failure, status = 0x%02x\n",
1591 c2->error_data.status);
a09c1441 1592 retry = 1;
c349775e
ST		 1593 break;
1594 case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE:
1595 break;
1596 case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS:
1597 break;
1598 case IOACCEL2_SERV_RESPONSE_TMF_REJECTED:
1599 dev_warn(&h->pdev->dev, "task management function rejected.\n");
a09c1441 1600 retry = 1;
c349775e
ST		 1601 break;
1602 case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN:
1603 dev_warn(&h->pdev->dev, "task management function invalid LUN\n");
1604 break;
1605 default:
1606 dev_warn(&h->pdev->dev,
1607 "%s: Unrecognized server response: 0x%02x\n",
a09c1441
ST		 1608 "HP SSD Smart Path",
1609 c2->error_data.serv_response);
1610 retry = 1;
c349775e
ST		 1611 break;
1612 }
a09c1441
ST		 1613
1614 return retry; /* retry on raid path? */
c349775e
ST		 1615}
1616
1617static void process_ioaccel2_completion(struct ctlr_info *h,
1618 struct CommandList *c, struct scsi_cmnd *cmd,
1619 struct hpsa_scsi_dev_t *dev)
1620{
1621 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
a09c1441 1622 int raid_retry = 0;
c349775e
ST		 1623
1624 /* check for good status */
1625 if (likely(c2->error_data.serv_response == 0 &&
1626 c2->error_data.status == 0)) {
1627 cmd_free(h, c);
1628 cmd->scsi_done(cmd);
1629 return;
1630 }
1631
1632 /* Any RAID offload error results in retry which will use
1633 * the normal I/O path so the controller can handle whatever's
1634 * wrong.
1635 */
1636 if (is_logical_dev_addr_mode(dev->scsi3addr) &&
1637 c2->error_data.serv_response ==
1638 IOACCEL2_SERV_RESPONSE_FAILURE) {
c349775e 1639 dev->offload_enabled = 0;
e863d68e 1640 h->drv_req_rescan = 1; /* schedule controller for a rescan */
c349775e
ST		 1641 cmd->result = DID_SOFT_ERROR << 16;
1642 cmd_free(h, c);
1643 cmd->scsi_done(cmd);
1644 return;
1645 }
a09c1441
ST		 1646 raid_retry = handle_ioaccel_mode2_error(h, c, cmd, c2);
1647 /* If error found, disable Smart Path, schedule a rescan,
1648 * and force a retry on the standard path.
1649 */
1650 if (raid_retry) {
1651 dev_warn(&h->pdev->dev, "%s: Retrying on standard path.\n",
1652 "HP SSD Smart Path");
1653 dev->offload_enabled = 0; /* Disable Smart Path */
1654 h->drv_req_rescan = 1; /* schedule controller rescan */
1655 cmd->result = DID_SOFT_ERROR << 16;
1656 }
c349775e
ST		 1657 cmd_free(h, c);
1658 cmd->scsi_done(cmd);
1659}
1660
1fb011fb 1661static void complete_scsi_command(struct CommandList *cp)
edd16368
SC		 1662{
1663 struct scsi_cmnd *cmd;
1664 struct ctlr_info *h;
1665 struct ErrorInfo *ei;
283b4a9b 1666 struct hpsa_scsi_dev_t *dev;
edd16368
SC		 1667
1668 unsigned char sense_key;
1669 unsigned char asc; /* additional sense code */
1670 unsigned char ascq; /* additional sense code qualifier */
db111e18 1671 unsigned long sense_data_size;
edd16368
SC		 1672
1673 ei = cp->err_info;
1674 cmd = (struct scsi_cmnd *) cp->scsi_cmd;
1675 h = cp->h;
283b4a9b 1676 dev = cmd->device->hostdata;
edd16368
SC		 1677
1678 scsi_dma_unmap(cmd); /* undo the DMA mappings */
e1f7de0c 1679 if ((cp->cmd_type == CMD_SCSI) &&
2b08b3e9 1680 (le16_to_cpu(cp->Header.SGTotal) > h->max_cmd_sg_entries))
33a2ffce 1681 hpsa_unmap_sg_chain_block(h, cp);
edd16368
SC		 1682
1683 cmd->result = (DID_OK << 16); /* host byte */
1684 cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
c349775e
ST		 1685
1686 if (cp->cmd_type == CMD_IOACCEL2)
1687 return process_ioaccel2_completion(h, cp, cmd, dev);
1688
5512672f 1689 cmd->result |= ei->ScsiStatus;
edd16368 1690
6aa4c361
RE		 1691 scsi_set_resid(cmd, ei->ResidualCnt);
1692 if (ei->CommandStatus == 0) {
1693 cmd_free(h, cp);
1694 cmd->scsi_done(cmd);
1695 return;
1696 }
1697
1698 /* copy the sense data */
db111e18
SC		 1699 if (SCSI_SENSE_BUFFERSIZE < sizeof(ei->SenseInfo))
1700 sense_data_size = SCSI_SENSE_BUFFERSIZE;
1701 else
1702 sense_data_size = sizeof(ei->SenseInfo);
1703 if (ei->SenseLen < sense_data_size)
1704 sense_data_size = ei->SenseLen;
1705
1706 memcpy(cmd->sense_buffer, ei->SenseInfo, sense_data_size);
edd16368 1707
e1f7de0c
MG		 1708 /* For I/O accelerator commands, copy over some fields to the normal
1709 * CISS header used below for error handling.
1710 */
1711 if (cp->cmd_type == CMD_IOACCEL1) {
1712 struct io_accel1_cmd *c = &h->ioaccel_cmd_pool[cp->cmdindex];
2b08b3e9
DB		 1713 cp->Header.SGList = scsi_sg_count(cmd);
1714 cp->Header.SGTotal = cpu_to_le16(cp->Header.SGList);
1715 cp->Request.CDBLen = le16_to_cpu(c->io_flags) &
1716 IOACCEL1_IOFLAGS_CDBLEN_MASK;
50a0decf 1717 cp->Header.tag = c->tag;
e1f7de0c
MG		 1718 memcpy(cp->Header.LUN.LunAddrBytes, c->CISS_LUN, 8);
1719 memcpy(cp->Request.CDB, c->CDB, cp->Request.CDBLen);
283b4a9b
SC		 1720
1721 /* Any RAID offload error results in retry which will use
1722 * the normal I/O path so the controller can handle whatever's
1723 * wrong.
1724 */
1725 if (is_logical_dev_addr_mode(dev->scsi3addr)) {
1726 if (ei->CommandStatus == CMD_IOACCEL_DISABLED)
1727 dev->offload_enabled = 0;
1728 cmd->result = DID_SOFT_ERROR << 16;
1729 cmd_free(h, cp);
1730 cmd->scsi_done(cmd);
1731 return;
1732 }
e1f7de0c
MG		 1733 }
1734
edd16368
SC		 1735 /* an error has occurred */
1736 switch (ei->CommandStatus) {
1737
1738 case CMD_TARGET_STATUS:
1739 if (ei->ScsiStatus) {
1740 /* Get sense key */
1741 sense_key = 0xf & ei->SenseInfo[2];
1742 /* Get additional sense code */
1743 asc = ei->SenseInfo[12];
1744 /* Get addition sense code qualifier */
1745 ascq = ei->SenseInfo[13];
1746 }
edd16368 1747 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION) {
1d3b3609 1748 if (sense_key == ABORTED_COMMAND) {
2e311fba 1749 cmd->result |= DID_SOFT_ERROR << 16;
1d3b3609
MG		 1750 break;
1751 }
edd16368
SC		 1752 break;
1753 }
edd16368
SC		 1754 /* Problem was not a check condition
1755 * Pass it up to the upper layers...
1756 */
1757 if (ei->ScsiStatus) {
1758 dev_warn(&h->pdev->dev, "cp %p has status 0x%x "
1759 "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
1760 "Returning result: 0x%x\n",
1761 cp, ei->ScsiStatus,
1762 sense_key, asc, ascq,
1763 cmd->result);
1764 } else { /* scsi status is zero??? How??? */
1765 dev_warn(&h->pdev->dev, "cp %p SCSI status was 0. "
1766 "Returning no connection.\n", cp),
1767
1768 /* Ordinarily, this case should never happen,
1769 * but there is a bug in some released firmware
1770 * revisions that allows it to happen if, for
1771 * example, a 4100 backplane loses power and
1772 * the tape drive is in it. We assume that
1773 * it's a fatal error of some kind because we
1774 * can't show that it wasn't. We will make it
1775 * look like selection timeout since that is
1776 * the most common reason for this to occur,
1777 * and it's severe enough.
1778 */
1779
1780 cmd->result = DID_NO_CONNECT << 16;
1781 }
1782 break;
1783
1784 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
1785 break;
1786 case CMD_DATA_OVERRUN:
1787 dev_warn(&h->pdev->dev, "cp %p has"
1788 " completed with data overrun "
1789 "reported\n", cp);
1790 break;
1791 case CMD_INVALID: {
1792 /* print_bytes(cp, sizeof(*cp), 1, 0);
1793 print_cmd(cp); */
1794 /* We get CMD_INVALID if you address a non-existent device
1795 * instead of a selection timeout (no response). You will
1796 * see this if you yank out a drive, then try to access it.
1797 * This is kind of a shame because it means that any other
1798 * CMD_INVALID (e.g. driver bug) will get interpreted as a
1799 * missing target. */
1800 cmd->result = DID_NO_CONNECT << 16;
1801 }
1802 break;
1803 case CMD_PROTOCOL_ERR:
256d0eaa 1804 cmd->result = DID_ERROR << 16;
edd16368 1805 dev_warn(&h->pdev->dev, "cp %p has "
256d0eaa 1806 "protocol error\n", cp);
edd16368
SC		 1807 break;
1808 case CMD_HARDWARE_ERR:
1809 cmd->result = DID_ERROR << 16;
1810 dev_warn(&h->pdev->dev, "cp %p had hardware error\n", cp);
1811 break;
1812 case CMD_CONNECTION_LOST:
1813 cmd->result = DID_ERROR << 16;
1814 dev_warn(&h->pdev->dev, "cp %p had connection lost\n", cp);
1815 break;
1816 case CMD_ABORTED:
1817 cmd->result = DID_ABORT << 16;
1818 dev_warn(&h->pdev->dev, "cp %p was aborted with status 0x%x\n",
1819 cp, ei->ScsiStatus);
1820 break;
1821 case CMD_ABORT_FAILED:
1822 cmd->result = DID_ERROR << 16;
1823 dev_warn(&h->pdev->dev, "cp %p reports abort failed\n", cp);
1824 break;
1825 case CMD_UNSOLICITED_ABORT:
f6e76055
SC		 1826 cmd->result = DID_SOFT_ERROR << 16; /* retry the command */
1827 dev_warn(&h->pdev->dev, "cp %p aborted due to an unsolicited "
edd16368
SC		 1828 "abort\n", cp);
1829 break;
1830 case CMD_TIMEOUT:
1831 cmd->result = DID_TIME_OUT << 16;
1832 dev_warn(&h->pdev->dev, "cp %p timedout\n", cp);
1833 break;
1d5e2ed0
SC		 1834 case CMD_UNABORTABLE:
1835 cmd->result = DID_ERROR << 16;
1836 dev_warn(&h->pdev->dev, "Command unabortable\n");
1837 break;
283b4a9b
SC		 1838 case CMD_IOACCEL_DISABLED:
1839 /* This only handles the direct pass-through case since RAID
1840 * offload is handled above. Just attempt a retry.
1841 */
1842 cmd->result = DID_SOFT_ERROR << 16;
1843 dev_warn(&h->pdev->dev,
1844 "cp %p had HP SSD Smart Path error\n", cp);
1845 break;
edd16368
SC		 1846 default:
1847 cmd->result = DID_ERROR << 16;
1848 dev_warn(&h->pdev->dev, "cp %p returned unknown status %x\n",
1849 cp, ei->CommandStatus);
1850 }
edd16368 1851 cmd_free(h, cp);
2cc5bfaf 1852 cmd->scsi_done(cmd);
edd16368
SC		 1853}
1854
edd16368
SC		 1855static void hpsa_pci_unmap(struct pci_dev *pdev,
1856 struct CommandList *c, int sg_used, int data_direction)
1857{
1858 int i;
edd16368 1859
50a0decf
SC		 1860 for (i = 0; i < sg_used; i++)
1861 pci_unmap_single(pdev, (dma_addr_t) le64_to_cpu(c->SG[i].Addr),
1862 le32_to_cpu(c->SG[i].Len),
1863 data_direction);
edd16368
SC		 1864}
1865
a2dac136 1866static int hpsa_map_one(struct pci_dev *pdev,
edd16368
SC		 1867 struct CommandList *cp,
1868 unsigned char *buf,
1869 size_t buflen,
1870 int data_direction)
1871{
01a02ffc 1872 u64 addr64;
edd16368
SC		 1873
1874 if (buflen == 0 || data_direction == PCI_DMA_NONE) {
1875 cp->Header.SGList = 0;
50a0decf 1876 cp->Header.SGTotal = cpu_to_le16(0);
a2dac136 1877 return 0;
edd16368
SC		 1878 }
1879
50a0decf 1880 addr64 = pci_map_single(pdev, buf, buflen, data_direction);
eceaae18 1881 if (dma_mapping_error(&pdev->dev, addr64)) {
a2dac136 1882 /* Prevent subsequent unmap of something never mapped */
eceaae18 1883 cp->Header.SGList = 0;
50a0decf 1884 cp->Header.SGTotal = cpu_to_le16(0);
a2dac136 1885 return -1;
eceaae18 1886 }
50a0decf
SC		 1887 cp->SG[0].Addr = cpu_to_le64(addr64);
1888 cp->SG[0].Len = cpu_to_le32(buflen);
1889 cp->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* we are not chaining */
1890 cp->Header.SGList = 1; /* no. SGs contig in this cmd */
1891 cp->Header.SGTotal = cpu_to_le16(1); /* total sgs in cmd list */
a2dac136 1892 return 0;
edd16368
SC		 1893}
1894
1895static inline void hpsa_scsi_do_simple_cmd_core(struct ctlr_info *h,
1896 struct CommandList *c)
1897{
1898 DECLARE_COMPLETION_ONSTACK(wait);
1899
1900 c->waiting = &wait;
1901 enqueue_cmd_and_start_io(h, c);
1902 wait_for_completion(&wait);
1903}
1904
094963da
SC		 1905static u32 lockup_detected(struct ctlr_info *h)
1906{
1907 int cpu;
1908 u32 rc, *lockup_detected;
1909
1910 cpu = get_cpu();
1911 lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
1912 rc = *lockup_detected;
1913 put_cpu();
1914 return rc;
1915}
1916
a0c12413
SC		 1917static void hpsa_scsi_do_simple_cmd_core_if_no_lockup(struct ctlr_info *h,
1918 struct CommandList *c)
1919{
a0c12413 1920 /* If controller lockup detected, fake a hardware error. */
094963da 1921 if (unlikely(lockup_detected(h)))
a0c12413 1922 c->err_info->CommandStatus = CMD_HARDWARE_ERR;
094963da 1923 else
a0c12413 1924 hpsa_scsi_do_simple_cmd_core(h, c);
a0c12413
SC		 1925}
1926
9c2fc160 1927#define MAX_DRIVER_CMD_RETRIES 25
edd16368
SC		 1928static void hpsa_scsi_do_simple_cmd_with_retry(struct ctlr_info *h,
1929 struct CommandList *c, int data_direction)
1930{
9c2fc160 1931 int backoff_time = 10, retry_count = 0;
edd16368
SC		 1932
1933 do {
7630abd0 1934 memset(c->err_info, 0, sizeof(*c->err_info));
edd16368
SC		 1935 hpsa_scsi_do_simple_cmd_core(h, c);
1936 retry_count++;
9c2fc160
SC		 1937 if (retry_count > 3) {
1938 msleep(backoff_time);
1939 if (backoff_time < 1000)
1940 backoff_time *= 2;
1941 }
852af20a 1942 } while ((check_for_unit_attention(h, c) ||
9c2fc160
SC		 1943 check_for_busy(h, c)) &&
1944 retry_count <= MAX_DRIVER_CMD_RETRIES);
edd16368
SC		 1945 hpsa_pci_unmap(h->pdev, c, 1, data_direction);
1946}
1947
d1e8beac
SC		 1948static void hpsa_print_cmd(struct ctlr_info *h, char *txt,
1949 struct CommandList *c)
edd16368 1950{
d1e8beac
SC		 1951 const u8 *cdb = c->Request.CDB;
1952 const u8 *lun = c->Header.LUN.LunAddrBytes;
1953
1954 dev_warn(&h->pdev->dev, "%s: LUN:%02x%02x%02x%02x%02x%02x%02x%02x"
1955 " CDB:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\n",
1956 txt, lun[0], lun[1], lun[2], lun[3],
1957 lun[4], lun[5], lun[6], lun[7],
1958 cdb[0], cdb[1], cdb[2], cdb[3],
1959 cdb[4], cdb[5], cdb[6], cdb[7],
1960 cdb[8], cdb[9], cdb[10], cdb[11],
1961 cdb[12], cdb[13], cdb[14], cdb[15]);
1962}
1963
1964static void hpsa_scsi_interpret_error(struct ctlr_info *h,
1965 struct CommandList *cp)
1966{
1967 const struct ErrorInfo *ei = cp->err_info;
edd16368 1968 struct device *d = &cp->h->pdev->dev;
d1e8beac 1969 const u8 *sd = ei->SenseInfo;
edd16368 1970
edd16368
SC		 1971 switch (ei->CommandStatus) {
1972 case CMD_TARGET_STATUS:
d1e8beac
SC		 1973 hpsa_print_cmd(h, "SCSI status", cp);
1974 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION)
1975 dev_warn(d, "SCSI Status = 02, Sense key = %02x, ASC = %02x, ASCQ = %02x\n",
1976 sd[2] & 0x0f, sd[12], sd[13]);
1977 else
1978 dev_warn(d, "SCSI Status = %02x\n", ei->ScsiStatus);
edd16368
SC		 1979 if (ei->ScsiStatus == 0)
1980 dev_warn(d, "SCSI status is abnormally zero. "
1981 "(probably indicates selection timeout "
1982 "reported incorrectly due to a known "
1983 "firmware bug, circa July, 2001.)\n");
1984 break;
1985 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
edd16368
SC		 1986 break;
1987 case CMD_DATA_OVERRUN:
d1e8beac 1988 hpsa_print_cmd(h, "overrun condition", cp);
edd16368
SC		 1989 break;
1990 case CMD_INVALID: {
1991 /* controller unfortunately reports SCSI passthru's
1992 * to non-existent targets as invalid commands.
1993 */
d1e8beac
SC		 1994 hpsa_print_cmd(h, "invalid command", cp);
1995 dev_warn(d, "probably means device no longer present\n");
edd16368
SC		 1996 }
1997 break;
1998 case CMD_PROTOCOL_ERR:
d1e8beac 1999 hpsa_print_cmd(h, "protocol error", cp);
edd16368
SC		 2000 break;
2001 case CMD_HARDWARE_ERR:
d1e8beac 2002 hpsa_print_cmd(h, "hardware error", cp);
edd16368
SC		 2003 break;
2004 case CMD_CONNECTION_LOST:
d1e8beac 2005 hpsa_print_cmd(h, "connection lost", cp);
edd16368
SC		 2006 break;
2007 case CMD_ABORTED:
d1e8beac 2008 hpsa_print_cmd(h, "aborted", cp);
edd16368
SC		 2009 break;
2010 case CMD_ABORT_FAILED:
d1e8beac 2011 hpsa_print_cmd(h, "abort failed", cp);
edd16368
SC		 2012 break;
2013 case CMD_UNSOLICITED_ABORT:
d1e8beac 2014 hpsa_print_cmd(h, "unsolicited abort", cp);
edd16368
SC		 2015 break;
2016 case CMD_TIMEOUT:
d1e8beac 2017 hpsa_print_cmd(h, "timed out", cp);
edd16368 2018 break;
1d5e2ed0 2019 case CMD_UNABORTABLE:
d1e8beac 2020 hpsa_print_cmd(h, "unabortable", cp);
1d5e2ed0 2021 break;
edd16368 2022 default:
d1e8beac
SC		 2023 hpsa_print_cmd(h, "unknown status", cp);
2024 dev_warn(d, "Unknown command status %x\n",
edd16368
SC		 2025 ei->CommandStatus);
2026 }
2027}
2028
2029static int hpsa_scsi_do_inquiry(struct ctlr_info *h, unsigned char *scsi3addr,
b7bb24eb 2030 u16 page, unsigned char *buf,
edd16368
SC		 2031 unsigned char bufsize)
2032{
2033 int rc = IO_OK;
2034 struct CommandList *c;
2035 struct ErrorInfo *ei;
2036
45fcb86e 2037 c = cmd_alloc(h);
edd16368
SC		 2038
2039 if (c == NULL) { /* trouble... */
45fcb86e 2040 dev_warn(&h->pdev->dev, "cmd_alloc returned NULL!\n");
ecd9aad4 2041 return -ENOMEM;
edd16368
SC		 2042 }
2043
a2dac136
SC		 2044 if (fill_cmd(c, HPSA_INQUIRY, h, buf, bufsize,
2045 page, scsi3addr, TYPE_CMD)) {
2046 rc = -1;
2047 goto out;
2048 }
edd16368
SC		 2049 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
2050 ei = c->err_info;
2051 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2052 hpsa_scsi_interpret_error(h, c);
edd16368
SC		 2053 rc = -1;
2054 }
a2dac136 2055out:
45fcb86e 2056 cmd_free(h, c);
edd16368
SC		 2057 return rc;
2058}
2059
316b221a
SC		 2060static int hpsa_bmic_ctrl_mode_sense(struct ctlr_info *h,
2061 unsigned char *scsi3addr, unsigned char page,
2062 struct bmic_controller_parameters *buf, size_t bufsize)
2063{
2064 int rc = IO_OK;
2065 struct CommandList *c;
2066 struct ErrorInfo *ei;
2067
45fcb86e 2068 c = cmd_alloc(h);
316b221a 2069 if (c == NULL) { /* trouble... */
45fcb86e 2070 dev_warn(&h->pdev->dev, "cmd_alloc returned NULL!\n");
316b221a
SC		 2071 return -ENOMEM;
2072 }
2073
2074 if (fill_cmd(c, BMIC_SENSE_CONTROLLER_PARAMETERS, h, buf, bufsize,
2075 page, scsi3addr, TYPE_CMD)) {
2076 rc = -1;
2077 goto out;
2078 }
2079 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
2080 ei = c->err_info;
2081 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
2082 hpsa_scsi_interpret_error(h, c);
2083 rc = -1;
2084 }
2085out:
45fcb86e 2086 cmd_free(h, c);
316b221a
SC		 2087 return rc;
2088 }
2089
bf711ac6
ST		 2090static int hpsa_send_reset(struct ctlr_info *h, unsigned char *scsi3addr,
2091 u8 reset_type)
edd16368
SC		 2092{
2093 int rc = IO_OK;
2094 struct CommandList *c;
2095 struct ErrorInfo *ei;
2096
45fcb86e 2097 c = cmd_alloc(h);
edd16368
SC		 2098
2099 if (c == NULL) { /* trouble... */
45fcb86e 2100 dev_warn(&h->pdev->dev, "cmd_alloc returned NULL!\n");
e9ea04a6 2101 return -ENOMEM;
edd16368
SC		 2102 }
2103
a2dac136 2104 /* fill_cmd can't fail here, no data buffer to map. */
bf711ac6
ST		 2105 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
2106 scsi3addr, TYPE_MSG);
2107 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to LUN reset */
edd16368
SC		 2108 hpsa_scsi_do_simple_cmd_core(h, c);
2109 /* no unmap needed here because no data xfer. */
2110
2111 ei = c->err_info;
2112 if (ei->CommandStatus != 0) {
d1e8beac 2113 hpsa_scsi_interpret_error(h, c);
edd16368
SC		 2114 rc = -1;
2115 }
45fcb86e 2116 cmd_free(h, c);
edd16368
SC		 2117 return rc;
2118}
2119
2120static void hpsa_get_raid_level(struct ctlr_info *h,
2121 unsigned char *scsi3addr, unsigned char *raid_level)
2122{
2123 int rc;
2124 unsigned char *buf;
2125
2126 *raid_level = RAID_UNKNOWN;
2127 buf = kzalloc(64, GFP_KERNEL);
2128 if (!buf)
2129 return;
b7bb24eb 2130 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0xC1, buf, 64);
edd16368
SC		 2131 if (rc == 0)
2132 *raid_level = buf[8];
2133 if (*raid_level > RAID_UNKNOWN)
2134 *raid_level = RAID_UNKNOWN;
2135 kfree(buf);
2136 return;
2137}
2138
283b4a9b
SC		 2139#define HPSA_MAP_DEBUG
2140#ifdef HPSA_MAP_DEBUG
2141static void hpsa_debug_map_buff(struct ctlr_info *h, int rc,
2142 struct raid_map_data *map_buff)
2143{
2144 struct raid_map_disk_data *dd = &map_buff->data[0];
2145 int map, row, col;
2146 u16 map_cnt, row_cnt, disks_per_row;
2147
2148 if (rc != 0)
2149 return;
2150
2ba8bfc8
SC		 2151 /* Show details only if debugging has been activated. */
2152 if (h->raid_offload_debug < 2)
2153 return;
2154
283b4a9b
SC		 2155 dev_info(&h->pdev->dev, "structure_size = %u\n",
2156 le32_to_cpu(map_buff->structure_size));
2157 dev_info(&h->pdev->dev, "volume_blk_size = %u\n",
2158 le32_to_cpu(map_buff->volume_blk_size));
2159 dev_info(&h->pdev->dev, "volume_blk_cnt = 0x%llx\n",
2160 le64_to_cpu(map_buff->volume_blk_cnt));
2161 dev_info(&h->pdev->dev, "physicalBlockShift = %u\n",
2162 map_buff->phys_blk_shift);
2163 dev_info(&h->pdev->dev, "parity_rotation_shift = %u\n",
2164 map_buff->parity_rotation_shift);
2165 dev_info(&h->pdev->dev, "strip_size = %u\n",
2166 le16_to_cpu(map_buff->strip_size));
2167 dev_info(&h->pdev->dev, "disk_starting_blk = 0x%llx\n",
2168 le64_to_cpu(map_buff->disk_starting_blk));
2169 dev_info(&h->pdev->dev, "disk_blk_cnt = 0x%llx\n",
2170 le64_to_cpu(map_buff->disk_blk_cnt));
2171 dev_info(&h->pdev->dev, "data_disks_per_row = %u\n",
2172 le16_to_cpu(map_buff->data_disks_per_row));
2173 dev_info(&h->pdev->dev, "metadata_disks_per_row = %u\n",
2174 le16_to_cpu(map_buff->metadata_disks_per_row));
2175 dev_info(&h->pdev->dev, "row_cnt = %u\n",
2176 le16_to_cpu(map_buff->row_cnt));
2177 dev_info(&h->pdev->dev, "layout_map_count = %u\n",
2178 le16_to_cpu(map_buff->layout_map_count));
2b08b3e9 2179 dev_info(&h->pdev->dev, "flags = 0x%x\n",
dd0e19f3 2180 le16_to_cpu(map_buff->flags));
2b08b3e9
DB		 2181 dev_info(&h->pdev->dev, "encrypytion = %s\n",
2182 le16_to_cpu(map_buff->flags) &
2183 RAID_MAP_FLAG_ENCRYPT_ON ? "ON" : "OFF");
dd0e19f3
ST		 2184 dev_info(&h->pdev->dev, "dekindex = %u\n",
2185 le16_to_cpu(map_buff->dekindex));
283b4a9b
SC		 2186 map_cnt = le16_to_cpu(map_buff->layout_map_count);
2187 for (map = 0; map < map_cnt; map++) {
2188 dev_info(&h->pdev->dev, "Map%u:\n", map);
2189 row_cnt = le16_to_cpu(map_buff->row_cnt);
2190 for (row = 0; row < row_cnt; row++) {
2191 dev_info(&h->pdev->dev, " Row%u:\n", row);
2192 disks_per_row =
2193 le16_to_cpu(map_buff->data_disks_per_row);
2194 for (col = 0; col < disks_per_row; col++, dd++)
2195 dev_info(&h->pdev->dev,
2196 " D%02u: h=0x%04x xor=%u,%u\n",
2197 col, dd->ioaccel_handle,
2198 dd->xor_mult[0], dd->xor_mult[1]);
2199 disks_per_row =
2200 le16_to_cpu(map_buff->metadata_disks_per_row);
2201 for (col = 0; col < disks_per_row; col++, dd++)
2202 dev_info(&h->pdev->dev,
2203 " M%02u: h=0x%04x xor=%u,%u\n",
2204 col, dd->ioaccel_handle,
2205 dd->xor_mult[0], dd->xor_mult[1]);
2206 }
2207 }
2208}
2209#else
2210static void hpsa_debug_map_buff(__attribute__((unused)) struct ctlr_info *h,
2211 __attribute__((unused)) int rc,
2212 __attribute__((unused)) struct raid_map_data *map_buff)
2213{
2214}
2215#endif
2216
2217static int hpsa_get_raid_map(struct ctlr_info *h,
2218 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
2219{
2220 int rc = 0;
2221 struct CommandList *c;
2222 struct ErrorInfo *ei;
2223
45fcb86e 2224 c = cmd_alloc(h);
283b4a9b 2225 if (c == NULL) {
45fcb86e 2226 dev_warn(&h->pdev->dev, "cmd_alloc returned NULL!\n");
283b4a9b
SC		 2227 return -ENOMEM;
2228 }
2229 if (fill_cmd(c, HPSA_GET_RAID_MAP, h, &this_device->raid_map,
2230 sizeof(this_device->raid_map), 0,
2231 scsi3addr, TYPE_CMD)) {
2232 dev_warn(&h->pdev->dev, "Out of memory in hpsa_get_raid_map()\n");
45fcb86e 2233 cmd_free(h, c);
283b4a9b
SC		 2234 return -ENOMEM;
2235 }
2236 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
2237 ei = c->err_info;
2238 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2239 hpsa_scsi_interpret_error(h, c);
45fcb86e 2240 cmd_free(h, c);
283b4a9b
SC		 2241 return -1;
2242 }
45fcb86e 2243 cmd_free(h, c);
283b4a9b
SC		 2244
2245 /* @todo in the future, dynamically allocate RAID map memory */
2246 if (le32_to_cpu(this_device->raid_map.structure_size) >
2247 sizeof(this_device->raid_map)) {
2248 dev_warn(&h->pdev->dev, "RAID map size is too large!\n");
2249 rc = -1;
2250 }
2251 hpsa_debug_map_buff(h, rc, &this_device->raid_map);
2252 return rc;
2253}
2254
1b70150a
SC		 2255static int hpsa_vpd_page_supported(struct ctlr_info *h,
2256 unsigned char scsi3addr[], u8 page)
2257{
2258 int rc;
2259 int i;
2260 int pages;
2261 unsigned char *buf, bufsize;
2262
2263 buf = kzalloc(256, GFP_KERNEL);
2264 if (!buf)
2265 return 0;
2266
2267 /* Get the size of the page list first */
2268 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
2269 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
2270 buf, HPSA_VPD_HEADER_SZ);
2271 if (rc != 0)
2272 goto exit_unsupported;
2273 pages = buf[3];
2274 if ((pages + HPSA_VPD_HEADER_SZ) <= 255)
2275 bufsize = pages + HPSA_VPD_HEADER_SZ;
2276 else
2277 bufsize = 255;
2278
2279 /* Get the whole VPD page list */
2280 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
2281 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
2282 buf, bufsize);
2283 if (rc != 0)
2284 goto exit_unsupported;
2285
2286 pages = buf[3];
2287 for (i = 1; i <= pages; i++)
2288 if (buf[3 + i] == page)
2289 goto exit_supported;
2290exit_unsupported:
2291 kfree(buf);
2292 return 0;
2293exit_supported:
2294 kfree(buf);
2295 return 1;
2296}
2297
283b4a9b
SC		 2298static void hpsa_get_ioaccel_status(struct ctlr_info *h,
2299 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
2300{
2301 int rc;
2302 unsigned char *buf;
2303 u8 ioaccel_status;
2304
2305 this_device->offload_config = 0;
2306 this_device->offload_enabled = 0;
2307
2308 buf = kzalloc(64, GFP_KERNEL);
2309 if (!buf)
2310 return;
1b70150a
SC		 2311 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_IOACCEL_STATUS))
2312 goto out;
283b4a9b 2313 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
b7bb24eb 2314 VPD_PAGE | HPSA_VPD_LV_IOACCEL_STATUS, buf, 64);
283b4a9b
SC		 2315 if (rc != 0)
2316 goto out;
2317
2318#define IOACCEL_STATUS_BYTE 4
2319#define OFFLOAD_CONFIGURED_BIT 0x01
2320#define OFFLOAD_ENABLED_BIT 0x02
2321 ioaccel_status = buf[IOACCEL_STATUS_BYTE];
2322 this_device->offload_config =
2323 !!(ioaccel_status & OFFLOAD_CONFIGURED_BIT);
2324 if (this_device->offload_config) {
2325 this_device->offload_enabled =
2326 !!(ioaccel_status & OFFLOAD_ENABLED_BIT);
2327 if (hpsa_get_raid_map(h, scsi3addr, this_device))
2328 this_device->offload_enabled = 0;
2329 }
2330out:
2331 kfree(buf);
2332 return;
2333}
2334
edd16368
SC		 2335/* Get the device id from inquiry page 0x83 */
2336static int hpsa_get_device_id(struct ctlr_info *h, unsigned char *scsi3addr,
2337 unsigned char *device_id, int buflen)
2338{
2339 int rc;
2340 unsigned char *buf;
2341
2342 if (buflen > 16)
2343 buflen = 16;
2344 buf = kzalloc(64, GFP_KERNEL);
2345 if (!buf)
a84d794d 2346 return -ENOMEM;
b7bb24eb 2347 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0x83, buf, 64);
edd16368
SC		 2348 if (rc == 0)
2349 memcpy(device_id, &buf[8], buflen);
2350 kfree(buf);
2351 return rc != 0;
2352}
2353
2354static int hpsa_scsi_do_report_luns(struct ctlr_info *h, int logical,
2355 struct ReportLUNdata *buf, int bufsize,
2356 int extended_response)
2357{
2358 int rc = IO_OK;
2359 struct CommandList *c;
2360 unsigned char scsi3addr[8];
2361 struct ErrorInfo *ei;
2362
45fcb86e 2363 c = cmd_alloc(h);
edd16368 2364 if (c == NULL) { /* trouble... */
45fcb86e 2365 dev_err(&h->pdev->dev, "cmd_alloc returned NULL!\n");
edd16368
SC		 2366 return -1;
2367 }
e89c0ae7
SC		 2368 /* address the controller */
2369 memset(scsi3addr, 0, sizeof(scsi3addr));
a2dac136
SC		 2370 if (fill_cmd(c, logical ? HPSA_REPORT_LOG : HPSA_REPORT_PHYS, h,
2371 buf, bufsize, 0, scsi3addr, TYPE_CMD)) {
2372 rc = -1;
2373 goto out;
2374 }
edd16368
SC		 2375 if (extended_response)
2376 c->Request.CDB[1] = extended_response;
2377 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
2378 ei = c->err_info;
2379 if (ei->CommandStatus != 0 &&
2380 ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2381 hpsa_scsi_interpret_error(h, c);
edd16368 2382 rc = -1;
283b4a9b
SC		 2383 } else {
2384 if (buf->extended_response_flag != extended_response) {
2385 dev_err(&h->pdev->dev,
2386 "report luns requested format %u, got %u\n",
2387 extended_response,
2388 buf->extended_response_flag);
2389 rc = -1;
2390 }
edd16368 2391 }
a2dac136 2392out:
45fcb86e 2393 cmd_free(h, c);
edd16368
SC		 2394 return rc;
2395}
2396
2397static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h,
2398 struct ReportLUNdata *buf,
2399 int bufsize, int extended_response)
2400{
2401 return hpsa_scsi_do_report_luns(h, 0, buf, bufsize, extended_response);
2402}
2403
2404static inline int hpsa_scsi_do_report_log_luns(struct ctlr_info *h,
2405 struct ReportLUNdata *buf, int bufsize)
2406{
2407 return hpsa_scsi_do_report_luns(h, 1, buf, bufsize, 0);
2408}
2409
2410static inline void hpsa_set_bus_target_lun(struct hpsa_scsi_dev_t *device,
2411 int bus, int target, int lun)
2412{
2413 device->bus = bus;
2414 device->target = target;
2415 device->lun = lun;
2416}
2417
9846590e
SC		 2418/* Use VPD inquiry to get details of volume status */
2419static int hpsa_get_volume_status(struct ctlr_info *h,
2420 unsigned char scsi3addr[])
2421{
2422 int rc;
2423 int status;
2424 int size;
2425 unsigned char *buf;
2426
2427 buf = kzalloc(64, GFP_KERNEL);
2428 if (!buf)
2429 return HPSA_VPD_LV_STATUS_UNSUPPORTED;
2430
2431 /* Does controller have VPD for logical volume status? */
24a4b078 2432 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_STATUS))
9846590e 2433 goto exit_failed;
9846590e
SC		 2434
2435 /* Get the size of the VPD return buffer */
2436 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
2437 buf, HPSA_VPD_HEADER_SZ);
24a4b078 2438 if (rc != 0)
9846590e 2439 goto exit_failed;
9846590e
SC		 2440 size = buf[3];
2441
2442 /* Now get the whole VPD buffer */
2443 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
2444 buf, size + HPSA_VPD_HEADER_SZ);
24a4b078 2445 if (rc != 0)
9846590e 2446 goto exit_failed;
9846590e
SC		 2447 status = buf[4]; /* status byte */
2448
2449 kfree(buf);
2450 return status;
2451exit_failed:
2452 kfree(buf);
2453 return HPSA_VPD_LV_STATUS_UNSUPPORTED;
2454}
2455
2456/* Determine offline status of a volume.
2457 * Return either:
2458 * 0 (not offline)
67955ba3 2459 * 0xff (offline for unknown reasons)
9846590e
SC		 2460 * # (integer code indicating one of several NOT READY states
2461 * describing why a volume is to be kept offline)
2462 */
67955ba3 2463static int hpsa_volume_offline(struct ctlr_info *h,
9846590e
SC		 2464 unsigned char scsi3addr[])
2465{
2466 struct CommandList *c;
2467 unsigned char *sense, sense_key, asc, ascq;
2468 int ldstat = 0;
2469 u16 cmd_status;
2470 u8 scsi_status;
2471#define ASC_LUN_NOT_READY 0x04
2472#define ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS 0x04
2473#define ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ 0x02
2474
2475 c = cmd_alloc(h);
2476 if (!c)
2477 return 0;
2478 (void) fill_cmd(c, TEST_UNIT_READY, h, NULL, 0, 0, scsi3addr, TYPE_CMD);
2479 hpsa_scsi_do_simple_cmd_core(h, c);
2480 sense = c->err_info->SenseInfo;
2481 sense_key = sense[2];
2482 asc = sense[12];
2483 ascq = sense[13];
2484 cmd_status = c->err_info->CommandStatus;
2485 scsi_status = c->err_info->ScsiStatus;
2486 cmd_free(h, c);
2487 /* Is the volume 'not ready'? */
2488 if (cmd_status != CMD_TARGET_STATUS ||
2489 scsi_status != SAM_STAT_CHECK_CONDITION ||
2490 sense_key != NOT_READY ||
2491 asc != ASC_LUN_NOT_READY) {
2492 return 0;
2493 }
2494
2495 /* Determine the reason for not ready state */
2496 ldstat = hpsa_get_volume_status(h, scsi3addr);
2497
2498 /* Keep volume offline in certain cases: */
2499 switch (ldstat) {
2500 case HPSA_LV_UNDERGOING_ERASE:
2501 case HPSA_LV_UNDERGOING_RPI:
2502 case HPSA_LV_PENDING_RPI:
2503 case HPSA_LV_ENCRYPTED_NO_KEY:
2504 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
2505 case HPSA_LV_UNDERGOING_ENCRYPTION:
2506 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
2507 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
2508 return ldstat;
2509 case HPSA_VPD_LV_STATUS_UNSUPPORTED:
2510 /* If VPD status page isn't available,
2511 * use ASC/ASCQ to determine state
2512 */
2513 if ((ascq == ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS) ||
2514 (ascq == ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ))
2515 return ldstat;
2516 break;
2517 default:
2518 break;
2519 }
2520 return 0;
2521}
2522
edd16368 2523static int hpsa_update_device_info(struct ctlr_info *h,
0b0e1d6c
SC		 2524 unsigned char scsi3addr[], struct hpsa_scsi_dev_t *this_device,
2525 unsigned char *is_OBDR_device)
edd16368 2526{
0b0e1d6c
SC		 2527
2528#define OBDR_SIG_OFFSET 43
2529#define OBDR_TAPE_SIG "$DR-10"
2530#define OBDR_SIG_LEN (sizeof(OBDR_TAPE_SIG) - 1)
2531#define OBDR_TAPE_INQ_SIZE (OBDR_SIG_OFFSET + OBDR_SIG_LEN)
2532
ea6d3bc3 2533 unsigned char *inq_buff;
0b0e1d6c 2534 unsigned char *obdr_sig;
edd16368 2535
ea6d3bc3 2536 inq_buff = kzalloc(OBDR_TAPE_INQ_SIZE, GFP_KERNEL);
edd16368
SC		 2537 if (!inq_buff)
2538 goto bail_out;
2539
edd16368
SC		 2540 /* Do an inquiry to the device to see what it is. */
2541 if (hpsa_scsi_do_inquiry(h, scsi3addr, 0, inq_buff,
2542 (unsigned char) OBDR_TAPE_INQ_SIZE) != 0) {
2543 /* Inquiry failed (msg printed already) */
2544 dev_err(&h->pdev->dev,
2545 "hpsa_update_device_info: inquiry failed\n");
2546 goto bail_out;
2547 }
2548
edd16368
SC		 2549 this_device->devtype = (inq_buff[0] & 0x1f);
2550 memcpy(this_device->scsi3addr, scsi3addr, 8);
2551 memcpy(this_device->vendor, &inq_buff[8],
2552 sizeof(this_device->vendor));
2553 memcpy(this_device->model, &inq_buff[16],
2554 sizeof(this_device->model));
edd16368
SC		 2555 memset(this_device->device_id, 0,
2556 sizeof(this_device->device_id));
2557 hpsa_get_device_id(h, scsi3addr, this_device->device_id,
2558 sizeof(this_device->device_id));
2559
2560 if (this_device->devtype == TYPE_DISK &&
283b4a9b 2561 is_logical_dev_addr_mode(scsi3addr)) {
67955ba3
SC		 2562 int volume_offline;
2563
edd16368 2564 hpsa_get_raid_level(h, scsi3addr, &this_device->raid_level);
283b4a9b
SC		 2565 if (h->fw_support & MISC_FW_RAID_OFFLOAD_BASIC)
2566 hpsa_get_ioaccel_status(h, scsi3addr, this_device);
67955ba3
SC		 2567 volume_offline = hpsa_volume_offline(h, scsi3addr);
2568 if (volume_offline < 0 || volume_offline > 0xff)
2569 volume_offline = HPSA_VPD_LV_STATUS_UNSUPPORTED;
2570 this_device->volume_offline = volume_offline & 0xff;
283b4a9b 2571 } else {
edd16368 2572 this_device->raid_level = RAID_UNKNOWN;
283b4a9b
SC		 2573 this_device->offload_config = 0;
2574 this_device->offload_enabled = 0;
9846590e 2575 this_device->volume_offline = 0;
283b4a9b 2576 }
edd16368 2577
0b0e1d6c
SC		 2578 if (is_OBDR_device) {
2579 /* See if this is a One-Button-Disaster-Recovery device
2580 * by looking for "$DR-10" at offset 43 in inquiry data.
2581 */
2582 obdr_sig = &inq_buff[OBDR_SIG_OFFSET];
2583 *is_OBDR_device = (this_device->devtype == TYPE_ROM &&
2584 strncmp(obdr_sig, OBDR_TAPE_SIG,
2585 OBDR_SIG_LEN) == 0);
2586 }
2587
edd16368
SC		 2588 kfree(inq_buff);
2589 return 0;
2590
2591bail_out:
2592 kfree(inq_buff);
2593 return 1;
2594}
2595
4f4eb9f1 2596static unsigned char *ext_target_model[] = {
edd16368
SC		 2597 "MSA2012",
2598 "MSA2024",
2599 "MSA2312",
2600 "MSA2324",
fda38518 2601 "P2000 G3 SAS",
e06c8e5c 2602 "MSA 2040 SAS",
edd16368
SC		 2603 NULL,
2604};
2605
4f4eb9f1 2606static int is_ext_target(struct ctlr_info *h, struct hpsa_scsi_dev_t *device)
edd16368
SC		 2607{
2608 int i;
2609
4f4eb9f1
ST		 2610 for (i = 0; ext_target_model[i]; i++)
2611 if (strncmp(device->model, ext_target_model[i],
2612 strlen(ext_target_model[i])) == 0)
edd16368
SC		 2613 return 1;
2614 return 0;
2615}
2616
2617/* Helper function to assign bus, target, lun mapping of devices.
4f4eb9f1 2618 * Puts non-external target logical volumes on bus 0, external target logical
edd16368
SC		 2619 * volumes on bus 1, physical devices on bus 2. and the hba on bus 3.
2620 * Logical drive target and lun are assigned at this time, but
2621 * physical device lun and target assignment are deferred (assigned
2622 * in hpsa_find_target_lun, called by hpsa_scsi_add_entry.)
2623 */
2624static void figure_bus_target_lun(struct ctlr_info *h,
1f310bde 2625 u8 *lunaddrbytes, struct hpsa_scsi_dev_t *device)
edd16368 2626{
1f310bde
SC		 2627 u32 lunid = le32_to_cpu(*((__le32 *) lunaddrbytes));
2628
2629 if (!is_logical_dev_addr_mode(lunaddrbytes)) {
2630 /* physical device, target and lun filled in later */
edd16368 2631 if (is_hba_lunid(lunaddrbytes))
1f310bde 2632 hpsa_set_bus_target_lun(device, 3, 0, lunid & 0x3fff);
edd16368 2633 else
1f310bde
SC		 2634 /* defer target, lun assignment for physical devices */
2635 hpsa_set_bus_target_lun(device, 2, -1, -1);
2636 return;
2637 }
2638 /* It's a logical device */
4f4eb9f1
ST		 2639 if (is_ext_target(h, device)) {
2640 /* external target way, put logicals on bus 1
1f310bde
SC		 2641 * and match target/lun numbers box
2642 * reports, other smart array, bus 0, target 0, match lunid
2643 */
2644 hpsa_set_bus_target_lun(device,
2645 1, (lunid >> 16) & 0x3fff, lunid & 0x00ff);
2646 return;
edd16368 2647 }
1f310bde 2648 hpsa_set_bus_target_lun(device, 0, 0, lunid & 0x3fff);
edd16368
SC		 2649}
2650
2651/*
2652 * If there is no lun 0 on a target, linux won't find any devices.
4f4eb9f1 2653 * For the external targets (arrays), we have to manually detect the enclosure
edd16368
SC		 2654 * which is at lun zero, as CCISS_REPORT_PHYSICAL_LUNS doesn't report
2655 * it for some reason. *tmpdevice is the target we're adding,
2656 * this_device is a pointer into the current element of currentsd[]
2657 * that we're building up in update_scsi_devices(), below.
2658 * lunzerobits is a bitmap that tracks which targets already have a
2659 * lun 0 assigned.
2660 * Returns 1 if an enclosure was added, 0 if not.
2661 */
4f4eb9f1 2662static int add_ext_target_dev(struct ctlr_info *h,
edd16368 2663 struct hpsa_scsi_dev_t *tmpdevice,
01a02ffc 2664 struct hpsa_scsi_dev_t *this_device, u8 *lunaddrbytes,
4f4eb9f1 2665 unsigned long lunzerobits[], int *n_ext_target_devs)
edd16368
SC		 2666{
2667 unsigned char scsi3addr[8];
2668
1f310bde 2669 if (test_bit(tmpdevice->target, lunzerobits))
edd16368
SC		 2670 return 0; /* There is already a lun 0 on this target. */
2671
2672 if (!is_logical_dev_addr_mode(lunaddrbytes))
2673 return 0; /* It's the logical targets that may lack lun 0. */
2674
4f4eb9f1
ST		 2675 if (!is_ext_target(h, tmpdevice))
2676 return 0; /* Only external target devices have this problem. */
edd16368 2677
1f310bde 2678 if (tmpdevice->lun == 0) /* if lun is 0, then we have a lun 0. */
edd16368
SC		 2679 return 0;
2680
c4f8a299 2681 memset(scsi3addr, 0, 8);
1f310bde 2682 scsi3addr[3] = tmpdevice->target;
edd16368
SC		 2683 if (is_hba_lunid(scsi3addr))
2684 return 0; /* Don't add the RAID controller here. */
2685
339b2b14
SC		 2686 if (is_scsi_rev_5(h))
2687 return 0; /* p1210m doesn't need to do this. */
2688
4f4eb9f1 2689 if (*n_ext_target_devs >= MAX_EXT_TARGETS) {
aca4a520
ST		 2690 dev_warn(&h->pdev->dev, "Maximum number of external "
2691 "target devices exceeded. Check your hardware "
edd16368
SC		 2692 "configuration.");
2693 return 0;
2694 }
2695
0b0e1d6c 2696 if (hpsa_update_device_info(h, scsi3addr, this_device, NULL))
edd16368 2697 return 0;
4f4eb9f1 2698 (*n_ext_target_devs)++;
1f310bde
SC		 2699 hpsa_set_bus_target_lun(this_device,
2700 tmpdevice->bus, tmpdevice->target, 0);
2701 set_bit(tmpdevice->target, lunzerobits);
edd16368
SC		 2702 return 1;
2703}
2704
54b6e9e9
ST		 2705/*
2706 * Get address of physical disk used for an ioaccel2 mode command:
2707 * 1. Extract ioaccel2 handle from the command.
2708 * 2. Find a matching ioaccel2 handle from list of physical disks.
2709 * 3. Return:
2710 * 1 and set scsi3addr to address of matching physical
2711 * 0 if no matching physical disk was found.
2712 */
2713static int hpsa_get_pdisk_of_ioaccel2(struct ctlr_info *h,
2714 struct CommandList *ioaccel2_cmd_to_abort, unsigned char *scsi3addr)
2715{
2716 struct ReportExtendedLUNdata *physicals = NULL;
2717 int responsesize = 24; /* size of physical extended response */
2718 int extended = 2; /* flag forces reporting 'other dev info'. */
2719 int reportsize = sizeof(*physicals) + HPSA_MAX_PHYS_LUN * responsesize;
2720 u32 nphysicals = 0; /* number of reported physical devs */
2721 int found = 0; /* found match (1) or not (0) */
2722 u32 find; /* handle we need to match */
2723 int i;
2724 struct scsi_cmnd *scmd; /* scsi command within request being aborted */
2725 struct hpsa_scsi_dev_t *d; /* device of request being aborted */
2726 struct io_accel2_cmd *c2a; /* ioaccel2 command to abort */
2b08b3e9
DB		 2727 __le32 it_nexus; /* 4 byte device handle for the ioaccel2 cmd */
2728 __le32 scsi_nexus; /* 4 byte device handle for the ioaccel2 cmd */
54b6e9e9
ST		 2729
2730 if (ioaccel2_cmd_to_abort->cmd_type != CMD_IOACCEL2)
2731 return 0; /* no match */
2732
2733 /* point to the ioaccel2 device handle */
2734 c2a = &h->ioaccel2_cmd_pool[ioaccel2_cmd_to_abort->cmdindex];
2735 if (c2a == NULL)
2736 return 0; /* no match */
2737
2738 scmd = (struct scsi_cmnd *) ioaccel2_cmd_to_abort->scsi_cmd;
2739 if (scmd == NULL)
2740 return 0; /* no match */
2741
2742 d = scmd->device->hostdata;
2743 if (d == NULL)
2744 return 0; /* no match */
2745
50a0decf 2746 it_nexus = cpu_to_le32(d->ioaccel_handle);
2b08b3e9
DB		 2747 scsi_nexus = c2a->scsi_nexus;
2748 find = le32_to_cpu(c2a->scsi_nexus);
54b6e9e9 2749
2ba8bfc8
SC		 2750 if (h->raid_offload_debug > 0)
2751 dev_info(&h->pdev->dev,
2752 "%s: scsi_nexus:0x%08x device id: 0x%02x%02x%02x%02x %02x%02x%02x%02x %02x%02x%02x%02x %02x%02x%02x%02x\n",
2753 __func__, scsi_nexus,
2754 d->device_id[0], d->device_id[1], d->device_id[2],
2755 d->device_id[3], d->device_id[4], d->device_id[5],
2756 d->device_id[6], d->device_id[7], d->device_id[8],
2757 d->device_id[9], d->device_id[10], d->device_id[11],
2758 d->device_id[12], d->device_id[13], d->device_id[14],
2759 d->device_id[15]);
2760
54b6e9e9
ST		 2761 /* Get the list of physical devices */
2762 physicals = kzalloc(reportsize, GFP_KERNEL);
3b51a7a3
JH		 2763 if (physicals == NULL)
2764 return 0;
54b6e9e9
ST		 2765 if (hpsa_scsi_do_report_phys_luns(h, (struct ReportLUNdata *) physicals,
2766 reportsize, extended)) {
2767 dev_err(&h->pdev->dev,
2768 "Can't lookup %s device handle: report physical LUNs failed.\n",
2769 "HP SSD Smart Path");
2770 kfree(physicals);
2771 return 0;
2772 }
2773 nphysicals = be32_to_cpu(*((__be32 *)physicals->LUNListLength)) /
2774 responsesize;
2775
54b6e9e9
ST		 2776 /* find ioaccel2 handle in list of physicals: */
2777 for (i = 0; i < nphysicals; i++) {
d5b5d964
SC		 2778 struct ext_report_lun_entry *entry = &physicals->LUN[i];
2779
54b6e9e9 2780 /* handle is in bytes 28-31 of each lun */
d5b5d964 2781 if (entry->ioaccel_handle != find)
54b6e9e9 2782 continue; /* didn't match */
54b6e9e9 2783 found = 1;
d5b5d964 2784 memcpy(scsi3addr, entry->lunid, 8);
2ba8bfc8
SC		 2785 if (h->raid_offload_debug > 0)
2786 dev_info(&h->pdev->dev,
d5b5d964 2787 "%s: Searched h=0x%08x, Found h=0x%08x, scsiaddr 0x%8phN\n",
2ba8bfc8 2788 __func__, find,
d5b5d964 2789 entry->ioaccel_handle, scsi3addr);
54b6e9e9
ST		 2790 break; /* found it */
2791 }
2792
2793 kfree(physicals);
2794 if (found)
2795 return 1;
2796 else
2797 return 0;
2798
2799}
edd16368
SC		 2800/*
2801 * Do CISS_REPORT_PHYS and CISS_REPORT_LOG. Data is returned in physdev,
2802 * logdev. The number of luns in physdev and logdev are returned in
2803 * *nphysicals and *nlogicals, respectively.
2804 * Returns 0 on success, -1 otherwise.
2805 */
2806static int hpsa_gather_lun_info(struct ctlr_info *h,
92084715 2807 int reportphyslunsize, int reportloglunsize,
283b4a9b 2808 struct ReportLUNdata *physdev, u32 *nphysicals, int *physical_mode,
01a02ffc 2809 struct ReportLUNdata *logdev, u32 *nlogicals)
edd16368 2810{
283b4a9b
SC		 2811 int physical_entry_size = 8;
2812
2813 *physical_mode = 0;
2814
2815 /* For I/O accelerator mode we need to read physical device handles */
317d4adf
MM		 2816 if (h->transMethod & CFGTBL_Trans_io_accel1 ||
2817 h->transMethod & CFGTBL_Trans_io_accel2) {
283b4a9b
SC		 2818 *physical_mode = HPSA_REPORT_PHYS_EXTENDED;
2819 physical_entry_size = 24;
2820 }
92084715 2821 if (hpsa_scsi_do_report_phys_luns(h, physdev, reportphyslunsize,
283b4a9b 2822 *physical_mode)) {
edd16368
SC		 2823 dev_err(&h->pdev->dev, "report physical LUNs failed.\n");
2824 return -1;
2825 }
283b4a9b
SC		 2826 *nphysicals = be32_to_cpu(*((__be32 *)physdev->LUNListLength)) /
2827 physical_entry_size;
edd16368
SC		 2828 if (*nphysicals > HPSA_MAX_PHYS_LUN) {
2829 dev_warn(&h->pdev->dev, "maximum physical LUNs (%d) exceeded."
2830 " %d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
2831 *nphysicals - HPSA_MAX_PHYS_LUN);
2832 *nphysicals = HPSA_MAX_PHYS_LUN;
2833 }
92084715 2834 if (hpsa_scsi_do_report_log_luns(h, logdev, reportloglunsize)) {
edd16368
SC		 2835 dev_err(&h->pdev->dev, "report logical LUNs failed.\n");
2836 return -1;
2837 }
6df1e954 2838 *nlogicals = be32_to_cpu(*((__be32 *) logdev->LUNListLength)) / 8;
edd16368
SC		 2839 /* Reject Logicals in excess of our max capability. */
2840 if (*nlogicals > HPSA_MAX_LUN) {
2841 dev_warn(&h->pdev->dev,
2842 "maximum logical LUNs (%d) exceeded. "
2843 "%d LUNs ignored.\n", HPSA_MAX_LUN,
2844 *nlogicals - HPSA_MAX_LUN);
2845 *nlogicals = HPSA_MAX_LUN;
2846 }
2847 if (*nlogicals + *nphysicals > HPSA_MAX_PHYS_LUN) {
2848 dev_warn(&h->pdev->dev,
2849 "maximum logical + physical LUNs (%d) exceeded. "
2850 "%d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
2851 *nphysicals + *nlogicals - HPSA_MAX_PHYS_LUN);
2852 *nlogicals = HPSA_MAX_PHYS_LUN - *nphysicals;
2853 }
2854 return 0;
2855}
2856
42a91641
DB		 2857static u8 *figure_lunaddrbytes(struct ctlr_info *h, int raid_ctlr_position,
2858 int i, int nphysicals, int nlogicals,
a93aa1fe 2859 struct ReportExtendedLUNdata *physdev_list,
339b2b14
SC		 2860 struct ReportLUNdata *logdev_list)
2861{
2862 /* Helper function, figure out where the LUN ID info is coming from
2863 * given index i, lists of physical and logical devices, where in
2864 * the list the raid controller is supposed to appear (first or last)
2865 */
2866
2867 int logicals_start = nphysicals + (raid_ctlr_position == 0);
2868 int last_device = nphysicals + nlogicals + (raid_ctlr_position == 0);
2869
2870 if (i == raid_ctlr_position)
2871 return RAID_CTLR_LUNID;
2872
2873 if (i < logicals_start)
d5b5d964
SC		 2874 return &physdev_list->LUN[i -
2875 (raid_ctlr_position == 0)].lunid[0];
339b2b14
SC		 2876
2877 if (i < last_device)
2878 return &logdev_list->LUN[i - nphysicals -
2879 (raid_ctlr_position == 0)][0];
2880 BUG();
2881 return NULL;
2882}
2883
316b221a
SC		 2884static int hpsa_hba_mode_enabled(struct ctlr_info *h)
2885{
2886 int rc;
6e8e8088 2887 int hba_mode_enabled;
316b221a
SC		 2888 struct bmic_controller_parameters *ctlr_params;
2889 ctlr_params = kzalloc(sizeof(struct bmic_controller_parameters),
2890 GFP_KERNEL);
2891
2892 if (!ctlr_params)
96444fbb 2893 return -ENOMEM;
316b221a
SC		 2894 rc = hpsa_bmic_ctrl_mode_sense(h, RAID_CTLR_LUNID, 0, ctlr_params,
2895 sizeof(struct bmic_controller_parameters));
96444fbb 2896 if (rc) {
316b221a 2897 kfree(ctlr_params);
96444fbb 2898 return rc;
316b221a 2899 }
6e8e8088
JH		 2900
2901 hba_mode_enabled =
2902 ((ctlr_params->nvram_flags & HBA_MODE_ENABLED_FLAG) != 0);
2903 kfree(ctlr_params);
2904 return hba_mode_enabled;
316b221a
SC		 2905}
2906
edd16368
SC		 2907static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno)
2908{
2909 /* the idea here is we could get notified
2910 * that some devices have changed, so we do a report
2911 * physical luns and report logical luns cmd, and adjust
2912 * our list of devices accordingly.
2913 *
2914 * The scsi3addr's of devices won't change so long as the
2915 * adapter is not reset. That means we can rescan and
2916 * tell which devices we already know about, vs. new
2917 * devices, vs. disappearing devices.
2918 */
a93aa1fe 2919 struct ReportExtendedLUNdata *physdev_list = NULL;
edd16368 2920 struct ReportLUNdata *logdev_list = NULL;
01a02ffc
SC		 2921 u32 nphysicals = 0;
2922 u32 nlogicals = 0;
283b4a9b 2923 int physical_mode = 0;
01a02ffc 2924 u32 ndev_allocated = 0;
edd16368
SC		 2925 struct hpsa_scsi_dev_t **currentsd, *this_device, *tmpdevice;
2926 int ncurrent = 0;
4f4eb9f1 2927 int i, n_ext_target_devs, ndevs_to_allocate;
339b2b14 2928 int raid_ctlr_position;
2bbf5c7f 2929 int rescan_hba_mode;
aca4a520 2930 DECLARE_BITMAP(lunzerobits, MAX_EXT_TARGETS);
edd16368 2931
cfe5badc 2932 currentsd = kzalloc(sizeof(*currentsd) * HPSA_MAX_DEVICES, GFP_KERNEL);
92084715
SC		 2933 physdev_list = kzalloc(sizeof(*physdev_list), GFP_KERNEL);
2934 logdev_list = kzalloc(sizeof(*logdev_list), GFP_KERNEL);
edd16368
SC		 2935 tmpdevice = kzalloc(sizeof(*tmpdevice), GFP_KERNEL);
2936
0b0e1d6c 2937 if (!currentsd || !physdev_list || !logdev_list || !tmpdevice) {
edd16368
SC		 2938 dev_err(&h->pdev->dev, "out of memory\n");
2939 goto out;
2940 }
2941 memset(lunzerobits, 0, sizeof(lunzerobits));
2942
316b221a 2943 rescan_hba_mode = hpsa_hba_mode_enabled(h);
96444fbb
JH		 2944 if (rescan_hba_mode < 0)
2945 goto out;
316b221a
SC		 2946
2947 if (!h->hba_mode_enabled && rescan_hba_mode)
2948 dev_warn(&h->pdev->dev, "HBA mode enabled\n");
2949 else if (h->hba_mode_enabled && !rescan_hba_mode)
2950 dev_warn(&h->pdev->dev, "HBA mode disabled\n");
2951
2952 h->hba_mode_enabled = rescan_hba_mode;
2953
92084715
SC		 2954 if (hpsa_gather_lun_info(h,
2955 sizeof(*physdev_list), sizeof(*logdev_list),
a93aa1fe 2956 (struct ReportLUNdata *) physdev_list, &nphysicals,
283b4a9b 2957 &physical_mode, logdev_list, &nlogicals))
edd16368
SC		 2958 goto out;
2959
aca4a520
ST		 2960 /* We might see up to the maximum number of logical and physical disks
2961 * plus external target devices, and a device for the local RAID
2962 * controller.
edd16368 2963 */
aca4a520 2964 ndevs_to_allocate = nphysicals + nlogicals + MAX_EXT_TARGETS + 1;
edd16368
SC		 2965
2966 /* Allocate the per device structures */
2967 for (i = 0; i < ndevs_to_allocate; i++) {
b7ec021f
ST		 2968 if (i >= HPSA_MAX_DEVICES) {
2969 dev_warn(&h->pdev->dev, "maximum devices (%d) exceeded."
2970 " %d devices ignored.\n", HPSA_MAX_DEVICES,
2971 ndevs_to_allocate - HPSA_MAX_DEVICES);
2972 break;
2973 }
2974
edd16368
SC		 2975 currentsd[i] = kzalloc(sizeof(*currentsd[i]), GFP_KERNEL);
2976 if (!currentsd[i]) {
2977 dev_warn(&h->pdev->dev, "out of memory at %s:%d\n",
2978 __FILE__, __LINE__);
2979 goto out;
2980 }
2981 ndev_allocated++;
2982 }
2983
8645291b 2984 if (is_scsi_rev_5(h))
339b2b14
SC		 2985 raid_ctlr_position = 0;
2986 else
2987 raid_ctlr_position = nphysicals + nlogicals;
2988
edd16368 2989 /* adjust our table of devices */
4f4eb9f1 2990 n_ext_target_devs = 0;
edd16368 2991 for (i = 0; i < nphysicals + nlogicals + 1; i++) {
0b0e1d6c 2992 u8 *lunaddrbytes, is_OBDR = 0;
edd16368
SC		 2993
2994 /* Figure out where the LUN ID info is coming from */
339b2b14
SC		 2995 lunaddrbytes = figure_lunaddrbytes(h, raid_ctlr_position,
2996 i, nphysicals, nlogicals, physdev_list, logdev_list);
edd16368 2997 /* skip masked physical devices. */
339b2b14
SC		 2998 if (lunaddrbytes[3] & 0xC0 &&
2999 i < nphysicals + (raid_ctlr_position == 0))
edd16368
SC		 3000 continue;
3001
3002 /* Get device type, vendor, model, device id */
0b0e1d6c
SC		 3003 if (hpsa_update_device_info(h, lunaddrbytes, tmpdevice,
3004 &is_OBDR))
edd16368 3005 continue; /* skip it if we can't talk to it. */
1f310bde 3006 figure_bus_target_lun(h, lunaddrbytes, tmpdevice);
edd16368
SC		 3007 this_device = currentsd[ncurrent];
3008
3009 /*
4f4eb9f1 3010 * For external target devices, we have to insert a LUN 0 which
edd16368
SC		 3011 * doesn't show up in CCISS_REPORT_PHYSICAL data, but there
3012 * is nonetheless an enclosure device there. We have to
3013 * present that otherwise linux won't find anything if
3014 * there is no lun 0.
3015 */
4f4eb9f1 3016 if (add_ext_target_dev(h, tmpdevice, this_device,
1f310bde 3017 lunaddrbytes, lunzerobits,
4f4eb9f1 3018 &n_ext_target_devs)) {
edd16368
SC		 3019 ncurrent++;
3020 this_device = currentsd[ncurrent];
3021 }
3022
3023 *this_device = *tmpdevice;
edd16368
SC		 3024
3025 switch (this_device->devtype) {
0b0e1d6c 3026 case TYPE_ROM:
edd16368
SC		 3027 /* We don't *really* support actual CD-ROM devices,
3028 * just "One Button Disaster Recovery" tape drive
3029 * which temporarily pretends to be a CD-ROM drive.
3030 * So we check that the device is really an OBDR tape
3031 * device by checking for "$DR-10" in bytes 43-48 of
3032 * the inquiry data.
3033 */
0b0e1d6c
SC		 3034 if (is_OBDR)
3035 ncurrent++;
edd16368
SC		 3036 break;
3037 case TYPE_DISK:
316b221a
SC		 3038 if (h->hba_mode_enabled) {
3039 /* never use raid mapper in HBA mode */
3040 this_device->offload_enabled = 0;
3041 ncurrent++;
3042 break;
3043 } else if (h->acciopath_status) {
3044 if (i >= nphysicals) {
3045 ncurrent++;
3046 break;
3047 }
3048 } else {
3049 if (i < nphysicals)
3050 break;
283b4a9b 3051 ncurrent++;
edd16368 3052 break;
283b4a9b
SC		 3053 }
3054 if (physical_mode == HPSA_REPORT_PHYS_EXTENDED) {
3055 memcpy(&this_device->ioaccel_handle,
3056 &lunaddrbytes[20],
3057 sizeof(this_device->ioaccel_handle));
3058 ncurrent++;
3059 }
edd16368
SC		 3060 break;
3061 case TYPE_TAPE:
3062 case TYPE_MEDIUM_CHANGER:
3063 ncurrent++;
3064 break;
3065 case TYPE_RAID:
3066 /* Only present the Smartarray HBA as a RAID controller.
3067 * If it's a RAID controller other than the HBA itself
3068 * (an external RAID controller, MSA500 or similar)
3069 * don't present it.
3070 */
3071 if (!is_hba_lunid(lunaddrbytes))
3072 break;
3073 ncurrent++;
3074 break;
3075 default:
3076 break;
3077 }
cfe5badc 3078 if (ncurrent >= HPSA_MAX_DEVICES)
edd16368
SC		 3079 break;
3080 }
3081 adjust_hpsa_scsi_table(h, hostno, currentsd, ncurrent);
3082out:
3083 kfree(tmpdevice);
3084 for (i = 0; i < ndev_allocated; i++)
3085 kfree(currentsd[i]);
3086 kfree(currentsd);
edd16368
SC		 3087 kfree(physdev_list);
3088 kfree(logdev_list);
edd16368
SC		 3089}
3090
c7ee65b3
WS		 3091/*
3092 * hpsa_scatter_gather takes a struct scsi_cmnd, (cmd), and does the pci
edd16368
SC		 3093 * dma mapping and fills in the scatter gather entries of the
3094 * hpsa command, cp.
3095 */
33a2ffce 3096static int hpsa_scatter_gather(struct ctlr_info *h,
edd16368
SC		 3097 struct CommandList *cp,
3098 struct scsi_cmnd *cmd)
3099{
3100 unsigned int len;
3101 struct scatterlist *sg;
01a02ffc 3102 u64 addr64;
33a2ffce
SC		 3103 int use_sg, i, sg_index, chained;
3104 struct SGDescriptor *curr_sg;
edd16368 3105
33a2ffce 3106 BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
edd16368
SC		 3107
3108 use_sg = scsi_dma_map(cmd);
3109 if (use_sg < 0)
3110 return use_sg;
3111
3112 if (!use_sg)
3113 goto sglist_finished;
3114
33a2ffce
SC		 3115 curr_sg = cp->SG;
3116 chained = 0;
3117 sg_index = 0;
edd16368 3118 scsi_for_each_sg(cmd, sg, use_sg, i) {
33a2ffce
SC		 3119 if (i == h->max_cmd_sg_entries - 1 &&
3120 use_sg > h->max_cmd_sg_entries) {
3121 chained = 1;
3122 curr_sg = h->cmd_sg_list[cp->cmdindex];
3123 sg_index = 0;
3124 }
01a02ffc 3125 addr64 = (u64) sg_dma_address(sg);
edd16368 3126 len = sg_dma_len(sg);
50a0decf
SC		 3127 curr_sg->Addr = cpu_to_le64(addr64);
3128 curr_sg->Len = cpu_to_le32(len);
3129 curr_sg->Ext = cpu_to_le32(0);
33a2ffce
SC		 3130 curr_sg++;
3131 }
50a0decf 3132 (--curr_sg)->Ext = cpu_to_le32(HPSA_SG_LAST);
33a2ffce
SC		 3133
3134 if (use_sg + chained > h->maxSG)
3135 h->maxSG = use_sg + chained;
3136
3137 if (chained) {
3138 cp->Header.SGList = h->max_cmd_sg_entries;
50a0decf 3139 cp->Header.SGTotal = cpu_to_le16(use_sg + 1);
e2bea6df
SC		 3140 if (hpsa_map_sg_chain_block(h, cp)) {
3141 scsi_dma_unmap(cmd);
3142 return -1;
3143 }
33a2ffce 3144 return 0;
edd16368
SC		 3145 }
3146
3147sglist_finished:
3148
01a02ffc 3149 cp->Header.SGList = (u8) use_sg; /* no. SGs contig in this cmd */
c7ee65b3 3150 cp->Header.SGTotal = cpu_to_le16(use_sg); /* total sgs in cmd list */
edd16368
SC		 3151 return 0;
3152}
3153
283b4a9b
SC		 3154#define IO_ACCEL_INELIGIBLE (1)
3155static int fixup_ioaccel_cdb(u8 *cdb, int *cdb_len)
3156{
3157 int is_write = 0;
3158 u32 block;
3159 u32 block_cnt;
3160
3161 /* Perform some CDB fixups if needed using 10 byte reads/writes only */
3162 switch (cdb[0]) {
3163 case WRITE_6:
3164 case WRITE_12:
3165 is_write = 1;
3166 case READ_6:
3167 case READ_12:
3168 if (*cdb_len == 6) {
3169 block = (((u32) cdb[2]) << 8) | cdb[3];
3170 block_cnt = cdb[4];
3171 } else {
3172 BUG_ON(*cdb_len != 12);
3173 block = (((u32) cdb[2]) << 24) |
3174 (((u32) cdb[3]) << 16) |
3175 (((u32) cdb[4]) << 8) |
3176 cdb[5];
3177 block_cnt =
3178 (((u32) cdb[6]) << 24) |
3179 (((u32) cdb[7]) << 16) |
3180 (((u32) cdb[8]) << 8) |
3181 cdb[9];
3182 }
3183 if (block_cnt > 0xffff)
3184 return IO_ACCEL_INELIGIBLE;
3185
3186 cdb[0] = is_write ? WRITE_10 : READ_10;
3187 cdb[1] = 0;
3188 cdb[2] = (u8) (block >> 24);
3189 cdb[3] = (u8) (block >> 16);
3190 cdb[4] = (u8) (block >> 8);
3191 cdb[5] = (u8) (block);
3192 cdb[6] = 0;
3193 cdb[7] = (u8) (block_cnt >> 8);
3194 cdb[8] = (u8) (block_cnt);
3195 cdb[9] = 0;
3196 *cdb_len = 10;
3197 break;
3198 }
3199 return 0;
3200}
3201
c349775e 3202static int hpsa_scsi_ioaccel1_queue_command(struct ctlr_info *h,
283b4a9b
SC		 3203 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
3204 u8 *scsi3addr)
e1f7de0c
MG		 3205{
3206 struct scsi_cmnd *cmd = c->scsi_cmd;
e1f7de0c
MG		 3207 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
3208 unsigned int len;
3209 unsigned int total_len = 0;
3210 struct scatterlist *sg;
3211 u64 addr64;
3212 int use_sg, i;
3213 struct SGDescriptor *curr_sg;
3214 u32 control = IOACCEL1_CONTROL_SIMPLEQUEUE;
3215
283b4a9b
SC		 3216 /* TODO: implement chaining support */
3217 if (scsi_sg_count(cmd) > h->ioaccel_maxsg)
3218 return IO_ACCEL_INELIGIBLE;
3219
e1f7de0c
MG		 3220 BUG_ON(cmd->cmd_len > IOACCEL1_IOFLAGS_CDBLEN_MAX);
3221
283b4a9b
SC		 3222 if (fixup_ioaccel_cdb(cdb, &cdb_len))
3223 return IO_ACCEL_INELIGIBLE;
3224
e1f7de0c
MG		 3225 c->cmd_type = CMD_IOACCEL1;
3226
3227 /* Adjust the DMA address to point to the accelerated command buffer */
3228 c->busaddr = (u32) h->ioaccel_cmd_pool_dhandle +
3229 (c->cmdindex * sizeof(*cp));
3230 BUG_ON(c->busaddr & 0x0000007F);
3231
3232 use_sg = scsi_dma_map(cmd);
3233 if (use_sg < 0)
3234 return use_sg;
3235
3236 if (use_sg) {
3237 curr_sg = cp->SG;
3238 scsi_for_each_sg(cmd, sg, use_sg, i) {
3239 addr64 = (u64) sg_dma_address(sg);
3240 len = sg_dma_len(sg);
3241 total_len += len;
50a0decf
SC		 3242 curr_sg->Addr = cpu_to_le64(addr64);
3243 curr_sg->Len = cpu_to_le32(len);
3244 curr_sg->Ext = cpu_to_le32(0);
e1f7de0c
MG		 3245 curr_sg++;
3246 }
50a0decf 3247 (--curr_sg)->Ext = cpu_to_le32(HPSA_SG_LAST);
e1f7de0c
MG		 3248
3249 switch (cmd->sc_data_direction) {
3250 case DMA_TO_DEVICE:
3251 control |= IOACCEL1_CONTROL_DATA_OUT;
3252 break;
3253 case DMA_FROM_DEVICE:
3254 control |= IOACCEL1_CONTROL_DATA_IN;
3255 break;
3256 case DMA_NONE:
3257 control |= IOACCEL1_CONTROL_NODATAXFER;
3258 break;
3259 default:
3260 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
3261 cmd->sc_data_direction);
3262 BUG();
3263 break;
3264 }
3265 } else {
3266 control |= IOACCEL1_CONTROL_NODATAXFER;
3267 }
3268
c349775e 3269 c->Header.SGList = use_sg;
e1f7de0c 3270 /* Fill out the command structure to submit */
2b08b3e9
DB		 3271 cp->dev_handle = cpu_to_le16(ioaccel_handle & 0xFFFF);
3272 cp->transfer_len = cpu_to_le32(total_len);
3273 cp->io_flags = cpu_to_le16(IOACCEL1_IOFLAGS_IO_REQ |
3274 (cdb_len & IOACCEL1_IOFLAGS_CDBLEN_MASK));
3275 cp->control = cpu_to_le32(control);
283b4a9b
SC		 3276 memcpy(cp->CDB, cdb, cdb_len);
3277 memcpy(cp->CISS_LUN, scsi3addr, 8);
c349775e 3278 /* Tag was already set at init time. */
283b4a9b 3279 enqueue_cmd_and_start_io(h, c);
e1f7de0c
MG		 3280 return 0;
3281}
edd16368 3282
283b4a9b
SC		 3283/*
3284 * Queue a command directly to a device behind the controller using the
3285 * I/O accelerator path.
3286 */
3287static int hpsa_scsi_ioaccel_direct_map(struct ctlr_info *h,
3288 struct CommandList *c)
3289{
3290 struct scsi_cmnd *cmd = c->scsi_cmd;
3291 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
3292
3293 return hpsa_scsi_ioaccel_queue_command(h, c, dev->ioaccel_handle,
3294 cmd->cmnd, cmd->cmd_len, dev->scsi3addr);
3295}
3296
dd0e19f3
ST		 3297/*
3298 * Set encryption parameters for the ioaccel2 request
3299 */
3300static void set_encrypt_ioaccel2(struct ctlr_info *h,
3301 struct CommandList *c, struct io_accel2_cmd *cp)
3302{
3303 struct scsi_cmnd *cmd = c->scsi_cmd;
3304 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
3305 struct raid_map_data *map = &dev->raid_map;
3306 u64 first_block;
3307
3308 BUG_ON(!(dev->offload_config && dev->offload_enabled));
3309
3310 /* Are we doing encryption on this device */
2b08b3e9 3311 if (!(le16_to_cpu(map->flags) & RAID_MAP_FLAG_ENCRYPT_ON))
dd0e19f3
ST		 3312 return;
3313 /* Set the data encryption key index. */
3314 cp->dekindex = map->dekindex;
3315
3316 /* Set the encryption enable flag, encoded into direction field. */
3317 cp->direction |= IOACCEL2_DIRECTION_ENCRYPT_MASK;
3318
3319 /* Set encryption tweak values based on logical block address
3320 * If block size is 512, tweak value is LBA.
3321 * For other block sizes, tweak is (LBA * block size)/ 512)
3322 */
3323 switch (cmd->cmnd[0]) {
3324 /* Required? 6-byte cdbs eliminated by fixup_ioaccel_cdb */
3325 case WRITE_6:
3326 case READ_6:
2b08b3e9 3327 first_block = get_unaligned_be16(&cmd->cmnd[2]);
dd0e19f3
ST		 3328 break;
3329 case WRITE_10:
3330 case READ_10:
dd0e19f3
ST		 3331 /* Required? 12-byte cdbs eliminated by fixup_ioaccel_cdb */
3332 case WRITE_12:
3333 case READ_12:
2b08b3e9 3334 first_block = get_unaligned_be32(&cmd->cmnd[2]);
dd0e19f3
ST		 3335 break;
3336 case WRITE_16:
3337 case READ_16:
2b08b3e9 3338 first_block = get_unaligned_be64(&cmd->cmnd[2]);
dd0e19f3
ST		 3339 break;
3340 default:
3341 dev_err(&h->pdev->dev,
2b08b3e9
DB		 3342 "ERROR: %s: size (0x%x) not supported for encryption\n",
3343 __func__, cmd->cmnd[0]);
dd0e19f3
ST		 3344 BUG();
3345 break;
3346 }
2b08b3e9
DB		 3347
3348 if (le32_to_cpu(map->volume_blk_size) != 512)
3349 first_block = first_block *
3350 le32_to_cpu(map->volume_blk_size)/512;
3351
3352 cp->tweak_lower = cpu_to_le32(first_block);
3353 cp->tweak_upper = cpu_to_le32(first_block >> 32);
dd0e19f3
ST		 3354}
3355
c349775e
ST		 3356static int hpsa_scsi_ioaccel2_queue_command(struct ctlr_info *h,
3357 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
3358 u8 *scsi3addr)
3359{
3360 struct scsi_cmnd *cmd = c->scsi_cmd;
3361 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
3362 struct ioaccel2_sg_element *curr_sg;
3363 int use_sg, i;
3364 struct scatterlist *sg;
3365 u64 addr64;
3366 u32 len;
3367 u32 total_len = 0;
3368
3369 if (scsi_sg_count(cmd) > h->ioaccel_maxsg)
3370 return IO_ACCEL_INELIGIBLE;
3371
3372 if (fixup_ioaccel_cdb(cdb, &cdb_len))
3373 return IO_ACCEL_INELIGIBLE;
3374 c->cmd_type = CMD_IOACCEL2;
3375 /* Adjust the DMA address to point to the accelerated command buffer */
3376 c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle +
3377 (c->cmdindex * sizeof(*cp));
3378 BUG_ON(c->busaddr & 0x0000007F);
3379
3380 memset(cp, 0, sizeof(*cp));
3381 cp->IU_type = IOACCEL2_IU_TYPE;
3382
3383 use_sg = scsi_dma_map(cmd);
3384 if (use_sg < 0)
3385 return use_sg;
3386
3387 if (use_sg) {
3388 BUG_ON(use_sg > IOACCEL2_MAXSGENTRIES);
3389 curr_sg = cp->sg;
3390 scsi_for_each_sg(cmd, sg, use_sg, i) {
3391 addr64 = (u64) sg_dma_address(sg);
3392 len = sg_dma_len(sg);
3393 total_len += len;
3394 curr_sg->address = cpu_to_le64(addr64);
3395 curr_sg->length = cpu_to_le32(len);
3396 curr_sg->reserved[0] = 0;
3397 curr_sg->reserved[1] = 0;
3398 curr_sg->reserved[2] = 0;
3399 curr_sg->chain_indicator = 0;
3400 curr_sg++;
3401 }
3402
3403 switch (cmd->sc_data_direction) {
3404 case DMA_TO_DEVICE:
dd0e19f3
ST		 3405 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3406 cp->direction |= IOACCEL2_DIR_DATA_OUT;
c349775e
ST		 3407 break;
3408 case DMA_FROM_DEVICE:
dd0e19f3
ST		 3409 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3410 cp->direction |= IOACCEL2_DIR_DATA_IN;
c349775e
ST		 3411 break;
3412 case DMA_NONE:
dd0e19f3
ST		 3413 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3414 cp->direction |= IOACCEL2_DIR_NO_DATA;
c349775e
ST		 3415 break;
3416 default:
3417 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
3418 cmd->sc_data_direction);
3419 BUG();
3420 break;
3421 }
3422 } else {
dd0e19f3
ST		 3423 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3424 cp->direction |= IOACCEL2_DIR_NO_DATA;
c349775e 3425 }
dd0e19f3
ST		 3426
3427 /* Set encryption parameters, if necessary */
3428 set_encrypt_ioaccel2(h, c, cp);
3429
2b08b3e9 3430 cp->scsi_nexus = cpu_to_le32(ioaccel_handle);
f2405db8 3431 cp->Tag = cpu_to_le32(c->cmdindex << DIRECT_LOOKUP_SHIFT);
c349775e 3432 memcpy(cp->cdb, cdb, sizeof(cp->cdb));
c349775e
ST		 3433
3434 /* fill in sg elements */
3435 cp->sg_count = (u8) use_sg;
3436
3437 cp->data_len = cpu_to_le32(total_len);
3438 cp->err_ptr = cpu_to_le64(c->busaddr +
3439 offsetof(struct io_accel2_cmd, error_data));
50a0decf 3440 cp->err_len = cpu_to_le32(sizeof(cp->error_data));
c349775e
ST		 3441
3442 enqueue_cmd_and_start_io(h, c);
3443 return 0;
3444}
3445
3446/*
3447 * Queue a command to the correct I/O accelerator path.
3448 */
3449static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
3450 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
3451 u8 *scsi3addr)
3452{
3453 if (h->transMethod & CFGTBL_Trans_io_accel1)
3454 return hpsa_scsi_ioaccel1_queue_command(h, c, ioaccel_handle,
3455 cdb, cdb_len, scsi3addr);
3456 else
3457 return hpsa_scsi_ioaccel2_queue_command(h, c, ioaccel_handle,
3458 cdb, cdb_len, scsi3addr);
3459}
3460
6b80b18f
ST		 3461static void raid_map_helper(struct raid_map_data *map,
3462 int offload_to_mirror, u32 *map_index, u32 *current_group)
3463{
3464 if (offload_to_mirror == 0) {
3465 /* use physical disk in the first mirrored group. */
2b08b3e9 3466 *map_index %= le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 3467 return;
3468 }
3469 do {
3470 /* determine mirror group that *map_index indicates */
2b08b3e9
DB		 3471 *current_group = *map_index /
3472 le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 3473 if (offload_to_mirror == *current_group)
3474 continue;
2b08b3e9 3475 if (*current_group < le16_to_cpu(map->layout_map_count) - 1) {
6b80b18f 3476 /* select map index from next group */
2b08b3e9 3477 *map_index += le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 3478 (*current_group)++;
3479 } else {
3480 /* select map index from first group */
2b08b3e9 3481 *map_index %= le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 3482 *current_group = 0;
3483 }
3484 } while (offload_to_mirror != *current_group);
3485}
3486
283b4a9b
SC		 3487/*
3488 * Attempt to perform offload RAID mapping for a logical volume I/O.
3489 */
3490static int hpsa_scsi_ioaccel_raid_map(struct ctlr_info *h,
3491 struct CommandList *c)
3492{
3493 struct scsi_cmnd *cmd = c->scsi_cmd;
3494 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
3495 struct raid_map_data *map = &dev->raid_map;
3496 struct raid_map_disk_data *dd = &map->data[0];
3497 int is_write = 0;
3498 u32 map_index;
3499 u64 first_block, last_block;
3500 u32 block_cnt;
3501 u32 blocks_per_row;
3502 u64 first_row, last_row;
3503 u32 first_row_offset, last_row_offset;
3504 u32 first_column, last_column;
6b80b18f
ST		 3505 u64 r0_first_row, r0_last_row;
3506 u32 r5or6_blocks_per_row;
3507 u64 r5or6_first_row, r5or6_last_row;
3508 u32 r5or6_first_row_offset, r5or6_last_row_offset;
3509 u32 r5or6_first_column, r5or6_last_column;
3510 u32 total_disks_per_row;
3511 u32 stripesize;
3512 u32 first_group, last_group, current_group;
283b4a9b
SC		 3513 u32 map_row;
3514 u32 disk_handle;
3515 u64 disk_block;
3516 u32 disk_block_cnt;
3517 u8 cdb[16];
3518 u8 cdb_len;
2b08b3e9 3519 u16 strip_size;
283b4a9b
SC		 3520#if BITS_PER_LONG == 32
3521 u64 tmpdiv;
3522#endif
6b80b18f 3523 int offload_to_mirror;
283b4a9b
SC		 3524
3525 BUG_ON(!(dev->offload_config && dev->offload_enabled));
3526
3527 /* check for valid opcode, get LBA and block count */
3528 switch (cmd->cmnd[0]) {
3529 case WRITE_6:
3530 is_write = 1;
3531 case READ_6:
3532 first_block =
3533 (((u64) cmd->cmnd[2]) << 8) |
3534 cmd->cmnd[3];
3535 block_cnt = cmd->cmnd[4];
3fa89a04
SC		 3536 if (block_cnt == 0)
3537 block_cnt = 256;
283b4a9b
SC		 3538 break;
3539 case WRITE_10:
3540 is_write = 1;
3541 case READ_10:
3542 first_block =
3543 (((u64) cmd->cmnd[2]) << 24) |
3544 (((u64) cmd->cmnd[3]) << 16) |
3545 (((u64) cmd->cmnd[4]) << 8) |
3546 cmd->cmnd[5];
3547 block_cnt =
3548 (((u32) cmd->cmnd[7]) << 8) |
3549 cmd->cmnd[8];
3550 break;
3551 case WRITE_12:
3552 is_write = 1;
3553 case READ_12:
3554 first_block =
3555 (((u64) cmd->cmnd[2]) << 24) |
3556 (((u64) cmd->cmnd[3]) << 16) |
3557 (((u64) cmd->cmnd[4]) << 8) |
3558 cmd->cmnd[5];
3559 block_cnt =
3560 (((u32) cmd->cmnd[6]) << 24) |
3561 (((u32) cmd->cmnd[7]) << 16) |
3562 (((u32) cmd->cmnd[8]) << 8) |
3563 cmd->cmnd[9];
3564 break;
3565 case WRITE_16:
3566 is_write = 1;
3567 case READ_16:
3568 first_block =
3569 (((u64) cmd->cmnd[2]) << 56) |
3570 (((u64) cmd->cmnd[3]) << 48) |
3571 (((u64) cmd->cmnd[4]) << 40) |
3572 (((u64) cmd->cmnd[5]) << 32) |
3573 (((u64) cmd->cmnd[6]) << 24) |
3574 (((u64) cmd->cmnd[7]) << 16) |
3575 (((u64) cmd->cmnd[8]) << 8) |
3576 cmd->cmnd[9];
3577 block_cnt =
3578 (((u32) cmd->cmnd[10]) << 24) |
3579 (((u32) cmd->cmnd[11]) << 16) |
3580 (((u32) cmd->cmnd[12]) << 8) |
3581 cmd->cmnd[13];
3582 break;
3583 default:
3584 return IO_ACCEL_INELIGIBLE; /* process via normal I/O path */
3585 }
283b4a9b
SC		 3586 last_block = first_block + block_cnt - 1;
3587
3588 /* check for write to non-RAID-0 */
3589 if (is_write && dev->raid_level != 0)
3590 return IO_ACCEL_INELIGIBLE;
3591
3592 /* check for invalid block or wraparound */
2b08b3e9
DB		 3593 if (last_block >= le64_to_cpu(map->volume_blk_cnt) ||
3594 last_block < first_block)
283b4a9b
SC		 3595 return IO_ACCEL_INELIGIBLE;
3596
3597 /* calculate stripe information for the request */
2b08b3e9
DB		 3598 blocks_per_row = le16_to_cpu(map->data_disks_per_row) *
3599 le16_to_cpu(map->strip_size);
3600 strip_size = le16_to_cpu(map->strip_size);
283b4a9b
SC		 3601#if BITS_PER_LONG == 32
3602 tmpdiv = first_block;
3603 (void) do_div(tmpdiv, blocks_per_row);
3604 first_row = tmpdiv;
3605 tmpdiv = last_block;
3606 (void) do_div(tmpdiv, blocks_per_row);
3607 last_row = tmpdiv;
3608 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
3609 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
3610 tmpdiv = first_row_offset;
2b08b3e9 3611 (void) do_div(tmpdiv, strip_size);
283b4a9b
SC		 3612 first_column = tmpdiv;
3613 tmpdiv = last_row_offset;
2b08b3e9 3614 (void) do_div(tmpdiv, strip_size);
283b4a9b
SC		 3615 last_column = tmpdiv;
3616#else
3617 first_row = first_block / blocks_per_row;
3618 last_row = last_block / blocks_per_row;
3619 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
3620 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
2b08b3e9
DB		 3621 first_column = first_row_offset / strip_size;
3622 last_column = last_row_offset / strip_size;
283b4a9b
SC		 3623#endif
3624
3625 /* if this isn't a single row/column then give to the controller */
3626 if ((first_row != last_row) || (first_column != last_column))
3627 return IO_ACCEL_INELIGIBLE;
3628
3629 /* proceeding with driver mapping */
2b08b3e9
DB		 3630 total_disks_per_row = le16_to_cpu(map->data_disks_per_row) +
3631 le16_to_cpu(map->metadata_disks_per_row);
283b4a9b 3632 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
2b08b3e9 3633 le16_to_cpu(map->row_cnt);
6b80b18f
ST		 3634 map_index = (map_row * total_disks_per_row) + first_column;
3635
3636 switch (dev->raid_level) {
3637 case HPSA_RAID_0:
3638 break; /* nothing special to do */
3639 case HPSA_RAID_1:
3640 /* Handles load balance across RAID 1 members.
3641 * (2-drive R1 and R10 with even # of drives.)
3642 * Appropriate for SSDs, not optimal for HDDs
283b4a9b 3643 */
2b08b3e9 3644 BUG_ON(le16_to_cpu(map->layout_map_count) != 2);
283b4a9b 3645 if (dev->offload_to_mirror)
2b08b3e9 3646 map_index += le16_to_cpu(map->data_disks_per_row);
283b4a9b 3647 dev->offload_to_mirror = !dev->offload_to_mirror;
6b80b18f
ST		 3648 break;
3649 case HPSA_RAID_ADM:
3650 /* Handles N-way mirrors (R1-ADM)
3651 * and R10 with # of drives divisible by 3.)
3652 */
2b08b3e9 3653 BUG_ON(le16_to_cpu(map->layout_map_count) != 3);
6b80b18f
ST		 3654
3655 offload_to_mirror = dev->offload_to_mirror;
3656 raid_map_helper(map, offload_to_mirror,
3657 &map_index, &current_group);
3658 /* set mirror group to use next time */
3659 offload_to_mirror =
2b08b3e9
DB		 3660 (offload_to_mirror >=
3661 le16_to_cpu(map->layout_map_count) - 1)
6b80b18f 3662 ? 0 : offload_to_mirror + 1;
6b80b18f
ST		 3663 dev->offload_to_mirror = offload_to_mirror;
3664 /* Avoid direct use of dev->offload_to_mirror within this
3665 * function since multiple threads might simultaneously
3666 * increment it beyond the range of dev->layout_map_count -1.
3667 */
3668 break;
3669 case HPSA_RAID_5:
3670 case HPSA_RAID_6:
2b08b3e9 3671 if (le16_to_cpu(map->layout_map_count) <= 1)
6b80b18f
ST		 3672 break;
3673
3674 /* Verify first and last block are in same RAID group */
3675 r5or6_blocks_per_row =
2b08b3e9
DB		 3676 le16_to_cpu(map->strip_size) *
3677 le16_to_cpu(map->data_disks_per_row);
6b80b18f 3678 BUG_ON(r5or6_blocks_per_row == 0);
2b08b3e9
DB		 3679 stripesize = r5or6_blocks_per_row *
3680 le16_to_cpu(map->layout_map_count);
6b80b18f
ST		 3681#if BITS_PER_LONG == 32
3682 tmpdiv = first_block;
3683 first_group = do_div(tmpdiv, stripesize);
3684 tmpdiv = first_group;
3685 (void) do_div(tmpdiv, r5or6_blocks_per_row);
3686 first_group = tmpdiv;
3687 tmpdiv = last_block;
3688 last_group = do_div(tmpdiv, stripesize);
3689 tmpdiv = last_group;
3690 (void) do_div(tmpdiv, r5or6_blocks_per_row);
3691 last_group = tmpdiv;
3692#else
3693 first_group = (first_block % stripesize) / r5or6_blocks_per_row;
3694 last_group = (last_block % stripesize) / r5or6_blocks_per_row;
6b80b18f 3695#endif
000ff7c2 3696 if (first_group != last_group)
6b80b18f
ST		 3697 return IO_ACCEL_INELIGIBLE;
3698
3699 /* Verify request is in a single row of RAID 5/6 */
3700#if BITS_PER_LONG == 32
3701 tmpdiv = first_block;
3702 (void) do_div(tmpdiv, stripesize);
3703 first_row = r5or6_first_row = r0_first_row = tmpdiv;
3704 tmpdiv = last_block;
3705 (void) do_div(tmpdiv, stripesize);
3706 r5or6_last_row = r0_last_row = tmpdiv;
3707#else
3708 first_row = r5or6_first_row = r0_first_row =
3709 first_block / stripesize;
3710 r5or6_last_row = r0_last_row = last_block / stripesize;
3711#endif
3712 if (r5or6_first_row != r5or6_last_row)
3713 return IO_ACCEL_INELIGIBLE;
3714
3715
3716 /* Verify request is in a single column */
3717#if BITS_PER_LONG == 32
3718 tmpdiv = first_block;
3719 first_row_offset = do_div(tmpdiv, stripesize);
3720 tmpdiv = first_row_offset;
3721 first_row_offset = (u32) do_div(tmpdiv, r5or6_blocks_per_row);
3722 r5or6_first_row_offset = first_row_offset;
3723 tmpdiv = last_block;
3724 r5or6_last_row_offset = do_div(tmpdiv, stripesize);
3725 tmpdiv = r5or6_last_row_offset;
3726 r5or6_last_row_offset = do_div(tmpdiv, r5or6_blocks_per_row);
3727 tmpdiv = r5or6_first_row_offset;
3728 (void) do_div(tmpdiv, map->strip_size);
3729 first_column = r5or6_first_column = tmpdiv;
3730 tmpdiv = r5or6_last_row_offset;
3731 (void) do_div(tmpdiv, map->strip_size);
3732 r5or6_last_column = tmpdiv;
3733#else
3734 first_row_offset = r5or6_first_row_offset =
3735 (u32)((first_block % stripesize) %
3736 r5or6_blocks_per_row);
3737
3738 r5or6_last_row_offset =
3739 (u32)((last_block % stripesize) %
3740 r5or6_blocks_per_row);
3741
3742 first_column = r5or6_first_column =
2b08b3e9 3743 r5or6_first_row_offset / le16_to_cpu(map->strip_size);
6b80b18f 3744 r5or6_last_column =
2b08b3e9 3745 r5or6_last_row_offset / le16_to_cpu(map->strip_size);
6b80b18f
ST		 3746#endif
3747 if (r5or6_first_column != r5or6_last_column)
3748 return IO_ACCEL_INELIGIBLE;
3749
3750 /* Request is eligible */
3751 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
2b08b3e9 3752 le16_to_cpu(map->row_cnt);
6b80b18f
ST		 3753
3754 map_index = (first_group *
2b08b3e9 3755 (le16_to_cpu(map->row_cnt) * total_disks_per_row)) +
6b80b18f
ST		 3756 (map_row * total_disks_per_row) + first_column;
3757 break;
3758 default:
3759 return IO_ACCEL_INELIGIBLE;
283b4a9b 3760 }
6b80b18f 3761
283b4a9b 3762 disk_handle = dd[map_index].ioaccel_handle;
2b08b3e9
DB		 3763 disk_block = le64_to_cpu(map->disk_starting_blk) +
3764 first_row * le16_to_cpu(map->strip_size) +
3765 (first_row_offset - first_column *
3766 le16_to_cpu(map->strip_size));
283b4a9b
SC		 3767 disk_block_cnt = block_cnt;
3768
3769 /* handle differing logical/physical block sizes */
3770 if (map->phys_blk_shift) {
3771 disk_block <<= map->phys_blk_shift;
3772 disk_block_cnt <<= map->phys_blk_shift;
3773 }
3774 BUG_ON(disk_block_cnt > 0xffff);
3775
3776 /* build the new CDB for the physical disk I/O */
3777 if (disk_block > 0xffffffff) {
3778 cdb[0] = is_write ? WRITE_16 : READ_16;
3779 cdb[1] = 0;
3780 cdb[2] = (u8) (disk_block >> 56);
3781 cdb[3] = (u8) (disk_block >> 48);
3782 cdb[4] = (u8) (disk_block >> 40);
3783 cdb[5] = (u8) (disk_block >> 32);
3784 cdb[6] = (u8) (disk_block >> 24);
3785 cdb[7] = (u8) (disk_block >> 16);
3786 cdb[8] = (u8) (disk_block >> 8);
3787 cdb[9] = (u8) (disk_block);
3788 cdb[10] = (u8) (disk_block_cnt >> 24);
3789 cdb[11] = (u8) (disk_block_cnt >> 16);
3790 cdb[12] = (u8) (disk_block_cnt >> 8);
3791 cdb[13] = (u8) (disk_block_cnt);
3792 cdb[14] = 0;
3793 cdb[15] = 0;
3794 cdb_len = 16;
3795 } else {
3796 cdb[0] = is_write ? WRITE_10 : READ_10;
3797 cdb[1] = 0;
3798 cdb[2] = (u8) (disk_block >> 24);
3799 cdb[3] = (u8) (disk_block >> 16);
3800 cdb[4] = (u8) (disk_block >> 8);
3801 cdb[5] = (u8) (disk_block);
3802 cdb[6] = 0;
3803 cdb[7] = (u8) (disk_block_cnt >> 8);
3804 cdb[8] = (u8) (disk_block_cnt);
3805 cdb[9] = 0;
3806 cdb_len = 10;
3807 }
3808 return hpsa_scsi_ioaccel_queue_command(h, c, disk_handle, cdb, cdb_len,
3809 dev->scsi3addr);
3810}
3811
f2405db8 3812/* Running in struct Scsi_Host->host_lock less mode */
763aadbf 3813static int hpsa_scsi_queue_command(struct Scsi_Host *sh, struct scsi_cmnd *cmd)
edd16368
SC		 3814{
3815 struct ctlr_info *h;
3816 struct hpsa_scsi_dev_t *dev;
3817 unsigned char scsi3addr[8];
3818 struct CommandList *c;
283b4a9b 3819 int rc = 0;
edd16368
SC		 3820
3821 /* Get the ptr to our adapter structure out of cmd->host. */
3822 h = sdev_to_hba(cmd->device);
3823 dev = cmd->device->hostdata;
3824 if (!dev) {
3825 cmd->result = DID_NO_CONNECT << 16;
763aadbf 3826 cmd->scsi_done(cmd);
edd16368
SC		 3827 return 0;
3828 }
3829 memcpy(scsi3addr, dev->scsi3addr, sizeof(scsi3addr));
3830
094963da 3831 if (unlikely(lockup_detected(h))) {
a0c12413 3832 cmd->result = DID_ERROR << 16;
763aadbf 3833 cmd->scsi_done(cmd);
a0c12413
SC		 3834 return 0;
3835 }
e16a33ad 3836 c = cmd_alloc(h);
edd16368
SC		 3837 if (c == NULL) { /* trouble... */
3838 dev_err(&h->pdev->dev, "cmd_alloc returned NULL!\n");
3839 return SCSI_MLQUEUE_HOST_BUSY;
3840 }
3841
3842 /* Fill in the command list header */
edd16368
SC		 3843 /* save c in case we have to abort it */
3844 cmd->host_scribble = (unsigned char *) c;
3845
3846 c->cmd_type = CMD_SCSI;
3847 c->scsi_cmd = cmd;
e1f7de0c 3848
283b4a9b
SC		 3849 /* Call alternate submit routine for I/O accelerated commands.
3850 * Retries always go down the normal I/O path.
3851 */
3852 if (likely(cmd->retries == 0 &&
da0697bd
ST		 3853 cmd->request->cmd_type == REQ_TYPE_FS &&
3854 h->acciopath_status)) {
283b4a9b
SC		 3855 if (dev->offload_enabled) {
3856 rc = hpsa_scsi_ioaccel_raid_map(h, c);
3857 if (rc == 0)
3858 return 0; /* Sent on ioaccel path */
3859 if (rc < 0) { /* scsi_dma_map failed. */
3860 cmd_free(h, c);
3861 return SCSI_MLQUEUE_HOST_BUSY;
3862 }
3863 } else if (dev->ioaccel_handle) {
3864 rc = hpsa_scsi_ioaccel_direct_map(h, c);
3865 if (rc == 0)
3866 return 0; /* Sent on direct map path */
3867 if (rc < 0) { /* scsi_dma_map failed. */
3868 cmd_free(h, c);
3869 return SCSI_MLQUEUE_HOST_BUSY;
3870 }
3871 }
3872 }
e1f7de0c 3873
edd16368
SC		 3874 c->Header.ReplyQueue = 0; /* unused in simple mode */
3875 memcpy(&c->Header.LUN.LunAddrBytes[0], &scsi3addr[0], 8);
f2405db8 3876 c->Header.tag = cpu_to_le64((c->cmdindex << DIRECT_LOOKUP_SHIFT));
edd16368
SC		 3877
3878 /* Fill in the request block... */
3879
3880 c->Request.Timeout = 0;
3881 memset(c->Request.CDB, 0, sizeof(c->Request.CDB));
3882 BUG_ON(cmd->cmd_len > sizeof(c->Request.CDB));
3883 c->Request.CDBLen = cmd->cmd_len;
3884 memcpy(c->Request.CDB, cmd->cmnd, cmd->cmd_len);
edd16368
SC		 3885 switch (cmd->sc_data_direction) {
3886 case DMA_TO_DEVICE:
a505b86f
SC		 3887 c->Request.type_attr_dir =
3888 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_WRITE);
edd16368
SC		 3889 break;
3890 case DMA_FROM_DEVICE:
a505b86f
SC		 3891 c->Request.type_attr_dir =
3892 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 3893 break;
3894 case DMA_NONE:
a505b86f
SC		 3895 c->Request.type_attr_dir =
3896 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_NONE);
edd16368
SC		 3897 break;
3898 case DMA_BIDIRECTIONAL:
3899 /* This can happen if a buggy application does a scsi passthru
3900 * and sets both inlen and outlen to non-zero. ( see
3901 * ../scsi/scsi_ioctl.c:scsi_ioctl_send_command() )
3902 */
3903
a505b86f
SC		 3904 c->Request.type_attr_dir =
3905 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_RSVD);
edd16368
SC		 3906 /* This is technically wrong, and hpsa controllers should
3907 * reject it with CMD_INVALID, which is the most correct
3908 * response, but non-fibre backends appear to let it
3909 * slide by, and give the same results as if this field
3910 * were set correctly. Either way is acceptable for
3911 * our purposes here.
3912 */
3913
3914 break;
3915
3916 default:
3917 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
3918 cmd->sc_data_direction);
3919 BUG();
3920 break;
3921 }
3922
33a2ffce 3923 if (hpsa_scatter_gather(h, c, cmd) < 0) { /* Fill SG list */
edd16368
SC		 3924 cmd_free(h, c);
3925 return SCSI_MLQUEUE_HOST_BUSY;
3926 }
3927 enqueue_cmd_and_start_io(h, c);
3928 /* the cmd'll come back via intr handler in complete_scsi_command() */
3929 return 0;
3930}
3931
5f389360
SC		 3932static int do_not_scan_if_controller_locked_up(struct ctlr_info *h)
3933{
3934 unsigned long flags;
3935
3936 /*
3937 * Don't let rescans be initiated on a controller known
3938 * to be locked up. If the controller locks up *during*
3939 * a rescan, that thread is probably hosed, but at least
3940 * we can prevent new rescan threads from piling up on a
3941 * locked up controller.
3942 */
094963da 3943 if (unlikely(lockup_detected(h))) {
5f389360
SC		 3944 spin_lock_irqsave(&h->scan_lock, flags);
3945 h->scan_finished = 1;
3946 wake_up_all(&h->scan_wait_queue);
3947 spin_unlock_irqrestore(&h->scan_lock, flags);
3948 return 1;
3949 }
5f389360
SC		 3950 return 0;
3951}
3952
a08a8471
SC		 3953static void hpsa_scan_start(struct Scsi_Host *sh)
3954{
3955 struct ctlr_info *h = shost_to_hba(sh);
3956 unsigned long flags;
3957
5f389360
SC		 3958 if (do_not_scan_if_controller_locked_up(h))
3959 return;
3960
a08a8471
SC		 3961 /* wait until any scan already in progress is finished. */
3962 while (1) {
3963 spin_lock_irqsave(&h->scan_lock, flags);
3964 if (h->scan_finished)
3965 break;
3966 spin_unlock_irqrestore(&h->scan_lock, flags);
3967 wait_event(h->scan_wait_queue, h->scan_finished);
3968 /* Note: We don't need to worry about a race between this
3969 * thread and driver unload because the midlayer will
3970 * have incremented the reference count, so unload won't
3971 * happen if we're in here.
3972 */
3973 }
3974 h->scan_finished = 0; /* mark scan as in progress */
3975 spin_unlock_irqrestore(&h->scan_lock, flags);
3976
5f389360
SC		 3977 if (do_not_scan_if_controller_locked_up(h))
3978 return;
3979
a08a8471
SC		 3980 hpsa_update_scsi_devices(h, h->scsi_host->host_no);
3981
3982 spin_lock_irqsave(&h->scan_lock, flags);
3983 h->scan_finished = 1; /* mark scan as finished. */
3984 wake_up_all(&h->scan_wait_queue);
3985 spin_unlock_irqrestore(&h->scan_lock, flags);
3986}
3987
7c0a0229
DB		 3988static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth)
3989{
3990 struct ctlr_info *h = sdev_to_hba(sdev);
3991
3992 if (qdepth < 1)
3993 qdepth = 1;
3994 else
3995 if (qdepth > h->nr_cmds)
3996 qdepth = h->nr_cmds;
3997 scsi_change_queue_depth(sdev, qdepth);
3998 return sdev->queue_depth;
3999}
4000
a08a8471
SC		 4001static int hpsa_scan_finished(struct Scsi_Host *sh,
4002 unsigned long elapsed_time)
4003{
4004 struct ctlr_info *h = shost_to_hba(sh);
4005 unsigned long flags;
4006 int finished;
4007
4008 spin_lock_irqsave(&h->scan_lock, flags);
4009 finished = h->scan_finished;
4010 spin_unlock_irqrestore(&h->scan_lock, flags);
4011 return finished;
4012}
4013
edd16368
SC		 4014static void hpsa_unregister_scsi(struct ctlr_info *h)
4015{
4016 /* we are being forcibly unloaded, and may not refuse. */
4017 scsi_remove_host(h->scsi_host);
4018 scsi_host_put(h->scsi_host);
4019 h->scsi_host = NULL;
4020}
4021
4022static int hpsa_register_scsi(struct ctlr_info *h)
4023{
b705690d
SC		 4024 struct Scsi_Host *sh;
4025 int error;
edd16368 4026
b705690d
SC		 4027 sh = scsi_host_alloc(&hpsa_driver_template, sizeof(h));
4028 if (sh == NULL)
4029 goto fail;
4030
4031 sh->io_port = 0;
4032 sh->n_io_port = 0;
4033 sh->this_id = -1;
4034 sh->max_channel = 3;
4035 sh->max_cmd_len = MAX_COMMAND_SIZE;
4036 sh->max_lun = HPSA_MAX_LUN;
4037 sh->max_id = HPSA_MAX_LUN;
d54c5c24
SC		 4038 sh->can_queue = h->nr_cmds -
4039 HPSA_CMDS_RESERVED_FOR_ABORTS -
4040 HPSA_CMDS_RESERVED_FOR_DRIVER -
4041 HPSA_MAX_CONCURRENT_PASSTHRUS;
316b221a
SC		 4042 if (h->hba_mode_enabled)
4043 sh->cmd_per_lun = 7;
4044 else
d54c5c24 4045 sh->cmd_per_lun = sh->can_queue;
b705690d
SC		 4046 sh->sg_tablesize = h->maxsgentries;
4047 h->scsi_host = sh;
4048 sh->hostdata[0] = (unsigned long) h;
4049 sh->irq = h->intr[h->intr_mode];
4050 sh->unique_id = sh->irq;
4051 error = scsi_add_host(sh, &h->pdev->dev);
4052 if (error)
4053 goto fail_host_put;
4054 scsi_scan_host(sh);
4055 return 0;
4056
4057 fail_host_put:
4058 dev_err(&h->pdev->dev, "%s: scsi_add_host"
4059 " failed for controller %d\n", __func__, h->ctlr);
4060 scsi_host_put(sh);
4061 return error;
4062 fail:
4063 dev_err(&h->pdev->dev, "%s: scsi_host_alloc"
4064 " failed for controller %d\n", __func__, h->ctlr);
4065 return -ENOMEM;
edd16368
SC		 4066}
4067
4068static int wait_for_device_to_become_ready(struct ctlr_info *h,
4069 unsigned char lunaddr[])
4070{
8919358e 4071 int rc;
edd16368
SC		 4072 int count = 0;
4073 int waittime = 1; /* seconds */
4074 struct CommandList *c;
4075
45fcb86e 4076 c = cmd_alloc(h);
edd16368
SC		 4077 if (!c) {
4078 dev_warn(&h->pdev->dev, "out of memory in "
4079 "wait_for_device_to_become_ready.\n");
4080 return IO_ERROR;
4081 }
4082
4083 /* Send test unit ready until device ready, or give up. */
4084 while (count < HPSA_TUR_RETRY_LIMIT) {
4085
4086 /* Wait for a bit. do this first, because if we send
4087 * the TUR right away, the reset will just abort it.
4088 */
4089 msleep(1000 * waittime);
4090 count++;
8919358e 4091 rc = 0; /* Device ready. */
edd16368
SC		 4092
4093 /* Increase wait time with each try, up to a point. */
4094 if (waittime < HPSA_MAX_WAIT_INTERVAL_SECS)
4095 waittime = waittime * 2;
4096
a2dac136
SC		 4097 /* Send the Test Unit Ready, fill_cmd can't fail, no mapping */
4098 (void) fill_cmd(c, TEST_UNIT_READY, h,
4099 NULL, 0, 0, lunaddr, TYPE_CMD);
edd16368
SC		 4100 hpsa_scsi_do_simple_cmd_core(h, c);
4101 /* no unmap needed here because no data xfer. */
4102
4103 if (c->err_info->CommandStatus == CMD_SUCCESS)
4104 break;
4105
4106 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
4107 c->err_info->ScsiStatus == SAM_STAT_CHECK_CONDITION &&
4108 (c->err_info->SenseInfo[2] == NO_SENSE ||
4109 c->err_info->SenseInfo[2] == UNIT_ATTENTION))
4110 break;
4111
4112 dev_warn(&h->pdev->dev, "waiting %d secs "
4113 "for device to become ready.\n", waittime);
4114 rc = 1; /* device not ready. */
4115 }
4116
4117 if (rc)
4118 dev_warn(&h->pdev->dev, "giving up on device.\n");
4119 else
4120 dev_warn(&h->pdev->dev, "device is ready.\n");
4121
45fcb86e 4122 cmd_free(h, c);
edd16368
SC		 4123 return rc;
4124}
4125
4126/* Need at least one of these error handlers to keep ../scsi/hosts.c from
4127 * complaining. Doing a host- or bus-reset can't do anything good here.
4128 */
4129static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd)
4130{
4131 int rc;
4132 struct ctlr_info *h;
4133 struct hpsa_scsi_dev_t *dev;
4134
4135 /* find the controller to which the command to be aborted was sent */
4136 h = sdev_to_hba(scsicmd->device);
4137 if (h == NULL) /* paranoia */
4138 return FAILED;
edd16368
SC		 4139 dev = scsicmd->device->hostdata;
4140 if (!dev) {
4141 dev_err(&h->pdev->dev, "hpsa_eh_device_reset_handler: "
4142 "device lookup failed.\n");
4143 return FAILED;
4144 }
d416b0c7
SC		 4145 dev_warn(&h->pdev->dev, "resetting device %d:%d:%d:%d\n",
4146 h->scsi_host->host_no, dev->bus, dev->target, dev->lun);
edd16368 4147 /* send a reset to the SCSI LUN which the command was sent to */
bf711ac6 4148 rc = hpsa_send_reset(h, dev->scsi3addr, HPSA_RESET_TYPE_LUN);
edd16368
SC		 4149 if (rc == 0 && wait_for_device_to_become_ready(h, dev->scsi3addr) == 0)
4150 return SUCCESS;
4151
4152 dev_warn(&h->pdev->dev, "resetting device failed.\n");
4153 return FAILED;
4154}
4155
6cba3f19
SC		 4156static void swizzle_abort_tag(u8 *tag)
4157{
4158 u8 original_tag[8];
4159
4160 memcpy(original_tag, tag, 8);
4161 tag[0] = original_tag[3];
4162 tag[1] = original_tag[2];
4163 tag[2] = original_tag[1];
4164 tag[3] = original_tag[0];
4165 tag[4] = original_tag[7];
4166 tag[5] = original_tag[6];
4167 tag[6] = original_tag[5];
4168 tag[7] = original_tag[4];
4169}
4170
17eb87d2 4171static void hpsa_get_tag(struct ctlr_info *h,
2b08b3e9 4172 struct CommandList *c, __le32 *taglower, __le32 *tagupper)
17eb87d2 4173{
2b08b3e9 4174 u64 tag;
17eb87d2
ST		 4175 if (c->cmd_type == CMD_IOACCEL1) {
4176 struct io_accel1_cmd *cm1 = (struct io_accel1_cmd *)
4177 &h->ioaccel_cmd_pool[c->cmdindex];
2b08b3e9
DB		 4178 tag = le64_to_cpu(cm1->tag);
4179 *tagupper = cpu_to_le32(tag >> 32);
4180 *taglower = cpu_to_le32(tag);
54b6e9e9
ST		 4181 return;
4182 }
4183 if (c->cmd_type == CMD_IOACCEL2) {
4184 struct io_accel2_cmd *cm2 = (struct io_accel2_cmd *)
4185 &h->ioaccel2_cmd_pool[c->cmdindex];
dd0e19f3
ST		 4186 /* upper tag not used in ioaccel2 mode */
4187 memset(tagupper, 0, sizeof(*tagupper));
4188 *taglower = cm2->Tag;
54b6e9e9 4189 return;
17eb87d2 4190 }
2b08b3e9
DB		 4191 tag = le64_to_cpu(c->Header.tag);
4192 *tagupper = cpu_to_le32(tag >> 32);
4193 *taglower = cpu_to_le32(tag);
17eb87d2
ST		 4194}
4195
75167d2c 4196static int hpsa_send_abort(struct ctlr_info *h, unsigned char *scsi3addr,
6cba3f19 4197 struct CommandList *abort, int swizzle)
75167d2c
SC		 4198{
4199 int rc = IO_OK;
4200 struct CommandList *c;
4201 struct ErrorInfo *ei;
2b08b3e9 4202 __le32 tagupper, taglower;
75167d2c 4203
45fcb86e 4204 c = cmd_alloc(h);
75167d2c 4205 if (c == NULL) { /* trouble... */
45fcb86e 4206 dev_warn(&h->pdev->dev, "cmd_alloc returned NULL!\n");
75167d2c
SC		 4207 return -ENOMEM;
4208 }
4209
a2dac136
SC		 4210 /* fill_cmd can't fail here, no buffer to map */
4211 (void) fill_cmd(c, HPSA_ABORT_MSG, h, abort,
4212 0, 0, scsi3addr, TYPE_MSG);
6cba3f19
SC		 4213 if (swizzle)
4214 swizzle_abort_tag(&c->Request.CDB[4]);
75167d2c 4215 hpsa_scsi_do_simple_cmd_core(h, c);
17eb87d2 4216 hpsa_get_tag(h, abort, &taglower, &tagupper);
75167d2c 4217 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: do_simple_cmd_core completed.\n",
17eb87d2 4218 __func__, tagupper, taglower);
75167d2c
SC		 4219 /* no unmap needed here because no data xfer. */
4220
4221 ei = c->err_info;
4222 switch (ei->CommandStatus) {
4223 case CMD_SUCCESS:
4224 break;
4225 case CMD_UNABORTABLE: /* Very common, don't make noise. */
4226 rc = -1;
4227 break;
4228 default:
4229 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: interpreting error.\n",
17eb87d2 4230 __func__, tagupper, taglower);
d1e8beac 4231 hpsa_scsi_interpret_error(h, c);
75167d2c
SC		 4232 rc = -1;
4233 break;
4234 }
45fcb86e 4235 cmd_free(h, c);
dd0e19f3
ST		 4236 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n",
4237 __func__, tagupper, taglower);
75167d2c
SC		 4238 return rc;
4239}
4240
54b6e9e9
ST		 4241/* ioaccel2 path firmware cannot handle abort task requests.
4242 * Change abort requests to physical target reset, and send to the
4243 * address of the physical disk used for the ioaccel 2 command.
4244 * Return 0 on success (IO_OK)
4245 * -1 on failure
4246 */
4247
4248static int hpsa_send_reset_as_abort_ioaccel2(struct ctlr_info *h,
4249 unsigned char *scsi3addr, struct CommandList *abort)
4250{
4251 int rc = IO_OK;
4252 struct scsi_cmnd *scmd; /* scsi command within request being aborted */
4253 struct hpsa_scsi_dev_t *dev; /* device to which scsi cmd was sent */
4254 unsigned char phys_scsi3addr[8]; /* addr of phys disk with volume */
4255 unsigned char *psa = &phys_scsi3addr[0];
4256
4257 /* Get a pointer to the hpsa logical device. */
4258 scmd = (struct scsi_cmnd *) abort->scsi_cmd;
4259 dev = (struct hpsa_scsi_dev_t *)(scmd->device->hostdata);
4260 if (dev == NULL) {
4261 dev_warn(&h->pdev->dev,
4262 "Cannot abort: no device pointer for command.\n");
4263 return -1; /* not abortable */
4264 }
4265
2ba8bfc8
SC		 4266 if (h->raid_offload_debug > 0)
4267 dev_info(&h->pdev->dev,
4268 "Reset as abort: Abort requested on C%d:B%d:T%d:L%d scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4269 h->scsi_host->host_no, dev->bus, dev->target, dev->lun,
4270 scsi3addr[0], scsi3addr[1], scsi3addr[2], scsi3addr[3],
4271 scsi3addr[4], scsi3addr[5], scsi3addr[6], scsi3addr[7]);
4272
54b6e9e9
ST		 4273 if (!dev->offload_enabled) {
4274 dev_warn(&h->pdev->dev,
4275 "Can't abort: device is not operating in HP SSD Smart Path mode.\n");
4276 return -1; /* not abortable */
4277 }
4278
4279 /* Incoming scsi3addr is logical addr. We need physical disk addr. */
4280 if (!hpsa_get_pdisk_of_ioaccel2(h, abort, psa)) {
4281 dev_warn(&h->pdev->dev, "Can't abort: Failed lookup of physical address.\n");
4282 return -1; /* not abortable */
4283 }
4284
4285 /* send the reset */
2ba8bfc8
SC		 4286 if (h->raid_offload_debug > 0)
4287 dev_info(&h->pdev->dev,
4288 "Reset as abort: Resetting physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4289 psa[0], psa[1], psa[2], psa[3],
4290 psa[4], psa[5], psa[6], psa[7]);
54b6e9e9
ST		 4291 rc = hpsa_send_reset(h, psa, HPSA_RESET_TYPE_TARGET);
4292 if (rc != 0) {
4293 dev_warn(&h->pdev->dev,
4294 "Reset as abort: Failed on physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4295 psa[0], psa[1], psa[2], psa[3],
4296 psa[4], psa[5], psa[6], psa[7]);
4297 return rc; /* failed to reset */
4298 }
4299
4300 /* wait for device to recover */
4301 if (wait_for_device_to_become_ready(h, psa) != 0) {
4302 dev_warn(&h->pdev->dev,
4303 "Reset as abort: Failed: Device never recovered from reset: 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4304 psa[0], psa[1], psa[2], psa[3],
4305 psa[4], psa[5], psa[6], psa[7]);
4306 return -1; /* failed to recover */
4307 }
4308
4309 /* device recovered */
4310 dev_info(&h->pdev->dev,
4311 "Reset as abort: Device recovered from reset: scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4312 psa[0], psa[1], psa[2], psa[3],
4313 psa[4], psa[5], psa[6], psa[7]);
4314
4315 return rc; /* success */
4316}
4317
6cba3f19
SC		 4318/* Some Smart Arrays need the abort tag swizzled, and some don't. It's hard to
4319 * tell which kind we're dealing with, so we send the abort both ways. There
4320 * shouldn't be any collisions between swizzled and unswizzled tags due to the
4321 * way we construct our tags but we check anyway in case the assumptions which
4322 * make this true someday become false.
4323 */
4324static int hpsa_send_abort_both_ways(struct ctlr_info *h,
4325 unsigned char *scsi3addr, struct CommandList *abort)
4326{
54b6e9e9
ST		 4327 /* ioccelerator mode 2 commands should be aborted via the
4328 * accelerated path, since RAID path is unaware of these commands,
4329 * but underlying firmware can't handle abort TMF.
4330 * Change abort to physical device reset.
4331 */
4332 if (abort->cmd_type == CMD_IOACCEL2)
4333 return hpsa_send_reset_as_abort_ioaccel2(h, scsi3addr, abort);
4334
f2405db8
DB		 4335 return hpsa_send_abort(h, scsi3addr, abort, 0) &&
4336 hpsa_send_abort(h, scsi3addr, abort, 1);
6cba3f19
SC		 4337}
4338
75167d2c
SC		 4339/* Send an abort for the specified command.
4340 * If the device and controller support it,
4341 * send a task abort request.
4342 */
4343static int hpsa_eh_abort_handler(struct scsi_cmnd *sc)
4344{
4345
4346 int i, rc;
4347 struct ctlr_info *h;
4348 struct hpsa_scsi_dev_t *dev;
4349 struct CommandList *abort; /* pointer to command to be aborted */
75167d2c
SC		 4350 struct scsi_cmnd *as; /* ptr to scsi cmd inside aborted command. */
4351 char msg[256]; /* For debug messaging. */
4352 int ml = 0;
2b08b3e9 4353 __le32 tagupper, taglower;
75167d2c
SC		 4354
4355 /* Find the controller of the command to be aborted */
4356 h = sdev_to_hba(sc->device);
4357 if (WARN(h == NULL,
4358 "ABORT REQUEST FAILED, Controller lookup failed.\n"))
4359 return FAILED;
4360
4361 /* Check that controller supports some kind of task abort */
4362 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags) &&
4363 !(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
4364 return FAILED;
4365
4366 memset(msg, 0, sizeof(msg));
9cb78c16 4367 ml += sprintf(msg+ml, "ABORT REQUEST on C%d:B%d:T%d:L%llu ",
75167d2c
SC		 4368 h->scsi_host->host_no, sc->device->channel,
4369 sc->device->id, sc->device->lun);
4370
4371 /* Find the device of the command to be aborted */
4372 dev = sc->device->hostdata;
4373 if (!dev) {
4374 dev_err(&h->pdev->dev, "%s FAILED, Device lookup failed.\n",
4375 msg);
4376 return FAILED;
4377 }
4378
4379 /* Get SCSI command to be aborted */
4380 abort = (struct CommandList *) sc->host_scribble;
4381 if (abort == NULL) {
4382 dev_err(&h->pdev->dev, "%s FAILED, Command to abort is NULL.\n",
4383 msg);
4384 return FAILED;
4385 }
17eb87d2
ST		 4386 hpsa_get_tag(h, abort, &taglower, &tagupper);
4387 ml += sprintf(msg+ml, "Tag:0x%08x:%08x ", tagupper, taglower);
75167d2c
SC		 4388 as = (struct scsi_cmnd *) abort->scsi_cmd;
4389 if (as != NULL)
4390 ml += sprintf(msg+ml, "Command:0x%x SN:0x%lx ",
4391 as->cmnd[0], as->serial_number);
4392 dev_dbg(&h->pdev->dev, "%s\n", msg);
4393 dev_warn(&h->pdev->dev, "Abort request on C%d:B%d:T%d:L%d\n",
4394 h->scsi_host->host_no, dev->bus, dev->target, dev->lun);
75167d2c
SC		 4395 /*
4396 * Command is in flight, or possibly already completed
4397 * by the firmware (but not to the scsi mid layer) but we can't
4398 * distinguish which. Send the abort down.
4399 */
6cba3f19 4400 rc = hpsa_send_abort_both_ways(h, dev->scsi3addr, abort);
75167d2c
SC		 4401 if (rc != 0) {
4402 dev_dbg(&h->pdev->dev, "%s Request FAILED.\n", msg);
4403 dev_warn(&h->pdev->dev, "FAILED abort on device C%d:B%d:T%d:L%d\n",
4404 h->scsi_host->host_no,
4405 dev->bus, dev->target, dev->lun);
4406 return FAILED;
4407 }
4408 dev_info(&h->pdev->dev, "%s REQUEST SUCCEEDED.\n", msg);
4409
4410 /* If the abort(s) above completed and actually aborted the
4411 * command, then the command to be aborted should already be
4412 * completed. If not, wait around a bit more to see if they
4413 * manage to complete normally.
4414 */
4415#define ABORT_COMPLETE_WAIT_SECS 30
4416 for (i = 0; i < ABORT_COMPLETE_WAIT_SECS * 10; i++) {
f2405db8
DB		 4417 if (test_bit(abort->cmdindex & (BITS_PER_LONG - 1),
4418 h->cmd_pool_bits +
4419 (abort->cmdindex / BITS_PER_LONG)))
4420 msleep(100);
4421 else
75167d2c 4422 return SUCCESS;
75167d2c
SC		 4423 }
4424 dev_warn(&h->pdev->dev, "%s FAILED. Aborted command has not completed after %d seconds.\n",
4425 msg, ABORT_COMPLETE_WAIT_SECS);
4426 return FAILED;
4427}
4428
4429
edd16368
SC		 4430/*
4431 * For operations that cannot sleep, a command block is allocated at init,
4432 * and managed by cmd_alloc() and cmd_free() using a simple bitmap to track
4433 * which ones are free or in use. Lock must be held when calling this.
4434 * cmd_free() is the complement.
4435 */
4436static struct CommandList *cmd_alloc(struct ctlr_info *h)
4437{
4438 struct CommandList *c;
4439 int i;
4440 union u64bit temp64;
4441 dma_addr_t cmd_dma_handle, err_dma_handle;
4c413128
SC		 4442 int loopcount;
4443
4444 /* There is some *extremely* small but non-zero chance that that
4445 * multiple threads could get in here, and one thread could
4446 * be scanning through the list of bits looking for a free
4447 * one, but the free ones are always behind him, and other
4448 * threads sneak in behind him and eat them before he can
4449 * get to them, so that while there is always a free one, a
4450 * very unlucky thread might be starved anyway, never able to
4451 * beat the other threads. In reality, this happens so
4452 * infrequently as to be indistinguishable from never.
4453 */
edd16368 4454
4c413128 4455 loopcount = 0;
edd16368
SC		 4456 do {
4457 i = find_first_zero_bit(h->cmd_pool_bits, h->nr_cmds);
4c413128
SC		 4458 if (i == h->nr_cmds)
4459 i = 0;
4460 loopcount++;
4461 } while (test_and_set_bit(i & (BITS_PER_LONG - 1),
4462 h->cmd_pool_bits + (i / BITS_PER_LONG)) != 0 &&
4463 loopcount < 10);
4464
4465 /* Thread got starved? We do not expect this to ever happen. */
4466 if (loopcount >= 10)
4467 return NULL;
e16a33ad 4468
edd16368
SC		 4469 c = h->cmd_pool + i;
4470 memset(c, 0, sizeof(*c));
f2405db8
DB		 4471 c->Header.tag = cpu_to_le64((u64) i << DIRECT_LOOKUP_SHIFT);
4472 cmd_dma_handle = h->cmd_pool_dhandle + i * sizeof(*c);
edd16368
SC		 4473 c->err_info = h->errinfo_pool + i;
4474 memset(c->err_info, 0, sizeof(*c->err_info));
4475 err_dma_handle = h->errinfo_pool_dhandle
4476 + i * sizeof(*c->err_info);
edd16368
SC		 4477
4478 c->cmdindex = i;
4479
01a02ffc
SC		 4480 c->busaddr = (u32) cmd_dma_handle;
4481 temp64.val = (u64) err_dma_handle;
50a0decf
SC		 4482 c->ErrDesc.Addr = cpu_to_le64(err_dma_handle);
4483 c->ErrDesc.Len = cpu_to_le32(sizeof(*c->err_info));
edd16368
SC		 4484
4485 c->h = h;
4486 return c;
4487}
4488
edd16368
SC		 4489static void cmd_free(struct ctlr_info *h, struct CommandList *c)
4490{
4491 int i;
4492
4493 i = c - h->cmd_pool;
4494 clear_bit(i & (BITS_PER_LONG - 1),
4495 h->cmd_pool_bits + (i / BITS_PER_LONG));
edd16368
SC		 4496}
4497
edd16368
SC		 4498#ifdef CONFIG_COMPAT
4499
42a91641
DB		 4500static int hpsa_ioctl32_passthru(struct scsi_device *dev, int cmd,
4501 void __user *arg)
edd16368
SC		 4502{
4503 IOCTL32_Command_struct __user *arg32 =
4504 (IOCTL32_Command_struct __user *) arg;
4505 IOCTL_Command_struct arg64;
4506 IOCTL_Command_struct __user *p = compat_alloc_user_space(sizeof(arg64));
4507 int err;
4508 u32 cp;
4509
938abd84 4510 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 4511 err = 0;
4512 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
4513 sizeof(arg64.LUN_info));
4514 err |= copy_from_user(&arg64.Request, &arg32->Request,
4515 sizeof(arg64.Request));
4516 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
4517 sizeof(arg64.error_info));
4518 err |= get_user(arg64.buf_size, &arg32->buf_size);
4519 err |= get_user(cp, &arg32->buf);
4520 arg64.buf = compat_ptr(cp);
4521 err |= copy_to_user(p, &arg64, sizeof(arg64));
4522
4523 if (err)
4524 return -EFAULT;
4525
42a91641 4526 err = hpsa_ioctl(dev, CCISS_PASSTHRU, p);
edd16368
SC		 4527 if (err)
4528 return err;
4529 err |= copy_in_user(&arg32->error_info, &p->error_info,
4530 sizeof(arg32->error_info));
4531 if (err)
4532 return -EFAULT;
4533 return err;
4534}
4535
4536static int hpsa_ioctl32_big_passthru(struct scsi_device *dev,
42a91641 4537 int cmd, void __user *arg)
edd16368
SC		 4538{
4539 BIG_IOCTL32_Command_struct __user *arg32 =
4540 (BIG_IOCTL32_Command_struct __user *) arg;
4541 BIG_IOCTL_Command_struct arg64;
4542 BIG_IOCTL_Command_struct __user *p =
4543 compat_alloc_user_space(sizeof(arg64));
4544 int err;
4545 u32 cp;
4546
938abd84 4547 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 4548 err = 0;
4549 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
4550 sizeof(arg64.LUN_info));
4551 err |= copy_from_user(&arg64.Request, &arg32->Request,
4552 sizeof(arg64.Request));
4553 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
4554 sizeof(arg64.error_info));
4555 err |= get_user(arg64.buf_size, &arg32->buf_size);
4556 err |= get_user(arg64.malloc_size, &arg32->malloc_size);
4557 err |= get_user(cp, &arg32->buf);
4558 arg64.buf = compat_ptr(cp);
4559 err |= copy_to_user(p, &arg64, sizeof(arg64));
4560
4561 if (err)
4562 return -EFAULT;
4563
42a91641 4564 err = hpsa_ioctl(dev, CCISS_BIG_PASSTHRU, p);
edd16368
SC		 4565 if (err)
4566 return err;
4567 err |= copy_in_user(&arg32->error_info, &p->error_info,
4568 sizeof(arg32->error_info));
4569 if (err)
4570 return -EFAULT;
4571 return err;
4572}
71fe75a7 4573
42a91641 4574static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void __user *arg)
71fe75a7
SC		 4575{
4576 switch (cmd) {
4577 case CCISS_GETPCIINFO:
4578 case CCISS_GETINTINFO:
4579 case CCISS_SETINTINFO:
4580 case CCISS_GETNODENAME:
4581 case CCISS_SETNODENAME:
4582 case CCISS_GETHEARTBEAT:
4583 case CCISS_GETBUSTYPES:
4584 case CCISS_GETFIRMVER:
4585 case CCISS_GETDRIVVER:
4586 case CCISS_REVALIDVOLS:
4587 case CCISS_DEREGDISK:
4588 case CCISS_REGNEWDISK:
4589 case CCISS_REGNEWD:
4590 case CCISS_RESCANDISK:
4591 case CCISS_GETLUNINFO:
4592 return hpsa_ioctl(dev, cmd, arg);
4593
4594 case CCISS_PASSTHRU32:
4595 return hpsa_ioctl32_passthru(dev, cmd, arg);
4596 case CCISS_BIG_PASSTHRU32:
4597 return hpsa_ioctl32_big_passthru(dev, cmd, arg);
4598
4599 default:
4600 return -ENOIOCTLCMD;
4601 }
4602}
edd16368
SC		 4603#endif
4604
4605static int hpsa_getpciinfo_ioctl(struct ctlr_info *h, void __user *argp)
4606{
4607 struct hpsa_pci_info pciinfo;
4608
4609 if (!argp)
4610 return -EINVAL;
4611 pciinfo.domain = pci_domain_nr(h->pdev->bus);
4612 pciinfo.bus = h->pdev->bus->number;
4613 pciinfo.dev_fn = h->pdev->devfn;
4614 pciinfo.board_id = h->board_id;
4615 if (copy_to_user(argp, &pciinfo, sizeof(pciinfo)))
4616 return -EFAULT;
4617 return 0;
4618}
4619
4620static int hpsa_getdrivver_ioctl(struct ctlr_info *h, void __user *argp)
4621{
4622 DriverVer_type DriverVer;
4623 unsigned char vmaj, vmin, vsubmin;
4624 int rc;
4625
4626 rc = sscanf(HPSA_DRIVER_VERSION, "%hhu.%hhu.%hhu",
4627 &vmaj, &vmin, &vsubmin);
4628 if (rc != 3) {
4629 dev_info(&h->pdev->dev, "driver version string '%s' "
4630 "unrecognized.", HPSA_DRIVER_VERSION);
4631 vmaj = 0;
4632 vmin = 0;
4633 vsubmin = 0;
4634 }
4635 DriverVer = (vmaj << 16) | (vmin << 8) | vsubmin;
4636 if (!argp)
4637 return -EINVAL;
4638 if (copy_to_user(argp, &DriverVer, sizeof(DriverVer_type)))
4639 return -EFAULT;
4640 return 0;
4641}
4642
4643static int hpsa_passthru_ioctl(struct ctlr_info *h, void __user *argp)
4644{
4645 IOCTL_Command_struct iocommand;
4646 struct CommandList *c;
4647 char *buff = NULL;
50a0decf 4648 u64 temp64;
c1f63c8f 4649 int rc = 0;
edd16368
SC		 4650
4651 if (!argp)
4652 return -EINVAL;
4653 if (!capable(CAP_SYS_RAWIO))
4654 return -EPERM;
4655 if (copy_from_user(&iocommand, argp, sizeof(iocommand)))
4656 return -EFAULT;
4657 if ((iocommand.buf_size < 1) &&
4658 (iocommand.Request.Type.Direction != XFER_NONE)) {
4659 return -EINVAL;
4660 }
4661 if (iocommand.buf_size > 0) {
4662 buff = kmalloc(iocommand.buf_size, GFP_KERNEL);
4663 if (buff == NULL)
4664 return -EFAULT;
9233fb10 4665 if (iocommand.Request.Type.Direction & XFER_WRITE) {
b03a7771
SC		 4666 /* Copy the data into the buffer we created */
4667 if (copy_from_user(buff, iocommand.buf,
4668 iocommand.buf_size)) {
c1f63c8f
SC		 4669 rc = -EFAULT;
4670 goto out_kfree;
b03a7771
SC		 4671 }
4672 } else {
4673 memset(buff, 0, iocommand.buf_size);
edd16368 4674 }
b03a7771 4675 }
45fcb86e 4676 c = cmd_alloc(h);
edd16368 4677 if (c == NULL) {
c1f63c8f
SC		 4678 rc = -ENOMEM;
4679 goto out_kfree;
edd16368
SC		 4680 }
4681 /* Fill in the command type */
4682 c->cmd_type = CMD_IOCTL_PEND;
4683 /* Fill in Command Header */
4684 c->Header.ReplyQueue = 0; /* unused in simple mode */
4685 if (iocommand.buf_size > 0) { /* buffer to fill */
4686 c->Header.SGList = 1;
50a0decf 4687 c->Header.SGTotal = cpu_to_le16(1);
edd16368
SC		 4688 } else { /* no buffers to fill */
4689 c->Header.SGList = 0;
50a0decf 4690 c->Header.SGTotal = cpu_to_le16(0);
edd16368
SC		 4691 }
4692 memcpy(&c->Header.LUN, &iocommand.LUN_info, sizeof(c->Header.LUN));
edd16368
SC		 4693
4694 /* Fill in Request block */
4695 memcpy(&c->Request, &iocommand.Request,
4696 sizeof(c->Request));
4697
4698 /* Fill in the scatter gather information */
4699 if (iocommand.buf_size > 0) {
50a0decf 4700 temp64 = pci_map_single(h->pdev, buff,
edd16368 4701 iocommand.buf_size, PCI_DMA_BIDIRECTIONAL);
50a0decf
SC		 4702 if (dma_mapping_error(&h->pdev->dev, (dma_addr_t) temp64)) {
4703 c->SG[0].Addr = cpu_to_le64(0);
4704 c->SG[0].Len = cpu_to_le32(0);
bcc48ffa
SC		 4705 rc = -ENOMEM;
4706 goto out;
4707 }
50a0decf
SC		 4708 c->SG[0].Addr = cpu_to_le64(temp64);
4709 c->SG[0].Len = cpu_to_le32(iocommand.buf_size);
4710 c->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* not chaining */
edd16368 4711 }
a0c12413 4712 hpsa_scsi_do_simple_cmd_core_if_no_lockup(h, c);
c2dd32e0
SC		 4713 if (iocommand.buf_size > 0)
4714 hpsa_pci_unmap(h->pdev, c, 1, PCI_DMA_BIDIRECTIONAL);
edd16368
SC		 4715 check_ioctl_unit_attention(h, c);
4716
4717 /* Copy the error information out */
4718 memcpy(&iocommand.error_info, c->err_info,
4719 sizeof(iocommand.error_info));
4720 if (copy_to_user(argp, &iocommand, sizeof(iocommand))) {
c1f63c8f
SC		 4721 rc = -EFAULT;
4722 goto out;
edd16368 4723 }
9233fb10 4724 if ((iocommand.Request.Type.Direction & XFER_READ) &&
b03a7771 4725 iocommand.buf_size > 0) {
edd16368
SC		 4726 /* Copy the data out of the buffer we created */
4727 if (copy_to_user(iocommand.buf, buff, iocommand.buf_size)) {
c1f63c8f
SC		 4728 rc = -EFAULT;
4729 goto out;
edd16368
SC		 4730 }
4731 }
c1f63c8f 4732out:
45fcb86e 4733 cmd_free(h, c);
c1f63c8f
SC		 4734out_kfree:
4735 kfree(buff);
4736 return rc;
edd16368
SC		 4737}
4738
4739static int hpsa_big_passthru_ioctl(struct ctlr_info *h, void __user *argp)
4740{
4741 BIG_IOCTL_Command_struct *ioc;
4742 struct CommandList *c;
4743 unsigned char **buff = NULL;
4744 int *buff_size = NULL;
50a0decf 4745 u64 temp64;
edd16368
SC		 4746 BYTE sg_used = 0;
4747 int status = 0;
01a02ffc
SC		 4748 u32 left;
4749 u32 sz;
edd16368
SC		 4750 BYTE __user *data_ptr;
4751
4752 if (!argp)
4753 return -EINVAL;
4754 if (!capable(CAP_SYS_RAWIO))
4755 return -EPERM;
4756 ioc = (BIG_IOCTL_Command_struct *)
4757 kmalloc(sizeof(*ioc), GFP_KERNEL);
4758 if (!ioc) {
4759 status = -ENOMEM;
4760 goto cleanup1;
4761 }
4762 if (copy_from_user(ioc, argp, sizeof(*ioc))) {
4763 status = -EFAULT;
4764 goto cleanup1;
4765 }
4766 if ((ioc->buf_size < 1) &&
4767 (ioc->Request.Type.Direction != XFER_NONE)) {
4768 status = -EINVAL;
4769 goto cleanup1;
4770 }
4771 /* Check kmalloc limits using all SGs */
4772 if (ioc->malloc_size > MAX_KMALLOC_SIZE) {
4773 status = -EINVAL;
4774 goto cleanup1;
4775 }
d66ae08b 4776 if (ioc->buf_size > ioc->malloc_size * SG_ENTRIES_IN_CMD) {
edd16368
SC		 4777 status = -EINVAL;
4778 goto cleanup1;
4779 }
d66ae08b 4780 buff = kzalloc(SG_ENTRIES_IN_CMD * sizeof(char *), GFP_KERNEL);
edd16368
SC		 4781 if (!buff) {
4782 status = -ENOMEM;
4783 goto cleanup1;
4784 }
d66ae08b 4785 buff_size = kmalloc(SG_ENTRIES_IN_CMD * sizeof(int), GFP_KERNEL);
edd16368
SC		 4786 if (!buff_size) {
4787 status = -ENOMEM;
4788 goto cleanup1;
4789 }
4790 left = ioc->buf_size;
4791 data_ptr = ioc->buf;
4792 while (left) {
4793 sz = (left > ioc->malloc_size) ? ioc->malloc_size : left;
4794 buff_size[sg_used] = sz;
4795 buff[sg_used] = kmalloc(sz, GFP_KERNEL);
4796 if (buff[sg_used] == NULL) {
4797 status = -ENOMEM;
4798 goto cleanup1;
4799 }
9233fb10 4800 if (ioc->Request.Type.Direction & XFER_WRITE) {
edd16368 4801 if (copy_from_user(buff[sg_used], data_ptr, sz)) {
0758f4f7 4802 status = -EFAULT;
edd16368
SC		 4803 goto cleanup1;
4804 }
4805 } else
4806 memset(buff[sg_used], 0, sz);
4807 left -= sz;
4808 data_ptr += sz;
4809 sg_used++;
4810 }
45fcb86e 4811 c = cmd_alloc(h);
edd16368
SC		 4812 if (c == NULL) {
4813 status = -ENOMEM;
4814 goto cleanup1;
4815 }
4816 c->cmd_type = CMD_IOCTL_PEND;
4817 c->Header.ReplyQueue = 0;
50a0decf
SC		 4818 c->Header.SGList = (u8) sg_used;
4819 c->Header.SGTotal = cpu_to_le16(sg_used);
edd16368 4820 memcpy(&c->Header.LUN, &ioc->LUN_info, sizeof(c->Header.LUN));
edd16368
SC		 4821 memcpy(&c->Request, &ioc->Request, sizeof(c->Request));
4822 if (ioc->buf_size > 0) {
4823 int i;
4824 for (i = 0; i < sg_used; i++) {
50a0decf 4825 temp64 = pci_map_single(h->pdev, buff[i],
edd16368 4826 buff_size[i], PCI_DMA_BIDIRECTIONAL);
50a0decf
SC		 4827 if (dma_mapping_error(&h->pdev->dev,
4828 (dma_addr_t) temp64)) {
4829 c->SG[i].Addr = cpu_to_le64(0);
4830 c->SG[i].Len = cpu_to_le32(0);
bcc48ffa
SC		 4831 hpsa_pci_unmap(h->pdev, c, i,
4832 PCI_DMA_BIDIRECTIONAL);
4833 status = -ENOMEM;
e2d4a1f6 4834 goto cleanup0;
bcc48ffa 4835 }
50a0decf
SC		 4836 c->SG[i].Addr = cpu_to_le64(temp64);
4837 c->SG[i].Len = cpu_to_le32(buff_size[i]);
4838 c->SG[i].Ext = cpu_to_le32(0);
edd16368 4839 }
50a0decf 4840 c->SG[--i].Ext = cpu_to_le32(HPSA_SG_LAST);
edd16368 4841 }
a0c12413 4842 hpsa_scsi_do_simple_cmd_core_if_no_lockup(h, c);
b03a7771
SC		 4843 if (sg_used)
4844 hpsa_pci_unmap(h->pdev, c, sg_used, PCI_DMA_BIDIRECTIONAL);
edd16368
SC		 4845 check_ioctl_unit_attention(h, c);
4846 /* Copy the error information out */
4847 memcpy(&ioc->error_info, c->err_info, sizeof(ioc->error_info));
4848 if (copy_to_user(argp, ioc, sizeof(*ioc))) {
edd16368 4849 status = -EFAULT;
e2d4a1f6 4850 goto cleanup0;
edd16368 4851 }
9233fb10 4852 if ((ioc->Request.Type.Direction & XFER_READ) && ioc->buf_size > 0) {
2b08b3e9
DB		 4853 int i;
4854
edd16368
SC		 4855 /* Copy the data out of the buffer we created */
4856 BYTE __user *ptr = ioc->buf;
4857 for (i = 0; i < sg_used; i++) {
4858 if (copy_to_user(ptr, buff[i], buff_size[i])) {
edd16368 4859 status = -EFAULT;
e2d4a1f6 4860 goto cleanup0;
edd16368
SC		 4861 }
4862 ptr += buff_size[i];
4863 }
4864 }
edd16368 4865 status = 0;
e2d4a1f6 4866cleanup0:
45fcb86e 4867 cmd_free(h, c);
edd16368
SC		 4868cleanup1:
4869 if (buff) {
2b08b3e9
DB		 4870 int i;
4871
edd16368
SC		 4872 for (i = 0; i < sg_used; i++)
4873 kfree(buff[i]);
4874 kfree(buff);
4875 }
4876 kfree(buff_size);
4877 kfree(ioc);
4878 return status;
4879}
4880
4881static void check_ioctl_unit_attention(struct ctlr_info *h,
4882 struct CommandList *c)
4883{
4884 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
4885 c->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION)
4886 (void) check_for_unit_attention(h, c);
4887}
0390f0c0
SC		 4888
4889static int increment_passthru_count(struct ctlr_info *h)
4890{
4891 unsigned long flags;
4892
4893 spin_lock_irqsave(&h->passthru_count_lock, flags);
4894 if (h->passthru_count >= HPSA_MAX_CONCURRENT_PASSTHRUS) {
4895 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
4896 return -1;
4897 }
4898 h->passthru_count++;
4899 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
4900 return 0;
4901}
4902
4903static void decrement_passthru_count(struct ctlr_info *h)
4904{
4905 unsigned long flags;
4906
4907 spin_lock_irqsave(&h->passthru_count_lock, flags);
4908 if (h->passthru_count <= 0) {
4909 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
4910 /* not expecting to get here. */
4911 dev_warn(&h->pdev->dev, "Bug detected, passthru_count seems to be incorrect.\n");
4912 return;
4913 }
4914 h->passthru_count--;
4915 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
4916}
4917
edd16368
SC		 4918/*
4919 * ioctl
4920 */
42a91641 4921static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg)
edd16368
SC		 4922{
4923 struct ctlr_info *h;
4924 void __user *argp = (void __user *)arg;
0390f0c0 4925 int rc;
edd16368
SC		 4926
4927 h = sdev_to_hba(dev);
4928
4929 switch (cmd) {
4930 case CCISS_DEREGDISK:
4931 case CCISS_REGNEWDISK:
4932 case CCISS_REGNEWD:
a08a8471 4933 hpsa_scan_start(h->scsi_host);
edd16368
SC		 4934 return 0;
4935 case CCISS_GETPCIINFO:
4936 return hpsa_getpciinfo_ioctl(h, argp);
4937 case CCISS_GETDRIVVER:
4938 return hpsa_getdrivver_ioctl(h, argp);
4939 case CCISS_PASSTHRU:
0390f0c0
SC		 4940 if (increment_passthru_count(h))
4941 return -EAGAIN;
4942 rc = hpsa_passthru_ioctl(h, argp);
4943 decrement_passthru_count(h);
4944 return rc;
edd16368 4945 case CCISS_BIG_PASSTHRU:
0390f0c0
SC		 4946 if (increment_passthru_count(h))
4947 return -EAGAIN;
4948 rc = hpsa_big_passthru_ioctl(h, argp);
4949 decrement_passthru_count(h);
4950 return rc;
edd16368
SC		 4951 default:
4952 return -ENOTTY;
4953 }
4954}
4955
6f039790
GKH		 4956static int hpsa_send_host_reset(struct ctlr_info *h, unsigned char *scsi3addr,
4957 u8 reset_type)
64670ac8
SC		 4958{
4959 struct CommandList *c;
4960
4961 c = cmd_alloc(h);
4962 if (!c)
4963 return -ENOMEM;
a2dac136
SC		 4964 /* fill_cmd can't fail here, no data buffer to map */
4965 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
64670ac8
SC		 4966 RAID_CTLR_LUNID, TYPE_MSG);
4967 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to target reset */
4968 c->waiting = NULL;
4969 enqueue_cmd_and_start_io(h, c);
4970 /* Don't wait for completion, the reset won't complete. Don't free
4971 * the command either. This is the last command we will send before
4972 * re-initializing everything, so it doesn't matter and won't leak.
4973 */
4974 return 0;
4975}
4976
a2dac136 4977static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
b7bb24eb 4978 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
edd16368
SC		 4979 int cmd_type)
4980{
4981 int pci_dir = XFER_NONE;
75167d2c 4982 struct CommandList *a; /* for commands to be aborted */
edd16368
SC		 4983
4984 c->cmd_type = CMD_IOCTL_PEND;
4985 c->Header.ReplyQueue = 0;
4986 if (buff != NULL && size > 0) {
4987 c->Header.SGList = 1;
50a0decf 4988 c->Header.SGTotal = cpu_to_le16(1);
edd16368
SC		 4989 } else {
4990 c->Header.SGList = 0;
50a0decf 4991 c->Header.SGTotal = cpu_to_le16(0);
edd16368 4992 }
edd16368
SC		 4993 memcpy(c->Header.LUN.LunAddrBytes, scsi3addr, 8);
4994
edd16368
SC		 4995 if (cmd_type == TYPE_CMD) {
4996 switch (cmd) {
4997 case HPSA_INQUIRY:
4998 /* are we trying to read a vital product page */
b7bb24eb 4999 if (page_code & VPD_PAGE) {
edd16368 5000 c->Request.CDB[1] = 0x01;
b7bb24eb 5001 c->Request.CDB[2] = (page_code & 0xff);
edd16368
SC		 5002 }
5003 c->Request.CDBLen = 6;
a505b86f
SC		 5004 c->Request.type_attr_dir =
5005 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 5006 c->Request.Timeout = 0;
5007 c->Request.CDB[0] = HPSA_INQUIRY;
5008 c->Request.CDB[4] = size & 0xFF;
5009 break;
5010 case HPSA_REPORT_LOG:
5011 case HPSA_REPORT_PHYS:
5012 /* Talking to controller so It's a physical command
5013 mode = 00 target = 0. Nothing to write.
5014 */
5015 c->Request.CDBLen = 12;
a505b86f
SC		 5016 c->Request.type_attr_dir =
5017 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 5018 c->Request.Timeout = 0;
5019 c->Request.CDB[0] = cmd;
5020 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
5021 c->Request.CDB[7] = (size >> 16) & 0xFF;
5022 c->Request.CDB[8] = (size >> 8) & 0xFF;
5023 c->Request.CDB[9] = size & 0xFF;
5024 break;
edd16368
SC		 5025 case HPSA_CACHE_FLUSH:
5026 c->Request.CDBLen = 12;
a505b86f
SC		 5027 c->Request.type_attr_dir =
5028 TYPE_ATTR_DIR(cmd_type,
5029 ATTR_SIMPLE, XFER_WRITE);
edd16368
SC		 5030 c->Request.Timeout = 0;
5031 c->Request.CDB[0] = BMIC_WRITE;
5032 c->Request.CDB[6] = BMIC_CACHE_FLUSH;
bb158eab
SC		 5033 c->Request.CDB[7] = (size >> 8) & 0xFF;
5034 c->Request.CDB[8] = size & 0xFF;
edd16368
SC		 5035 break;
5036 case TEST_UNIT_READY:
5037 c->Request.CDBLen = 6;
a505b86f
SC		 5038 c->Request.type_attr_dir =
5039 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
edd16368
SC		 5040 c->Request.Timeout = 0;
5041 break;
283b4a9b
SC		 5042 case HPSA_GET_RAID_MAP:
5043 c->Request.CDBLen = 12;
a505b86f
SC		 5044 c->Request.type_attr_dir =
5045 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
283b4a9b
SC		 5046 c->Request.Timeout = 0;
5047 c->Request.CDB[0] = HPSA_CISS_READ;
5048 c->Request.CDB[1] = cmd;
5049 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
5050 c->Request.CDB[7] = (size >> 16) & 0xFF;
5051 c->Request.CDB[8] = (size >> 8) & 0xFF;
5052 c->Request.CDB[9] = size & 0xFF;
5053 break;
316b221a
SC		 5054 case BMIC_SENSE_CONTROLLER_PARAMETERS:
5055 c->Request.CDBLen = 10;
a505b86f
SC		 5056 c->Request.type_attr_dir =
5057 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
316b221a
SC		 5058 c->Request.Timeout = 0;
5059 c->Request.CDB[0] = BMIC_READ;
5060 c->Request.CDB[6] = BMIC_SENSE_CONTROLLER_PARAMETERS;
5061 c->Request.CDB[7] = (size >> 16) & 0xFF;
5062 c->Request.CDB[8] = (size >> 8) & 0xFF;
5063 break;
edd16368
SC		 5064 default:
5065 dev_warn(&h->pdev->dev, "unknown command 0x%c\n", cmd);
5066 BUG();
a2dac136 5067 return -1;
edd16368
SC		 5068 }
5069 } else if (cmd_type == TYPE_MSG) {
5070 switch (cmd) {
5071
5072 case HPSA_DEVICE_RESET_MSG:
5073 c->Request.CDBLen = 16;
a505b86f
SC		 5074 c->Request.type_attr_dir =
5075 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
edd16368 5076 c->Request.Timeout = 0; /* Don't time out */
64670ac8
SC		 5077 memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
5078 c->Request.CDB[0] = cmd;
21e89afd 5079 c->Request.CDB[1] = HPSA_RESET_TYPE_LUN;
edd16368
SC		 5080 /* If bytes 4-7 are zero, it means reset the */
5081 /* LunID device */
5082 c->Request.CDB[4] = 0x00;
5083 c->Request.CDB[5] = 0x00;
5084 c->Request.CDB[6] = 0x00;
5085 c->Request.CDB[7] = 0x00;
75167d2c
SC		 5086 break;
5087 case HPSA_ABORT_MSG:
5088 a = buff; /* point to command to be aborted */
2b08b3e9
DB		 5089 dev_dbg(&h->pdev->dev,
5090 "Abort Tag:0x%016llx request Tag:0x%016llx",
50a0decf 5091 a->Header.tag, c->Header.tag);
75167d2c 5092 c->Request.CDBLen = 16;
a505b86f
SC		 5093 c->Request.type_attr_dir =
5094 TYPE_ATTR_DIR(cmd_type,
5095 ATTR_SIMPLE, XFER_WRITE);
75167d2c
SC		 5096 c->Request.Timeout = 0; /* Don't time out */
5097 c->Request.CDB[0] = HPSA_TASK_MANAGEMENT;
5098 c->Request.CDB[1] = HPSA_TMF_ABORT_TASK;
5099 c->Request.CDB[2] = 0x00; /* reserved */
5100 c->Request.CDB[3] = 0x00; /* reserved */
5101 /* Tag to abort goes in CDB[4]-CDB[11] */
2b08b3e9
DB		 5102 memcpy(&c->Request.CDB[4], &a->Header.tag,
5103 sizeof(a->Header.tag));
75167d2c
SC		 5104 c->Request.CDB[12] = 0x00; /* reserved */
5105 c->Request.CDB[13] = 0x00; /* reserved */
5106 c->Request.CDB[14] = 0x00; /* reserved */
5107 c->Request.CDB[15] = 0x00; /* reserved */
edd16368 5108 break;
edd16368
SC		 5109 default:
5110 dev_warn(&h->pdev->dev, "unknown message type %d\n",
5111 cmd);
5112 BUG();
5113 }
5114 } else {
5115 dev_warn(&h->pdev->dev, "unknown command type %d\n", cmd_type);
5116 BUG();
5117 }
5118
a505b86f 5119 switch (GET_DIR(c->Request.type_attr_dir)) {
edd16368
SC		 5120 case XFER_READ:
5121 pci_dir = PCI_DMA_FROMDEVICE;
5122 break;
5123 case XFER_WRITE:
5124 pci_dir = PCI_DMA_TODEVICE;
5125 break;
5126 case XFER_NONE:
5127 pci_dir = PCI_DMA_NONE;
5128 break;
5129 default:
5130 pci_dir = PCI_DMA_BIDIRECTIONAL;
5131 }
a2dac136
SC		 5132 if (hpsa_map_one(h->pdev, c, buff, size, pci_dir))
5133 return -1;
5134 return 0;
edd16368
SC		 5135}
5136
5137/*
5138 * Map (physical) PCI mem into (virtual) kernel space
5139 */
5140static void __iomem *remap_pci_mem(ulong base, ulong size)
5141{
5142 ulong page_base = ((ulong) base) & PAGE_MASK;
5143 ulong page_offs = ((ulong) base) - page_base;
088ba34c
SC		 5144 void __iomem *page_remapped = ioremap_nocache(page_base,
5145 page_offs + size);
edd16368
SC		 5146
5147 return page_remapped ? (page_remapped + page_offs) : NULL;
5148}
5149
254f796b 5150static inline unsigned long get_next_completion(struct ctlr_info *h, u8 q)
edd16368 5151{
254f796b 5152 return h->access.command_completed(h, q);
edd16368
SC		 5153}
5154
900c5440 5155static inline bool interrupt_pending(struct ctlr_info *h)
edd16368
SC		 5156{
5157 return h->access.intr_pending(h);
5158}
5159
5160static inline long interrupt_not_for_us(struct ctlr_info *h)
5161{
10f66018
SC		 5162 return (h->access.intr_pending(h) == 0) ||
5163 (h->interrupts_enabled == 0);
edd16368
SC		 5164}
5165
01a02ffc
SC		 5166static inline int bad_tag(struct ctlr_info *h, u32 tag_index,
5167 u32 raw_tag)
edd16368
SC		 5168{
5169 if (unlikely(tag_index >= h->nr_cmds)) {
5170 dev_warn(&h->pdev->dev, "bad tag 0x%08x ignored.\n", raw_tag);
5171 return 1;
5172 }
5173 return 0;
5174}
5175
5a3d16f5 5176static inline void finish_cmd(struct CommandList *c)
edd16368 5177{
e85c5974 5178 dial_up_lockup_detection_on_fw_flash_complete(c->h, c);
c349775e
ST		 5179 if (likely(c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_SCSI
5180 || c->cmd_type == CMD_IOACCEL2))
1fb011fb 5181 complete_scsi_command(c);
edd16368
SC		 5182 else if (c->cmd_type == CMD_IOCTL_PEND)
5183 complete(c->waiting);
a104c99f
SC		 5184}
5185
a9a3a273
SC		 5186
5187static inline u32 hpsa_tag_discard_error_bits(struct ctlr_info *h, u32 tag)
a104c99f 5188{
a9a3a273
SC		 5189#define HPSA_PERF_ERROR_BITS ((1 << DIRECT_LOOKUP_SHIFT) - 1)
5190#define HPSA_SIMPLE_ERROR_BITS 0x03
960a30e7 5191 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
a9a3a273
SC		 5192 return tag & ~HPSA_SIMPLE_ERROR_BITS;
5193 return tag & ~HPSA_PERF_ERROR_BITS;
a104c99f
SC		 5194}
5195
303932fd 5196/* process completion of an indexed ("direct lookup") command */
1d94f94d 5197static inline void process_indexed_cmd(struct ctlr_info *h,
303932fd
DB		 5198 u32 raw_tag)
5199{
5200 u32 tag_index;
5201 struct CommandList *c;
5202
f2405db8 5203 tag_index = raw_tag >> DIRECT_LOOKUP_SHIFT;
1d94f94d
SC		 5204 if (!bad_tag(h, tag_index, raw_tag)) {
5205 c = h->cmd_pool + tag_index;
5206 finish_cmd(c);
5207 }
303932fd
DB		 5208}
5209
64670ac8
SC		 5210/* Some controllers, like p400, will give us one interrupt
5211 * after a soft reset, even if we turned interrupts off.
5212 * Only need to check for this in the hpsa_xxx_discard_completions
5213 * functions.
5214 */
5215static int ignore_bogus_interrupt(struct ctlr_info *h)
5216{
5217 if (likely(!reset_devices))
5218 return 0;
5219
5220 if (likely(h->interrupts_enabled))
5221 return 0;
5222
5223 dev_info(&h->pdev->dev, "Received interrupt while interrupts disabled "
5224 "(known firmware bug.) Ignoring.\n");
5225
5226 return 1;
5227}
5228
254f796b
MG		 5229/*
5230 * Convert &h->q[x] (passed to interrupt handlers) back to h.
5231 * Relies on (h-q[x] == x) being true for x such that
5232 * 0 <= x < MAX_REPLY_QUEUES.
5233 */
5234static struct ctlr_info *queue_to_hba(u8 *queue)
64670ac8 5235{
254f796b
MG		 5236 return container_of((queue - *queue), struct ctlr_info, q[0]);
5237}
5238
5239static irqreturn_t hpsa_intx_discard_completions(int irq, void *queue)
5240{
5241 struct ctlr_info *h = queue_to_hba(queue);
5242 u8 q = *(u8 *) queue;
64670ac8
SC		 5243 u32 raw_tag;
5244
5245 if (ignore_bogus_interrupt(h))
5246 return IRQ_NONE;
5247
5248 if (interrupt_not_for_us(h))
5249 return IRQ_NONE;
a0c12413 5250 h->last_intr_timestamp = get_jiffies_64();
64670ac8 5251 while (interrupt_pending(h)) {
254f796b 5252 raw_tag = get_next_completion(h, q);
64670ac8 5253 while (raw_tag != FIFO_EMPTY)
254f796b 5254 raw_tag = next_command(h, q);
64670ac8 5255 }
64670ac8
SC		 5256 return IRQ_HANDLED;
5257}
5258
254f796b 5259static irqreturn_t hpsa_msix_discard_completions(int irq, void *queue)
64670ac8 5260{
254f796b 5261 struct ctlr_info *h = queue_to_hba(queue);
64670ac8 5262 u32 raw_tag;
254f796b 5263 u8 q = *(u8 *) queue;
64670ac8
SC		 5264
5265 if (ignore_bogus_interrupt(h))
5266 return IRQ_NONE;
5267
a0c12413 5268 h->last_intr_timestamp = get_jiffies_64();
254f796b 5269 raw_tag = get_next_completion(h, q);
64670ac8 5270 while (raw_tag != FIFO_EMPTY)
254f796b 5271 raw_tag = next_command(h, q);
64670ac8
SC		 5272 return IRQ_HANDLED;
5273}
5274
254f796b 5275static irqreturn_t do_hpsa_intr_intx(int irq, void *queue)
edd16368 5276{
254f796b 5277 struct ctlr_info *h = queue_to_hba((u8 *) queue);
303932fd 5278 u32 raw_tag;
254f796b 5279 u8 q = *(u8 *) queue;
edd16368
SC		 5280
5281 if (interrupt_not_for_us(h))
5282 return IRQ_NONE;
a0c12413 5283 h->last_intr_timestamp = get_jiffies_64();
10f66018 5284 while (interrupt_pending(h)) {
254f796b 5285 raw_tag = get_next_completion(h, q);
10f66018 5286 while (raw_tag != FIFO_EMPTY) {
f2405db8 5287 process_indexed_cmd(h, raw_tag);
254f796b 5288 raw_tag = next_command(h, q);
10f66018
SC		 5289 }
5290 }
10f66018
SC		 5291 return IRQ_HANDLED;
5292}
5293
254f796b 5294static irqreturn_t do_hpsa_intr_msi(int irq, void *queue)
10f66018 5295{
254f796b 5296 struct ctlr_info *h = queue_to_hba(queue);
10f66018 5297 u32 raw_tag;
254f796b 5298 u8 q = *(u8 *) queue;
10f66018 5299
a0c12413 5300 h->last_intr_timestamp = get_jiffies_64();
254f796b 5301 raw_tag = get_next_completion(h, q);
303932fd 5302 while (raw_tag != FIFO_EMPTY) {
f2405db8 5303 process_indexed_cmd(h, raw_tag);
254f796b 5304 raw_tag = next_command(h, q);
edd16368 5305 }
edd16368
SC		 5306 return IRQ_HANDLED;
5307}
5308
a9a3a273
SC		 5309/* Send a message CDB to the firmware. Careful, this only works
5310 * in simple mode, not performant mode due to the tag lookup.
5311 * We only ever use this immediately after a controller reset.
5312 */
6f039790
GKH		 5313static int hpsa_message(struct pci_dev *pdev, unsigned char opcode,
5314 unsigned char type)
edd16368
SC		 5315{
5316 struct Command {
5317 struct CommandListHeader CommandHeader;
5318 struct RequestBlock Request;
5319 struct ErrDescriptor ErrorDescriptor;
5320 };
5321 struct Command *cmd;
5322 static const size_t cmd_sz = sizeof(*cmd) +
5323 sizeof(cmd->ErrorDescriptor);
5324 dma_addr_t paddr64;
2b08b3e9
DB		 5325 __le32 paddr32;
5326 u32 tag;
edd16368
SC		 5327 void __iomem *vaddr;
5328 int i, err;
5329
5330 vaddr = pci_ioremap_bar(pdev, 0);
5331 if (vaddr == NULL)
5332 return -ENOMEM;
5333
5334 /* The Inbound Post Queue only accepts 32-bit physical addresses for the
5335 * CCISS commands, so they must be allocated from the lower 4GiB of
5336 * memory.
5337 */
5338 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
5339 if (err) {
5340 iounmap(vaddr);
1eaec8f3 5341 return err;
edd16368
SC		 5342 }
5343
5344 cmd = pci_alloc_consistent(pdev, cmd_sz, &paddr64);
5345 if (cmd == NULL) {
5346 iounmap(vaddr);
5347 return -ENOMEM;
5348 }
5349
5350 /* This must fit, because of the 32-bit consistent DMA mask. Also,
5351 * although there's no guarantee, we assume that the address is at
5352 * least 4-byte aligned (most likely, it's page-aligned).
5353 */
2b08b3e9 5354 paddr32 = cpu_to_le32(paddr64);
edd16368
SC		 5355
5356 cmd->CommandHeader.ReplyQueue = 0;
5357 cmd->CommandHeader.SGList = 0;
50a0decf 5358 cmd->CommandHeader.SGTotal = cpu_to_le16(0);
2b08b3e9 5359 cmd->CommandHeader.tag = cpu_to_le64(paddr64);
edd16368
SC		 5360 memset(&cmd->CommandHeader.LUN.LunAddrBytes, 0, 8);
5361
5362 cmd->Request.CDBLen = 16;
a505b86f
SC		 5363 cmd->Request.type_attr_dir =
5364 TYPE_ATTR_DIR(TYPE_MSG, ATTR_HEADOFQUEUE, XFER_NONE);
edd16368
SC		 5365 cmd->Request.Timeout = 0; /* Don't time out */
5366 cmd->Request.CDB[0] = opcode;
5367 cmd->Request.CDB[1] = type;
5368 memset(&cmd->Request.CDB[2], 0, 14); /* rest of the CDB is reserved */
50a0decf 5369 cmd->ErrorDescriptor.Addr =
2b08b3e9 5370 cpu_to_le64((le32_to_cpu(paddr32) + sizeof(*cmd)));
50a0decf 5371 cmd->ErrorDescriptor.Len = cpu_to_le32(sizeof(struct ErrorInfo));
edd16368 5372
2b08b3e9 5373 writel(le32_to_cpu(paddr32), vaddr + SA5_REQUEST_PORT_OFFSET);
edd16368
SC		 5374
5375 for (i = 0; i < HPSA_MSG_SEND_RETRY_LIMIT; i++) {
5376 tag = readl(vaddr + SA5_REPLY_PORT_OFFSET);
2b08b3e9 5377 if ((tag & ~HPSA_SIMPLE_ERROR_BITS) == paddr64)
edd16368
SC		 5378 break;
5379 msleep(HPSA_MSG_SEND_RETRY_INTERVAL_MSECS);
5380 }
5381
5382 iounmap(vaddr);
5383
5384 /* we leak the DMA buffer here ... no choice since the controller could
5385 * still complete the command.
5386 */
5387 if (i == HPSA_MSG_SEND_RETRY_LIMIT) {
5388 dev_err(&pdev->dev, "controller message %02x:%02x timed out\n",
5389 opcode, type);
5390 return -ETIMEDOUT;
5391 }
5392
5393 pci_free_consistent(pdev, cmd_sz, cmd, paddr64);
5394
5395 if (tag & HPSA_ERROR_BIT) {
5396 dev_err(&pdev->dev, "controller message %02x:%02x failed\n",
5397 opcode, type);
5398 return -EIO;
5399 }
5400
5401 dev_info(&pdev->dev, "controller message %02x:%02x succeeded\n",
5402 opcode, type);
5403 return 0;
5404}
5405
edd16368
SC		 5406#define hpsa_noop(p) hpsa_message(p, 3, 0)
5407
1df8552a 5408static int hpsa_controller_hard_reset(struct pci_dev *pdev,
42a91641 5409 void __iomem *vaddr, u32 use_doorbell)
1df8552a 5410{
1df8552a
SC		 5411
5412 if (use_doorbell) {
5413 /* For everything after the P600, the PCI power state method
5414 * of resetting the controller doesn't work, so we have this
5415 * other way using the doorbell register.
5416 */
5417 dev_info(&pdev->dev, "using doorbell to reset controller\n");
cf0b08d0 5418 writel(use_doorbell, vaddr + SA5_DOORBELL);
85009239 5419
00701a96 5420 /* PMC hardware guys tell us we need a 10 second delay after
85009239
SC		 5421 * doorbell reset and before any attempt to talk to the board
5422 * at all to ensure that this actually works and doesn't fall
5423 * over in some weird corner cases.
5424 */
00701a96 5425 msleep(10000);
1df8552a
SC		 5426 } else { /* Try to do it the PCI power state way */
5427
5428 /* Quoting from the Open CISS Specification: "The Power
5429 * Management Control/Status Register (CSR) controls the power
5430 * state of the device. The normal operating state is D0,
5431 * CSR=00h. The software off state is D3, CSR=03h. To reset
5432 * the controller, place the interface device in D3 then to D0,
5433 * this causes a secondary PCI reset which will reset the
5434 * controller." */
2662cab8
DB		 5435
5436 int rc = 0;
5437
1df8552a 5438 dev_info(&pdev->dev, "using PCI PM to reset controller\n");
2662cab8 5439
1df8552a 5440 /* enter the D3hot power management state */
2662cab8
DB		 5441 rc = pci_set_power_state(pdev, PCI_D3hot);
5442 if (rc)
5443 return rc;
1df8552a
SC		 5444
5445 msleep(500);
5446
5447 /* enter the D0 power management state */
2662cab8
DB		 5448 rc = pci_set_power_state(pdev, PCI_D0);
5449 if (rc)
5450 return rc;
c4853efe
MM		 5451
5452 /*
5453 * The P600 requires a small delay when changing states.
5454 * Otherwise we may think the board did not reset and we bail.
5455 * This for kdump only and is particular to the P600.
5456 */
5457 msleep(500);
1df8552a
SC		 5458 }
5459 return 0;
5460}
5461
6f039790 5462static void init_driver_version(char *driver_version, int len)
580ada3c
SC		 5463{
5464 memset(driver_version, 0, len);
f79cfec6 5465 strncpy(driver_version, HPSA " " HPSA_DRIVER_VERSION, len - 1);
580ada3c
SC		 5466}
5467
6f039790 5468static int write_driver_ver_to_cfgtable(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 5469{
5470 char *driver_version;
5471 int i, size = sizeof(cfgtable->driver_version);
5472
5473 driver_version = kmalloc(size, GFP_KERNEL);
5474 if (!driver_version)
5475 return -ENOMEM;
5476
5477 init_driver_version(driver_version, size);
5478 for (i = 0; i < size; i++)
5479 writeb(driver_version[i], &cfgtable->driver_version[i]);
5480 kfree(driver_version);
5481 return 0;
5482}
5483
6f039790
GKH		 5484static void read_driver_ver_from_cfgtable(struct CfgTable __iomem *cfgtable,
5485 unsigned char *driver_ver)
580ada3c
SC		 5486{
5487 int i;
5488
5489 for (i = 0; i < sizeof(cfgtable->driver_version); i++)
5490 driver_ver[i] = readb(&cfgtable->driver_version[i]);
5491}
5492
6f039790 5493static int controller_reset_failed(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 5494{
5495
5496 char *driver_ver, *old_driver_ver;
5497 int rc, size = sizeof(cfgtable->driver_version);
5498
5499 old_driver_ver = kmalloc(2 * size, GFP_KERNEL);
5500 if (!old_driver_ver)
5501 return -ENOMEM;
5502 driver_ver = old_driver_ver + size;
5503
5504 /* After a reset, the 32 bytes of "driver version" in the cfgtable
5505 * should have been changed, otherwise we know the reset failed.
5506 */
5507 init_driver_version(old_driver_ver, size);
5508 read_driver_ver_from_cfgtable(cfgtable, driver_ver);
5509 rc = !memcmp(driver_ver, old_driver_ver, size);
5510 kfree(old_driver_ver);
5511 return rc;
5512}
edd16368 5513/* This does a hard reset of the controller using PCI power management
1df8552a 5514 * states or the using the doorbell register.
edd16368 5515 */
6f039790 5516static int hpsa_kdump_hard_reset_controller(struct pci_dev *pdev)
edd16368 5517{
1df8552a
SC		 5518 u64 cfg_offset;
5519 u32 cfg_base_addr;
5520 u64 cfg_base_addr_index;
5521 void __iomem *vaddr;
5522 unsigned long paddr;
580ada3c 5523 u32 misc_fw_support;
270d05de 5524 int rc;
1df8552a 5525 struct CfgTable __iomem *cfgtable;
cf0b08d0 5526 u32 use_doorbell;
18867659 5527 u32 board_id;
270d05de 5528 u16 command_register;
edd16368 5529
1df8552a
SC		 5530 /* For controllers as old as the P600, this is very nearly
5531 * the same thing as
edd16368
SC		 5532 *
5533 * pci_save_state(pci_dev);
5534 * pci_set_power_state(pci_dev, PCI_D3hot);
5535 * pci_set_power_state(pci_dev, PCI_D0);
5536 * pci_restore_state(pci_dev);
5537 *
1df8552a
SC		 5538 * For controllers newer than the P600, the pci power state
5539 * method of resetting doesn't work so we have another way
5540 * using the doorbell register.
edd16368 5541 */
18867659 5542
25c1e56a 5543 rc = hpsa_lookup_board_id(pdev, &board_id);
60f923b9
RE		 5544 if (rc < 0) {
5545 dev_warn(&pdev->dev, "Board ID not found\n");
5546 return rc;
5547 }
5548 if (!ctlr_is_resettable(board_id)) {
5549 dev_warn(&pdev->dev, "Controller not resettable\n");
25c1e56a
SC		 5550 return -ENODEV;
5551 }
46380786
SC		 5552
5553 /* if controller is soft- but not hard resettable... */
5554 if (!ctlr_is_hard_resettable(board_id))
5555 return -ENOTSUPP; /* try soft reset later. */
18867659 5556
270d05de
SC		 5557 /* Save the PCI command register */
5558 pci_read_config_word(pdev, 4, &command_register);
270d05de 5559 pci_save_state(pdev);
edd16368 5560
1df8552a
SC		 5561 /* find the first memory BAR, so we can find the cfg table */
5562 rc = hpsa_pci_find_memory_BAR(pdev, &paddr);
5563 if (rc)
5564 return rc;
5565 vaddr = remap_pci_mem(paddr, 0x250);
5566 if (!vaddr)
5567 return -ENOMEM;
edd16368 5568
1df8552a
SC		 5569 /* find cfgtable in order to check if reset via doorbell is supported */
5570 rc = hpsa_find_cfg_addrs(pdev, vaddr, &cfg_base_addr,
5571 &cfg_base_addr_index, &cfg_offset);
5572 if (rc)
5573 goto unmap_vaddr;
5574 cfgtable = remap_pci_mem(pci_resource_start(pdev,
5575 cfg_base_addr_index) + cfg_offset, sizeof(*cfgtable));
5576 if (!cfgtable) {
5577 rc = -ENOMEM;
5578 goto unmap_vaddr;
5579 }
580ada3c
SC		 5580 rc = write_driver_ver_to_cfgtable(cfgtable);
5581 if (rc)
03741d95 5582 goto unmap_cfgtable;
edd16368 5583
cf0b08d0
SC		 5584 /* If reset via doorbell register is supported, use that.
5585 * There are two such methods. Favor the newest method.
5586 */
1df8552a 5587 misc_fw_support = readl(&cfgtable->misc_fw_support);
cf0b08d0
SC		 5588 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET2;
5589 if (use_doorbell) {
5590 use_doorbell = DOORBELL_CTLR_RESET2;
5591 } else {
5592 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET;
5593 if (use_doorbell) {
050f7147
SC		 5594 dev_warn(&pdev->dev,
5595 "Soft reset not supported. Firmware update is required.\n");
64670ac8 5596 rc = -ENOTSUPP; /* try soft reset */
cf0b08d0
SC		 5597 goto unmap_cfgtable;
5598 }
5599 }
edd16368 5600
1df8552a
SC		 5601 rc = hpsa_controller_hard_reset(pdev, vaddr, use_doorbell);
5602 if (rc)
5603 goto unmap_cfgtable;
edd16368 5604
270d05de 5605 pci_restore_state(pdev);
270d05de 5606 pci_write_config_word(pdev, 4, command_register);
edd16368 5607
1df8552a
SC		 5608 /* Some devices (notably the HP Smart Array 5i Controller)
5609 need a little pause here */
5610 msleep(HPSA_POST_RESET_PAUSE_MSECS);
5611
fe5389c8
SC		 5612 rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_READY);
5613 if (rc) {
5614 dev_warn(&pdev->dev,
050f7147 5615 "Failed waiting for board to become ready after hard reset\n");
fe5389c8
SC		 5616 goto unmap_cfgtable;
5617 }
fe5389c8 5618
580ada3c
SC		 5619 rc = controller_reset_failed(vaddr);
5620 if (rc < 0)
5621 goto unmap_cfgtable;
5622 if (rc) {
64670ac8
SC		 5623 dev_warn(&pdev->dev, "Unable to successfully reset "
5624 "controller. Will try soft reset.\n");
5625 rc = -ENOTSUPP;
580ada3c 5626 } else {
64670ac8 5627 dev_info(&pdev->dev, "board ready after hard reset.\n");
1df8552a
SC		 5628 }
5629
5630unmap_cfgtable:
5631 iounmap(cfgtable);
5632
5633unmap_vaddr:
5634 iounmap(vaddr);
5635 return rc;
edd16368
SC		 5636}
5637
5638/*
5639 * We cannot read the structure directly, for portability we must use
5640 * the io functions.
5641 * This is for debug only.
5642 */
42a91641 5643static void print_cfg_table(struct device *dev, struct CfgTable __iomem *tb)
edd16368 5644{
58f8665c 5645#ifdef HPSA_DEBUG
edd16368
SC		 5646 int i;
5647 char temp_name[17];
5648
5649 dev_info(dev, "Controller Configuration information\n");
5650 dev_info(dev, "------------------------------------\n");
5651 for (i = 0; i < 4; i++)
5652 temp_name[i] = readb(&(tb->Signature[i]));
5653 temp_name[4] = '\0';
5654 dev_info(dev, " Signature = %s\n", temp_name);
5655 dev_info(dev, " Spec Number = %d\n", readl(&(tb->SpecValence)));
5656 dev_info(dev, " Transport methods supported = 0x%x\n",
5657 readl(&(tb->TransportSupport)));
5658 dev_info(dev, " Transport methods active = 0x%x\n",
5659 readl(&(tb->TransportActive)));
5660 dev_info(dev, " Requested transport Method = 0x%x\n",
5661 readl(&(tb->HostWrite.TransportRequest)));
5662 dev_info(dev, " Coalesce Interrupt Delay = 0x%x\n",
5663 readl(&(tb->HostWrite.CoalIntDelay)));
5664 dev_info(dev, " Coalesce Interrupt Count = 0x%x\n",
5665 readl(&(tb->HostWrite.CoalIntCount)));
69d6e33d 5666 dev_info(dev, " Max outstanding commands = %d\n",
edd16368
SC		 5667 readl(&(tb->CmdsOutMax)));
5668 dev_info(dev, " Bus Types = 0x%x\n", readl(&(tb->BusTypes)));
5669 for (i = 0; i < 16; i++)
5670 temp_name[i] = readb(&(tb->ServerName[i]));
5671 temp_name[16] = '\0';
5672 dev_info(dev, " Server Name = %s\n", temp_name);
5673 dev_info(dev, " Heartbeat Counter = 0x%x\n\n\n",
5674 readl(&(tb->HeartBeat)));
edd16368 5675#endif /* HPSA_DEBUG */
58f8665c 5676}
edd16368
SC		 5677
5678static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr)
5679{
5680 int i, offset, mem_type, bar_type;
5681
5682 if (pci_bar_addr == PCI_BASE_ADDRESS_0) /* looking for BAR zero? */
5683 return 0;
5684 offset = 0;
5685 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
5686 bar_type = pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE;
5687 if (bar_type == PCI_BASE_ADDRESS_SPACE_IO)
5688 offset += 4;
5689 else {
5690 mem_type = pci_resource_flags(pdev, i) &
5691 PCI_BASE_ADDRESS_MEM_TYPE_MASK;
5692 switch (mem_type) {
5693 case PCI_BASE_ADDRESS_MEM_TYPE_32:
5694 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
5695 offset += 4; /* 32 bit */
5696 break;
5697 case PCI_BASE_ADDRESS_MEM_TYPE_64:
5698 offset += 8;
5699 break;
5700 default: /* reserved in PCI 2.2 */
5701 dev_warn(&pdev->dev,
5702 "base address is invalid\n");
5703 return -1;
5704 break;
5705 }
5706 }
5707 if (offset == pci_bar_addr - PCI_BASE_ADDRESS_0)
5708 return i + 1;
5709 }
5710 return -1;
5711}
5712
5713/* If MSI/MSI-X is supported by the kernel we will try to enable it on
050f7147 5714 * controllers that are capable. If not, we use legacy INTx mode.
edd16368
SC		 5715 */
5716
6f039790 5717static void hpsa_interrupt_mode(struct ctlr_info *h)
edd16368
SC		 5718{
5719#ifdef CONFIG_PCI_MSI
254f796b
MG		 5720 int err, i;
5721 struct msix_entry hpsa_msix_entries[MAX_REPLY_QUEUES];
5722
5723 for (i = 0; i < MAX_REPLY_QUEUES; i++) {
5724 hpsa_msix_entries[i].vector = 0;
5725 hpsa_msix_entries[i].entry = i;
5726 }
edd16368
SC		 5727
5728 /* Some boards advertise MSI but don't really support it */
6b3f4c52
SC		 5729 if ((h->board_id == 0x40700E11) || (h->board_id == 0x40800E11) ||
5730 (h->board_id == 0x40820E11) || (h->board_id == 0x40830E11))
edd16368 5731 goto default_int_mode;
55c06c71 5732 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSIX)) {
050f7147 5733 dev_info(&h->pdev->dev, "MSI-X capable controller\n");
eee0f03a 5734 h->msix_vector = MAX_REPLY_QUEUES;
f89439bc
SC		 5735 if (h->msix_vector > num_online_cpus())
5736 h->msix_vector = num_online_cpus();
18fce3c4
AG		 5737 err = pci_enable_msix_range(h->pdev, hpsa_msix_entries,
5738 1, h->msix_vector);
5739 if (err < 0) {
5740 dev_warn(&h->pdev->dev, "MSI-X init failed %d\n", err);
5741 h->msix_vector = 0;
5742 goto single_msi_mode;
5743 } else if (err < h->msix_vector) {
55c06c71 5744 dev_warn(&h->pdev->dev, "only %d MSI-X vectors "
edd16368 5745 "available\n", err);
edd16368 5746 }
18fce3c4
AG		 5747 h->msix_vector = err;
5748 for (i = 0; i < h->msix_vector; i++)
5749 h->intr[i] = hpsa_msix_entries[i].vector;
5750 return;
edd16368 5751 }
18fce3c4 5752single_msi_mode:
55c06c71 5753 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSI)) {
050f7147 5754 dev_info(&h->pdev->dev, "MSI capable controller\n");
55c06c71 5755 if (!pci_enable_msi(h->pdev))
edd16368
SC		 5756 h->msi_vector = 1;
5757 else
55c06c71 5758 dev_warn(&h->pdev->dev, "MSI init failed\n");
edd16368
SC		 5759 }
5760default_int_mode:
5761#endif /* CONFIG_PCI_MSI */
5762 /* if we get here we're going to use the default interrupt mode */
a9a3a273 5763 h->intr[h->intr_mode] = h->pdev->irq;
edd16368
SC		 5764}
5765
6f039790 5766static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id)
e5c880d1
SC		 5767{
5768 int i;
5769 u32 subsystem_vendor_id, subsystem_device_id;
5770
5771 subsystem_vendor_id = pdev->subsystem_vendor;
5772 subsystem_device_id = pdev->subsystem_device;
5773 *board_id = ((subsystem_device_id << 16) & 0xffff0000) |
5774 subsystem_vendor_id;
5775
5776 for (i = 0; i < ARRAY_SIZE(products); i++)
5777 if (*board_id == products[i].board_id)
5778 return i;
5779
6798cc0a
SC		 5780 if ((subsystem_vendor_id != PCI_VENDOR_ID_HP &&
5781 subsystem_vendor_id != PCI_VENDOR_ID_COMPAQ) ||
5782 !hpsa_allow_any) {
e5c880d1
SC		 5783 dev_warn(&pdev->dev, "unrecognized board ID: "
5784 "0x%08x, ignoring.\n", *board_id);
5785 return -ENODEV;
5786 }
5787 return ARRAY_SIZE(products) - 1; /* generic unknown smart array */
5788}
5789
6f039790
GKH		 5790static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
5791 unsigned long *memory_bar)
3a7774ce
SC		 5792{
5793 int i;
5794
5795 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
12d2cd47 5796 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
3a7774ce 5797 /* addressing mode bits already removed */
12d2cd47
SC		 5798 *memory_bar = pci_resource_start(pdev, i);
5799 dev_dbg(&pdev->dev, "memory BAR = %lx\n",
3a7774ce
SC		 5800 *memory_bar);
5801 return 0;
5802 }
12d2cd47 5803 dev_warn(&pdev->dev, "no memory BAR found\n");
3a7774ce
SC		 5804 return -ENODEV;
5805}
5806
6f039790
GKH		 5807static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
5808 int wait_for_ready)
2c4c8c8b 5809{
fe5389c8 5810 int i, iterations;
2c4c8c8b 5811 u32 scratchpad;
fe5389c8
SC		 5812 if (wait_for_ready)
5813 iterations = HPSA_BOARD_READY_ITERATIONS;
5814 else
5815 iterations = HPSA_BOARD_NOT_READY_ITERATIONS;
2c4c8c8b 5816
fe5389c8
SC		 5817 for (i = 0; i < iterations; i++) {
5818 scratchpad = readl(vaddr + SA5_SCRATCHPAD_OFFSET);
5819 if (wait_for_ready) {
5820 if (scratchpad == HPSA_FIRMWARE_READY)
5821 return 0;
5822 } else {
5823 if (scratchpad != HPSA_FIRMWARE_READY)
5824 return 0;
5825 }
2c4c8c8b
SC		 5826 msleep(HPSA_BOARD_READY_POLL_INTERVAL_MSECS);
5827 }
fe5389c8 5828 dev_warn(&pdev->dev, "board not ready, timed out.\n");
2c4c8c8b
SC		 5829 return -ENODEV;
5830}
5831
6f039790
GKH		 5832static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
5833 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
5834 u64 *cfg_offset)
a51fd47f
SC		 5835{
5836 *cfg_base_addr = readl(vaddr + SA5_CTCFG_OFFSET);
5837 *cfg_offset = readl(vaddr + SA5_CTMEM_OFFSET);
5838 *cfg_base_addr &= (u32) 0x0000ffff;
5839 *cfg_base_addr_index = find_PCI_BAR_index(pdev, *cfg_base_addr);
5840 if (*cfg_base_addr_index == -1) {
5841 dev_warn(&pdev->dev, "cannot find cfg_base_addr_index\n");
5842 return -ENODEV;
5843 }
5844 return 0;
5845}
5846
6f039790 5847static int hpsa_find_cfgtables(struct ctlr_info *h)
edd16368 5848{
01a02ffc
SC		 5849 u64 cfg_offset;
5850 u32 cfg_base_addr;
5851 u64 cfg_base_addr_index;
303932fd 5852 u32 trans_offset;
a51fd47f 5853 int rc;
77c4495c 5854
a51fd47f
SC		 5855 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
5856 &cfg_base_addr_index, &cfg_offset);
5857 if (rc)
5858 return rc;
77c4495c 5859 h->cfgtable = remap_pci_mem(pci_resource_start(h->pdev,
a51fd47f 5860 cfg_base_addr_index) + cfg_offset, sizeof(*h->cfgtable));
cd3c81c4
RE		 5861 if (!h->cfgtable) {
5862 dev_err(&h->pdev->dev, "Failed mapping cfgtable\n");
77c4495c 5863 return -ENOMEM;
cd3c81c4 5864 }
580ada3c
SC		 5865 rc = write_driver_ver_to_cfgtable(h->cfgtable);
5866 if (rc)
5867 return rc;
77c4495c 5868 /* Find performant mode table. */
a51fd47f 5869 trans_offset = readl(&h->cfgtable->TransMethodOffset);
77c4495c
SC		 5870 h->transtable = remap_pci_mem(pci_resource_start(h->pdev,
5871 cfg_base_addr_index)+cfg_offset+trans_offset,
5872 sizeof(*h->transtable));
5873 if (!h->transtable)
5874 return -ENOMEM;
5875 return 0;
5876}
5877
6f039790 5878static void hpsa_get_max_perf_mode_cmds(struct ctlr_info *h)
cba3d38b
SC		 5879{
5880 h->max_commands = readl(&(h->cfgtable->MaxPerformantModeCommands));
72ceeaec
SC		 5881
5882 /* Limit commands in memory limited kdump scenario. */
5883 if (reset_devices && h->max_commands > 32)
5884 h->max_commands = 32;
5885
cba3d38b
SC		 5886 if (h->max_commands < 16) {
5887 dev_warn(&h->pdev->dev, "Controller reports "
5888 "max supported commands of %d, an obvious lie. "
5889 "Using 16. Ensure that firmware is up to date.\n",
5890 h->max_commands);
5891 h->max_commands = 16;
5892 }
5893}
5894
c7ee65b3
WS		 5895/* If the controller reports that the total max sg entries is greater than 512,
5896 * then we know that chained SG blocks work. (Original smart arrays did not
5897 * support chained SG blocks and would return zero for max sg entries.)
5898 */
5899static int hpsa_supports_chained_sg_blocks(struct ctlr_info *h)
5900{
5901 return h->maxsgentries > 512;
5902}
5903
b93d7536
SC		 5904/* Interrogate the hardware for some limits:
5905 * max commands, max SG elements without chaining, and with chaining,
5906 * SG chain block size, etc.
5907 */
6f039790 5908static void hpsa_find_board_params(struct ctlr_info *h)
b93d7536 5909{
cba3d38b 5910 hpsa_get_max_perf_mode_cmds(h);
45fcb86e 5911 h->nr_cmds = h->max_commands;
b93d7536 5912 h->maxsgentries = readl(&(h->cfgtable->MaxScatterGatherElements));
283b4a9b 5913 h->fw_support = readl(&(h->cfgtable->misc_fw_support));
c7ee65b3
WS		 5914 if (hpsa_supports_chained_sg_blocks(h)) {
5915 /* Limit in-command s/g elements to 32 save dma'able memory. */
b93d7536 5916 h->max_cmd_sg_entries = 32;
1a63ea6f 5917 h->chainsize = h->maxsgentries - h->max_cmd_sg_entries;
b93d7536
SC		 5918 h->maxsgentries--; /* save one for chain pointer */
5919 } else {
c7ee65b3
WS		 5920 /*
5921 * Original smart arrays supported at most 31 s/g entries
5922 * embedded inline in the command (trying to use more
5923 * would lock up the controller)
5924 */
5925 h->max_cmd_sg_entries = 31;
1a63ea6f 5926 h->maxsgentries = 31; /* default to traditional values */
c7ee65b3 5927 h->chainsize = 0;
b93d7536 5928 }
75167d2c
SC		 5929
5930 /* Find out what task management functions are supported and cache */
5931 h->TMFSupportFlags = readl(&(h->cfgtable->TMFSupportFlags));
0e7a7fce
ST		 5932 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags))
5933 dev_warn(&h->pdev->dev, "Physical aborts not supported\n");
5934 if (!(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
5935 dev_warn(&h->pdev->dev, "Logical aborts not supported\n");
b93d7536
SC		 5936}
5937
76c46e49
SC		 5938static inline bool hpsa_CISS_signature_present(struct ctlr_info *h)
5939{
0fc9fd40 5940 if (!check_signature(h->cfgtable->Signature, "CISS", 4)) {
050f7147 5941 dev_err(&h->pdev->dev, "not a valid CISS config table\n");
76c46e49
SC		 5942 return false;
5943 }
5944 return true;
5945}
5946
97a5e98c 5947static inline void hpsa_set_driver_support_bits(struct ctlr_info *h)
f7c39101 5948{
97a5e98c 5949 u32 driver_support;
f7c39101 5950
97a5e98c 5951 driver_support = readl(&(h->cfgtable->driver_support));
0b9e7b74
AB		 5952 /* Need to enable prefetch in the SCSI core for 6400 in x86 */
5953#ifdef CONFIG_X86
97a5e98c 5954 driver_support |= ENABLE_SCSI_PREFETCH;
f7c39101 5955#endif
28e13446
SC		 5956 driver_support |= ENABLE_UNIT_ATTN;
5957 writel(driver_support, &(h->cfgtable->driver_support));
f7c39101
SC		 5958}
5959
3d0eab67
SC		 5960/* Disable DMA prefetch for the P600. Otherwise an ASIC bug may result
5961 * in a prefetch beyond physical memory.
5962 */
5963static inline void hpsa_p600_dma_prefetch_quirk(struct ctlr_info *h)
5964{
5965 u32 dma_prefetch;
5966
5967 if (h->board_id != 0x3225103C)
5968 return;
5969 dma_prefetch = readl(h->vaddr + I2O_DMA1_CFG);
5970 dma_prefetch |= 0x8000;
5971 writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG);
5972}
5973
76438d08
SC		 5974static void hpsa_wait_for_clear_event_notify_ack(struct ctlr_info *h)
5975{
5976 int i;
5977 u32 doorbell_value;
5978 unsigned long flags;
5979 /* wait until the clear_event_notify bit 6 is cleared by controller. */
5980 for (i = 0; i < MAX_CONFIG_WAIT; i++) {
5981 spin_lock_irqsave(&h->lock, flags);
5982 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
5983 spin_unlock_irqrestore(&h->lock, flags);
5984 if (!(doorbell_value & DOORBELL_CLEAR_EVENTS))
5985 break;
5986 /* delay and try again */
5987 msleep(20);
5988 }
5989}
5990
6f039790 5991static void hpsa_wait_for_mode_change_ack(struct ctlr_info *h)
eb6b2ae9
SC		 5992{
5993 int i;
6eaf46fd
SC		 5994 u32 doorbell_value;
5995 unsigned long flags;
eb6b2ae9
SC		 5996
5997 /* under certain very rare conditions, this can take awhile.
5998 * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right
5999 * as we enter this code.)
6000 */
6001 for (i = 0; i < MAX_CONFIG_WAIT; i++) {
6eaf46fd
SC		 6002 spin_lock_irqsave(&h->lock, flags);
6003 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
6004 spin_unlock_irqrestore(&h->lock, flags);
382be668 6005 if (!(doorbell_value & CFGTBL_ChangeReq))
eb6b2ae9
SC		 6006 break;
6007 /* delay and try again */
60d3f5b0 6008 usleep_range(10000, 20000);
eb6b2ae9 6009 }
3f4336f3
SC		 6010}
6011
6f039790 6012static int hpsa_enter_simple_mode(struct ctlr_info *h)
3f4336f3
SC		 6013{
6014 u32 trans_support;
6015
6016 trans_support = readl(&(h->cfgtable->TransportSupport));
6017 if (!(trans_support & SIMPLE_MODE))
6018 return -ENOTSUPP;
6019
6020 h->max_commands = readl(&(h->cfgtable->CmdsOutMax));
283b4a9b 6021
3f4336f3
SC		 6022 /* Update the field, and then ring the doorbell */
6023 writel(CFGTBL_Trans_Simple, &(h->cfgtable->HostWrite.TransportRequest));
b9af4937 6024 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
3f4336f3
SC		 6025 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
6026 hpsa_wait_for_mode_change_ack(h);
eb6b2ae9 6027 print_cfg_table(&h->pdev->dev, h->cfgtable);
283b4a9b
SC		 6028 if (!(readl(&(h->cfgtable->TransportActive)) & CFGTBL_Trans_Simple))
6029 goto error;
960a30e7 6030 h->transMethod = CFGTBL_Trans_Simple;
eb6b2ae9 6031 return 0;
283b4a9b 6032error:
050f7147 6033 dev_err(&h->pdev->dev, "failed to enter simple mode\n");
283b4a9b 6034 return -ENODEV;
eb6b2ae9
SC		 6035}
6036
6f039790 6037static int hpsa_pci_init(struct ctlr_info *h)
77c4495c 6038{
eb6b2ae9 6039 int prod_index, err;
edd16368 6040
e5c880d1
SC		 6041 prod_index = hpsa_lookup_board_id(h->pdev, &h->board_id);
6042 if (prod_index < 0)
60f923b9 6043 return prod_index;
e5c880d1
SC		 6044 h->product_name = products[prod_index].product_name;
6045 h->access = *(products[prod_index].access);
edd16368 6046
e5a44df8
MG		 6047 pci_disable_link_state(h->pdev, PCIE_LINK_STATE_L0S |
6048 PCIE_LINK_STATE_L1 | PCIE_LINK_STATE_CLKPM);
6049
55c06c71 6050 err = pci_enable_device(h->pdev);
edd16368 6051 if (err) {
55c06c71 6052 dev_warn(&h->pdev->dev, "unable to enable PCI device\n");
edd16368
SC		 6053 return err;
6054 }
6055
f79cfec6 6056 err = pci_request_regions(h->pdev, HPSA);
edd16368 6057 if (err) {
55c06c71
SC		 6058 dev_err(&h->pdev->dev,
6059 "cannot obtain PCI resources, aborting\n");
edd16368
SC		 6060 return err;
6061 }
4fa604e1
RE		 6062
6063 pci_set_master(h->pdev);
6064
6b3f4c52 6065 hpsa_interrupt_mode(h);
12d2cd47 6066 err = hpsa_pci_find_memory_BAR(h->pdev, &h->paddr);
3a7774ce 6067 if (err)
edd16368 6068 goto err_out_free_res;
edd16368 6069 h->vaddr = remap_pci_mem(h->paddr, 0x250);
204892e9
SC		 6070 if (!h->vaddr) {
6071 err = -ENOMEM;
6072 goto err_out_free_res;
6073 }
fe5389c8 6074 err = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
2c4c8c8b 6075 if (err)
edd16368 6076 goto err_out_free_res;
77c4495c
SC		 6077 err = hpsa_find_cfgtables(h);
6078 if (err)
edd16368 6079 goto err_out_free_res;
b93d7536 6080 hpsa_find_board_params(h);
edd16368 6081
76c46e49 6082 if (!hpsa_CISS_signature_present(h)) {
edd16368
SC		 6083 err = -ENODEV;
6084 goto err_out_free_res;
6085 }
97a5e98c 6086 hpsa_set_driver_support_bits(h);
3d0eab67 6087 hpsa_p600_dma_prefetch_quirk(h);
eb6b2ae9
SC		 6088 err = hpsa_enter_simple_mode(h);
6089 if (err)
edd16368 6090 goto err_out_free_res;
edd16368
SC		 6091 return 0;
6092
6093err_out_free_res:
204892e9
SC		 6094 if (h->transtable)
6095 iounmap(h->transtable);
6096 if (h->cfgtable)
6097 iounmap(h->cfgtable);
6098 if (h->vaddr)
6099 iounmap(h->vaddr);
f0bd0b68 6100 pci_disable_device(h->pdev);
55c06c71 6101 pci_release_regions(h->pdev);
edd16368
SC		 6102 return err;
6103}
6104
6f039790 6105static void hpsa_hba_inquiry(struct ctlr_info *h)
339b2b14
SC		 6106{
6107 int rc;
6108
6109#define HBA_INQUIRY_BYTE_COUNT 64
6110 h->hba_inquiry_data = kmalloc(HBA_INQUIRY_BYTE_COUNT, GFP_KERNEL);
6111 if (!h->hba_inquiry_data)
6112 return;
6113 rc = hpsa_scsi_do_inquiry(h, RAID_CTLR_LUNID, 0,
6114 h->hba_inquiry_data, HBA_INQUIRY_BYTE_COUNT);
6115 if (rc != 0) {
6116 kfree(h->hba_inquiry_data);
6117 h->hba_inquiry_data = NULL;
6118 }
6119}
6120
6f039790 6121static int hpsa_init_reset_devices(struct pci_dev *pdev)
4c2a8c40 6122{
1df8552a 6123 int rc, i;
3b747298 6124 void __iomem *vaddr;
4c2a8c40
SC		 6125
6126 if (!reset_devices)
6127 return 0;
6128
132aa220
TH		 6129 /* kdump kernel is loading, we don't know in which state is
6130 * the pci interface. The dev->enable_cnt is equal zero
6131 * so we call enable+disable, wait a while and switch it on.
6132 */
6133 rc = pci_enable_device(pdev);
6134 if (rc) {
6135 dev_warn(&pdev->dev, "Failed to enable PCI device\n");
6136 return -ENODEV;
6137 }
6138 pci_disable_device(pdev);
6139 msleep(260); /* a randomly chosen number */
6140 rc = pci_enable_device(pdev);
6141 if (rc) {
6142 dev_warn(&pdev->dev, "failed to enable device.\n");
6143 return -ENODEV;
6144 }
4fa604e1 6145
859c75ab 6146 pci_set_master(pdev);
4fa604e1 6147
3b747298
TH		 6148 vaddr = pci_ioremap_bar(pdev, 0);
6149 if (vaddr == NULL) {
6150 rc = -ENOMEM;
6151 goto out_disable;
6152 }
6153 writel(SA5_INTR_OFF, vaddr + SA5_REPLY_INTR_MASK_OFFSET);
6154 iounmap(vaddr);
6155
1df8552a
SC		 6156 /* Reset the controller with a PCI power-cycle or via doorbell */
6157 rc = hpsa_kdump_hard_reset_controller(pdev);
4c2a8c40 6158
1df8552a
SC		 6159 /* -ENOTSUPP here means we cannot reset the controller
6160 * but it's already (and still) up and running in
18867659
SC		 6161 * "performant mode". Or, it might be 640x, which can't reset
6162 * due to concerns about shared bbwc between 6402/6404 pair.
1df8552a 6163 */
adf1b3a3 6164 if (rc)
132aa220 6165 goto out_disable;
4c2a8c40
SC		 6166
6167 /* Now try to get the controller to respond to a no-op */
1ba66c9c 6168 dev_info(&pdev->dev, "Waiting for controller to respond to no-op\n");
4c2a8c40
SC		 6169 for (i = 0; i < HPSA_POST_RESET_NOOP_RETRIES; i++) {
6170 if (hpsa_noop(pdev) == 0)
6171 break;
6172 else
6173 dev_warn(&pdev->dev, "no-op failed%s\n",
6174 (i < 11 ? "; re-trying" : ""));
6175 }
132aa220
TH		 6176
6177out_disable:
6178
6179 pci_disable_device(pdev);
6180 return rc;
4c2a8c40
SC		 6181}
6182
6f039790 6183static int hpsa_allocate_cmd_pool(struct ctlr_info *h)
2e9d1b36
SC		 6184{
6185 h->cmd_pool_bits = kzalloc(
6186 DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG) *
6187 sizeof(unsigned long), GFP_KERNEL);
6188 h->cmd_pool = pci_alloc_consistent(h->pdev,
6189 h->nr_cmds * sizeof(*h->cmd_pool),
6190 &(h->cmd_pool_dhandle));
6191 h->errinfo_pool = pci_alloc_consistent(h->pdev,
6192 h->nr_cmds * sizeof(*h->errinfo_pool),
6193 &(h->errinfo_pool_dhandle));
6194 if ((h->cmd_pool_bits == NULL)
6195 || (h->cmd_pool == NULL)
6196 || (h->errinfo_pool == NULL)) {
6197 dev_err(&h->pdev->dev, "out of memory in %s", __func__);
2c143342 6198 goto clean_up;
2e9d1b36
SC		 6199 }
6200 return 0;
2c143342
RE		 6201clean_up:
6202 hpsa_free_cmd_pool(h);
6203 return -ENOMEM;
2e9d1b36
SC		 6204}
6205
6206static void hpsa_free_cmd_pool(struct ctlr_info *h)
6207{
6208 kfree(h->cmd_pool_bits);
6209 if (h->cmd_pool)
6210 pci_free_consistent(h->pdev,
6211 h->nr_cmds * sizeof(struct CommandList),
6212 h->cmd_pool, h->cmd_pool_dhandle);
aca9012a
SC		 6213 if (h->ioaccel2_cmd_pool)
6214 pci_free_consistent(h->pdev,
6215 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
6216 h->ioaccel2_cmd_pool, h->ioaccel2_cmd_pool_dhandle);
2e9d1b36
SC		 6217 if (h->errinfo_pool)
6218 pci_free_consistent(h->pdev,
6219 h->nr_cmds * sizeof(struct ErrorInfo),
6220 h->errinfo_pool,
6221 h->errinfo_pool_dhandle);
e1f7de0c
MG		 6222 if (h->ioaccel_cmd_pool)
6223 pci_free_consistent(h->pdev,
6224 h->nr_cmds * sizeof(struct io_accel1_cmd),
6225 h->ioaccel_cmd_pool, h->ioaccel_cmd_pool_dhandle);
2e9d1b36
SC		 6226}
6227
41b3cf08
SC		 6228static void hpsa_irq_affinity_hints(struct ctlr_info *h)
6229{
ec429952 6230 int i, cpu;
41b3cf08
SC		 6231
6232 cpu = cpumask_first(cpu_online_mask);
6233 for (i = 0; i < h->msix_vector; i++) {
ec429952 6234 irq_set_affinity_hint(h->intr[i], get_cpu_mask(cpu));
41b3cf08
SC		 6235 cpu = cpumask_next(cpu, cpu_online_mask);
6236 }
6237}
6238
ec501a18
RE		 6239/* clear affinity hints and free MSI-X, MSI, or legacy INTx vectors */
6240static void hpsa_free_irqs(struct ctlr_info *h)
6241{
6242 int i;
6243
6244 if (!h->msix_vector || h->intr_mode != PERF_MODE_INT) {
6245 /* Single reply queue, only one irq to free */
6246 i = h->intr_mode;
6247 irq_set_affinity_hint(h->intr[i], NULL);
6248 free_irq(h->intr[i], &h->q[i]);
6249 return;
6250 }
6251
6252 for (i = 0; i < h->msix_vector; i++) {
6253 irq_set_affinity_hint(h->intr[i], NULL);
6254 free_irq(h->intr[i], &h->q[i]);
6255 }
a4e17fc1
RE		 6256 for (; i < MAX_REPLY_QUEUES; i++)
6257 h->q[i] = 0;
ec501a18
RE		 6258}
6259
9ee61794
RE		 6260/* returns 0 on success; cleans up and returns -Enn on error */
6261static int hpsa_request_irqs(struct ctlr_info *h,
0ae01a32
SC		 6262 irqreturn_t (*msixhandler)(int, void *),
6263 irqreturn_t (*intxhandler)(int, void *))
6264{
254f796b 6265 int rc, i;
0ae01a32 6266
254f796b
MG		 6267 /*
6268 * initialize h->q[x] = x so that interrupt handlers know which
6269 * queue to process.
6270 */
6271 for (i = 0; i < MAX_REPLY_QUEUES; i++)
6272 h->q[i] = (u8) i;
6273
eee0f03a 6274 if (h->intr_mode == PERF_MODE_INT && h->msix_vector > 0) {
254f796b 6275 /* If performant mode and MSI-X, use multiple reply queues */
a4e17fc1 6276 for (i = 0; i < h->msix_vector; i++) {
254f796b
MG		 6277 rc = request_irq(h->intr[i], msixhandler,
6278 0, h->devname,
6279 &h->q[i]);
a4e17fc1
RE		 6280 if (rc) {
6281 int j;
6282
6283 dev_err(&h->pdev->dev,
6284 "failed to get irq %d for %s\n",
6285 h->intr[i], h->devname);
6286 for (j = 0; j < i; j++) {
6287 free_irq(h->intr[j], &h->q[j]);
6288 h->q[j] = 0;
6289 }
6290 for (; j < MAX_REPLY_QUEUES; j++)
6291 h->q[j] = 0;
6292 return rc;
6293 }
6294 }
41b3cf08 6295 hpsa_irq_affinity_hints(h);
254f796b
MG		 6296 } else {
6297 /* Use single reply pool */
eee0f03a 6298 if (h->msix_vector > 0 || h->msi_vector) {
254f796b
MG		 6299 rc = request_irq(h->intr[h->intr_mode],
6300 msixhandler, 0, h->devname,
6301 &h->q[h->intr_mode]);
6302 } else {
6303 rc = request_irq(h->intr[h->intr_mode],
6304 intxhandler, IRQF_SHARED, h->devname,
6305 &h->q[h->intr_mode]);
6306 }
6307 }
0ae01a32
SC		 6308 if (rc) {
6309 dev_err(&h->pdev->dev, "unable to get irq %d for %s\n",
6310 h->intr[h->intr_mode], h->devname);
6311 return -ENODEV;
6312 }
6313 return 0;
6314}
6315
6f039790 6316static int hpsa_kdump_soft_reset(struct ctlr_info *h)
64670ac8
SC		 6317{
6318 if (hpsa_send_host_reset(h, RAID_CTLR_LUNID,
6319 HPSA_RESET_TYPE_CONTROLLER)) {
6320 dev_warn(&h->pdev->dev, "Resetting array controller failed.\n");
6321 return -EIO;
6322 }
6323
6324 dev_info(&h->pdev->dev, "Waiting for board to soft reset.\n");
6325 if (hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_NOT_READY)) {
6326 dev_warn(&h->pdev->dev, "Soft reset had no effect.\n");
6327 return -1;
6328 }
6329
6330 dev_info(&h->pdev->dev, "Board reset, awaiting READY status.\n");
6331 if (hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY)) {
6332 dev_warn(&h->pdev->dev, "Board failed to become ready "
6333 "after soft reset.\n");
6334 return -1;
6335 }
6336
6337 return 0;
6338}
6339
0097f0f4 6340static void hpsa_free_irqs_and_disable_msix(struct ctlr_info *h)
64670ac8 6341{
ec501a18 6342 hpsa_free_irqs(h);
64670ac8 6343#ifdef CONFIG_PCI_MSI
0097f0f4
SC		 6344 if (h->msix_vector) {
6345 if (h->pdev->msix_enabled)
6346 pci_disable_msix(h->pdev);
6347 } else if (h->msi_vector) {
6348 if (h->pdev->msi_enabled)
6349 pci_disable_msi(h->pdev);
6350 }
64670ac8 6351#endif /* CONFIG_PCI_MSI */
0097f0f4
SC		 6352}
6353
072b0518
SC		 6354static void hpsa_free_reply_queues(struct ctlr_info *h)
6355{
6356 int i;
6357
6358 for (i = 0; i < h->nreply_queues; i++) {
6359 if (!h->reply_queue[i].head)
6360 continue;
6361 pci_free_consistent(h->pdev, h->reply_queue_size,
6362 h->reply_queue[i].head, h->reply_queue[i].busaddr);
6363 h->reply_queue[i].head = NULL;
6364 h->reply_queue[i].busaddr = 0;
6365 }
6366}
6367
0097f0f4
SC		 6368static void hpsa_undo_allocations_after_kdump_soft_reset(struct ctlr_info *h)
6369{
6370 hpsa_free_irqs_and_disable_msix(h);
64670ac8
SC		 6371 hpsa_free_sg_chain_blocks(h);
6372 hpsa_free_cmd_pool(h);
e1f7de0c 6373 kfree(h->ioaccel1_blockFetchTable);
64670ac8 6374 kfree(h->blockFetchTable);
072b0518 6375 hpsa_free_reply_queues(h);
64670ac8
SC		 6376 if (h->vaddr)
6377 iounmap(h->vaddr);
6378 if (h->transtable)
6379 iounmap(h->transtable);
6380 if (h->cfgtable)
6381 iounmap(h->cfgtable);
132aa220 6382 pci_disable_device(h->pdev);
64670ac8
SC		 6383 pci_release_regions(h->pdev);
6384 kfree(h);
6385}
6386
a0c12413 6387/* Called when controller lockup detected. */
f2405db8 6388static void fail_all_outstanding_cmds(struct ctlr_info *h)
a0c12413 6389{
f2405db8 6390 int i;
a0c12413
SC		 6391 struct CommandList *c = NULL;
6392
f2405db8
DB		 6393 for (i = 0; i < h->nr_cmds; i++) {
6394 if (!test_bit(i & (BITS_PER_LONG - 1),
6395 h->cmd_pool_bits + (i / BITS_PER_LONG)))
6396 continue;
6397 c = h->cmd_pool + i;
a0c12413 6398 c->err_info->CommandStatus = CMD_HARDWARE_ERR;
5a3d16f5 6399 finish_cmd(c);
a0c12413
SC		 6400 }
6401}
6402
094963da
SC		 6403static void set_lockup_detected_for_all_cpus(struct ctlr_info *h, u32 value)
6404{
6405 int i, cpu;
6406
6407 cpu = cpumask_first(cpu_online_mask);
6408 for (i = 0; i < num_online_cpus(); i++) {
6409 u32 *lockup_detected;
6410 lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
6411 *lockup_detected = value;
6412 cpu = cpumask_next(cpu, cpu_online_mask);
6413 }
6414 wmb(); /* be sure the per-cpu variables are out to memory */
6415}
6416
a0c12413
SC		 6417static void controller_lockup_detected(struct ctlr_info *h)
6418{
6419 unsigned long flags;
094963da 6420 u32 lockup_detected;
a0c12413 6421
a0c12413
SC		 6422 h->access.set_intr_mask(h, HPSA_INTR_OFF);
6423 spin_lock_irqsave(&h->lock, flags);
094963da
SC		 6424 lockup_detected = readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
6425 if (!lockup_detected) {
6426 /* no heartbeat, but controller gave us a zero. */
6427 dev_warn(&h->pdev->dev,
6428 "lockup detected but scratchpad register is zero\n");
6429 lockup_detected = 0xffffffff;
6430 }
6431 set_lockup_detected_for_all_cpus(h, lockup_detected);
a0c12413
SC		 6432 spin_unlock_irqrestore(&h->lock, flags);
6433 dev_warn(&h->pdev->dev, "Controller lockup detected: 0x%08x\n",
094963da 6434 lockup_detected);
a0c12413
SC		 6435 pci_disable_device(h->pdev);
6436 spin_lock_irqsave(&h->lock, flags);
f2405db8 6437 fail_all_outstanding_cmds(h);
a0c12413
SC		 6438 spin_unlock_irqrestore(&h->lock, flags);
6439}
6440
a0c12413
SC		 6441static void detect_controller_lockup(struct ctlr_info *h)
6442{
6443 u64 now;
6444 u32 heartbeat;
6445 unsigned long flags;
6446
a0c12413
SC		 6447 now = get_jiffies_64();
6448 /* If we've received an interrupt recently, we're ok. */
6449 if (time_after64(h->last_intr_timestamp +
e85c5974 6450 (h->heartbeat_sample_interval), now))
a0c12413
SC		 6451 return;
6452
6453 /*
6454 * If we've already checked the heartbeat recently, we're ok.
6455 * This could happen if someone sends us a signal. We
6456 * otherwise don't care about signals in this thread.
6457 */
6458 if (time_after64(h->last_heartbeat_timestamp +
e85c5974 6459 (h->heartbeat_sample_interval), now))
a0c12413
SC		 6460 return;
6461
6462 /* If heartbeat has not changed since we last looked, we're not ok. */
6463 spin_lock_irqsave(&h->lock, flags);
6464 heartbeat = readl(&h->cfgtable->HeartBeat);
6465 spin_unlock_irqrestore(&h->lock, flags);
6466 if (h->last_heartbeat == heartbeat) {
6467 controller_lockup_detected(h);
6468 return;
6469 }
6470
6471 /* We're ok. */
6472 h->last_heartbeat = heartbeat;
6473 h->last_heartbeat_timestamp = now;
6474}
6475
9846590e 6476static void hpsa_ack_ctlr_events(struct ctlr_info *h)
76438d08
SC		 6477{
6478 int i;
6479 char *event_type;
6480
e863d68e
ST		 6481 /* Clear the driver-requested rescan flag */
6482 h->drv_req_rescan = 0;
6483
76438d08 6484 /* Ask the controller to clear the events we're handling. */
1f7cee8c
SC		 6485 if ((h->transMethod & (CFGTBL_Trans_io_accel1
6486 | CFGTBL_Trans_io_accel2)) &&
76438d08
SC		 6487 (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE ||
6488 h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)) {
6489
6490 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE)
6491 event_type = "state change";
6492 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)
6493 event_type = "configuration change";
6494 /* Stop sending new RAID offload reqs via the IO accelerator */
6495 scsi_block_requests(h->scsi_host);
6496 for (i = 0; i < h->ndevices; i++)
6497 h->dev[i]->offload_enabled = 0;
23100dd9 6498 hpsa_drain_accel_commands(h);
76438d08
SC		 6499 /* Set 'accelerator path config change' bit */
6500 dev_warn(&h->pdev->dev,
6501 "Acknowledging event: 0x%08x (HP SSD Smart Path %s)\n",
6502 h->events, event_type);
6503 writel(h->events, &(h->cfgtable->clear_event_notify));
6504 /* Set the "clear event notify field update" bit 6 */
6505 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
6506 /* Wait until ctlr clears 'clear event notify field', bit 6 */
6507 hpsa_wait_for_clear_event_notify_ack(h);
6508 scsi_unblock_requests(h->scsi_host);
6509 } else {
6510 /* Acknowledge controller notification events. */
6511 writel(h->events, &(h->cfgtable->clear_event_notify));
6512 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
6513 hpsa_wait_for_clear_event_notify_ack(h);
6514#if 0
6515 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
6516 hpsa_wait_for_mode_change_ack(h);
6517#endif
6518 }
9846590e 6519 return;
76438d08
SC		 6520}
6521
6522/* Check a register on the controller to see if there are configuration
6523 * changes (added/changed/removed logical drives, etc.) which mean that
e863d68e
ST		 6524 * we should rescan the controller for devices.
6525 * Also check flag for driver-initiated rescan.
76438d08 6526 */
9846590e 6527static int hpsa_ctlr_needs_rescan(struct ctlr_info *h)
76438d08 6528{
9846590e
SC		 6529 if (h->drv_req_rescan)
6530 return 1;
6531
76438d08 6532 if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
9846590e 6533 return 0;
76438d08
SC		 6534
6535 h->events = readl(&(h->cfgtable->event_notify));
9846590e
SC		 6536 return h->events & RESCAN_REQUIRED_EVENT_BITS;
6537}
76438d08 6538
9846590e
SC		 6539/*
6540 * Check if any of the offline devices have become ready
6541 */
6542static int hpsa_offline_devices_ready(struct ctlr_info *h)
6543{
6544 unsigned long flags;
6545 struct offline_device_entry *d;
6546 struct list_head *this, *tmp;
6547
6548 spin_lock_irqsave(&h->offline_device_lock, flags);
6549 list_for_each_safe(this, tmp, &h->offline_device_list) {
6550 d = list_entry(this, struct offline_device_entry,
6551 offline_list);
6552 spin_unlock_irqrestore(&h->offline_device_lock, flags);
d1fea47c
SC		 6553 if (!hpsa_volume_offline(h, d->scsi3addr)) {
6554 spin_lock_irqsave(&h->offline_device_lock, flags);
6555 list_del(&d->offline_list);
6556 spin_unlock_irqrestore(&h->offline_device_lock, flags);
9846590e 6557 return 1;
d1fea47c 6558 }
9846590e
SC		 6559 spin_lock_irqsave(&h->offline_device_lock, flags);
6560 }
6561 spin_unlock_irqrestore(&h->offline_device_lock, flags);
6562 return 0;
76438d08
SC		 6563}
6564
9846590e 6565
8a98db73 6566static void hpsa_monitor_ctlr_worker(struct work_struct *work)
a0c12413
SC		 6567{
6568 unsigned long flags;
8a98db73
SC		 6569 struct ctlr_info *h = container_of(to_delayed_work(work),
6570 struct ctlr_info, monitor_ctlr_work);
6571 detect_controller_lockup(h);
094963da 6572 if (lockup_detected(h))
8a98db73 6573 return;
9846590e
SC		 6574
6575 if (hpsa_ctlr_needs_rescan(h) || hpsa_offline_devices_ready(h)) {
6576 scsi_host_get(h->scsi_host);
6577 h->drv_req_rescan = 0;
6578 hpsa_ack_ctlr_events(h);
6579 hpsa_scan_start(h->scsi_host);
6580 scsi_host_put(h->scsi_host);
6581 }
6582
8a98db73
SC		 6583 spin_lock_irqsave(&h->lock, flags);
6584 if (h->remove_in_progress) {
6585 spin_unlock_irqrestore(&h->lock, flags);
a0c12413
SC		 6586 return;
6587 }
8a98db73
SC		 6588 schedule_delayed_work(&h->monitor_ctlr_work,
6589 h->heartbeat_sample_interval);
6590 spin_unlock_irqrestore(&h->lock, flags);
a0c12413
SC		 6591}
6592
6f039790 6593static int hpsa_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
edd16368 6594{
4c2a8c40 6595 int dac, rc;
edd16368 6596 struct ctlr_info *h;
64670ac8
SC		 6597 int try_soft_reset = 0;
6598 unsigned long flags;
edd16368
SC		 6599
6600 if (number_of_controllers == 0)
6601 printk(KERN_INFO DRIVER_NAME "\n");
edd16368 6602
4c2a8c40 6603 rc = hpsa_init_reset_devices(pdev);
64670ac8
SC		 6604 if (rc) {
6605 if (rc != -ENOTSUPP)
6606 return rc;
6607 /* If the reset fails in a particular way (it has no way to do
6608 * a proper hard reset, so returns -ENOTSUPP) we can try to do
6609 * a soft reset once we get the controller configured up to the
6610 * point that it can accept a command.
6611 */
6612 try_soft_reset = 1;
6613 rc = 0;
6614 }
6615
6616reinit_after_soft_reset:
edd16368 6617
303932fd
DB		 6618 /* Command structures must be aligned on a 32-byte boundary because
6619 * the 5 lower bits of the address are used by the hardware. and by
6620 * the driver. See comments in hpsa.h for more info.
6621 */
303932fd 6622 BUILD_BUG_ON(sizeof(struct CommandList) % COMMANDLIST_ALIGNMENT);
edd16368
SC		 6623 h = kzalloc(sizeof(*h), GFP_KERNEL);
6624 if (!h)
ecd9aad4 6625 return -ENOMEM;
edd16368 6626
55c06c71 6627 h->pdev = pdev;
a9a3a273 6628 h->intr_mode = hpsa_simple_mode ? SIMPLE_MODE_INT : PERF_MODE_INT;
9846590e 6629 INIT_LIST_HEAD(&h->offline_device_list);
6eaf46fd 6630 spin_lock_init(&h->lock);
9846590e 6631 spin_lock_init(&h->offline_device_lock);
6eaf46fd 6632 spin_lock_init(&h->scan_lock);
0390f0c0 6633 spin_lock_init(&h->passthru_count_lock);
094963da
SC		 6634
6635 /* Allocate and clear per-cpu variable lockup_detected */
6636 h->lockup_detected = alloc_percpu(u32);
2a5ac326
SC		 6637 if (!h->lockup_detected) {
6638 rc = -ENOMEM;
094963da 6639 goto clean1;
2a5ac326 6640 }
094963da
SC		 6641 set_lockup_detected_for_all_cpus(h, 0);
6642
55c06c71 6643 rc = hpsa_pci_init(h);
ecd9aad4 6644 if (rc != 0)
edd16368
SC		 6645 goto clean1;
6646
f79cfec6 6647 sprintf(h->devname, HPSA "%d", number_of_controllers);
edd16368
SC		 6648 h->ctlr = number_of_controllers;
6649 number_of_controllers++;
edd16368
SC		 6650
6651 /* configure PCI DMA stuff */
ecd9aad4
SC		 6652 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
6653 if (rc == 0) {
edd16368 6654 dac = 1;
ecd9aad4
SC		 6655 } else {
6656 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6657 if (rc == 0) {
6658 dac = 0;
6659 } else {
6660 dev_err(&pdev->dev, "no suitable DMA available\n");
6661 goto clean1;
6662 }
edd16368
SC		 6663 }
6664
6665 /* make sure the board interrupts are off */
6666 h->access.set_intr_mask(h, HPSA_INTR_OFF);
10f66018 6667
9ee61794 6668 if (hpsa_request_irqs(h, do_hpsa_intr_msi, do_hpsa_intr_intx))
edd16368 6669 goto clean2;
303932fd
DB		 6670 dev_info(&pdev->dev, "%s: <0x%x> at IRQ %d%s using DAC\n",
6671 h->devname, pdev->device,
a9a3a273 6672 h->intr[h->intr_mode], dac ? "" : " not");
8947fd10
RE		 6673 rc = hpsa_allocate_cmd_pool(h);
6674 if (rc)
6675 goto clean2_and_free_irqs;
33a2ffce
SC		 6676 if (hpsa_allocate_sg_chain_blocks(h))
6677 goto clean4;
a08a8471
SC		 6678 init_waitqueue_head(&h->scan_wait_queue);
6679 h->scan_finished = 1; /* no scan currently in progress */
edd16368
SC		 6680
6681 pci_set_drvdata(pdev, h);
9a41338e 6682 h->ndevices = 0;
316b221a 6683 h->hba_mode_enabled = 0;
9a41338e
SC		 6684 h->scsi_host = NULL;
6685 spin_lock_init(&h->devlock);
64670ac8
SC		 6686 hpsa_put_ctlr_into_performant_mode(h);
6687
6688 /* At this point, the controller is ready to take commands.
6689 * Now, if reset_devices and the hard reset didn't work, try
6690 * the soft reset and see if that works.
6691 */
6692 if (try_soft_reset) {
6693
6694 /* This is kind of gross. We may or may not get a completion
6695 * from the soft reset command, and if we do, then the value
6696 * from the fifo may or may not be valid. So, we wait 10 secs
6697 * after the reset throwing away any completions we get during
6698 * that time. Unregister the interrupt handler and register
6699 * fake ones to scoop up any residual completions.
6700 */
6701 spin_lock_irqsave(&h->lock, flags);
6702 h->access.set_intr_mask(h, HPSA_INTR_OFF);
6703 spin_unlock_irqrestore(&h->lock, flags);
ec501a18 6704 hpsa_free_irqs(h);
9ee61794 6705 rc = hpsa_request_irqs(h, hpsa_msix_discard_completions,
64670ac8
SC		 6706 hpsa_intx_discard_completions);
6707 if (rc) {
9ee61794
RE		 6708 dev_warn(&h->pdev->dev,
6709 "Failed to request_irq after soft reset.\n");
64670ac8
SC		 6710 goto clean4;
6711 }
6712
6713 rc = hpsa_kdump_soft_reset(h);
6714 if (rc)
6715 /* Neither hard nor soft reset worked, we're hosed. */
6716 goto clean4;
6717
6718 dev_info(&h->pdev->dev, "Board READY.\n");
6719 dev_info(&h->pdev->dev,
6720 "Waiting for stale completions to drain.\n");
6721 h->access.set_intr_mask(h, HPSA_INTR_ON);
6722 msleep(10000);
6723 h->access.set_intr_mask(h, HPSA_INTR_OFF);
6724
6725 rc = controller_reset_failed(h->cfgtable);
6726 if (rc)
6727 dev_info(&h->pdev->dev,
6728 "Soft reset appears to have failed.\n");
6729
6730 /* since the controller's reset, we have to go back and re-init
6731 * everything. Easiest to just forget what we've done and do it
6732 * all over again.
6733 */
6734 hpsa_undo_allocations_after_kdump_soft_reset(h);
6735 try_soft_reset = 0;
6736 if (rc)
6737 /* don't go to clean4, we already unallocated */
6738 return -ENODEV;
6739
6740 goto reinit_after_soft_reset;
6741 }
edd16368 6742
316b221a
SC		 6743 /* Enable Accelerated IO path at driver layer */
6744 h->acciopath_status = 1;
da0697bd 6745
e863d68e
ST		 6746 h->drv_req_rescan = 0;
6747
edd16368
SC		 6748 /* Turn the interrupts on so we can service requests */
6749 h->access.set_intr_mask(h, HPSA_INTR_ON);
6750
339b2b14 6751 hpsa_hba_inquiry(h);
edd16368 6752 hpsa_register_scsi(h); /* hook ourselves into SCSI subsystem */
8a98db73
SC		 6753
6754 /* Monitor the controller for firmware lockups */
6755 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
6756 INIT_DELAYED_WORK(&h->monitor_ctlr_work, hpsa_monitor_ctlr_worker);
6757 schedule_delayed_work(&h->monitor_ctlr_work,
6758 h->heartbeat_sample_interval);
88bf6d62 6759 return 0;
edd16368
SC		 6760
6761clean4:
33a2ffce 6762 hpsa_free_sg_chain_blocks(h);
2e9d1b36 6763 hpsa_free_cmd_pool(h);
8947fd10 6764clean2_and_free_irqs:
ec501a18 6765 hpsa_free_irqs(h);
edd16368
SC		 6766clean2:
6767clean1:
094963da
SC		 6768 if (h->lockup_detected)
6769 free_percpu(h->lockup_detected);
edd16368 6770 kfree(h);
ecd9aad4 6771 return rc;
edd16368
SC		 6772}
6773
6774static void hpsa_flush_cache(struct ctlr_info *h)
6775{
6776 char *flush_buf;
6777 struct CommandList *c;
702890e3
SC		 6778
6779 /* Don't bother trying to flush the cache if locked up */
094963da 6780 if (unlikely(lockup_detected(h)))
702890e3 6781 return;
edd16368
SC		 6782 flush_buf = kzalloc(4, GFP_KERNEL);
6783 if (!flush_buf)
6784 return;
6785
45fcb86e 6786 c = cmd_alloc(h);
edd16368 6787 if (!c) {
45fcb86e 6788 dev_warn(&h->pdev->dev, "cmd_alloc returned NULL!\n");
edd16368
SC		 6789 goto out_of_memory;
6790 }
a2dac136
SC		 6791 if (fill_cmd(c, HPSA_CACHE_FLUSH, h, flush_buf, 4, 0,
6792 RAID_CTLR_LUNID, TYPE_CMD)) {
6793 goto out;
6794 }
edd16368
SC		 6795 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_TODEVICE);
6796 if (c->err_info->CommandStatus != 0)
a2dac136 6797out:
edd16368
SC		 6798 dev_warn(&h->pdev->dev,
6799 "error flushing cache on controller\n");
45fcb86e 6800 cmd_free(h, c);
edd16368
SC		 6801out_of_memory:
6802 kfree(flush_buf);
6803}
6804
6805static void hpsa_shutdown(struct pci_dev *pdev)
6806{
6807 struct ctlr_info *h;
6808
6809 h = pci_get_drvdata(pdev);
6810 /* Turn board interrupts off and send the flush cache command
6811 * sendcmd will turn off interrupt, and send the flush...
6812 * To write all data in the battery backed cache to disks
6813 */
6814 hpsa_flush_cache(h);
6815 h->access.set_intr_mask(h, HPSA_INTR_OFF);
0097f0f4 6816 hpsa_free_irqs_and_disable_msix(h);
edd16368
SC		 6817}
6818
6f039790 6819static void hpsa_free_device_info(struct ctlr_info *h)
55e14e76
SC		 6820{
6821 int i;
6822
6823 for (i = 0; i < h->ndevices; i++)
6824 kfree(h->dev[i]);
6825}
6826
6f039790 6827static void hpsa_remove_one(struct pci_dev *pdev)
edd16368
SC		 6828{
6829 struct ctlr_info *h;
8a98db73 6830 unsigned long flags;
edd16368
SC		 6831
6832 if (pci_get_drvdata(pdev) == NULL) {
a0c12413 6833 dev_err(&pdev->dev, "unable to remove device\n");
edd16368
SC		 6834 return;
6835 }
6836 h = pci_get_drvdata(pdev);
8a98db73
SC		 6837
6838 /* Get rid of any controller monitoring work items */
6839 spin_lock_irqsave(&h->lock, flags);
6840 h->remove_in_progress = 1;
6841 cancel_delayed_work(&h->monitor_ctlr_work);
6842 spin_unlock_irqrestore(&h->lock, flags);
6843
edd16368
SC		 6844 hpsa_unregister_scsi(h); /* unhook from SCSI subsystem */
6845 hpsa_shutdown(pdev);
6846 iounmap(h->vaddr);
204892e9
SC		 6847 iounmap(h->transtable);
6848 iounmap(h->cfgtable);
55e14e76 6849 hpsa_free_device_info(h);
33a2ffce 6850 hpsa_free_sg_chain_blocks(h);
edd16368
SC		 6851 pci_free_consistent(h->pdev,
6852 h->nr_cmds * sizeof(struct CommandList),
6853 h->cmd_pool, h->cmd_pool_dhandle);
6854 pci_free_consistent(h->pdev,
6855 h->nr_cmds * sizeof(struct ErrorInfo),
6856 h->errinfo_pool, h->errinfo_pool_dhandle);
072b0518 6857 hpsa_free_reply_queues(h);
edd16368 6858 kfree(h->cmd_pool_bits);
303932fd 6859 kfree(h->blockFetchTable);
e1f7de0c 6860 kfree(h->ioaccel1_blockFetchTable);
aca9012a 6861 kfree(h->ioaccel2_blockFetchTable);
339b2b14 6862 kfree(h->hba_inquiry_data);
f0bd0b68 6863 pci_disable_device(pdev);
edd16368 6864 pci_release_regions(pdev);
094963da 6865 free_percpu(h->lockup_detected);
edd16368
SC		 6866 kfree(h);
6867}
6868
6869static int hpsa_suspend(__attribute__((unused)) struct pci_dev *pdev,
6870 __attribute__((unused)) pm_message_t state)
6871{
6872 return -ENOSYS;
6873}
6874
6875static int hpsa_resume(__attribute__((unused)) struct pci_dev *pdev)
6876{
6877 return -ENOSYS;
6878}
6879
6880static struct pci_driver hpsa_pci_driver = {
f79cfec6 6881 .name = HPSA,
edd16368 6882 .probe = hpsa_init_one,
6f039790 6883 .remove = hpsa_remove_one,
edd16368
SC		 6884 .id_table = hpsa_pci_device_id, /* id_table */
6885 .shutdown = hpsa_shutdown,
6886 .suspend = hpsa_suspend,
6887 .resume = hpsa_resume,
6888};
6889
303932fd
DB		 6890/* Fill in bucket_map[], given nsgs (the max number of
6891 * scatter gather elements supported) and bucket[],
6892 * which is an array of 8 integers. The bucket[] array
6893 * contains 8 different DMA transfer sizes (in 16
6894 * byte increments) which the controller uses to fetch
6895 * commands. This function fills in bucket_map[], which
6896 * maps a given number of scatter gather elements to one of
6897 * the 8 DMA transfer sizes. The point of it is to allow the
6898 * controller to only do as much DMA as needed to fetch the
6899 * command, with the DMA transfer size encoded in the lower
6900 * bits of the command address.
6901 */
6902static void calc_bucket_map(int bucket[], int num_buckets,
2b08b3e9 6903 int nsgs, int min_blocks, u32 *bucket_map)
303932fd
DB		 6904{
6905 int i, j, b, size;
6906
303932fd
DB		 6907 /* Note, bucket_map must have nsgs+1 entries. */
6908 for (i = 0; i <= nsgs; i++) {
6909 /* Compute size of a command with i SG entries */
e1f7de0c 6910 size = i + min_blocks;
303932fd
DB		 6911 b = num_buckets; /* Assume the biggest bucket */
6912 /* Find the bucket that is just big enough */
e1f7de0c 6913 for (j = 0; j < num_buckets; j++) {
303932fd
DB		 6914 if (bucket[j] >= size) {
6915 b = j;
6916 break;
6917 }
6918 }
6919 /* for a command with i SG entries, use bucket b. */
6920 bucket_map[i] = b;
6921 }
6922}
6923
e1f7de0c 6924static void hpsa_enter_performant_mode(struct ctlr_info *h, u32 trans_support)
303932fd 6925{
6c311b57
SC		 6926 int i;
6927 unsigned long register_value;
e1f7de0c
MG		 6928 unsigned long transMethod = CFGTBL_Trans_Performant |
6929 (trans_support & CFGTBL_Trans_use_short_tags) |
b9af4937
SC		 6930 CFGTBL_Trans_enable_directed_msix |
6931 (trans_support & (CFGTBL_Trans_io_accel1 |
6932 CFGTBL_Trans_io_accel2));
e1f7de0c 6933 struct access_method access = SA5_performant_access;
def342bd
SC		 6934
6935 /* This is a bit complicated. There are 8 registers on
6936 * the controller which we write to to tell it 8 different
6937 * sizes of commands which there may be. It's a way of
6938 * reducing the DMA done to fetch each command. Encoded into
6939 * each command's tag are 3 bits which communicate to the controller
6940 * which of the eight sizes that command fits within. The size of
6941 * each command depends on how many scatter gather entries there are.
6942 * Each SG entry requires 16 bytes. The eight registers are programmed
6943 * with the number of 16-byte blocks a command of that size requires.
6944 * The smallest command possible requires 5 such 16 byte blocks.
d66ae08b 6945 * the largest command possible requires SG_ENTRIES_IN_CMD + 4 16-byte
def342bd
SC		 6946 * blocks. Note, this only extends to the SG entries contained
6947 * within the command block, and does not extend to chained blocks
6948 * of SG elements. bft[] contains the eight values we write to
6949 * the registers. They are not evenly distributed, but have more
6950 * sizes for small commands, and fewer sizes for larger commands.
6951 */
d66ae08b 6952 int bft[8] = {5, 6, 8, 10, 12, 20, 28, SG_ENTRIES_IN_CMD + 4};
b9af4937
SC		 6953#define MIN_IOACCEL2_BFT_ENTRY 5
6954#define HPSA_IOACCEL2_HEADER_SZ 4
6955 int bft2[16] = {MIN_IOACCEL2_BFT_ENTRY, 6, 7, 8, 9, 10, 11, 12,
6956 13, 14, 15, 16, 17, 18, 19,
6957 HPSA_IOACCEL2_HEADER_SZ + IOACCEL2_MAXSGENTRIES};
6958 BUILD_BUG_ON(ARRAY_SIZE(bft2) != 16);
6959 BUILD_BUG_ON(ARRAY_SIZE(bft) != 8);
6960 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) >
6961 16 * MIN_IOACCEL2_BFT_ENTRY);
6962 BUILD_BUG_ON(sizeof(struct ioaccel2_sg_element) != 16);
d66ae08b 6963 BUILD_BUG_ON(28 > SG_ENTRIES_IN_CMD + 4);
303932fd
DB		 6964 /* 5 = 1 s/g entry or 4k
6965 * 6 = 2 s/g entry or 8k
6966 * 8 = 4 s/g entry or 16k
6967 * 10 = 6 s/g entry or 24k
6968 */
303932fd 6969
b3a52e79
SC		 6970 /* If the controller supports either ioaccel method then
6971 * we can also use the RAID stack submit path that does not
6972 * perform the superfluous readl() after each command submission.
6973 */
6974 if (trans_support & (CFGTBL_Trans_io_accel1 | CFGTBL_Trans_io_accel2))
6975 access = SA5_performant_access_no_read;
6976
303932fd 6977 /* Controller spec: zero out this buffer. */
072b0518
SC		 6978 for (i = 0; i < h->nreply_queues; i++)
6979 memset(h->reply_queue[i].head, 0, h->reply_queue_size);
303932fd 6980
d66ae08b
SC		 6981 bft[7] = SG_ENTRIES_IN_CMD + 4;
6982 calc_bucket_map(bft, ARRAY_SIZE(bft),
e1f7de0c 6983 SG_ENTRIES_IN_CMD, 4, h->blockFetchTable);
303932fd
DB		 6984 for (i = 0; i < 8; i++)
6985 writel(bft[i], &h->transtable->BlockFetch[i]);
6986
6987 /* size of controller ring buffer */
6988 writel(h->max_commands, &h->transtable->RepQSize);
254f796b 6989 writel(h->nreply_queues, &h->transtable->RepQCount);
303932fd
DB		 6990 writel(0, &h->transtable->RepQCtrAddrLow32);
6991 writel(0, &h->transtable->RepQCtrAddrHigh32);
254f796b
MG		 6992
6993 for (i = 0; i < h->nreply_queues; i++) {
6994 writel(0, &h->transtable->RepQAddr[i].upper);
072b0518 6995 writel(h->reply_queue[i].busaddr,
254f796b
MG		 6996 &h->transtable->RepQAddr[i].lower);
6997 }
6998
b9af4937 6999 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
e1f7de0c
MG		 7000 writel(transMethod, &(h->cfgtable->HostWrite.TransportRequest));
7001 /*
7002 * enable outbound interrupt coalescing in accelerator mode;
7003 */
7004 if (trans_support & CFGTBL_Trans_io_accel1) {
7005 access = SA5_ioaccel_mode1_access;
7006 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
7007 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
c349775e
ST		 7008 } else {
7009 if (trans_support & CFGTBL_Trans_io_accel2) {
7010 access = SA5_ioaccel_mode2_access;
7011 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
7012 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
7013 }
e1f7de0c 7014 }
303932fd 7015 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
3f4336f3 7016 hpsa_wait_for_mode_change_ack(h);
303932fd
DB		 7017 register_value = readl(&(h->cfgtable->TransportActive));
7018 if (!(register_value & CFGTBL_Trans_Performant)) {
050f7147
SC		 7019 dev_err(&h->pdev->dev,
7020 "performant mode problem - transport not active\n");
303932fd
DB		 7021 return;
7022 }
960a30e7 7023 /* Change the access methods to the performant access methods */
e1f7de0c
MG		 7024 h->access = access;
7025 h->transMethod = transMethod;
7026
b9af4937
SC		 7027 if (!((trans_support & CFGTBL_Trans_io_accel1) ||
7028 (trans_support & CFGTBL_Trans_io_accel2)))
e1f7de0c
MG		 7029 return;
7030
b9af4937
SC		 7031 if (trans_support & CFGTBL_Trans_io_accel1) {
7032 /* Set up I/O accelerator mode */
7033 for (i = 0; i < h->nreply_queues; i++) {
7034 writel(i, h->vaddr + IOACCEL_MODE1_REPLY_QUEUE_INDEX);
7035 h->reply_queue[i].current_entry =
7036 readl(h->vaddr + IOACCEL_MODE1_PRODUCER_INDEX);
7037 }
7038 bft[7] = h->ioaccel_maxsg + 8;
7039 calc_bucket_map(bft, ARRAY_SIZE(bft), h->ioaccel_maxsg, 8,
7040 h->ioaccel1_blockFetchTable);
e1f7de0c 7041
b9af4937 7042 /* initialize all reply queue entries to unused */
072b0518
SC		 7043 for (i = 0; i < h->nreply_queues; i++)
7044 memset(h->reply_queue[i].head,
7045 (u8) IOACCEL_MODE1_REPLY_UNUSED,
7046 h->reply_queue_size);
e1f7de0c 7047
b9af4937
SC		 7048 /* set all the constant fields in the accelerator command
7049 * frames once at init time to save CPU cycles later.
7050 */
7051 for (i = 0; i < h->nr_cmds; i++) {
7052 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[i];
7053
7054 cp->function = IOACCEL1_FUNCTION_SCSIIO;
7055 cp->err_info = (u32) (h->errinfo_pool_dhandle +
7056 (i * sizeof(struct ErrorInfo)));
7057 cp->err_info_len = sizeof(struct ErrorInfo);
7058 cp->sgl_offset = IOACCEL1_SGLOFFSET;
2b08b3e9
DB		 7059 cp->host_context_flags =
7060 cpu_to_le16(IOACCEL1_HCFLAGS_CISS_FORMAT);
b9af4937
SC		 7061 cp->timeout_sec = 0;
7062 cp->ReplyQueue = 0;
50a0decf 7063 cp->tag =
f2405db8 7064 cpu_to_le64((i << DIRECT_LOOKUP_SHIFT));
50a0decf
SC		 7065 cp->host_addr =
7066 cpu_to_le64(h->ioaccel_cmd_pool_dhandle +
b9af4937 7067 (i * sizeof(struct io_accel1_cmd)));
b9af4937
SC		 7068 }
7069 } else if (trans_support & CFGTBL_Trans_io_accel2) {
7070 u64 cfg_offset, cfg_base_addr_index;
7071 u32 bft2_offset, cfg_base_addr;
7072 int rc;
7073
7074 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
7075 &cfg_base_addr_index, &cfg_offset);
7076 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) != 64);
7077 bft2[15] = h->ioaccel_maxsg + HPSA_IOACCEL2_HEADER_SZ;
7078 calc_bucket_map(bft2, ARRAY_SIZE(bft2), h->ioaccel_maxsg,
7079 4, h->ioaccel2_blockFetchTable);
7080 bft2_offset = readl(&h->cfgtable->io_accel_request_size_offset);
7081 BUILD_BUG_ON(offsetof(struct CfgTable,
7082 io_accel_request_size_offset) != 0xb8);
7083 h->ioaccel2_bft2_regs =
7084 remap_pci_mem(pci_resource_start(h->pdev,
7085 cfg_base_addr_index) +
7086 cfg_offset + bft2_offset,
7087 ARRAY_SIZE(bft2) *
7088 sizeof(*h->ioaccel2_bft2_regs));
7089 for (i = 0; i < ARRAY_SIZE(bft2); i++)
7090 writel(bft2[i], &h->ioaccel2_bft2_regs[i]);
e1f7de0c 7091 }
b9af4937
SC		 7092 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
7093 hpsa_wait_for_mode_change_ack(h);
e1f7de0c
MG		 7094}
7095
7096static int hpsa_alloc_ioaccel_cmd_and_bft(struct ctlr_info *h)
7097{
283b4a9b
SC		 7098 h->ioaccel_maxsg =
7099 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
7100 if (h->ioaccel_maxsg > IOACCEL1_MAXSGENTRIES)
7101 h->ioaccel_maxsg = IOACCEL1_MAXSGENTRIES;
7102
e1f7de0c
MG		 7103 /* Command structures must be aligned on a 128-byte boundary
7104 * because the 7 lower bits of the address are used by the
7105 * hardware.
7106 */
e1f7de0c
MG		 7107 BUILD_BUG_ON(sizeof(struct io_accel1_cmd) %
7108 IOACCEL1_COMMANDLIST_ALIGNMENT);
7109 h->ioaccel_cmd_pool =
7110 pci_alloc_consistent(h->pdev,
7111 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
7112 &(h->ioaccel_cmd_pool_dhandle));
7113
7114 h->ioaccel1_blockFetchTable =
283b4a9b 7115 kmalloc(((h->ioaccel_maxsg + 1) *
e1f7de0c
MG		 7116 sizeof(u32)), GFP_KERNEL);
7117
7118 if ((h->ioaccel_cmd_pool == NULL) ||
7119 (h->ioaccel1_blockFetchTable == NULL))
7120 goto clean_up;
7121
7122 memset(h->ioaccel_cmd_pool, 0,
7123 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool));
7124 return 0;
7125
7126clean_up:
7127 if (h->ioaccel_cmd_pool)
7128 pci_free_consistent(h->pdev,
7129 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
7130 h->ioaccel_cmd_pool, h->ioaccel_cmd_pool_dhandle);
7131 kfree(h->ioaccel1_blockFetchTable);
7132 return 1;
6c311b57
SC		 7133}
7134
aca9012a
SC		 7135static int ioaccel2_alloc_cmds_and_bft(struct ctlr_info *h)
7136{
7137 /* Allocate ioaccel2 mode command blocks and block fetch table */
7138
7139 h->ioaccel_maxsg =
7140 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
7141 if (h->ioaccel_maxsg > IOACCEL2_MAXSGENTRIES)
7142 h->ioaccel_maxsg = IOACCEL2_MAXSGENTRIES;
7143
aca9012a
SC		 7144 BUILD_BUG_ON(sizeof(struct io_accel2_cmd) %
7145 IOACCEL2_COMMANDLIST_ALIGNMENT);
7146 h->ioaccel2_cmd_pool =
7147 pci_alloc_consistent(h->pdev,
7148 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
7149 &(h->ioaccel2_cmd_pool_dhandle));
7150
7151 h->ioaccel2_blockFetchTable =
7152 kmalloc(((h->ioaccel_maxsg + 1) *
7153 sizeof(u32)), GFP_KERNEL);
7154
7155 if ((h->ioaccel2_cmd_pool == NULL) ||
7156 (h->ioaccel2_blockFetchTable == NULL))
7157 goto clean_up;
7158
7159 memset(h->ioaccel2_cmd_pool, 0,
7160 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool));
7161 return 0;
7162
7163clean_up:
7164 if (h->ioaccel2_cmd_pool)
7165 pci_free_consistent(h->pdev,
7166 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
7167 h->ioaccel2_cmd_pool, h->ioaccel2_cmd_pool_dhandle);
7168 kfree(h->ioaccel2_blockFetchTable);
7169 return 1;
7170}
7171
6f039790 7172static void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h)
6c311b57
SC		 7173{
7174 u32 trans_support;
e1f7de0c
MG		 7175 unsigned long transMethod = CFGTBL_Trans_Performant |
7176 CFGTBL_Trans_use_short_tags;
254f796b 7177 int i;
6c311b57 7178
02ec19c8
SC		 7179 if (hpsa_simple_mode)
7180 return;
7181
67c99a72 7182 trans_support = readl(&(h->cfgtable->TransportSupport));
7183 if (!(trans_support & PERFORMANT_MODE))
7184 return;
7185
e1f7de0c
MG		 7186 /* Check for I/O accelerator mode support */
7187 if (trans_support & CFGTBL_Trans_io_accel1) {
7188 transMethod |= CFGTBL_Trans_io_accel1 |
7189 CFGTBL_Trans_enable_directed_msix;
7190 if (hpsa_alloc_ioaccel_cmd_and_bft(h))
7191 goto clean_up;
aca9012a
SC		 7192 } else {
7193 if (trans_support & CFGTBL_Trans_io_accel2) {
7194 transMethod |= CFGTBL_Trans_io_accel2 |
7195 CFGTBL_Trans_enable_directed_msix;
7196 if (ioaccel2_alloc_cmds_and_bft(h))
7197 goto clean_up;
7198 }
e1f7de0c
MG		 7199 }
7200
eee0f03a 7201 h->nreply_queues = h->msix_vector > 0 ? h->msix_vector : 1;
cba3d38b 7202 hpsa_get_max_perf_mode_cmds(h);
6c311b57 7203 /* Performant mode ring buffer and supporting data structures */
072b0518 7204 h->reply_queue_size = h->max_commands * sizeof(u64);
6c311b57 7205
254f796b 7206 for (i = 0; i < h->nreply_queues; i++) {
072b0518
SC		 7207 h->reply_queue[i].head = pci_alloc_consistent(h->pdev,
7208 h->reply_queue_size,
7209 &(h->reply_queue[i].busaddr));
7210 if (!h->reply_queue[i].head)
7211 goto clean_up;
254f796b
MG		 7212 h->reply_queue[i].size = h->max_commands;
7213 h->reply_queue[i].wraparound = 1; /* spec: init to 1 */
7214 h->reply_queue[i].current_entry = 0;
7215 }
7216
6c311b57 7217 /* Need a block fetch table for performant mode */
d66ae08b 7218 h->blockFetchTable = kmalloc(((SG_ENTRIES_IN_CMD + 1) *
6c311b57 7219 sizeof(u32)), GFP_KERNEL);
072b0518 7220 if (!h->blockFetchTable)
6c311b57
SC		 7221 goto clean_up;
7222
e1f7de0c 7223 hpsa_enter_performant_mode(h, trans_support);
303932fd
DB		 7224 return;
7225
7226clean_up:
072b0518 7227 hpsa_free_reply_queues(h);
303932fd
DB		 7228 kfree(h->blockFetchTable);
7229}
7230
23100dd9 7231static int is_accelerated_cmd(struct CommandList *c)
76438d08 7232{
23100dd9
SC		 7233 return c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_IOACCEL2;
7234}
7235
7236static void hpsa_drain_accel_commands(struct ctlr_info *h)
7237{
7238 struct CommandList *c = NULL;
f2405db8 7239 int i, accel_cmds_out;
76438d08 7240
f2405db8 7241 do { /* wait for all outstanding ioaccel commands to drain out */
23100dd9 7242 accel_cmds_out = 0;
f2405db8
DB		 7243 for (i = 0; i < h->nr_cmds; i++) {
7244 if (!test_bit(i & (BITS_PER_LONG - 1),
7245 h->cmd_pool_bits + (i / BITS_PER_LONG)))
7246 continue;
7247 c = h->cmd_pool + i;
23100dd9 7248 accel_cmds_out += is_accelerated_cmd(c);
f2405db8 7249 }
23100dd9 7250 if (accel_cmds_out <= 0)
f2405db8 7251 break;
76438d08
SC		 7252 msleep(100);
7253 } while (1);
7254}
7255
edd16368
SC		 7256/*
7257 * This is it. Register the PCI driver information for the cards we control
7258 * the OS will call our registered routines when it finds one of our cards.
7259 */
7260static int __init hpsa_init(void)
7261{
31468401 7262 return pci_register_driver(&hpsa_pci_driver);
edd16368
SC		 7263}
7264
7265static void __exit hpsa_cleanup(void)
7266{
7267 pci_unregister_driver(&hpsa_pci_driver);
edd16368
SC		 7268}
7269
e1f7de0c
MG		 7270static void __attribute__((unused)) verify_offsets(void)
7271{
dd0e19f3
ST		 7272#define VERIFY_OFFSET(member, offset) \
7273 BUILD_BUG_ON(offsetof(struct raid_map_data, member) != offset)
7274
7275 VERIFY_OFFSET(structure_size, 0);
7276 VERIFY_OFFSET(volume_blk_size, 4);
7277 VERIFY_OFFSET(volume_blk_cnt, 8);
7278 VERIFY_OFFSET(phys_blk_shift, 16);
7279 VERIFY_OFFSET(parity_rotation_shift, 17);
7280 VERIFY_OFFSET(strip_size, 18);
7281 VERIFY_OFFSET(disk_starting_blk, 20);
7282 VERIFY_OFFSET(disk_blk_cnt, 28);
7283 VERIFY_OFFSET(data_disks_per_row, 36);
7284 VERIFY_OFFSET(metadata_disks_per_row, 38);
7285 VERIFY_OFFSET(row_cnt, 40);
7286 VERIFY_OFFSET(layout_map_count, 42);
7287 VERIFY_OFFSET(flags, 44);
7288 VERIFY_OFFSET(dekindex, 46);
7289 /* VERIFY_OFFSET(reserved, 48 */
7290 VERIFY_OFFSET(data, 64);
7291
7292#undef VERIFY_OFFSET
7293
b66cc250
MM		 7294#define VERIFY_OFFSET(member, offset) \
7295 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, member) != offset)
7296
7297 VERIFY_OFFSET(IU_type, 0);
7298 VERIFY_OFFSET(direction, 1);
7299 VERIFY_OFFSET(reply_queue, 2);
7300 /* VERIFY_OFFSET(reserved1, 3); */
7301 VERIFY_OFFSET(scsi_nexus, 4);
7302 VERIFY_OFFSET(Tag, 8);
7303 VERIFY_OFFSET(cdb, 16);
7304 VERIFY_OFFSET(cciss_lun, 32);
7305 VERIFY_OFFSET(data_len, 40);
7306 VERIFY_OFFSET(cmd_priority_task_attr, 44);
7307 VERIFY_OFFSET(sg_count, 45);
7308 /* VERIFY_OFFSET(reserved3 */
7309 VERIFY_OFFSET(err_ptr, 48);
7310 VERIFY_OFFSET(err_len, 56);
7311 /* VERIFY_OFFSET(reserved4 */
7312 VERIFY_OFFSET(sg, 64);
7313
7314#undef VERIFY_OFFSET
7315
e1f7de0c
MG		 7316#define VERIFY_OFFSET(member, offset) \
7317 BUILD_BUG_ON(offsetof(struct io_accel1_cmd, member) != offset)
7318
7319 VERIFY_OFFSET(dev_handle, 0x00);
7320 VERIFY_OFFSET(reserved1, 0x02);
7321 VERIFY_OFFSET(function, 0x03);
7322 VERIFY_OFFSET(reserved2, 0x04);
7323 VERIFY_OFFSET(err_info, 0x0C);
7324 VERIFY_OFFSET(reserved3, 0x10);
7325 VERIFY_OFFSET(err_info_len, 0x12);
7326 VERIFY_OFFSET(reserved4, 0x13);
7327 VERIFY_OFFSET(sgl_offset, 0x14);
7328 VERIFY_OFFSET(reserved5, 0x15);
7329 VERIFY_OFFSET(transfer_len, 0x1C);
7330 VERIFY_OFFSET(reserved6, 0x20);
7331 VERIFY_OFFSET(io_flags, 0x24);
7332 VERIFY_OFFSET(reserved7, 0x26);
7333 VERIFY_OFFSET(LUN, 0x34);
7334 VERIFY_OFFSET(control, 0x3C);
7335 VERIFY_OFFSET(CDB, 0x40);
7336 VERIFY_OFFSET(reserved8, 0x50);
7337 VERIFY_OFFSET(host_context_flags, 0x60);
7338 VERIFY_OFFSET(timeout_sec, 0x62);
7339 VERIFY_OFFSET(ReplyQueue, 0x64);
7340 VERIFY_OFFSET(reserved9, 0x65);
50a0decf 7341 VERIFY_OFFSET(tag, 0x68);
e1f7de0c
MG		 7342 VERIFY_OFFSET(host_addr, 0x70);
7343 VERIFY_OFFSET(CISS_LUN, 0x78);
7344 VERIFY_OFFSET(SG, 0x78 + 8);
7345#undef VERIFY_OFFSET
7346}
7347
edd16368
SC		 7348module_init(hpsa_init);
7349module_exit(hpsa_cleanup);
Linux kernel - Deliverables
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