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edd16368 SC |
1 | /* |
2 | * Disk Array driver for HP Smart Array SAS controllers | |
3 | * Copyright 2000, 2009 Hewlett-Packard Development Company, L.P. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; version 2 of the License. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
12 | * NON INFRINGEMENT. See the GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
17 | * | |
18 | * Questions/Comments/Bugfixes to iss_storagedev@hp.com | |
19 | * | |
20 | */ | |
21 | #ifndef HPSA_CMD_H | |
22 | #define HPSA_CMD_H | |
23 | ||
24 | /* general boundary defintions */ | |
25 | #define SENSEINFOBYTES 32 /* may vary between hbas */ | |
d66ae08b | 26 | #define SG_ENTRIES_IN_CMD 32 /* Max SG entries excluding chain blocks */ |
33a2ffce | 27 | #define HPSA_SG_CHAIN 0x80000000 |
edd16368 SC |
28 | #define MAXREPLYQS 256 |
29 | ||
30 | /* Command Status value */ | |
31 | #define CMD_SUCCESS 0x0000 | |
32 | #define CMD_TARGET_STATUS 0x0001 | |
33 | #define CMD_DATA_UNDERRUN 0x0002 | |
34 | #define CMD_DATA_OVERRUN 0x0003 | |
35 | #define CMD_INVALID 0x0004 | |
36 | #define CMD_PROTOCOL_ERR 0x0005 | |
37 | #define CMD_HARDWARE_ERR 0x0006 | |
38 | #define CMD_CONNECTION_LOST 0x0007 | |
39 | #define CMD_ABORTED 0x0008 | |
40 | #define CMD_ABORT_FAILED 0x0009 | |
41 | #define CMD_UNSOLICITED_ABORT 0x000A | |
42 | #define CMD_TIMEOUT 0x000B | |
43 | #define CMD_UNABORTABLE 0x000C | |
44 | ||
45 | /* Unit Attentions ASC's as defined for the MSA2012sa */ | |
46 | #define POWER_OR_RESET 0x29 | |
47 | #define STATE_CHANGED 0x2a | |
48 | #define UNIT_ATTENTION_CLEARED 0x2f | |
49 | #define LUN_FAILED 0x3e | |
50 | #define REPORT_LUNS_CHANGED 0x3f | |
51 | ||
52 | /* Unit Attentions ASCQ's as defined for the MSA2012sa */ | |
53 | ||
54 | /* These ASCQ's defined for ASC = POWER_OR_RESET */ | |
55 | #define POWER_ON_RESET 0x00 | |
56 | #define POWER_ON_REBOOT 0x01 | |
57 | #define SCSI_BUS_RESET 0x02 | |
58 | #define MSA_TARGET_RESET 0x03 | |
59 | #define CONTROLLER_FAILOVER 0x04 | |
60 | #define TRANSCEIVER_SE 0x05 | |
61 | #define TRANSCEIVER_LVD 0x06 | |
62 | ||
63 | /* These ASCQ's defined for ASC = STATE_CHANGED */ | |
64 | #define RESERVATION_PREEMPTED 0x03 | |
65 | #define ASYM_ACCESS_CHANGED 0x06 | |
66 | #define LUN_CAPACITY_CHANGED 0x09 | |
67 | ||
68 | /* transfer direction */ | |
69 | #define XFER_NONE 0x00 | |
70 | #define XFER_WRITE 0x01 | |
71 | #define XFER_READ 0x02 | |
72 | #define XFER_RSVD 0x03 | |
73 | ||
74 | /* task attribute */ | |
75 | #define ATTR_UNTAGGED 0x00 | |
76 | #define ATTR_SIMPLE 0x04 | |
77 | #define ATTR_HEADOFQUEUE 0x05 | |
78 | #define ATTR_ORDERED 0x06 | |
79 | #define ATTR_ACA 0x07 | |
80 | ||
81 | /* cdb type */ | |
82 | #define TYPE_CMD 0x00 | |
83 | #define TYPE_MSG 0x01 | |
84 | ||
85 | /* config space register offsets */ | |
86 | #define CFG_VENDORID 0x00 | |
87 | #define CFG_DEVICEID 0x02 | |
88 | #define CFG_I2OBAR 0x10 | |
89 | #define CFG_MEM1BAR 0x14 | |
90 | ||
91 | /* i2o space register offsets */ | |
92 | #define I2O_IBDB_SET 0x20 | |
93 | #define I2O_IBDB_CLEAR 0x70 | |
94 | #define I2O_INT_STATUS 0x30 | |
95 | #define I2O_INT_MASK 0x34 | |
96 | #define I2O_IBPOST_Q 0x40 | |
97 | #define I2O_OBPOST_Q 0x44 | |
98 | #define I2O_DMA1_CFG 0x214 | |
99 | ||
100 | /* Configuration Table */ | |
101 | #define CFGTBL_ChangeReq 0x00000001l | |
102 | #define CFGTBL_AccCmds 0x00000001l | |
1df8552a | 103 | #define DOORBELL_CTLR_RESET 0x00000004l |
cf0b08d0 | 104 | #define DOORBELL_CTLR_RESET2 0x00000020l |
edd16368 SC |
105 | |
106 | #define CFGTBL_Trans_Simple 0x00000002l | |
303932fd | 107 | #define CFGTBL_Trans_Performant 0x00000004l |
960a30e7 | 108 | #define CFGTBL_Trans_use_short_tags 0x20000000l |
edd16368 SC |
109 | |
110 | #define CFGTBL_BusType_Ultra2 0x00000001l | |
111 | #define CFGTBL_BusType_Ultra3 0x00000002l | |
112 | #define CFGTBL_BusType_Fibre1G 0x00000100l | |
113 | #define CFGTBL_BusType_Fibre2G 0x00000200l | |
114 | struct vals32 { | |
01a02ffc SC |
115 | u32 lower; |
116 | u32 upper; | |
edd16368 SC |
117 | }; |
118 | ||
119 | union u64bit { | |
120 | struct vals32 val32; | |
01a02ffc | 121 | u64 val; |
edd16368 SC |
122 | }; |
123 | ||
124 | /* FIXME this is a per controller value (barf!) */ | |
b7ec021f | 125 | #define HPSA_MAX_LUN 1024 |
edd16368 | 126 | #define HPSA_MAX_PHYS_LUN 1024 |
aca4a520 | 127 | #define MAX_EXT_TARGETS 32 |
b7ec021f | 128 | #define HPSA_MAX_DEVICES (HPSA_MAX_PHYS_LUN + HPSA_MAX_LUN + \ |
aca4a520 | 129 | MAX_EXT_TARGETS + 1) /* + 1 is for the controller itself */ |
edd16368 SC |
130 | |
131 | /* SCSI-3 Commands */ | |
132 | #pragma pack(1) | |
133 | ||
134 | #define HPSA_INQUIRY 0x12 | |
135 | struct InquiryData { | |
01a02ffc | 136 | u8 data_byte[36]; |
edd16368 SC |
137 | }; |
138 | ||
139 | #define HPSA_REPORT_LOG 0xc2 /* Report Logical LUNs */ | |
140 | #define HPSA_REPORT_PHYS 0xc3 /* Report Physical LUNs */ | |
141 | struct ReportLUNdata { | |
01a02ffc SC |
142 | u8 LUNListLength[4]; |
143 | u32 reserved; | |
144 | u8 LUN[HPSA_MAX_LUN][8]; | |
edd16368 SC |
145 | }; |
146 | ||
147 | struct ReportExtendedLUNdata { | |
01a02ffc SC |
148 | u8 LUNListLength[4]; |
149 | u8 extended_response_flag; | |
150 | u8 reserved[3]; | |
151 | u8 LUN[HPSA_MAX_LUN][24]; | |
edd16368 SC |
152 | }; |
153 | ||
154 | struct SenseSubsystem_info { | |
01a02ffc SC |
155 | u8 reserved[36]; |
156 | u8 portname[8]; | |
157 | u8 reserved1[1108]; | |
edd16368 SC |
158 | }; |
159 | ||
edd16368 SC |
160 | /* BMIC commands */ |
161 | #define BMIC_READ 0x26 | |
162 | #define BMIC_WRITE 0x27 | |
163 | #define BMIC_CACHE_FLUSH 0xc2 | |
164 | #define HPSA_CACHE_FLUSH 0x01 /* C2 was already being used by HPSA */ | |
165 | ||
166 | /* Command List Structure */ | |
167 | union SCSI3Addr { | |
168 | struct { | |
01a02ffc SC |
169 | u8 Dev; |
170 | u8 Bus:6; | |
171 | u8 Mode:2; /* b00 */ | |
edd16368 SC |
172 | } PeripDev; |
173 | struct { | |
01a02ffc SC |
174 | u8 DevLSB; |
175 | u8 DevMSB:6; | |
176 | u8 Mode:2; /* b01 */ | |
edd16368 SC |
177 | } LogDev; |
178 | struct { | |
01a02ffc SC |
179 | u8 Dev:5; |
180 | u8 Bus:3; | |
181 | u8 Targ:6; | |
182 | u8 Mode:2; /* b10 */ | |
edd16368 SC |
183 | } LogUnit; |
184 | }; | |
185 | ||
186 | struct PhysDevAddr { | |
01a02ffc SC |
187 | u32 TargetId:24; |
188 | u32 Bus:6; | |
189 | u32 Mode:2; | |
edd16368 SC |
190 | /* 2 level target device addr */ |
191 | union SCSI3Addr Target[2]; | |
192 | }; | |
193 | ||
194 | struct LogDevAddr { | |
01a02ffc SC |
195 | u32 VolId:30; |
196 | u32 Mode:2; | |
197 | u8 reserved[4]; | |
edd16368 SC |
198 | }; |
199 | ||
200 | union LUNAddr { | |
01a02ffc | 201 | u8 LunAddrBytes[8]; |
edd16368 SC |
202 | union SCSI3Addr SCSI3Lun[4]; |
203 | struct PhysDevAddr PhysDev; | |
204 | struct LogDevAddr LogDev; | |
205 | }; | |
206 | ||
207 | struct CommandListHeader { | |
01a02ffc SC |
208 | u8 ReplyQueue; |
209 | u8 SGList; | |
210 | u16 SGTotal; | |
edd16368 SC |
211 | struct vals32 Tag; |
212 | union LUNAddr LUN; | |
213 | }; | |
214 | ||
215 | struct RequestBlock { | |
01a02ffc | 216 | u8 CDBLen; |
edd16368 | 217 | struct { |
01a02ffc SC |
218 | u8 Type:3; |
219 | u8 Attribute:3; | |
220 | u8 Direction:2; | |
edd16368 | 221 | } Type; |
01a02ffc SC |
222 | u16 Timeout; |
223 | u8 CDB[16]; | |
edd16368 SC |
224 | }; |
225 | ||
226 | struct ErrDescriptor { | |
227 | struct vals32 Addr; | |
01a02ffc | 228 | u32 Len; |
edd16368 SC |
229 | }; |
230 | ||
231 | struct SGDescriptor { | |
232 | struct vals32 Addr; | |
01a02ffc SC |
233 | u32 Len; |
234 | u32 Ext; | |
edd16368 SC |
235 | }; |
236 | ||
237 | union MoreErrInfo { | |
238 | struct { | |
01a02ffc SC |
239 | u8 Reserved[3]; |
240 | u8 Type; | |
241 | u32 ErrorInfo; | |
edd16368 SC |
242 | } Common_Info; |
243 | struct { | |
01a02ffc SC |
244 | u8 Reserved[2]; |
245 | u8 offense_size; /* size of offending entry */ | |
246 | u8 offense_num; /* byte # of offense 0-base */ | |
247 | u32 offense_value; | |
edd16368 SC |
248 | } Invalid_Cmd; |
249 | }; | |
250 | struct ErrorInfo { | |
01a02ffc SC |
251 | u8 ScsiStatus; |
252 | u8 SenseLen; | |
253 | u16 CommandStatus; | |
254 | u32 ResidualCnt; | |
edd16368 | 255 | union MoreErrInfo MoreErrInfo; |
01a02ffc | 256 | u8 SenseInfo[SENSEINFOBYTES]; |
edd16368 SC |
257 | }; |
258 | /* Command types */ | |
259 | #define CMD_IOCTL_PEND 0x01 | |
260 | #define CMD_SCSI 0x03 | |
261 | ||
303932fd DB |
262 | #define DIRECT_LOOKUP_SHIFT 5 |
263 | #define DIRECT_LOOKUP_BIT 0x10 | |
d896f3f3 | 264 | #define DIRECT_LOOKUP_MASK (~((1 << DIRECT_LOOKUP_SHIFT) - 1)) |
303932fd DB |
265 | |
266 | #define HPSA_ERROR_BIT 0x02 | |
edd16368 | 267 | struct ctlr_info; /* defined in hpsa.h */ |
303932fd DB |
268 | /* The size of this structure needs to be divisible by 32 |
269 | * on all architectures because low 5 bits of the addresses | |
270 | * are used as follows: | |
271 | * | |
272 | * bit 0: to device, used to indicate "performant mode" command | |
273 | * from device, indidcates error status. | |
274 | * bit 1-3: to device, indicates block fetch table entry for | |
275 | * reducing DMA in fetching commands from host memory. | |
276 | * bit 4: used to indicate whether tag is "direct lookup" (index), | |
277 | * or a bus address. | |
edd16368 | 278 | */ |
303932fd | 279 | |
edd16368 SC |
280 | struct CommandList { |
281 | struct CommandListHeader Header; | |
282 | struct RequestBlock Request; | |
283 | struct ErrDescriptor ErrDesc; | |
d66ae08b | 284 | struct SGDescriptor SG[SG_ENTRIES_IN_CMD]; |
edd16368 | 285 | /* information associated with the command */ |
01a02ffc | 286 | u32 busaddr; /* physical addr of this record */ |
edd16368 SC |
287 | struct ErrorInfo *err_info; /* pointer to the allocated mem */ |
288 | struct ctlr_info *h; | |
289 | int cmd_type; | |
290 | long cmdindex; | |
9e0fc764 | 291 | struct list_head list; |
edd16368 SC |
292 | struct request *rq; |
293 | struct completion *waiting; | |
edd16368 | 294 | void *scsi_cmd; |
303932fd DB |
295 | |
296 | /* on 64 bit architectures, to get this to be 32-byte-aligned | |
db61bfcf SC |
297 | * it so happens we need PAD_64 bytes of padding, on 32 bit systems, |
298 | * we need PAD_32 bytes of padding (see below). This does that. | |
299 | * If it happens that 64 bit and 32 bit systems need different | |
300 | * padding, PAD_32 and PAD_64 can be set independently, and. | |
301 | * the code below will do the right thing. | |
303932fd | 302 | */ |
db61bfcf SC |
303 | #define IS_32_BIT ((8 - sizeof(long))/4) |
304 | #define IS_64_BIT (!IS_32_BIT) | |
43aebfa1 SC |
305 | #define PAD_32 (4) |
306 | #define PAD_64 (4) | |
db61bfcf | 307 | #define COMMANDLIST_PAD (IS_32_BIT * PAD_32 + IS_64_BIT * PAD_64) |
303932fd | 308 | u8 pad[COMMANDLIST_PAD]; |
edd16368 SC |
309 | }; |
310 | ||
311 | /* Configuration Table Structure */ | |
312 | struct HostWrite { | |
01a02ffc SC |
313 | u32 TransportRequest; |
314 | u32 Reserved; | |
315 | u32 CoalIntDelay; | |
316 | u32 CoalIntCount; | |
edd16368 SC |
317 | }; |
318 | ||
303932fd DB |
319 | #define SIMPLE_MODE 0x02 |
320 | #define PERFORMANT_MODE 0x04 | |
321 | #define MEMQ_MODE 0x08 | |
322 | ||
edd16368 | 323 | struct CfgTable { |
303932fd DB |
324 | u8 Signature[4]; |
325 | u32 SpecValence; | |
326 | u32 TransportSupport; | |
327 | u32 TransportActive; | |
328 | struct HostWrite HostWrite; | |
329 | u32 CmdsOutMax; | |
330 | u32 BusTypes; | |
331 | u32 TransMethodOffset; | |
332 | u8 ServerName[16]; | |
333 | u32 HeartBeat; | |
334 | u32 SCSI_Prefetch; | |
335 | u32 MaxScatterGatherElements; | |
336 | u32 MaxLogicalUnits; | |
337 | u32 MaxPhysicalDevices; | |
338 | u32 MaxPhysicalDrivesPerLogicalUnit; | |
339 | u32 MaxPerformantModeCommands; | |
1df8552a SC |
340 | u8 reserved[0x78 - 0x58]; |
341 | u32 misc_fw_support; /* offset 0x78 */ | |
342 | #define MISC_FW_DOORBELL_RESET (0x02) | |
cf0b08d0 | 343 | #define MISC_FW_DOORBELL_RESET2 (0x010) |
580ada3c | 344 | u8 driver_version[32]; |
303932fd DB |
345 | }; |
346 | ||
347 | #define NUM_BLOCKFETCH_ENTRIES 8 | |
348 | struct TransTable_struct { | |
349 | u32 BlockFetch[NUM_BLOCKFETCH_ENTRIES]; | |
350 | u32 RepQSize; | |
351 | u32 RepQCount; | |
352 | u32 RepQCtrAddrLow32; | |
353 | u32 RepQCtrAddrHigh32; | |
354 | u32 RepQAddr0Low32; | |
355 | u32 RepQAddr0High32; | |
edd16368 SC |
356 | }; |
357 | ||
358 | struct hpsa_pci_info { | |
359 | unsigned char bus; | |
360 | unsigned char dev_fn; | |
361 | unsigned short domain; | |
01a02ffc | 362 | u32 board_id; |
edd16368 SC |
363 | }; |
364 | ||
365 | #pragma pack() | |
366 | #endif /* HPSA_CMD_H */ |