[deliverable/linux.git] / drivers / scsi / hpsa_cmd.h

/*
 *    Disk Array driver for HP Smart Array SAS controllers
 *    Copyright 2000, 2009 Hewlett-Packard Development Company, L.P.
 *
 *    This program is free software; you can redistribute it and/or modify
 *    it under the terms of the GNU General Public License as published by
 *    the Free Software Foundation; version 2 of the License.
 *
 *    This program is distributed in the hope that it will be useful,
 *    but WITHOUT ANY WARRANTY; without even the implied warranty of
 *    MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
 *    NON INFRINGEMENT.  See the GNU General Public License for more details.
 *
 *    You should have received a copy of the GNU General Public License
 *    along with this program; if not, write to the Free Software
 *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 *    Questions/Comments/Bugfixes to iss_storagedev@hp.com
 *
 */
#ifndef HPSA_CMD_H
#define HPSA_CMD_H

/* general boundary defintions */
#define SENSEINFOBYTES          32 /* may vary between hbas */
#define SG_ENTRIES_IN_CMD	32 /* Max SG entries excluding chain blocks */
#define HPSA_SG_CHAIN		0x80000000
#define HPSA_SG_LAST		0x40000000
#define MAXREPLYQS              256

/* Command Status value */
#define CMD_SUCCESS             0x0000
#define CMD_TARGET_STATUS       0x0001
#define CMD_DATA_UNDERRUN       0x0002
#define CMD_DATA_OVERRUN        0x0003
#define CMD_INVALID             0x0004
#define CMD_PROTOCOL_ERR        0x0005
#define CMD_HARDWARE_ERR        0x0006
#define CMD_CONNECTION_LOST     0x0007
#define CMD_ABORTED             0x0008
#define CMD_ABORT_FAILED        0x0009
#define CMD_UNSOLICITED_ABORT   0x000A
#define CMD_TIMEOUT             0x000B
#define CMD_UNABORTABLE		0x000C

/* Unit Attentions ASC's as defined for the MSA2012sa */
#define POWER_OR_RESET			0x29
#define STATE_CHANGED			0x2a
#define UNIT_ATTENTION_CLEARED		0x2f
#define LUN_FAILED			0x3e
#define REPORT_LUNS_CHANGED		0x3f

/* Unit Attentions ASCQ's as defined for the MSA2012sa */

	/* These ASCQ's defined for ASC = POWER_OR_RESET */
#define POWER_ON_RESET			0x00
#define POWER_ON_REBOOT			0x01
#define SCSI_BUS_RESET			0x02
#define MSA_TARGET_RESET		0x03
#define CONTROLLER_FAILOVER		0x04
#define TRANSCEIVER_SE			0x05
#define TRANSCEIVER_LVD			0x06

	/* These ASCQ's defined for ASC = STATE_CHANGED */
#define RESERVATION_PREEMPTED		0x03
#define ASYM_ACCESS_CHANGED		0x06
#define LUN_CAPACITY_CHANGED		0x09

/* transfer direction */
#define XFER_NONE               0x00
#define XFER_WRITE              0x01
#define XFER_READ               0x02
#define XFER_RSVD               0x03

/* task attribute */
#define ATTR_UNTAGGED           0x00
#define ATTR_SIMPLE             0x04
#define ATTR_HEADOFQUEUE        0x05
#define ATTR_ORDERED            0x06
#define ATTR_ACA                0x07

/* cdb type */
#define TYPE_CMD				0x00
#define TYPE_MSG				0x01

/* Message Types  */
#define HPSA_TASK_MANAGEMENT    0x00
#define HPSA_RESET              0x01
#define HPSA_SCAN               0x02
#define HPSA_NOOP               0x03

#define HPSA_CTLR_RESET_TYPE    0x00
#define HPSA_BUS_RESET_TYPE     0x01
#define HPSA_TARGET_RESET_TYPE  0x03
#define HPSA_LUN_RESET_TYPE     0x04
#define HPSA_NEXUS_RESET_TYPE   0x05

/* Task Management Functions */
#define HPSA_TMF_ABORT_TASK     0x00
#define HPSA_TMF_ABORT_TASK_SET 0x01
#define HPSA_TMF_CLEAR_ACA      0x02
#define HPSA_TMF_CLEAR_TASK_SET 0x03
#define HPSA_TMF_QUERY_TASK     0x04
#define HPSA_TMF_QUERY_TASK_SET 0x05
#define HPSA_TMF_QUERY_ASYNCEVENT 0x06


/* config space register offsets */
#define CFG_VENDORID            0x00
#define CFG_DEVICEID            0x02
#define CFG_I2OBAR              0x10
#define CFG_MEM1BAR             0x14

/* i2o space register offsets */
#define I2O_IBDB_SET            0x20
#define I2O_IBDB_CLEAR          0x70
#define I2O_INT_STATUS          0x30
#define I2O_INT_MASK            0x34
#define I2O_IBPOST_Q            0x40
#define I2O_OBPOST_Q            0x44
#define I2O_DMA1_CFG		0x214

/* Configuration Table */
#define CFGTBL_ChangeReq        0x00000001l
#define CFGTBL_AccCmds          0x00000001l
#define DOORBELL_CTLR_RESET	0x00000004l
#define DOORBELL_CTLR_RESET2	0x00000020l

#define CFGTBL_Trans_Simple     0x00000002l
#define CFGTBL_Trans_Performant 0x00000004l
#define CFGTBL_Trans_io_accel1	0x00000080l
#define CFGTBL_Trans_use_short_tags 0x20000000l
#define CFGTBL_Trans_enable_directed_msix (1 << 30)

#define CFGTBL_BusType_Ultra2   0x00000001l
#define CFGTBL_BusType_Ultra3   0x00000002l
#define CFGTBL_BusType_Fibre1G  0x00000100l
#define CFGTBL_BusType_Fibre2G  0x00000200l
struct vals32 {
	u32   lower;
	u32   upper;
};

union u64bit {
	struct vals32 val32;
	u64 val;
};

/* FIXME this is a per controller value (barf!) */
#define HPSA_MAX_LUN 1024
#define HPSA_MAX_PHYS_LUN 1024
#define MAX_EXT_TARGETS 32
#define HPSA_MAX_DEVICES (HPSA_MAX_PHYS_LUN + HPSA_MAX_LUN + \
	MAX_EXT_TARGETS + 1) /* + 1 is for the controller itself */

/* SCSI-3 Commands */
#pragma pack(1)

#define HPSA_INQUIRY 0x12
struct InquiryData {
	u8 data_byte[36];
};

#define HPSA_REPORT_LOG 0xc2    /* Report Logical LUNs */
#define HPSA_REPORT_PHYS 0xc3   /* Report Physical LUNs */
#define HPSA_REPORT_PHYS_EXTENDED 0x02
struct ReportLUNdata {
	u8 LUNListLength[4];
	u32 reserved;
	u8 LUN[HPSA_MAX_LUN][8];
};

struct ReportExtendedLUNdata {
	u8 LUNListLength[4];
	u8 extended_response_flag;
	u8 reserved[3];
	u8 LUN[HPSA_MAX_LUN][24];
};

struct SenseSubsystem_info {
	u8 reserved[36];
	u8 portname[8];
	u8 reserved1[1108];
};

/* BMIC commands */
#define BMIC_READ 0x26
#define BMIC_WRITE 0x27
#define BMIC_CACHE_FLUSH 0xc2
#define HPSA_CACHE_FLUSH 0x01	/* C2 was already being used by HPSA */
#define BMIC_FLASH_FIRMWARE 0xF7

/* Command List Structure */
union SCSI3Addr {
	struct {
		u8 Dev;
		u8 Bus:6;
		u8 Mode:2;        /* b00 */
	} PeripDev;
	struct {
		u8 DevLSB;
		u8 DevMSB:6;
		u8 Mode:2;        /* b01 */
	} LogDev;
	struct {
		u8 Dev:5;
		u8 Bus:3;
		u8 Targ:6;
		u8 Mode:2;        /* b10 */
	} LogUnit;
};

struct PhysDevAddr {
	u32             TargetId:24;
	u32             Bus:6;
	u32             Mode:2;
	/* 2 level target device addr */
	union SCSI3Addr  Target[2];
};

struct LogDevAddr {
	u32            VolId:30;
	u32            Mode:2;
	u8             reserved[4];
};

union LUNAddr {
	u8               LunAddrBytes[8];
	union SCSI3Addr    SCSI3Lun[4];
	struct PhysDevAddr PhysDev;
	struct LogDevAddr  LogDev;
};

struct CommandListHeader {
	u8              ReplyQueue;
	u8              SGList;
	u16             SGTotal;
	struct vals32     Tag;
	union LUNAddr     LUN;
};

struct RequestBlock {
	u8   CDBLen;
	struct {
		u8 Type:3;
		u8 Attribute:3;
		u8 Direction:2;
	} Type;
	u16  Timeout;
	u8   CDB[16];
};

struct ErrDescriptor {
	struct vals32 Addr;
	u32  Len;
};

struct SGDescriptor {
	struct vals32 Addr;
	u32  Len;
	u32  Ext;
};

union MoreErrInfo {
	struct {
		u8  Reserved[3];
		u8  Type;
		u32 ErrorInfo;
	} Common_Info;
	struct {
		u8  Reserved[2];
		u8  offense_size; /* size of offending entry */
		u8  offense_num;  /* byte # of offense 0-base */
		u32 offense_value;
	} Invalid_Cmd;
};
struct ErrorInfo {
	u8               ScsiStatus;
	u8               SenseLen;
	u16              CommandStatus;
	u32              ResidualCnt;
	union MoreErrInfo  MoreErrInfo;
	u8               SenseInfo[SENSEINFOBYTES];
};
/* Command types */
#define CMD_IOCTL_PEND  0x01
#define CMD_SCSI	0x03
#define CMD_IOACCEL1	0x04

#define DIRECT_LOOKUP_SHIFT 5
#define DIRECT_LOOKUP_BIT 0x10
#define DIRECT_LOOKUP_MASK (~((1 << DIRECT_LOOKUP_SHIFT) - 1))

#define HPSA_ERROR_BIT          0x02
struct ctlr_info; /* defined in hpsa.h */
/* The size of this structure needs to be divisible by 32
 * on all architectures because low 5 bits of the addresses
 * are used as follows:
 *
 * bit 0: to device, used to indicate "performant mode" command
 *        from device, indidcates error status.
 * bit 1-3: to device, indicates block fetch table entry for
 *          reducing DMA in fetching commands from host memory.
 * bit 4: used to indicate whether tag is "direct lookup" (index),
 *        or a bus address.
 */

struct CommandList {
	struct CommandListHeader Header;
	struct RequestBlock      Request;
	struct ErrDescriptor     ErrDesc;
	struct SGDescriptor      SG[SG_ENTRIES_IN_CMD];
	/* information associated with the command */
	u32			   busaddr; /* physical addr of this record */
	struct ErrorInfo *err_info; /* pointer to the allocated mem */
	struct ctlr_info	   *h;
	int			   cmd_type;
	long			   cmdindex;
	struct list_head list;
	struct request *rq;
	struct completion *waiting;
	void   *scsi_cmd;

/* on 64 bit architectures, to get this to be 32-byte-aligned
 * it so happens we need PAD_64 bytes of padding, on 32 bit systems,
 * we need PAD_32 bytes of padding (see below).   This does that.
 * If it happens that 64 bit and 32 bit systems need different
 * padding, PAD_32 and PAD_64 can be set independently, and.
 * the code below will do the right thing.
 */
#define IS_32_BIT ((8 - sizeof(long))/4)
#define IS_64_BIT (!IS_32_BIT)
#define PAD_32 (4)
#define PAD_64 (4)
#define COMMANDLIST_PAD (IS_32_BIT * PAD_32 + IS_64_BIT * PAD_64)
	u8 pad[COMMANDLIST_PAD];
};

/* Max S/G elements in I/O accelerator command */
#define IOACCEL1_MAXSGENTRIES           24

/*
 * Structure for I/O accelerator (mode 1) commands.
 * Note that this structure must be 128-byte aligned in size.
 */
struct io_accel1_cmd {
	u16 dev_handle;			/* 0x00 - 0x01 */
	u8  reserved1;			/* 0x02 */
	u8  function;			/* 0x03 */
	u8  reserved2[8];		/* 0x04 - 0x0B */
	u32 err_info;			/* 0x0C - 0x0F */
	u8  reserved3[2];		/* 0x10 - 0x11 */
	u8  err_info_len;		/* 0x12 */
	u8  reserved4;			/* 0x13 */
	u8  sgl_offset;			/* 0x14 */
	u8  reserved5[7];		/* 0x15 - 0x1B */
	u32 transfer_len;		/* 0x1C - 0x1F */
	u8  reserved6[4];		/* 0x20 - 0x23 */
	u16 io_flags;			/* 0x24 - 0x25 */
	u8  reserved7[14];		/* 0x26 - 0x33 */
	u8  LUN[8];			/* 0x34 - 0x3B */
	u32 control;			/* 0x3C - 0x3F */
	u8  CDB[16];			/* 0x40 - 0x4F */
	u8  reserved8[16];		/* 0x50 - 0x5F */
	u16 host_context_flags;		/* 0x60 - 0x61 */
	u16 timeout_sec;		/* 0x62 - 0x63 */
	u8  ReplyQueue;			/* 0x64 */
	u8  reserved9[3];		/* 0x65 - 0x67 */
	struct vals32 Tag;		/* 0x68 - 0x6F */
	struct vals32 host_addr;	/* 0x70 - 0x77 */
	u8  CISS_LUN[8];		/* 0x78 - 0x7F */
	struct SGDescriptor SG[IOACCEL1_MAXSGENTRIES];
};

#define IOACCEL1_FUNCTION_SCSIIO        0x00
#define IOACCEL1_SGLOFFSET              32

#define IOACCEL1_IOFLAGS_IO_REQ         0x4000
#define IOACCEL1_IOFLAGS_CDBLEN_MASK    0x001F
#define IOACCEL1_IOFLAGS_CDBLEN_MAX     16

#define IOACCEL1_CONTROL_NODATAXFER     0x00000000
#define IOACCEL1_CONTROL_DATA_OUT       0x01000000
#define IOACCEL1_CONTROL_DATA_IN        0x02000000
#define IOACCEL1_CONTROL_TASKPRIO_MASK  0x00007800
#define IOACCEL1_CONTROL_TASKPRIO_SHIFT 11
#define IOACCEL1_CONTROL_SIMPLEQUEUE    0x00000000
#define IOACCEL1_CONTROL_HEADOFQUEUE    0x00000100
#define IOACCEL1_CONTROL_ORDEREDQUEUE   0x00000200
#define IOACCEL1_CONTROL_ACA            0x00000400

#define IOACCEL1_HCFLAGS_CISS_FORMAT    0x0013

#define IOACCEL1_BUSADDR_CMDTYPE        0x00000060

/* Configuration Table Structure */
struct HostWrite {
	u32 TransportRequest;
	u32 Reserved;
	u32 CoalIntDelay;
	u32 CoalIntCount;
};

#define SIMPLE_MODE     0x02
#define PERFORMANT_MODE 0x04
#define MEMQ_MODE       0x08
#define IOACCEL_MODE_1  0x80

struct CfgTable {
	u8            Signature[4];
	u32		SpecValence;
	u32           TransportSupport;
	u32           TransportActive;
	struct 		HostWrite HostWrite;
	u32           CmdsOutMax;
	u32           BusTypes;
	u32           TransMethodOffset;
	u8            ServerName[16];
	u32           HeartBeat;
	u32           driver_support;
#define			ENABLE_SCSI_PREFETCH 0x100
#define			ENABLE_UNIT_ATTN 0x01
	u32	 	MaxScatterGatherElements;
	u32		MaxLogicalUnits;
	u32		MaxPhysicalDevices;
	u32		MaxPhysicalDrivesPerLogicalUnit;
	u32		MaxPerformantModeCommands;
	u32		MaxBlockFetch;
	u32		PowerConservationSupport;
	u32		PowerConservationEnable;
	u32		TMFSupportFlags;
	u8		TMFTagMask[8];
	u8		reserved[0x78 - 0x70];
	u32		misc_fw_support; /* offset 0x78 */
#define			MISC_FW_DOORBELL_RESET (0x02)
#define			MISC_FW_DOORBELL_RESET2 (0x010)
	u8		driver_version[32];

};

#define NUM_BLOCKFETCH_ENTRIES 8
struct TransTable_struct {
	u32            BlockFetch[NUM_BLOCKFETCH_ENTRIES];
	u32            RepQSize;
	u32            RepQCount;
	u32            RepQCtrAddrLow32;
	u32            RepQCtrAddrHigh32;
#define MAX_REPLY_QUEUES 8
	struct vals32  RepQAddr[MAX_REPLY_QUEUES];
};

struct hpsa_pci_info {
	unsigned char	bus;
	unsigned char	dev_fn;
	unsigned short	domain;
	u32		board_id;
};

#pragma pack()
#endif /* HPSA_CMD_H */
Commit	Line	Data
edd16368 SC	1	/*
	2	* Disk Array driver for HP Smart Array SAS controllers
	3	* Copyright 2000, 2009 Hewlett-Packard Development Company, L.P.
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License as published by
	7	* the Free Software Foundation; version 2 of the License.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
	12	* NON INFRINGEMENT. See the GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	17	*
	18	* Questions/Comments/Bugfixes to iss_storagedev@hp.com
	19	*
	20	*/
	21	#ifndef HPSA_CMD_H
	22	#define HPSA_CMD_H
	23
	24	/* general boundary defintions */
	25	#define SENSEINFOBYTES 32 /* may vary between hbas */
d66ae08b	26	#define SG_ENTRIES_IN_CMD 32 /* Max SG entries excluding chain blocks */
33a2ffce	27	#define HPSA_SG_CHAIN 0x80000000
e1d9cbfa	28	#define HPSA_SG_LAST 0x40000000
edd16368 SC	29	#define MAXREPLYQS 256
	30
	31	/* Command Status value */
	32	#define CMD_SUCCESS 0x0000
	33	#define CMD_TARGET_STATUS 0x0001
	34	#define CMD_DATA_UNDERRUN 0x0002
	35	#define CMD_DATA_OVERRUN 0x0003
	36	#define CMD_INVALID 0x0004
	37	#define CMD_PROTOCOL_ERR 0x0005
	38	#define CMD_HARDWARE_ERR 0x0006
	39	#define CMD_CONNECTION_LOST 0x0007
	40	#define CMD_ABORTED 0x0008
	41	#define CMD_ABORT_FAILED 0x0009
	42	#define CMD_UNSOLICITED_ABORT 0x000A
	43	#define CMD_TIMEOUT 0x000B
	44	#define CMD_UNABORTABLE 0x000C
	45
	46	/* Unit Attentions ASC's as defined for the MSA2012sa */
	47	#define POWER_OR_RESET 0x29
	48	#define STATE_CHANGED 0x2a
	49	#define UNIT_ATTENTION_CLEARED 0x2f
	50	#define LUN_FAILED 0x3e
	51	#define REPORT_LUNS_CHANGED 0x3f
	52
	53	/* Unit Attentions ASCQ's as defined for the MSA2012sa */
	54
	55	/* These ASCQ's defined for ASC = POWER_OR_RESET */
	56	#define POWER_ON_RESET 0x00
	57	#define POWER_ON_REBOOT 0x01
	58	#define SCSI_BUS_RESET 0x02
	59	#define MSA_TARGET_RESET 0x03
	60	#define CONTROLLER_FAILOVER 0x04
	61	#define TRANSCEIVER_SE 0x05
	62	#define TRANSCEIVER_LVD 0x06
	63
	64	/* These ASCQ's defined for ASC = STATE_CHANGED */
	65	#define RESERVATION_PREEMPTED 0x03
	66	#define ASYM_ACCESS_CHANGED 0x06
	67	#define LUN_CAPACITY_CHANGED 0x09
	68
	69	/* transfer direction */
	70	#define XFER_NONE 0x00
	71	#define XFER_WRITE 0x01
	72	#define XFER_READ 0x02
	73	#define XFER_RSVD 0x03
	74
	75	/* task attribute */
	76	#define ATTR_UNTAGGED 0x00
	77	#define ATTR_SIMPLE 0x04
	78	#define ATTR_HEADOFQUEUE 0x05
	79	#define ATTR_ORDERED 0x06
	80	#define ATTR_ACA 0x07
	81
	82	/* cdb type */
	83	#define TYPE_CMD 0x00
	84	#define TYPE_MSG 0x01
	85
75167d2c SC	86	/* Message Types */
	87	#define HPSA_TASK_MANAGEMENT 0x00
	88	#define HPSA_RESET 0x01
	89	#define HPSA_SCAN 0x02
	90	#define HPSA_NOOP 0x03
	91
	92	#define HPSA_CTLR_RESET_TYPE 0x00
	93	#define HPSA_BUS_RESET_TYPE 0x01
	94	#define HPSA_TARGET_RESET_TYPE 0x03
	95	#define HPSA_LUN_RESET_TYPE 0x04
	96	#define HPSA_NEXUS_RESET_TYPE 0x05
	97
	98	/* Task Management Functions */
	99	#define HPSA_TMF_ABORT_TASK 0x00
	100	#define HPSA_TMF_ABORT_TASK_SET 0x01
	101	#define HPSA_TMF_CLEAR_ACA 0x02
	102	#define HPSA_TMF_CLEAR_TASK_SET 0x03
	103	#define HPSA_TMF_QUERY_TASK 0x04
	104	#define HPSA_TMF_QUERY_TASK_SET 0x05
	105	#define HPSA_TMF_QUERY_ASYNCEVENT 0x06
	106
	107
	108
edd16368 SC	109	/* config space register offsets */
	110	#define CFG_VENDORID 0x00
	111	#define CFG_DEVICEID 0x02
	112	#define CFG_I2OBAR 0x10
	113	#define CFG_MEM1BAR 0x14
	114
	115	/* i2o space register offsets */
	116	#define I2O_IBDB_SET 0x20
	117	#define I2O_IBDB_CLEAR 0x70
	118	#define I2O_INT_STATUS 0x30
	119	#define I2O_INT_MASK 0x34
	120	#define I2O_IBPOST_Q 0x40
	121	#define I2O_OBPOST_Q 0x44
	122	#define I2O_DMA1_CFG 0x214
	123
	124	/* Configuration Table */
	125	#define CFGTBL_ChangeReq 0x00000001l
	126	#define CFGTBL_AccCmds 0x00000001l
1df8552a	127	#define DOORBELL_CTLR_RESET 0x00000004l
cf0b08d0	128	#define DOORBELL_CTLR_RESET2 0x00000020l
edd16368 SC	129
edd16368 SC	130	#define CFGTBL_Trans_Simple 0x00000002l
303932fd	131	#define CFGTBL_Trans_Performant 0x00000004l
e1f7de0c	132	#define CFGTBL_Trans_io_accel1 0x00000080l
960a30e7	133	#define CFGTBL_Trans_use_short_tags 0x20000000l
254f796b	134	#define CFGTBL_Trans_enable_directed_msix (1 << 30)
edd16368 SC	135
	136	#define CFGTBL_BusType_Ultra2 0x00000001l
	137	#define CFGTBL_BusType_Ultra3 0x00000002l
	138	#define CFGTBL_BusType_Fibre1G 0x00000100l
	139	#define CFGTBL_BusType_Fibre2G 0x00000200l
	140	struct vals32 {
01a02ffc SC	141	u32 lower;
01a02ffc SC	142	u32 upper;
edd16368 SC	143	};
	144
	145	union u64bit {
	146	struct vals32 val32;
01a02ffc	147	u64 val;
edd16368 SC	148	};
	149
	150	/* FIXME this is a per controller value (barf!) */
b7ec021f	151	#define HPSA_MAX_LUN 1024
edd16368	152	#define HPSA_MAX_PHYS_LUN 1024
aca4a520	153	#define MAX_EXT_TARGETS 32
b7ec021f	154	#define HPSA_MAX_DEVICES (HPSA_MAX_PHYS_LUN + HPSA_MAX_LUN + \
aca4a520	155	MAX_EXT_TARGETS + 1) /* + 1 is for the controller itself */
edd16368 SC	156
	157	/* SCSI-3 Commands */
	158	#pragma pack(1)
	159
	160	#define HPSA_INQUIRY 0x12
	161	struct InquiryData {
01a02ffc	162	u8 data_byte[36];
edd16368 SC	163	};
	164
	165	#define HPSA_REPORT_LOG 0xc2 /* Report Logical LUNs */
	166	#define HPSA_REPORT_PHYS 0xc3 /* Report Physical LUNs */
a93aa1fe	167	#define HPSA_REPORT_PHYS_EXTENDED 0x02
edd16368	168	struct ReportLUNdata {
01a02ffc SC	169	u8 LUNListLength[4];
	170	u32 reserved;
	171	u8 LUN[HPSA_MAX_LUN][8];
edd16368 SC	172	};
	173
	174	struct ReportExtendedLUNdata {
01a02ffc SC	175	u8 LUNListLength[4];
	176	u8 extended_response_flag;
	177	u8 reserved[3];
	178	u8 LUN[HPSA_MAX_LUN][24];
edd16368 SC	179	};
	180
	181	struct SenseSubsystem_info {
01a02ffc SC	182	u8 reserved[36];
	183	u8 portname[8];
	184	u8 reserved1[1108];
edd16368 SC	185	};
edd16368 SC	186
edd16368 SC	187	/* BMIC commands */
	188	#define BMIC_READ 0x26
	189	#define BMIC_WRITE 0x27
	190	#define BMIC_CACHE_FLUSH 0xc2
	191	#define HPSA_CACHE_FLUSH 0x01 /* C2 was already being used by HPSA */
e85c5974	192	#define BMIC_FLASH_FIRMWARE 0xF7
edd16368 SC	193
	194	/* Command List Structure */
	195	union SCSI3Addr {
	196	struct {
01a02ffc SC	197	u8 Dev;
	198	u8 Bus:6;
	199	u8 Mode:2; /* b00 */
edd16368 SC	200	} PeripDev;
edd16368 SC	201	struct {
01a02ffc SC	202	u8 DevLSB;
	203	u8 DevMSB:6;
	204	u8 Mode:2; /* b01 */
edd16368 SC	205	} LogDev;
edd16368 SC	206	struct {
01a02ffc SC	207	u8 Dev:5;
	208	u8 Bus:3;
	209	u8 Targ:6;
	210	u8 Mode:2; /* b10 */
edd16368 SC	211	} LogUnit;
	212	};
	213
	214	struct PhysDevAddr {
01a02ffc SC	215	u32 TargetId:24;
	216	u32 Bus:6;
	217	u32 Mode:2;
edd16368 SC	218	/* 2 level target device addr */
	219	union SCSI3Addr Target[2];
	220	};
	221
	222	struct LogDevAddr {
01a02ffc SC	223	u32 VolId:30;
	224	u32 Mode:2;
	225	u8 reserved[4];
edd16368 SC	226	};
	227
	228	union LUNAddr {
01a02ffc	229	u8 LunAddrBytes[8];
edd16368 SC	230	union SCSI3Addr SCSI3Lun[4];
	231	struct PhysDevAddr PhysDev;
	232	struct LogDevAddr LogDev;
	233	};
	234
	235	struct CommandListHeader {
01a02ffc SC	236	u8 ReplyQueue;
	237	u8 SGList;
	238	u16 SGTotal;
edd16368 SC	239	struct vals32 Tag;
	240	union LUNAddr LUN;
	241	};
	242
	243	struct RequestBlock {
01a02ffc	244	u8 CDBLen;
edd16368	245	struct {
01a02ffc SC	246	u8 Type:3;
	247	u8 Attribute:3;
	248	u8 Direction:2;
edd16368	249	} Type;
01a02ffc SC	250	u16 Timeout;
01a02ffc SC	251	u8 CDB[16];
edd16368 SC	252	};
	253
	254	struct ErrDescriptor {
	255	struct vals32 Addr;
01a02ffc	256	u32 Len;
edd16368 SC	257	};
	258
	259	struct SGDescriptor {
	260	struct vals32 Addr;
01a02ffc SC	261	u32 Len;
01a02ffc SC	262	u32 Ext;
edd16368 SC	263	};
	264
	265	union MoreErrInfo {
	266	struct {
01a02ffc SC	267	u8 Reserved[3];
	268	u8 Type;
	269	u32 ErrorInfo;
edd16368 SC	270	} Common_Info;
edd16368 SC	271	struct {
01a02ffc SC	272	u8 Reserved[2];
	273	u8 offense_size; /* size of offending entry */
	274	u8 offense_num; /* byte # of offense 0-base */
	275	u32 offense_value;
edd16368 SC	276	} Invalid_Cmd;
	277	};
	278	struct ErrorInfo {
01a02ffc SC	279	u8 ScsiStatus;
	280	u8 SenseLen;
	281	u16 CommandStatus;
	282	u32 ResidualCnt;
edd16368	283	union MoreErrInfo MoreErrInfo;
01a02ffc	284	u8 SenseInfo[SENSEINFOBYTES];
edd16368 SC	285	};
	286	/* Command types */
	287	#define CMD_IOCTL_PEND 0x01
	288	#define CMD_SCSI 0x03
e1f7de0c	289	#define CMD_IOACCEL1 0x04
edd16368	290
303932fd DB	291	#define DIRECT_LOOKUP_SHIFT 5
303932fd DB	292	#define DIRECT_LOOKUP_BIT 0x10
d896f3f3	293	#define DIRECT_LOOKUP_MASK (~((1 << DIRECT_LOOKUP_SHIFT) - 1))
303932fd DB	294
303932fd DB	295	#define HPSA_ERROR_BIT 0x02
edd16368	296	struct ctlr_info; /* defined in hpsa.h */
303932fd DB	297	/* The size of this structure needs to be divisible by 32
	298	* on all architectures because low 5 bits of the addresses
	299	* are used as follows:
	300	*
	301	* bit 0: to device, used to indicate "performant mode" command
	302	* from device, indidcates error status.
	303	* bit 1-3: to device, indicates block fetch table entry for
	304	* reducing DMA in fetching commands from host memory.
	305	* bit 4: used to indicate whether tag is "direct lookup" (index),
	306	* or a bus address.
edd16368	307	*/
303932fd	308
edd16368 SC	309	struct CommandList {
	310	struct CommandListHeader Header;
	311	struct RequestBlock Request;
	312	struct ErrDescriptor ErrDesc;
d66ae08b	313	struct SGDescriptor SG[SG_ENTRIES_IN_CMD];
edd16368	314	/* information associated with the command */
01a02ffc	315	u32 busaddr; /* physical addr of this record */
edd16368 SC	316	struct ErrorInfo err_info; / pointer to the allocated mem */
	317	struct ctlr_info *h;
	318	int cmd_type;
	319	long cmdindex;
9e0fc764	320	struct list_head list;
edd16368 SC	321	struct request *rq;
edd16368 SC	322	struct completion *waiting;
edd16368	323	void *scsi_cmd;
303932fd DB	324
303932fd DB	325	/* on 64 bit architectures, to get this to be 32-byte-aligned
db61bfcf SC	326	* it so happens we need PAD_64 bytes of padding, on 32 bit systems,
	327	* we need PAD_32 bytes of padding (see below). This does that.
	328	* If it happens that 64 bit and 32 bit systems need different
	329	* padding, PAD_32 and PAD_64 can be set independently, and.
	330	* the code below will do the right thing.
303932fd	331	*/
db61bfcf SC	332	#define IS_32_BIT ((8 - sizeof(long))/4)
db61bfcf SC	333	#define IS_64_BIT (!IS_32_BIT)
43aebfa1 SC	334	#define PAD_32 (4)
43aebfa1 SC	335	#define PAD_64 (4)
db61bfcf	336	#define COMMANDLIST_PAD (IS_32_BIT * PAD_32 + IS_64_BIT * PAD_64)
303932fd	337	u8 pad[COMMANDLIST_PAD];
edd16368 SC	338	};
edd16368 SC	339
e1f7de0c MG	340	/* Max S/G elements in I/O accelerator command */
	341	#define IOACCEL1_MAXSGENTRIES 24
	342
	343	/*
	344	* Structure for I/O accelerator (mode 1) commands.
	345	* Note that this structure must be 128-byte aligned in size.
	346	*/
	347	struct io_accel1_cmd {
	348	u16 dev_handle; /* 0x00 - 0x01 */
	349	u8 reserved1; /* 0x02 */
	350	u8 function; /* 0x03 */
	351	u8 reserved2[8]; /* 0x04 - 0x0B */
	352	u32 err_info; /* 0x0C - 0x0F */
	353	u8 reserved3[2]; /* 0x10 - 0x11 */
	354	u8 err_info_len; /* 0x12 */
	355	u8 reserved4; /* 0x13 */
	356	u8 sgl_offset; /* 0x14 */
	357	u8 reserved5[7]; /* 0x15 - 0x1B */
	358	u32 transfer_len; /* 0x1C - 0x1F */
	359	u8 reserved6[4]; /* 0x20 - 0x23 */
	360	u16 io_flags; /* 0x24 - 0x25 */
	361	u8 reserved7[14]; /* 0x26 - 0x33 */
	362	u8 LUN[8]; /* 0x34 - 0x3B */
	363	u32 control; /* 0x3C - 0x3F */
	364	u8 CDB[16]; /* 0x40 - 0x4F */
	365	u8 reserved8[16]; /* 0x50 - 0x5F */
	366	u16 host_context_flags; /* 0x60 - 0x61 */
	367	u16 timeout_sec; /* 0x62 - 0x63 */
	368	u8 ReplyQueue; /* 0x64 */
	369	u8 reserved9[3]; /* 0x65 - 0x67 */
	370	struct vals32 Tag; /* 0x68 - 0x6F */
	371	struct vals32 host_addr; /* 0x70 - 0x77 */
	372	u8 CISS_LUN[8]; /* 0x78 - 0x7F */
	373	struct SGDescriptor SG[IOACCEL1_MAXSGENTRIES];
	374	};
	375
	376	#define IOACCEL1_FUNCTION_SCSIIO 0x00
	377	#define IOACCEL1_SGLOFFSET 32
	378
	379	#define IOACCEL1_IOFLAGS_IO_REQ 0x4000
	380	#define IOACCEL1_IOFLAGS_CDBLEN_MASK 0x001F
	381	#define IOACCEL1_IOFLAGS_CDBLEN_MAX 16
	382
	383	#define IOACCEL1_CONTROL_NODATAXFER 0x00000000
	384	#define IOACCEL1_CONTROL_DATA_OUT 0x01000000
	385	#define IOACCEL1_CONTROL_DATA_IN 0x02000000
	386	#define IOACCEL1_CONTROL_TASKPRIO_MASK 0x00007800
	387	#define IOACCEL1_CONTROL_TASKPRIO_SHIFT 11
	388	#define IOACCEL1_CONTROL_SIMPLEQUEUE 0x00000000
	389	#define IOACCEL1_CONTROL_HEADOFQUEUE 0x00000100
	390	#define IOACCEL1_CONTROL_ORDEREDQUEUE 0x00000200
	391	#define IOACCEL1_CONTROL_ACA 0x00000400
	392
	393	#define IOACCEL1_HCFLAGS_CISS_FORMAT 0x0013
	394
	395	#define IOACCEL1_BUSADDR_CMDTYPE 0x00000060
	396
edd16368 SC	397	/* Configuration Table Structure */
edd16368 SC	398	struct HostWrite {
01a02ffc SC	399	u32 TransportRequest;
	400	u32 Reserved;
	401	u32 CoalIntDelay;
	402	u32 CoalIntCount;
edd16368 SC	403	};
edd16368 SC	404
303932fd DB	405	#define SIMPLE_MODE 0x02
	406	#define PERFORMANT_MODE 0x04
	407	#define MEMQ_MODE 0x08
e1f7de0c	408	#define IOACCEL_MODE_1 0x80
303932fd	409
edd16368	410	struct CfgTable {
303932fd DB	411	u8 Signature[4];
	412	u32 SpecValence;
	413	u32 TransportSupport;
	414	u32 TransportActive;
	415	struct HostWrite HostWrite;
	416	u32 CmdsOutMax;
	417	u32 BusTypes;
	418	u32 TransMethodOffset;
	419	u8 ServerName[16];
	420	u32 HeartBeat;
97a5e98c SC	421	u32 driver_support;
97a5e98c SC	422	#define ENABLE_SCSI_PREFETCH 0x100
28e13446	423	#define ENABLE_UNIT_ATTN 0x01
303932fd DB	424	u32 MaxScatterGatherElements;
	425	u32 MaxLogicalUnits;
	426	u32 MaxPhysicalDevices;
	427	u32 MaxPhysicalDrivesPerLogicalUnit;
	428	u32 MaxPerformantModeCommands;
75167d2c SC	429	u32 MaxBlockFetch;
	430	u32 PowerConservationSupport;
	431	u32 PowerConservationEnable;
	432	u32 TMFSupportFlags;
	433	u8 TMFTagMask[8];
	434	u8 reserved[0x78 - 0x70];
1df8552a SC	435	u32 misc_fw_support; /* offset 0x78 */
1df8552a SC	436	#define MISC_FW_DOORBELL_RESET (0x02)
cf0b08d0	437	#define MISC_FW_DOORBELL_RESET2 (0x010)
580ada3c	438	u8 driver_version[32];
75167d2c	439
303932fd DB	440	};
	441
	442	#define NUM_BLOCKFETCH_ENTRIES 8
	443	struct TransTable_struct {
	444	u32 BlockFetch[NUM_BLOCKFETCH_ENTRIES];
	445	u32 RepQSize;
	446	u32 RepQCount;
	447	u32 RepQCtrAddrLow32;
	448	u32 RepQCtrAddrHigh32;
254f796b MG	449	#define MAX_REPLY_QUEUES 8
254f796b MG	450	struct vals32 RepQAddr[MAX_REPLY_QUEUES];
edd16368 SC	451	};
	452
	453	struct hpsa_pci_info {
	454	unsigned char bus;
	455	unsigned char dev_fn;
	456	unsigned short domain;
01a02ffc	457	u32 board_id;
edd16368 SC	458	};
	459
	460	#pragma pack()
	461	#endif /* HPSA_CMD_H */