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edd16368 SC |
1 | /* |
2 | * Disk Array driver for HP Smart Array SAS controllers | |
51c35139 | 3 | * Copyright 2000, 2014 Hewlett-Packard Development Company, L.P. |
edd16368 SC |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; version 2 of the License. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
12 | * NON INFRINGEMENT. See the GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
17 | * | |
18 | * Questions/Comments/Bugfixes to iss_storagedev@hp.com | |
19 | * | |
20 | */ | |
21 | #ifndef HPSA_CMD_H | |
22 | #define HPSA_CMD_H | |
23 | ||
24 | /* general boundary defintions */ | |
25 | #define SENSEINFOBYTES 32 /* may vary between hbas */ | |
d66ae08b | 26 | #define SG_ENTRIES_IN_CMD 32 /* Max SG entries excluding chain blocks */ |
33a2ffce | 27 | #define HPSA_SG_CHAIN 0x80000000 |
e1d9cbfa | 28 | #define HPSA_SG_LAST 0x40000000 |
edd16368 SC |
29 | #define MAXREPLYQS 256 |
30 | ||
31 | /* Command Status value */ | |
32 | #define CMD_SUCCESS 0x0000 | |
33 | #define CMD_TARGET_STATUS 0x0001 | |
34 | #define CMD_DATA_UNDERRUN 0x0002 | |
35 | #define CMD_DATA_OVERRUN 0x0003 | |
36 | #define CMD_INVALID 0x0004 | |
37 | #define CMD_PROTOCOL_ERR 0x0005 | |
38 | #define CMD_HARDWARE_ERR 0x0006 | |
39 | #define CMD_CONNECTION_LOST 0x0007 | |
40 | #define CMD_ABORTED 0x0008 | |
41 | #define CMD_ABORT_FAILED 0x0009 | |
42 | #define CMD_UNSOLICITED_ABORT 0x000A | |
43 | #define CMD_TIMEOUT 0x000B | |
44 | #define CMD_UNABORTABLE 0x000C | |
283b4a9b SC |
45 | #define CMD_IOACCEL_DISABLED 0x000E |
46 | ||
edd16368 SC |
47 | |
48 | /* Unit Attentions ASC's as defined for the MSA2012sa */ | |
49 | #define POWER_OR_RESET 0x29 | |
50 | #define STATE_CHANGED 0x2a | |
51 | #define UNIT_ATTENTION_CLEARED 0x2f | |
52 | #define LUN_FAILED 0x3e | |
53 | #define REPORT_LUNS_CHANGED 0x3f | |
54 | ||
55 | /* Unit Attentions ASCQ's as defined for the MSA2012sa */ | |
56 | ||
57 | /* These ASCQ's defined for ASC = POWER_OR_RESET */ | |
58 | #define POWER_ON_RESET 0x00 | |
59 | #define POWER_ON_REBOOT 0x01 | |
60 | #define SCSI_BUS_RESET 0x02 | |
61 | #define MSA_TARGET_RESET 0x03 | |
62 | #define CONTROLLER_FAILOVER 0x04 | |
63 | #define TRANSCEIVER_SE 0x05 | |
64 | #define TRANSCEIVER_LVD 0x06 | |
65 | ||
66 | /* These ASCQ's defined for ASC = STATE_CHANGED */ | |
67 | #define RESERVATION_PREEMPTED 0x03 | |
68 | #define ASYM_ACCESS_CHANGED 0x06 | |
69 | #define LUN_CAPACITY_CHANGED 0x09 | |
70 | ||
71 | /* transfer direction */ | |
72 | #define XFER_NONE 0x00 | |
73 | #define XFER_WRITE 0x01 | |
74 | #define XFER_READ 0x02 | |
75 | #define XFER_RSVD 0x03 | |
76 | ||
77 | /* task attribute */ | |
78 | #define ATTR_UNTAGGED 0x00 | |
79 | #define ATTR_SIMPLE 0x04 | |
80 | #define ATTR_HEADOFQUEUE 0x05 | |
81 | #define ATTR_ORDERED 0x06 | |
82 | #define ATTR_ACA 0x07 | |
83 | ||
84 | /* cdb type */ | |
54b6e9e9 ST |
85 | #define TYPE_CMD 0x00 |
86 | #define TYPE_MSG 0x01 | |
87 | #define TYPE_IOACCEL2_CMD 0x81 /* 0x81 is not used by hardware */ | |
edd16368 | 88 | |
75167d2c SC |
89 | /* Message Types */ |
90 | #define HPSA_TASK_MANAGEMENT 0x00 | |
91 | #define HPSA_RESET 0x01 | |
92 | #define HPSA_SCAN 0x02 | |
93 | #define HPSA_NOOP 0x03 | |
94 | ||
95 | #define HPSA_CTLR_RESET_TYPE 0x00 | |
96 | #define HPSA_BUS_RESET_TYPE 0x01 | |
97 | #define HPSA_TARGET_RESET_TYPE 0x03 | |
98 | #define HPSA_LUN_RESET_TYPE 0x04 | |
99 | #define HPSA_NEXUS_RESET_TYPE 0x05 | |
100 | ||
101 | /* Task Management Functions */ | |
102 | #define HPSA_TMF_ABORT_TASK 0x00 | |
103 | #define HPSA_TMF_ABORT_TASK_SET 0x01 | |
104 | #define HPSA_TMF_CLEAR_ACA 0x02 | |
105 | #define HPSA_TMF_CLEAR_TASK_SET 0x03 | |
106 | #define HPSA_TMF_QUERY_TASK 0x04 | |
107 | #define HPSA_TMF_QUERY_TASK_SET 0x05 | |
108 | #define HPSA_TMF_QUERY_ASYNCEVENT 0x06 | |
109 | ||
110 | ||
111 | ||
edd16368 SC |
112 | /* config space register offsets */ |
113 | #define CFG_VENDORID 0x00 | |
114 | #define CFG_DEVICEID 0x02 | |
115 | #define CFG_I2OBAR 0x10 | |
116 | #define CFG_MEM1BAR 0x14 | |
117 | ||
118 | /* i2o space register offsets */ | |
119 | #define I2O_IBDB_SET 0x20 | |
120 | #define I2O_IBDB_CLEAR 0x70 | |
121 | #define I2O_INT_STATUS 0x30 | |
122 | #define I2O_INT_MASK 0x34 | |
123 | #define I2O_IBPOST_Q 0x40 | |
124 | #define I2O_OBPOST_Q 0x44 | |
125 | #define I2O_DMA1_CFG 0x214 | |
126 | ||
127 | /* Configuration Table */ | |
128 | #define CFGTBL_ChangeReq 0x00000001l | |
129 | #define CFGTBL_AccCmds 0x00000001l | |
1df8552a | 130 | #define DOORBELL_CTLR_RESET 0x00000004l |
cf0b08d0 | 131 | #define DOORBELL_CTLR_RESET2 0x00000020l |
76438d08 | 132 | #define DOORBELL_CLEAR_EVENTS 0x00000040l |
edd16368 SC |
133 | |
134 | #define CFGTBL_Trans_Simple 0x00000002l | |
303932fd | 135 | #define CFGTBL_Trans_Performant 0x00000004l |
e1f7de0c | 136 | #define CFGTBL_Trans_io_accel1 0x00000080l |
1f7cee8c | 137 | #define CFGTBL_Trans_io_accel2 0x00000100l |
960a30e7 | 138 | #define CFGTBL_Trans_use_short_tags 0x20000000l |
254f796b | 139 | #define CFGTBL_Trans_enable_directed_msix (1 << 30) |
edd16368 SC |
140 | |
141 | #define CFGTBL_BusType_Ultra2 0x00000001l | |
142 | #define CFGTBL_BusType_Ultra3 0x00000002l | |
143 | #define CFGTBL_BusType_Fibre1G 0x00000100l | |
144 | #define CFGTBL_BusType_Fibre2G 0x00000200l | |
283b4a9b SC |
145 | |
146 | /* VPD Inquiry types */ | |
1b70150a | 147 | #define HPSA_VPD_SUPPORTED_PAGES 0x00 |
283b4a9b SC |
148 | #define HPSA_VPD_LV_DEVICE_GEOMETRY 0xC1 |
149 | #define HPSA_VPD_LV_IOACCEL_STATUS 0xC2 | |
9846590e | 150 | #define HPSA_VPD_LV_STATUS 0xC3 |
1b70150a | 151 | #define HPSA_VPD_HEADER_SZ 4 |
283b4a9b | 152 | |
9846590e | 153 | /* Logical volume states */ |
67955ba3 | 154 | #define HPSA_VPD_LV_STATUS_UNSUPPORTED 0xff |
9846590e SC |
155 | #define HPSA_LV_OK 0x0 |
156 | #define HPSA_LV_UNDERGOING_ERASE 0x0F | |
157 | #define HPSA_LV_UNDERGOING_RPI 0x12 | |
158 | #define HPSA_LV_PENDING_RPI 0x13 | |
159 | #define HPSA_LV_ENCRYPTED_NO_KEY 0x14 | |
160 | #define HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER 0x15 | |
161 | #define HPSA_LV_UNDERGOING_ENCRYPTION 0x16 | |
162 | #define HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING 0x17 | |
163 | #define HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER 0x18 | |
164 | #define HPSA_LV_PENDING_ENCRYPTION 0x19 | |
165 | #define HPSA_LV_PENDING_ENCRYPTION_REKEYING 0x1A | |
166 | ||
edd16368 | 167 | struct vals32 { |
01a02ffc SC |
168 | u32 lower; |
169 | u32 upper; | |
edd16368 SC |
170 | }; |
171 | ||
172 | union u64bit { | |
173 | struct vals32 val32; | |
01a02ffc | 174 | u64 val; |
edd16368 SC |
175 | }; |
176 | ||
177 | /* FIXME this is a per controller value (barf!) */ | |
b7ec021f | 178 | #define HPSA_MAX_LUN 1024 |
edd16368 | 179 | #define HPSA_MAX_PHYS_LUN 1024 |
aca4a520 | 180 | #define MAX_EXT_TARGETS 32 |
b7ec021f | 181 | #define HPSA_MAX_DEVICES (HPSA_MAX_PHYS_LUN + HPSA_MAX_LUN + \ |
aca4a520 | 182 | MAX_EXT_TARGETS + 1) /* + 1 is for the controller itself */ |
edd16368 SC |
183 | |
184 | /* SCSI-3 Commands */ | |
185 | #pragma pack(1) | |
186 | ||
187 | #define HPSA_INQUIRY 0x12 | |
188 | struct InquiryData { | |
01a02ffc | 189 | u8 data_byte[36]; |
edd16368 SC |
190 | }; |
191 | ||
192 | #define HPSA_REPORT_LOG 0xc2 /* Report Logical LUNs */ | |
193 | #define HPSA_REPORT_PHYS 0xc3 /* Report Physical LUNs */ | |
a93aa1fe | 194 | #define HPSA_REPORT_PHYS_EXTENDED 0x02 |
283b4a9b SC |
195 | #define HPSA_CISS_READ 0xc0 /* CISS Read */ |
196 | #define HPSA_GET_RAID_MAP 0xc8 /* CISS Get RAID Layout Map */ | |
197 | ||
198 | #define RAID_MAP_MAX_ENTRIES 256 | |
199 | ||
200 | struct raid_map_disk_data { | |
201 | u32 ioaccel_handle; /**< Handle to access this disk via the | |
202 | * I/O accelerator */ | |
203 | u8 xor_mult[2]; /**< XOR multipliers for this position, | |
204 | * valid for data disks only */ | |
205 | u8 reserved[2]; | |
206 | }; | |
207 | ||
208 | struct raid_map_data { | |
2b08b3e9 DB |
209 | __le32 structure_size; /* Size of entire structure in bytes */ |
210 | __le32 volume_blk_size; /* bytes / block in the volume */ | |
211 | __le64 volume_blk_cnt; /* logical blocks on the volume */ | |
283b4a9b SC |
212 | u8 phys_blk_shift; /* Shift factor to convert between |
213 | * units of logical blocks and physical | |
214 | * disk blocks */ | |
215 | u8 parity_rotation_shift; /* Shift factor to convert between units | |
216 | * of logical stripes and physical | |
217 | * stripes */ | |
2b08b3e9 DB |
218 | __le16 strip_size; /* blocks used on each disk / stripe */ |
219 | __le64 disk_starting_blk; /* First disk block used in volume */ | |
220 | __le64 disk_blk_cnt; /* disk blocks used by volume / disk */ | |
221 | __le16 data_disks_per_row; /* data disk entries / row in the map */ | |
222 | __le16 metadata_disks_per_row;/* mirror/parity disk entries / row | |
283b4a9b | 223 | * in the map */ |
2b08b3e9 DB |
224 | __le16 row_cnt; /* rows in each layout map */ |
225 | __le16 layout_map_count; /* layout maps (1 map per mirror/parity | |
283b4a9b | 226 | * group) */ |
2b08b3e9 | 227 | __le16 flags; /* Bit 0 set if encryption enabled */ |
dd0e19f3 | 228 | #define RAID_MAP_FLAG_ENCRYPT_ON 0x01 |
2b08b3e9 | 229 | __le16 dekindex; /* Data encryption key index. */ |
dd0e19f3 | 230 | u8 reserved[16]; |
283b4a9b SC |
231 | struct raid_map_disk_data data[RAID_MAP_MAX_ENTRIES]; |
232 | }; | |
233 | ||
edd16368 | 234 | struct ReportLUNdata { |
01a02ffc | 235 | u8 LUNListLength[4]; |
283b4a9b SC |
236 | u8 extended_response_flag; |
237 | u8 reserved[3]; | |
01a02ffc | 238 | u8 LUN[HPSA_MAX_LUN][8]; |
edd16368 SC |
239 | }; |
240 | ||
d5b5d964 SC |
241 | struct ext_report_lun_entry { |
242 | u8 lunid[8]; | |
03383736 DB |
243 | #define GET_BMIC_BUS(lunid) ((lunid)[7] & 0x3F) |
244 | #define GET_BMIC_LEVEL_TWO_TARGET(lunid) ((lunid)[6]) | |
245 | #define GET_BMIC_DRIVE_NUMBER(lunid) (((GET_BMIC_BUS((lunid)) - 1) << 8) + \ | |
246 | GET_BMIC_LEVEL_TWO_TARGET((lunid))) | |
d5b5d964 SC |
247 | u8 wwid[8]; |
248 | u8 device_type; | |
249 | u8 device_flags; | |
250 | u8 lun_count; /* multi-lun device, how many luns */ | |
251 | u8 redundant_paths; | |
252 | u32 ioaccel_handle; /* ioaccel1 only uses lower 16 bits */ | |
253 | }; | |
254 | ||
edd16368 | 255 | struct ReportExtendedLUNdata { |
01a02ffc SC |
256 | u8 LUNListLength[4]; |
257 | u8 extended_response_flag; | |
258 | u8 reserved[3]; | |
92084715 | 259 | struct ext_report_lun_entry LUN[HPSA_MAX_PHYS_LUN]; |
edd16368 SC |
260 | }; |
261 | ||
262 | struct SenseSubsystem_info { | |
01a02ffc SC |
263 | u8 reserved[36]; |
264 | u8 portname[8]; | |
265 | u8 reserved1[1108]; | |
edd16368 SC |
266 | }; |
267 | ||
edd16368 SC |
268 | /* BMIC commands */ |
269 | #define BMIC_READ 0x26 | |
270 | #define BMIC_WRITE 0x27 | |
271 | #define BMIC_CACHE_FLUSH 0xc2 | |
272 | #define HPSA_CACHE_FLUSH 0x01 /* C2 was already being used by HPSA */ | |
e85c5974 | 273 | #define BMIC_FLASH_FIRMWARE 0xF7 |
316b221a | 274 | #define BMIC_SENSE_CONTROLLER_PARAMETERS 0x64 |
03383736 | 275 | #define BMIC_IDENTIFY_PHYSICAL_DEVICE 0x15 |
edd16368 SC |
276 | |
277 | /* Command List Structure */ | |
278 | union SCSI3Addr { | |
279 | struct { | |
01a02ffc SC |
280 | u8 Dev; |
281 | u8 Bus:6; | |
282 | u8 Mode:2; /* b00 */ | |
edd16368 SC |
283 | } PeripDev; |
284 | struct { | |
01a02ffc SC |
285 | u8 DevLSB; |
286 | u8 DevMSB:6; | |
287 | u8 Mode:2; /* b01 */ | |
edd16368 SC |
288 | } LogDev; |
289 | struct { | |
01a02ffc SC |
290 | u8 Dev:5; |
291 | u8 Bus:3; | |
292 | u8 Targ:6; | |
293 | u8 Mode:2; /* b10 */ | |
edd16368 SC |
294 | } LogUnit; |
295 | }; | |
296 | ||
297 | struct PhysDevAddr { | |
01a02ffc SC |
298 | u32 TargetId:24; |
299 | u32 Bus:6; | |
300 | u32 Mode:2; | |
edd16368 SC |
301 | /* 2 level target device addr */ |
302 | union SCSI3Addr Target[2]; | |
303 | }; | |
304 | ||
305 | struct LogDevAddr { | |
01a02ffc SC |
306 | u32 VolId:30; |
307 | u32 Mode:2; | |
308 | u8 reserved[4]; | |
edd16368 SC |
309 | }; |
310 | ||
311 | union LUNAddr { | |
01a02ffc | 312 | u8 LunAddrBytes[8]; |
edd16368 SC |
313 | union SCSI3Addr SCSI3Lun[4]; |
314 | struct PhysDevAddr PhysDev; | |
315 | struct LogDevAddr LogDev; | |
316 | }; | |
317 | ||
318 | struct CommandListHeader { | |
01a02ffc SC |
319 | u8 ReplyQueue; |
320 | u8 SGList; | |
2b08b3e9 DB |
321 | __le16 SGTotal; |
322 | __le64 tag; | |
edd16368 SC |
323 | union LUNAddr LUN; |
324 | }; | |
325 | ||
326 | struct RequestBlock { | |
01a02ffc | 327 | u8 CDBLen; |
a505b86f SC |
328 | /* |
329 | * type_attr_dir: | |
330 | * type: low 3 bits | |
331 | * attr: middle 3 bits | |
332 | * dir: high 2 bits | |
333 | */ | |
334 | u8 type_attr_dir; | |
335 | #define TYPE_ATTR_DIR(t, a, d) ((((d) & 0x03) << 6) |\ | |
336 | (((a) & 0x07) << 3) |\ | |
337 | ((t) & 0x07)) | |
338 | #define GET_TYPE(tad) ((tad) & 0x07) | |
339 | #define GET_ATTR(tad) (((tad) >> 3) & 0x07) | |
340 | #define GET_DIR(tad) (((tad) >> 6) & 0x03) | |
01a02ffc SC |
341 | u16 Timeout; |
342 | u8 CDB[16]; | |
edd16368 SC |
343 | }; |
344 | ||
345 | struct ErrDescriptor { | |
2b08b3e9 DB |
346 | __le64 Addr; |
347 | __le32 Len; | |
edd16368 SC |
348 | }; |
349 | ||
350 | struct SGDescriptor { | |
2b08b3e9 DB |
351 | __le64 Addr; |
352 | __le32 Len; | |
353 | __le32 Ext; | |
edd16368 SC |
354 | }; |
355 | ||
356 | union MoreErrInfo { | |
357 | struct { | |
01a02ffc SC |
358 | u8 Reserved[3]; |
359 | u8 Type; | |
360 | u32 ErrorInfo; | |
edd16368 SC |
361 | } Common_Info; |
362 | struct { | |
01a02ffc SC |
363 | u8 Reserved[2]; |
364 | u8 offense_size; /* size of offending entry */ | |
365 | u8 offense_num; /* byte # of offense 0-base */ | |
366 | u32 offense_value; | |
edd16368 SC |
367 | } Invalid_Cmd; |
368 | }; | |
369 | struct ErrorInfo { | |
01a02ffc SC |
370 | u8 ScsiStatus; |
371 | u8 SenseLen; | |
372 | u16 CommandStatus; | |
373 | u32 ResidualCnt; | |
edd16368 | 374 | union MoreErrInfo MoreErrInfo; |
01a02ffc | 375 | u8 SenseInfo[SENSEINFOBYTES]; |
edd16368 SC |
376 | }; |
377 | /* Command types */ | |
378 | #define CMD_IOCTL_PEND 0x01 | |
379 | #define CMD_SCSI 0x03 | |
e1f7de0c | 380 | #define CMD_IOACCEL1 0x04 |
b66cc250 | 381 | #define CMD_IOACCEL2 0x05 |
edd16368 | 382 | |
f2405db8 | 383 | #define DIRECT_LOOKUP_SHIFT 4 |
d896f3f3 | 384 | #define DIRECT_LOOKUP_MASK (~((1 << DIRECT_LOOKUP_SHIFT) - 1)) |
303932fd DB |
385 | |
386 | #define HPSA_ERROR_BIT 0x02 | |
edd16368 | 387 | struct ctlr_info; /* defined in hpsa.h */ |
f2405db8 DB |
388 | /* The size of this structure needs to be divisible by 128 |
389 | * on all architectures. The low 4 bits of the addresses | |
303932fd DB |
390 | * are used as follows: |
391 | * | |
392 | * bit 0: to device, used to indicate "performant mode" command | |
393 | * from device, indidcates error status. | |
394 | * bit 1-3: to device, indicates block fetch table entry for | |
395 | * reducing DMA in fetching commands from host memory. | |
edd16368 | 396 | */ |
303932fd | 397 | |
35d697c4 | 398 | #define COMMANDLIST_ALIGNMENT 128 |
edd16368 SC |
399 | struct CommandList { |
400 | struct CommandListHeader Header; | |
401 | struct RequestBlock Request; | |
402 | struct ErrDescriptor ErrDesc; | |
d66ae08b | 403 | struct SGDescriptor SG[SG_ENTRIES_IN_CMD]; |
edd16368 | 404 | /* information associated with the command */ |
01a02ffc | 405 | u32 busaddr; /* physical addr of this record */ |
edd16368 SC |
406 | struct ErrorInfo *err_info; /* pointer to the allocated mem */ |
407 | struct ctlr_info *h; | |
408 | int cmd_type; | |
409 | long cmdindex; | |
edd16368 | 410 | struct completion *waiting; |
7fa3030c | 411 | struct scsi_cmnd *scsi_cmd; |
080ef1cc | 412 | struct work_struct work; |
03383736 DB |
413 | |
414 | /* | |
415 | * For commands using either of the two "ioaccel" paths to | |
416 | * bypass the RAID stack and go directly to the physical disk | |
417 | * phys_disk is a pointer to the hpsa_scsi_dev_t to which the | |
418 | * i/o is destined. We need to store that here because the command | |
419 | * may potentially encounter TASK SET FULL and need to be resubmitted | |
420 | * For "normal" i/o's not using the "ioaccel" paths, phys_disk is | |
421 | * not used. | |
422 | */ | |
423 | struct hpsa_scsi_dev_t *phys_disk; | |
281a7fd0 | 424 | atomic_t refcount; /* Must be last to avoid memset in cmd_alloc */ |
35d697c4 | 425 | } __aligned(COMMANDLIST_ALIGNMENT); |
edd16368 | 426 | |
e1f7de0c MG |
427 | /* Max S/G elements in I/O accelerator command */ |
428 | #define IOACCEL1_MAXSGENTRIES 24 | |
b66cc250 | 429 | #define IOACCEL2_MAXSGENTRIES 28 |
e1f7de0c MG |
430 | |
431 | /* | |
432 | * Structure for I/O accelerator (mode 1) commands. | |
433 | * Note that this structure must be 128-byte aligned in size. | |
434 | */ | |
35d697c4 | 435 | #define IOACCEL1_COMMANDLIST_ALIGNMENT 128 |
e1f7de0c | 436 | struct io_accel1_cmd { |
2b08b3e9 | 437 | __le16 dev_handle; /* 0x00 - 0x01 */ |
e1f7de0c MG |
438 | u8 reserved1; /* 0x02 */ |
439 | u8 function; /* 0x03 */ | |
440 | u8 reserved2[8]; /* 0x04 - 0x0B */ | |
441 | u32 err_info; /* 0x0C - 0x0F */ | |
442 | u8 reserved3[2]; /* 0x10 - 0x11 */ | |
443 | u8 err_info_len; /* 0x12 */ | |
444 | u8 reserved4; /* 0x13 */ | |
445 | u8 sgl_offset; /* 0x14 */ | |
446 | u8 reserved5[7]; /* 0x15 - 0x1B */ | |
2b08b3e9 | 447 | __le32 transfer_len; /* 0x1C - 0x1F */ |
e1f7de0c | 448 | u8 reserved6[4]; /* 0x20 - 0x23 */ |
2b08b3e9 | 449 | __le16 io_flags; /* 0x24 - 0x25 */ |
e1f7de0c MG |
450 | u8 reserved7[14]; /* 0x26 - 0x33 */ |
451 | u8 LUN[8]; /* 0x34 - 0x3B */ | |
2b08b3e9 | 452 | __le32 control; /* 0x3C - 0x3F */ |
e1f7de0c MG |
453 | u8 CDB[16]; /* 0x40 - 0x4F */ |
454 | u8 reserved8[16]; /* 0x50 - 0x5F */ | |
2b08b3e9 DB |
455 | __le16 host_context_flags; /* 0x60 - 0x61 */ |
456 | __le16 timeout_sec; /* 0x62 - 0x63 */ | |
e1f7de0c MG |
457 | u8 ReplyQueue; /* 0x64 */ |
458 | u8 reserved9[3]; /* 0x65 - 0x67 */ | |
2b08b3e9 DB |
459 | __le64 tag; /* 0x68 - 0x6F */ |
460 | __le64 host_addr; /* 0x70 - 0x77 */ | |
e1f7de0c MG |
461 | u8 CISS_LUN[8]; /* 0x78 - 0x7F */ |
462 | struct SGDescriptor SG[IOACCEL1_MAXSGENTRIES]; | |
35d697c4 | 463 | } __aligned(IOACCEL1_COMMANDLIST_ALIGNMENT); |
e1f7de0c MG |
464 | |
465 | #define IOACCEL1_FUNCTION_SCSIIO 0x00 | |
466 | #define IOACCEL1_SGLOFFSET 32 | |
467 | ||
468 | #define IOACCEL1_IOFLAGS_IO_REQ 0x4000 | |
469 | #define IOACCEL1_IOFLAGS_CDBLEN_MASK 0x001F | |
470 | #define IOACCEL1_IOFLAGS_CDBLEN_MAX 16 | |
471 | ||
472 | #define IOACCEL1_CONTROL_NODATAXFER 0x00000000 | |
473 | #define IOACCEL1_CONTROL_DATA_OUT 0x01000000 | |
474 | #define IOACCEL1_CONTROL_DATA_IN 0x02000000 | |
475 | #define IOACCEL1_CONTROL_TASKPRIO_MASK 0x00007800 | |
476 | #define IOACCEL1_CONTROL_TASKPRIO_SHIFT 11 | |
477 | #define IOACCEL1_CONTROL_SIMPLEQUEUE 0x00000000 | |
478 | #define IOACCEL1_CONTROL_HEADOFQUEUE 0x00000100 | |
479 | #define IOACCEL1_CONTROL_ORDEREDQUEUE 0x00000200 | |
480 | #define IOACCEL1_CONTROL_ACA 0x00000400 | |
481 | ||
482 | #define IOACCEL1_HCFLAGS_CISS_FORMAT 0x0013 | |
483 | ||
484 | #define IOACCEL1_BUSADDR_CMDTYPE 0x00000060 | |
485 | ||
b66cc250 | 486 | struct ioaccel2_sg_element { |
2b08b3e9 DB |
487 | __le64 address; |
488 | __le32 length; | |
b66cc250 MM |
489 | u8 reserved[3]; |
490 | u8 chain_indicator; | |
491 | #define IOACCEL2_CHAIN 0x80 | |
492 | }; | |
493 | ||
494 | /* | |
495 | * SCSI Response Format structure for IO Accelerator Mode 2 | |
496 | */ | |
497 | struct io_accel2_scsi_response { | |
498 | u8 IU_type; | |
499 | #define IOACCEL2_IU_TYPE_SRF 0x60 | |
500 | u8 reserved1[3]; | |
501 | u8 req_id[4]; /* request identifier */ | |
502 | u8 reserved2[4]; | |
503 | u8 serv_response; /* service response */ | |
504 | #define IOACCEL2_SERV_RESPONSE_COMPLETE 0x000 | |
505 | #define IOACCEL2_SERV_RESPONSE_FAILURE 0x001 | |
506 | #define IOACCEL2_SERV_RESPONSE_TMF_COMPLETE 0x002 | |
507 | #define IOACCEL2_SERV_RESPONSE_TMF_SUCCESS 0x003 | |
508 | #define IOACCEL2_SERV_RESPONSE_TMF_REJECTED 0x004 | |
509 | #define IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN 0x005 | |
510 | u8 status; /* status */ | |
511 | #define IOACCEL2_STATUS_SR_TASK_COMP_GOOD 0x00 | |
512 | #define IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND 0x02 | |
513 | #define IOACCEL2_STATUS_SR_TASK_COMP_BUSY 0x08 | |
514 | #define IOACCEL2_STATUS_SR_TASK_COMP_RES_CON 0x18 | |
515 | #define IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL 0x28 | |
516 | #define IOACCEL2_STATUS_SR_TASK_COMP_ABORTED 0x40 | |
c349775e | 517 | #define IOACCEL2_STATUS_SR_IOACCEL_DISABLED 0x0E |
b66cc250 MM |
518 | u8 data_present; /* low 2 bits */ |
519 | #define IOACCEL2_NO_DATAPRESENT 0x000 | |
520 | #define IOACCEL2_RESPONSE_DATAPRESENT 0x001 | |
521 | #define IOACCEL2_SENSE_DATA_PRESENT 0x002 | |
522 | #define IOACCEL2_RESERVED 0x003 | |
523 | u8 sense_data_len; /* sense/response data length */ | |
524 | u8 resid_cnt[4]; /* residual count */ | |
525 | u8 sense_data_buff[32]; /* sense/response data buffer */ | |
526 | }; | |
527 | ||
b66cc250 MM |
528 | /* |
529 | * Structure for I/O accelerator (mode 2 or m2) commands. | |
530 | * Note that this structure must be 128-byte aligned in size. | |
531 | */ | |
35d697c4 | 532 | #define IOACCEL2_COMMANDLIST_ALIGNMENT 128 |
b66cc250 MM |
533 | struct io_accel2_cmd { |
534 | u8 IU_type; /* IU Type */ | |
dd0e19f3 ST |
535 | u8 direction; /* direction, memtype, and encryption */ |
536 | #define IOACCEL2_DIRECTION_MASK 0x03 /* bits 0,1: direction */ | |
537 | #define IOACCEL2_DIRECTION_MEMTYPE_MASK 0x04 /* bit 2: memtype source/dest */ | |
538 | /* 0b=PCIe, 1b=DDR */ | |
539 | #define IOACCEL2_DIRECTION_ENCRYPT_MASK 0x08 /* bit 3: encryption flag */ | |
540 | /* 0=off, 1=on */ | |
b66cc250 MM |
541 | u8 reply_queue; /* Reply Queue ID */ |
542 | u8 reserved1; /* Reserved */ | |
2b08b3e9 DB |
543 | __le32 scsi_nexus; /* Device Handle */ |
544 | __le32 Tag; /* cciss tag, lower 4 bytes only */ | |
545 | __le32 tweak_lower; /* Encryption tweak, lower 4 bytes */ | |
b66cc250 MM |
546 | u8 cdb[16]; /* SCSI Command Descriptor Block */ |
547 | u8 cciss_lun[8]; /* 8 byte SCSI address */ | |
2b08b3e9 | 548 | __le32 data_len; /* Total bytes to transfer */ |
b66cc250 MM |
549 | u8 cmd_priority_task_attr; /* priority and task attrs */ |
550 | #define IOACCEL2_PRIORITY_MASK 0x78 | |
551 | #define IOACCEL2_ATTR_MASK 0x07 | |
552 | u8 sg_count; /* Number of sg elements */ | |
2b08b3e9 DB |
553 | __le16 dekindex; /* Data encryption key index */ |
554 | __le64 err_ptr; /* Error Pointer */ | |
555 | __le32 err_len; /* Error Length*/ | |
556 | __le32 tweak_upper; /* Encryption tweak, upper 4 bytes */ | |
b66cc250 MM |
557 | struct ioaccel2_sg_element sg[IOACCEL2_MAXSGENTRIES]; |
558 | struct io_accel2_scsi_response error_data; | |
35d697c4 | 559 | } __aligned(IOACCEL2_COMMANDLIST_ALIGNMENT); |
b66cc250 MM |
560 | |
561 | /* | |
562 | * defines for Mode 2 command struct | |
563 | * FIXME: this can't be all I need mfm | |
564 | */ | |
565 | #define IOACCEL2_IU_TYPE 0x40 | |
54b6e9e9 | 566 | #define IOACCEL2_IU_TMF_TYPE 0x41 |
b66cc250 MM |
567 | #define IOACCEL2_DIR_NO_DATA 0x00 |
568 | #define IOACCEL2_DIR_DATA_IN 0x01 | |
569 | #define IOACCEL2_DIR_DATA_OUT 0x02 | |
570 | /* | |
571 | * SCSI Task Management Request format for Accelerator Mode 2 | |
572 | */ | |
573 | struct hpsa_tmf_struct { | |
574 | u8 iu_type; /* Information Unit Type */ | |
575 | u8 reply_queue; /* Reply Queue ID */ | |
576 | u8 tmf; /* Task Management Function */ | |
577 | u8 reserved1; /* byte 3 Reserved */ | |
578 | u32 it_nexus; /* SCSI I-T Nexus */ | |
579 | u8 lun_id[8]; /* LUN ID for TMF request */ | |
2b08b3e9 DB |
580 | __le64 tag; /* cciss tag associated w/ request */ |
581 | __le64 abort_tag; /* cciss tag of SCSI cmd or TMF to abort */ | |
582 | __le64 error_ptr; /* Error Pointer */ | |
583 | __le32 error_len; /* Error Length */ | |
b66cc250 MM |
584 | }; |
585 | ||
edd16368 SC |
586 | /* Configuration Table Structure */ |
587 | struct HostWrite { | |
2b08b3e9 DB |
588 | __le32 TransportRequest; |
589 | __le32 command_pool_addr_hi; | |
590 | __le32 CoalIntDelay; | |
591 | __le32 CoalIntCount; | |
edd16368 SC |
592 | }; |
593 | ||
303932fd DB |
594 | #define SIMPLE_MODE 0x02 |
595 | #define PERFORMANT_MODE 0x04 | |
596 | #define MEMQ_MODE 0x08 | |
e1f7de0c | 597 | #define IOACCEL_MODE_1 0x80 |
303932fd | 598 | |
283b4a9b SC |
599 | #define DRIVER_SUPPORT_UA_ENABLE 0x00000001 |
600 | ||
edd16368 | 601 | struct CfgTable { |
2b08b3e9 DB |
602 | u8 Signature[4]; |
603 | __le32 SpecValence; | |
604 | __le32 TransportSupport; | |
605 | __le32 TransportActive; | |
606 | struct HostWrite HostWrite; | |
607 | __le32 CmdsOutMax; | |
608 | __le32 BusTypes; | |
609 | __le32 TransMethodOffset; | |
610 | u8 ServerName[16]; | |
611 | __le32 HeartBeat; | |
612 | __le32 driver_support; | |
613 | #define ENABLE_SCSI_PREFETCH 0x100 | |
614 | #define ENABLE_UNIT_ATTN 0x01 | |
615 | __le32 MaxScatterGatherElements; | |
616 | __le32 MaxLogicalUnits; | |
617 | __le32 MaxPhysicalDevices; | |
618 | __le32 MaxPhysicalDrivesPerLogicalUnit; | |
619 | __le32 MaxPerformantModeCommands; | |
620 | __le32 MaxBlockFetch; | |
621 | __le32 PowerConservationSupport; | |
622 | __le32 PowerConservationEnable; | |
623 | __le32 TMFSupportFlags; | |
75167d2c SC |
624 | u8 TMFTagMask[8]; |
625 | u8 reserved[0x78 - 0x70]; | |
2b08b3e9 DB |
626 | __le32 misc_fw_support; /* offset 0x78 */ |
627 | #define MISC_FW_DOORBELL_RESET 0x02 | |
628 | #define MISC_FW_DOORBELL_RESET2 0x010 | |
629 | #define MISC_FW_RAID_OFFLOAD_BASIC 0x020 | |
630 | #define MISC_FW_EVENT_NOTIFY 0x080 | |
580ada3c | 631 | u8 driver_version[32]; |
2b08b3e9 DB |
632 | __le32 max_cached_write_size; |
633 | u8 driver_scratchpad[16]; | |
634 | __le32 max_error_info_length; | |
635 | __le32 io_accel_max_embedded_sg_count; | |
636 | __le32 io_accel_request_size_offset; | |
637 | __le32 event_notify; | |
638 | #define HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE (1 << 30) | |
639 | #define HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE (1 << 31) | |
640 | __le32 clear_event_notify; | |
303932fd DB |
641 | }; |
642 | ||
643 | #define NUM_BLOCKFETCH_ENTRIES 8 | |
644 | struct TransTable_struct { | |
2b08b3e9 DB |
645 | __le32 BlockFetch[NUM_BLOCKFETCH_ENTRIES]; |
646 | __le32 RepQSize; | |
647 | __le32 RepQCount; | |
648 | __le32 RepQCtrAddrLow32; | |
649 | __le32 RepQCtrAddrHigh32; | |
f89439bc | 650 | #define MAX_REPLY_QUEUES 64 |
254f796b | 651 | struct vals32 RepQAddr[MAX_REPLY_QUEUES]; |
edd16368 SC |
652 | }; |
653 | ||
654 | struct hpsa_pci_info { | |
655 | unsigned char bus; | |
656 | unsigned char dev_fn; | |
657 | unsigned short domain; | |
01a02ffc | 658 | u32 board_id; |
edd16368 SC |
659 | }; |
660 | ||
03383736 DB |
661 | struct bmic_identify_physical_device { |
662 | u8 scsi_bus; /* SCSI Bus number on controller */ | |
663 | u8 scsi_id; /* SCSI ID on this bus */ | |
664 | __le16 block_size; /* sector size in bytes */ | |
665 | __le32 total_blocks; /* number for sectors on drive */ | |
666 | __le32 reserved_blocks; /* controller reserved (RIS) */ | |
667 | u8 model[40]; /* Physical Drive Model */ | |
668 | u8 serial_number[40]; /* Drive Serial Number */ | |
669 | u8 firmware_revision[8]; /* drive firmware revision */ | |
670 | u8 scsi_inquiry_bits; /* inquiry byte 7 bits */ | |
671 | u8 compaq_drive_stamp; /* 0 means drive not stamped */ | |
672 | u8 last_failure_reason; | |
673 | #define BMIC_LAST_FAILURE_TOO_SMALL_IN_LOAD_CONFIG 0x01 | |
674 | #define BMIC_LAST_FAILURE_ERROR_ERASING_RIS 0x02 | |
675 | #define BMIC_LAST_FAILURE_ERROR_SAVING_RIS 0x03 | |
676 | #define BMIC_LAST_FAILURE_FAIL_DRIVE_COMMAND 0x04 | |
677 | #define BMIC_LAST_FAILURE_MARK_BAD_FAILED 0x05 | |
678 | #define BMIC_LAST_FAILURE_MARK_BAD_FAILED_IN_FINISH_REMAP 0x06 | |
679 | #define BMIC_LAST_FAILURE_TIMEOUT 0x07 | |
680 | #define BMIC_LAST_FAILURE_AUTOSENSE_FAILED 0x08 | |
681 | #define BMIC_LAST_FAILURE_MEDIUM_ERROR_1 0x09 | |
682 | #define BMIC_LAST_FAILURE_MEDIUM_ERROR_2 0x0a | |
683 | #define BMIC_LAST_FAILURE_NOT_READY_BAD_SENSE 0x0b | |
684 | #define BMIC_LAST_FAILURE_NOT_READY 0x0c | |
685 | #define BMIC_LAST_FAILURE_HARDWARE_ERROR 0x0d | |
686 | #define BMIC_LAST_FAILURE_ABORTED_COMMAND 0x0e | |
687 | #define BMIC_LAST_FAILURE_WRITE_PROTECTED 0x0f | |
688 | #define BMIC_LAST_FAILURE_SPIN_UP_FAILURE_IN_RECOVER 0x10 | |
689 | #define BMIC_LAST_FAILURE_REBUILD_WRITE_ERROR 0x11 | |
690 | #define BMIC_LAST_FAILURE_TOO_SMALL_IN_HOT_PLUG 0x12 | |
691 | #define BMIC_LAST_FAILURE_BUS_RESET_RECOVERY_ABORTED 0x13 | |
692 | #define BMIC_LAST_FAILURE_REMOVED_IN_HOT_PLUG 0x14 | |
693 | #define BMIC_LAST_FAILURE_INIT_REQUEST_SENSE_FAILED 0x15 | |
694 | #define BMIC_LAST_FAILURE_INIT_START_UNIT_FAILED 0x16 | |
695 | #define BMIC_LAST_FAILURE_INQUIRY_FAILED 0x17 | |
696 | #define BMIC_LAST_FAILURE_NON_DISK_DEVICE 0x18 | |
697 | #define BMIC_LAST_FAILURE_READ_CAPACITY_FAILED 0x19 | |
698 | #define BMIC_LAST_FAILURE_INVALID_BLOCK_SIZE 0x1a | |
699 | #define BMIC_LAST_FAILURE_HOT_PLUG_REQUEST_SENSE_FAILED 0x1b | |
700 | #define BMIC_LAST_FAILURE_HOT_PLUG_START_UNIT_FAILED 0x1c | |
701 | #define BMIC_LAST_FAILURE_WRITE_ERROR_AFTER_REMAP 0x1d | |
702 | #define BMIC_LAST_FAILURE_INIT_RESET_RECOVERY_ABORTED 0x1e | |
703 | #define BMIC_LAST_FAILURE_DEFERRED_WRITE_ERROR 0x1f | |
704 | #define BMIC_LAST_FAILURE_MISSING_IN_SAVE_RIS 0x20 | |
705 | #define BMIC_LAST_FAILURE_WRONG_REPLACE 0x21 | |
706 | #define BMIC_LAST_FAILURE_GDP_VPD_INQUIRY_FAILED 0x22 | |
707 | #define BMIC_LAST_FAILURE_GDP_MODE_SENSE_FAILED 0x23 | |
708 | #define BMIC_LAST_FAILURE_DRIVE_NOT_IN_48BIT_MODE 0x24 | |
709 | #define BMIC_LAST_FAILURE_DRIVE_TYPE_MIX_IN_HOT_PLUG 0x25 | |
710 | #define BMIC_LAST_FAILURE_DRIVE_TYPE_MIX_IN_LOAD_CFG 0x26 | |
711 | #define BMIC_LAST_FAILURE_PROTOCOL_ADAPTER_FAILED 0x27 | |
712 | #define BMIC_LAST_FAILURE_FAULTY_ID_BAY_EMPTY 0x28 | |
713 | #define BMIC_LAST_FAILURE_FAULTY_ID_BAY_OCCUPIED 0x29 | |
714 | #define BMIC_LAST_FAILURE_FAULTY_ID_INVALID_BAY 0x2a | |
715 | #define BMIC_LAST_FAILURE_WRITE_RETRIES_FAILED 0x2b | |
716 | ||
717 | #define BMIC_LAST_FAILURE_SMART_ERROR_REPORTED 0x37 | |
718 | #define BMIC_LAST_FAILURE_PHY_RESET_FAILED 0x38 | |
719 | #define BMIC_LAST_FAILURE_ONLY_ONE_CTLR_CAN_SEE_DRIVE 0x40 | |
720 | #define BMIC_LAST_FAILURE_KC_VOLUME_FAILED 0x41 | |
721 | #define BMIC_LAST_FAILURE_UNEXPECTED_REPLACEMENT 0x42 | |
722 | #define BMIC_LAST_FAILURE_OFFLINE_ERASE 0x80 | |
723 | #define BMIC_LAST_FAILURE_OFFLINE_TOO_SMALL 0x81 | |
724 | #define BMIC_LAST_FAILURE_OFFLINE_DRIVE_TYPE_MIX 0x82 | |
725 | #define BMIC_LAST_FAILURE_OFFLINE_ERASE_COMPLETE 0x83 | |
726 | ||
727 | u8 flags; | |
728 | u8 more_flags; | |
729 | u8 scsi_lun; /* SCSI LUN for phys drive */ | |
730 | u8 yet_more_flags; | |
731 | u8 even_more_flags; | |
732 | __le32 spi_speed_rules;/* SPI Speed data:Ultra disable diagnose */ | |
733 | u8 phys_connector[2]; /* connector number on controller */ | |
734 | u8 phys_box_on_bus; /* phys enclosure this drive resides */ | |
735 | u8 phys_bay_in_box; /* phys drv bay this drive resides */ | |
736 | __le32 rpm; /* Drive rotational speed in rpm */ | |
737 | u8 device_type; /* type of drive */ | |
738 | u8 sata_version; /* only valid when drive_type is SATA */ | |
739 | __le64 big_total_block_count; | |
740 | __le64 ris_starting_lba; | |
741 | __le32 ris_size; | |
742 | u8 wwid[20]; | |
743 | u8 controller_phy_map[32]; | |
744 | __le16 phy_count; | |
745 | u8 phy_connected_dev_type[256]; | |
746 | u8 phy_to_drive_bay_num[256]; | |
747 | __le16 phy_to_attached_dev_index[256]; | |
748 | u8 box_index; | |
749 | u8 reserved; | |
750 | __le16 extra_physical_drive_flags; | |
751 | #define BMIC_PHYS_DRIVE_SUPPORTS_GAS_GAUGE(idphydrv) \ | |
752 | (idphydrv->extra_physical_drive_flags & (1 << 10)) | |
753 | u8 negotiated_link_rate[256]; | |
754 | u8 phy_to_phy_map[256]; | |
755 | u8 redundant_path_present_map; | |
756 | u8 redundant_path_failure_map; | |
757 | u8 active_path_number; | |
758 | __le16 alternate_paths_phys_connector[8]; | |
759 | u8 alternate_paths_phys_box_on_port[8]; | |
760 | u8 multi_lun_device_lun_count; | |
761 | u8 minimum_good_fw_revision[8]; | |
762 | u8 unique_inquiry_bytes[20]; | |
763 | u8 current_temperature_degreesC; | |
764 | u8 temperature_threshold_degreesC; | |
765 | u8 max_temperature_degreesC; | |
766 | u8 logical_blocks_per_phys_block_exp; /* phyblocksize = 512*2^exp */ | |
767 | __le16 current_queue_depth_limit; | |
768 | u8 switch_name[10]; | |
769 | __le16 switch_port; | |
770 | u8 alternate_paths_switch_name[40]; | |
771 | u8 alternate_paths_switch_port[8]; | |
772 | __le16 power_on_hours; /* valid only if gas gauge supported */ | |
773 | __le16 percent_endurance_used; /* valid only if gas gauge supported. */ | |
774 | #define BMIC_PHYS_DRIVE_SSD_WEAROUT(idphydrv) \ | |
775 | ((idphydrv->percent_endurance_used & 0x80) || \ | |
776 | (idphydrv->percent_endurance_used > 10000)) | |
777 | u8 drive_authentication; | |
778 | #define BMIC_PHYS_DRIVE_AUTHENTICATED(idphydrv) \ | |
779 | (idphydrv->drive_authentication == 0x80) | |
780 | u8 smart_carrier_authentication; | |
781 | #define BMIC_SMART_CARRIER_AUTHENTICATION_SUPPORTED(idphydrv) \ | |
782 | (idphydrv->smart_carrier_authentication != 0x0) | |
783 | #define BMIC_SMART_CARRIER_AUTHENTICATED(idphydrv) \ | |
784 | (idphydrv->smart_carrier_authentication == 0x01) | |
785 | u8 smart_carrier_app_fw_version; | |
786 | u8 smart_carrier_bootloader_fw_version; | |
787 | u8 encryption_key_name[64]; | |
788 | __le32 misc_drive_flags; | |
789 | __le16 dek_index; | |
790 | u8 padding[112]; | |
791 | }; | |
792 | ||
edd16368 SC |
793 | #pragma pack() |
794 | #endif /* HPSA_CMD_H */ |