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[SCSI] mvsas: fix potential NULL dereference
[deliverable/linux.git] / drivers / scsi / ipr.h
CommitLineData
1da177e4
LT		 1/*
2 * ipr.h -- driver for IBM Power Linux RAID adapters
3 *
4 * Written By: Brian King <brking@us.ibm.com>, IBM Corporation
5 *
6 * Copyright (C) 2003, 2004 IBM Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
fa195afe 22 * Alan Cox <alan@lxorguk.ukuu.org.uk> - Removed several careless u32/dma_addr_t errors
1da177e4
LT		 23 * that broke 64bit platforms.
24 */
25
26#ifndef _IPR_H
27#define _IPR_H
28
29#include <linux/types.h>
30#include <linux/completion.h>
35a39691 31#include <linux/libata.h>
1da177e4
LT		 32#include <linux/list.h>
33#include <linux/kref.h>
34#include <scsi/scsi.h>
35#include <scsi/scsi_cmnd.h>
36
37/*
38 * Literals
39 */
d7b4627f
WB		 40#define IPR_DRIVER_VERSION "2.5.0"
41#define IPR_DRIVER_DATE "(February 11, 2010)"
1da177e4 42
1da177e4
LT		 43/*
44 * IPR_MAX_CMD_PER_LUN: This defines the maximum number of outstanding
45 * ops per device for devices not running tagged command queuing.
46 * This can be adjusted at runtime through sysfs device attributes.
47 */
48#define IPR_MAX_CMD_PER_LUN 6
b5145d25 49#define IPR_MAX_CMD_PER_ATA_LUN 1
1da177e4
LT		 50
51/*
52 * IPR_NUM_BASE_CMD_BLKS: This defines the maximum number of
53 * ops the mid-layer can send to the adapter.
54 */
55#define IPR_NUM_BASE_CMD_BLKS 100
56
60e7486b 57#define PCI_DEVICE_ID_IBM_OBSIDIAN_E 0x0339
d7b4627f
WB		 58
59#define PCI_DEVICE_ID_IBM_CROC_FPGA_E2 0x033D
60#define PCI_DEVICE_ID_IBM_CROC_ASIC_E2 0x034A
60e7486b 61
1da177e4
LT		 62#define IPR_SUBS_DEV_ID_2780 0x0264
63#define IPR_SUBS_DEV_ID_5702 0x0266
64#define IPR_SUBS_DEV_ID_5703 0x0278
65#define IPR_SUBS_DEV_ID_572E 0x028D
66#define IPR_SUBS_DEV_ID_573E 0x02D3
67#define IPR_SUBS_DEV_ID_573D 0x02D4
68#define IPR_SUBS_DEV_ID_571A 0x02C0
69#define IPR_SUBS_DEV_ID_571B 0x02BE
70#define IPR_SUBS_DEV_ID_571E 0x02BF
86f51436 71#define IPR_SUBS_DEV_ID_571F 0x02D5
72#define IPR_SUBS_DEV_ID_572A 0x02C1
73#define IPR_SUBS_DEV_ID_572B 0x02C2
60e7486b 74#define IPR_SUBS_DEV_ID_572F 0x02C3
185eb31c 75#define IPR_SUBS_DEV_ID_574E 0x030A
86f51436 76#define IPR_SUBS_DEV_ID_575B 0x030D
60e7486b 77#define IPR_SUBS_DEV_ID_575C 0x0338
185eb31c 78#define IPR_SUBS_DEV_ID_57B3 0x033A
60e7486b
BK		 79#define IPR_SUBS_DEV_ID_57B7 0x0360
80#define IPR_SUBS_DEV_ID_57B8 0x02C2
1da177e4 81
d7b4627f
WB		 82#define IPR_SUBS_DEV_ID_57B4 0x033B
83#define IPR_SUBS_DEV_ID_57B2 0x035F
84#define IPR_SUBS_DEV_ID_57C6 0x0357
85
86#define IPR_SUBS_DEV_ID_57B5 0x033C
87#define IPR_SUBS_DEV_ID_57CE 0x035E
88#define IPR_SUBS_DEV_ID_57B1 0x0355
89
90#define IPR_SUBS_DEV_ID_574D 0x0356
91#define IPR_SUBS_DEV_ID_575D 0x035D
92
1da177e4
LT		 93#define IPR_NAME "ipr"
94
95/*
96 * Return codes
97 */
98#define IPR_RC_JOB_CONTINUE 1
99#define IPR_RC_JOB_RETURN 2
100
101/*
102 * IOASCs
103 */
104#define IPR_IOASC_NR_INIT_CMD_REQUIRED 0x02040200
65f56475 105#define IPR_IOASC_NR_IOA_RESET_REQUIRED 0x02048000
1da177e4
LT		 106#define IPR_IOASC_SYNC_REQUIRED 0x023f0000
107#define IPR_IOASC_MED_DO_NOT_REALLOC 0x03110C00
108#define IPR_IOASC_HW_SEL_TIMEOUT 0x04050000
109#define IPR_IOASC_HW_DEV_BUS_STATUS 0x04448500
110#define IPR_IOASC_IOASC_MASK 0xFFFFFF00
111#define IPR_IOASC_SCSI_STATUS_MASK 0x000000FF
dfed823e 112#define IPR_IOASC_IR_INVALID_REQ_TYPE_OR_PKT 0x05240000
1da177e4 113#define IPR_IOASC_IR_RESOURCE_HANDLE 0x05250000
b0df54bb 114#define IPR_IOASC_IR_NO_CMDS_TO_2ND_IOA 0x05258100
115#define IPR_IOASA_IR_DUAL_IOA_DISABLED 0x052C8000
1da177e4
LT		 116#define IPR_IOASC_BUS_WAS_RESET 0x06290000
117#define IPR_IOASC_BUS_WAS_RESET_BY_OTHER 0x06298000
118#define IPR_IOASC_ABORTED_CMD_TERM_BY_HOST 0x0B5A0000
119
120#define IPR_FIRST_DRIVER_IOASC 0x10000000
121#define IPR_IOASC_IOA_WAS_RESET 0x10000001
122#define IPR_IOASC_PCI_ACCESS_ERROR 0x10000002
123
5469cb5b
BK		 124/* Driver data flags */
125#define IPR_USE_LONG_TRANSOP_TIMEOUT 0x00000001
463fc696 126#define IPR_USE_PCI_WARM_RESET 0x00000002
5469cb5b 127
ac719aba 128#define IPR_DEFAULT_MAX_ERROR_DUMP 984
1da177e4
LT		 129#define IPR_NUM_LOG_HCAMS 2
130#define IPR_NUM_CFG_CHG_HCAMS 2
131#define IPR_NUM_HCAMS (IPR_NUM_LOG_HCAMS + IPR_NUM_CFG_CHG_HCAMS)
3e7ebdfa
WB		 132
133#define IPR_MAX_SIS64_TARGETS_PER_BUS 1024
134#define IPR_MAX_SIS64_LUNS_PER_TARGET 0xffffffff
135
d71a8b0c 136#define IPR_MAX_NUM_TARGETS_PER_BUS 256
1da177e4
LT		 137#define IPR_MAX_NUM_LUNS_PER_TARGET 256
138#define IPR_MAX_NUM_VSET_LUNS_PER_TARGET 8
139#define IPR_VSET_BUS 0xff
140#define IPR_IOA_BUS 0xff
141#define IPR_IOA_TARGET 0xff
142#define IPR_IOA_LUN 0xff
b5145d25 143#define IPR_MAX_NUM_BUSES 16
1da177e4
LT		 144#define IPR_MAX_BUS_TO_SCAN IPR_MAX_NUM_BUSES
145
146#define IPR_NUM_RESET_RELOAD_RETRIES 3
147
148/* We need resources for HCAMS, IOA reset, IOA bringdown, and ERP */
149#define IPR_NUM_INTERNAL_CMD_BLKS (IPR_NUM_HCAMS + \
f72919ec 150 ((IPR_NUM_RESET_RELOAD_RETRIES + 1) * 2) + 4)
1da177e4
LT		 151
152#define IPR_MAX_COMMANDS IPR_NUM_BASE_CMD_BLKS
153#define IPR_NUM_CMD_BLKS (IPR_NUM_BASE_CMD_BLKS + \
154 IPR_NUM_INTERNAL_CMD_BLKS)
155
156#define IPR_MAX_PHYSICAL_DEVS 192
3e7ebdfa
WB		 157#define IPR_DEFAULT_SIS64_DEVS 1024
158#define IPR_MAX_SIS64_DEVS 4096
1da177e4
LT		 159
160#define IPR_MAX_SGLIST 64
161#define IPR_IOA_MAX_SECTORS 32767
162#define IPR_VSET_MAX_SECTORS 512
163#define IPR_MAX_CDB_LEN 16
3feeb89d 164#define IPR_MAX_HRRQ_RETRIES 3
1da177e4
LT		 165
166#define IPR_DEFAULT_BUS_WIDTH 16
167#define IPR_80MBs_SCSI_RATE ((80 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
168#define IPR_U160_SCSI_RATE ((160 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
169#define IPR_U320_SCSI_RATE ((320 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
170#define IPR_MAX_SCSI_RATE(width) ((320 * 10) / ((width) / 8))
171
172#define IPR_IOA_RES_HANDLE 0xffffffff
1121b794 173#define IPR_INVALID_RES_HANDLE 0
1da177e4
LT		 174#define IPR_IOA_RES_ADDR 0x00ffffff
175
176/*
177 * Adapter Commands
178 */
179#define IPR_QUERY_RSRC_STATE 0xC2
180#define IPR_RESET_DEVICE 0xC3
181#define IPR_RESET_TYPE_SELECT 0x80
182#define IPR_LUN_RESET 0x40
183#define IPR_TARGET_RESET 0x20
184#define IPR_BUS_RESET 0x10
b5145d25 185#define IPR_ATA_PHY_RESET 0x80
1da177e4
LT		 186#define IPR_ID_HOST_RR_Q 0xC4
187#define IPR_QUERY_IOA_CONFIG 0xC5
188#define IPR_CANCEL_ALL_REQUESTS 0xCE
189#define IPR_HOST_CONTROLLED_ASYNC 0xCF
190#define IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE 0x01
191#define IPR_HCAM_CDB_OP_CODE_LOG_DATA 0x02
192#define IPR_SET_SUPPORTED_DEVICES 0xFB
3e7ebdfa 193#define IPR_SET_ALL_SUPPORTED_DEVICES 0x80
1da177e4
LT		 194#define IPR_IOA_SHUTDOWN 0xF7
195#define IPR_WR_BUF_DOWNLOAD_AND_SAVE 0x05
196
197/*
198 * Timeouts
199 */
200#define IPR_SHUTDOWN_TIMEOUT (ipr_fastfail ? 60 * HZ : 10 * 60 * HZ)
201#define IPR_VSET_RW_TIMEOUT (ipr_fastfail ? 30 * HZ : 2 * 60 * HZ)
202#define IPR_ABBREV_SHUTDOWN_TIMEOUT (10 * HZ)
ac09c349 203#define IPR_DUAL_IOA_ABBR_SHUTDOWN_TO (2 * 60 * HZ)
1da177e4
LT		 204#define IPR_DEVICE_RESET_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
205#define IPR_CANCEL_ALL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
206#define IPR_ABORT_TASK_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
207#define IPR_INTERNAL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
208#define IPR_WRITE_BUFFER_TIMEOUT (10 * 60 * HZ)
209#define IPR_SET_SUP_DEVICE_TIMEOUT (2 * 60 * HZ)
210#define IPR_REQUEST_SENSE_TIMEOUT (10 * HZ)
211#define IPR_OPERATIONAL_TIMEOUT (5 * 60)
5469cb5b 212#define IPR_LONG_OPERATIONAL_TIMEOUT (12 * 60)
1da177e4
LT		 213#define IPR_WAIT_FOR_RESET_TIMEOUT (2 * HZ)
214#define IPR_CHECK_FOR_RESET_TIMEOUT (HZ / 10)
215#define IPR_WAIT_FOR_BIST_TIMEOUT (2 * HZ)
463fc696 216#define IPR_PCI_RESET_TIMEOUT (HZ / 2)
1da177e4
LT		 217#define IPR_DUMP_TIMEOUT (15 * HZ)
218
219/*
220 * SCSI Literals
221 */
222#define IPR_VENDOR_ID_LEN 8
223#define IPR_PROD_ID_LEN 16
224#define IPR_SERIAL_NUM_LEN 8
225
226/*
227 * Hardware literals
228 */
229#define IPR_FMT2_MBX_ADDR_MASK 0x0fffffff
230#define IPR_FMT2_MBX_BAR_SEL_MASK 0xf0000000
231#define IPR_FMT2_MKR_BAR_SEL_SHIFT 28
232#define IPR_GET_FMT2_BAR_SEL(mbx) \
233(((mbx) & IPR_FMT2_MBX_BAR_SEL_MASK) >> IPR_FMT2_MKR_BAR_SEL_SHIFT)
234#define IPR_SDT_FMT2_BAR0_SEL 0x0
235#define IPR_SDT_FMT2_BAR1_SEL 0x1
236#define IPR_SDT_FMT2_BAR2_SEL 0x2
237#define IPR_SDT_FMT2_BAR3_SEL 0x3
238#define IPR_SDT_FMT2_BAR4_SEL 0x4
239#define IPR_SDT_FMT2_BAR5_SEL 0x5
240#define IPR_SDT_FMT2_EXP_ROM_SEL 0x8
241#define IPR_FMT2_SDT_READY_TO_USE 0xC4D4E3F2
dcbad00e 242#define IPR_FMT3_SDT_READY_TO_USE 0xC4D4E3F3
1da177e4 243#define IPR_DOORBELL 0x82800000
3d1d0da6 244#define IPR_RUNTIME_RESET 0x40000000
1da177e4 245
214777ba 246#define IPR_IPL_INIT_MIN_STAGE_TIME 5
438b0331 247#define IPR_IPL_INIT_DEFAULT_STAGE_TIME 15
214777ba
WB		 248#define IPR_IPL_INIT_STAGE_UNKNOWN 0x0
249#define IPR_IPL_INIT_STAGE_TRANSOP 0xB0000000
250#define IPR_IPL_INIT_STAGE_MASK 0xff000000
251#define IPR_IPL_INIT_STAGE_TIME_MASK 0x0000ffff
252#define IPR_PCII_IPL_STAGE_CHANGE (0x80000000 >> 0)
253
1da177e4
LT		 254#define IPR_PCII_IOA_TRANS_TO_OPER (0x80000000 >> 0)
255#define IPR_PCII_IOARCB_XFER_FAILED (0x80000000 >> 3)
256#define IPR_PCII_IOA_UNIT_CHECKED (0x80000000 >> 4)
257#define IPR_PCII_NO_HOST_RRQ (0x80000000 >> 5)
258#define IPR_PCII_CRITICAL_OPERATION (0x80000000 >> 6)
259#define IPR_PCII_IO_DEBUG_ACKNOWLEDGE (0x80000000 >> 7)
260#define IPR_PCII_IOARRIN_LOST (0x80000000 >> 27)
261#define IPR_PCII_MMIO_ERROR (0x80000000 >> 28)
262#define IPR_PCII_PROC_ERR_STATE (0x80000000 >> 29)
263#define IPR_PCII_HRRQ_UPDATED (0x80000000 >> 30)
264#define IPR_PCII_CORE_ISSUED_RST_REQ (0x80000000 >> 31)
265
266#define IPR_PCII_ERROR_INTERRUPTS \
267(IPR_PCII_IOARCB_XFER_FAILED | IPR_PCII_IOA_UNIT_CHECKED | \
268IPR_PCII_NO_HOST_RRQ | IPR_PCII_IOARRIN_LOST | IPR_PCII_MMIO_ERROR)
269
270#define IPR_PCII_OPER_INTERRUPTS \
271(IPR_PCII_ERROR_INTERRUPTS | IPR_PCII_HRRQ_UPDATED | IPR_PCII_IOA_TRANS_TO_OPER)
272
273#define IPR_UPROCI_RESET_ALERT (0x80000000 >> 7)
274#define IPR_UPROCI_IO_DEBUG_ALERT (0x80000000 >> 9)
cb237ef7 275#define IPR_UPROCI_SIS64_START_BIST (0x80000000 >> 23)
1da177e4
LT		 276
277#define IPR_LDUMP_MAX_LONG_ACK_DELAY_IN_USEC 200000 /* 200 ms */
278#define IPR_LDUMP_MAX_SHORT_ACK_DELAY_IN_USEC 200000 /* 200 ms */
279
280/*
281 * Dump literals
282 */
283#define IPR_MAX_IOA_DUMP_SIZE (4 * 1024 * 1024)
284#define IPR_NUM_SDT_ENTRIES 511
285#define IPR_MAX_NUM_DUMP_PAGES ((IPR_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1)
286
287/*
288 * Misc literals
289 */
290#define IPR_NUM_IOADL_ENTRIES IPR_MAX_SGLIST
291
292/*
293 * Adapter interface types
294 */
295
296struct ipr_res_addr {
297 u8 reserved;
298 u8 bus;
299 u8 target;
300 u8 lun;
301#define IPR_GET_PHYS_LOC(res_addr) \
302 (((res_addr).bus << 16) | ((res_addr).target << 8) | (res_addr).lun)
303}__attribute__((packed, aligned (4)));
304
305struct ipr_std_inq_vpids {
306 u8 vendor_id[IPR_VENDOR_ID_LEN];
307 u8 product_id[IPR_PROD_ID_LEN];
308}__attribute__((packed));
309
cfc32139 310struct ipr_vpd {
311 struct ipr_std_inq_vpids vpids;
312 u8 sn[IPR_SERIAL_NUM_LEN];
313}__attribute__((packed));
314
ee0f05b8 315struct ipr_ext_vpd {
316 struct ipr_vpd vpd;
317 __be32 wwid[2];
318}__attribute__((packed));
319
1da177e4
LT		 320struct ipr_std_inq_data {
321 u8 peri_qual_dev_type;
322#define IPR_STD_INQ_PERI_QUAL(peri) ((peri) >> 5)
323#define IPR_STD_INQ_PERI_DEV_TYPE(peri) ((peri) & 0x1F)
324
325 u8 removeable_medium_rsvd;
326#define IPR_STD_INQ_REMOVEABLE_MEDIUM 0x80
327
328#define IPR_IS_DASD_DEVICE(std_inq) \
329((IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_DISK) && \
330!(((std_inq).removeable_medium_rsvd) & IPR_STD_INQ_REMOVEABLE_MEDIUM))
331
332#define IPR_IS_SES_DEVICE(std_inq) \
333(IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_ENCLOSURE)
334
335 u8 version;
336 u8 aen_naca_fmt;
337 u8 additional_len;
338 u8 sccs_rsvd;
339 u8 bq_enc_multi;
340 u8 sync_cmdq_flags;
341
342 struct ipr_std_inq_vpids vpids;
343
344 u8 ros_rsvd_ram_rsvd[4];
345
346 u8 serial_num[IPR_SERIAL_NUM_LEN];
347}__attribute__ ((packed));
348
3e7ebdfa
WB		 349#define IPR_RES_TYPE_AF_DASD 0x00
350#define IPR_RES_TYPE_GENERIC_SCSI 0x01
351#define IPR_RES_TYPE_VOLUME_SET 0x02
352#define IPR_RES_TYPE_REMOTE_AF_DASD 0x03
353#define IPR_RES_TYPE_GENERIC_ATA 0x04
354#define IPR_RES_TYPE_ARRAY 0x05
355#define IPR_RES_TYPE_IOAFP 0xff
356
1da177e4 357struct ipr_config_table_entry {
b5145d25
BK		 358 u8 proto;
359#define IPR_PROTO_SATA 0x02
360#define IPR_PROTO_SATA_ATAPI 0x03
361#define IPR_PROTO_SAS_STP 0x06
3e7ebdfa 362#define IPR_PROTO_SAS_STP_ATAPI 0x07
1da177e4
LT		 363 u8 array_id;
364 u8 flags;
3e7ebdfa 365#define IPR_IS_IOA_RESOURCE 0x80
1da177e4 366 u8 rsvd_subtype;
3e7ebdfa
WB		 367
368#define IPR_QUEUEING_MODEL(res) ((((res)->flags) & 0x70) >> 4)
369#define IPR_QUEUE_FROZEN_MODEL 0
ee0a90fa 370#define IPR_QUEUE_NACA_MODEL 1
371
1da177e4
LT		 372 struct ipr_res_addr res_addr;
373 __be32 res_handle;
374 __be32 reserved4[2];
375 struct ipr_std_inq_data std_inq_data;
376}__attribute__ ((packed, aligned (4)));
377
3e7ebdfa
WB		 378struct ipr_config_table_entry64 {
379 u8 res_type;
380 u8 proto;
381 u8 vset_num;
382 u8 array_id;
383 __be16 flags;
384 __be16 res_flags;
385#define IPR_QUEUEING_MODEL64(res) ((((res)->res_flags) & 0x7000) >> 12)
386 __be32 res_handle;
387 u8 dev_id_type;
388 u8 reserved[3];
389 __be64 dev_id;
390 __be64 lun;
391 __be64 lun_wwn[2];
392#define IPR_MAX_RES_PATH_LENGTH 24
393 __be64 res_path;
394 struct ipr_std_inq_data std_inq_data;
395 u8 reserved2[4];
396 __be64 reserved3[2]; // description text
397 u8 reserved4[8];
398}__attribute__ ((packed, aligned (8)));
399
1da177e4
LT		 400struct ipr_config_table_hdr {
401 u8 num_entries;
402 u8 flags;
403#define IPR_UCODE_DOWNLOAD_REQ 0x10
404 __be16 reserved;
405}__attribute__((packed, aligned (4)));
406
3e7ebdfa
WB		 407struct ipr_config_table_hdr64 {
408 __be16 num_entries;
409 __be16 reserved;
410 u8 flags;
411 u8 reserved2[11];
412}__attribute__((packed, aligned (4)));
413
1da177e4
LT		 414struct ipr_config_table {
415 struct ipr_config_table_hdr hdr;
3e7ebdfa 416 struct ipr_config_table_entry dev[0];
1da177e4
LT		 417}__attribute__((packed, aligned (4)));
418
3e7ebdfa
WB		 419struct ipr_config_table64 {
420 struct ipr_config_table_hdr64 hdr64;
421 struct ipr_config_table_entry64 dev[0];
422}__attribute__((packed, aligned (8)));
423
424struct ipr_config_table_entry_wrapper {
425 union {
426 struct ipr_config_table_entry *cfgte;
427 struct ipr_config_table_entry64 *cfgte64;
428 } u;
429};
430
1da177e4 431struct ipr_hostrcb_cfg_ch_not {
3e7ebdfa
WB		 432 union {
433 struct ipr_config_table_entry cfgte;
434 struct ipr_config_table_entry64 cfgte64;
435 } u;
1da177e4
LT		 436 u8 reserved[936];
437}__attribute__((packed, aligned (4)));
438
439struct ipr_supported_device {
440 __be16 data_length;
441 u8 reserved;
442 u8 num_records;
443 struct ipr_std_inq_vpids vpids;
444 u8 reserved2[16];
445}__attribute__((packed, aligned (4)));
446
447/* Command packet structure */
448struct ipr_cmd_pkt {
449 __be16 reserved; /* Reserved by IOA */
450 u8 request_type;
451#define IPR_RQTYPE_SCSICDB 0x00
452#define IPR_RQTYPE_IOACMD 0x01
453#define IPR_RQTYPE_HCAM 0x02
b5145d25 454#define IPR_RQTYPE_ATA_PASSTHRU 0x04
1da177e4 455
a32c055f 456 u8 reserved2;
1da177e4
LT		 457
458 u8 flags_hi;
459#define IPR_FLAGS_HI_WRITE_NOT_READ 0x80
460#define IPR_FLAGS_HI_NO_ULEN_CHK 0x20
461#define IPR_FLAGS_HI_SYNC_OVERRIDE 0x10
462#define IPR_FLAGS_HI_SYNC_COMPLETE 0x08
463#define IPR_FLAGS_HI_NO_LINK_DESC 0x04
464
465 u8 flags_lo;
466#define IPR_FLAGS_LO_ALIGNED_BFR 0x20
467#define IPR_FLAGS_LO_DELAY_AFTER_RST 0x10
468#define IPR_FLAGS_LO_UNTAGGED_TASK 0x00
469#define IPR_FLAGS_LO_SIMPLE_TASK 0x02
470#define IPR_FLAGS_LO_ORDERED_TASK 0x04
471#define IPR_FLAGS_LO_HEAD_OF_Q_TASK 0x06
472#define IPR_FLAGS_LO_ACA_TASK 0x08
473
474 u8 cdb[16];
475 __be16 timeout;
476}__attribute__ ((packed, aligned(4)));
477
a32c055f 478struct ipr_ioarcb_ata_regs { /* 22 bytes */
b5145d25
BK		 479 u8 flags;
480#define IPR_ATA_FLAG_PACKET_CMD 0x80
481#define IPR_ATA_FLAG_XFER_TYPE_DMA 0x40
482#define IPR_ATA_FLAG_STATUS_ON_GOOD_COMPLETION 0x20
483 u8 reserved[3];
484
485 __be16 data;
486 u8 feature;
487 u8 nsect;
488 u8 lbal;
489 u8 lbam;
490 u8 lbah;
491 u8 device;
492 u8 command;
493 u8 reserved2[3];
494 u8 hob_feature;
495 u8 hob_nsect;
496 u8 hob_lbal;
497 u8 hob_lbam;
498 u8 hob_lbah;
499 u8 ctl;
500}__attribute__ ((packed, aligned(4)));
501
51b1c7e1
BK		 502struct ipr_ioadl_desc {
503 __be32 flags_and_data_len;
504#define IPR_IOADL_FLAGS_MASK 0xff000000
505#define IPR_IOADL_GET_FLAGS(x) (be32_to_cpu(x) & IPR_IOADL_FLAGS_MASK)
506#define IPR_IOADL_DATA_LEN_MASK 0x00ffffff
507#define IPR_IOADL_GET_DATA_LEN(x) (be32_to_cpu(x) & IPR_IOADL_DATA_LEN_MASK)
508#define IPR_IOADL_FLAGS_READ 0x48000000
509#define IPR_IOADL_FLAGS_READ_LAST 0x49000000
510#define IPR_IOADL_FLAGS_WRITE 0x68000000
511#define IPR_IOADL_FLAGS_WRITE_LAST 0x69000000
512#define IPR_IOADL_FLAGS_LAST 0x01000000
513
514 __be32 address;
515}__attribute__((packed, aligned (8)));
516
a32c055f
WB		 517struct ipr_ioadl64_desc {
518 __be32 flags;
519 __be32 data_len;
520 __be64 address;
521}__attribute__((packed, aligned (16)));
522
523struct ipr_ata64_ioadl {
524 struct ipr_ioarcb_ata_regs regs;
525 u16 reserved[5];
526 struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
527}__attribute__((packed, aligned (16)));
528
b5145d25
BK		 529struct ipr_ioarcb_add_data {
530 union {
531 struct ipr_ioarcb_ata_regs regs;
51b1c7e1 532 struct ipr_ioadl_desc ioadl[5];
b5145d25 533 __be32 add_cmd_parms[10];
a32c055f
WB		 534 } u;
535}__attribute__ ((packed, aligned (4)));
536
537struct ipr_ioarcb_sis64_add_addr_ecb {
538 __be64 ioasa_host_pci_addr;
539 __be64 data_ioadl_addr;
540 __be64 reserved;
541 __be32 ext_control_buf[4];
542}__attribute__((packed, aligned (8)));
b5145d25 543
1da177e4
LT		 544/* IOA Request Control Block 128 bytes */
545struct ipr_ioarcb {
a32c055f
WB		 546 union {
547 __be32 ioarcb_host_pci_addr;
548 __be64 ioarcb_host_pci_addr64;
549 } a;
1da177e4
LT		 550 __be32 res_handle;
551 __be32 host_response_handle;
552 __be32 reserved1;
553 __be32 reserved2;
554 __be32 reserved3;
555
a32c055f 556 __be32 data_transfer_length;
1da177e4
LT		 557 __be32 read_data_transfer_length;
558 __be32 write_ioadl_addr;
a32c055f 559 __be32 ioadl_len;
1da177e4
LT		 560 __be32 read_ioadl_addr;
561 __be32 read_ioadl_len;
562
563 __be32 ioasa_host_pci_addr;
564 __be16 ioasa_len;
565 __be16 reserved4;
566
567 struct ipr_cmd_pkt cmd_pkt;
568
a32c055f
WB		 569 __be16 add_cmd_parms_offset;
570 __be16 add_cmd_parms_len;
571
572 union {
573 struct ipr_ioarcb_add_data add_data;
574 struct ipr_ioarcb_sis64_add_addr_ecb sis64_addr_data;
575 } u;
576
1da177e4
LT		 577}__attribute__((packed, aligned (4)));
578
1da177e4
LT		 579struct ipr_ioasa_vset {
580 __be32 failing_lba_hi;
581 __be32 failing_lba_lo;
c8f74892 582 __be32 reserved;
1da177e4
LT		 583}__attribute__((packed, aligned (4)));
584
585struct ipr_ioasa_af_dasd {
586 __be32 failing_lba;
c8f74892 587 __be32 reserved[2];
1da177e4
LT		 588}__attribute__((packed, aligned (4)));
589
590struct ipr_ioasa_gpdd {
591 u8 end_state;
592 u8 bus_phase;
593 __be16 reserved;
c8f74892 594 __be32 ioa_data[2];
1da177e4
LT		 595}__attribute__((packed, aligned (4)));
596
b5145d25
BK		 597struct ipr_ioasa_gata {
598 u8 error;
599 u8 nsect; /* Interrupt reason */
600 u8 lbal;
601 u8 lbam;
602 u8 lbah;
603 u8 device;
604 u8 status;
605 u8 alt_status; /* ATA CTL */
606 u8 hob_nsect;
607 u8 hob_lbal;
608 u8 hob_lbam;
609 u8 hob_lbah;
610}__attribute__((packed, aligned (4)));
611
c8f74892 612struct ipr_auto_sense {
613 __be16 auto_sense_len;
614 __be16 ioa_data_len;
615 __be32 data[SCSI_SENSE_BUFFERSIZE/sizeof(__be32)];
616};
1da177e4 617
96d21f00 618struct ipr_ioasa_hdr {
1da177e4
LT		 619 __be32 ioasc;
620#define IPR_IOASC_SENSE_KEY(ioasc) ((ioasc) >> 24)
621#define IPR_IOASC_SENSE_CODE(ioasc) (((ioasc) & 0x00ff0000) >> 16)
622#define IPR_IOASC_SENSE_QUAL(ioasc) (((ioasc) & 0x0000ff00) >> 8)
623#define IPR_IOASC_SENSE_STATUS(ioasc) ((ioasc) & 0x000000ff)
624
625 __be16 ret_stat_len; /* Length of the returned IOASA */
626
627 __be16 avail_stat_len; /* Total Length of status available. */
628
629 __be32 residual_data_len; /* number of bytes in the host data */
630 /* buffers that were not used by the IOARCB command. */
631
632 __be32 ilid;
633#define IPR_NO_ILID 0
634#define IPR_DRIVER_ILID 0xffffffff
635
636 __be32 fd_ioasc;
637
638 __be32 fd_phys_locator;
639
640 __be32 fd_res_handle;
641
642 __be32 ioasc_specific; /* status code specific field */
c8f74892 643#define IPR_ADDITIONAL_STATUS_FMT 0x80000000
644#define IPR_AUTOSENSE_VALID 0x40000000
b5145d25 645#define IPR_ATA_DEVICE_WAS_RESET 0x20000000
1da177e4
LT		 646#define IPR_IOASC_SPECIFIC_MASK 0x00ffffff
647#define IPR_FIELD_POINTER_VALID (0x80000000 >> 8)
648#define IPR_FIELD_POINTER_MASK 0x0000ffff
649
96d21f00
WB		 650}__attribute__((packed, aligned (4)));
651
652struct ipr_ioasa {
653 struct ipr_ioasa_hdr hdr;
654
655 union {
656 struct ipr_ioasa_vset vset;
657 struct ipr_ioasa_af_dasd dasd;
658 struct ipr_ioasa_gpdd gpdd;
659 struct ipr_ioasa_gata gata;
660 } u;
661
662 struct ipr_auto_sense auto_sense;
663}__attribute__((packed, aligned (4)));
664
665struct ipr_ioasa64 {
666 struct ipr_ioasa_hdr hdr;
667 u8 fd_res_path[8];
668
1da177e4
LT		 669 union {
670 struct ipr_ioasa_vset vset;
671 struct ipr_ioasa_af_dasd dasd;
672 struct ipr_ioasa_gpdd gpdd;
b5145d25 673 struct ipr_ioasa_gata gata;
1da177e4 674 } u;
c8f74892 675
676 struct ipr_auto_sense auto_sense;
1da177e4
LT		 677}__attribute__((packed, aligned (4)));
678
679struct ipr_mode_parm_hdr {
680 u8 length;
681 u8 medium_type;
682 u8 device_spec_parms;
683 u8 block_desc_len;
684}__attribute__((packed));
685
686struct ipr_mode_pages {
687 struct ipr_mode_parm_hdr hdr;
688 u8 data[255 - sizeof(struct ipr_mode_parm_hdr)];
689}__attribute__((packed));
690
691struct ipr_mode_page_hdr {
692 u8 ps_page_code;
693#define IPR_MODE_PAGE_PS 0x80
694#define IPR_GET_MODE_PAGE_CODE(hdr) ((hdr)->ps_page_code & 0x3F)
695 u8 page_length;
696}__attribute__ ((packed));
697
698struct ipr_dev_bus_entry {
699 struct ipr_res_addr res_addr;
700 u8 flags;
701#define IPR_SCSI_ATTR_ENABLE_QAS 0x80
702#define IPR_SCSI_ATTR_DISABLE_QAS 0x40
703#define IPR_SCSI_ATTR_QAS_MASK 0xC0
704#define IPR_SCSI_ATTR_ENABLE_TM 0x20
705#define IPR_SCSI_ATTR_NO_TERM_PWR 0x10
706#define IPR_SCSI_ATTR_TM_SUPPORTED 0x08
707#define IPR_SCSI_ATTR_LVD_TO_SE_NOT_ALLOWED 0x04
708
709 u8 scsi_id;
710 u8 bus_width;
711 u8 extended_reset_delay;
712#define IPR_EXTENDED_RESET_DELAY 7
713
714 __be32 max_xfer_rate;
715
716 u8 spinup_delay;
717 u8 reserved3;
718 __be16 reserved4;
719}__attribute__((packed, aligned (4)));
720
721struct ipr_mode_page28 {
722 struct ipr_mode_page_hdr hdr;
723 u8 num_entries;
724 u8 entry_length;
725 struct ipr_dev_bus_entry bus[0];
726}__attribute__((packed));
727
ac09c349
BK		 728struct ipr_mode_page24 {
729 struct ipr_mode_page_hdr hdr;
730 u8 flags;
731#define IPR_ENABLE_DUAL_IOA_AF 0x80
732}__attribute__((packed));
733
1da177e4
LT		 734struct ipr_ioa_vpd {
735 struct ipr_std_inq_data std_inq_data;
736 u8 ascii_part_num[12];
737 u8 reserved[40];
738 u8 ascii_plant_code[4];
739}__attribute__((packed));
740
741struct ipr_inquiry_page3 {
742 u8 peri_qual_dev_type;
743 u8 page_code;
744 u8 reserved1;
745 u8 page_length;
746 u8 ascii_len;
747 u8 reserved2[3];
748 u8 load_id[4];
749 u8 major_release;
750 u8 card_type;
751 u8 minor_release[2];
752 u8 ptf_number[4];
753 u8 patch_number[4];
754}__attribute__((packed));
755
ac09c349
BK		 756struct ipr_inquiry_cap {
757 u8 peri_qual_dev_type;
758 u8 page_code;
759 u8 reserved1;
760 u8 page_length;
761 u8 ascii_len;
762 u8 reserved2;
763 u8 sis_version[2];
764 u8 cap;
765#define IPR_CAP_DUAL_IOA_RAID 0x80
766 u8 reserved3[15];
767}__attribute__((packed));
768
62275040 769#define IPR_INQUIRY_PAGE0_ENTRIES 20
770struct ipr_inquiry_page0 {
771 u8 peri_qual_dev_type;
772 u8 page_code;
773 u8 reserved1;
774 u8 len;
775 u8 page[IPR_INQUIRY_PAGE0_ENTRIES];
776}__attribute__((packed));
777
1da177e4 778struct ipr_hostrcb_device_data_entry {
cfc32139 779 struct ipr_vpd vpd;
1da177e4 780 struct ipr_res_addr dev_res_addr;
cfc32139 781 struct ipr_vpd new_vpd;
782 struct ipr_vpd ioa_last_with_dev_vpd;
783 struct ipr_vpd cfc_last_with_dev_vpd;
1da177e4
LT		 784 __be32 ioa_data[5];
785}__attribute__((packed, aligned (4)));
786
ee0f05b8 787struct ipr_hostrcb_device_data_entry_enhanced {
788 struct ipr_ext_vpd vpd;
789 u8 ccin[4];
790 struct ipr_res_addr dev_res_addr;
791 struct ipr_ext_vpd new_vpd;
792 u8 new_ccin[4];
793 struct ipr_ext_vpd ioa_last_with_dev_vpd;
794 struct ipr_ext_vpd cfc_last_with_dev_vpd;
795}__attribute__((packed, aligned (4)));
796
4565e370
WB		 797struct ipr_hostrcb64_device_data_entry_enhanced {
798 struct ipr_ext_vpd vpd;
799 u8 ccin[4];
800 u8 res_path[8];
801 struct ipr_ext_vpd new_vpd;
802 u8 new_ccin[4];
803 struct ipr_ext_vpd ioa_last_with_dev_vpd;
804 struct ipr_ext_vpd cfc_last_with_dev_vpd;
805}__attribute__((packed, aligned (4)));
806
1da177e4 807struct ipr_hostrcb_array_data_entry {
cfc32139 808 struct ipr_vpd vpd;
1da177e4
LT		 809 struct ipr_res_addr expected_dev_res_addr;
810 struct ipr_res_addr dev_res_addr;
811}__attribute__((packed, aligned (4)));
812
4565e370
WB		 813struct ipr_hostrcb64_array_data_entry {
814 struct ipr_ext_vpd vpd;
815 u8 ccin[4];
816 u8 expected_res_path[8];
817 u8 res_path[8];
818}__attribute__((packed, aligned (4)));
819
ee0f05b8 820struct ipr_hostrcb_array_data_entry_enhanced {
821 struct ipr_ext_vpd vpd;
822 u8 ccin[4];
823 struct ipr_res_addr expected_dev_res_addr;
824 struct ipr_res_addr dev_res_addr;
825}__attribute__((packed, aligned (4)));
826
1da177e4 827struct ipr_hostrcb_type_ff_error {
438b0331 828 __be32 ioa_data[758];
1da177e4
LT		 829}__attribute__((packed, aligned (4)));
830
831struct ipr_hostrcb_type_01_error {
832 __be32 seek_counter;
833 __be32 read_counter;
834 u8 sense_data[32];
835 __be32 ioa_data[236];
836}__attribute__((packed, aligned (4)));
837
838struct ipr_hostrcb_type_02_error {
cfc32139 839 struct ipr_vpd ioa_vpd;
840 struct ipr_vpd cfc_vpd;
841 struct ipr_vpd ioa_last_attached_to_cfc_vpd;
842 struct ipr_vpd cfc_last_attached_to_ioa_vpd;
1da177e4 843 __be32 ioa_data[3];
1da177e4
LT		 844}__attribute__((packed, aligned (4)));
845
ee0f05b8 846struct ipr_hostrcb_type_12_error {
847 struct ipr_ext_vpd ioa_vpd;
848 struct ipr_ext_vpd cfc_vpd;
849 struct ipr_ext_vpd ioa_last_attached_to_cfc_vpd;
850 struct ipr_ext_vpd cfc_last_attached_to_ioa_vpd;
851 __be32 ioa_data[3];
852}__attribute__((packed, aligned (4)));
853
1da177e4 854struct ipr_hostrcb_type_03_error {
cfc32139 855 struct ipr_vpd ioa_vpd;
856 struct ipr_vpd cfc_vpd;
1da177e4
LT		 857 __be32 errors_detected;
858 __be32 errors_logged;
859 u8 ioa_data[12];
cfc32139 860 struct ipr_hostrcb_device_data_entry dev[3];
1da177e4
LT		 861}__attribute__((packed, aligned (4)));
862
ee0f05b8 863struct ipr_hostrcb_type_13_error {
864 struct ipr_ext_vpd ioa_vpd;
865 struct ipr_ext_vpd cfc_vpd;
866 __be32 errors_detected;
867 __be32 errors_logged;
868 struct ipr_hostrcb_device_data_entry_enhanced dev[3];
869}__attribute__((packed, aligned (4)));
870
4565e370
WB		 871struct ipr_hostrcb_type_23_error {
872 struct ipr_ext_vpd ioa_vpd;
873 struct ipr_ext_vpd cfc_vpd;
874 __be32 errors_detected;
875 __be32 errors_logged;
876 struct ipr_hostrcb64_device_data_entry_enhanced dev[3];
877}__attribute__((packed, aligned (4)));
878
1da177e4 879struct ipr_hostrcb_type_04_error {
cfc32139 880 struct ipr_vpd ioa_vpd;
881 struct ipr_vpd cfc_vpd;
1da177e4
LT		 882 u8 ioa_data[12];
883 struct ipr_hostrcb_array_data_entry array_member[10];
884 __be32 exposed_mode_adn;
885 __be32 array_id;
cfc32139 886 struct ipr_vpd incomp_dev_vpd;
1da177e4
LT		 887 __be32 ioa_data2;
888 struct ipr_hostrcb_array_data_entry array_member2[8];
889 struct ipr_res_addr last_func_vset_res_addr;
890 u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
891 u8 protection_level[8];
1da177e4
LT		 892}__attribute__((packed, aligned (4)));
893
ee0f05b8 894struct ipr_hostrcb_type_14_error {
895 struct ipr_ext_vpd ioa_vpd;
896 struct ipr_ext_vpd cfc_vpd;
897 __be32 exposed_mode_adn;
898 __be32 array_id;
899 struct ipr_res_addr last_func_vset_res_addr;
900 u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
901 u8 protection_level[8];
902 __be32 num_entries;
903 struct ipr_hostrcb_array_data_entry_enhanced array_member[18];
904}__attribute__((packed, aligned (4)));
905
4565e370
WB		 906struct ipr_hostrcb_type_24_error {
907 struct ipr_ext_vpd ioa_vpd;
908 struct ipr_ext_vpd cfc_vpd;
909 u8 reserved[2];
910 u8 exposed_mode_adn;
911#define IPR_INVALID_ARRAY_DEV_NUM 0xff
912 u8 array_id;
913 u8 last_res_path[8];
914 u8 protection_level[8];
915 struct ipr_ext_vpd array_vpd;
916 u8 description[16];
917 u8 reserved2[3];
918 u8 num_entries;
919 struct ipr_hostrcb64_array_data_entry array_member[32];
920}__attribute__((packed, aligned (4)));
921
b0df54bb 922struct ipr_hostrcb_type_07_error {
923 u8 failure_reason[64];
924 struct ipr_vpd vpd;
925 u32 data[222];
926}__attribute__((packed, aligned (4)));
927
ee0f05b8 928struct ipr_hostrcb_type_17_error {
929 u8 failure_reason[64];
930 struct ipr_ext_vpd vpd;
931 u32 data[476];
932}__attribute__((packed, aligned (4)));
933
49dc6a18
BK		 934struct ipr_hostrcb_config_element {
935 u8 type_status;
936#define IPR_PATH_CFG_TYPE_MASK 0xF0
937#define IPR_PATH_CFG_NOT_EXIST 0x00
938#define IPR_PATH_CFG_IOA_PORT 0x10
939#define IPR_PATH_CFG_EXP_PORT 0x20
940#define IPR_PATH_CFG_DEVICE_PORT 0x30
941#define IPR_PATH_CFG_DEVICE_LUN 0x40
942
943#define IPR_PATH_CFG_STATUS_MASK 0x0F
944#define IPR_PATH_CFG_NO_PROB 0x00
945#define IPR_PATH_CFG_DEGRADED 0x01
946#define IPR_PATH_CFG_FAILED 0x02
947#define IPR_PATH_CFG_SUSPECT 0x03
948#define IPR_PATH_NOT_DETECTED 0x04
949#define IPR_PATH_INCORRECT_CONN 0x05
950
951 u8 cascaded_expander;
952 u8 phy;
953 u8 link_rate;
954#define IPR_PHY_LINK_RATE_MASK 0x0F
955
956 __be32 wwid[2];
957}__attribute__((packed, aligned (4)));
958
4565e370
WB		 959struct ipr_hostrcb64_config_element {
960 __be16 length;
961 u8 descriptor_id;
962#define IPR_DESCRIPTOR_MASK 0xC0
963#define IPR_DESCRIPTOR_SIS64 0x00
964
965 u8 reserved;
966 u8 type_status;
967
968 u8 reserved2[2];
969 u8 link_rate;
970
971 u8 res_path[8];
972 __be32 wwid[2];
973}__attribute__((packed, aligned (8)));
974
49dc6a18
BK		 975struct ipr_hostrcb_fabric_desc {
976 __be16 length;
977 u8 ioa_port;
978 u8 cascaded_expander;
979 u8 phy;
980 u8 path_state;
981#define IPR_PATH_ACTIVE_MASK 0xC0
982#define IPR_PATH_NO_INFO 0x00
983#define IPR_PATH_ACTIVE 0x40
984#define IPR_PATH_NOT_ACTIVE 0x80
985
986#define IPR_PATH_STATE_MASK 0x0F
987#define IPR_PATH_STATE_NO_INFO 0x00
988#define IPR_PATH_HEALTHY 0x01
989#define IPR_PATH_DEGRADED 0x02
990#define IPR_PATH_FAILED 0x03
991
992 __be16 num_entries;
993 struct ipr_hostrcb_config_element elem[1];
994}__attribute__((packed, aligned (4)));
995
4565e370
WB		 996struct ipr_hostrcb64_fabric_desc {
997 __be16 length;
998 u8 descriptor_id;
999
8701f185 1000 u8 reserved[2];
4565e370
WB		 1001 u8 path_state;
1002
1003 u8 reserved2[2];
1004 u8 res_path[8];
1005 u8 reserved3[6];
1006 __be16 num_entries;
1007 struct ipr_hostrcb64_config_element elem[1];
1008}__attribute__((packed, aligned (8)));
1009
49dc6a18
BK		 1010#define for_each_fabric_cfg(fabric, cfg) \
1011 for (cfg = (fabric)->elem; \
1012 cfg < ((fabric)->elem + be16_to_cpu((fabric)->num_entries)); \
1013 cfg++)
1014
1015struct ipr_hostrcb_type_20_error {
1016 u8 failure_reason[64];
1017 u8 reserved[3];
1018 u8 num_entries;
1019 struct ipr_hostrcb_fabric_desc desc[1];
1020}__attribute__((packed, aligned (4)));
1021
4565e370
WB		 1022struct ipr_hostrcb_type_30_error {
1023 u8 failure_reason[64];
1024 u8 reserved[3];
1025 u8 num_entries;
1026 struct ipr_hostrcb64_fabric_desc desc[1];
1027}__attribute__((packed, aligned (4)));
1028
1da177e4 1029struct ipr_hostrcb_error {
4565e370
WB		 1030 __be32 fd_ioasc;
1031 struct ipr_res_addr fd_res_addr;
1032 __be32 fd_res_handle;
1da177e4
LT		 1033 __be32 prc;
1034 union {
1035 struct ipr_hostrcb_type_ff_error type_ff_error;
1036 struct ipr_hostrcb_type_01_error type_01_error;
1037 struct ipr_hostrcb_type_02_error type_02_error;
1038 struct ipr_hostrcb_type_03_error type_03_error;
1039 struct ipr_hostrcb_type_04_error type_04_error;
b0df54bb 1040 struct ipr_hostrcb_type_07_error type_07_error;
ee0f05b8 1041 struct ipr_hostrcb_type_12_error type_12_error;
1042 struct ipr_hostrcb_type_13_error type_13_error;
1043 struct ipr_hostrcb_type_14_error type_14_error;
1044 struct ipr_hostrcb_type_17_error type_17_error;
49dc6a18 1045 struct ipr_hostrcb_type_20_error type_20_error;
1da177e4
LT		 1046 } u;
1047}__attribute__((packed, aligned (4)));
1048
4565e370
WB		 1049struct ipr_hostrcb64_error {
1050 __be32 fd_ioasc;
1051 __be32 ioa_fw_level;
1052 __be32 fd_res_handle;
1053 __be32 prc;
1054 __be64 fd_dev_id;
1055 __be64 fd_lun;
1056 u8 fd_res_path[8];
1057 __be64 time_stamp;
8701f185 1058 u8 reserved[16];
4565e370
WB		 1059 union {
1060 struct ipr_hostrcb_type_ff_error type_ff_error;
1061 struct ipr_hostrcb_type_12_error type_12_error;
1062 struct ipr_hostrcb_type_17_error type_17_error;
1063 struct ipr_hostrcb_type_23_error type_23_error;
1064 struct ipr_hostrcb_type_24_error type_24_error;
1065 struct ipr_hostrcb_type_30_error type_30_error;
1066 } u;
1067}__attribute__((packed, aligned (8)));
1068
1da177e4
LT		 1069struct ipr_hostrcb_raw {
1070 __be32 data[sizeof(struct ipr_hostrcb_error)/sizeof(__be32)];
1071}__attribute__((packed, aligned (4)));
1072
1073struct ipr_hcam {
1074 u8 op_code;
1075#define IPR_HOST_RCB_OP_CODE_CONFIG_CHANGE 0xE1
1076#define IPR_HOST_RCB_OP_CODE_LOG_DATA 0xE2
1077
1078 u8 notify_type;
1079#define IPR_HOST_RCB_NOTIF_TYPE_EXISTING_CHANGED 0x00
1080#define IPR_HOST_RCB_NOTIF_TYPE_NEW_ENTRY 0x01
1081#define IPR_HOST_RCB_NOTIF_TYPE_REM_ENTRY 0x02
1082#define IPR_HOST_RCB_NOTIF_TYPE_ERROR_LOG_ENTRY 0x10
1083#define IPR_HOST_RCB_NOTIF_TYPE_INFORMATION_ENTRY 0x11
1084
1085 u8 notifications_lost;
1086#define IPR_HOST_RCB_NO_NOTIFICATIONS_LOST 0
1087#define IPR_HOST_RCB_NOTIFICATIONS_LOST 0x80
1088
1089 u8 flags;
1090#define IPR_HOSTRCB_INTERNAL_OPER 0x80
1091#define IPR_HOSTRCB_ERR_RESP_SENT 0x40
1092
1093 u8 overlay_id;
1094#define IPR_HOST_RCB_OVERLAY_ID_1 0x01
1095#define IPR_HOST_RCB_OVERLAY_ID_2 0x02
1096#define IPR_HOST_RCB_OVERLAY_ID_3 0x03
1097#define IPR_HOST_RCB_OVERLAY_ID_4 0x04
1098#define IPR_HOST_RCB_OVERLAY_ID_6 0x06
b0df54bb 1099#define IPR_HOST_RCB_OVERLAY_ID_7 0x07
ee0f05b8 1100#define IPR_HOST_RCB_OVERLAY_ID_12 0x12
1101#define IPR_HOST_RCB_OVERLAY_ID_13 0x13
1102#define IPR_HOST_RCB_OVERLAY_ID_14 0x14
1103#define IPR_HOST_RCB_OVERLAY_ID_16 0x16
1104#define IPR_HOST_RCB_OVERLAY_ID_17 0x17
49dc6a18 1105#define IPR_HOST_RCB_OVERLAY_ID_20 0x20
4565e370
WB		 1106#define IPR_HOST_RCB_OVERLAY_ID_23 0x23
1107#define IPR_HOST_RCB_OVERLAY_ID_24 0x24
1108#define IPR_HOST_RCB_OVERLAY_ID_26 0x26
1109#define IPR_HOST_RCB_OVERLAY_ID_30 0x30
1110#define IPR_HOST_RCB_OVERLAY_ID_DEFAULT 0xFF
1da177e4
LT		 1111
1112 u8 reserved1[3];
1113 __be32 ilid;
1114 __be32 time_since_last_ioa_reset;
1115 __be32 reserved2;
1116 __be32 length;
1117
1118 union {
1119 struct ipr_hostrcb_error error;
4565e370 1120 struct ipr_hostrcb64_error error64;
1da177e4
LT		 1121 struct ipr_hostrcb_cfg_ch_not ccn;
1122 struct ipr_hostrcb_raw raw;
1123 } u;
1124}__attribute__((packed, aligned (4)));
1125
1126struct ipr_hostrcb {
1127 struct ipr_hcam hcam;
1128 dma_addr_t hostrcb_dma;
1129 struct list_head queue;
49dc6a18 1130 struct ipr_ioa_cfg *ioa_cfg;
4565e370 1131 char rp_buffer[IPR_MAX_RES_PATH_LENGTH];
1da177e4
LT		 1132};
1133
1134/* IPR smart dump table structures */
1135struct ipr_sdt_entry {
dcbad00e
WB		 1136 __be32 start_token;
1137 __be32 end_token;
1138 u8 reserved[4];
1da177e4
LT		 1139
1140 u8 flags;
1141#define IPR_SDT_ENDIAN 0x80
1142#define IPR_SDT_VALID_ENTRY 0x20
1143
1144 u8 resv;
1145 __be16 priority;
1146}__attribute__((packed, aligned (4)));
1147
1148struct ipr_sdt_header {
1149 __be32 state;
1150 __be32 num_entries;
1151 __be32 num_entries_used;
1152 __be32 dump_size;
1153}__attribute__((packed, aligned (4)));
1154
1155struct ipr_sdt {
1156 struct ipr_sdt_header hdr;
1157 struct ipr_sdt_entry entry[IPR_NUM_SDT_ENTRIES];
1158}__attribute__((packed, aligned (4)));
1159
1160struct ipr_uc_sdt {
1161 struct ipr_sdt_header hdr;
1162 struct ipr_sdt_entry entry[1];
1163}__attribute__((packed, aligned (4)));
1164
1165/*
1166 * Driver types
1167 */
1168struct ipr_bus_attributes {
1169 u8 bus;
1170 u8 qas_enabled;
1171 u8 bus_width;
1172 u8 reserved;
1173 u32 max_xfer_rate;
1174};
1175
35a39691
BK		 1176struct ipr_sata_port {
1177 struct ipr_ioa_cfg *ioa_cfg;
1178 struct ata_port *ap;
1179 struct ipr_resource_entry *res;
1180 struct ipr_ioasa_gata ioasa;
1181};
1182
1da177e4 1183struct ipr_resource_entry {
1da177e4
LT		 1184 u8 needs_sync_complete:1;
1185 u8 in_erp:1;
1186 u8 add_to_ml:1;
1187 u8 del_from_ml:1;
1188 u8 resetting_device:1;
1189
3e7ebdfa
WB		 1190 u32 bus; /* AKA channel */
1191 u32 target; /* AKA id */
1192 u32 lun;
1193#define IPR_ARRAY_VIRTUAL_BUS 0x1
1194#define IPR_VSET_VIRTUAL_BUS 0x2
1195#define IPR_IOAFP_VIRTUAL_BUS 0x3
1196
1197#define IPR_GET_RES_PHYS_LOC(res) \
1198 (((res)->bus << 24) | ((res)->target << 8) | (res)->lun)
1199
1200 u8 ata_class;
1201
1202 u8 flags;
1203 __be16 res_flags;
1204
7be96900 1205 u8 type;
3e7ebdfa
WB		 1206
1207 u8 qmodel;
1208 struct ipr_std_inq_data std_inq_data;
1209
1210 __be32 res_handle;
1211 __be64 dev_id;
1212 struct scsi_lun dev_lun;
1213 u8 res_path[8];
1214
1215 struct ipr_ioa_cfg *ioa_cfg;
1da177e4 1216 struct scsi_device *sdev;
35a39691 1217 struct ipr_sata_port *sata_port;
1da177e4 1218 struct list_head queue;
3e7ebdfa 1219}; /* struct ipr_resource_entry */
1da177e4
LT		 1220
1221struct ipr_resource_hdr {
1222 u16 num_entries;
1223 u16 reserved;
1224};
1225
1da177e4
LT		 1226struct ipr_misc_cbs {
1227 struct ipr_ioa_vpd ioa_vpd;
62275040 1228 struct ipr_inquiry_page0 page0_data;
1da177e4 1229 struct ipr_inquiry_page3 page3_data;
ac09c349 1230 struct ipr_inquiry_cap cap;
1da177e4
LT		 1231 struct ipr_mode_pages mode_pages;
1232 struct ipr_supported_device supp_dev;
1233};
1234
1235struct ipr_interrupt_offsets {
1236 unsigned long set_interrupt_mask_reg;
1237 unsigned long clr_interrupt_mask_reg;
214777ba 1238 unsigned long clr_interrupt_mask_reg32;
1da177e4 1239 unsigned long sense_interrupt_mask_reg;
214777ba 1240 unsigned long sense_interrupt_mask_reg32;
1da177e4 1241 unsigned long clr_interrupt_reg;
214777ba 1242 unsigned long clr_interrupt_reg32;
1da177e4
LT		 1243
1244 unsigned long sense_interrupt_reg;
214777ba 1245 unsigned long sense_interrupt_reg32;
1da177e4
LT		 1246 unsigned long ioarrin_reg;
1247 unsigned long sense_uproc_interrupt_reg;
214777ba 1248 unsigned long sense_uproc_interrupt_reg32;
1da177e4 1249 unsigned long set_uproc_interrupt_reg;
214777ba 1250 unsigned long set_uproc_interrupt_reg32;
1da177e4 1251 unsigned long clr_uproc_interrupt_reg;
214777ba
WB		 1252 unsigned long clr_uproc_interrupt_reg32;
1253
1254 unsigned long init_feedback_reg;
dcbad00e
WB		 1255
1256 unsigned long dump_addr_reg;
1257 unsigned long dump_data_reg;
8701f185
WB		 1258
1259#define IPR_ENDIAN_SWAP_KEY 0x000C0C00
1260 unsigned long endian_swap_reg;
1da177e4
LT		 1261};
1262
1263struct ipr_interrupts {
1264 void __iomem *set_interrupt_mask_reg;
1265 void __iomem *clr_interrupt_mask_reg;
214777ba 1266 void __iomem *clr_interrupt_mask_reg32;
1da177e4 1267 void __iomem *sense_interrupt_mask_reg;
214777ba 1268 void __iomem *sense_interrupt_mask_reg32;
1da177e4 1269 void __iomem *clr_interrupt_reg;
214777ba 1270 void __iomem *clr_interrupt_reg32;
1da177e4
LT		 1271
1272 void __iomem *sense_interrupt_reg;
214777ba 1273 void __iomem *sense_interrupt_reg32;
1da177e4
LT		 1274 void __iomem *ioarrin_reg;
1275 void __iomem *sense_uproc_interrupt_reg;
214777ba 1276 void __iomem *sense_uproc_interrupt_reg32;
1da177e4 1277 void __iomem *set_uproc_interrupt_reg;
214777ba 1278 void __iomem *set_uproc_interrupt_reg32;
1da177e4 1279 void __iomem *clr_uproc_interrupt_reg;
214777ba
WB		 1280 void __iomem *clr_uproc_interrupt_reg32;
1281
1282 void __iomem *init_feedback_reg;
dcbad00e
WB		 1283
1284 void __iomem *dump_addr_reg;
1285 void __iomem *dump_data_reg;
8701f185
WB		 1286
1287 void __iomem *endian_swap_reg;
1da177e4
LT		 1288};
1289
1290struct ipr_chip_cfg_t {
1291 u32 mailbox;
1292 u8 cache_line_size;
1293 struct ipr_interrupt_offsets regs;
1294};
1295
1296struct ipr_chip_t {
1297 u16 vendor;
1298 u16 device;
1be7bd82
WB		 1299 u16 intr_type;
1300#define IPR_USE_LSI 0x00
1301#define IPR_USE_MSI 0x01
a32c055f
WB		 1302 u16 sis_type;
1303#define IPR_SIS32 0x00
1304#define IPR_SIS64 0x01
cb237ef7
WB		 1305 u16 bist_method;
1306#define IPR_PCI_CFG 0x00
1307#define IPR_MMIO 0x01
1da177e4
LT		 1308 const struct ipr_chip_cfg_t *cfg;
1309};
1310
1311enum ipr_shutdown_type {
1312 IPR_SHUTDOWN_NORMAL = 0x00,
1313 IPR_SHUTDOWN_PREPARE_FOR_NORMAL = 0x40,
1314 IPR_SHUTDOWN_ABBREV = 0x80,
1315 IPR_SHUTDOWN_NONE = 0x100
1316};
1317
1318struct ipr_trace_entry {
1319 u32 time;
1320
1321 u8 op_code;
35a39691 1322 u8 ata_op_code;
1da177e4
LT		 1323 u8 type;
1324#define IPR_TRACE_START 0x00
1325#define IPR_TRACE_FINISH 0xff
35a39691 1326 u8 cmd_index;
1da177e4
LT		 1327
1328 __be32 res_handle;
1329 union {
1330 u32 ioasc;
1331 u32 add_data;
1332 u32 res_addr;
1333 } u;
1334};
1335
1336struct ipr_sglist {
1337 u32 order;
1338 u32 num_sg;
12baa420 1339 u32 num_dma_sg;
1da177e4
LT		 1340 u32 buffer_len;
1341 struct scatterlist scatterlist[1];
1342};
1343
1344enum ipr_sdt_state {
1345 INACTIVE,
1346 WAIT_FOR_DUMP,
1347 GET_DUMP,
1348 ABORT_DUMP,
1349 DUMP_OBTAINED
1350};
1351
1352/* Per-controller data */
1353struct ipr_ioa_cfg {
1354 char eye_catcher[8];
1355#define IPR_EYECATCHER "iprcfg"
1356
1357 struct list_head queue;
1358
1359 u8 allow_interrupts:1;
1360 u8 in_reset_reload:1;
1361 u8 in_ioa_bringdown:1;
1362 u8 ioa_unit_checked:1;
1363 u8 ioa_is_dead:1;
1364 u8 dump_taken:1;
1365 u8 allow_cmds:1;
1366 u8 allow_ml_add_del:1;
ce155cce 1367 u8 needs_hard_reset:1;
ac09c349 1368 u8 dual_raid:1;
463fc696 1369 u8 needs_warm_reset:1;
95fecd90 1370 u8 msi_received:1;
a32c055f 1371 u8 sis64:1;
463fc696
BK		 1372
1373 u8 revid;
1da177e4 1374
3e7ebdfa
WB		 1375 /*
1376 * Bitmaps for SIS64 generated target values
1377 */
1378 unsigned long *target_ids;
1379 unsigned long *array_ids;
1380 unsigned long *vset_ids;
1381
1da177e4
LT		 1382 u16 type; /* CCIN of the card */
1383
1384 u8 log_level;
1385#define IPR_MAX_LOG_LEVEL 4
1386#define IPR_DEFAULT_LOG_LEVEL 2
1387
1388#define IPR_NUM_TRACE_INDEX_BITS 8
1389#define IPR_NUM_TRACE_ENTRIES (1 << IPR_NUM_TRACE_INDEX_BITS)
1390#define IPR_TRACE_SIZE (sizeof(struct ipr_trace_entry) * IPR_NUM_TRACE_ENTRIES)
1391 char trace_start[8];
1392#define IPR_TRACE_START_LABEL "trace"
1393 struct ipr_trace_entry *trace;
1394 u32 trace_index:IPR_NUM_TRACE_INDEX_BITS;
1395
1396 /*
1397 * Queue for free command blocks
1398 */
1399 char ipr_free_label[8];
1400#define IPR_FREEQ_LABEL "free-q"
1401 struct list_head free_q;
1402
1403 /*
1404 * Queue for command blocks outstanding to the adapter
1405 */
1406 char ipr_pending_label[8];
1407#define IPR_PENDQ_LABEL "pend-q"
1408 struct list_head pending_q;
1409
1410 char cfg_table_start[8];
1411#define IPR_CFG_TBL_START "cfg"
3e7ebdfa
WB		 1412 union {
1413 struct ipr_config_table *cfg_table;
1414 struct ipr_config_table64 *cfg_table64;
1415 } u;
1da177e4 1416 dma_addr_t cfg_table_dma;
3e7ebdfa
WB		 1417 u32 cfg_table_size;
1418 u32 max_devs_supported;
1da177e4
LT		 1419
1420 char resource_table_label[8];
1421#define IPR_RES_TABLE_LABEL "res_tbl"
1422 struct ipr_resource_entry *res_entries;
1423 struct list_head free_res_q;
1424 struct list_head used_res_q;
1425
1426 char ipr_hcam_label[8];
1427#define IPR_HCAM_LABEL "hcams"
1428 struct ipr_hostrcb *hostrcb[IPR_NUM_HCAMS];
1429 dma_addr_t hostrcb_dma[IPR_NUM_HCAMS];
1430 struct list_head hostrcb_free_q;
1431 struct list_head hostrcb_pending_q;
1432
1433 __be32 *host_rrq;
1434 dma_addr_t host_rrq_dma;
1435#define IPR_HRRQ_REQ_RESP_HANDLE_MASK 0xfffffffc
1436#define IPR_HRRQ_RESP_BIT_SET 0x00000002
1437#define IPR_HRRQ_TOGGLE_BIT 0x00000001
1438#define IPR_HRRQ_REQ_RESP_HANDLE_SHIFT 2
1439 volatile __be32 *hrrq_start;
1440 volatile __be32 *hrrq_end;
1441 volatile __be32 *hrrq_curr;
1442 volatile u32 toggle_bit;
1443
1444 struct ipr_bus_attributes bus_attr[IPR_MAX_NUM_BUSES];
1445
5469cb5b 1446 unsigned int transop_timeout;
1da177e4 1447 const struct ipr_chip_cfg_t *chip_cfg;
1be7bd82 1448 const struct ipr_chip_t *ipr_chip;
1da177e4
LT		 1449
1450 void __iomem *hdw_dma_regs; /* iomapped PCI memory space */
1451 unsigned long hdw_dma_regs_pci; /* raw PCI memory space */
1452 void __iomem *ioa_mailbox;
1453 struct ipr_interrupts regs;
1454
1455 u16 saved_pcix_cmd_reg;
1456 u16 reset_retries;
1457
1458 u32 errors_logged;
3d1d0da6 1459 u32 doorbell;
1da177e4
LT		 1460
1461 struct Scsi_Host *host;
1462 struct pci_dev *pdev;
1463 struct ipr_sglist *ucode_sglist;
1da177e4
LT		 1464 u8 saved_mode_page_len;
1465
1466 struct work_struct work_q;
1467
1468 wait_queue_head_t reset_wait_q;
95fecd90 1469 wait_queue_head_t msi_wait_q;
1da177e4
LT		 1470
1471 struct ipr_dump *dump;
1472 enum ipr_sdt_state sdt_state;
1473
1474 struct ipr_misc_cbs *vpd_cbs;
1475 dma_addr_t vpd_cbs_dma;
1476
1477 struct pci_pool *ipr_cmd_pool;
1478
1479 struct ipr_cmnd *reset_cmd;
463fc696 1480 int (*reset) (struct ipr_cmnd *);
1da177e4 1481
35a39691 1482 struct ata_host ata_host;
1da177e4 1483 char ipr_cmd_label[8];
0124ca9d 1484#define IPR_CMD_LABEL "ipr_cmd"
1da177e4 1485 struct ipr_cmnd *ipr_cmnd_list[IPR_NUM_CMD_BLKS];
a32c055f 1486 dma_addr_t ipr_cmnd_list_dma[IPR_NUM_CMD_BLKS];
3e7ebdfa 1487}; /* struct ipr_ioa_cfg */
1da177e4
LT		 1488
1489struct ipr_cmnd {
1490 struct ipr_ioarcb ioarcb;
a32c055f
WB		 1491 union {
1492 struct ipr_ioadl_desc ioadl[IPR_NUM_IOADL_ENTRIES];
1493 struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
1494 struct ipr_ata64_ioadl ata_ioadl;
1495 } i;
96d21f00
WB		 1496 union {
1497 struct ipr_ioasa ioasa;
1498 struct ipr_ioasa64 ioasa64;
1499 } s;
1da177e4
LT		 1500 struct list_head queue;
1501 struct scsi_cmnd *scsi_cmd;
35a39691 1502 struct ata_queued_cmd *qc;
1da177e4
LT		 1503 struct completion completion;
1504 struct timer_list timer;
1505 void (*done) (struct ipr_cmnd *);
1506 int (*job_step) (struct ipr_cmnd *);
dfed823e 1507 int (*job_step_failed) (struct ipr_cmnd *);
1da177e4
LT		 1508 u16 cmd_index;
1509 u8 sense_buffer[SCSI_SENSE_BUFFERSIZE];
1510 dma_addr_t sense_buffer_dma;
1511 unsigned short dma_use_sg;
a32c055f 1512 dma_addr_t dma_addr;
1da177e4
LT		 1513 struct ipr_cmnd *sibling;
1514 union {
1515 enum ipr_shutdown_type shutdown_type;
1516 struct ipr_hostrcb *hostrcb;
1517 unsigned long time_left;
1518 unsigned long scratch;
1519 struct ipr_resource_entry *res;
1520 struct scsi_device *sdev;
1521 } u;
1522
1523 struct ipr_ioa_cfg *ioa_cfg;
1524};
1525
1526struct ipr_ses_table_entry {
1527 char product_id[17];
1528 char compare_product_id_byte[17];
1529 u32 max_bus_speed_limit; /* MB/sec limit for this backplane */
1530};
1531
1532struct ipr_dump_header {
1533 u32 eye_catcher;
1534#define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
1535 u32 len;
1536 u32 num_entries;
1537 u32 first_entry_offset;
1538 u32 status;
1539#define IPR_DUMP_STATUS_SUCCESS 0
1540#define IPR_DUMP_STATUS_QUAL_SUCCESS 2
1541#define IPR_DUMP_STATUS_FAILED 0xffffffff
1542 u32 os;
1543#define IPR_DUMP_OS_LINUX 0x4C4E5558
1544 u32 driver_name;
1545#define IPR_DUMP_DRIVER_NAME 0x49505232
1546}__attribute__((packed, aligned (4)));
1547
1548struct ipr_dump_entry_header {
1549 u32 eye_catcher;
1550#define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
1551 u32 len;
1552 u32 num_elems;
1553 u32 offset;
1554 u32 data_type;
1555#define IPR_DUMP_DATA_TYPE_ASCII 0x41534349
1556#define IPR_DUMP_DATA_TYPE_BINARY 0x42494E41
1557 u32 id;
1558#define IPR_DUMP_IOA_DUMP_ID 0x494F4131
1559#define IPR_DUMP_LOCATION_ID 0x4C4F4341
1560#define IPR_DUMP_TRACE_ID 0x54524143
1561#define IPR_DUMP_DRIVER_VERSION_ID 0x44525652
1562#define IPR_DUMP_DRIVER_TYPE_ID 0x54595045
1563#define IPR_DUMP_IOA_CTRL_BLK 0x494F4342
1564#define IPR_DUMP_PEND_OPS 0x414F5053
1565 u32 status;
1566}__attribute__((packed, aligned (4)));
1567
1568struct ipr_dump_location_entry {
1569 struct ipr_dump_entry_header hdr;
71610f55 1570 u8 location[20];
1da177e4
LT		 1571}__attribute__((packed));
1572
1573struct ipr_dump_trace_entry {
1574 struct ipr_dump_entry_header hdr;
1575 u32 trace[IPR_TRACE_SIZE / sizeof(u32)];
1576}__attribute__((packed, aligned (4)));
1577
1578struct ipr_dump_version_entry {
1579 struct ipr_dump_entry_header hdr;
1580 u8 version[sizeof(IPR_DRIVER_VERSION)];
1581};
1582
1583struct ipr_dump_ioa_type_entry {
1584 struct ipr_dump_entry_header hdr;
1585 u32 type;
1586 u32 fw_version;
1587};
1588
1589struct ipr_driver_dump {
1590 struct ipr_dump_header hdr;
1591 struct ipr_dump_version_entry version_entry;
1592 struct ipr_dump_location_entry location_entry;
1593 struct ipr_dump_ioa_type_entry ioa_type_entry;
1594 struct ipr_dump_trace_entry trace_entry;
1595}__attribute__((packed));
1596
1597struct ipr_ioa_dump {
1598 struct ipr_dump_entry_header hdr;
1599 struct ipr_sdt sdt;
1600 __be32 *ioa_data[IPR_MAX_NUM_DUMP_PAGES];
1601 u32 reserved;
1602 u32 next_page_index;
1603 u32 page_offset;
1604 u32 format;
1da177e4
LT		 1605}__attribute__((packed, aligned (4)));
1606
1607struct ipr_dump {
1608 struct kref kref;
1609 struct ipr_ioa_cfg *ioa_cfg;
1610 struct ipr_driver_dump driver_dump;
1611 struct ipr_ioa_dump ioa_dump;
1612};
1613
1614struct ipr_error_table_t {
1615 u32 ioasc;
1616 int log_ioasa;
1617 int log_hcam;
1618 char *error;
1619};
1620
1621struct ipr_software_inq_lid_info {
1622 __be32 load_id;
1623 __be32 timestamp[3];
1624}__attribute__((packed, aligned (4)));
1625
1626struct ipr_ucode_image_header {
1627 __be32 header_length;
1628 __be32 lid_table_offset;
1629 u8 major_release;
1630 u8 card_type;
1631 u8 minor_release[2];
1632 u8 reserved[20];
1633 char eyecatcher[16];
1634 __be32 num_lids;
1635 struct ipr_software_inq_lid_info lid[1];
1636}__attribute__((packed, aligned (4)));
1637
1638/*
1639 * Macros
1640 */
d3c74871 1641#define IPR_DBG_CMD(CMD) if (ipr_debug) { CMD; }
1da177e4
LT		 1642
1643#ifdef CONFIG_SCSI_IPR_TRACE
1644#define ipr_create_trace_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1645#define ipr_remove_trace_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1646#else
1647#define ipr_create_trace_file(kobj, attr) 0
1648#define ipr_remove_trace_file(kobj, attr) do { } while(0)
1649#endif
1650
1651#ifdef CONFIG_SCSI_IPR_DUMP
1652#define ipr_create_dump_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1653#define ipr_remove_dump_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1654#else
1655#define ipr_create_dump_file(kobj, attr) 0
1656#define ipr_remove_dump_file(kobj, attr) do { } while(0)
1657#endif
1658
1659/*
1660 * Error logging macros
1661 */
1662#define ipr_err(...) printk(KERN_ERR IPR_NAME ": "__VA_ARGS__)
1663#define ipr_info(...) printk(KERN_INFO IPR_NAME ": "__VA_ARGS__)
1da177e4
LT		 1664#define ipr_dbg(...) IPR_DBG_CMD(printk(KERN_INFO IPR_NAME ": "__VA_ARGS__))
1665
3e7ebdfa
WB		 1666#define ipr_res_printk(level, ioa_cfg, bus, target, lun, fmt, ...) \
1667 printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1668 bus, target, lun, ##__VA_ARGS__)
1669
1670#define ipr_res_err(ioa_cfg, res, fmt, ...) \
1671 ipr_res_printk(KERN_ERR, ioa_cfg, (res)->bus, (res)->target, (res)->lun, fmt, ##__VA_ARGS__)
1672
fb3ed3cb
BK		 1673#define ipr_ra_printk(level, ioa_cfg, ra, fmt, ...) \
1674 printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1675 (ra).bus, (ra).target, (ra).lun, ##__VA_ARGS__)
1da177e4 1676
fb3ed3cb
BK		 1677#define ipr_ra_err(ioa_cfg, ra, fmt, ...) \
1678 ipr_ra_printk(KERN_ERR, ioa_cfg, ra, fmt, ##__VA_ARGS__)
1da177e4 1679
fa15b1f6 1680#define ipr_phys_res_err(ioa_cfg, res, fmt, ...) \
1681{ \
1682 if ((res).bus >= IPR_MAX_NUM_BUSES) { \
1683 ipr_err(fmt": unknown\n", ##__VA_ARGS__); \
1684 } else { \
1685 ipr_err(fmt": %d:%d:%d:%d\n", \
1686 ##__VA_ARGS__, (ioa_cfg)->host->host_no, \
1687 (res).bus, (res).target, (res).lun); \
1688 } \
1689}
1690
49dc6a18 1691#define ipr_hcam_err(hostrcb, fmt, ...) \
4565e370
WB		 1692{ \
1693 if (ipr_is_device(hostrcb)) { \
1694 if ((hostrcb)->ioa_cfg->sis64) { \
1695 printk(KERN_ERR IPR_NAME ": %s: " fmt, \
5adcbeb3
WB		 1696 ipr_format_res_path(hostrcb->hcam.u.error64.fd_res_path, \
1697 hostrcb->rp_buffer, \
1698 sizeof(hostrcb->rp_buffer)), \
4565e370
WB		 1699 __VA_ARGS__); \
1700 } else { \
1701 ipr_ra_err((hostrcb)->ioa_cfg, \
1702 (hostrcb)->hcam.u.error.fd_res_addr, \
1703 fmt, __VA_ARGS__); \
1704 } \
1705 } else { \
1706 dev_err(&(hostrcb)->ioa_cfg->pdev->dev, fmt, __VA_ARGS__); \
1707 } \
49dc6a18
BK		 1708}
1709
1da177e4 1710#define ipr_trace ipr_dbg("%s: %s: Line: %d\n",\
cadbd4a5 1711 __FILE__, __func__, __LINE__)
1da177e4 1712
cadbd4a5
HH		 1713#define ENTER IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Entering %s\n", __func__))
1714#define LEAVE IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Leaving %s\n", __func__))
1da177e4
LT		 1715
1716#define ipr_err_separator \
1717ipr_err("----------------------------------------------------------\n")
1718
1719
1720/*
1721 * Inlines
1722 */
1723
1724/**
1725 * ipr_is_ioa_resource - Determine if a resource is the IOA
1726 * @res: resource entry struct
1727 *
1728 * Return value:
1729 * 1 if IOA / 0 if not IOA
1730 **/
1731static inline int ipr_is_ioa_resource(struct ipr_resource_entry *res)
1732{
3e7ebdfa 1733 return res->type == IPR_RES_TYPE_IOAFP;
1da177e4
LT		 1734}
1735
1736/**
1737 * ipr_is_af_dasd_device - Determine if a resource is an AF DASD
1738 * @res: resource entry struct
1739 *
1740 * Return value:
1741 * 1 if AF DASD / 0 if not AF DASD
1742 **/
1743static inline int ipr_is_af_dasd_device(struct ipr_resource_entry *res)
1744{
3e7ebdfa
WB		 1745 return res->type == IPR_RES_TYPE_AF_DASD ||
1746 res->type == IPR_RES_TYPE_REMOTE_AF_DASD;
1da177e4
LT		 1747}
1748
1749/**
1750 * ipr_is_vset_device - Determine if a resource is a VSET
1751 * @res: resource entry struct
1752 *
1753 * Return value:
1754 * 1 if VSET / 0 if not VSET
1755 **/
1756static inline int ipr_is_vset_device(struct ipr_resource_entry *res)
1757{
3e7ebdfa 1758 return res->type == IPR_RES_TYPE_VOLUME_SET;
1da177e4
LT		 1759}
1760
1761/**
1762 * ipr_is_gscsi - Determine if a resource is a generic scsi resource
1763 * @res: resource entry struct
1764 *
1765 * Return value:
1766 * 1 if GSCSI / 0 if not GSCSI
1767 **/
1768static inline int ipr_is_gscsi(struct ipr_resource_entry *res)
1769{
3e7ebdfa 1770 return res->type == IPR_RES_TYPE_GENERIC_SCSI;
1da177e4
LT		 1771}
1772
e4fbf44e
BK		 1773/**
1774 * ipr_is_scsi_disk - Determine if a resource is a SCSI disk
1775 * @res: resource entry struct
1776 *
1777 * Return value:
1778 * 1 if SCSI disk / 0 if not SCSI disk
1779 **/
1780static inline int ipr_is_scsi_disk(struct ipr_resource_entry *res)
1781{
1782 if (ipr_is_af_dasd_device(res) ||
3e7ebdfa 1783 (ipr_is_gscsi(res) && IPR_IS_DASD_DEVICE(res->std_inq_data)))
e4fbf44e
BK		 1784 return 1;
1785 else
1786 return 0;
1787}
1788
b5145d25
BK		 1789/**
1790 * ipr_is_gata - Determine if a resource is a generic ATA resource
1791 * @res: resource entry struct
1792 *
1793 * Return value:
1794 * 1 if GATA / 0 if not GATA
1795 **/
1796static inline int ipr_is_gata(struct ipr_resource_entry *res)
1797{
3e7ebdfa 1798 return res->type == IPR_RES_TYPE_GENERIC_ATA;
b5145d25
BK		 1799}
1800
ee0a90fa 1801/**
1802 * ipr_is_naca_model - Determine if a resource is using NACA queueing model
1803 * @res: resource entry struct
1804 *
1805 * Return value:
1806 * 1 if NACA queueing model / 0 if not NACA queueing model
1807 **/
1808static inline int ipr_is_naca_model(struct ipr_resource_entry *res)
1809{
3e7ebdfa 1810 if (ipr_is_gscsi(res) && res->qmodel == IPR_QUEUE_NACA_MODEL)
ee0a90fa 1811 return 1;
1812 return 0;
1813}
1814
1da177e4 1815/**
4565e370
WB		 1816 * ipr_is_device - Determine if the hostrcb structure is related to a device
1817 * @hostrcb: host resource control blocks struct
1da177e4
LT		 1818 *
1819 * Return value:
1820 * 1 if AF / 0 if not AF
1821 **/
4565e370 1822static inline int ipr_is_device(struct ipr_hostrcb *hostrcb)
1da177e4 1823{
4565e370
WB		 1824 struct ipr_res_addr *res_addr;
1825 u8 *res_path;
1826
1827 if (hostrcb->ioa_cfg->sis64) {
1828 res_path = &hostrcb->hcam.u.error64.fd_res_path[0];
1829 if ((res_path[0] == 0x00 || res_path[0] == 0x80 ||
1830 res_path[0] == 0x81) && res_path[2] != 0xFF)
1831 return 1;
1832 } else {
1833 res_addr = &hostrcb->hcam.u.error.fd_res_addr;
1834
1835 if ((res_addr->bus < IPR_MAX_NUM_BUSES) &&
1836 (res_addr->target < (IPR_MAX_NUM_TARGETS_PER_BUS - 1)))
1837 return 1;
1838 }
1da177e4
LT		 1839 return 0;
1840}
1841
1842/**
1843 * ipr_sdt_is_fmt2 - Determine if a SDT address is in format 2
1844 * @sdt_word: SDT address
1845 *
1846 * Return value:
1847 * 1 if format 2 / 0 if not
1848 **/
1849static inline int ipr_sdt_is_fmt2(u32 sdt_word)
1850{
1851 u32 bar_sel = IPR_GET_FMT2_BAR_SEL(sdt_word);
1852
1853 switch (bar_sel) {
1854 case IPR_SDT_FMT2_BAR0_SEL:
1855 case IPR_SDT_FMT2_BAR1_SEL:
1856 case IPR_SDT_FMT2_BAR2_SEL:
1857 case IPR_SDT_FMT2_BAR3_SEL:
1858 case IPR_SDT_FMT2_BAR4_SEL:
1859 case IPR_SDT_FMT2_BAR5_SEL:
1860 case IPR_SDT_FMT2_EXP_ROM_SEL:
1861 return 1;
1862 };
1863
1864 return 0;
1865}
1866
c5f10187
WB		 1867#ifndef writeq
1868static inline void writeq(u64 val, void __iomem *addr)
1869{
1870 writel(((u32) (val >> 32)), addr);
1871 writel(((u32) (val)), (addr + 4));
1872}
1da177e4 1873#endif
c5f10187
WB		 1874
1875#endif /* _IPR_H */
Linux kernel - Deliverables
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