projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[SCSI] qla2xxx: Update version number to 8.01.07-k7.
[deliverable/linux.git] / drivers / scsi / ipr.h
CommitLineData
1da177e4
LT		 1/*
2 * ipr.h -- driver for IBM Power Linux RAID adapters
3 *
4 * Written By: Brian King <brking@us.ibm.com>, IBM Corporation
5 *
6 * Copyright (C) 2003, 2004 IBM Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 * Alan Cox <alan@redhat.com> - Removed several careless u32/dma_addr_t errors
23 * that broke 64bit platforms.
24 */
25
26#ifndef _IPR_H
27#define _IPR_H
28
29#include <linux/types.h>
30#include <linux/completion.h>
35a39691 31#include <linux/libata.h>
1da177e4
LT		 32#include <linux/list.h>
33#include <linux/kref.h>
34#include <scsi/scsi.h>
35#include <scsi/scsi_cmnd.h>
36
37/*
38 * Literals
39 */
ac09c349
BK		 40#define IPR_DRIVER_VERSION "2.4.0"
41#define IPR_DRIVER_DATE "(April 24, 2007)"
1da177e4 42
1da177e4
LT		 43/*
44 * IPR_MAX_CMD_PER_LUN: This defines the maximum number of outstanding
45 * ops per device for devices not running tagged command queuing.
46 * This can be adjusted at runtime through sysfs device attributes.
47 */
48#define IPR_MAX_CMD_PER_LUN 6
b5145d25 49#define IPR_MAX_CMD_PER_ATA_LUN 1
1da177e4
LT		 50
51/*
52 * IPR_NUM_BASE_CMD_BLKS: This defines the maximum number of
53 * ops the mid-layer can send to the adapter.
54 */
55#define IPR_NUM_BASE_CMD_BLKS 100
56
60e7486b 57#define PCI_DEVICE_ID_IBM_OBSIDIAN_E 0x0339
185eb31c 58#define PCI_DEVICE_ID_IBM_SCAMP_E 0x034A
60e7486b 59
1da177e4
LT		 60#define IPR_SUBS_DEV_ID_2780 0x0264
61#define IPR_SUBS_DEV_ID_5702 0x0266
62#define IPR_SUBS_DEV_ID_5703 0x0278
63#define IPR_SUBS_DEV_ID_572E 0x028D
64#define IPR_SUBS_DEV_ID_573E 0x02D3
65#define IPR_SUBS_DEV_ID_573D 0x02D4
66#define IPR_SUBS_DEV_ID_571A 0x02C0
67#define IPR_SUBS_DEV_ID_571B 0x02BE
68#define IPR_SUBS_DEV_ID_571E 0x02BF
86f51436 69#define IPR_SUBS_DEV_ID_571F 0x02D5
70#define IPR_SUBS_DEV_ID_572A 0x02C1
71#define IPR_SUBS_DEV_ID_572B 0x02C2
60e7486b 72#define IPR_SUBS_DEV_ID_572F 0x02C3
185eb31c
BK		 73#define IPR_SUBS_DEV_ID_574D 0x030B
74#define IPR_SUBS_DEV_ID_574E 0x030A
86f51436 75#define IPR_SUBS_DEV_ID_575B 0x030D
60e7486b 76#define IPR_SUBS_DEV_ID_575C 0x0338
185eb31c
BK		 77#define IPR_SUBS_DEV_ID_575D 0x033E
78#define IPR_SUBS_DEV_ID_57B3 0x033A
60e7486b
BK		 79#define IPR_SUBS_DEV_ID_57B7 0x0360
80#define IPR_SUBS_DEV_ID_57B8 0x02C2
1da177e4
LT		 81
82#define IPR_NAME "ipr"
83
84/*
85 * Return codes
86 */
87#define IPR_RC_JOB_CONTINUE 1
88#define IPR_RC_JOB_RETURN 2
89
90/*
91 * IOASCs
92 */
93#define IPR_IOASC_NR_INIT_CMD_REQUIRED 0x02040200
65f56475 94#define IPR_IOASC_NR_IOA_RESET_REQUIRED 0x02048000
1da177e4
LT		 95#define IPR_IOASC_SYNC_REQUIRED 0x023f0000
96#define IPR_IOASC_MED_DO_NOT_REALLOC 0x03110C00
97#define IPR_IOASC_HW_SEL_TIMEOUT 0x04050000
98#define IPR_IOASC_HW_DEV_BUS_STATUS 0x04448500
99#define IPR_IOASC_IOASC_MASK 0xFFFFFF00
100#define IPR_IOASC_SCSI_STATUS_MASK 0x000000FF
dfed823e 101#define IPR_IOASC_IR_INVALID_REQ_TYPE_OR_PKT 0x05240000
1da177e4 102#define IPR_IOASC_IR_RESOURCE_HANDLE 0x05250000
b0df54bb 103#define IPR_IOASC_IR_NO_CMDS_TO_2ND_IOA 0x05258100
104#define IPR_IOASA_IR_DUAL_IOA_DISABLED 0x052C8000
1da177e4
LT		 105#define IPR_IOASC_BUS_WAS_RESET 0x06290000
106#define IPR_IOASC_BUS_WAS_RESET_BY_OTHER 0x06298000
107#define IPR_IOASC_ABORTED_CMD_TERM_BY_HOST 0x0B5A0000
108
109#define IPR_FIRST_DRIVER_IOASC 0x10000000
110#define IPR_IOASC_IOA_WAS_RESET 0x10000001
111#define IPR_IOASC_PCI_ACCESS_ERROR 0x10000002
112
5469cb5b
BK		 113/* Driver data flags */
114#define IPR_USE_LONG_TRANSOP_TIMEOUT 0x00000001
115
ac719aba 116#define IPR_DEFAULT_MAX_ERROR_DUMP 984
1da177e4
LT		 117#define IPR_NUM_LOG_HCAMS 2
118#define IPR_NUM_CFG_CHG_HCAMS 2
119#define IPR_NUM_HCAMS (IPR_NUM_LOG_HCAMS + IPR_NUM_CFG_CHG_HCAMS)
d71a8b0c 120#define IPR_MAX_NUM_TARGETS_PER_BUS 256
1da177e4
LT		 121#define IPR_MAX_NUM_LUNS_PER_TARGET 256
122#define IPR_MAX_NUM_VSET_LUNS_PER_TARGET 8
123#define IPR_VSET_BUS 0xff
124#define IPR_IOA_BUS 0xff
125#define IPR_IOA_TARGET 0xff
126#define IPR_IOA_LUN 0xff
b5145d25 127#define IPR_MAX_NUM_BUSES 16
1da177e4
LT		 128#define IPR_MAX_BUS_TO_SCAN IPR_MAX_NUM_BUSES
129
130#define IPR_NUM_RESET_RELOAD_RETRIES 3
131
132/* We need resources for HCAMS, IOA reset, IOA bringdown, and ERP */
133#define IPR_NUM_INTERNAL_CMD_BLKS (IPR_NUM_HCAMS + \
134 ((IPR_NUM_RESET_RELOAD_RETRIES + 1) * 2) + 3)
135
136#define IPR_MAX_COMMANDS IPR_NUM_BASE_CMD_BLKS
137#define IPR_NUM_CMD_BLKS (IPR_NUM_BASE_CMD_BLKS + \
138 IPR_NUM_INTERNAL_CMD_BLKS)
139
140#define IPR_MAX_PHYSICAL_DEVS 192
141
142#define IPR_MAX_SGLIST 64
143#define IPR_IOA_MAX_SECTORS 32767
144#define IPR_VSET_MAX_SECTORS 512
145#define IPR_MAX_CDB_LEN 16
146
147#define IPR_DEFAULT_BUS_WIDTH 16
148#define IPR_80MBs_SCSI_RATE ((80 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
149#define IPR_U160_SCSI_RATE ((160 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
150#define IPR_U320_SCSI_RATE ((320 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
151#define IPR_MAX_SCSI_RATE(width) ((320 * 10) / ((width) / 8))
152
153#define IPR_IOA_RES_HANDLE 0xffffffff
1121b794 154#define IPR_INVALID_RES_HANDLE 0
1da177e4
LT		 155#define IPR_IOA_RES_ADDR 0x00ffffff
156
157/*
158 * Adapter Commands
159 */
160#define IPR_QUERY_RSRC_STATE 0xC2
161#define IPR_RESET_DEVICE 0xC3
162#define IPR_RESET_TYPE_SELECT 0x80
163#define IPR_LUN_RESET 0x40
164#define IPR_TARGET_RESET 0x20
165#define IPR_BUS_RESET 0x10
b5145d25 166#define IPR_ATA_PHY_RESET 0x80
1da177e4
LT		 167#define IPR_ID_HOST_RR_Q 0xC4
168#define IPR_QUERY_IOA_CONFIG 0xC5
169#define IPR_CANCEL_ALL_REQUESTS 0xCE
170#define IPR_HOST_CONTROLLED_ASYNC 0xCF
171#define IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE 0x01
172#define IPR_HCAM_CDB_OP_CODE_LOG_DATA 0x02
173#define IPR_SET_SUPPORTED_DEVICES 0xFB
174#define IPR_IOA_SHUTDOWN 0xF7
175#define IPR_WR_BUF_DOWNLOAD_AND_SAVE 0x05
176
177/*
178 * Timeouts
179 */
180#define IPR_SHUTDOWN_TIMEOUT (ipr_fastfail ? 60 * HZ : 10 * 60 * HZ)
181#define IPR_VSET_RW_TIMEOUT (ipr_fastfail ? 30 * HZ : 2 * 60 * HZ)
182#define IPR_ABBREV_SHUTDOWN_TIMEOUT (10 * HZ)
ac09c349 183#define IPR_DUAL_IOA_ABBR_SHUTDOWN_TO (2 * 60 * HZ)
1da177e4
LT		 184#define IPR_DEVICE_RESET_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
185#define IPR_CANCEL_ALL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
186#define IPR_ABORT_TASK_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
187#define IPR_INTERNAL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
188#define IPR_WRITE_BUFFER_TIMEOUT (10 * 60 * HZ)
189#define IPR_SET_SUP_DEVICE_TIMEOUT (2 * 60 * HZ)
190#define IPR_REQUEST_SENSE_TIMEOUT (10 * HZ)
191#define IPR_OPERATIONAL_TIMEOUT (5 * 60)
5469cb5b 192#define IPR_LONG_OPERATIONAL_TIMEOUT (12 * 60)
1da177e4
LT		 193#define IPR_WAIT_FOR_RESET_TIMEOUT (2 * HZ)
194#define IPR_CHECK_FOR_RESET_TIMEOUT (HZ / 10)
195#define IPR_WAIT_FOR_BIST_TIMEOUT (2 * HZ)
196#define IPR_DUMP_TIMEOUT (15 * HZ)
197
198/*
199 * SCSI Literals
200 */
201#define IPR_VENDOR_ID_LEN 8
202#define IPR_PROD_ID_LEN 16
203#define IPR_SERIAL_NUM_LEN 8
204
205/*
206 * Hardware literals
207 */
208#define IPR_FMT2_MBX_ADDR_MASK 0x0fffffff
209#define IPR_FMT2_MBX_BAR_SEL_MASK 0xf0000000
210#define IPR_FMT2_MKR_BAR_SEL_SHIFT 28
211#define IPR_GET_FMT2_BAR_SEL(mbx) \
212(((mbx) & IPR_FMT2_MBX_BAR_SEL_MASK) >> IPR_FMT2_MKR_BAR_SEL_SHIFT)
213#define IPR_SDT_FMT2_BAR0_SEL 0x0
214#define IPR_SDT_FMT2_BAR1_SEL 0x1
215#define IPR_SDT_FMT2_BAR2_SEL 0x2
216#define IPR_SDT_FMT2_BAR3_SEL 0x3
217#define IPR_SDT_FMT2_BAR4_SEL 0x4
218#define IPR_SDT_FMT2_BAR5_SEL 0x5
219#define IPR_SDT_FMT2_EXP_ROM_SEL 0x8
220#define IPR_FMT2_SDT_READY_TO_USE 0xC4D4E3F2
221#define IPR_DOORBELL 0x82800000
3d1d0da6 222#define IPR_RUNTIME_RESET 0x40000000
1da177e4
LT		 223
224#define IPR_PCII_IOA_TRANS_TO_OPER (0x80000000 >> 0)
225#define IPR_PCII_IOARCB_XFER_FAILED (0x80000000 >> 3)
226#define IPR_PCII_IOA_UNIT_CHECKED (0x80000000 >> 4)
227#define IPR_PCII_NO_HOST_RRQ (0x80000000 >> 5)
228#define IPR_PCII_CRITICAL_OPERATION (0x80000000 >> 6)
229#define IPR_PCII_IO_DEBUG_ACKNOWLEDGE (0x80000000 >> 7)
230#define IPR_PCII_IOARRIN_LOST (0x80000000 >> 27)
231#define IPR_PCII_MMIO_ERROR (0x80000000 >> 28)
232#define IPR_PCII_PROC_ERR_STATE (0x80000000 >> 29)
233#define IPR_PCII_HRRQ_UPDATED (0x80000000 >> 30)
234#define IPR_PCII_CORE_ISSUED_RST_REQ (0x80000000 >> 31)
235
236#define IPR_PCII_ERROR_INTERRUPTS \
237(IPR_PCII_IOARCB_XFER_FAILED | IPR_PCII_IOA_UNIT_CHECKED | \
238IPR_PCII_NO_HOST_RRQ | IPR_PCII_IOARRIN_LOST | IPR_PCII_MMIO_ERROR)
239
240#define IPR_PCII_OPER_INTERRUPTS \
241(IPR_PCII_ERROR_INTERRUPTS | IPR_PCII_HRRQ_UPDATED | IPR_PCII_IOA_TRANS_TO_OPER)
242
243#define IPR_UPROCI_RESET_ALERT (0x80000000 >> 7)
244#define IPR_UPROCI_IO_DEBUG_ALERT (0x80000000 >> 9)
245
246#define IPR_LDUMP_MAX_LONG_ACK_DELAY_IN_USEC 200000 /* 200 ms */
247#define IPR_LDUMP_MAX_SHORT_ACK_DELAY_IN_USEC 200000 /* 200 ms */
248
249/*
250 * Dump literals
251 */
252#define IPR_MAX_IOA_DUMP_SIZE (4 * 1024 * 1024)
253#define IPR_NUM_SDT_ENTRIES 511
254#define IPR_MAX_NUM_DUMP_PAGES ((IPR_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1)
255
256/*
257 * Misc literals
258 */
259#define IPR_NUM_IOADL_ENTRIES IPR_MAX_SGLIST
260
261/*
262 * Adapter interface types
263 */
264
265struct ipr_res_addr {
266 u8 reserved;
267 u8 bus;
268 u8 target;
269 u8 lun;
270#define IPR_GET_PHYS_LOC(res_addr) \
271 (((res_addr).bus << 16) | ((res_addr).target << 8) | (res_addr).lun)
272}__attribute__((packed, aligned (4)));
273
274struct ipr_std_inq_vpids {
275 u8 vendor_id[IPR_VENDOR_ID_LEN];
276 u8 product_id[IPR_PROD_ID_LEN];
277}__attribute__((packed));
278
cfc32139 279struct ipr_vpd {
280 struct ipr_std_inq_vpids vpids;
281 u8 sn[IPR_SERIAL_NUM_LEN];
282}__attribute__((packed));
283
ee0f05b8 284struct ipr_ext_vpd {
285 struct ipr_vpd vpd;
286 __be32 wwid[2];
287}__attribute__((packed));
288
1da177e4
LT		 289struct ipr_std_inq_data {
290 u8 peri_qual_dev_type;
291#define IPR_STD_INQ_PERI_QUAL(peri) ((peri) >> 5)
292#define IPR_STD_INQ_PERI_DEV_TYPE(peri) ((peri) & 0x1F)
293
294 u8 removeable_medium_rsvd;
295#define IPR_STD_INQ_REMOVEABLE_MEDIUM 0x80
296
297#define IPR_IS_DASD_DEVICE(std_inq) \
298((IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_DISK) && \
299!(((std_inq).removeable_medium_rsvd) & IPR_STD_INQ_REMOVEABLE_MEDIUM))
300
301#define IPR_IS_SES_DEVICE(std_inq) \
302(IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_ENCLOSURE)
303
304 u8 version;
305 u8 aen_naca_fmt;
306 u8 additional_len;
307 u8 sccs_rsvd;
308 u8 bq_enc_multi;
309 u8 sync_cmdq_flags;
310
311 struct ipr_std_inq_vpids vpids;
312
313 u8 ros_rsvd_ram_rsvd[4];
314
315 u8 serial_num[IPR_SERIAL_NUM_LEN];
316}__attribute__ ((packed));
317
318struct ipr_config_table_entry {
b5145d25
BK		 319 u8 proto;
320#define IPR_PROTO_SATA 0x02
321#define IPR_PROTO_SATA_ATAPI 0x03
322#define IPR_PROTO_SAS_STP 0x06
323#define IPR_PROTO_SAS_STP_ATAPI 0x07
1da177e4
LT		 324 u8 array_id;
325 u8 flags;
326#define IPR_IS_IOA_RESOURCE 0x80
327#define IPR_IS_ARRAY_MEMBER 0x20
328#define IPR_IS_HOT_SPARE 0x10
329
330 u8 rsvd_subtype;
331#define IPR_RES_SUBTYPE(res) (((res)->cfgte.rsvd_subtype) & 0x0f)
332#define IPR_SUBTYPE_AF_DASD 0
333#define IPR_SUBTYPE_GENERIC_SCSI 1
334#define IPR_SUBTYPE_VOLUME_SET 2
b5145d25 335#define IPR_SUBTYPE_GENERIC_ATA 4
1da177e4 336
ee0a90fa 337#define IPR_QUEUEING_MODEL(res) ((((res)->cfgte.flags) & 0x70) >> 4)
338#define IPR_QUEUE_FROZEN_MODEL 0
339#define IPR_QUEUE_NACA_MODEL 1
340
1da177e4
LT		 341 struct ipr_res_addr res_addr;
342 __be32 res_handle;
343 __be32 reserved4[2];
344 struct ipr_std_inq_data std_inq_data;
345}__attribute__ ((packed, aligned (4)));
346
347struct ipr_config_table_hdr {
348 u8 num_entries;
349 u8 flags;
350#define IPR_UCODE_DOWNLOAD_REQ 0x10
351 __be16 reserved;
352}__attribute__((packed, aligned (4)));
353
354struct ipr_config_table {
355 struct ipr_config_table_hdr hdr;
356 struct ipr_config_table_entry dev[IPR_MAX_PHYSICAL_DEVS];
357}__attribute__((packed, aligned (4)));
358
359struct ipr_hostrcb_cfg_ch_not {
360 struct ipr_config_table_entry cfgte;
361 u8 reserved[936];
362}__attribute__((packed, aligned (4)));
363
364struct ipr_supported_device {
365 __be16 data_length;
366 u8 reserved;
367 u8 num_records;
368 struct ipr_std_inq_vpids vpids;
369 u8 reserved2[16];
370}__attribute__((packed, aligned (4)));
371
372/* Command packet structure */
373struct ipr_cmd_pkt {
374 __be16 reserved; /* Reserved by IOA */
375 u8 request_type;
376#define IPR_RQTYPE_SCSICDB 0x00
377#define IPR_RQTYPE_IOACMD 0x01
378#define IPR_RQTYPE_HCAM 0x02
b5145d25 379#define IPR_RQTYPE_ATA_PASSTHRU 0x04
1da177e4
LT		 380
381 u8 luntar_luntrn;
382
383 u8 flags_hi;
384#define IPR_FLAGS_HI_WRITE_NOT_READ 0x80
385#define IPR_FLAGS_HI_NO_ULEN_CHK 0x20
386#define IPR_FLAGS_HI_SYNC_OVERRIDE 0x10
387#define IPR_FLAGS_HI_SYNC_COMPLETE 0x08
388#define IPR_FLAGS_HI_NO_LINK_DESC 0x04
389
390 u8 flags_lo;
391#define IPR_FLAGS_LO_ALIGNED_BFR 0x20
392#define IPR_FLAGS_LO_DELAY_AFTER_RST 0x10
393#define IPR_FLAGS_LO_UNTAGGED_TASK 0x00
394#define IPR_FLAGS_LO_SIMPLE_TASK 0x02
395#define IPR_FLAGS_LO_ORDERED_TASK 0x04
396#define IPR_FLAGS_LO_HEAD_OF_Q_TASK 0x06
397#define IPR_FLAGS_LO_ACA_TASK 0x08
398
399 u8 cdb[16];
400 __be16 timeout;
401}__attribute__ ((packed, aligned(4)));
402
b5145d25
BK		 403struct ipr_ioarcb_ata_regs {
404 u8 flags;
405#define IPR_ATA_FLAG_PACKET_CMD 0x80
406#define IPR_ATA_FLAG_XFER_TYPE_DMA 0x40
407#define IPR_ATA_FLAG_STATUS_ON_GOOD_COMPLETION 0x20
408 u8 reserved[3];
409
410 __be16 data;
411 u8 feature;
412 u8 nsect;
413 u8 lbal;
414 u8 lbam;
415 u8 lbah;
416 u8 device;
417 u8 command;
418 u8 reserved2[3];
419 u8 hob_feature;
420 u8 hob_nsect;
421 u8 hob_lbal;
422 u8 hob_lbam;
423 u8 hob_lbah;
424 u8 ctl;
425}__attribute__ ((packed, aligned(4)));
426
51b1c7e1
BK		 427struct ipr_ioadl_desc {
428 __be32 flags_and_data_len;
429#define IPR_IOADL_FLAGS_MASK 0xff000000
430#define IPR_IOADL_GET_FLAGS(x) (be32_to_cpu(x) & IPR_IOADL_FLAGS_MASK)
431#define IPR_IOADL_DATA_LEN_MASK 0x00ffffff
432#define IPR_IOADL_GET_DATA_LEN(x) (be32_to_cpu(x) & IPR_IOADL_DATA_LEN_MASK)
433#define IPR_IOADL_FLAGS_READ 0x48000000
434#define IPR_IOADL_FLAGS_READ_LAST 0x49000000
435#define IPR_IOADL_FLAGS_WRITE 0x68000000
436#define IPR_IOADL_FLAGS_WRITE_LAST 0x69000000
437#define IPR_IOADL_FLAGS_LAST 0x01000000
438
439 __be32 address;
440}__attribute__((packed, aligned (8)));
441
b5145d25
BK		 442struct ipr_ioarcb_add_data {
443 union {
444 struct ipr_ioarcb_ata_regs regs;
51b1c7e1 445 struct ipr_ioadl_desc ioadl[5];
b5145d25
BK		 446 __be32 add_cmd_parms[10];
447 }u;
448}__attribute__ ((packed, aligned(4)));
449
1da177e4
LT		 450/* IOA Request Control Block 128 bytes */
451struct ipr_ioarcb {
452 __be32 ioarcb_host_pci_addr;
453 __be32 reserved;
454 __be32 res_handle;
455 __be32 host_response_handle;
456 __be32 reserved1;
457 __be32 reserved2;
458 __be32 reserved3;
459
460 __be32 write_data_transfer_length;
461 __be32 read_data_transfer_length;
462 __be32 write_ioadl_addr;
463 __be32 write_ioadl_len;
464 __be32 read_ioadl_addr;
465 __be32 read_ioadl_len;
466
467 __be32 ioasa_host_pci_addr;
468 __be16 ioasa_len;
469 __be16 reserved4;
470
471 struct ipr_cmd_pkt cmd_pkt;
472
473 __be32 add_cmd_parms_len;
b5145d25 474 struct ipr_ioarcb_add_data add_data;
1da177e4
LT		 475}__attribute__((packed, aligned (4)));
476
1da177e4
LT		 477struct ipr_ioasa_vset {
478 __be32 failing_lba_hi;
479 __be32 failing_lba_lo;
c8f74892 480 __be32 reserved;
1da177e4
LT		 481}__attribute__((packed, aligned (4)));
482
483struct ipr_ioasa_af_dasd {
484 __be32 failing_lba;
c8f74892 485 __be32 reserved[2];
1da177e4
LT		 486}__attribute__((packed, aligned (4)));
487
488struct ipr_ioasa_gpdd {
489 u8 end_state;
490 u8 bus_phase;
491 __be16 reserved;
c8f74892 492 __be32 ioa_data[2];
1da177e4
LT		 493}__attribute__((packed, aligned (4)));
494
b5145d25
BK		 495struct ipr_ioasa_gata {
496 u8 error;
497 u8 nsect; /* Interrupt reason */
498 u8 lbal;
499 u8 lbam;
500 u8 lbah;
501 u8 device;
502 u8 status;
503 u8 alt_status; /* ATA CTL */
504 u8 hob_nsect;
505 u8 hob_lbal;
506 u8 hob_lbam;
507 u8 hob_lbah;
508}__attribute__((packed, aligned (4)));
509
c8f74892 510struct ipr_auto_sense {
511 __be16 auto_sense_len;
512 __be16 ioa_data_len;
513 __be32 data[SCSI_SENSE_BUFFERSIZE/sizeof(__be32)];
514};
1da177e4
LT		 515
516struct ipr_ioasa {
517 __be32 ioasc;
518#define IPR_IOASC_SENSE_KEY(ioasc) ((ioasc) >> 24)
519#define IPR_IOASC_SENSE_CODE(ioasc) (((ioasc) & 0x00ff0000) >> 16)
520#define IPR_IOASC_SENSE_QUAL(ioasc) (((ioasc) & 0x0000ff00) >> 8)
521#define IPR_IOASC_SENSE_STATUS(ioasc) ((ioasc) & 0x000000ff)
522
523 __be16 ret_stat_len; /* Length of the returned IOASA */
524
525 __be16 avail_stat_len; /* Total Length of status available. */
526
527 __be32 residual_data_len; /* number of bytes in the host data */
528 /* buffers that were not used by the IOARCB command. */
529
530 __be32 ilid;
531#define IPR_NO_ILID 0
532#define IPR_DRIVER_ILID 0xffffffff
533
534 __be32 fd_ioasc;
535
536 __be32 fd_phys_locator;
537
538 __be32 fd_res_handle;
539
540 __be32 ioasc_specific; /* status code specific field */
c8f74892 541#define IPR_ADDITIONAL_STATUS_FMT 0x80000000
542#define IPR_AUTOSENSE_VALID 0x40000000
b5145d25 543#define IPR_ATA_DEVICE_WAS_RESET 0x20000000
1da177e4
LT		 544#define IPR_IOASC_SPECIFIC_MASK 0x00ffffff
545#define IPR_FIELD_POINTER_VALID (0x80000000 >> 8)
546#define IPR_FIELD_POINTER_MASK 0x0000ffff
547
548 union {
549 struct ipr_ioasa_vset vset;
550 struct ipr_ioasa_af_dasd dasd;
551 struct ipr_ioasa_gpdd gpdd;
b5145d25 552 struct ipr_ioasa_gata gata;
1da177e4 553 } u;
c8f74892 554
555 struct ipr_auto_sense auto_sense;
1da177e4
LT		 556}__attribute__((packed, aligned (4)));
557
558struct ipr_mode_parm_hdr {
559 u8 length;
560 u8 medium_type;
561 u8 device_spec_parms;
562 u8 block_desc_len;
563}__attribute__((packed));
564
565struct ipr_mode_pages {
566 struct ipr_mode_parm_hdr hdr;
567 u8 data[255 - sizeof(struct ipr_mode_parm_hdr)];
568}__attribute__((packed));
569
570struct ipr_mode_page_hdr {
571 u8 ps_page_code;
572#define IPR_MODE_PAGE_PS 0x80
573#define IPR_GET_MODE_PAGE_CODE(hdr) ((hdr)->ps_page_code & 0x3F)
574 u8 page_length;
575}__attribute__ ((packed));
576
577struct ipr_dev_bus_entry {
578 struct ipr_res_addr res_addr;
579 u8 flags;
580#define IPR_SCSI_ATTR_ENABLE_QAS 0x80
581#define IPR_SCSI_ATTR_DISABLE_QAS 0x40
582#define IPR_SCSI_ATTR_QAS_MASK 0xC0
583#define IPR_SCSI_ATTR_ENABLE_TM 0x20
584#define IPR_SCSI_ATTR_NO_TERM_PWR 0x10
585#define IPR_SCSI_ATTR_TM_SUPPORTED 0x08
586#define IPR_SCSI_ATTR_LVD_TO_SE_NOT_ALLOWED 0x04
587
588 u8 scsi_id;
589 u8 bus_width;
590 u8 extended_reset_delay;
591#define IPR_EXTENDED_RESET_DELAY 7
592
593 __be32 max_xfer_rate;
594
595 u8 spinup_delay;
596 u8 reserved3;
597 __be16 reserved4;
598}__attribute__((packed, aligned (4)));
599
600struct ipr_mode_page28 {
601 struct ipr_mode_page_hdr hdr;
602 u8 num_entries;
603 u8 entry_length;
604 struct ipr_dev_bus_entry bus[0];
605}__attribute__((packed));
606
ac09c349
BK		 607struct ipr_mode_page24 {
608 struct ipr_mode_page_hdr hdr;
609 u8 flags;
610#define IPR_ENABLE_DUAL_IOA_AF 0x80
611}__attribute__((packed));
612
1da177e4
LT		 613struct ipr_ioa_vpd {
614 struct ipr_std_inq_data std_inq_data;
615 u8 ascii_part_num[12];
616 u8 reserved[40];
617 u8 ascii_plant_code[4];
618}__attribute__((packed));
619
620struct ipr_inquiry_page3 {
621 u8 peri_qual_dev_type;
622 u8 page_code;
623 u8 reserved1;
624 u8 page_length;
625 u8 ascii_len;
626 u8 reserved2[3];
627 u8 load_id[4];
628 u8 major_release;
629 u8 card_type;
630 u8 minor_release[2];
631 u8 ptf_number[4];
632 u8 patch_number[4];
633}__attribute__((packed));
634
ac09c349
BK		 635struct ipr_inquiry_cap {
636 u8 peri_qual_dev_type;
637 u8 page_code;
638 u8 reserved1;
639 u8 page_length;
640 u8 ascii_len;
641 u8 reserved2;
642 u8 sis_version[2];
643 u8 cap;
644#define IPR_CAP_DUAL_IOA_RAID 0x80
645 u8 reserved3[15];
646}__attribute__((packed));
647
62275040 648#define IPR_INQUIRY_PAGE0_ENTRIES 20
649struct ipr_inquiry_page0 {
650 u8 peri_qual_dev_type;
651 u8 page_code;
652 u8 reserved1;
653 u8 len;
654 u8 page[IPR_INQUIRY_PAGE0_ENTRIES];
655}__attribute__((packed));
656
1da177e4 657struct ipr_hostrcb_device_data_entry {
cfc32139 658 struct ipr_vpd vpd;
1da177e4 659 struct ipr_res_addr dev_res_addr;
cfc32139 660 struct ipr_vpd new_vpd;
661 struct ipr_vpd ioa_last_with_dev_vpd;
662 struct ipr_vpd cfc_last_with_dev_vpd;
1da177e4
LT		 663 __be32 ioa_data[5];
664}__attribute__((packed, aligned (4)));
665
ee0f05b8 666struct ipr_hostrcb_device_data_entry_enhanced {
667 struct ipr_ext_vpd vpd;
668 u8 ccin[4];
669 struct ipr_res_addr dev_res_addr;
670 struct ipr_ext_vpd new_vpd;
671 u8 new_ccin[4];
672 struct ipr_ext_vpd ioa_last_with_dev_vpd;
673 struct ipr_ext_vpd cfc_last_with_dev_vpd;
674}__attribute__((packed, aligned (4)));
675
1da177e4 676struct ipr_hostrcb_array_data_entry {
cfc32139 677 struct ipr_vpd vpd;
1da177e4
LT		 678 struct ipr_res_addr expected_dev_res_addr;
679 struct ipr_res_addr dev_res_addr;
680}__attribute__((packed, aligned (4)));
681
ee0f05b8 682struct ipr_hostrcb_array_data_entry_enhanced {
683 struct ipr_ext_vpd vpd;
684 u8 ccin[4];
685 struct ipr_res_addr expected_dev_res_addr;
686 struct ipr_res_addr dev_res_addr;
687}__attribute__((packed, aligned (4)));
688
1da177e4 689struct ipr_hostrcb_type_ff_error {
ee0f05b8 690 __be32 ioa_data[502];
1da177e4
LT		 691}__attribute__((packed, aligned (4)));
692
693struct ipr_hostrcb_type_01_error {
694 __be32 seek_counter;
695 __be32 read_counter;
696 u8 sense_data[32];
697 __be32 ioa_data[236];
698}__attribute__((packed, aligned (4)));
699
700struct ipr_hostrcb_type_02_error {
cfc32139 701 struct ipr_vpd ioa_vpd;
702 struct ipr_vpd cfc_vpd;
703 struct ipr_vpd ioa_last_attached_to_cfc_vpd;
704 struct ipr_vpd cfc_last_attached_to_ioa_vpd;
1da177e4 705 __be32 ioa_data[3];
1da177e4
LT		 706}__attribute__((packed, aligned (4)));
707
ee0f05b8 708struct ipr_hostrcb_type_12_error {
709 struct ipr_ext_vpd ioa_vpd;
710 struct ipr_ext_vpd cfc_vpd;
711 struct ipr_ext_vpd ioa_last_attached_to_cfc_vpd;
712 struct ipr_ext_vpd cfc_last_attached_to_ioa_vpd;
713 __be32 ioa_data[3];
714}__attribute__((packed, aligned (4)));
715
1da177e4 716struct ipr_hostrcb_type_03_error {
cfc32139 717 struct ipr_vpd ioa_vpd;
718 struct ipr_vpd cfc_vpd;
1da177e4
LT		 719 __be32 errors_detected;
720 __be32 errors_logged;
721 u8 ioa_data[12];
cfc32139 722 struct ipr_hostrcb_device_data_entry dev[3];
1da177e4
LT		 723}__attribute__((packed, aligned (4)));
724
ee0f05b8 725struct ipr_hostrcb_type_13_error {
726 struct ipr_ext_vpd ioa_vpd;
727 struct ipr_ext_vpd cfc_vpd;
728 __be32 errors_detected;
729 __be32 errors_logged;
730 struct ipr_hostrcb_device_data_entry_enhanced dev[3];
731}__attribute__((packed, aligned (4)));
732
1da177e4 733struct ipr_hostrcb_type_04_error {
cfc32139 734 struct ipr_vpd ioa_vpd;
735 struct ipr_vpd cfc_vpd;
1da177e4
LT		 736 u8 ioa_data[12];
737 struct ipr_hostrcb_array_data_entry array_member[10];
738 __be32 exposed_mode_adn;
739 __be32 array_id;
cfc32139 740 struct ipr_vpd incomp_dev_vpd;
1da177e4
LT		 741 __be32 ioa_data2;
742 struct ipr_hostrcb_array_data_entry array_member2[8];
743 struct ipr_res_addr last_func_vset_res_addr;
744 u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
745 u8 protection_level[8];
1da177e4
LT		 746}__attribute__((packed, aligned (4)));
747
ee0f05b8 748struct ipr_hostrcb_type_14_error {
749 struct ipr_ext_vpd ioa_vpd;
750 struct ipr_ext_vpd cfc_vpd;
751 __be32 exposed_mode_adn;
752 __be32 array_id;
753 struct ipr_res_addr last_func_vset_res_addr;
754 u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
755 u8 protection_level[8];
756 __be32 num_entries;
757 struct ipr_hostrcb_array_data_entry_enhanced array_member[18];
758}__attribute__((packed, aligned (4)));
759
b0df54bb 760struct ipr_hostrcb_type_07_error {
761 u8 failure_reason[64];
762 struct ipr_vpd vpd;
763 u32 data[222];
764}__attribute__((packed, aligned (4)));
765
ee0f05b8 766struct ipr_hostrcb_type_17_error {
767 u8 failure_reason[64];
768 struct ipr_ext_vpd vpd;
769 u32 data[476];
770}__attribute__((packed, aligned (4)));
771
49dc6a18
BK		 772struct ipr_hostrcb_config_element {
773 u8 type_status;
774#define IPR_PATH_CFG_TYPE_MASK 0xF0
775#define IPR_PATH_CFG_NOT_EXIST 0x00
776#define IPR_PATH_CFG_IOA_PORT 0x10
777#define IPR_PATH_CFG_EXP_PORT 0x20
778#define IPR_PATH_CFG_DEVICE_PORT 0x30
779#define IPR_PATH_CFG_DEVICE_LUN 0x40
780
781#define IPR_PATH_CFG_STATUS_MASK 0x0F
782#define IPR_PATH_CFG_NO_PROB 0x00
783#define IPR_PATH_CFG_DEGRADED 0x01
784#define IPR_PATH_CFG_FAILED 0x02
785#define IPR_PATH_CFG_SUSPECT 0x03
786#define IPR_PATH_NOT_DETECTED 0x04
787#define IPR_PATH_INCORRECT_CONN 0x05
788
789 u8 cascaded_expander;
790 u8 phy;
791 u8 link_rate;
792#define IPR_PHY_LINK_RATE_MASK 0x0F
793
794 __be32 wwid[2];
795}__attribute__((packed, aligned (4)));
796
797struct ipr_hostrcb_fabric_desc {
798 __be16 length;
799 u8 ioa_port;
800 u8 cascaded_expander;
801 u8 phy;
802 u8 path_state;
803#define IPR_PATH_ACTIVE_MASK 0xC0
804#define IPR_PATH_NO_INFO 0x00
805#define IPR_PATH_ACTIVE 0x40
806#define IPR_PATH_NOT_ACTIVE 0x80
807
808#define IPR_PATH_STATE_MASK 0x0F
809#define IPR_PATH_STATE_NO_INFO 0x00
810#define IPR_PATH_HEALTHY 0x01
811#define IPR_PATH_DEGRADED 0x02
812#define IPR_PATH_FAILED 0x03
813
814 __be16 num_entries;
815 struct ipr_hostrcb_config_element elem[1];
816}__attribute__((packed, aligned (4)));
817
818#define for_each_fabric_cfg(fabric, cfg) \
819 for (cfg = (fabric)->elem; \
820 cfg < ((fabric)->elem + be16_to_cpu((fabric)->num_entries)); \
821 cfg++)
822
823struct ipr_hostrcb_type_20_error {
824 u8 failure_reason[64];
825 u8 reserved[3];
826 u8 num_entries;
827 struct ipr_hostrcb_fabric_desc desc[1];
828}__attribute__((packed, aligned (4)));
829
1da177e4
LT		 830struct ipr_hostrcb_error {
831 __be32 failing_dev_ioasc;
832 struct ipr_res_addr failing_dev_res_addr;
833 __be32 failing_dev_res_handle;
834 __be32 prc;
835 union {
836 struct ipr_hostrcb_type_ff_error type_ff_error;
837 struct ipr_hostrcb_type_01_error type_01_error;
838 struct ipr_hostrcb_type_02_error type_02_error;
839 struct ipr_hostrcb_type_03_error type_03_error;
840 struct ipr_hostrcb_type_04_error type_04_error;
b0df54bb 841 struct ipr_hostrcb_type_07_error type_07_error;
ee0f05b8 842 struct ipr_hostrcb_type_12_error type_12_error;
843 struct ipr_hostrcb_type_13_error type_13_error;
844 struct ipr_hostrcb_type_14_error type_14_error;
845 struct ipr_hostrcb_type_17_error type_17_error;
49dc6a18 846 struct ipr_hostrcb_type_20_error type_20_error;
1da177e4
LT		 847 } u;
848}__attribute__((packed, aligned (4)));
849
850struct ipr_hostrcb_raw {
851 __be32 data[sizeof(struct ipr_hostrcb_error)/sizeof(__be32)];
852}__attribute__((packed, aligned (4)));
853
854struct ipr_hcam {
855 u8 op_code;
856#define IPR_HOST_RCB_OP_CODE_CONFIG_CHANGE 0xE1
857#define IPR_HOST_RCB_OP_CODE_LOG_DATA 0xE2
858
859 u8 notify_type;
860#define IPR_HOST_RCB_NOTIF_TYPE_EXISTING_CHANGED 0x00
861#define IPR_HOST_RCB_NOTIF_TYPE_NEW_ENTRY 0x01
862#define IPR_HOST_RCB_NOTIF_TYPE_REM_ENTRY 0x02
863#define IPR_HOST_RCB_NOTIF_TYPE_ERROR_LOG_ENTRY 0x10
864#define IPR_HOST_RCB_NOTIF_TYPE_INFORMATION_ENTRY 0x11
865
866 u8 notifications_lost;
867#define IPR_HOST_RCB_NO_NOTIFICATIONS_LOST 0
868#define IPR_HOST_RCB_NOTIFICATIONS_LOST 0x80
869
870 u8 flags;
871#define IPR_HOSTRCB_INTERNAL_OPER 0x80
872#define IPR_HOSTRCB_ERR_RESP_SENT 0x40
873
874 u8 overlay_id;
875#define IPR_HOST_RCB_OVERLAY_ID_1 0x01
876#define IPR_HOST_RCB_OVERLAY_ID_2 0x02
877#define IPR_HOST_RCB_OVERLAY_ID_3 0x03
878#define IPR_HOST_RCB_OVERLAY_ID_4 0x04
879#define IPR_HOST_RCB_OVERLAY_ID_6 0x06
b0df54bb 880#define IPR_HOST_RCB_OVERLAY_ID_7 0x07
ee0f05b8 881#define IPR_HOST_RCB_OVERLAY_ID_12 0x12
882#define IPR_HOST_RCB_OVERLAY_ID_13 0x13
883#define IPR_HOST_RCB_OVERLAY_ID_14 0x14
884#define IPR_HOST_RCB_OVERLAY_ID_16 0x16
885#define IPR_HOST_RCB_OVERLAY_ID_17 0x17
49dc6a18 886#define IPR_HOST_RCB_OVERLAY_ID_20 0x20
1da177e4
LT		 887#define IPR_HOST_RCB_OVERLAY_ID_DEFAULT 0xFF
888
889 u8 reserved1[3];
890 __be32 ilid;
891 __be32 time_since_last_ioa_reset;
892 __be32 reserved2;
893 __be32 length;
894
895 union {
896 struct ipr_hostrcb_error error;
897 struct ipr_hostrcb_cfg_ch_not ccn;
898 struct ipr_hostrcb_raw raw;
899 } u;
900}__attribute__((packed, aligned (4)));
901
902struct ipr_hostrcb {
903 struct ipr_hcam hcam;
904 dma_addr_t hostrcb_dma;
905 struct list_head queue;
49dc6a18 906 struct ipr_ioa_cfg *ioa_cfg;
1da177e4
LT		 907};
908
909/* IPR smart dump table structures */
910struct ipr_sdt_entry {
911 __be32 bar_str_offset;
912 __be32 end_offset;
913 u8 entry_byte;
914 u8 reserved[3];
915
916 u8 flags;
917#define IPR_SDT_ENDIAN 0x80
918#define IPR_SDT_VALID_ENTRY 0x20
919
920 u8 resv;
921 __be16 priority;
922}__attribute__((packed, aligned (4)));
923
924struct ipr_sdt_header {
925 __be32 state;
926 __be32 num_entries;
927 __be32 num_entries_used;
928 __be32 dump_size;
929}__attribute__((packed, aligned (4)));
930
931struct ipr_sdt {
932 struct ipr_sdt_header hdr;
933 struct ipr_sdt_entry entry[IPR_NUM_SDT_ENTRIES];
934}__attribute__((packed, aligned (4)));
935
936struct ipr_uc_sdt {
937 struct ipr_sdt_header hdr;
938 struct ipr_sdt_entry entry[1];
939}__attribute__((packed, aligned (4)));
940
941/*
942 * Driver types
943 */
944struct ipr_bus_attributes {
945 u8 bus;
946 u8 qas_enabled;
947 u8 bus_width;
948 u8 reserved;
949 u32 max_xfer_rate;
950};
951
35a39691
BK		 952struct ipr_sata_port {
953 struct ipr_ioa_cfg *ioa_cfg;
954 struct ata_port *ap;
955 struct ipr_resource_entry *res;
956 struct ipr_ioasa_gata ioasa;
957};
958
1da177e4
LT		 959struct ipr_resource_entry {
960 struct ipr_config_table_entry cfgte;
961 u8 needs_sync_complete:1;
962 u8 in_erp:1;
963 u8 add_to_ml:1;
964 u8 del_from_ml:1;
965 u8 resetting_device:1;
966
967 struct scsi_device *sdev;
35a39691 968 struct ipr_sata_port *sata_port;
1da177e4
LT		 969 struct list_head queue;
970};
971
972struct ipr_resource_hdr {
973 u16 num_entries;
974 u16 reserved;
975};
976
977struct ipr_resource_table {
978 struct ipr_resource_hdr hdr;
979 struct ipr_resource_entry dev[IPR_MAX_PHYSICAL_DEVS];
980};
981
982struct ipr_misc_cbs {
983 struct ipr_ioa_vpd ioa_vpd;
62275040 984 struct ipr_inquiry_page0 page0_data;
1da177e4 985 struct ipr_inquiry_page3 page3_data;
ac09c349 986 struct ipr_inquiry_cap cap;
1da177e4
LT		 987 struct ipr_mode_pages mode_pages;
988 struct ipr_supported_device supp_dev;
989};
990
991struct ipr_interrupt_offsets {
992 unsigned long set_interrupt_mask_reg;
993 unsigned long clr_interrupt_mask_reg;
994 unsigned long sense_interrupt_mask_reg;
995 unsigned long clr_interrupt_reg;
996
997 unsigned long sense_interrupt_reg;
998 unsigned long ioarrin_reg;
999 unsigned long sense_uproc_interrupt_reg;
1000 unsigned long set_uproc_interrupt_reg;
1001 unsigned long clr_uproc_interrupt_reg;
1002};
1003
1004struct ipr_interrupts {
1005 void __iomem *set_interrupt_mask_reg;
1006 void __iomem *clr_interrupt_mask_reg;
1007 void __iomem *sense_interrupt_mask_reg;
1008 void __iomem *clr_interrupt_reg;
1009
1010 void __iomem *sense_interrupt_reg;
1011 void __iomem *ioarrin_reg;
1012 void __iomem *sense_uproc_interrupt_reg;
1013 void __iomem *set_uproc_interrupt_reg;
1014 void __iomem *clr_uproc_interrupt_reg;
1015};
1016
1017struct ipr_chip_cfg_t {
1018 u32 mailbox;
1019 u8 cache_line_size;
1020 struct ipr_interrupt_offsets regs;
1021};
1022
1023struct ipr_chip_t {
1024 u16 vendor;
1025 u16 device;
1026 const struct ipr_chip_cfg_t *cfg;
1027};
1028
1029enum ipr_shutdown_type {
1030 IPR_SHUTDOWN_NORMAL = 0x00,
1031 IPR_SHUTDOWN_PREPARE_FOR_NORMAL = 0x40,
1032 IPR_SHUTDOWN_ABBREV = 0x80,
1033 IPR_SHUTDOWN_NONE = 0x100
1034};
1035
1036struct ipr_trace_entry {
1037 u32 time;
1038
1039 u8 op_code;
35a39691 1040 u8 ata_op_code;
1da177e4
LT		 1041 u8 type;
1042#define IPR_TRACE_START 0x00
1043#define IPR_TRACE_FINISH 0xff
35a39691 1044 u8 cmd_index;
1da177e4
LT		 1045
1046 __be32 res_handle;
1047 union {
1048 u32 ioasc;
1049 u32 add_data;
1050 u32 res_addr;
1051 } u;
1052};
1053
1054struct ipr_sglist {
1055 u32 order;
1056 u32 num_sg;
12baa420 1057 u32 num_dma_sg;
1da177e4
LT		 1058 u32 buffer_len;
1059 struct scatterlist scatterlist[1];
1060};
1061
1062enum ipr_sdt_state {
1063 INACTIVE,
1064 WAIT_FOR_DUMP,
1065 GET_DUMP,
1066 ABORT_DUMP,
1067 DUMP_OBTAINED
1068};
1069
62275040 1070enum ipr_cache_state {
1071 CACHE_NONE,
1072 CACHE_DISABLED,
1073 CACHE_ENABLED,
1074 CACHE_INVALID
1075};
1076
1da177e4
LT		 1077/* Per-controller data */
1078struct ipr_ioa_cfg {
1079 char eye_catcher[8];
1080#define IPR_EYECATCHER "iprcfg"
1081
1082 struct list_head queue;
1083
1084 u8 allow_interrupts:1;
1085 u8 in_reset_reload:1;
1086 u8 in_ioa_bringdown:1;
1087 u8 ioa_unit_checked:1;
1088 u8 ioa_is_dead:1;
1089 u8 dump_taken:1;
1090 u8 allow_cmds:1;
1091 u8 allow_ml_add_del:1;
ce155cce 1092 u8 needs_hard_reset:1;
ac09c349 1093 u8 dual_raid:1;
1da177e4 1094
62275040 1095 enum ipr_cache_state cache_state;
1da177e4
LT		 1096 u16 type; /* CCIN of the card */
1097
1098 u8 log_level;
1099#define IPR_MAX_LOG_LEVEL 4
1100#define IPR_DEFAULT_LOG_LEVEL 2
1101
1102#define IPR_NUM_TRACE_INDEX_BITS 8
1103#define IPR_NUM_TRACE_ENTRIES (1 << IPR_NUM_TRACE_INDEX_BITS)
1104#define IPR_TRACE_SIZE (sizeof(struct ipr_trace_entry) * IPR_NUM_TRACE_ENTRIES)
1105 char trace_start[8];
1106#define IPR_TRACE_START_LABEL "trace"
1107 struct ipr_trace_entry *trace;
1108 u32 trace_index:IPR_NUM_TRACE_INDEX_BITS;
1109
1110 /*
1111 * Queue for free command blocks
1112 */
1113 char ipr_free_label[8];
1114#define IPR_FREEQ_LABEL "free-q"
1115 struct list_head free_q;
1116
1117 /*
1118 * Queue for command blocks outstanding to the adapter
1119 */
1120 char ipr_pending_label[8];
1121#define IPR_PENDQ_LABEL "pend-q"
1122 struct list_head pending_q;
1123
1124 char cfg_table_start[8];
1125#define IPR_CFG_TBL_START "cfg"
1126 struct ipr_config_table *cfg_table;
1127 dma_addr_t cfg_table_dma;
1128
1129 char resource_table_label[8];
1130#define IPR_RES_TABLE_LABEL "res_tbl"
1131 struct ipr_resource_entry *res_entries;
1132 struct list_head free_res_q;
1133 struct list_head used_res_q;
1134
1135 char ipr_hcam_label[8];
1136#define IPR_HCAM_LABEL "hcams"
1137 struct ipr_hostrcb *hostrcb[IPR_NUM_HCAMS];
1138 dma_addr_t hostrcb_dma[IPR_NUM_HCAMS];
1139 struct list_head hostrcb_free_q;
1140 struct list_head hostrcb_pending_q;
1141
1142 __be32 *host_rrq;
1143 dma_addr_t host_rrq_dma;
1144#define IPR_HRRQ_REQ_RESP_HANDLE_MASK 0xfffffffc
1145#define IPR_HRRQ_RESP_BIT_SET 0x00000002
1146#define IPR_HRRQ_TOGGLE_BIT 0x00000001
1147#define IPR_HRRQ_REQ_RESP_HANDLE_SHIFT 2
1148 volatile __be32 *hrrq_start;
1149 volatile __be32 *hrrq_end;
1150 volatile __be32 *hrrq_curr;
1151 volatile u32 toggle_bit;
1152
1153 struct ipr_bus_attributes bus_attr[IPR_MAX_NUM_BUSES];
1154
5469cb5b 1155 unsigned int transop_timeout;
1da177e4
LT		 1156 const struct ipr_chip_cfg_t *chip_cfg;
1157
1158 void __iomem *hdw_dma_regs; /* iomapped PCI memory space */
1159 unsigned long hdw_dma_regs_pci; /* raw PCI memory space */
1160 void __iomem *ioa_mailbox;
1161 struct ipr_interrupts regs;
1162
1163 u16 saved_pcix_cmd_reg;
1164 u16 reset_retries;
1165
1166 u32 errors_logged;
3d1d0da6 1167 u32 doorbell;
1da177e4
LT		 1168
1169 struct Scsi_Host *host;
1170 struct pci_dev *pdev;
1171 struct ipr_sglist *ucode_sglist;
1da177e4
LT		 1172 u8 saved_mode_page_len;
1173
1174 struct work_struct work_q;
1175
1176 wait_queue_head_t reset_wait_q;
1177
1178 struct ipr_dump *dump;
1179 enum ipr_sdt_state sdt_state;
1180
1181 struct ipr_misc_cbs *vpd_cbs;
1182 dma_addr_t vpd_cbs_dma;
1183
1184 struct pci_pool *ipr_cmd_pool;
1185
1186 struct ipr_cmnd *reset_cmd;
1187
35a39691 1188 struct ata_host ata_host;
1da177e4
LT		 1189 char ipr_cmd_label[8];
1190#define IPR_CMD_LABEL "ipr_cmnd"
1191 struct ipr_cmnd *ipr_cmnd_list[IPR_NUM_CMD_BLKS];
1192 u32 ipr_cmnd_list_dma[IPR_NUM_CMD_BLKS];
1193};
1194
1195struct ipr_cmnd {
1196 struct ipr_ioarcb ioarcb;
1197 struct ipr_ioasa ioasa;
1198 struct ipr_ioadl_desc ioadl[IPR_NUM_IOADL_ENTRIES];
1199 struct list_head queue;
1200 struct scsi_cmnd *scsi_cmd;
35a39691 1201 struct ata_queued_cmd *qc;
1da177e4
LT		 1202 struct completion completion;
1203 struct timer_list timer;
1204 void (*done) (struct ipr_cmnd *);
1205 int (*job_step) (struct ipr_cmnd *);
dfed823e 1206 int (*job_step_failed) (struct ipr_cmnd *);
1da177e4
LT		 1207 u16 cmd_index;
1208 u8 sense_buffer[SCSI_SENSE_BUFFERSIZE];
1209 dma_addr_t sense_buffer_dma;
1210 unsigned short dma_use_sg;
1211 dma_addr_t dma_handle;
1212 struct ipr_cmnd *sibling;
1213 union {
1214 enum ipr_shutdown_type shutdown_type;
1215 struct ipr_hostrcb *hostrcb;
1216 unsigned long time_left;
1217 unsigned long scratch;
1218 struct ipr_resource_entry *res;
1219 struct scsi_device *sdev;
1220 } u;
1221
1222 struct ipr_ioa_cfg *ioa_cfg;
1223};
1224
1225struct ipr_ses_table_entry {
1226 char product_id[17];
1227 char compare_product_id_byte[17];
1228 u32 max_bus_speed_limit; /* MB/sec limit for this backplane */
1229};
1230
1231struct ipr_dump_header {
1232 u32 eye_catcher;
1233#define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
1234 u32 len;
1235 u32 num_entries;
1236 u32 first_entry_offset;
1237 u32 status;
1238#define IPR_DUMP_STATUS_SUCCESS 0
1239#define IPR_DUMP_STATUS_QUAL_SUCCESS 2
1240#define IPR_DUMP_STATUS_FAILED 0xffffffff
1241 u32 os;
1242#define IPR_DUMP_OS_LINUX 0x4C4E5558
1243 u32 driver_name;
1244#define IPR_DUMP_DRIVER_NAME 0x49505232
1245}__attribute__((packed, aligned (4)));
1246
1247struct ipr_dump_entry_header {
1248 u32 eye_catcher;
1249#define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
1250 u32 len;
1251 u32 num_elems;
1252 u32 offset;
1253 u32 data_type;
1254#define IPR_DUMP_DATA_TYPE_ASCII 0x41534349
1255#define IPR_DUMP_DATA_TYPE_BINARY 0x42494E41
1256 u32 id;
1257#define IPR_DUMP_IOA_DUMP_ID 0x494F4131
1258#define IPR_DUMP_LOCATION_ID 0x4C4F4341
1259#define IPR_DUMP_TRACE_ID 0x54524143
1260#define IPR_DUMP_DRIVER_VERSION_ID 0x44525652
1261#define IPR_DUMP_DRIVER_TYPE_ID 0x54595045
1262#define IPR_DUMP_IOA_CTRL_BLK 0x494F4342
1263#define IPR_DUMP_PEND_OPS 0x414F5053
1264 u32 status;
1265}__attribute__((packed, aligned (4)));
1266
1267struct ipr_dump_location_entry {
1268 struct ipr_dump_entry_header hdr;
1269 u8 location[BUS_ID_SIZE];
1270}__attribute__((packed));
1271
1272struct ipr_dump_trace_entry {
1273 struct ipr_dump_entry_header hdr;
1274 u32 trace[IPR_TRACE_SIZE / sizeof(u32)];
1275}__attribute__((packed, aligned (4)));
1276
1277struct ipr_dump_version_entry {
1278 struct ipr_dump_entry_header hdr;
1279 u8 version[sizeof(IPR_DRIVER_VERSION)];
1280};
1281
1282struct ipr_dump_ioa_type_entry {
1283 struct ipr_dump_entry_header hdr;
1284 u32 type;
1285 u32 fw_version;
1286};
1287
1288struct ipr_driver_dump {
1289 struct ipr_dump_header hdr;
1290 struct ipr_dump_version_entry version_entry;
1291 struct ipr_dump_location_entry location_entry;
1292 struct ipr_dump_ioa_type_entry ioa_type_entry;
1293 struct ipr_dump_trace_entry trace_entry;
1294}__attribute__((packed));
1295
1296struct ipr_ioa_dump {
1297 struct ipr_dump_entry_header hdr;
1298 struct ipr_sdt sdt;
1299 __be32 *ioa_data[IPR_MAX_NUM_DUMP_PAGES];
1300 u32 reserved;
1301 u32 next_page_index;
1302 u32 page_offset;
1303 u32 format;
1304#define IPR_SDT_FMT2 2
1305#define IPR_SDT_UNKNOWN 3
1306}__attribute__((packed, aligned (4)));
1307
1308struct ipr_dump {
1309 struct kref kref;
1310 struct ipr_ioa_cfg *ioa_cfg;
1311 struct ipr_driver_dump driver_dump;
1312 struct ipr_ioa_dump ioa_dump;
1313};
1314
1315struct ipr_error_table_t {
1316 u32 ioasc;
1317 int log_ioasa;
1318 int log_hcam;
1319 char *error;
1320};
1321
1322struct ipr_software_inq_lid_info {
1323 __be32 load_id;
1324 __be32 timestamp[3];
1325}__attribute__((packed, aligned (4)));
1326
1327struct ipr_ucode_image_header {
1328 __be32 header_length;
1329 __be32 lid_table_offset;
1330 u8 major_release;
1331 u8 card_type;
1332 u8 minor_release[2];
1333 u8 reserved[20];
1334 char eyecatcher[16];
1335 __be32 num_lids;
1336 struct ipr_software_inq_lid_info lid[1];
1337}__attribute__((packed, aligned (4)));
1338
1339/*
1340 * Macros
1341 */
d3c74871 1342#define IPR_DBG_CMD(CMD) if (ipr_debug) { CMD; }
1da177e4
LT		 1343
1344#ifdef CONFIG_SCSI_IPR_TRACE
1345#define ipr_create_trace_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1346#define ipr_remove_trace_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1347#else
1348#define ipr_create_trace_file(kobj, attr) 0
1349#define ipr_remove_trace_file(kobj, attr) do { } while(0)
1350#endif
1351
1352#ifdef CONFIG_SCSI_IPR_DUMP
1353#define ipr_create_dump_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1354#define ipr_remove_dump_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1355#else
1356#define ipr_create_dump_file(kobj, attr) 0
1357#define ipr_remove_dump_file(kobj, attr) do { } while(0)
1358#endif
1359
1360/*
1361 * Error logging macros
1362 */
1363#define ipr_err(...) printk(KERN_ERR IPR_NAME ": "__VA_ARGS__)
1364#define ipr_info(...) printk(KERN_INFO IPR_NAME ": "__VA_ARGS__)
1da177e4
LT		 1365#define ipr_dbg(...) IPR_DBG_CMD(printk(KERN_INFO IPR_NAME ": "__VA_ARGS__))
1366
fb3ed3cb
BK		 1367#define ipr_ra_printk(level, ioa_cfg, ra, fmt, ...) \
1368 printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1369 (ra).bus, (ra).target, (ra).lun, ##__VA_ARGS__)
1da177e4 1370
fb3ed3cb
BK		 1371#define ipr_ra_err(ioa_cfg, ra, fmt, ...) \
1372 ipr_ra_printk(KERN_ERR, ioa_cfg, ra, fmt, ##__VA_ARGS__)
1da177e4
LT		 1373
1374#define ipr_res_err(ioa_cfg, res, fmt, ...) \
fb3ed3cb 1375 ipr_ra_err(ioa_cfg, (res)->cfgte.res_addr, fmt, ##__VA_ARGS__)
1da177e4 1376
fa15b1f6 1377#define ipr_phys_res_err(ioa_cfg, res, fmt, ...) \
1378{ \
1379 if ((res).bus >= IPR_MAX_NUM_BUSES) { \
1380 ipr_err(fmt": unknown\n", ##__VA_ARGS__); \
1381 } else { \
1382 ipr_err(fmt": %d:%d:%d:%d\n", \
1383 ##__VA_ARGS__, (ioa_cfg)->host->host_no, \
1384 (res).bus, (res).target, (res).lun); \
1385 } \
1386}
1387
49dc6a18
BK		 1388#define ipr_hcam_err(hostrcb, fmt, ...) \
1389{ \
1390 if (ipr_is_device(&(hostrcb)->hcam.u.error.failing_dev_res_addr)) { \
1391 ipr_ra_err((hostrcb)->ioa_cfg, \
1392 (hostrcb)->hcam.u.error.failing_dev_res_addr, \
1393 fmt, ##__VA_ARGS__); \
1394 } else { \
1395 dev_err(&(hostrcb)->ioa_cfg->pdev->dev, fmt, ##__VA_ARGS__); \
1396 } \
1397}
1398
1da177e4
LT		 1399#define ipr_trace ipr_dbg("%s: %s: Line: %d\n",\
1400 __FILE__, __FUNCTION__, __LINE__)
1401
d3c74871 1402#define ENTER IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Entering %s\n", __FUNCTION__))
1403#define LEAVE IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Leaving %s\n", __FUNCTION__))
1da177e4
LT		 1404
1405#define ipr_err_separator \
1406ipr_err("----------------------------------------------------------\n")
1407
1408
1409/*
1410 * Inlines
1411 */
1412
1413/**
1414 * ipr_is_ioa_resource - Determine if a resource is the IOA
1415 * @res: resource entry struct
1416 *
1417 * Return value:
1418 * 1 if IOA / 0 if not IOA
1419 **/
1420static inline int ipr_is_ioa_resource(struct ipr_resource_entry *res)
1421{
1422 return (res->cfgte.flags & IPR_IS_IOA_RESOURCE) ? 1 : 0;
1423}
1424
1425/**
1426 * ipr_is_af_dasd_device - Determine if a resource is an AF DASD
1427 * @res: resource entry struct
1428 *
1429 * Return value:
1430 * 1 if AF DASD / 0 if not AF DASD
1431 **/
1432static inline int ipr_is_af_dasd_device(struct ipr_resource_entry *res)
1433{
1434 if (IPR_IS_DASD_DEVICE(res->cfgte.std_inq_data) &&
1435 !ipr_is_ioa_resource(res) &&
1436 IPR_RES_SUBTYPE(res) == IPR_SUBTYPE_AF_DASD)
1437 return 1;
1438 else
1439 return 0;
1440}
1441
1442/**
1443 * ipr_is_vset_device - Determine if a resource is a VSET
1444 * @res: resource entry struct
1445 *
1446 * Return value:
1447 * 1 if VSET / 0 if not VSET
1448 **/
1449static inline int ipr_is_vset_device(struct ipr_resource_entry *res)
1450{
1451 if (IPR_IS_DASD_DEVICE(res->cfgte.std_inq_data) &&
1452 !ipr_is_ioa_resource(res) &&
1453 IPR_RES_SUBTYPE(res) == IPR_SUBTYPE_VOLUME_SET)
1454 return 1;
1455 else
1456 return 0;
1457}
1458
1459/**
1460 * ipr_is_gscsi - Determine if a resource is a generic scsi resource
1461 * @res: resource entry struct
1462 *
1463 * Return value:
1464 * 1 if GSCSI / 0 if not GSCSI
1465 **/
1466static inline int ipr_is_gscsi(struct ipr_resource_entry *res)
1467{
1468 if (!ipr_is_ioa_resource(res) &&
1469 IPR_RES_SUBTYPE(res) == IPR_SUBTYPE_GENERIC_SCSI)
1470 return 1;
1471 else
1472 return 0;
1473}
1474
e4fbf44e
BK		 1475/**
1476 * ipr_is_scsi_disk - Determine if a resource is a SCSI disk
1477 * @res: resource entry struct
1478 *
1479 * Return value:
1480 * 1 if SCSI disk / 0 if not SCSI disk
1481 **/
1482static inline int ipr_is_scsi_disk(struct ipr_resource_entry *res)
1483{
1484 if (ipr_is_af_dasd_device(res) ||
1485 (ipr_is_gscsi(res) && IPR_IS_DASD_DEVICE(res->cfgte.std_inq_data)))
1486 return 1;
1487 else
1488 return 0;
1489}
1490
b5145d25
BK		 1491/**
1492 * ipr_is_gata - Determine if a resource is a generic ATA resource
1493 * @res: resource entry struct
1494 *
1495 * Return value:
1496 * 1 if GATA / 0 if not GATA
1497 **/
1498static inline int ipr_is_gata(struct ipr_resource_entry *res)
1499{
1500 if (!ipr_is_ioa_resource(res) &&
1501 IPR_RES_SUBTYPE(res) == IPR_SUBTYPE_GENERIC_ATA)
1502 return 1;
1503 else
1504 return 0;
1505}
1506
ee0a90fa 1507/**
1508 * ipr_is_naca_model - Determine if a resource is using NACA queueing model
1509 * @res: resource entry struct
1510 *
1511 * Return value:
1512 * 1 if NACA queueing model / 0 if not NACA queueing model
1513 **/
1514static inline int ipr_is_naca_model(struct ipr_resource_entry *res)
1515{
1516 if (ipr_is_gscsi(res) && IPR_QUEUEING_MODEL(res) == IPR_QUEUE_NACA_MODEL)
1517 return 1;
1518 return 0;
1519}
1520
1da177e4
LT		 1521/**
1522 * ipr_is_device - Determine if resource address is that of a device
1523 * @res_addr: resource address struct
1524 *
1525 * Return value:
1526 * 1 if AF / 0 if not AF
1527 **/
1528static inline int ipr_is_device(struct ipr_res_addr *res_addr)
1529{
1530 if ((res_addr->bus < IPR_MAX_NUM_BUSES) &&
d71a8b0c 1531 (res_addr->target < (IPR_MAX_NUM_TARGETS_PER_BUS - 1)))
1da177e4
LT		 1532 return 1;
1533
1534 return 0;
1535}
1536
1537/**
1538 * ipr_sdt_is_fmt2 - Determine if a SDT address is in format 2
1539 * @sdt_word: SDT address
1540 *
1541 * Return value:
1542 * 1 if format 2 / 0 if not
1543 **/
1544static inline int ipr_sdt_is_fmt2(u32 sdt_word)
1545{
1546 u32 bar_sel = IPR_GET_FMT2_BAR_SEL(sdt_word);
1547
1548 switch (bar_sel) {
1549 case IPR_SDT_FMT2_BAR0_SEL:
1550 case IPR_SDT_FMT2_BAR1_SEL:
1551 case IPR_SDT_FMT2_BAR2_SEL:
1552 case IPR_SDT_FMT2_BAR3_SEL:
1553 case IPR_SDT_FMT2_BAR4_SEL:
1554 case IPR_SDT_FMT2_BAR5_SEL:
1555 case IPR_SDT_FMT2_EXP_ROM_SEL:
1556 return 1;
1557 };
1558
1559 return 0;
1560}
1561
1562#endif
Linux kernel - Deliverables
This page took 0.259194 seconds and 5 git commands to generate.