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d044af17 DW |
1 | /* |
2 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
3 | * redistributing this file, you may do so under either license. | |
4 | * | |
5 | * GPL LICENSE SUMMARY | |
6 | * | |
7 | * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of version 2 of the GNU General Public License as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
16 | * General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
21 | * The full GNU General Public License is included in this distribution | |
22 | * in the file called LICENSE.GPL. | |
23 | * | |
24 | * BSD LICENSE | |
25 | * | |
26 | * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. | |
27 | * All rights reserved. | |
28 | * | |
29 | * Redistribution and use in source and binary forms, with or without | |
30 | * modification, are permitted provided that the following conditions | |
31 | * are met: | |
32 | * | |
33 | * * Redistributions of source code must retain the above copyright | |
34 | * notice, this list of conditions and the following disclaimer. | |
35 | * * Redistributions in binary form must reproduce the above copyright | |
36 | * notice, this list of conditions and the following disclaimer in | |
37 | * the documentation and/or other materials provided with the | |
38 | * distribution. | |
39 | * * Neither the name of Intel Corporation nor the names of its | |
40 | * contributors may be used to endorse or promote products derived | |
41 | * from this software without specific prior written permission. | |
42 | * | |
43 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
44 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
45 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
46 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
47 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
48 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
49 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
50 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
51 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
52 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
53 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
54 | */ | |
55 | #ifndef _ISCI_PROBE_ROMS_H_ | |
56 | #define _ISCI_PROBE_ROMS_H_ | |
57 | ||
58 | #ifdef __KERNEL__ | |
59 | #include <linux/firmware.h> | |
60 | #include <linux/pci.h> | |
bf482c60 | 61 | #include <linux/efi.h> |
ce2b3261 | 62 | #include "isci.h" |
d044af17 | 63 | |
e2f8db50 DW |
64 | #define SCIC_SDS_PARM_NO_SPEED 0 |
65 | ||
66 | /* generation 1 (i.e. 1.5 Gb/s) */ | |
67 | #define SCIC_SDS_PARM_GEN1_SPEED 1 | |
68 | ||
69 | /* generation 2 (i.e. 3.0 Gb/s) */ | |
70 | #define SCIC_SDS_PARM_GEN2_SPEED 2 | |
71 | ||
72 | /* generation 3 (i.e. 6.0 Gb/s) */ | |
73 | #define SCIC_SDS_PARM_GEN3_SPEED 3 | |
74 | #define SCIC_SDS_PARM_MAX_SPEED SCIC_SDS_PARM_GEN3_SPEED | |
75 | ||
76 | /* parameters that can be set by module parameters */ | |
89a7301f | 77 | struct sci_user_parameters { |
e2f8db50 DW |
78 | struct sci_phy_user_params { |
79 | /** | |
80 | * This field specifies the NOTIFY (ENABLE SPIN UP) primitive | |
81 | * insertion frequency for this phy index. | |
82 | */ | |
83 | u32 notify_enable_spin_up_insertion_frequency; | |
84 | ||
85 | /** | |
86 | * This method specifies the number of transmitted DWORDs within which | |
87 | * to transmit a single ALIGN primitive. This value applies regardless | |
88 | * of what type of device is attached or connection state. A value of | |
89 | * 0 indicates that no ALIGN primitives will be inserted. | |
90 | */ | |
91 | u16 align_insertion_frequency; | |
92 | ||
93 | /** | |
94 | * This method specifies the number of transmitted DWORDs within which | |
95 | * to transmit 2 ALIGN primitives. This applies for SAS connections | |
96 | * only. A minimum value of 3 is required for this field. | |
97 | */ | |
98 | u16 in_connection_align_insertion_frequency; | |
99 | ||
100 | /** | |
101 | * This field indicates the maximum speed generation to be utilized | |
102 | * by phys in the supplied port. | |
103 | * - A value of 1 indicates generation 1 (i.e. 1.5 Gb/s). | |
104 | * - A value of 2 indicates generation 2 (i.e. 3.0 Gb/s). | |
105 | * - A value of 3 indicates generation 3 (i.e. 6.0 Gb/s). | |
106 | */ | |
107 | u8 max_speed_generation; | |
108 | ||
109 | } phys[SCI_MAX_PHYS]; | |
110 | ||
111 | /** | |
112 | * This field specifies the maximum number of direct attached devices | |
113 | * that can have power supplied to them simultaneously. | |
114 | */ | |
7000f7c7 | 115 | u8 max_concurr_spinup; |
e2f8db50 DW |
116 | |
117 | /** | |
118 | * This field specifies the number of seconds to allow a phy to consume | |
119 | * power before yielding to another phy. | |
120 | * | |
121 | */ | |
122 | u8 phy_spin_up_delay_interval; | |
123 | ||
124 | /** | |
125 | * These timer values specifies how long a link will remain open with no | |
126 | * activity in increments of a microsecond, it can be in increments of | |
127 | * 100 microseconds if the upper most bit is set. | |
128 | * | |
129 | */ | |
130 | u16 stp_inactivity_timeout; | |
131 | u16 ssp_inactivity_timeout; | |
132 | ||
133 | /** | |
134 | * These timer values specifies how long a link will remain open in increments | |
135 | * of 100 microseconds. | |
136 | * | |
137 | */ | |
138 | u16 stp_max_occupancy_timeout; | |
139 | u16 ssp_max_occupancy_timeout; | |
140 | ||
141 | /** | |
142 | * This timer value specifies how long a link will remain open with no | |
143 | * outbound traffic in increments of a microsecond. | |
144 | * | |
145 | */ | |
146 | u8 no_outbound_task_timeout; | |
147 | ||
148 | }; | |
149 | ||
e2f8db50 DW |
150 | #define SCIC_SDS_PARM_PHY_MASK_MIN 0x0 |
151 | #define SCIC_SDS_PARM_PHY_MASK_MAX 0xF | |
152 | #define MAX_CONCURRENT_DEVICE_SPIN_UP_COUNT 4 | |
153 | ||
89a7301f | 154 | struct sci_oem_params; |
594e566a | 155 | int sci_oem_parameters_validate(struct sci_oem_params *oem, u8 version); |
d044af17 | 156 | |
e2f8db50 DW |
157 | struct isci_orom; |
158 | struct isci_orom *isci_request_oprom(struct pci_dev *pdev); | |
89a7301f | 159 | enum sci_status isci_parse_oem_parameters(struct sci_oem_params *oem, |
e2f8db50 | 160 | struct isci_orom *orom, int scu_index); |
d044af17 | 161 | struct isci_orom *isci_request_firmware(struct pci_dev *pdev, const struct firmware *fw); |
8db37aab | 162 | struct isci_orom *isci_get_efi_var(struct pci_dev *pdev); |
3b67c1f3 DW |
163 | |
164 | struct isci_oem_hdr { | |
165 | u8 sig[4]; | |
166 | u8 rev_major; | |
167 | u8 rev_minor; | |
168 | u16 len; | |
169 | u8 checksum; | |
170 | u8 reserved1; | |
171 | u16 reserved2; | |
172 | } __attribute__ ((packed)); | |
173 | ||
d044af17 DW |
174 | #else |
175 | #define SCI_MAX_PORTS 4 | |
176 | #define SCI_MAX_PHYS 4 | |
ca507b98 | 177 | #define SCI_MAX_CONTROLLERS 2 |
d044af17 DW |
178 | #endif |
179 | ||
180 | #define ISCI_FW_NAME "isci/isci_firmware.bin" | |
181 | ||
182 | #define ROMSIGNATURE 0xaa55 | |
183 | ||
3b67c1f3 DW |
184 | #define ISCI_OEM_SIG "$OEM" |
185 | #define ISCI_OEM_SIG_SIZE 4 | |
d044af17 DW |
186 | #define ISCI_ROM_SIG "ISCUOEMB" |
187 | #define ISCI_ROM_SIG_SIZE 8 | |
188 | ||
ca507b98 DJ |
189 | #define ISCI_EFI_VENDOR_GUID \ |
190 | EFI_GUID(0x193dfefa, 0xa445, 0x4302, 0x99, 0xd8, 0xef, 0x3a, 0xad, \ | |
191 | 0x1a, 0x04, 0xc6) | |
2e8320f7 | 192 | #define ISCI_EFI_VAR_NAME "RstScuO" |
d044af17 | 193 | |
594e566a DJ |
194 | #define ISCI_ROM_VER_1_0 0x10 |
195 | #define ISCI_ROM_VER_1_1 0x11 | |
9fee607f JS |
196 | #define ISCI_ROM_VER_1_3 0x13 |
197 | #define ISCI_ROM_VER_LATEST ISCI_ROM_VER_1_3 | |
594e566a | 198 | |
07373a5c HD |
199 | /* Allowed PORT configuration modes APC Automatic PORT configuration mode is |
200 | * defined by the OEM configuration parameters providing no PHY_MASK parameters | |
201 | * for any PORT. i.e. There are no phys assigned to any of the ports at start. | |
202 | * MPC Manual PORT configuration mode is defined by the OEM configuration | |
203 | * parameters providing a PHY_MASK value for any PORT. It is assumed that any | |
204 | * PORT with no PHY_MASK is an invalid port and not all PHYs must be assigned. | |
205 | * A PORT_PHY mask that assigns just a single PHY to a port and no other PHYs | |
206 | * being assigned is sufficient to declare manual PORT configuration. | |
207 | */ | |
89a7301f | 208 | enum sci_port_configuration_mode { |
4eefd251 DW |
209 | SCIC_PORT_MANUAL_CONFIGURATION_MODE = 0, |
210 | SCIC_PORT_AUTOMATIC_CONFIGURATION_MODE = 1 | |
07373a5c HD |
211 | }; |
212 | ||
d044af17 DW |
213 | struct sci_bios_oem_param_block_hdr { |
214 | uint8_t signature[ISCI_ROM_SIG_SIZE]; | |
215 | uint16_t total_block_length; | |
216 | uint8_t hdr_length; | |
217 | uint8_t version; | |
218 | uint8_t preboot_source; | |
219 | uint8_t num_elements; | |
f22be5d8 | 220 | uint16_t element_length; |
d044af17 DW |
221 | uint8_t reserved[8]; |
222 | } __attribute__ ((packed)); | |
223 | ||
89a7301f | 224 | struct sci_oem_params { |
d044af17 DW |
225 | struct { |
226 | uint8_t mode_type; | |
7000f7c7 | 227 | uint8_t max_concurr_spin_up; |
594e566a DJ |
228 | /* |
229 | * This bitfield indicates the OEM's desired default Tx | |
230 | * Spread Spectrum Clocking (SSC) settings for SATA and SAS. | |
231 | * NOTE: Default SSC Modulation Frequency is 31.5KHz. | |
232 | */ | |
233 | union { | |
234 | struct { | |
235 | /* | |
236 | * NOTE: Max spread for SATA is +0 / -5000 PPM. | |
237 | * Down-spreading SSC (only method allowed for SATA): | |
238 | * SATA SSC Tx Disabled = 0x0 | |
239 | * SATA SSC Tx at +0 / -1419 PPM Spread = 0x2 | |
240 | * SATA SSC Tx at +0 / -2129 PPM Spread = 0x3 | |
241 | * SATA SSC Tx at +0 / -4257 PPM Spread = 0x6 | |
242 | * SATA SSC Tx at +0 / -4967 PPM Spread = 0x7 | |
243 | */ | |
244 | uint8_t ssc_sata_tx_spread_level:4; | |
245 | /* | |
246 | * SAS SSC Tx Disabled = 0x0 | |
247 | * | |
248 | * NOTE: Max spread for SAS down-spreading +0 / | |
249 | * -2300 PPM | |
250 | * Down-spreading SSC: | |
251 | * SAS SSC Tx at +0 / -1419 PPM Spread = 0x2 | |
252 | * SAS SSC Tx at +0 / -2129 PPM Spread = 0x3 | |
253 | * | |
254 | * NOTE: Max spread for SAS center-spreading +2300 / | |
255 | * -2300 PPM | |
256 | * Center-spreading SSC: | |
257 | * SAS SSC Tx at +1064 / -1064 PPM Spread = 0x3 | |
258 | * SAS SSC Tx at +2129 / -2129 PPM Spread = 0x6 | |
259 | */ | |
260 | uint8_t ssc_sas_tx_spread_level:3; | |
261 | /* | |
262 | * NOTE: Refer to the SSC section of the SAS 2.x | |
263 | * Specification for proper setting of this field. | |
264 | * For standard SAS Initiator SAS PHY operation it | |
265 | * should be 0 for Down-spreading. | |
266 | * SAS SSC Tx spread type: | |
267 | * Down-spreading SSC = 0 | |
268 | * Center-spreading SSC = 1 | |
269 | */ | |
270 | uint8_t ssc_sas_tx_type:1; | |
271 | }; | |
272 | uint8_t do_enable_ssc; | |
273 | }; | |
9fee607f JS |
274 | /* |
275 | * This field indicates length of the SAS/SATA cable between | |
276 | * host and device. | |
277 | * This field is used make relationship between analog | |
278 | * parameters of the phy in the silicon and length of the cable. | |
279 | * Supported cable attenuation levels: | |
280 | * "short"- up to 3m, "medium"-3m to 6m, and "long"- more than | |
281 | * 6m. | |
282 | * | |
283 | * This is bit mask field: | |
284 | * | |
285 | * BIT: (MSB) 7 6 5 4 | |
286 | * ASSIGNMENT: <phy3><phy2><phy1><phy0> - Medium cable | |
287 | * length assignment | |
288 | * BIT: 3 2 1 0 (LSB) | |
289 | * ASSIGNMENT: <phy3><phy2><phy1><phy0> - Long cable length | |
290 | * assignment | |
291 | * | |
292 | * BITS 7-4 are set when the cable length is assigned to medium | |
293 | * BITS 3-0 are set when the cable length is assigned to long | |
294 | * | |
295 | * The BIT positions are clear when the cable length is | |
296 | * assigned to short. | |
297 | * | |
298 | * Setting the bits for both long and medium cable length is | |
299 | * undefined. | |
300 | * | |
301 | * A value of 0x84 would assign | |
302 | * phy3 - medium | |
303 | * phy2 - long | |
304 | * phy1 - short | |
305 | * phy0 - short | |
306 | */ | |
307 | uint8_t cable_selection_mask; | |
d044af17 DW |
308 | } controller; |
309 | ||
310 | struct { | |
311 | uint8_t phy_mask; | |
312 | } ports[SCI_MAX_PORTS]; | |
313 | ||
314 | struct sci_phy_oem_params { | |
315 | struct { | |
316 | uint32_t high; | |
317 | uint32_t low; | |
318 | } sas_address; | |
319 | ||
320 | uint32_t afe_tx_amp_control0; | |
321 | uint32_t afe_tx_amp_control1; | |
322 | uint32_t afe_tx_amp_control2; | |
323 | uint32_t afe_tx_amp_control3; | |
324 | } phys[SCI_MAX_PHYS]; | |
325 | } __attribute__ ((packed)); | |
326 | ||
327 | struct isci_orom { | |
328 | struct sci_bios_oem_param_block_hdr hdr; | |
89a7301f | 329 | struct sci_oem_params ctrl[SCI_MAX_CONTROLLERS]; |
d044af17 DW |
330 | } __attribute__ ((packed)); |
331 | ||
332 | #endif |