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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mason/linux...
[deliverable/linux.git] / drivers / scsi / lpfc / lpfc.h
CommitLineData
dea3101e 1/*******************************************************************
2 * This file is part of the Emulex Linux Device Driver for *
c44ce173 3 * Fibre Channel Host Bus Adapters. *
b857ff33 4 * Copyright (C) 2004-2014 Emulex. All rights reserved. *
c44ce173 5 * EMULEX and SLI are trademarks of Emulex. *
dea3101e 6 * www.emulex.com *
c44ce173 7 * Portions Copyright (C) 2004-2005 Christoph Hellwig *
dea3101e 8 * *
9 * This program is free software; you can redistribute it and/or *
c44ce173
JSEC		 10 * modify it under the terms of version 2 of the GNU General *
11 * Public License as published by the Free Software Foundation. *
12 * This program is distributed in the hope that it will be useful. *
13 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
14 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
15 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
16 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
17 * TO BE LEGALLY INVALID. See the GNU General Public License for *
18 * more details, a copy of which can be found in the file COPYING *
19 * included with this package. *
dea3101e 20 *******************************************************************/
21
2e0fef85 22#include <scsi/scsi_host.h>
88a2cfbb
JS		 23
24#if defined(CONFIG_DEBUG_FS) && !defined(CONFIG_SCSI_LPFC_DEBUG_FS)
25#define CONFIG_SCSI_LPFC_DEBUG_FS
26#endif
27
dea3101e 28struct lpfc_sli2_slim;
29
5402a315
JS		 30#define ELX_MODEL_NAME_SIZE 80
31
3772a991
JS		 32#define LPFC_PCI_DEV_LP 0x1
33#define LPFC_PCI_DEV_OC 0x2
34
35#define LPFC_SLI_REV2 2
36#define LPFC_SLI_REV3 3
37#define LPFC_SLI_REV4 4
38
97eab634 39#define LPFC_MAX_TARGET 4096 /* max number of targets supported */
e17da18e
JS		 40#define LPFC_MAX_DISC_THREADS 64 /* max outstanding discovery els
41 requests */
42#define LPFC_MAX_NS_RETRY 3 /* Number of retry attempts to contact
43 the NameServer before giving up. */
445cf4f4 44#define LPFC_CMD_PER_LUN 3 /* max outstanding cmds per lun */
81301a9b 45#define LPFC_DEFAULT_SG_SEG_CNT 64 /* sg element count per scsi cmnd */
e2aed29f
JS		 46#define LPFC_DEFAULT_MENLO_SG_SEG_CNT 128 /* sg element count per scsi
47 cmnd for menlo needs nearly twice as for firmware
48 downloads using bsg */
96f7077f
JS		 49
50#define LPFC_MIN_SG_SLI4_BUF_SZ 0x800 /* based on LPFC_DEFAULT_SG_SEG_CNT */
51#define LPFC_MAX_SG_SLI4_SEG_CNT_DIF 128 /* sg element count per scsi cmnd */
52#define LPFC_MAX_SG_SEG_CNT_DIF 512 /* sg element count per scsi cmnd */
81301a9b 53#define LPFC_MAX_SG_SEG_CNT 4096 /* sg element count per scsi cmnd */
09294d46
JS		 54#define LPFC_MAX_SGL_SEG_CNT 512 /* SGL element count per scsi cmnd */
55#define LPFC_MAX_BPL_SEG_CNT 4096 /* BPL element count per scsi cmnd */
56
0558056c 57#define LPFC_MAX_SGE_SIZE 0x80000000 /* Maximum data allowed in a SGE */
dea3101e 58#define LPFC_IOCB_LIST_CNT 2250 /* list of IOCBs for fast-path usage. */
445cf4f4 59#define LPFC_Q_RAMP_UP_INTERVAL 120 /* lun q_depth ramp up interval */
495a714c 60#define LPFC_VNAME_LEN 100 /* vport symbolic name length */
977b5a0a
JS		 61#define LPFC_TGTQ_INTERVAL 40000 /* Min amount of time between tgt
62 queue depth change in millisecs */
63#define LPFC_TGTQ_RAMPUP_PCENT 5 /* Target queue rampup in percentage */
7dc517df 64#define LPFC_MIN_TGT_QDEPTH 10
977b5a0a 65#define LPFC_MAX_TGT_QDEPTH 0xFFFF
dea3101e 66
ea2151b4
JS		 67#define LPFC_MAX_BUCKET_COUNT 20 /* Maximum no. of buckets for stat data
68 collection. */
92d7f7b0
JS		 69/*
70 * Following time intervals are used of adjusting SCSI device
71 * queue depths when there are driver resource error or Firmware
72 * resource error.
73 */
256ec0d0
JS		 74/* 1 Second */
75#define QUEUE_RAMP_DOWN_INTERVAL (msecs_to_jiffies(1000 * 1))
92d7f7b0
JS		 76
77/* Number of exchanges reserved for discovery to complete */
78#define LPFC_DISC_IOCB_BUFF_COUNT 20
79
858c9f6c 80#define LPFC_HB_MBOX_INTERVAL 5 /* Heart beat interval in seconds. */
311464ec 81#define LPFC_HB_MBOX_TIMEOUT 30 /* Heart beat timeout in seconds. */
858c9f6c 82
ba20c853
JS		 83#define LPFC_LOOK_AHEAD_OFF 0 /* Look ahead logic is turned off */
84
9399627f
JS		 85/* Error Attention event polling interval */
86#define LPFC_ERATT_POLL_INTERVAL 5 /* EATT poll interval in seconds */
87
dea3101e 88/* Define macros for 64 bit support */
89#define putPaddrLow(addr) ((uint32_t) (0xffffffff & (u64)(addr)))
90#define putPaddrHigh(addr) ((uint32_t) (0xffffffff & (((u64)(addr))>>32)))
91#define getPaddr(high, low) ((dma_addr_t)( \
92 (( (u64)(high)<<16 ) << 16)|( (u64)(low))))
93/* Provide maximum configuration definitions. */
94#define LPFC_DRVR_TIMEOUT 16 /* driver iocb timeout value in sec */
dea3101e 95#define FC_MAX_ADPTMSG 64
96
97#define MAX_HBAEVT 32
98
9399627f
JS		 99/* Number of MSI-X vectors the driver uses */
100#define LPFC_MSIX_VECTORS 2
101
5e9d9b82
JS		 102/* lpfc wait event data ready flag */
103#define LPFC_DATA_READY (1<<0)
104
809c7536
JS		 105/* queue dump line buffer size */
106#define LPFC_LBUF_SZ 128
107
618a5230
JS		 108/* mailbox system shutdown options */
109#define LPFC_MBX_NO_WAIT 0
110#define LPFC_MBX_WAIT 1
111
875fbdfe
JSEC		 112enum lpfc_polling_flags {
113 ENABLE_FCP_RING_POLLING = 0x1,
114 DISABLE_FCP_RING_INT = 0x2
115};
116
dea3101e 117/* Provide DMA memory definitions the driver uses per port instance. */
118struct lpfc_dmabuf {
119 struct list_head list;
120 void *virt; /* virtual address ptr */
121 dma_addr_t phys; /* mapped address */
76bb24ef 122 uint32_t buffer_tag; /* used for tagged queue ring */
dea3101e 123};
124
125struct lpfc_dma_pool {
126 struct lpfc_dmabuf *elements;
127 uint32_t max_count;
128 uint32_t current_count;
129};
130
ed957684 131struct hbq_dmabuf {
da0436e9 132 struct lpfc_dmabuf hbuf;
ed957684 133 struct lpfc_dmabuf dbuf;
51ef4c26 134 uint32_t size;
ed957684 135 uint32_t tag;
4d9ab994 136 struct lpfc_cq_event cq_event;
45ed1190 137 unsigned long time_stamp;
ed957684
JS		 138};
139
dea3101e 140/* Priority bit. Set value to exceed low water mark in lpfc_mem. */
141#define MEM_PRI 0x100
142
143
144/****************************************************************************/
145/* Device VPD save area */
146/****************************************************************************/
147typedef struct lpfc_vpd {
148 uint32_t status; /* vpd status value */
149 uint32_t length; /* number of bytes actually returned */
150 struct {
151 uint32_t rsvd1; /* Revision numbers */
152 uint32_t biuRev;
153 uint32_t smRev;
154 uint32_t smFwRev;
155 uint32_t endecRev;
156 uint16_t rBit;
157 uint8_t fcphHigh;
158 uint8_t fcphLow;
159 uint8_t feaLevelHigh;
160 uint8_t feaLevelLow;
161 uint32_t postKernRev;
162 uint32_t opFwRev;
163 uint8_t opFwName[16];
164 uint32_t sli1FwRev;
165 uint8_t sli1FwName[16];
166 uint32_t sli2FwRev;
167 uint8_t sli2FwName[16];
168 } rev;
92d7f7b0
JS		 169 struct {
170#ifdef __BIG_ENDIAN_BITFIELD
da0436e9
JS		 171 uint32_t rsvd3 :19; /* Reserved */
172 uint32_t cdss : 1; /* Configure Data Security SLI */
173 uint32_t rsvd2 : 3; /* Reserved */
174 uint32_t cbg : 1; /* Configure BlockGuard */
92d7f7b0
JS		 175 uint32_t cmv : 1; /* Configure Max VPIs */
176 uint32_t ccrp : 1; /* Config Command Ring Polling */
177 uint32_t csah : 1; /* Configure Synchronous Abort Handling */
178 uint32_t chbs : 1; /* Cofigure Host Backing store */
179 uint32_t cinb : 1; /* Enable Interrupt Notification Block */
180 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
181 uint32_t cmx : 1; /* Configure Max XRIs */
182 uint32_t cmr : 1; /* Configure Max RPIs */
183#else /* __LITTLE_ENDIAN */
184 uint32_t cmr : 1; /* Configure Max RPIs */
185 uint32_t cmx : 1; /* Configure Max XRIs */
186 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
187 uint32_t cinb : 1; /* Enable Interrupt Notification Block */
188 uint32_t chbs : 1; /* Cofigure Host Backing store */
189 uint32_t csah : 1; /* Configure Synchronous Abort Handling */
190 uint32_t ccrp : 1; /* Config Command Ring Polling */
191 uint32_t cmv : 1; /* Configure Max VPIs */
da0436e9
JS		 192 uint32_t cbg : 1; /* Configure BlockGuard */
193 uint32_t rsvd2 : 3; /* Reserved */
194 uint32_t cdss : 1; /* Configure Data Security SLI */
195 uint32_t rsvd3 :19; /* Reserved */
92d7f7b0
JS		 196#endif
197 } sli3Feat;
dea3101e 198} lpfc_vpd_t;
199
200struct lpfc_scsi_buf;
201
202
203/*
204 * lpfc stat counters
205 */
206struct lpfc_stats {
207 /* Statistics for ELS commands */
208 uint32_t elsLogiCol;
209 uint32_t elsRetryExceeded;
210 uint32_t elsXmitRetry;
211 uint32_t elsDelayRetry;
212 uint32_t elsRcvDrop;
213 uint32_t elsRcvFrame;
214 uint32_t elsRcvRSCN;
215 uint32_t elsRcvRNID;
216 uint32_t elsRcvFARP;
217 uint32_t elsRcvFARPR;
218 uint32_t elsRcvFLOGI;
219 uint32_t elsRcvPLOGI;
220 uint32_t elsRcvADISC;
221 uint32_t elsRcvPDISC;
222 uint32_t elsRcvFAN;
223 uint32_t elsRcvLOGO;
224 uint32_t elsRcvPRLO;
225 uint32_t elsRcvPRLI;
7bb3b137 226 uint32_t elsRcvLIRR;
12265f68 227 uint32_t elsRcvRLS;
7bb3b137
JW		 228 uint32_t elsRcvRPS;
229 uint32_t elsRcvRPL;
5ffc266e 230 uint32_t elsRcvRRQ;
12265f68
JS		 231 uint32_t elsRcvRTV;
232 uint32_t elsRcvECHO;
dea3101e 233 uint32_t elsXmitFLOGI;
92d7f7b0 234 uint32_t elsXmitFDISC;
dea3101e 235 uint32_t elsXmitPLOGI;
236 uint32_t elsXmitPRLI;
237 uint32_t elsXmitADISC;
238 uint32_t elsXmitLOGO;
239 uint32_t elsXmitSCR;
240 uint32_t elsXmitRNID;
241 uint32_t elsXmitFARP;
242 uint32_t elsXmitFARPR;
243 uint32_t elsXmitACC;
244 uint32_t elsXmitLSRJT;
245
246 uint32_t frameRcvBcast;
247 uint32_t frameRcvMulti;
248 uint32_t strayXmitCmpl;
249 uint32_t frameXmitDelay;
250 uint32_t xriCmdCmpl;
251 uint32_t xriStatErr;
252 uint32_t LinkUp;
253 uint32_t LinkDown;
254 uint32_t LinkMultiEvent;
255 uint32_t NoRcvBuf;
256 uint32_t fcpCmd;
257 uint32_t fcpCmpl;
258 uint32_t fcpRspErr;
259 uint32_t fcpRemoteStop;
260 uint32_t fcpPortRjt;
261 uint32_t fcpPortBusy;
262 uint32_t fcpError;
263 uint32_t fcpLocalErr;
264};
265
2e0fef85
JS		 266struct lpfc_hba;
267
92d7f7b0 268
2e0fef85 269enum discovery_state {
92d7f7b0
JS		 270 LPFC_VPORT_UNKNOWN = 0, /* vport state is unknown */
271 LPFC_VPORT_FAILED = 1, /* vport has failed */
272 LPFC_LOCAL_CFG_LINK = 6, /* local NPORT Id configured */
273 LPFC_FLOGI = 7, /* FLOGI sent to Fabric */
274 LPFC_FDISC = 8, /* FDISC sent for vport */
275 LPFC_FABRIC_CFG_LINK = 9, /* Fabric assigned NPORT Id
276 * configured */
277 LPFC_NS_REG = 10, /* Register with NameServer */
278 LPFC_NS_QRY = 11, /* Query NameServer for NPort ID list */
279 LPFC_BUILD_DISC_LIST = 12, /* Build ADISC and PLOGI lists for
280 * device authentication / discovery */
281 LPFC_DISC_AUTH = 13, /* Processing ADISC list */
282 LPFC_VPORT_READY = 32,
2e0fef85
JS		 283};
284
285enum hba_state {
286 LPFC_LINK_UNKNOWN = 0, /* HBA state is unknown */
287 LPFC_WARM_START = 1, /* HBA state after selective reset */
288 LPFC_INIT_START = 2, /* Initial state after board reset */
289 LPFC_INIT_MBX_CMDS = 3, /* Initialize HBA with mbox commands */
290 LPFC_LINK_DOWN = 4, /* HBA initialized, link is down */
291 LPFC_LINK_UP = 5, /* Link is up - issue READ_LA */
92d7f7b0 292 LPFC_CLEAR_LA = 6, /* authentication cmplt - issue
2e0fef85 293 * CLEAR_LA */
92d7f7b0 294 LPFC_HBA_READY = 32,
2e0fef85
JS		 295 LPFC_HBA_ERROR = -1
296};
297
298struct lpfc_vport {
2e0fef85 299 struct lpfc_hba *phba;
3772a991 300 struct list_head listentry;
2e0fef85
JS		 301 uint8_t port_type;
302#define LPFC_PHYSICAL_PORT 1
303#define LPFC_NPIV_PORT 2
304#define LPFC_FABRIC_PORT 3
305 enum discovery_state port_state;
306
92d7f7b0 307 uint16_t vpi;
da0436e9 308 uint16_t vfi;
c868595d
JS		 309 uint8_t vpi_state;
310#define LPFC_VPI_REGISTERED 0x1
2e0fef85
JS		 311
312 uint32_t fc_flag; /* FC flags */
313/* Several of these flags are HBA centric and should be moved to
314 * phba->link_flag (e.g. FC_PTP, FC_PUBLIC_LOOP)
315 */
92d7f7b0
JS		 316#define FC_PT2PT 0x1 /* pt2pt with no fabric */
317#define FC_PT2PT_PLOGI 0x2 /* pt2pt initiate PLOGI */
318#define FC_DISC_TMO 0x4 /* Discovery timer running */
319#define FC_PUBLIC_LOOP 0x8 /* Public loop */
320#define FC_LBIT 0x10 /* LOGIN bit in loopinit set */
321#define FC_RSCN_MODE 0x20 /* RSCN cmd rcv'ed */
322#define FC_NLP_MORE 0x40 /* More node to process in node tbl */
323#define FC_OFFLINE_MODE 0x80 /* Interface is offline for diag */
324#define FC_FABRIC 0x100 /* We are fabric attached */
4b40c59e 325#define FC_VPORT_LOGO_RCVD 0x200 /* LOGO received on vport */
92d7f7b0 326#define FC_RSCN_DISCOVERY 0x400 /* Auth all devices after RSCN */
4b40c59e 327#define FC_LOGO_RCVD_DID_CHNG 0x800 /* FDISC on phys port detect DID chng*/
92d7f7b0
JS		 328#define FC_SCSI_SCAN_TMO 0x4000 /* scsi scan timer running */
329#define FC_ABORT_DISCOVERY 0x8000 /* we want to abort discovery */
330#define FC_NDISC_ACTIVE 0x10000 /* NPort discovery active */
331#define FC_BYPASSED_MODE 0x20000 /* NPort is in bypassed mode */
92d7f7b0
JS		 332#define FC_VPORT_NEEDS_REG_VPI 0x80000 /* Needs to have its vpi registered */
333#define FC_RSCN_DEFERRED 0x100000 /* A deferred RSCN being processed */
1c6834a7 334#define FC_VPORT_NEEDS_INIT_VPI 0x200000 /* Need to INIT_VPI before FDISC */
695a814e
JS		 335#define FC_VPORT_CVL_RCVD 0x400000 /* VLink failed due to CVL */
336#define FC_VFI_REGISTERED 0x800000 /* VFI is registered */
337#define FC_FDISC_COMPLETED 0x1000000/* FDISC completed */
92494144 338#define FC_DISC_DELAYED 0x2000000/* Delay NPort discovery */
2e0fef85 339
7ee5d43e
JS		 340 uint32_t ct_flags;
341#define FC_CT_RFF_ID 0x1 /* RFF_ID accepted by switch */
342#define FC_CT_RNN_ID 0x2 /* RNN_ID accepted by switch */
343#define FC_CT_RSNN_NN 0x4 /* RSNN_NN accepted by switch */
344#define FC_CT_RSPN_ID 0x8 /* RSPN_ID accepted by switch */
345#define FC_CT_RFT_ID 0x10 /* RFT_ID accepted by switch */
346
2e0fef85
JS		 347 struct list_head fc_nodes;
348
349 /* Keep counters for the number of entries in each list. */
350 uint16_t fc_plogi_cnt;
351 uint16_t fc_adisc_cnt;
352 uint16_t fc_reglogin_cnt;
353 uint16_t fc_prli_cnt;
354 uint16_t fc_unmap_cnt;
355 uint16_t fc_map_cnt;
356 uint16_t fc_npr_cnt;
357 uint16_t fc_unused_cnt;
358 struct serv_parm fc_sparam; /* buffer for our service parameters */
359
360 uint32_t fc_myDID; /* fibre channel S_ID */
361 uint32_t fc_prevDID; /* previous fibre channel S_ID */
92494144
JS		 362 struct lpfc_name fabric_portname;
363 struct lpfc_name fabric_nodename;
2e0fef85
JS		 364
365 int32_t stopped; /* HBA has not been restarted since last ERATT */
366 uint8_t fc_linkspeed; /* Link speed after last READ_LA */
367
368 uint32_t num_disc_nodes; /*in addition to hba_state */
369
370 uint32_t fc_nlp_cnt; /* outstanding NODELIST requests */
371 uint32_t fc_rscn_id_cnt; /* count of RSCNs payloads in list */
7f5f3d0d 372 uint32_t fc_rscn_flush; /* flag use of fc_rscn_id_list */
2e0fef85
JS		 373 struct lpfc_dmabuf *fc_rscn_id_list[FC_MAX_HOLD_RSCN];
374 struct lpfc_name fc_nodename; /* fc nodename */
375 struct lpfc_name fc_portname; /* fc portname */
376
377 struct lpfc_work_evt disc_timeout_evt;
378
379 struct timer_list fc_disctmo; /* Discovery rescue timer */
380 uint8_t fc_ns_retry; /* retries for fabric nameserver */
381 uint32_t fc_prli_sent; /* cntr for outstanding PRLIs */
382
383 spinlock_t work_port_lock;
384 uint32_t work_port_events; /* Timeout to be handled */
858c9f6c
JS		 385#define WORKER_DISC_TMO 0x1 /* vport: Discovery timeout */
386#define WORKER_ELS_TMO 0x2 /* vport: ELS timeout */
387#define WORKER_FDMI_TMO 0x4 /* vport: FDMI timeout */
92494144 388#define WORKER_DELAYED_DISC_TMO 0x8 /* vport: delayed discovery */
858c9f6c
JS		 389
390#define WORKER_MBOX_TMO 0x100 /* hba: MBOX timeout */
391#define WORKER_HB_TMO 0x200 /* hba: Heart beat timeout */
b1c11812 392#define WORKER_FABRIC_BLOCK_TMO 0x400 /* hba: fabric block timeout */
858c9f6c
JS		 393#define WORKER_RAMP_DOWN_QUEUE 0x800 /* hba: Decrease Q depth */
394#define WORKER_RAMP_UP_QUEUE 0x1000 /* hba: Increase Q depth */
2a9bf3d0 395#define WORKER_SERVICE_TXQ 0x2000 /* hba: IOCBs on the txq */
2e0fef85
JS		 396
397 struct timer_list fc_fdmitmo;
398 struct timer_list els_tmofunc;
92494144 399 struct timer_list delayed_disc_tmo;
2e0fef85
JS		 400
401 int unreg_vpi_cmpl;
402
403 uint8_t load_flag;
404#define FC_LOADING 0x1 /* HBA in process of loading drvr */
405#define FC_UNLOADING 0x2 /* HBA in process of unloading drvr */
3de2a653
JS		 406 /* Vport Config Parameters */
407 uint32_t cfg_scan_down;
408 uint32_t cfg_lun_queue_depth;
409 uint32_t cfg_nodev_tmo;
410 uint32_t cfg_devloss_tmo;
411 uint32_t cfg_restrict_login;
412 uint32_t cfg_peer_port_login;
413 uint32_t cfg_fcp_class;
414 uint32_t cfg_use_adisc;
415 uint32_t cfg_fdmi_on;
416 uint32_t cfg_discovery_threads;
e8b62011 417 uint32_t cfg_log_verbose;
3de2a653 418 uint32_t cfg_max_luns;
7ee5d43e 419 uint32_t cfg_enable_da_id;
977b5a0a 420 uint32_t cfg_max_scsicmpl_time;
7dc517df 421 uint32_t cfg_tgt_queue_depth;
3cb01c57 422 uint32_t cfg_first_burst_size;
3de2a653
JS		 423
424 uint32_t dev_loss_tmo_changed;
51ef4c26
JS		 425
426 struct fc_vport *fc_vport;
427
923e4b6a 428#ifdef CONFIG_SCSI_LPFC_DEBUG_FS
51ef4c26
JS		 429 struct dentry *debug_disc_trc;
430 struct dentry *debug_nodelist;
431 struct dentry *vport_debugfs_root;
432 struct lpfc_debugfs_trc *disc_trc;
433 atomic_t disc_trc_cnt;
434#endif
ea2151b4
JS		 435 uint8_t stat_data_enabled;
436 uint8_t stat_data_blocked;
da0436e9 437 struct list_head rcv_buffer_list;
45ed1190 438 unsigned long rcv_buffer_time_stamp;
da0436e9
JS		 439 uint32_t vport_flag;
440#define STATIC_VPORT 1
2e0fef85
JS		 441};
442
ed957684
JS		 443struct hbq_s {
444 uint16_t entry_count; /* Current number of HBQ slots */
a8adb832 445 uint16_t buffer_count; /* Current number of buffers posted */
ed957684
JS		 446 uint32_t next_hbqPutIdx; /* Index to next HBQ slot to use */
447 uint32_t hbqPutIdx; /* HBQ slot to use */
448 uint32_t local_hbqGetIdx; /* Local copy of Get index from Port */
51ef4c26
JS		 449 void *hbq_virt; /* Virtual ptr to this hbq */
450 struct list_head hbq_buffer_list; /* buffers assigned to this HBQ */
451 /* Callback for HBQ buffer allocation */
452 struct hbq_dmabuf *(*hbq_alloc_buffer) (struct lpfc_hba *);
453 /* Callback for HBQ buffer free */
454 void (*hbq_free_buffer) (struct lpfc_hba *,
455 struct hbq_dmabuf *);
ed957684
JS		 456};
457
51ef4c26
JS		 458#define LPFC_MAX_HBQS 4
459/* this matches the position in the lpfc_hbq_defs array */
92d7f7b0 460#define LPFC_ELS_HBQ 0
51ef4c26 461#define LPFC_EXTRA_HBQ 1
ed957684 462
7af67051
JS		 463enum hba_temp_state {
464 HBA_NORMAL_TEMP,
465 HBA_OVER_TEMP
466};
467
db2378e0
JS		 468enum intr_type_t {
469 NONE = 0,
470 INTx,
471 MSI,
472 MSIX,
473};
474
6dd9e31c 475#define LPFC_CT_CTX_MAX 64
f1c3b0fc
JS		 476struct unsol_rcv_ct_ctx {
477 uint32_t ctxt_id;
478 uint32_t SID;
6dd9e31c
JS		 479 uint32_t valid;
480#define UNSOL_INVALID 0
481#define UNSOL_VALID 1
7851fe2c
JS		 482 uint16_t oxid;
483 uint16_t rxid;
f1c3b0fc
JS		 484};
485
76a95d75
JS		 486#define LPFC_USER_LINK_SPEED_AUTO 0 /* auto select (default)*/
487#define LPFC_USER_LINK_SPEED_1G 1 /* 1 Gigabaud */
488#define LPFC_USER_LINK_SPEED_2G 2 /* 2 Gigabaud */
489#define LPFC_USER_LINK_SPEED_4G 4 /* 4 Gigabaud */
490#define LPFC_USER_LINK_SPEED_8G 8 /* 8 Gigabaud */
491#define LPFC_USER_LINK_SPEED_10G 10 /* 10 Gigabaud */
492#define LPFC_USER_LINK_SPEED_16G 16 /* 16 Gigabaud */
493#define LPFC_USER_LINK_SPEED_MAX LPFC_USER_LINK_SPEED_16G
494#define LPFC_USER_LINK_SPEED_BITMAP ((1 << LPFC_USER_LINK_SPEED_16G) | \
495 (1 << LPFC_USER_LINK_SPEED_10G) | \
496 (1 << LPFC_USER_LINK_SPEED_8G) | \
497 (1 << LPFC_USER_LINK_SPEED_4G) | \
498 (1 << LPFC_USER_LINK_SPEED_2G) | \
499 (1 << LPFC_USER_LINK_SPEED_1G) | \
500 (1 << LPFC_USER_LINK_SPEED_AUTO))
501#define LPFC_LINK_SPEED_STRING "0, 1, 2, 4, 8, 10, 16"
502
7ad20aa9
JS		 503enum nemb_type {
504 nemb_mse = 1,
505 nemb_hbd
506};
507
508enum mbox_type {
509 mbox_rd = 1,
510 mbox_wr
511};
512
513enum dma_type {
514 dma_mbox = 1,
515 dma_ebuf
516};
517
518enum sta_type {
519 sta_pre_addr = 1,
520 sta_pos_addr
521};
522
523struct lpfc_mbox_ext_buf_ctx {
524 uint32_t state;
525#define LPFC_BSG_MBOX_IDLE 0
526#define LPFC_BSG_MBOX_HOST 1
527#define LPFC_BSG_MBOX_PORT 2
528#define LPFC_BSG_MBOX_DONE 3
529#define LPFC_BSG_MBOX_ABTS 4
530 enum nemb_type nembType;
531 enum mbox_type mboxType;
532 uint32_t numBuf;
533 uint32_t mbxTag;
534 uint32_t seqNum;
535 struct lpfc_dmabuf *mbx_dmabuf;
536 struct list_head ext_dmabuf_list;
537};
538
dea3101e 539struct lpfc_hba {
3772a991
JS		 540 /* SCSI interface function jump table entries */
541 int (*lpfc_new_scsi_buf)
542 (struct lpfc_vport *, int);
543 struct lpfc_scsi_buf * (*lpfc_get_scsi_buf)
19ca7609 544 (struct lpfc_hba *, struct lpfc_nodelist *);
3772a991
JS		 545 int (*lpfc_scsi_prep_dma_buf)
546 (struct lpfc_hba *, struct lpfc_scsi_buf *);
547 void (*lpfc_scsi_unprep_dma_buf)
548 (struct lpfc_hba *, struct lpfc_scsi_buf *);
549 void (*lpfc_release_scsi_buf)
550 (struct lpfc_hba *, struct lpfc_scsi_buf *);
551 void (*lpfc_rampdown_queue_depth)
552 (struct lpfc_hba *);
553 void (*lpfc_scsi_prep_cmnd)
554 (struct lpfc_vport *, struct lpfc_scsi_buf *,
555 struct lpfc_nodelist *);
acd6859b 556
3772a991
JS		 557 /* IOCB interface function jump table entries */
558 int (*__lpfc_sli_issue_iocb)
559 (struct lpfc_hba *, uint32_t,
560 struct lpfc_iocbq *, uint32_t);
561 void (*__lpfc_sli_release_iocbq)(struct lpfc_hba *,
562 struct lpfc_iocbq *);
563 int (*lpfc_hba_down_post)(struct lpfc_hba *phba);
3772a991
JS		 564 IOCB_t * (*lpfc_get_iocb_from_iocbq)
565 (struct lpfc_iocbq *);
566 void (*lpfc_scsi_cmd_iocb_cmpl)
567 (struct lpfc_hba *, struct lpfc_iocbq *, struct lpfc_iocbq *);
568
569 /* MBOX interface function jump table entries */
570 int (*lpfc_sli_issue_mbox)
571 (struct lpfc_hba *, LPFC_MBOXQ_t *, uint32_t);
acd6859b 572
3772a991
JS		 573 /* Slow-path IOCB process function jump table entries */
574 void (*lpfc_sli_handle_slow_ring_event)
575 (struct lpfc_hba *phba, struct lpfc_sli_ring *pring,
576 uint32_t mask);
acd6859b 577
3772a991
JS		 578 /* INIT device interface function jump table entries */
579 int (*lpfc_sli_hbq_to_firmware)
580 (struct lpfc_hba *, uint32_t, struct hbq_dmabuf *);
581 int (*lpfc_sli_brdrestart)
582 (struct lpfc_hba *);
583 int (*lpfc_sli_brdready)
584 (struct lpfc_hba *, uint32_t);
585 void (*lpfc_handle_eratt)
586 (struct lpfc_hba *);
587 void (*lpfc_stop_port)
588 (struct lpfc_hba *);
84d1b006 589 int (*lpfc_hba_init_link)
6e7288d9 590 (struct lpfc_hba *, uint32_t);
84d1b006 591 int (*lpfc_hba_down_link)
6e7288d9 592 (struct lpfc_hba *, uint32_t);
7f86059a
JS		 593 int (*lpfc_selective_reset)
594 (struct lpfc_hba *);
3772a991 595
acd6859b
JS		 596 int (*lpfc_bg_scsi_prep_dma_buf)
597 (struct lpfc_hba *, struct lpfc_scsi_buf *);
598 /* Add new entries here */
599
3772a991
JS		 600 /* SLI4 specific HBA data structure */
601 struct lpfc_sli4_hba sli4_hba;
602
dea3101e 603 struct lpfc_sli sli;
3772a991
JS		 604 uint8_t pci_dev_grp; /* lpfc PCI dev group: 0x0, 0x1, 0x2,... */
605 uint32_t sli_rev; /* SLI2, SLI3, or SLI4 */
ed957684 606 uint32_t sli3_options; /* Mask of enabled SLI3 options */
34b02dcd
JS		 607#define LPFC_SLI3_HBQ_ENABLED 0x01
608#define LPFC_SLI3_NPIV_ENABLED 0x02
609#define LPFC_SLI3_VPORT_TEARDOWN 0x04
610#define LPFC_SLI3_CRP_ENABLED 0x08
81301a9b 611#define LPFC_SLI3_BG_ENABLED 0x20
da0436e9 612#define LPFC_SLI3_DSS_ENABLED 0x40
fedd3b7b
JS		 613#define LPFC_SLI4_PERFH_ENABLED 0x80
614#define LPFC_SLI4_PHWQ_ENABLED 0x100
ed957684
JS		 615 uint32_t iocb_cmd_size;
616 uint32_t iocb_rsp_size;
2e0fef85
JS		 617
618 enum hba_state link_state;
619 uint32_t link_flag; /* link state flags */
311464ec 620#define LS_LOOPBACK_MODE 0x1 /* NPort is in Loopback mode */
2e0fef85
JS		 621 /* This flag is set while issuing */
622 /* INIT_LINK mailbox command */
92d7f7b0 623#define LS_NPIV_FAB_SUPPORTED 0x2 /* Fabric supports NPIV */
1b32f6aa 624#define LS_IGNORE_ERATT 0x4 /* intr handler should ignore ERATT */
2e0fef85 625
9399627f
JS		 626 uint32_t hba_flag; /* hba generic flags */
627#define HBA_ERATT_HANDLED 0x1 /* This flag is set when eratt handled */
da0436e9 628#define DEFER_ERATT 0x2 /* Deferred error attention in progress */
76a95d75 629#define HBA_FCOE_MODE 0x4 /* HBA function in FCoE Mode */
45ed1190 630#define HBA_SP_QUEUE_EVT 0x8 /* Slow-path qevt posted to worker thread*/
da0436e9
JS		 631#define HBA_POST_RECEIVE_BUFFER 0x10 /* Rcv buffers need to be posted */
632#define FCP_XRI_ABORT_EVENT 0x20
633#define ELS_XRI_ABORT_EVENT 0x40
634#define ASYNC_EVENT 0x80
a0c87cbd 635#define LINK_DISABLED 0x100 /* Link disabled by user */
a93ff37a
JS		 636#define FCF_TS_INPROG 0x200 /* FCF table scan in progress */
637#define FCF_RR_INPROG 0x400 /* FCF roundrobin flogi in progress */
638#define HBA_FIP_SUPPORT 0x800 /* FIP support in HBA */
639#define HBA_AER_ENABLED 0x1000 /* AER enabled with HBA */
640#define HBA_DEVLOSS_TMO 0x2000 /* HBA in devloss timeout */
19ca7609 641#define HBA_RRQ_ACTIVE 0x4000 /* process the rrq active list */
4f2e66c6 642#define HBA_FCP_IOQ_FLUSH 0x8000 /* FCP I/O queues being flushed */
0293635e 643#define HBA_FW_DUMP_OP 0x10000 /* Skips fn reset before FW dump */
45ed1190 644 uint32_t fcp_ring_in_use; /* When polling test if intr-hndlr active*/
34b02dcd
JS		 645 struct lpfc_dmabuf slim2p;
646
647 MAILBOX_t *mbox;
7a470277 648 uint32_t *mbox_ext;
7ad20aa9 649 struct lpfc_mbox_ext_buf_ctx mbox_ext_buf_ctx;
9399627f 650 uint32_t ha_copy;
34b02dcd
JS		 651 struct _PCB *pcb;
652 struct _IOCB *IOCBs;
2e0fef85 653
34b02dcd 654 struct lpfc_dmabuf hbqslimp;
2e0fef85 655
dea3101e 656 uint16_t pci_cfg_value;
657
dea3101e 658 uint8_t fc_linkspeed; /* Link speed after last READ_LA */
659
660 uint32_t fc_eventTag; /* event tag for link attention */
4d9ab994 661 uint32_t link_events;
dea3101e 662
dea3101e 663 /* These fields used to be binfo */
dea3101e 664 uint32_t fc_pref_DID; /* preferred D_ID */
92d7f7b0 665 uint8_t fc_pref_ALPA; /* preferred AL_PA */
12265f68 666 uint32_t fc_edtovResol; /* E_D_TOV timer resolution */
dea3101e 667 uint32_t fc_edtov; /* E_D_TOV timer value */
668 uint32_t fc_arbtov; /* ARB_TOV timer value */
669 uint32_t fc_ratov; /* R_A_TOV timer value */
670 uint32_t fc_rttov; /* R_T_TOV timer value */
671 uint32_t fc_altov; /* AL_TOV timer value */
672 uint32_t fc_crtov; /* C_R_TOV timer value */
673 uint32_t fc_citov; /* C_I_TOV timer value */
dea3101e 674
dea3101e 675 struct serv_parm fc_fabparam; /* fabric service parameters buffer */
676 uint8_t alpa_map[128]; /* AL_PA map from READ_LA */
677
dea3101e 678 uint32_t lmt;
dea3101e 679
680 uint32_t fc_topology; /* link topology, from LINK INIT */
e74c03c8 681 uint32_t fc_topology_changed; /* link topology, from LINK INIT */
dea3101e 682
683 struct lpfc_stats fc_stat;
684
dea3101e 685 struct lpfc_nodelist fc_fcpnodev; /* nodelist entry for no device */
686 uint32_t nport_event_cnt; /* timestamp for nlplist entry */
687
2e0fef85
JS		 688 uint8_t wwnn[8];
689 uint8_t wwpn[8];
dea3101e 690 uint32_t RandomData[7];
691
3de2a653 692 /* HBA Config Parameters */
dea3101e 693 uint32_t cfg_ack0;
78b2d852 694 uint32_t cfg_enable_npiv;
19ca7609 695 uint32_t cfg_enable_rrq;
dea3101e 696 uint32_t cfg_topology;
dea3101e 697 uint32_t cfg_link_speed;
7d791df7
JS		 698#define LPFC_FCF_FOV 1 /* Fast fcf failover */
699#define LPFC_FCF_PRIORITY 2 /* Priority fcf failover */
700 uint32_t cfg_fcf_failover_policy;
49aa143d 701 uint32_t cfg_fcp_io_sched;
a6571c6e 702 uint32_t cfg_fcp2_no_tgt_reset;
dea3101e 703 uint32_t cfg_cr_delay;
704 uint32_t cfg_cr_count;
cf5bf97e 705 uint32_t cfg_multi_ring_support;
a4bc3379
JS		 706 uint32_t cfg_multi_ring_rctl;
707 uint32_t cfg_multi_ring_type;
875fbdfe
JSEC		 708 uint32_t cfg_poll;
709 uint32_t cfg_poll_tmo;
0c411222 710 uint32_t cfg_task_mgmt_tmo;
4ff43246 711 uint32_t cfg_use_msi;
da0436e9 712 uint32_t cfg_fcp_imax;
7bb03bbf 713 uint32_t cfg_fcp_cpu_map;
67d12733 714 uint32_t cfg_fcp_io_channel;
96f7077f 715 uint32_t cfg_total_seg_cnt;
dea3101e 716 uint32_t cfg_sg_seg_cnt;
81301a9b 717 uint32_t cfg_prot_sg_seg_cnt;
dea3101e 718 uint32_t cfg_sg_dma_buf_size;
a12e07bc 719 uint64_t cfg_soft_wwnn;
c3f28afa 720 uint64_t cfg_soft_wwpn;
3de2a653 721 uint32_t cfg_hba_queue_depth;
13815c83
JS		 722 uint32_t cfg_enable_hba_reset;
723 uint32_t cfg_enable_hba_heartbeat;
1ba981fd
JS		 724 uint32_t cfg_fof;
725 uint32_t cfg_EnableXLane;
726 uint8_t cfg_oas_tgt_wwpn[8];
727 uint8_t cfg_oas_vpt_wwpn[8];
728 uint32_t cfg_oas_lun_state;
729#define OAS_LUN_ENABLE 1
730#define OAS_LUN_DISABLE 0
731 uint32_t cfg_oas_lun_status;
732#define OAS_LUN_STATUS_EXISTS 0x01
733 uint32_t cfg_oas_flags;
734#define OAS_FIND_ANY_VPORT 0x01
735#define OAS_FIND_ANY_TARGET 0x02
736#define OAS_LUN_VALID 0x04
737 uint32_t cfg_XLanePriority;
81301a9b 738 uint32_t cfg_enable_bg;
7a470277 739 uint32_t cfg_hostmem_hgp;
da0436e9 740 uint32_t cfg_log_verbose;
0d878419 741 uint32_t cfg_aer_support;
912e3acd 742 uint32_t cfg_sriov_nr_virtfn;
c71ab861 743 uint32_t cfg_request_firmware_upgrade;
2a9bf3d0 744 uint32_t cfg_iocb_cnt;
84d1b006 745 uint32_t cfg_suppress_link_up;
cff261f6 746 uint32_t cfg_rrq_xri_bitmap_sz;
e40a02c1
JS		 747#define LPFC_INITIALIZE_LINK 0 /* do normal init_link mbox */
748#define LPFC_DELAY_INIT_LINK 1 /* layered driver hold off */
749#define LPFC_DELAY_INIT_LINK_INDEFINITELY 2 /* wait, manual intervention */
ab56dc2e 750 uint32_t cfg_enable_dss;
dea3101e 751 lpfc_vpd_t vpd; /* vital product data */
752
dea3101e 753 struct pci_dev *pcidev;
754 struct list_head work_list;
755 uint32_t work_ha; /* Host Attention Bits for WT */
756 uint32_t work_ha_mask; /* HA Bits owned by WT */
757 uint32_t work_hs; /* HS stored in case of ERRAT */
758 uint32_t work_status[2]; /* Extra status from SLIM */
dea3101e 759
5e9d9b82 760 wait_queue_head_t work_waitq;
dea3101e 761 struct task_struct *worker_thread;
d7c255b2 762 unsigned long data_flags;
dea3101e 763
3163f725 764 uint32_t hbq_in_use; /* HBQs in use flag */
3772a991 765 struct list_head rb_pend_list; /* Received buffers to be processed */
ed957684 766 uint32_t hbq_count; /* Count of configured HBQs */
92d7f7b0 767 struct hbq_s hbqs[LPFC_MAX_HBQS]; /* local copy of hbq indicies */
ed957684 768
2a76a283 769 atomic_t fcp_qidx; /* next work queue to post work to */
8fa38513 770
dea3101e 771 unsigned long pci_bar0_map; /* Physical address for PCI BAR0 */
3772a991 772 unsigned long pci_bar1_map; /* Physical address for PCI BAR1 */
dea3101e 773 unsigned long pci_bar2_map; /* Physical address for PCI BAR2 */
774 void __iomem *slim_memmap_p; /* Kernel memory mapped address for
775 PCI BAR0 */
776 void __iomem *ctrl_regs_memmap_p;/* Kernel memory mapped address for
777 PCI BAR2 */
778
962bc51b
JS		 779 void __iomem *pci_bar0_memmap_p; /* Kernel memory mapped address for
780 PCI BAR0 with dual-ULP support */
781 void __iomem *pci_bar2_memmap_p; /* Kernel memory mapped address for
782 PCI BAR2 with dual-ULP support */
783 void __iomem *pci_bar4_memmap_p; /* Kernel memory mapped address for
784 PCI BAR4 with dual-ULP support */
785#define PCI_64BIT_BAR0 0
786#define PCI_64BIT_BAR2 2
787#define PCI_64BIT_BAR4 4
dea3101e 788 void __iomem *MBslimaddr; /* virtual address for mbox cmds */
789 void __iomem *HAregaddr; /* virtual address for host attn reg */
790 void __iomem *CAregaddr; /* virtual address for chip attn reg */
791 void __iomem *HSregaddr; /* virtual address for host status
792 reg */
793 void __iomem *HCregaddr; /* virtual address for host ctl reg */
794
ed957684 795 struct lpfc_hgp __iomem *host_gp; /* Host side get/put pointers */
34b02dcd 796 struct lpfc_pgp *port_gp;
ed957684 797 uint32_t __iomem *hbq_put; /* Address in SLIM to HBQ put ptrs */
92d7f7b0 798 uint32_t *hbq_get; /* Host mem address of HBQ get ptrs */
ed957684 799
dea3101e 800 int brd_no; /* FC board number */
dea3101e 801 char SerialNumber[32]; /* adapter Serial Number */
802 char OptionROMVersion[32]; /* adapter BIOS / Fcode version */
803 char ModelDesc[256]; /* Model Description */
804 char ModelName[80]; /* Model Name */
805 char ProgramType[256]; /* Program Type */
806 char Port[20]; /* Port No */
807 uint8_t vpd_flag; /* VPD data flag */
808
809#define VPD_MODEL_DESC 0x1 /* valid vpd model description */
810#define VPD_MODEL_NAME 0x2 /* valid vpd model name */
811#define VPD_PROGRAM_TYPE 0x4 /* valid vpd program type */
812#define VPD_PORT 0x8 /* valid vpd port data */
813#define VPD_MASK 0xf /* mask for any vpd data */
814
a12e07bc 815 uint8_t soft_wwn_enable;
c3f28afa 816
875fbdfe 817 struct timer_list fcp_poll_timer;
9399627f 818 struct timer_list eratt_poll;
875fbdfe 819
dea3101e 820 /*
821 * stat counters
822 */
823 uint64_t fc4InputRequests;
824 uint64_t fc4OutputRequests;
825 uint64_t fc4ControlRequests;
81301a9b
JS		 826 uint64_t bg_guard_err_cnt;
827 uint64_t bg_apptag_err_cnt;
828 uint64_t bg_reftag_err_cnt;
dea3101e 829
dea3101e 830 /* fastpath list. */
a40fc5f0
JS		 831 spinlock_t scsi_buf_list_get_lock; /* SCSI buf alloc list lock */
832 spinlock_t scsi_buf_list_put_lock; /* SCSI buf free list lock */
833 struct list_head lpfc_scsi_buf_list_get;
834 struct list_head lpfc_scsi_buf_list_put;
dea3101e 835 uint32_t total_scsi_bufs;
836 struct list_head lpfc_iocb_list;
837 uint32_t total_iocbq_bufs;
19ca7609 838 struct list_head active_rrq_list;
2e0fef85 839 spinlock_t hbalock;
dea3101e 840
841 /* pci_mem_pools */
842 struct pci_pool *lpfc_scsi_dma_buf_pool;
843 struct pci_pool *lpfc_mbuf_pool;
da0436e9
JS		 844 struct pci_pool *lpfc_hrb_pool; /* header receive buffer pool */
845 struct pci_pool *lpfc_drb_pool; /* data receive buffer pool */
8568a4d2 846 struct pci_pool *lpfc_hbq_pool; /* SLI3 hbq buffer pool */
dea3101e 847 struct lpfc_dma_pool lpfc_mbuf_safety_pool;
848
849 mempool_t *mbox_mem_pool;
850 mempool_t *nlp_mem_pool;
19ca7609 851 mempool_t *rrq_pool;
cff261f6 852 mempool_t *active_rrq_pool;
f888ba3c
JSEC		 853
854 struct fc_host_statistics link_stats;
db2378e0 855 enum intr_type_t intr_type;
5b75da2f
JS		 856 uint32_t intr_mode;
857#define LPFC_INTR_ERROR 0xFFFFFFFF
9399627f 858 struct msix_entry msix_entries[LPFC_MSIX_VECTORS];
858c9f6c 859
2e0fef85 860 struct list_head port_list;
549e55cd
JS		 861 struct lpfc_vport *pport; /* physical lpfc_vport pointer */
862 uint16_t max_vpi; /* Maximum virtual nports */
09372820 863#define LPFC_MAX_VPI 0xFFFF /* Max number of VPI supported */
da0436e9
JS		 864 uint16_t max_vports; /*
865 * For IOV HBAs max_vpi can change
866 * after a reset. max_vports is max
867 * number of vports present. This can
868 * be greater than max_vpi.
869 */
870 uint16_t vpi_base;
871 uint16_t vfi_base;
549e55cd 872 unsigned long *vpi_bmask; /* vpi allocation table */
6d368e53
JS		 873 uint16_t *vpi_ids;
874 uint16_t vpi_count;
875 struct list_head lpfc_vpi_blk_list;
92d7f7b0
JS		 876
877 /* Data structure used by fabric iocb scheduler */
878 struct list_head fabric_iocb_list;
879 atomic_t fabric_iocb_count;
880 struct timer_list fabric_block_timer;
881 unsigned long bit_flags;
882#define FABRIC_COMANDS_BLOCKED 0
883 atomic_t num_rsrc_err;
884 atomic_t num_cmd_success;
885 unsigned long last_rsrc_error_time;
886 unsigned long last_ramp_down_time;
923e4b6a 887#ifdef CONFIG_SCSI_LPFC_DEBUG_FS
858c9f6c
JS		 888 struct dentry *hba_debugfs_root;
889 atomic_t debugfs_vport_count;
78b2d852 890 struct dentry *debug_hbqinfo;
c95d6c6c
JS		 891 struct dentry *debug_dumpHostSlim;
892 struct dentry *debug_dumpHBASlim;
f9bb2da1
JS		 893 struct dentry *debug_dumpData; /* BlockGuard BPL */
894 struct dentry *debug_dumpDif; /* BlockGuard BPL */
895 struct dentry *debug_InjErrLBA; /* LBA to inject errors at */
4ac9b226
JS		 896 struct dentry *debug_InjErrNPortID; /* NPortID to inject errors at */
897 struct dentry *debug_InjErrWWPN; /* WWPN to inject errors at */
f9bb2da1
JS		 898 struct dentry *debug_writeGuard; /* inject write guard_tag errors */
899 struct dentry *debug_writeApp; /* inject write app_tag errors */
900 struct dentry *debug_writeRef; /* inject write ref_tag errors */
acd6859b 901 struct dentry *debug_readGuard; /* inject read guard_tag errors */
f9bb2da1
JS		 902 struct dentry *debug_readApp; /* inject read app_tag errors */
903 struct dentry *debug_readRef; /* inject read ref_tag errors */
904
905 /* T10 DIF error injection */
906 uint32_t lpfc_injerr_wgrd_cnt;
907 uint32_t lpfc_injerr_wapp_cnt;
908 uint32_t lpfc_injerr_wref_cnt;
acd6859b 909 uint32_t lpfc_injerr_rgrd_cnt;
f9bb2da1
JS		 910 uint32_t lpfc_injerr_rapp_cnt;
911 uint32_t lpfc_injerr_rref_cnt;
4ac9b226
JS		 912 uint32_t lpfc_injerr_nportid;
913 struct lpfc_name lpfc_injerr_wwpn;
f9bb2da1 914 sector_t lpfc_injerr_lba;
acd6859b 915#define LPFC_INJERR_LBA_OFF (sector_t)(-1)
f9bb2da1 916
a58cbd52
JS		 917 struct dentry *debug_slow_ring_trc;
918 struct lpfc_debugfs_trc *slow_ring_trc;
919 atomic_t slow_ring_trc_cnt;
2a622bfb
JS		 920 /* iDiag debugfs sub-directory */
921 struct dentry *idiag_root;
922 struct dentry *idiag_pci_cfg;
b76f2dc9 923 struct dentry *idiag_bar_acc;
2a622bfb 924 struct dentry *idiag_que_info;
86a80846
JS		 925 struct dentry *idiag_que_acc;
926 struct dentry *idiag_drb_acc;
b76f2dc9
JS		 927 struct dentry *idiag_ctl_acc;
928 struct dentry *idiag_mbx_acc;
929 struct dentry *idiag_ext_acc;
858c9f6c
JS		 930#endif
931
0ff10d46
JS		 932 /* Used for deferred freeing of ELS data buffers */
933 struct list_head elsbuf;
934 int elsbuf_cnt;
935 int elsbuf_prev_cnt;
936
57127f15 937 uint8_t temp_sensor_support;
858c9f6c
JS		 938 /* Fields used for heart beat. */
939 unsigned long last_completion_time;
bc73905a 940 unsigned long skipped_hb;
858c9f6c
JS		 941 struct timer_list hb_tmofunc;
942 uint8_t hb_outstanding;
19ca7609 943 struct timer_list rrq_tmr;
84774a4d 944 enum hba_temp_state over_temp_state;
e47c9093
JS		 945 /* ndlp reference management */
946 spinlock_t ndlp_lock;
76bb24ef
JS		 947 /*
948 * Following bit will be set for all buffer tags which are not
949 * associated with any HBQ.
950 */
951#define QUE_BUFTAG_BIT (1<<31)
952 uint32_t buffer_tag_count;
84774a4d
JS		 953 int wait_4_mlo_maint_flg;
954 wait_queue_head_t wait_4_mlo_m_q;
ea2151b4
JS		 955 /* data structure used for latency data collection */
956#define LPFC_NO_BUCKET 0
957#define LPFC_LINEAR_BUCKET 1
958#define LPFC_POWER2_BUCKET 2
959 uint8_t bucket_type;
960 uint32_t bucket_base;
961 uint32_t bucket_step;
962
963/* Maximum number of events that can be outstanding at any time*/
964#define LPFC_MAX_EVT_COUNT 512
965 atomic_t fast_event_count;
32b9793f
JS		 966 uint32_t fcoe_eventtag;
967 uint32_t fcoe_eventtag_at_fcf_scan;
80c17849
JS		 968 uint32_t fcoe_cvl_eventtag;
969 uint32_t fcoe_cvl_eventtag_attn;
da0436e9
JS		 970 struct lpfc_fcf fcf;
971 uint8_t fc_map[3];
972 uint8_t valid_vlan;
973 uint16_t vlan_id;
974 struct list_head fcf_conn_rec_list;
f1c3b0fc 975
4fede78f 976 spinlock_t ct_ev_lock; /* synchronize access to ct_ev_waiters */
f1c3b0fc 977 struct list_head ct_ev_waiters;
6dd9e31c 978 struct unsol_rcv_ct_ctx ct_ctx[LPFC_CT_CTX_MAX];
f1c3b0fc 979 uint32_t ctx_idx;
e2aed29f
JS		 980
981 uint8_t menlo_flag; /* menlo generic flags */
982#define HBA_MENLO_SUPPORT 0x1 /* HBA supports menlo commands */
2a9bf3d0
JS		 983 uint32_t iocb_cnt;
984 uint32_t iocb_max;
d7c47992 985 atomic_t sdev_cnt;
bc73905a
JS		 986 uint8_t fips_spec_rev;
987 uint8_t fips_level;
1ba981fd
JS		 988 spinlock_t devicelock; /* lock for luns list */
989 mempool_t *device_data_mem_pool;
990 struct list_head luns;
dea3101e 991};
992
2e0fef85
JS		 993static inline struct Scsi_Host *
994lpfc_shost_from_vport(struct lpfc_vport *vport)
995{
996 return container_of((void *) vport, struct Scsi_Host, hostdata[0]);
997}
998
5b8bd0c9 999static inline void
2e0fef85
JS		 1000lpfc_set_loopback_flag(struct lpfc_hba *phba)
1001{
5b8bd0c9 1002 if (phba->cfg_topology == FLAGS_LOCAL_LB)
2e0fef85 1003 phba->link_flag |= LS_LOOPBACK_MODE;
5b8bd0c9 1004 else
2e0fef85
JS		 1005 phba->link_flag &= ~LS_LOOPBACK_MODE;
1006}
1007
1008static inline int
1009lpfc_is_link_up(struct lpfc_hba *phba)
1010{
1011 return phba->link_state == LPFC_LINK_UP ||
92d7f7b0
JS		 1012 phba->link_state == LPFC_CLEAR_LA ||
1013 phba->link_state == LPFC_HBA_READY;
5b8bd0c9 1014}
dea3101e 1015
5e9d9b82
JS		 1016static inline void
1017lpfc_worker_wake_up(struct lpfc_hba *phba)
1018{
1019 /* Set the lpfc data pending flag */
1020 set_bit(LPFC_DATA_READY, &phba->data_flags);
1021
1022 /* Wake up worker thread */
1023 wake_up(&phba->work_waitq);
1024 return;
1025}
1026
9940b97b
JS		 1027static inline int
1028lpfc_readl(void __iomem *addr, uint32_t *data)
1029{
1030 uint32_t temp;
1031 temp = readl(addr);
1032 if (temp == 0xffffffff)
1033 return -EIO;
1034 *data = temp;
1035 return 0;
1036}
1037
1038static inline int
9399627f
JS		 1039lpfc_sli_read_hs(struct lpfc_hba *phba)
1040{
1041 /*
1042 * There was a link/board error. Read the status register to retrieve
1043 * the error event and process it.
1044 */
1045 phba->sli.slistat.err_attn_event++;
1046
9940b97b
JS		 1047 /* Save status info and check for unplug error */
1048 if (lpfc_readl(phba->HSregaddr, &phba->work_hs) ||
1049 lpfc_readl(phba->MBslimaddr + 0xa8, &phba->work_status[0]) ||
1050 lpfc_readl(phba->MBslimaddr + 0xac, &phba->work_status[1])) {
1051 return -EIO;
1052 }
9399627f
JS		 1053
1054 /* Clear chip Host Attention error bit */
1055 writel(HA_ERATT, phba->HAregaddr);
1056 readl(phba->HAregaddr); /* flush */
1057 phba->pport->stopped = 1;
1058
9940b97b 1059 return 0;
9399627f 1060}
Linux kernel - Deliverables
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