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c4a3e0a5 | 1 | /* |
3f1530c1 | 2 | * Linux MegaRAID driver for SAS based RAID controllers |
c4a3e0a5 | 3 | * |
e399065b SS |
4 | * Copyright (c) 2003-2013 LSI Corporation |
5 | * Copyright (c) 2013-2014 Avago Technologies | |
c4a3e0a5 | 6 | * |
3f1530c1 | 7 | * This program is free software; you can redistribute it and/or |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; either version 2 | |
10 | * of the License, or (at your option) any later version. | |
c4a3e0a5 | 11 | * |
3f1530c1 | 12 | * This program is distributed in the hope that it will be useful, |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
c4a3e0a5 | 16 | * |
3f1530c1 | 17 | * You should have received a copy of the GNU General Public License |
e399065b | 18 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
3f1530c1 | 19 | * |
20 | * FILE: megaraid_sas.h | |
21 | * | |
e399065b SS |
22 | * Authors: Avago Technologies |
23 | * Kashyap Desai <kashyap.desai@avagotech.com> | |
24 | * Sumit Saxena <sumit.saxena@avagotech.com> | |
3f1530c1 | 25 | * |
e399065b | 26 | * Send feedback to: megaraidlinux.pdl@avagotech.com |
3f1530c1 | 27 | * |
e399065b SS |
28 | * Mail to: Avago Technologies, 350 West Trimble Road, Building 90, |
29 | * San Jose, California 95131 | |
c4a3e0a5 BS |
30 | */ |
31 | ||
32 | #ifndef LSI_MEGARAID_SAS_H | |
33 | #define LSI_MEGARAID_SAS_H | |
34 | ||
a69b74d3 | 35 | /* |
c4a3e0a5 BS |
36 | * MegaRAID SAS Driver meta data |
37 | */ | |
54c40428 SS |
38 | #define MEGASAS_VERSION "06.811.02.00-rc1" |
39 | #define MEGASAS_RELDATE "April 12, 2016" | |
0e98936c SP |
40 | |
41 | /* | |
42 | * Device IDs | |
43 | */ | |
44 | #define PCI_DEVICE_ID_LSI_SAS1078R 0x0060 | |
af7a5647 | 45 | #define PCI_DEVICE_ID_LSI_SAS1078DE 0x007C |
0e98936c | 46 | #define PCI_DEVICE_ID_LSI_VERDE_ZCR 0x0413 |
6610a6b3 YB |
47 | #define PCI_DEVICE_ID_LSI_SAS1078GEN2 0x0078 |
48 | #define PCI_DEVICE_ID_LSI_SAS0079GEN2 0x0079 | |
87911122 YB |
49 | #define PCI_DEVICE_ID_LSI_SAS0073SKINNY 0x0073 |
50 | #define PCI_DEVICE_ID_LSI_SAS0071SKINNY 0x0071 | |
9c915a8c | 51 | #define PCI_DEVICE_ID_LSI_FUSION 0x005b |
229fe47c | 52 | #define PCI_DEVICE_ID_LSI_PLASMA 0x002f |
36807e67 | 53 | #define PCI_DEVICE_ID_LSI_INVADER 0x005d |
21d3c710 | 54 | #define PCI_DEVICE_ID_LSI_FURY 0x005f |
90c204bc | 55 | #define PCI_DEVICE_ID_LSI_INTRUDER 0x00ce |
56 | #define PCI_DEVICE_ID_LSI_INTRUDER_24 0x00cf | |
7364d34b | 57 | #define PCI_DEVICE_ID_LSI_CUTLASS_52 0x0052 |
58 | #define PCI_DEVICE_ID_LSI_CUTLASS_53 0x0053 | |
0e98936c | 59 | |
39b72c3c SS |
60 | /* |
61 | * Intel HBA SSDIDs | |
62 | */ | |
63 | #define MEGARAID_INTEL_RS3DC080_SSDID 0x9360 | |
64 | #define MEGARAID_INTEL_RS3DC040_SSDID 0x9362 | |
65 | #define MEGARAID_INTEL_RS3SC008_SSDID 0x9380 | |
66 | #define MEGARAID_INTEL_RS3MC044_SSDID 0x9381 | |
67 | #define MEGARAID_INTEL_RS3WC080_SSDID 0x9341 | |
68 | #define MEGARAID_INTEL_RS3WC040_SSDID 0x9343 | |
7364d34b | 69 | #define MEGARAID_INTEL_RMS3BC160_SSDID 0x352B |
39b72c3c | 70 | |
90c204bc | 71 | /* |
72 | * Intruder HBA SSDIDs | |
73 | */ | |
74 | #define MEGARAID_INTRUDER_SSDID1 0x9371 | |
75 | #define MEGARAID_INTRUDER_SSDID2 0x9390 | |
76 | #define MEGARAID_INTRUDER_SSDID3 0x9370 | |
77 | ||
39b72c3c SS |
78 | /* |
79 | * Intel HBA branding | |
80 | */ | |
81 | #define MEGARAID_INTEL_RS3DC080_BRANDING \ | |
82 | "Intel(R) RAID Controller RS3DC080" | |
83 | #define MEGARAID_INTEL_RS3DC040_BRANDING \ | |
84 | "Intel(R) RAID Controller RS3DC040" | |
85 | #define MEGARAID_INTEL_RS3SC008_BRANDING \ | |
86 | "Intel(R) RAID Controller RS3SC008" | |
87 | #define MEGARAID_INTEL_RS3MC044_BRANDING \ | |
88 | "Intel(R) RAID Controller RS3MC044" | |
89 | #define MEGARAID_INTEL_RS3WC080_BRANDING \ | |
90 | "Intel(R) RAID Controller RS3WC080" | |
91 | #define MEGARAID_INTEL_RS3WC040_BRANDING \ | |
92 | "Intel(R) RAID Controller RS3WC040" | |
7364d34b | 93 | #define MEGARAID_INTEL_RMS3BC160_BRANDING \ |
94 | "Intel(R) Integrated RAID Module RMS3BC160" | |
39b72c3c | 95 | |
c4a3e0a5 BS |
96 | /* |
97 | * ===================================== | |
98 | * MegaRAID SAS MFI firmware definitions | |
99 | * ===================================== | |
100 | */ | |
101 | ||
102 | /* | |
103 | * MFI stands for MegaRAID SAS FW Interface. This is just a moniker for | |
104 | * protocol between the software and firmware. Commands are issued using | |
105 | * "message frames" | |
106 | */ | |
107 | ||
a69b74d3 | 108 | /* |
c4a3e0a5 BS |
109 | * FW posts its state in upper 4 bits of outbound_msg_0 register |
110 | */ | |
111 | #define MFI_STATE_MASK 0xF0000000 | |
112 | #define MFI_STATE_UNDEFINED 0x00000000 | |
113 | #define MFI_STATE_BB_INIT 0x10000000 | |
114 | #define MFI_STATE_FW_INIT 0x40000000 | |
115 | #define MFI_STATE_WAIT_HANDSHAKE 0x60000000 | |
116 | #define MFI_STATE_FW_INIT_2 0x70000000 | |
117 | #define MFI_STATE_DEVICE_SCAN 0x80000000 | |
e3bbff9f | 118 | #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000 |
c4a3e0a5 BS |
119 | #define MFI_STATE_FLUSH_CACHE 0xA0000000 |
120 | #define MFI_STATE_READY 0xB0000000 | |
121 | #define MFI_STATE_OPERATIONAL 0xC0000000 | |
122 | #define MFI_STATE_FAULT 0xF0000000 | |
fc62b3fc SS |
123 | #define MFI_STATE_FORCE_OCR 0x00000080 |
124 | #define MFI_STATE_DMADONE 0x00000008 | |
125 | #define MFI_STATE_CRASH_DUMP_DONE 0x00000004 | |
7e70e733 | 126 | #define MFI_RESET_REQUIRED 0x00000001 |
127 | #define MFI_RESET_ADAPTER 0x00000002 | |
c4a3e0a5 BS |
128 | #define MEGAMFI_FRAME_SIZE 64 |
129 | ||
a69b74d3 | 130 | /* |
c4a3e0a5 BS |
131 | * During FW init, clear pending cmds & reset state using inbound_msg_0 |
132 | * | |
133 | * ABORT : Abort all pending cmds | |
134 | * READY : Move from OPERATIONAL to READY state; discard queue info | |
135 | * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??) | |
136 | * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver | |
e3bbff9f SP |
137 | * HOTPLUG : Resume from Hotplug |
138 | * MFI_STOP_ADP : Send signal to FW to stop processing | |
c4a3e0a5 | 139 | */ |
39a98554 | 140 | #define WRITE_SEQUENCE_OFFSET (0x0000000FC) /* I20 */ |
141 | #define HOST_DIAGNOSTIC_OFFSET (0x000000F8) /* I20 */ | |
142 | #define DIAG_WRITE_ENABLE (0x00000080) | |
143 | #define DIAG_RESET_ADAPTER (0x00000004) | |
144 | ||
145 | #define MFI_ADP_RESET 0x00000040 | |
e3bbff9f | 146 | #define MFI_INIT_ABORT 0x00000001 |
c4a3e0a5 BS |
147 | #define MFI_INIT_READY 0x00000002 |
148 | #define MFI_INIT_MFIMODE 0x00000004 | |
149 | #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008 | |
e3bbff9f SP |
150 | #define MFI_INIT_HOTPLUG 0x00000010 |
151 | #define MFI_STOP_ADP 0x00000020 | |
152 | #define MFI_RESET_FLAGS MFI_INIT_READY| \ | |
153 | MFI_INIT_MFIMODE| \ | |
154 | MFI_INIT_ABORT | |
179ac142 | 155 | #define MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE (0x01) |
c4a3e0a5 | 156 | |
a69b74d3 | 157 | /* |
c4a3e0a5 BS |
158 | * MFI frame flags |
159 | */ | |
160 | #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 | |
161 | #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 | |
162 | #define MFI_FRAME_SGL32 0x0000 | |
163 | #define MFI_FRAME_SGL64 0x0002 | |
164 | #define MFI_FRAME_SENSE32 0x0000 | |
165 | #define MFI_FRAME_SENSE64 0x0004 | |
166 | #define MFI_FRAME_DIR_NONE 0x0000 | |
167 | #define MFI_FRAME_DIR_WRITE 0x0008 | |
168 | #define MFI_FRAME_DIR_READ 0x0010 | |
169 | #define MFI_FRAME_DIR_BOTH 0x0018 | |
f4c9a131 | 170 | #define MFI_FRAME_IEEE 0x0020 |
c4a3e0a5 | 171 | |
4026e9aa SS |
172 | /* Driver internal */ |
173 | #define DRV_DCMD_POLLED_MODE 0x1 | |
6d40afbc | 174 | #define DRV_DCMD_SKIP_REFIRE 0x2 |
4026e9aa | 175 | |
a69b74d3 | 176 | /* |
c4a3e0a5 BS |
177 | * Definition for cmd_status |
178 | */ | |
179 | #define MFI_CMD_STATUS_POLL_MODE 0xFF | |
180 | ||
a69b74d3 | 181 | /* |
c4a3e0a5 BS |
182 | * MFI command opcodes |
183 | */ | |
184 | #define MFI_CMD_INIT 0x00 | |
185 | #define MFI_CMD_LD_READ 0x01 | |
186 | #define MFI_CMD_LD_WRITE 0x02 | |
187 | #define MFI_CMD_LD_SCSI_IO 0x03 | |
188 | #define MFI_CMD_PD_SCSI_IO 0x04 | |
189 | #define MFI_CMD_DCMD 0x05 | |
190 | #define MFI_CMD_ABORT 0x06 | |
191 | #define MFI_CMD_SMP 0x07 | |
192 | #define MFI_CMD_STP 0x08 | |
e5f93a36 | 193 | #define MFI_CMD_INVALID 0xff |
c4a3e0a5 BS |
194 | |
195 | #define MR_DCMD_CTRL_GET_INFO 0x01010000 | |
bdc6fb8d | 196 | #define MR_DCMD_LD_GET_LIST 0x03010000 |
21c9e160 | 197 | #define MR_DCMD_LD_LIST_QUERY 0x03010100 |
c4a3e0a5 BS |
198 | |
199 | #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000 | |
200 | #define MR_FLUSH_CTRL_CACHE 0x01 | |
201 | #define MR_FLUSH_DISK_CACHE 0x02 | |
202 | ||
203 | #define MR_DCMD_CTRL_SHUTDOWN 0x01050000 | |
31ea7088 | 204 | #define MR_DCMD_HIBERNATE_SHUTDOWN 0x01060000 |
c4a3e0a5 BS |
205 | #define MR_ENABLE_DRIVE_SPINDOWN 0x01 |
206 | ||
207 | #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100 | |
208 | #define MR_DCMD_CTRL_EVENT_GET 0x01040300 | |
209 | #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500 | |
210 | #define MR_DCMD_LD_GET_PROPERTIES 0x03030000 | |
211 | ||
212 | #define MR_DCMD_CLUSTER 0x08000000 | |
213 | #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100 | |
214 | #define MR_DCMD_CLUSTER_RESET_LD 0x08010200 | |
81e403ce | 215 | #define MR_DCMD_PD_LIST_QUERY 0x02010100 |
c4a3e0a5 | 216 | |
fc62b3fc SS |
217 | #define MR_DCMD_CTRL_SET_CRASH_DUMP_PARAMS 0x01190100 |
218 | #define MR_DRIVER_SET_APP_CRASHDUMP_MODE (0xF0010000 | 0x0600) | |
2216c305 | 219 | #define MR_DCMD_PD_GET_INFO 0x02020000 |
fc62b3fc | 220 | |
bc93d425 SS |
221 | /* |
222 | * Global functions | |
223 | */ | |
224 | extern u8 MR_ValidateMapInfo(struct megasas_instance *instance); | |
225 | ||
226 | ||
a69b74d3 | 227 | /* |
c4a3e0a5 BS |
228 | * MFI command completion codes |
229 | */ | |
230 | enum MFI_STAT { | |
231 | MFI_STAT_OK = 0x00, | |
232 | MFI_STAT_INVALID_CMD = 0x01, | |
233 | MFI_STAT_INVALID_DCMD = 0x02, | |
234 | MFI_STAT_INVALID_PARAMETER = 0x03, | |
235 | MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04, | |
236 | MFI_STAT_ABORT_NOT_POSSIBLE = 0x05, | |
237 | MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06, | |
238 | MFI_STAT_APP_IN_USE = 0x07, | |
239 | MFI_STAT_APP_NOT_INITIALIZED = 0x08, | |
240 | MFI_STAT_ARRAY_INDEX_INVALID = 0x09, | |
241 | MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a, | |
242 | MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b, | |
243 | MFI_STAT_DEVICE_NOT_FOUND = 0x0c, | |
244 | MFI_STAT_DRIVE_TOO_SMALL = 0x0d, | |
245 | MFI_STAT_FLASH_ALLOC_FAIL = 0x0e, | |
246 | MFI_STAT_FLASH_BUSY = 0x0f, | |
247 | MFI_STAT_FLASH_ERROR = 0x10, | |
248 | MFI_STAT_FLASH_IMAGE_BAD = 0x11, | |
249 | MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12, | |
250 | MFI_STAT_FLASH_NOT_OPEN = 0x13, | |
251 | MFI_STAT_FLASH_NOT_STARTED = 0x14, | |
252 | MFI_STAT_FLUSH_FAILED = 0x15, | |
253 | MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16, | |
254 | MFI_STAT_LD_CC_IN_PROGRESS = 0x17, | |
255 | MFI_STAT_LD_INIT_IN_PROGRESS = 0x18, | |
256 | MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19, | |
257 | MFI_STAT_LD_MAX_CONFIGURED = 0x1a, | |
258 | MFI_STAT_LD_NOT_OPTIMAL = 0x1b, | |
259 | MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c, | |
260 | MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d, | |
261 | MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e, | |
262 | MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f, | |
263 | MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, | |
264 | MFI_STAT_MFC_HW_ERROR = 0x21, | |
265 | MFI_STAT_NO_HW_PRESENT = 0x22, | |
266 | MFI_STAT_NOT_FOUND = 0x23, | |
267 | MFI_STAT_NOT_IN_ENCL = 0x24, | |
268 | MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25, | |
269 | MFI_STAT_PD_TYPE_WRONG = 0x26, | |
270 | MFI_STAT_PR_DISABLED = 0x27, | |
271 | MFI_STAT_ROW_INDEX_INVALID = 0x28, | |
272 | MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29, | |
273 | MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a, | |
274 | MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b, | |
275 | MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c, | |
276 | MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d, | |
277 | MFI_STAT_SCSI_IO_FAILED = 0x2e, | |
278 | MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f, | |
279 | MFI_STAT_SHUTDOWN_FAILED = 0x30, | |
280 | MFI_STAT_TIME_NOT_SET = 0x31, | |
281 | MFI_STAT_WRONG_STATE = 0x32, | |
282 | MFI_STAT_LD_OFFLINE = 0x33, | |
283 | MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34, | |
284 | MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35, | |
285 | MFI_STAT_RESERVATION_IN_PROGRESS = 0x36, | |
286 | MFI_STAT_I2C_ERRORS_DETECTED = 0x37, | |
287 | MFI_STAT_PCI_ERRORS_DETECTED = 0x38, | |
36807e67 | 288 | MFI_STAT_CONFIG_SEQ_MISMATCH = 0x67, |
c4a3e0a5 BS |
289 | |
290 | MFI_STAT_INVALID_STATUS = 0xFF | |
291 | }; | |
292 | ||
714f5177 | 293 | enum mfi_evt_class { |
294 | MFI_EVT_CLASS_DEBUG = -2, | |
295 | MFI_EVT_CLASS_PROGRESS = -1, | |
296 | MFI_EVT_CLASS_INFO = 0, | |
297 | MFI_EVT_CLASS_WARNING = 1, | |
298 | MFI_EVT_CLASS_CRITICAL = 2, | |
299 | MFI_EVT_CLASS_FATAL = 3, | |
300 | MFI_EVT_CLASS_DEAD = 4 | |
301 | }; | |
302 | ||
fc62b3fc SS |
303 | /* |
304 | * Crash dump related defines | |
305 | */ | |
306 | #define MAX_CRASH_DUMP_SIZE 512 | |
307 | #define CRASH_DMA_BUF_SIZE (1024 * 1024) | |
308 | ||
309 | enum MR_FW_CRASH_DUMP_STATE { | |
310 | UNAVAILABLE = 0, | |
311 | AVAILABLE = 1, | |
312 | COPYING = 2, | |
313 | COPIED = 3, | |
314 | COPY_ERROR = 4, | |
315 | }; | |
316 | ||
317 | enum _MR_CRASH_BUF_STATUS { | |
318 | MR_CRASH_BUF_TURN_OFF = 0, | |
319 | MR_CRASH_BUF_TURN_ON = 1, | |
320 | }; | |
321 | ||
c4a3e0a5 BS |
322 | /* |
323 | * Number of mailbox bytes in DCMD message frame | |
324 | */ | |
325 | #define MFI_MBOX_SIZE 12 | |
326 | ||
327 | enum MR_EVT_CLASS { | |
328 | ||
329 | MR_EVT_CLASS_DEBUG = -2, | |
330 | MR_EVT_CLASS_PROGRESS = -1, | |
331 | MR_EVT_CLASS_INFO = 0, | |
332 | MR_EVT_CLASS_WARNING = 1, | |
333 | MR_EVT_CLASS_CRITICAL = 2, | |
334 | MR_EVT_CLASS_FATAL = 3, | |
335 | MR_EVT_CLASS_DEAD = 4, | |
336 | ||
337 | }; | |
338 | ||
339 | enum MR_EVT_LOCALE { | |
340 | ||
341 | MR_EVT_LOCALE_LD = 0x0001, | |
342 | MR_EVT_LOCALE_PD = 0x0002, | |
343 | MR_EVT_LOCALE_ENCL = 0x0004, | |
344 | MR_EVT_LOCALE_BBU = 0x0008, | |
345 | MR_EVT_LOCALE_SAS = 0x0010, | |
346 | MR_EVT_LOCALE_CTRL = 0x0020, | |
347 | MR_EVT_LOCALE_CONFIG = 0x0040, | |
348 | MR_EVT_LOCALE_CLUSTER = 0x0080, | |
349 | MR_EVT_LOCALE_ALL = 0xffff, | |
350 | ||
351 | }; | |
352 | ||
353 | enum MR_EVT_ARGS { | |
354 | ||
355 | MR_EVT_ARGS_NONE, | |
356 | MR_EVT_ARGS_CDB_SENSE, | |
357 | MR_EVT_ARGS_LD, | |
358 | MR_EVT_ARGS_LD_COUNT, | |
359 | MR_EVT_ARGS_LD_LBA, | |
360 | MR_EVT_ARGS_LD_OWNER, | |
361 | MR_EVT_ARGS_LD_LBA_PD_LBA, | |
362 | MR_EVT_ARGS_LD_PROG, | |
363 | MR_EVT_ARGS_LD_STATE, | |
364 | MR_EVT_ARGS_LD_STRIP, | |
365 | MR_EVT_ARGS_PD, | |
366 | MR_EVT_ARGS_PD_ERR, | |
367 | MR_EVT_ARGS_PD_LBA, | |
368 | MR_EVT_ARGS_PD_LBA_LD, | |
369 | MR_EVT_ARGS_PD_PROG, | |
370 | MR_EVT_ARGS_PD_STATE, | |
371 | MR_EVT_ARGS_PCI, | |
372 | MR_EVT_ARGS_RATE, | |
373 | MR_EVT_ARGS_STR, | |
374 | MR_EVT_ARGS_TIME, | |
375 | MR_EVT_ARGS_ECC, | |
81e403ce YB |
376 | MR_EVT_ARGS_LD_PROP, |
377 | MR_EVT_ARGS_PD_SPARE, | |
378 | MR_EVT_ARGS_PD_INDEX, | |
379 | MR_EVT_ARGS_DIAG_PASS, | |
380 | MR_EVT_ARGS_DIAG_FAIL, | |
381 | MR_EVT_ARGS_PD_LBA_LBA, | |
382 | MR_EVT_ARGS_PORT_PHY, | |
383 | MR_EVT_ARGS_PD_MISSING, | |
384 | MR_EVT_ARGS_PD_ADDRESS, | |
385 | MR_EVT_ARGS_BITMAP, | |
386 | MR_EVT_ARGS_CONNECTOR, | |
387 | MR_EVT_ARGS_PD_PD, | |
388 | MR_EVT_ARGS_PD_FRU, | |
389 | MR_EVT_ARGS_PD_PATHINFO, | |
390 | MR_EVT_ARGS_PD_POWER_STATE, | |
391 | MR_EVT_ARGS_GENERIC, | |
392 | }; | |
c4a3e0a5 | 393 | |
357ae967 | 394 | |
395 | #define SGE_BUFFER_SIZE 4096 | |
8f67c8c5 | 396 | #define MEGASAS_CLUSTER_ID_SIZE 16 |
81e403ce YB |
397 | /* |
398 | * define constants for device list query options | |
399 | */ | |
400 | enum MR_PD_QUERY_TYPE { | |
401 | MR_PD_QUERY_TYPE_ALL = 0, | |
402 | MR_PD_QUERY_TYPE_STATE = 1, | |
403 | MR_PD_QUERY_TYPE_POWER_STATE = 2, | |
404 | MR_PD_QUERY_TYPE_MEDIA_TYPE = 3, | |
405 | MR_PD_QUERY_TYPE_SPEED = 4, | |
406 | MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5, | |
c4a3e0a5 BS |
407 | }; |
408 | ||
21c9e160 | 409 | enum MR_LD_QUERY_TYPE { |
410 | MR_LD_QUERY_TYPE_ALL = 0, | |
411 | MR_LD_QUERY_TYPE_EXPOSED_TO_HOST = 1, | |
412 | MR_LD_QUERY_TYPE_USED_TGT_IDS = 2, | |
413 | MR_LD_QUERY_TYPE_CLUSTER_ACCESS = 3, | |
414 | MR_LD_QUERY_TYPE_CLUSTER_LOCALE = 4, | |
415 | }; | |
416 | ||
417 | ||
7e8a75f4 YB |
418 | #define MR_EVT_CFG_CLEARED 0x0004 |
419 | #define MR_EVT_LD_STATE_CHANGE 0x0051 | |
420 | #define MR_EVT_PD_INSERTED 0x005b | |
421 | #define MR_EVT_PD_REMOVED 0x0070 | |
422 | #define MR_EVT_LD_CREATED 0x008a | |
423 | #define MR_EVT_LD_DELETED 0x008b | |
424 | #define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db | |
425 | #define MR_EVT_LD_OFFLINE 0x00fc | |
426 | #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152 | |
c4bd2654 | 427 | #define MR_EVT_CTRL_PROP_CHANGED 0x012f |
7e8a75f4 | 428 | |
81e403ce YB |
429 | enum MR_PD_STATE { |
430 | MR_PD_STATE_UNCONFIGURED_GOOD = 0x00, | |
431 | MR_PD_STATE_UNCONFIGURED_BAD = 0x01, | |
432 | MR_PD_STATE_HOT_SPARE = 0x02, | |
433 | MR_PD_STATE_OFFLINE = 0x10, | |
434 | MR_PD_STATE_FAILED = 0x11, | |
435 | MR_PD_STATE_REBUILD = 0x14, | |
436 | MR_PD_STATE_ONLINE = 0x18, | |
437 | MR_PD_STATE_COPYBACK = 0x20, | |
438 | MR_PD_STATE_SYSTEM = 0x40, | |
439 | }; | |
440 | ||
2216c305 SS |
441 | union MR_PD_REF { |
442 | struct { | |
443 | u16 deviceId; | |
444 | u16 seqNum; | |
445 | } mrPdRef; | |
446 | u32 ref; | |
447 | }; | |
448 | ||
449 | /* | |
450 | * define the DDF Type bit structure | |
451 | */ | |
452 | union MR_PD_DDF_TYPE { | |
453 | struct { | |
454 | union { | |
455 | struct { | |
456 | #ifndef __BIG_ENDIAN_BITFIELD | |
457 | u16 forcedPDGUID:1; | |
458 | u16 inVD:1; | |
459 | u16 isGlobalSpare:1; | |
460 | u16 isSpare:1; | |
461 | u16 isForeign:1; | |
462 | u16 reserved:7; | |
463 | u16 intf:4; | |
464 | #else | |
465 | u16 intf:4; | |
466 | u16 reserved:7; | |
467 | u16 isForeign:1; | |
468 | u16 isSpare:1; | |
469 | u16 isGlobalSpare:1; | |
470 | u16 inVD:1; | |
471 | u16 forcedPDGUID:1; | |
472 | #endif | |
473 | } pdType; | |
474 | u16 type; | |
475 | }; | |
476 | u16 reserved; | |
477 | } ddf; | |
478 | struct { | |
479 | u32 reserved; | |
480 | } nonDisk; | |
481 | u32 type; | |
482 | } __packed; | |
483 | ||
484 | /* | |
485 | * defines the progress structure | |
486 | */ | |
487 | union MR_PROGRESS { | |
488 | struct { | |
489 | u16 progress; | |
490 | union { | |
491 | u16 elapsedSecs; | |
492 | u16 elapsedSecsForLastPercent; | |
493 | }; | |
494 | } mrProgress; | |
495 | u32 w; | |
496 | } __packed; | |
497 | ||
498 | /* | |
499 | * defines the physical drive progress structure | |
500 | */ | |
501 | struct MR_PD_PROGRESS { | |
502 | struct { | |
503 | #ifndef MFI_BIG_ENDIAN | |
504 | u32 rbld:1; | |
505 | u32 patrol:1; | |
506 | u32 clear:1; | |
507 | u32 copyBack:1; | |
508 | u32 erase:1; | |
509 | u32 locate:1; | |
510 | u32 reserved:26; | |
511 | #else | |
512 | u32 reserved:26; | |
513 | u32 locate:1; | |
514 | u32 erase:1; | |
515 | u32 copyBack:1; | |
516 | u32 clear:1; | |
517 | u32 patrol:1; | |
518 | u32 rbld:1; | |
519 | #endif | |
520 | } active; | |
521 | union MR_PROGRESS rbld; | |
522 | union MR_PROGRESS patrol; | |
523 | union { | |
524 | union MR_PROGRESS clear; | |
525 | union MR_PROGRESS erase; | |
526 | }; | |
527 | ||
528 | struct { | |
529 | #ifndef MFI_BIG_ENDIAN | |
530 | u32 rbld:1; | |
531 | u32 patrol:1; | |
532 | u32 clear:1; | |
533 | u32 copyBack:1; | |
534 | u32 erase:1; | |
535 | u32 reserved:27; | |
536 | #else | |
537 | u32 reserved:27; | |
538 | u32 erase:1; | |
539 | u32 copyBack:1; | |
540 | u32 clear:1; | |
541 | u32 patrol:1; | |
542 | u32 rbld:1; | |
543 | #endif | |
544 | } pause; | |
545 | ||
546 | union MR_PROGRESS reserved[3]; | |
547 | } __packed; | |
548 | ||
549 | struct MR_PD_INFO { | |
550 | union MR_PD_REF ref; | |
551 | u8 inquiryData[96]; | |
552 | u8 vpdPage83[64]; | |
553 | u8 notSupported; | |
554 | u8 scsiDevType; | |
555 | ||
556 | union { | |
557 | u8 connectedPortBitmap; | |
558 | u8 connectedPortNumbers; | |
559 | }; | |
560 | ||
561 | u8 deviceSpeed; | |
562 | u32 mediaErrCount; | |
563 | u32 otherErrCount; | |
564 | u32 predFailCount; | |
565 | u32 lastPredFailEventSeqNum; | |
566 | ||
567 | u16 fwState; | |
568 | u8 disabledForRemoval; | |
569 | u8 linkSpeed; | |
570 | union MR_PD_DDF_TYPE state; | |
571 | ||
572 | struct { | |
573 | u8 count; | |
574 | #ifndef __BIG_ENDIAN_BITFIELD | |
575 | u8 isPathBroken:4; | |
576 | u8 reserved3:3; | |
577 | u8 widePortCapable:1; | |
578 | #else | |
579 | u8 widePortCapable:1; | |
580 | u8 reserved3:3; | |
581 | u8 isPathBroken:4; | |
582 | #endif | |
583 | ||
584 | u8 connectorIndex[2]; | |
585 | u8 reserved[4]; | |
586 | u64 sasAddr[2]; | |
587 | u8 reserved2[16]; | |
588 | } pathInfo; | |
589 | ||
590 | u64 rawSize; | |
591 | u64 nonCoercedSize; | |
592 | u64 coercedSize; | |
593 | u16 enclDeviceId; | |
594 | u8 enclIndex; | |
595 | ||
596 | union { | |
597 | u8 slotNumber; | |
598 | u8 enclConnectorIndex; | |
599 | }; | |
600 | ||
601 | struct MR_PD_PROGRESS progInfo; | |
602 | u8 badBlockTableFull; | |
603 | u8 unusableInCurrentConfig; | |
604 | u8 vpdPage83Ext[64]; | |
605 | u8 powerState; | |
606 | u8 enclPosition; | |
607 | u32 allowedOps; | |
608 | u16 copyBackPartnerId; | |
609 | u16 enclPartnerDeviceId; | |
610 | struct { | |
611 | #ifndef __BIG_ENDIAN_BITFIELD | |
612 | u16 fdeCapable:1; | |
613 | u16 fdeEnabled:1; | |
614 | u16 secured:1; | |
615 | u16 locked:1; | |
616 | u16 foreign:1; | |
617 | u16 needsEKM:1; | |
618 | u16 reserved:10; | |
619 | #else | |
620 | u16 reserved:10; | |
621 | u16 needsEKM:1; | |
622 | u16 foreign:1; | |
623 | u16 locked:1; | |
624 | u16 secured:1; | |
625 | u16 fdeEnabled:1; | |
626 | u16 fdeCapable:1; | |
627 | #endif | |
628 | } security; | |
629 | u8 mediaType; | |
630 | u8 notCertified; | |
631 | u8 bridgeVendor[8]; | |
632 | u8 bridgeProductIdentification[16]; | |
633 | u8 bridgeProductRevisionLevel[4]; | |
634 | u8 satBridgeExists; | |
635 | ||
636 | u8 interfaceType; | |
637 | u8 temperature; | |
638 | u8 emulatedBlockSize; | |
639 | u16 userDataBlockSize; | |
640 | u16 reserved2; | |
641 | ||
642 | struct { | |
643 | #ifndef __BIG_ENDIAN_BITFIELD | |
644 | u32 piType:3; | |
645 | u32 piFormatted:1; | |
646 | u32 piEligible:1; | |
647 | u32 NCQ:1; | |
648 | u32 WCE:1; | |
649 | u32 commissionedSpare:1; | |
650 | u32 emergencySpare:1; | |
651 | u32 ineligibleForSSCD:1; | |
652 | u32 ineligibleForLd:1; | |
653 | u32 useSSEraseType:1; | |
654 | u32 wceUnchanged:1; | |
655 | u32 supportScsiUnmap:1; | |
656 | u32 reserved:18; | |
657 | #else | |
658 | u32 reserved:18; | |
659 | u32 supportScsiUnmap:1; | |
660 | u32 wceUnchanged:1; | |
661 | u32 useSSEraseType:1; | |
662 | u32 ineligibleForLd:1; | |
663 | u32 ineligibleForSSCD:1; | |
664 | u32 emergencySpare:1; | |
665 | u32 commissionedSpare:1; | |
666 | u32 WCE:1; | |
667 | u32 NCQ:1; | |
668 | u32 piEligible:1; | |
669 | u32 piFormatted:1; | |
670 | u32 piType:3; | |
671 | #endif | |
672 | } properties; | |
673 | ||
674 | u64 shieldDiagCompletionTime; | |
675 | u8 shieldCounter; | |
676 | ||
677 | u8 linkSpeedOther; | |
678 | u8 reserved4[2]; | |
679 | ||
680 | struct { | |
681 | #ifndef __BIG_ENDIAN_BITFIELD | |
682 | u32 bbmErrCountSupported:1; | |
683 | u32 bbmErrCount:31; | |
684 | #else | |
685 | u32 bbmErrCount:31; | |
686 | u32 bbmErrCountSupported:1; | |
687 | #endif | |
688 | } bbmErr; | |
689 | ||
690 | u8 reserved1[512-428]; | |
691 | } __packed; | |
81e403ce YB |
692 | |
693 | /* | |
694 | * defines the physical drive address structure | |
695 | */ | |
696 | struct MR_PD_ADDRESS { | |
9ab9ed38 | 697 | __le16 deviceId; |
81e403ce YB |
698 | u16 enclDeviceId; |
699 | ||
700 | union { | |
701 | struct { | |
702 | u8 enclIndex; | |
703 | u8 slotNumber; | |
704 | } mrPdAddress; | |
705 | struct { | |
706 | u8 enclPosition; | |
707 | u8 enclConnectorIndex; | |
708 | } mrEnclAddress; | |
709 | }; | |
710 | u8 scsiDevType; | |
711 | union { | |
712 | u8 connectedPortBitmap; | |
713 | u8 connectedPortNumbers; | |
714 | }; | |
715 | u64 sasAddr[2]; | |
716 | } __packed; | |
717 | ||
718 | /* | |
719 | * defines the physical drive list structure | |
720 | */ | |
721 | struct MR_PD_LIST { | |
9ab9ed38 CH |
722 | __le32 size; |
723 | __le32 count; | |
81e403ce YB |
724 | struct MR_PD_ADDRESS addr[1]; |
725 | } __packed; | |
726 | ||
727 | struct megasas_pd_list { | |
728 | u16 tid; | |
729 | u8 driveType; | |
730 | u8 driveState; | |
2216c305 | 731 | u8 interface; |
81e403ce YB |
732 | } __packed; |
733 | ||
bdc6fb8d YB |
734 | /* |
735 | * defines the logical drive reference structure | |
736 | */ | |
737 | union MR_LD_REF { | |
738 | struct { | |
739 | u8 targetId; | |
740 | u8 reserved; | |
9ab9ed38 | 741 | __le16 seqNum; |
bdc6fb8d | 742 | }; |
9ab9ed38 | 743 | __le32 ref; |
bdc6fb8d YB |
744 | } __packed; |
745 | ||
746 | /* | |
747 | * defines the logical drive list structure | |
748 | */ | |
749 | struct MR_LD_LIST { | |
9ab9ed38 CH |
750 | __le32 ldCount; |
751 | __le32 reserved; | |
bdc6fb8d YB |
752 | struct { |
753 | union MR_LD_REF ref; | |
754 | u8 state; | |
755 | u8 reserved[3]; | |
9ab9ed38 | 756 | __le64 size; |
51087a86 | 757 | } ldList[MAX_LOGICAL_DRIVES_EXT]; |
bdc6fb8d YB |
758 | } __packed; |
759 | ||
21c9e160 | 760 | struct MR_LD_TARGETID_LIST { |
9ab9ed38 CH |
761 | __le32 size; |
762 | __le32 count; | |
21c9e160 | 763 | u8 pad[3]; |
51087a86 | 764 | u8 targetId[MAX_LOGICAL_DRIVES_EXT]; |
21c9e160 | 765 | }; |
766 | ||
767 | ||
c4a3e0a5 BS |
768 | /* |
769 | * SAS controller properties | |
770 | */ | |
771 | struct megasas_ctrl_prop { | |
772 | ||
773 | u16 seq_num; | |
774 | u16 pred_fail_poll_interval; | |
775 | u16 intr_throttle_count; | |
776 | u16 intr_throttle_timeouts; | |
777 | u8 rebuild_rate; | |
778 | u8 patrol_read_rate; | |
779 | u8 bgi_rate; | |
780 | u8 cc_rate; | |
781 | u8 recon_rate; | |
782 | u8 cache_flush_interval; | |
783 | u8 spinup_drv_count; | |
784 | u8 spinup_delay; | |
785 | u8 cluster_enable; | |
786 | u8 coercion_mode; | |
787 | u8 alarm_enable; | |
788 | u8 disable_auto_rebuild; | |
789 | u8 disable_battery_warn; | |
790 | u8 ecc_bucket_size; | |
791 | u16 ecc_bucket_leak_rate; | |
792 | u8 restore_hotspare_on_insertion; | |
793 | u8 expose_encl_devices; | |
39a98554 | 794 | u8 maintainPdFailHistory; |
795 | u8 disallowHostRequestReordering; | |
796 | u8 abortCCOnError; | |
797 | u8 loadBalanceMode; | |
798 | u8 disableAutoDetectBackplane; | |
799 | ||
800 | u8 snapVDSpace; | |
801 | ||
802 | /* | |
803 | * Add properties that can be controlled by | |
804 | * a bit in the following structure. | |
805 | */ | |
39a98554 | 806 | struct { |
94cd65dd SS |
807 | #if defined(__BIG_ENDIAN_BITFIELD) |
808 | u32 reserved:18; | |
809 | u32 enableJBOD:1; | |
810 | u32 disableSpinDownHS:1; | |
811 | u32 allowBootWithPinnedCache:1; | |
812 | u32 disableOnlineCtrlReset:1; | |
813 | u32 enableSecretKeyControl:1; | |
814 | u32 autoEnhancedImport:1; | |
815 | u32 enableSpinDownUnconfigured:1; | |
816 | u32 SSDPatrolReadEnabled:1; | |
817 | u32 SSDSMARTerEnabled:1; | |
818 | u32 disableNCQ:1; | |
819 | u32 useFdeOnly:1; | |
820 | u32 prCorrectUnconfiguredAreas:1; | |
821 | u32 SMARTerEnabled:1; | |
822 | u32 copyBackDisabled:1; | |
823 | #else | |
824 | u32 copyBackDisabled:1; | |
825 | u32 SMARTerEnabled:1; | |
826 | u32 prCorrectUnconfiguredAreas:1; | |
827 | u32 useFdeOnly:1; | |
828 | u32 disableNCQ:1; | |
829 | u32 SSDSMARTerEnabled:1; | |
830 | u32 SSDPatrolReadEnabled:1; | |
831 | u32 enableSpinDownUnconfigured:1; | |
832 | u32 autoEnhancedImport:1; | |
833 | u32 enableSecretKeyControl:1; | |
834 | u32 disableOnlineCtrlReset:1; | |
835 | u32 allowBootWithPinnedCache:1; | |
836 | u32 disableSpinDownHS:1; | |
837 | u32 enableJBOD:1; | |
838 | u32 reserved:18; | |
839 | #endif | |
39a98554 | 840 | } OnOffProperties; |
841 | u8 autoSnapVDSpace; | |
842 | u8 viewSpace; | |
9ab9ed38 | 843 | __le16 spinDownTime; |
39a98554 | 844 | u8 reserved[24]; |
81e403ce | 845 | } __packed; |
c4a3e0a5 BS |
846 | |
847 | /* | |
848 | * SAS controller information | |
849 | */ | |
850 | struct megasas_ctrl_info { | |
851 | ||
852 | /* | |
853 | * PCI device information | |
854 | */ | |
855 | struct { | |
856 | ||
9ab9ed38 CH |
857 | __le16 vendor_id; |
858 | __le16 device_id; | |
859 | __le16 sub_vendor_id; | |
860 | __le16 sub_device_id; | |
c4a3e0a5 BS |
861 | u8 reserved[24]; |
862 | ||
863 | } __attribute__ ((packed)) pci; | |
864 | ||
865 | /* | |
866 | * Host interface information | |
867 | */ | |
868 | struct { | |
869 | ||
870 | u8 PCIX:1; | |
871 | u8 PCIE:1; | |
872 | u8 iSCSI:1; | |
873 | u8 SAS_3G:1; | |
229fe47c | 874 | u8 SRIOV:1; |
875 | u8 reserved_0:3; | |
c4a3e0a5 BS |
876 | u8 reserved_1[6]; |
877 | u8 port_count; | |
878 | u64 port_addr[8]; | |
879 | ||
880 | } __attribute__ ((packed)) host_interface; | |
881 | ||
882 | /* | |
883 | * Device (backend) interface information | |
884 | */ | |
885 | struct { | |
886 | ||
887 | u8 SPI:1; | |
888 | u8 SAS_3G:1; | |
889 | u8 SATA_1_5G:1; | |
890 | u8 SATA_3G:1; | |
891 | u8 reserved_0:4; | |
892 | u8 reserved_1[6]; | |
893 | u8 port_count; | |
894 | u64 port_addr[8]; | |
895 | ||
896 | } __attribute__ ((packed)) device_interface; | |
897 | ||
898 | /* | |
899 | * List of components residing in flash. All str are null terminated | |
900 | */ | |
9ab9ed38 CH |
901 | __le32 image_check_word; |
902 | __le32 image_component_count; | |
c4a3e0a5 BS |
903 | |
904 | struct { | |
905 | ||
906 | char name[8]; | |
907 | char version[32]; | |
908 | char build_date[16]; | |
909 | char built_time[16]; | |
910 | ||
911 | } __attribute__ ((packed)) image_component[8]; | |
912 | ||
913 | /* | |
914 | * List of flash components that have been flashed on the card, but | |
915 | * are not in use, pending reset of the adapter. This list will be | |
916 | * empty if a flash operation has not occurred. All stings are null | |
917 | * terminated | |
918 | */ | |
9ab9ed38 | 919 | __le32 pending_image_component_count; |
c4a3e0a5 BS |
920 | |
921 | struct { | |
922 | ||
923 | char name[8]; | |
924 | char version[32]; | |
925 | char build_date[16]; | |
926 | char build_time[16]; | |
927 | ||
928 | } __attribute__ ((packed)) pending_image_component[8]; | |
929 | ||
930 | u8 max_arms; | |
931 | u8 max_spans; | |
932 | u8 max_arrays; | |
933 | u8 max_lds; | |
934 | ||
935 | char product_name[80]; | |
936 | char serial_no[32]; | |
937 | ||
938 | /* | |
939 | * Other physical/controller/operation information. Indicates the | |
940 | * presence of the hardware | |
941 | */ | |
942 | struct { | |
943 | ||
944 | u32 bbu:1; | |
945 | u32 alarm:1; | |
946 | u32 nvram:1; | |
947 | u32 uart:1; | |
948 | u32 reserved:28; | |
949 | ||
950 | } __attribute__ ((packed)) hw_present; | |
951 | ||
9ab9ed38 | 952 | __le32 current_fw_time; |
c4a3e0a5 BS |
953 | |
954 | /* | |
955 | * Maximum data transfer sizes | |
956 | */ | |
9ab9ed38 CH |
957 | __le16 max_concurrent_cmds; |
958 | __le16 max_sge_count; | |
959 | __le32 max_request_size; | |
c4a3e0a5 BS |
960 | |
961 | /* | |
962 | * Logical and physical device counts | |
963 | */ | |
9ab9ed38 CH |
964 | __le16 ld_present_count; |
965 | __le16 ld_degraded_count; | |
966 | __le16 ld_offline_count; | |
c4a3e0a5 | 967 | |
9ab9ed38 CH |
968 | __le16 pd_present_count; |
969 | __le16 pd_disk_present_count; | |
970 | __le16 pd_disk_pred_failure_count; | |
971 | __le16 pd_disk_failed_count; | |
c4a3e0a5 BS |
972 | |
973 | /* | |
974 | * Memory size information | |
975 | */ | |
9ab9ed38 CH |
976 | __le16 nvram_size; |
977 | __le16 memory_size; | |
978 | __le16 flash_size; | |
c4a3e0a5 BS |
979 | |
980 | /* | |
981 | * Error counters | |
982 | */ | |
9ab9ed38 CH |
983 | __le16 mem_correctable_error_count; |
984 | __le16 mem_uncorrectable_error_count; | |
c4a3e0a5 BS |
985 | |
986 | /* | |
987 | * Cluster information | |
988 | */ | |
989 | u8 cluster_permitted; | |
990 | u8 cluster_active; | |
991 | ||
992 | /* | |
993 | * Additional max data transfer sizes | |
994 | */ | |
9ab9ed38 | 995 | __le16 max_strips_per_io; |
c4a3e0a5 BS |
996 | |
997 | /* | |
998 | * Controller capabilities structures | |
999 | */ | |
1000 | struct { | |
1001 | ||
1002 | u32 raid_level_0:1; | |
1003 | u32 raid_level_1:1; | |
1004 | u32 raid_level_5:1; | |
1005 | u32 raid_level_1E:1; | |
1006 | u32 raid_level_6:1; | |
1007 | u32 reserved:27; | |
1008 | ||
1009 | } __attribute__ ((packed)) raid_levels; | |
1010 | ||
1011 | struct { | |
1012 | ||
1013 | u32 rbld_rate:1; | |
1014 | u32 cc_rate:1; | |
1015 | u32 bgi_rate:1; | |
1016 | u32 recon_rate:1; | |
1017 | u32 patrol_rate:1; | |
1018 | u32 alarm_control:1; | |
1019 | u32 cluster_supported:1; | |
1020 | u32 bbu:1; | |
1021 | u32 spanning_allowed:1; | |
1022 | u32 dedicated_hotspares:1; | |
1023 | u32 revertible_hotspares:1; | |
1024 | u32 foreign_config_import:1; | |
1025 | u32 self_diagnostic:1; | |
1026 | u32 mixed_redundancy_arr:1; | |
1027 | u32 global_hot_spares:1; | |
1028 | u32 reserved:17; | |
1029 | ||
1030 | } __attribute__ ((packed)) adapter_operations; | |
1031 | ||
1032 | struct { | |
1033 | ||
1034 | u32 read_policy:1; | |
1035 | u32 write_policy:1; | |
1036 | u32 io_policy:1; | |
1037 | u32 access_policy:1; | |
1038 | u32 disk_cache_policy:1; | |
1039 | u32 reserved:27; | |
1040 | ||
1041 | } __attribute__ ((packed)) ld_operations; | |
1042 | ||
1043 | struct { | |
1044 | ||
1045 | u8 min; | |
1046 | u8 max; | |
1047 | u8 reserved[2]; | |
1048 | ||
1049 | } __attribute__ ((packed)) stripe_sz_ops; | |
1050 | ||
1051 | struct { | |
1052 | ||
1053 | u32 force_online:1; | |
1054 | u32 force_offline:1; | |
1055 | u32 force_rebuild:1; | |
1056 | u32 reserved:29; | |
1057 | ||
1058 | } __attribute__ ((packed)) pd_operations; | |
1059 | ||
1060 | struct { | |
1061 | ||
1062 | u32 ctrl_supports_sas:1; | |
1063 | u32 ctrl_supports_sata:1; | |
1064 | u32 allow_mix_in_encl:1; | |
1065 | u32 allow_mix_in_ld:1; | |
1066 | u32 allow_sata_in_cluster:1; | |
1067 | u32 reserved:27; | |
1068 | ||
1069 | } __attribute__ ((packed)) pd_mix_support; | |
1070 | ||
1071 | /* | |
1072 | * Define ECC single-bit-error bucket information | |
1073 | */ | |
1074 | u8 ecc_bucket_count; | |
1075 | u8 reserved_2[11]; | |
1076 | ||
1077 | /* | |
1078 | * Include the controller properties (changeable items) | |
1079 | */ | |
1080 | struct megasas_ctrl_prop properties; | |
1081 | ||
1082 | /* | |
1083 | * Define FW pkg version (set in envt v'bles on OEM basis) | |
1084 | */ | |
1085 | char package_version[0x60]; | |
1086 | ||
c4a3e0a5 | 1087 | |
bc93d425 SS |
1088 | /* |
1089 | * If adapterOperations.supportMoreThan8Phys is set, | |
1090 | * and deviceInterface.portCount is greater than 8, | |
1091 | * SAS Addrs for first 8 ports shall be populated in | |
1092 | * deviceInterface.portAddr, and the rest shall be | |
1093 | * populated in deviceInterfacePortAddr2. | |
1094 | */ | |
9ab9ed38 | 1095 | __le64 deviceInterfacePortAddr2[8]; /*6a0h */ |
bc93d425 SS |
1096 | u8 reserved3[128]; /*6e0h */ |
1097 | ||
1098 | struct { /*760h */ | |
1099 | u16 minPdRaidLevel_0:4; | |
1100 | u16 maxPdRaidLevel_0:12; | |
1101 | ||
1102 | u16 minPdRaidLevel_1:4; | |
1103 | u16 maxPdRaidLevel_1:12; | |
1104 | ||
1105 | u16 minPdRaidLevel_5:4; | |
1106 | u16 maxPdRaidLevel_5:12; | |
1107 | ||
1108 | u16 minPdRaidLevel_1E:4; | |
1109 | u16 maxPdRaidLevel_1E:12; | |
1110 | ||
1111 | u16 minPdRaidLevel_6:4; | |
1112 | u16 maxPdRaidLevel_6:12; | |
1113 | ||
1114 | u16 minPdRaidLevel_10:4; | |
1115 | u16 maxPdRaidLevel_10:12; | |
1116 | ||
1117 | u16 minPdRaidLevel_50:4; | |
1118 | u16 maxPdRaidLevel_50:12; | |
1119 | ||
1120 | u16 minPdRaidLevel_60:4; | |
1121 | u16 maxPdRaidLevel_60:12; | |
1122 | ||
1123 | u16 minPdRaidLevel_1E_RLQ0:4; | |
1124 | u16 maxPdRaidLevel_1E_RLQ0:12; | |
1125 | ||
1126 | u16 minPdRaidLevel_1E0_RLQ0:4; | |
1127 | u16 maxPdRaidLevel_1E0_RLQ0:12; | |
1128 | ||
1129 | u16 reserved[6]; | |
1130 | } pdsForRaidLevels; | |
1131 | ||
9ab9ed38 CH |
1132 | __le16 maxPds; /*780h */ |
1133 | __le16 maxDedHSPs; /*782h */ | |
1134 | __le16 maxGlobalHSP; /*784h */ | |
1135 | __le16 ddfSize; /*786h */ | |
bc93d425 SS |
1136 | u8 maxLdsPerArray; /*788h */ |
1137 | u8 partitionsInDDF; /*789h */ | |
1138 | u8 lockKeyBinding; /*78ah */ | |
1139 | u8 maxPITsPerLd; /*78bh */ | |
1140 | u8 maxViewsPerLd; /*78ch */ | |
1141 | u8 maxTargetId; /*78dh */ | |
9ab9ed38 | 1142 | __le16 maxBvlVdSize; /*78eh */ |
bc93d425 | 1143 | |
9ab9ed38 CH |
1144 | __le16 maxConfigurableSSCSize; /*790h */ |
1145 | __le16 currentSSCsize; /*792h */ | |
bc93d425 SS |
1146 | |
1147 | char expanderFwVersion[12]; /*794h */ | |
1148 | ||
9ab9ed38 | 1149 | __le16 PFKTrialTimeRemaining; /*7A0h */ |
bc93d425 | 1150 | |
9ab9ed38 | 1151 | __le16 cacheMemorySize; /*7A2h */ |
bc93d425 SS |
1152 | |
1153 | struct { /*7A4h */ | |
94cd65dd | 1154 | #if defined(__BIG_ENDIAN_BITFIELD) |
229fe47c | 1155 | u32 reserved:5; |
1156 | u32 activePassive:2; | |
1157 | u32 supportConfigAutoBalance:1; | |
1158 | u32 mpio:1; | |
1159 | u32 supportDataLDonSSCArray:1; | |
1160 | u32 supportPointInTimeProgress:1; | |
94cd65dd SS |
1161 | u32 supportUnevenSpans:1; |
1162 | u32 dedicatedHotSparesLimited:1; | |
1163 | u32 headlessMode:1; | |
1164 | u32 supportEmulatedDrives:1; | |
1165 | u32 supportResetNow:1; | |
1166 | u32 realTimeScheduler:1; | |
1167 | u32 supportSSDPatrolRead:1; | |
1168 | u32 supportPerfTuning:1; | |
1169 | u32 disableOnlinePFKChange:1; | |
1170 | u32 supportJBOD:1; | |
1171 | u32 supportBootTimePFKChange:1; | |
1172 | u32 supportSetLinkSpeed:1; | |
1173 | u32 supportEmergencySpares:1; | |
1174 | u32 supportSuspendResumeBGops:1; | |
1175 | u32 blockSSDWriteCacheChange:1; | |
1176 | u32 supportShieldState:1; | |
1177 | u32 supportLdBBMInfo:1; | |
1178 | u32 supportLdPIType3:1; | |
1179 | u32 supportLdPIType2:1; | |
1180 | u32 supportLdPIType1:1; | |
1181 | u32 supportPIcontroller:1; | |
1182 | #else | |
bc93d425 SS |
1183 | u32 supportPIcontroller:1; |
1184 | u32 supportLdPIType1:1; | |
1185 | u32 supportLdPIType2:1; | |
1186 | u32 supportLdPIType3:1; | |
1187 | u32 supportLdBBMInfo:1; | |
1188 | u32 supportShieldState:1; | |
1189 | u32 blockSSDWriteCacheChange:1; | |
1190 | u32 supportSuspendResumeBGops:1; | |
1191 | u32 supportEmergencySpares:1; | |
1192 | u32 supportSetLinkSpeed:1; | |
1193 | u32 supportBootTimePFKChange:1; | |
1194 | u32 supportJBOD:1; | |
1195 | u32 disableOnlinePFKChange:1; | |
1196 | u32 supportPerfTuning:1; | |
1197 | u32 supportSSDPatrolRead:1; | |
1198 | u32 realTimeScheduler:1; | |
1199 | ||
1200 | u32 supportResetNow:1; | |
1201 | u32 supportEmulatedDrives:1; | |
1202 | u32 headlessMode:1; | |
1203 | u32 dedicatedHotSparesLimited:1; | |
1204 | ||
1205 | ||
1206 | u32 supportUnevenSpans:1; | |
229fe47c | 1207 | u32 supportPointInTimeProgress:1; |
1208 | u32 supportDataLDonSSCArray:1; | |
1209 | u32 mpio:1; | |
1210 | u32 supportConfigAutoBalance:1; | |
1211 | u32 activePassive:2; | |
1212 | u32 reserved:5; | |
94cd65dd | 1213 | #endif |
bc93d425 SS |
1214 | } adapterOperations2; |
1215 | ||
1216 | u8 driverVersion[32]; /*7A8h */ | |
1217 | u8 maxDAPdCountSpinup60; /*7C8h */ | |
1218 | u8 temperatureROC; /*7C9h */ | |
1219 | u8 temperatureCtrl; /*7CAh */ | |
1220 | u8 reserved4; /*7CBh */ | |
9ab9ed38 | 1221 | __le16 maxConfigurablePds; /*7CCh */ |
bc93d425 SS |
1222 | |
1223 | ||
1224 | u8 reserved5[2]; /*0x7CDh */ | |
1225 | ||
1226 | /* | |
1227 | * HA cluster information | |
1228 | */ | |
1229 | struct { | |
51087a86 | 1230 | #if defined(__BIG_ENDIAN_BITFIELD) |
8f67c8c5 SS |
1231 | u32 reserved:25; |
1232 | u32 passive:1; | |
51087a86 SS |
1233 | u32 premiumFeatureMismatch:1; |
1234 | u32 ctrlPropIncompatible:1; | |
1235 | u32 fwVersionMismatch:1; | |
1236 | u32 hwIncompatible:1; | |
1237 | u32 peerIsIncompatible:1; | |
1238 | u32 peerIsPresent:1; | |
1239 | #else | |
bc93d425 SS |
1240 | u32 peerIsPresent:1; |
1241 | u32 peerIsIncompatible:1; | |
1242 | u32 hwIncompatible:1; | |
1243 | u32 fwVersionMismatch:1; | |
1244 | u32 ctrlPropIncompatible:1; | |
1245 | u32 premiumFeatureMismatch:1; | |
8f67c8c5 SS |
1246 | u32 passive:1; |
1247 | u32 reserved:25; | |
51087a86 | 1248 | #endif |
bc93d425 SS |
1249 | } cluster; |
1250 | ||
8f67c8c5 | 1251 | char clusterId[MEGASAS_CLUSTER_ID_SIZE]; /*0x7D4 */ |
229fe47c | 1252 | struct { |
1253 | u8 maxVFsSupported; /*0x7E4*/ | |
1254 | u8 numVFsEnabled; /*0x7E5*/ | |
1255 | u8 requestorId; /*0x7E6 0:PF, 1:VF1, 2:VF2*/ | |
1256 | u8 reserved; /*0x7E7*/ | |
1257 | } iov; | |
bc93d425 | 1258 | |
fc62b3fc SS |
1259 | struct { |
1260 | #if defined(__BIG_ENDIAN_BITFIELD) | |
3761cb4c | 1261 | u32 reserved:7; |
1262 | u32 useSeqNumJbodFP:1; | |
0be3f4c9 | 1263 | u32 supportExtendedSSCSize:1; |
1264 | u32 supportDiskCacheSettingForSysPDs:1; | |
1265 | u32 supportCPLDUpdate:1; | |
1266 | u32 supportTTYLogCompression:1; | |
7497cde8 SS |
1267 | u32 discardCacheDuringLDDelete:1; |
1268 | u32 supportSecurityonJBOD:1; | |
1269 | u32 supportCacheBypassModes:1; | |
1270 | u32 supportDisableSESMonitoring:1; | |
1271 | u32 supportForceFlash:1; | |
1272 | u32 supportNVDRAM:1; | |
1273 | u32 supportDrvActivityLEDSetting:1; | |
1274 | u32 supportAllowedOpsforDrvRemoval:1; | |
1275 | u32 supportHOQRebuild:1; | |
1276 | u32 supportForceTo512e:1; | |
1277 | u32 supportNVCacheErase:1; | |
1278 | u32 supportDebugQueue:1; | |
1279 | u32 supportSwZone:1; | |
fc62b3fc | 1280 | u32 supportCrashDump:1; |
51087a86 SS |
1281 | u32 supportMaxExtLDs:1; |
1282 | u32 supportT10RebuildAssist:1; | |
1283 | u32 supportDisableImmediateIO:1; | |
1284 | u32 supportThermalPollInterval:1; | |
1285 | u32 supportPersonalityChange:2; | |
fc62b3fc | 1286 | #else |
51087a86 SS |
1287 | u32 supportPersonalityChange:2; |
1288 | u32 supportThermalPollInterval:1; | |
1289 | u32 supportDisableImmediateIO:1; | |
1290 | u32 supportT10RebuildAssist:1; | |
7497cde8 SS |
1291 | u32 supportMaxExtLDs:1; |
1292 | u32 supportCrashDump:1; | |
1293 | u32 supportSwZone:1; | |
1294 | u32 supportDebugQueue:1; | |
1295 | u32 supportNVCacheErase:1; | |
1296 | u32 supportForceTo512e:1; | |
1297 | u32 supportHOQRebuild:1; | |
1298 | u32 supportAllowedOpsforDrvRemoval:1; | |
1299 | u32 supportDrvActivityLEDSetting:1; | |
1300 | u32 supportNVDRAM:1; | |
1301 | u32 supportForceFlash:1; | |
1302 | u32 supportDisableSESMonitoring:1; | |
1303 | u32 supportCacheBypassModes:1; | |
1304 | u32 supportSecurityonJBOD:1; | |
1305 | u32 discardCacheDuringLDDelete:1; | |
0be3f4c9 | 1306 | u32 supportTTYLogCompression:1; |
1307 | u32 supportCPLDUpdate:1; | |
1308 | u32 supportDiskCacheSettingForSysPDs:1; | |
1309 | u32 supportExtendedSSCSize:1; | |
3761cb4c | 1310 | u32 useSeqNumJbodFP:1; |
1311 | u32 reserved:7; | |
fc62b3fc SS |
1312 | #endif |
1313 | } adapterOperations3; | |
1314 | ||
1315 | u8 pad[0x800-0x7EC]; | |
81e403ce | 1316 | } __packed; |
c4a3e0a5 BS |
1317 | |
1318 | /* | |
1319 | * =============================== | |
1320 | * MegaRAID SAS driver definitions | |
1321 | * =============================== | |
1322 | */ | |
1323 | #define MEGASAS_MAX_PD_CHANNELS 2 | |
51087a86 | 1324 | #define MEGASAS_MAX_LD_CHANNELS 2 |
c4a3e0a5 BS |
1325 | #define MEGASAS_MAX_CHANNELS (MEGASAS_MAX_PD_CHANNELS + \ |
1326 | MEGASAS_MAX_LD_CHANNELS) | |
1327 | #define MEGASAS_MAX_DEV_PER_CHANNEL 128 | |
1328 | #define MEGASAS_DEFAULT_INIT_ID -1 | |
1329 | #define MEGASAS_MAX_LUN 8 | |
6bf579a3 | 1330 | #define MEGASAS_DEFAULT_CMD_PER_LUN 256 |
81e403ce YB |
1331 | #define MEGASAS_MAX_PD (MEGASAS_MAX_PD_CHANNELS * \ |
1332 | MEGASAS_MAX_DEV_PER_CHANNEL) | |
bdc6fb8d YB |
1333 | #define MEGASAS_MAX_LD_IDS (MEGASAS_MAX_LD_CHANNELS * \ |
1334 | MEGASAS_MAX_DEV_PER_CHANNEL) | |
c4a3e0a5 | 1335 | |
1fd10685 | 1336 | #define MEGASAS_MAX_SECTORS (2*1024) |
42a8d2b3 | 1337 | #define MEGASAS_MAX_SECTORS_IEEE (2*128) |
658dcedb SP |
1338 | #define MEGASAS_DBG_LVL 1 |
1339 | ||
05e9ebbe SP |
1340 | #define MEGASAS_FW_BUSY 1 |
1341 | ||
51087a86 SS |
1342 | #define VD_EXT_DEBUG 0 |
1343 | ||
11c71cb4 SS |
1344 | #define SCAN_PD_CHANNEL 0x1 |
1345 | #define SCAN_VD_CHANNEL 0x2 | |
90dc9d98 | 1346 | |
c3e385a1 SS |
1347 | #define MEGASAS_KDUMP_QUEUE_DEPTH 100 |
1348 | ||
7497cde8 SS |
1349 | enum MR_SCSI_CMD_TYPE { |
1350 | READ_WRITE_LDIO = 0, | |
1351 | NON_READ_WRITE_LDIO = 1, | |
1352 | READ_WRITE_SYSPDIO = 2, | |
1353 | NON_READ_WRITE_SYSPDIO = 3, | |
1354 | }; | |
1355 | ||
6d40afbc SS |
1356 | enum DCMD_TIMEOUT_ACTION { |
1357 | INITIATE_OCR = 0, | |
1358 | KILL_ADAPTER = 1, | |
1359 | IGNORE_TIMEOUT = 2, | |
1360 | }; | |
308ec459 SS |
1361 | |
1362 | enum FW_BOOT_CONTEXT { | |
1363 | PROBE_CONTEXT = 0, | |
1364 | OCR_CONTEXT = 1, | |
1365 | }; | |
1366 | ||
d532dbe2 | 1367 | /* Frame Type */ |
1368 | #define IO_FRAME 0 | |
1369 | #define PTHRU_FRAME 1 | |
1370 | ||
c4a3e0a5 BS |
1371 | /* |
1372 | * When SCSI mid-layer calls driver's reset routine, driver waits for | |
1373 | * MEGASAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note | |
1374 | * that the driver cannot _actually_ abort or reset pending commands. While | |
1375 | * it is waiting for the commands to complete, it prints a diagnostic message | |
1376 | * every MEGASAS_RESET_NOTICE_INTERVAL seconds | |
1377 | */ | |
1378 | #define MEGASAS_RESET_WAIT_TIME 180 | |
2a3681e5 | 1379 | #define MEGASAS_INTERNAL_CMD_WAIT_TIME 180 |
c4a3e0a5 | 1380 | #define MEGASAS_RESET_NOTICE_INTERVAL 5 |
c4a3e0a5 | 1381 | #define MEGASAS_IOCTL_CMD 0 |
05e9ebbe | 1382 | #define MEGASAS_DEFAULT_CMD_TIMEOUT 90 |
c5daa6a9 | 1383 | #define MEGASAS_THROTTLE_QUEUE_DEPTH 16 |
90dc9d98 | 1384 | #define MEGASAS_BLOCKED_CMD_TIMEOUT 60 |
c4a3e0a5 BS |
1385 | /* |
1386 | * FW reports the maximum of number of commands that it can accept (maximum | |
1387 | * commands that can be outstanding) at any time. The driver must report a | |
1388 | * lower number to the mid layer because it can issue a few internal commands | |
1389 | * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs | |
1390 | * is shown below | |
1391 | */ | |
1392 | #define MEGASAS_INT_CMDS 32 | |
7bebf5c7 | 1393 | #define MEGASAS_SKINNY_INT_CMDS 5 |
ae09a6c1 SS |
1394 | #define MEGASAS_FUSION_INTERNAL_CMDS 5 |
1395 | #define MEGASAS_FUSION_IOCTL_CMDS 3 | |
f26ac3a1 | 1396 | #define MEGASAS_MFI_IOCTL_CMDS 27 |
c4a3e0a5 | 1397 | |
d46a3ad6 | 1398 | #define MEGASAS_MAX_MSIX_QUEUES 128 |
c4a3e0a5 BS |
1399 | /* |
1400 | * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit | |
1401 | * SGLs based on the size of dma_addr_t | |
1402 | */ | |
1403 | #define IS_DMA64 (sizeof(dma_addr_t) == 8) | |
1404 | ||
39a98554 | 1405 | #define MFI_XSCALE_OMR0_CHANGE_INTERRUPT 0x00000001 |
1406 | ||
1407 | #define MFI_INTR_FLAG_REPLY_MESSAGE 0x00000001 | |
1408 | #define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE 0x00000002 | |
1409 | #define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT 0x00000004 | |
1410 | ||
c4a3e0a5 | 1411 | #define MFI_OB_INTR_STATUS_MASK 0x00000002 |
14faea9f | 1412 | #define MFI_POLL_TIMEOUT_SECS 60 |
6d40afbc | 1413 | #define MFI_IO_TIMEOUT_SECS 180 |
229fe47c | 1414 | #define MEGASAS_SRIOV_HEARTBEAT_INTERVAL_VF (5 * HZ) |
1415 | #define MEGASAS_OCR_SETTLE_TIME_VF (1000 * 30) | |
1416 | #define MEGASAS_ROUTINE_WAIT_TIME_VF 300 | |
f9876f0b | 1417 | #define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000 |
6610a6b3 YB |
1418 | #define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001 |
1419 | #define MFI_GEN2_ENABLE_INTERRUPT_MASK (0x00000001 | 0x00000004) | |
87911122 YB |
1420 | #define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000 |
1421 | #define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001) | |
0e98936c | 1422 | |
39a98554 | 1423 | #define MFI_1068_PCSR_OFFSET 0x84 |
1424 | #define MFI_1068_FW_HANDSHAKE_OFFSET 0x64 | |
1425 | #define MFI_1068_FW_READY 0xDDDD0000 | |
d46a3ad6 SS |
1426 | |
1427 | #define MR_MAX_REPLY_QUEUES_OFFSET 0X0000001F | |
1428 | #define MR_MAX_REPLY_QUEUES_EXT_OFFSET 0X003FC000 | |
1429 | #define MR_MAX_REPLY_QUEUES_EXT_OFFSET_SHIFT 14 | |
1430 | #define MR_MAX_MSIX_REG_ARRAY 16 | |
179ac142 | 1431 | #define MR_RDPQ_MODE_OFFSET 0X00800000 |
0e98936c SP |
1432 | /* |
1433 | * register set for both 1068 and 1078 controllers | |
1434 | * structure extended for 1078 registers | |
1435 | */ | |
f9876f0b | 1436 | |
c4a3e0a5 | 1437 | struct megasas_register_set { |
9c915a8c | 1438 | u32 doorbell; /*0000h*/ |
1439 | u32 fusion_seq_offset; /*0004h*/ | |
1440 | u32 fusion_host_diag; /*0008h*/ | |
1441 | u32 reserved_01; /*000Ch*/ | |
c4a3e0a5 | 1442 | |
f9876f0b SP |
1443 | u32 inbound_msg_0; /*0010h*/ |
1444 | u32 inbound_msg_1; /*0014h*/ | |
1445 | u32 outbound_msg_0; /*0018h*/ | |
1446 | u32 outbound_msg_1; /*001Ch*/ | |
c4a3e0a5 | 1447 | |
f9876f0b SP |
1448 | u32 inbound_doorbell; /*0020h*/ |
1449 | u32 inbound_intr_status; /*0024h*/ | |
1450 | u32 inbound_intr_mask; /*0028h*/ | |
c4a3e0a5 | 1451 | |
f9876f0b SP |
1452 | u32 outbound_doorbell; /*002Ch*/ |
1453 | u32 outbound_intr_status; /*0030h*/ | |
1454 | u32 outbound_intr_mask; /*0034h*/ | |
c4a3e0a5 | 1455 | |
f9876f0b | 1456 | u32 reserved_1[2]; /*0038h*/ |
c4a3e0a5 | 1457 | |
f9876f0b SP |
1458 | u32 inbound_queue_port; /*0040h*/ |
1459 | u32 outbound_queue_port; /*0044h*/ | |
c4a3e0a5 | 1460 | |
9c915a8c | 1461 | u32 reserved_2[9]; /*0048h*/ |
1462 | u32 reply_post_host_index; /*006Ch*/ | |
1463 | u32 reserved_2_2[12]; /*0070h*/ | |
c4a3e0a5 | 1464 | |
f9876f0b | 1465 | u32 outbound_doorbell_clear; /*00A0h*/ |
c4a3e0a5 | 1466 | |
f9876f0b SP |
1467 | u32 reserved_3[3]; /*00A4h*/ |
1468 | ||
1469 | u32 outbound_scratch_pad ; /*00B0h*/ | |
9c915a8c | 1470 | u32 outbound_scratch_pad_2; /*00B4h*/ |
179ac142 | 1471 | u32 outbound_scratch_pad_3; /*00B8h*/ |
f9876f0b | 1472 | |
179ac142 | 1473 | u32 reserved_4; /*00BCh*/ |
f9876f0b SP |
1474 | |
1475 | u32 inbound_low_queue_port ; /*00C0h*/ | |
1476 | ||
1477 | u32 inbound_high_queue_port ; /*00C4h*/ | |
1478 | ||
1479 | u32 reserved_5; /*00C8h*/ | |
39a98554 | 1480 | u32 res_6[11]; /*CCh*/ |
1481 | u32 host_diag; | |
1482 | u32 seq_offset; | |
1483 | u32 index_registers[807]; /*00CCh*/ | |
c4a3e0a5 BS |
1484 | } __attribute__ ((packed)); |
1485 | ||
1486 | struct megasas_sge32 { | |
1487 | ||
9ab9ed38 CH |
1488 | __le32 phys_addr; |
1489 | __le32 length; | |
c4a3e0a5 BS |
1490 | |
1491 | } __attribute__ ((packed)); | |
1492 | ||
1493 | struct megasas_sge64 { | |
1494 | ||
9ab9ed38 CH |
1495 | __le64 phys_addr; |
1496 | __le32 length; | |
c4a3e0a5 BS |
1497 | |
1498 | } __attribute__ ((packed)); | |
1499 | ||
f4c9a131 | 1500 | struct megasas_sge_skinny { |
9ab9ed38 CH |
1501 | __le64 phys_addr; |
1502 | __le32 length; | |
1503 | __le32 flag; | |
f4c9a131 YB |
1504 | } __packed; |
1505 | ||
c4a3e0a5 BS |
1506 | union megasas_sgl { |
1507 | ||
1508 | struct megasas_sge32 sge32[1]; | |
1509 | struct megasas_sge64 sge64[1]; | |
f4c9a131 | 1510 | struct megasas_sge_skinny sge_skinny[1]; |
c4a3e0a5 BS |
1511 | |
1512 | } __attribute__ ((packed)); | |
1513 | ||
1514 | struct megasas_header { | |
1515 | ||
1516 | u8 cmd; /*00h */ | |
1517 | u8 sense_len; /*01h */ | |
1518 | u8 cmd_status; /*02h */ | |
1519 | u8 scsi_status; /*03h */ | |
1520 | ||
1521 | u8 target_id; /*04h */ | |
1522 | u8 lun; /*05h */ | |
1523 | u8 cdb_len; /*06h */ | |
1524 | u8 sge_count; /*07h */ | |
1525 | ||
9ab9ed38 CH |
1526 | __le32 context; /*08h */ |
1527 | __le32 pad_0; /*0Ch */ | |
c4a3e0a5 | 1528 | |
9ab9ed38 CH |
1529 | __le16 flags; /*10h */ |
1530 | __le16 timeout; /*12h */ | |
1531 | __le32 data_xferlen; /*14h */ | |
c4a3e0a5 BS |
1532 | |
1533 | } __attribute__ ((packed)); | |
1534 | ||
1535 | union megasas_sgl_frame { | |
1536 | ||
1537 | struct megasas_sge32 sge32[8]; | |
1538 | struct megasas_sge64 sge64[5]; | |
1539 | ||
1540 | } __attribute__ ((packed)); | |
1541 | ||
d46a3ad6 SS |
1542 | typedef union _MFI_CAPABILITIES { |
1543 | struct { | |
94cd65dd | 1544 | #if defined(__BIG_ENDIAN_BITFIELD) |
52b62ac7 SS |
1545 | u32 reserved:20; |
1546 | u32 support_qd_throttling:1; | |
8f05024c SS |
1547 | u32 support_fp_rlbypass:1; |
1548 | u32 support_vfid_in_ioframe:1; | |
bd5f9484 | 1549 | u32 support_ext_io_size:1; |
0be3f4c9 | 1550 | u32 support_ext_queue_depth:1; |
7497cde8 SS |
1551 | u32 security_protocol_cmds_fw:1; |
1552 | u32 support_core_affinity:1; | |
d2552ebe | 1553 | u32 support_ndrive_r1_lb:1; |
51087a86 | 1554 | u32 support_max_255lds:1; |
7497cde8 | 1555 | u32 support_fastpath_wb:1; |
94cd65dd SS |
1556 | u32 support_additional_msix:1; |
1557 | u32 support_fp_remote_lun:1; | |
1558 | #else | |
d46a3ad6 SS |
1559 | u32 support_fp_remote_lun:1; |
1560 | u32 support_additional_msix:1; | |
7497cde8 | 1561 | u32 support_fastpath_wb:1; |
51087a86 | 1562 | u32 support_max_255lds:1; |
d2552ebe | 1563 | u32 support_ndrive_r1_lb:1; |
7497cde8 SS |
1564 | u32 support_core_affinity:1; |
1565 | u32 security_protocol_cmds_fw:1; | |
0be3f4c9 | 1566 | u32 support_ext_queue_depth:1; |
bd5f9484 | 1567 | u32 support_ext_io_size:1; |
8f05024c SS |
1568 | u32 support_vfid_in_ioframe:1; |
1569 | u32 support_fp_rlbypass:1; | |
52b62ac7 SS |
1570 | u32 support_qd_throttling:1; |
1571 | u32 reserved:20; | |
94cd65dd | 1572 | #endif |
d46a3ad6 | 1573 | } mfi_capabilities; |
9ab9ed38 | 1574 | __le32 reg; |
d46a3ad6 SS |
1575 | } MFI_CAPABILITIES; |
1576 | ||
c4a3e0a5 BS |
1577 | struct megasas_init_frame { |
1578 | ||
1579 | u8 cmd; /*00h */ | |
1580 | u8 reserved_0; /*01h */ | |
1581 | u8 cmd_status; /*02h */ | |
1582 | ||
1583 | u8 reserved_1; /*03h */ | |
d46a3ad6 | 1584 | MFI_CAPABILITIES driver_operations; /*04h*/ |
c4a3e0a5 | 1585 | |
9ab9ed38 CH |
1586 | __le32 context; /*08h */ |
1587 | __le32 pad_0; /*0Ch */ | |
c4a3e0a5 | 1588 | |
9ab9ed38 CH |
1589 | __le16 flags; /*10h */ |
1590 | __le16 reserved_3; /*12h */ | |
1591 | __le32 data_xfer_len; /*14h */ | |
c4a3e0a5 | 1592 | |
9ab9ed38 CH |
1593 | __le32 queue_info_new_phys_addr_lo; /*18h */ |
1594 | __le32 queue_info_new_phys_addr_hi; /*1Ch */ | |
1595 | __le32 queue_info_old_phys_addr_lo; /*20h */ | |
1596 | __le32 queue_info_old_phys_addr_hi; /*24h */ | |
1597 | __le32 reserved_4[2]; /*28h */ | |
1598 | __le32 system_info_lo; /*30h */ | |
1599 | __le32 system_info_hi; /*34h */ | |
1600 | __le32 reserved_5[2]; /*38h */ | |
c4a3e0a5 BS |
1601 | |
1602 | } __attribute__ ((packed)); | |
1603 | ||
1604 | struct megasas_init_queue_info { | |
1605 | ||
9ab9ed38 CH |
1606 | __le32 init_flags; /*00h */ |
1607 | __le32 reply_queue_entries; /*04h */ | |
c4a3e0a5 | 1608 | |
9ab9ed38 CH |
1609 | __le32 reply_queue_start_phys_addr_lo; /*08h */ |
1610 | __le32 reply_queue_start_phys_addr_hi; /*0Ch */ | |
1611 | __le32 producer_index_phys_addr_lo; /*10h */ | |
1612 | __le32 producer_index_phys_addr_hi; /*14h */ | |
1613 | __le32 consumer_index_phys_addr_lo; /*18h */ | |
1614 | __le32 consumer_index_phys_addr_hi; /*1Ch */ | |
c4a3e0a5 BS |
1615 | |
1616 | } __attribute__ ((packed)); | |
1617 | ||
1618 | struct megasas_io_frame { | |
1619 | ||
1620 | u8 cmd; /*00h */ | |
1621 | u8 sense_len; /*01h */ | |
1622 | u8 cmd_status; /*02h */ | |
1623 | u8 scsi_status; /*03h */ | |
1624 | ||
1625 | u8 target_id; /*04h */ | |
1626 | u8 access_byte; /*05h */ | |
1627 | u8 reserved_0; /*06h */ | |
1628 | u8 sge_count; /*07h */ | |
1629 | ||
9ab9ed38 CH |
1630 | __le32 context; /*08h */ |
1631 | __le32 pad_0; /*0Ch */ | |
c4a3e0a5 | 1632 | |
9ab9ed38 CH |
1633 | __le16 flags; /*10h */ |
1634 | __le16 timeout; /*12h */ | |
1635 | __le32 lba_count; /*14h */ | |
c4a3e0a5 | 1636 | |
9ab9ed38 CH |
1637 | __le32 sense_buf_phys_addr_lo; /*18h */ |
1638 | __le32 sense_buf_phys_addr_hi; /*1Ch */ | |
c4a3e0a5 | 1639 | |
9ab9ed38 CH |
1640 | __le32 start_lba_lo; /*20h */ |
1641 | __le32 start_lba_hi; /*24h */ | |
c4a3e0a5 BS |
1642 | |
1643 | union megasas_sgl sgl; /*28h */ | |
1644 | ||
1645 | } __attribute__ ((packed)); | |
1646 | ||
1647 | struct megasas_pthru_frame { | |
1648 | ||
1649 | u8 cmd; /*00h */ | |
1650 | u8 sense_len; /*01h */ | |
1651 | u8 cmd_status; /*02h */ | |
1652 | u8 scsi_status; /*03h */ | |
1653 | ||
1654 | u8 target_id; /*04h */ | |
1655 | u8 lun; /*05h */ | |
1656 | u8 cdb_len; /*06h */ | |
1657 | u8 sge_count; /*07h */ | |
1658 | ||
9ab9ed38 CH |
1659 | __le32 context; /*08h */ |
1660 | __le32 pad_0; /*0Ch */ | |
c4a3e0a5 | 1661 | |
9ab9ed38 CH |
1662 | __le16 flags; /*10h */ |
1663 | __le16 timeout; /*12h */ | |
1664 | __le32 data_xfer_len; /*14h */ | |
c4a3e0a5 | 1665 | |
9ab9ed38 CH |
1666 | __le32 sense_buf_phys_addr_lo; /*18h */ |
1667 | __le32 sense_buf_phys_addr_hi; /*1Ch */ | |
c4a3e0a5 BS |
1668 | |
1669 | u8 cdb[16]; /*20h */ | |
1670 | union megasas_sgl sgl; /*30h */ | |
1671 | ||
1672 | } __attribute__ ((packed)); | |
1673 | ||
1674 | struct megasas_dcmd_frame { | |
1675 | ||
1676 | u8 cmd; /*00h */ | |
1677 | u8 reserved_0; /*01h */ | |
1678 | u8 cmd_status; /*02h */ | |
1679 | u8 reserved_1[4]; /*03h */ | |
1680 | u8 sge_count; /*07h */ | |
1681 | ||
9ab9ed38 CH |
1682 | __le32 context; /*08h */ |
1683 | __le32 pad_0; /*0Ch */ | |
c4a3e0a5 | 1684 | |
9ab9ed38 CH |
1685 | __le16 flags; /*10h */ |
1686 | __le16 timeout; /*12h */ | |
c4a3e0a5 | 1687 | |
9ab9ed38 CH |
1688 | __le32 data_xfer_len; /*14h */ |
1689 | __le32 opcode; /*18h */ | |
c4a3e0a5 BS |
1690 | |
1691 | union { /*1Ch */ | |
1692 | u8 b[12]; | |
9ab9ed38 CH |
1693 | __le16 s[6]; |
1694 | __le32 w[3]; | |
c4a3e0a5 BS |
1695 | } mbox; |
1696 | ||
1697 | union megasas_sgl sgl; /*28h */ | |
1698 | ||
1699 | } __attribute__ ((packed)); | |
1700 | ||
1701 | struct megasas_abort_frame { | |
1702 | ||
1703 | u8 cmd; /*00h */ | |
1704 | u8 reserved_0; /*01h */ | |
1705 | u8 cmd_status; /*02h */ | |
1706 | ||
1707 | u8 reserved_1; /*03h */ | |
9ab9ed38 | 1708 | __le32 reserved_2; /*04h */ |
c4a3e0a5 | 1709 | |
9ab9ed38 CH |
1710 | __le32 context; /*08h */ |
1711 | __le32 pad_0; /*0Ch */ | |
c4a3e0a5 | 1712 | |
9ab9ed38 CH |
1713 | __le16 flags; /*10h */ |
1714 | __le16 reserved_3; /*12h */ | |
1715 | __le32 reserved_4; /*14h */ | |
c4a3e0a5 | 1716 | |
9ab9ed38 CH |
1717 | __le32 abort_context; /*18h */ |
1718 | __le32 pad_1; /*1Ch */ | |
c4a3e0a5 | 1719 | |
9ab9ed38 CH |
1720 | __le32 abort_mfi_phys_addr_lo; /*20h */ |
1721 | __le32 abort_mfi_phys_addr_hi; /*24h */ | |
c4a3e0a5 | 1722 | |
9ab9ed38 | 1723 | __le32 reserved_5[6]; /*28h */ |
c4a3e0a5 BS |
1724 | |
1725 | } __attribute__ ((packed)); | |
1726 | ||
1727 | struct megasas_smp_frame { | |
1728 | ||
1729 | u8 cmd; /*00h */ | |
1730 | u8 reserved_1; /*01h */ | |
1731 | u8 cmd_status; /*02h */ | |
1732 | u8 connection_status; /*03h */ | |
1733 | ||
1734 | u8 reserved_2[3]; /*04h */ | |
1735 | u8 sge_count; /*07h */ | |
1736 | ||
9ab9ed38 CH |
1737 | __le32 context; /*08h */ |
1738 | __le32 pad_0; /*0Ch */ | |
c4a3e0a5 | 1739 | |
9ab9ed38 CH |
1740 | __le16 flags; /*10h */ |
1741 | __le16 timeout; /*12h */ | |
c4a3e0a5 | 1742 | |
9ab9ed38 CH |
1743 | __le32 data_xfer_len; /*14h */ |
1744 | __le64 sas_addr; /*18h */ | |
c4a3e0a5 BS |
1745 | |
1746 | union { | |
1747 | struct megasas_sge32 sge32[2]; /* [0]: resp [1]: req */ | |
1748 | struct megasas_sge64 sge64[2]; /* [0]: resp [1]: req */ | |
1749 | } sgl; | |
1750 | ||
1751 | } __attribute__ ((packed)); | |
1752 | ||
1753 | struct megasas_stp_frame { | |
1754 | ||
1755 | u8 cmd; /*00h */ | |
1756 | u8 reserved_1; /*01h */ | |
1757 | u8 cmd_status; /*02h */ | |
1758 | u8 reserved_2; /*03h */ | |
1759 | ||
1760 | u8 target_id; /*04h */ | |
1761 | u8 reserved_3[2]; /*05h */ | |
1762 | u8 sge_count; /*07h */ | |
1763 | ||
9ab9ed38 CH |
1764 | __le32 context; /*08h */ |
1765 | __le32 pad_0; /*0Ch */ | |
c4a3e0a5 | 1766 | |
9ab9ed38 CH |
1767 | __le16 flags; /*10h */ |
1768 | __le16 timeout; /*12h */ | |
c4a3e0a5 | 1769 | |
9ab9ed38 | 1770 | __le32 data_xfer_len; /*14h */ |
c4a3e0a5 | 1771 | |
9ab9ed38 CH |
1772 | __le16 fis[10]; /*18h */ |
1773 | __le32 stp_flags; | |
c4a3e0a5 BS |
1774 | |
1775 | union { | |
1776 | struct megasas_sge32 sge32[2]; /* [0]: resp [1]: data */ | |
1777 | struct megasas_sge64 sge64[2]; /* [0]: resp [1]: data */ | |
1778 | } sgl; | |
1779 | ||
1780 | } __attribute__ ((packed)); | |
1781 | ||
1782 | union megasas_frame { | |
1783 | ||
1784 | struct megasas_header hdr; | |
1785 | struct megasas_init_frame init; | |
1786 | struct megasas_io_frame io; | |
1787 | struct megasas_pthru_frame pthru; | |
1788 | struct megasas_dcmd_frame dcmd; | |
1789 | struct megasas_abort_frame abort; | |
1790 | struct megasas_smp_frame smp; | |
1791 | struct megasas_stp_frame stp; | |
1792 | ||
1793 | u8 raw_bytes[64]; | |
1794 | }; | |
1795 | ||
18365b13 SS |
1796 | /** |
1797 | * struct MR_PRIV_DEVICE - sdev private hostdata | |
1798 | * @is_tm_capable: firmware managed tm_capable flag | |
1799 | * @tm_busy: TM request is in progress | |
1800 | */ | |
1801 | struct MR_PRIV_DEVICE { | |
1802 | bool is_tm_capable; | |
1803 | bool tm_busy; | |
1804 | }; | |
c4a3e0a5 BS |
1805 | struct megasas_cmd; |
1806 | ||
1807 | union megasas_evt_class_locale { | |
1808 | ||
1809 | struct { | |
be26374b | 1810 | #ifndef __BIG_ENDIAN_BITFIELD |
c4a3e0a5 BS |
1811 | u16 locale; |
1812 | u8 reserved; | |
1813 | s8 class; | |
be26374b SS |
1814 | #else |
1815 | s8 class; | |
1816 | u8 reserved; | |
1817 | u16 locale; | |
1818 | #endif | |
c4a3e0a5 BS |
1819 | } __attribute__ ((packed)) members; |
1820 | ||
1821 | u32 word; | |
1822 | ||
1823 | } __attribute__ ((packed)); | |
1824 | ||
1825 | struct megasas_evt_log_info { | |
9ab9ed38 CH |
1826 | __le32 newest_seq_num; |
1827 | __le32 oldest_seq_num; | |
1828 | __le32 clear_seq_num; | |
1829 | __le32 shutdown_seq_num; | |
1830 | __le32 boot_seq_num; | |
c4a3e0a5 BS |
1831 | |
1832 | } __attribute__ ((packed)); | |
1833 | ||
1834 | struct megasas_progress { | |
1835 | ||
9ab9ed38 CH |
1836 | __le16 progress; |
1837 | __le16 elapsed_seconds; | |
c4a3e0a5 BS |
1838 | |
1839 | } __attribute__ ((packed)); | |
1840 | ||
1841 | struct megasas_evtarg_ld { | |
1842 | ||
1843 | u16 target_id; | |
1844 | u8 ld_index; | |
1845 | u8 reserved; | |
1846 | ||
1847 | } __attribute__ ((packed)); | |
1848 | ||
1849 | struct megasas_evtarg_pd { | |
1850 | u16 device_id; | |
1851 | u8 encl_index; | |
1852 | u8 slot_number; | |
1853 | ||
1854 | } __attribute__ ((packed)); | |
1855 | ||
1856 | struct megasas_evt_detail { | |
1857 | ||
9ab9ed38 CH |
1858 | __le32 seq_num; |
1859 | __le32 time_stamp; | |
1860 | __le32 code; | |
c4a3e0a5 BS |
1861 | union megasas_evt_class_locale cl; |
1862 | u8 arg_type; | |
1863 | u8 reserved1[15]; | |
1864 | ||
1865 | union { | |
1866 | struct { | |
1867 | struct megasas_evtarg_pd pd; | |
1868 | u8 cdb_length; | |
1869 | u8 sense_length; | |
1870 | u8 reserved[2]; | |
1871 | u8 cdb[16]; | |
1872 | u8 sense[64]; | |
1873 | } __attribute__ ((packed)) cdbSense; | |
1874 | ||
1875 | struct megasas_evtarg_ld ld; | |
1876 | ||
1877 | struct { | |
1878 | struct megasas_evtarg_ld ld; | |
9ab9ed38 | 1879 | __le64 count; |
c4a3e0a5 BS |
1880 | } __attribute__ ((packed)) ld_count; |
1881 | ||
1882 | struct { | |
9ab9ed38 | 1883 | __le64 lba; |
c4a3e0a5 BS |
1884 | struct megasas_evtarg_ld ld; |
1885 | } __attribute__ ((packed)) ld_lba; | |
1886 | ||
1887 | struct { | |
1888 | struct megasas_evtarg_ld ld; | |
9ab9ed38 CH |
1889 | __le32 prevOwner; |
1890 | __le32 newOwner; | |
c4a3e0a5 BS |
1891 | } __attribute__ ((packed)) ld_owner; |
1892 | ||
1893 | struct { | |
1894 | u64 ld_lba; | |
1895 | u64 pd_lba; | |
1896 | struct megasas_evtarg_ld ld; | |
1897 | struct megasas_evtarg_pd pd; | |
1898 | } __attribute__ ((packed)) ld_lba_pd_lba; | |
1899 | ||
1900 | struct { | |
1901 | struct megasas_evtarg_ld ld; | |
1902 | struct megasas_progress prog; | |
1903 | } __attribute__ ((packed)) ld_prog; | |
1904 | ||
1905 | struct { | |
1906 | struct megasas_evtarg_ld ld; | |
1907 | u32 prev_state; | |
1908 | u32 new_state; | |
1909 | } __attribute__ ((packed)) ld_state; | |
1910 | ||
1911 | struct { | |
1912 | u64 strip; | |
1913 | struct megasas_evtarg_ld ld; | |
1914 | } __attribute__ ((packed)) ld_strip; | |
1915 | ||
1916 | struct megasas_evtarg_pd pd; | |
1917 | ||
1918 | struct { | |
1919 | struct megasas_evtarg_pd pd; | |
1920 | u32 err; | |
1921 | } __attribute__ ((packed)) pd_err; | |
1922 | ||
1923 | struct { | |
1924 | u64 lba; | |
1925 | struct megasas_evtarg_pd pd; | |
1926 | } __attribute__ ((packed)) pd_lba; | |
1927 | ||
1928 | struct { | |
1929 | u64 lba; | |
1930 | struct megasas_evtarg_pd pd; | |
1931 | struct megasas_evtarg_ld ld; | |
1932 | } __attribute__ ((packed)) pd_lba_ld; | |
1933 | ||
1934 | struct { | |
1935 | struct megasas_evtarg_pd pd; | |
1936 | struct megasas_progress prog; | |
1937 | } __attribute__ ((packed)) pd_prog; | |
1938 | ||
1939 | struct { | |
1940 | struct megasas_evtarg_pd pd; | |
1941 | u32 prevState; | |
1942 | u32 newState; | |
1943 | } __attribute__ ((packed)) pd_state; | |
1944 | ||
1945 | struct { | |
1946 | u16 vendorId; | |
9ab9ed38 | 1947 | __le16 deviceId; |
c4a3e0a5 BS |
1948 | u16 subVendorId; |
1949 | u16 subDeviceId; | |
1950 | } __attribute__ ((packed)) pci; | |
1951 | ||
1952 | u32 rate; | |
1953 | char str[96]; | |
1954 | ||
1955 | struct { | |
1956 | u32 rtc; | |
1957 | u32 elapsedSeconds; | |
1958 | } __attribute__ ((packed)) time; | |
1959 | ||
1960 | struct { | |
1961 | u32 ecar; | |
1962 | u32 elog; | |
1963 | char str[64]; | |
1964 | } __attribute__ ((packed)) ecc; | |
1965 | ||
1966 | u8 b[96]; | |
9ab9ed38 CH |
1967 | __le16 s[48]; |
1968 | __le32 w[24]; | |
1969 | __le64 d[12]; | |
c4a3e0a5 BS |
1970 | } args; |
1971 | ||
1972 | char description[128]; | |
1973 | ||
1974 | } __attribute__ ((packed)); | |
1975 | ||
7e8a75f4 | 1976 | struct megasas_aen_event { |
c1d390d8 | 1977 | struct delayed_work hotplug_work; |
7e8a75f4 YB |
1978 | struct megasas_instance *instance; |
1979 | }; | |
1980 | ||
c8e858fe | 1981 | struct megasas_irq_context { |
1982 | struct megasas_instance *instance; | |
1983 | u32 MSIxIndex; | |
1984 | }; | |
1985 | ||
5765c5b8 SS |
1986 | struct MR_DRV_SYSTEM_INFO { |
1987 | u8 infoVersion; | |
1988 | u8 systemIdLength; | |
1989 | u16 reserved0; | |
1990 | u8 systemId[64]; | |
1991 | u8 reserved[1980]; | |
1992 | }; | |
1993 | ||
2216c305 SS |
1994 | enum MR_PD_TYPE { |
1995 | UNKNOWN_DRIVE = 0, | |
1996 | PARALLEL_SCSI = 1, | |
1997 | SAS_PD = 2, | |
1998 | SATA_PD = 3, | |
1999 | FC_PD = 4, | |
2000 | }; | |
2001 | ||
2002 | /* JBOD Queue depth definitions */ | |
2003 | #define MEGASAS_SATA_QD 32 | |
2004 | #define MEGASAS_SAS_QD 64 | |
2005 | #define MEGASAS_DEFAULT_PD_QD 64 | |
2006 | ||
c4a3e0a5 BS |
2007 | struct megasas_instance { |
2008 | ||
9ab9ed38 | 2009 | __le32 *producer; |
c4a3e0a5 | 2010 | dma_addr_t producer_h; |
9ab9ed38 | 2011 | __le32 *consumer; |
c4a3e0a5 | 2012 | dma_addr_t consumer_h; |
5765c5b8 SS |
2013 | struct MR_DRV_SYSTEM_INFO *system_info_buf; |
2014 | dma_addr_t system_info_h; | |
229fe47c | 2015 | struct MR_LD_VF_AFFILIATION *vf_affiliation; |
2016 | dma_addr_t vf_affiliation_h; | |
2017 | struct MR_LD_VF_AFFILIATION_111 *vf_affiliation_111; | |
2018 | dma_addr_t vf_affiliation_111_h; | |
2019 | struct MR_CTRL_HB_HOST_MEM *hb_host_mem; | |
2020 | dma_addr_t hb_host_mem_h; | |
2216c305 SS |
2021 | struct MR_PD_INFO *pd_info; |
2022 | dma_addr_t pd_info_h; | |
c4a3e0a5 | 2023 | |
9ab9ed38 | 2024 | __le32 *reply_queue; |
c4a3e0a5 BS |
2025 | dma_addr_t reply_queue_h; |
2026 | ||
fc62b3fc SS |
2027 | u32 *crash_dump_buf; |
2028 | dma_addr_t crash_dump_h; | |
2029 | void *crash_buf[MAX_CRASH_DUMP_SIZE]; | |
2030 | u32 crash_buf_pages; | |
2031 | unsigned int fw_crash_buffer_size; | |
2032 | unsigned int fw_crash_state; | |
2033 | unsigned int fw_crash_buffer_offset; | |
2034 | u32 drv_buf_index; | |
2035 | u32 drv_buf_alloc; | |
2036 | u32 crash_dump_fw_support; | |
2037 | u32 crash_dump_drv_support; | |
2038 | u32 crash_dump_app_support; | |
7497cde8 | 2039 | u32 secure_jbod_support; |
3761cb4c | 2040 | bool use_seqnum_jbod_fp; /* Added for PD sequence */ |
fc62b3fc SS |
2041 | spinlock_t crashdump_lock; |
2042 | ||
c4a3e0a5 | 2043 | struct megasas_register_set __iomem *reg_set; |
8a232bb3 | 2044 | u32 __iomem *reply_post_host_index_addr[MR_MAX_MSIX_REG_ARRAY]; |
81e403ce | 2045 | struct megasas_pd_list pd_list[MEGASAS_MAX_PD]; |
999ece0a | 2046 | struct megasas_pd_list local_pd_list[MEGASAS_MAX_PD]; |
7497cde8 | 2047 | u8 ld_ids[MEGASAS_MAX_LD_IDS]; |
c4a3e0a5 | 2048 | s8 init_id; |
c4a3e0a5 BS |
2049 | |
2050 | u16 max_num_sge; | |
2051 | u16 max_fw_cmds; | |
9c915a8c | 2052 | u16 max_mfi_cmds; |
ae09a6c1 | 2053 | u16 max_scsi_cmds; |
308ec459 SS |
2054 | u16 ldio_threshold; |
2055 | u16 cur_can_queue; | |
c4a3e0a5 | 2056 | u32 max_sectors_per_req; |
7e8a75f4 | 2057 | struct megasas_aen_event *ev; |
c4a3e0a5 BS |
2058 | |
2059 | struct megasas_cmd **cmd_list; | |
2060 | struct list_head cmd_pool; | |
39a98554 | 2061 | /* used to sync fire the cmd to fw */ |
90dc9d98 | 2062 | spinlock_t mfi_pool_lock; |
39a98554 | 2063 | /* used to sync fire the cmd to fw */ |
2064 | spinlock_t hba_lock; | |
7343eb65 | 2065 | /* used to synch producer, consumer ptrs in dpc */ |
2066 | spinlock_t completion_lock; | |
c4a3e0a5 BS |
2067 | struct dma_pool *frame_dma_pool; |
2068 | struct dma_pool *sense_dma_pool; | |
2069 | ||
2070 | struct megasas_evt_detail *evt_detail; | |
2071 | dma_addr_t evt_detail_h; | |
2072 | struct megasas_cmd *aen_cmd; | |
2216c305 | 2073 | struct mutex hba_mutex; |
c4a3e0a5 BS |
2074 | struct semaphore ioctl_sem; |
2075 | ||
2076 | struct Scsi_Host *host; | |
2077 | ||
2078 | wait_queue_head_t int_cmd_wait_q; | |
2079 | wait_queue_head_t abort_cmd_wait_q; | |
2080 | ||
2081 | struct pci_dev *pdev; | |
2082 | u32 unique_id; | |
39a98554 | 2083 | u32 fw_support_ieee; |
c4a3e0a5 | 2084 | |
e4a082c7 | 2085 | atomic_t fw_outstanding; |
308ec459 | 2086 | atomic_t ldio_outstanding; |
39a98554 | 2087 | atomic_t fw_reset_no_pci_access; |
1341c939 SP |
2088 | |
2089 | struct megasas_instance_template *instancet; | |
5d018ad0 | 2090 | struct tasklet_struct isr_tasklet; |
39a98554 | 2091 | struct work_struct work_init; |
fc62b3fc | 2092 | struct work_struct crash_init; |
05e9ebbe SP |
2093 | |
2094 | u8 flag; | |
c3518837 | 2095 | u8 unload; |
f4c9a131 | 2096 | u8 flag_ieee; |
39a98554 | 2097 | u8 issuepend_done; |
2098 | u8 disableOnlineCtrlReset; | |
bc93d425 | 2099 | u8 UnevenSpanSupport; |
51087a86 SS |
2100 | |
2101 | u8 supportmax256vd; | |
30845586 | 2102 | u8 pd_list_not_supported; |
51087a86 SS |
2103 | u16 fw_supported_vd_count; |
2104 | u16 fw_supported_pd_count; | |
2105 | ||
2106 | u16 drv_supported_vd_count; | |
2107 | u16 drv_supported_pd_count; | |
2108 | ||
8a01a41d | 2109 | atomic_t adprecovery; |
05e9ebbe | 2110 | unsigned long last_time; |
39a98554 | 2111 | u32 mfiStatus; |
2112 | u32 last_seq_num; | |
ad84db2e | 2113 | |
39a98554 | 2114 | struct list_head internal_reset_pending_q; |
80d9da98 | 2115 | |
25985edc | 2116 | /* Ptr to hba specific information */ |
9c915a8c | 2117 | void *ctrl_context; |
51087a86 SS |
2118 | u32 ctrl_context_pages; |
2119 | struct megasas_ctrl_info *ctrl_info; | |
c8e858fe | 2120 | unsigned int msix_vectors; |
2121 | struct msix_entry msixentry[MEGASAS_MAX_MSIX_QUEUES]; | |
2122 | struct megasas_irq_context irq_context[MEGASAS_MAX_MSIX_QUEUES]; | |
9c915a8c | 2123 | u64 map_id; |
3761cb4c | 2124 | u64 pd_seq_map_id; |
9c915a8c | 2125 | struct megasas_cmd *map_update_cmd; |
3761cb4c | 2126 | struct megasas_cmd *jbod_seq_cmd; |
b6d5d880 | 2127 | unsigned long bar; |
9c915a8c | 2128 | long reset_flags; |
2129 | struct mutex reset_mutex; | |
229fe47c | 2130 | struct timer_list sriov_heartbeat_timer; |
2131 | char skip_heartbeat_timer_del; | |
2132 | u8 requestorId; | |
229fe47c | 2133 | char PlasmaFW111; |
8f67c8c5 SS |
2134 | char clusterId[MEGASAS_CLUSTER_ID_SIZE]; |
2135 | u8 peerIsPresent; | |
2136 | u8 passive; | |
ae09a6c1 | 2137 | u16 throttlequeuedepth; |
d46a3ad6 | 2138 | u8 mask_interrupts; |
bd5f9484 | 2139 | u16 max_chain_frame_sz; |
404a8a1a | 2140 | u8 is_imr; |
179ac142 | 2141 | u8 is_rdpq; |
5765c5b8 | 2142 | bool dev_handle; |
39a98554 | 2143 | }; |
229fe47c | 2144 | struct MR_LD_VF_MAP { |
2145 | u32 size; | |
2146 | union MR_LD_REF ref; | |
2147 | u8 ldVfCount; | |
2148 | u8 reserved[6]; | |
2149 | u8 policy[1]; | |
2150 | }; | |
2151 | ||
2152 | struct MR_LD_VF_AFFILIATION { | |
2153 | u32 size; | |
2154 | u8 ldCount; | |
2155 | u8 vfCount; | |
2156 | u8 thisVf; | |
2157 | u8 reserved[9]; | |
2158 | struct MR_LD_VF_MAP map[1]; | |
2159 | }; | |
2160 | ||
2161 | /* Plasma 1.11 FW backward compatibility structures */ | |
2162 | #define IOV_111_OFFSET 0x7CE | |
2163 | #define MAX_VIRTUAL_FUNCTIONS 8 | |
4cbfea88 | 2164 | #define MR_LD_ACCESS_HIDDEN 15 |
229fe47c | 2165 | |
2166 | struct IOV_111 { | |
2167 | u8 maxVFsSupported; | |
2168 | u8 numVFsEnabled; | |
2169 | u8 requestorId; | |
2170 | u8 reserved[5]; | |
2171 | }; | |
2172 | ||
2173 | struct MR_LD_VF_MAP_111 { | |
2174 | u8 targetId; | |
2175 | u8 reserved[3]; | |
2176 | u8 policy[MAX_VIRTUAL_FUNCTIONS]; | |
2177 | }; | |
2178 | ||
2179 | struct MR_LD_VF_AFFILIATION_111 { | |
2180 | u8 vdCount; | |
2181 | u8 vfCount; | |
2182 | u8 thisVf; | |
2183 | u8 reserved[5]; | |
2184 | struct MR_LD_VF_MAP_111 map[MAX_LOGICAL_DRIVES]; | |
2185 | }; | |
2186 | ||
2187 | struct MR_CTRL_HB_HOST_MEM { | |
2188 | struct { | |
2189 | u32 fwCounter; /* Firmware heart beat counter */ | |
2190 | struct { | |
2191 | u32 debugmode:1; /* 1=Firmware is in debug mode. | |
2192 | Heart beat will not be updated. */ | |
2193 | u32 reserved:31; | |
2194 | } debug; | |
2195 | u32 reserved_fw[6]; | |
2196 | u32 driverCounter; /* Driver heart beat counter. 0x20 */ | |
2197 | u32 reserved_driver[7]; | |
2198 | } HB; | |
2199 | u8 pad[0x400-0x40]; | |
2200 | }; | |
39a98554 | 2201 | |
2202 | enum { | |
2203 | MEGASAS_HBA_OPERATIONAL = 0, | |
2204 | MEGASAS_ADPRESET_SM_INFAULT = 1, | |
2205 | MEGASAS_ADPRESET_SM_FW_RESET_SUCCESS = 2, | |
2206 | MEGASAS_ADPRESET_SM_OPERATIONAL = 3, | |
2207 | MEGASAS_HW_CRITICAL_ERROR = 4, | |
229fe47c | 2208 | MEGASAS_ADPRESET_SM_POLLING = 5, |
39a98554 | 2209 | MEGASAS_ADPRESET_INPROG_SIGN = 0xDEADDEAD, |
c4a3e0a5 BS |
2210 | }; |
2211 | ||
0c79e681 YB |
2212 | struct megasas_instance_template { |
2213 | void (*fire_cmd)(struct megasas_instance *, dma_addr_t, \ | |
2214 | u32, struct megasas_register_set __iomem *); | |
2215 | ||
d46a3ad6 SS |
2216 | void (*enable_intr)(struct megasas_instance *); |
2217 | void (*disable_intr)(struct megasas_instance *); | |
0c79e681 YB |
2218 | |
2219 | int (*clear_intr)(struct megasas_register_set __iomem *); | |
2220 | ||
2221 | u32 (*read_fw_status_reg)(struct megasas_register_set __iomem *); | |
39a98554 | 2222 | int (*adp_reset)(struct megasas_instance *, \ |
2223 | struct megasas_register_set __iomem *); | |
2224 | int (*check_reset)(struct megasas_instance *, \ | |
2225 | struct megasas_register_set __iomem *); | |
cd50ba8e | 2226 | irqreturn_t (*service_isr)(int irq, void *devp); |
2227 | void (*tasklet)(unsigned long); | |
2228 | u32 (*init_adapter)(struct megasas_instance *); | |
2229 | u32 (*build_and_issue_cmd) (struct megasas_instance *, | |
2230 | struct scsi_cmnd *); | |
6d40afbc | 2231 | int (*issue_dcmd)(struct megasas_instance *instance, |
cd50ba8e | 2232 | struct megasas_cmd *cmd); |
0c79e681 YB |
2233 | }; |
2234 | ||
c4a3e0a5 BS |
2235 | #define MEGASAS_IS_LOGICAL(scp) \ |
2236 | (scp->device->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1 | |
2237 | ||
4a5c814d SS |
2238 | #define MEGASAS_DEV_INDEX(scp) \ |
2239 | (((scp->device->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) + \ | |
2240 | scp->device->id) | |
2241 | ||
2242 | #define MEGASAS_PD_INDEX(scp) \ | |
2243 | ((scp->device->channel * MEGASAS_MAX_DEV_PER_CHANNEL) + \ | |
2244 | scp->device->id) | |
c4a3e0a5 BS |
2245 | |
2246 | struct megasas_cmd { | |
2247 | ||
2248 | union megasas_frame *frame; | |
2249 | dma_addr_t frame_phys_addr; | |
2250 | u8 *sense; | |
2251 | dma_addr_t sense_phys_addr; | |
2252 | ||
2253 | u32 index; | |
2254 | u8 sync_cmd; | |
2be2a988 | 2255 | u8 cmd_status_drv; |
39a98554 | 2256 | u8 abort_aen; |
2257 | u8 retry_for_fw_reset; | |
2258 | ||
c4a3e0a5 BS |
2259 | |
2260 | struct list_head list; | |
2261 | struct scsi_cmnd *scmd; | |
4026e9aa | 2262 | u8 flags; |
90dc9d98 | 2263 | |
c4a3e0a5 | 2264 | struct megasas_instance *instance; |
9c915a8c | 2265 | union { |
2266 | struct { | |
2267 | u16 smid; | |
2268 | u16 resvd; | |
2269 | } context; | |
2270 | u32 frame_count; | |
2271 | }; | |
c4a3e0a5 BS |
2272 | }; |
2273 | ||
2274 | #define MAX_MGMT_ADAPTERS 1024 | |
2275 | #define MAX_IOCTL_SGE 16 | |
2276 | ||
2277 | struct megasas_iocpacket { | |
2278 | ||
2279 | u16 host_no; | |
2280 | u16 __pad1; | |
2281 | u32 sgl_off; | |
2282 | u32 sge_count; | |
2283 | u32 sense_off; | |
2284 | u32 sense_len; | |
2285 | union { | |
2286 | u8 raw[128]; | |
2287 | struct megasas_header hdr; | |
2288 | } frame; | |
2289 | ||
2290 | struct iovec sgl[MAX_IOCTL_SGE]; | |
2291 | ||
2292 | } __attribute__ ((packed)); | |
2293 | ||
2294 | struct megasas_aen { | |
2295 | u16 host_no; | |
2296 | u16 __pad1; | |
2297 | u32 seq_num; | |
2298 | u32 class_locale_word; | |
2299 | } __attribute__ ((packed)); | |
2300 | ||
2301 | #ifdef CONFIG_COMPAT | |
2302 | struct compat_megasas_iocpacket { | |
2303 | u16 host_no; | |
2304 | u16 __pad1; | |
2305 | u32 sgl_off; | |
2306 | u32 sge_count; | |
2307 | u32 sense_off; | |
2308 | u32 sense_len; | |
2309 | union { | |
2310 | u8 raw[128]; | |
2311 | struct megasas_header hdr; | |
2312 | } frame; | |
2313 | struct compat_iovec sgl[MAX_IOCTL_SGE]; | |
2314 | } __attribute__ ((packed)); | |
2315 | ||
0e98936c | 2316 | #define MEGASAS_IOC_FIRMWARE32 _IOWR('M', 1, struct compat_megasas_iocpacket) |
c4a3e0a5 BS |
2317 | #endif |
2318 | ||
cb59aa6a | 2319 | #define MEGASAS_IOC_FIRMWARE _IOWR('M', 1, struct megasas_iocpacket) |
c4a3e0a5 BS |
2320 | #define MEGASAS_IOC_GET_AEN _IOW('M', 3, struct megasas_aen) |
2321 | ||
2322 | struct megasas_mgmt_info { | |
2323 | ||
2324 | u16 count; | |
2325 | struct megasas_instance *instance[MAX_MGMT_ADAPTERS]; | |
2326 | int max_index; | |
2327 | }; | |
2328 | ||
6d40afbc SS |
2329 | enum MEGASAS_OCR_CAUSE { |
2330 | FW_FAULT_OCR = 0, | |
2331 | SCSIIO_TIMEOUT_OCR = 1, | |
2332 | MFI_IO_TIMEOUT_OCR = 2, | |
2333 | }; | |
2334 | ||
2335 | enum DCMD_RETURN_STATUS { | |
2336 | DCMD_SUCCESS = 0, | |
2337 | DCMD_TIMEOUT = 1, | |
2338 | DCMD_FAILED = 2, | |
2339 | DCMD_NOT_FIRED = 3, | |
2340 | }; | |
2341 | ||
21c9e160 | 2342 | u8 |
2343 | MR_BuildRaidContext(struct megasas_instance *instance, | |
2344 | struct IO_REQUEST_INFO *io_info, | |
2345 | struct RAID_CONTEXT *pRAID_Context, | |
51087a86 SS |
2346 | struct MR_DRV_RAID_MAP_ALL *map, u8 **raidLUN); |
2347 | u8 MR_TargetIdToLdGet(u32 ldTgtId, struct MR_DRV_RAID_MAP_ALL *map); | |
2348 | struct MR_LD_RAID *MR_LdRaidGet(u32 ld, struct MR_DRV_RAID_MAP_ALL *map); | |
2349 | u16 MR_ArPdGet(u32 ar, u32 arm, struct MR_DRV_RAID_MAP_ALL *map); | |
2350 | u16 MR_LdSpanArrayGet(u32 ld, u32 span, struct MR_DRV_RAID_MAP_ALL *map); | |
9ab9ed38 | 2351 | __le16 MR_PdDevHandleGet(u32 pd, struct MR_DRV_RAID_MAP_ALL *map); |
51087a86 SS |
2352 | u16 MR_GetLDTgtId(u32 ld, struct MR_DRV_RAID_MAP_ALL *map); |
2353 | ||
9ab9ed38 | 2354 | __le16 get_updated_dev_handle(struct megasas_instance *instance, |
d2552ebe | 2355 | struct LD_LOAD_BALANCE_INFO *lbInfo, struct IO_REQUEST_INFO *in_info); |
51087a86 SS |
2356 | void mr_update_load_balance_params(struct MR_DRV_RAID_MAP_ALL *map, |
2357 | struct LD_LOAD_BALANCE_INFO *lbInfo); | |
d009b576 | 2358 | int megasas_get_ctrl_info(struct megasas_instance *instance); |
3761cb4c | 2359 | /* PD sequence */ |
2360 | int | |
2361 | megasas_sync_pd_seq_num(struct megasas_instance *instance, bool pend); | |
fc62b3fc | 2362 | int megasas_set_crash_dump_params(struct megasas_instance *instance, |
51087a86 | 2363 | u8 crash_buf_state); |
fc62b3fc SS |
2364 | void megasas_free_host_crash_buffer(struct megasas_instance *instance); |
2365 | void megasas_fusion_crash_dump_wq(struct work_struct *work); | |
51087a86 | 2366 | |
90dc9d98 SS |
2367 | void megasas_return_cmd_fusion(struct megasas_instance *instance, |
2368 | struct megasas_cmd_fusion *cmd); | |
2369 | int megasas_issue_blocked_cmd(struct megasas_instance *instance, | |
2370 | struct megasas_cmd *cmd, int timeout); | |
2371 | void __megasas_return_cmd(struct megasas_instance *instance, | |
2372 | struct megasas_cmd *cmd); | |
2373 | ||
2374 | void megasas_return_mfi_mpt_pthr(struct megasas_instance *instance, | |
2375 | struct megasas_cmd *cmd_mfi, struct megasas_cmd_fusion *cmd_fusion); | |
7497cde8 | 2376 | int megasas_cmd_type(struct scsi_cmnd *cmd); |
3761cb4c | 2377 | void megasas_setup_jbod_map(struct megasas_instance *instance); |
90dc9d98 | 2378 | |
18365b13 SS |
2379 | void megasas_update_sdev_properties(struct scsi_device *sdev); |
2380 | int megasas_reset_fusion(struct Scsi_Host *shost, int reason); | |
2381 | int megasas_task_abort_fusion(struct scsi_cmnd *scmd); | |
2382 | int megasas_reset_target_fusion(struct scsi_cmnd *scmd); | |
c4a3e0a5 | 2383 | #endif /*LSI_MEGARAID_SAS_H */ |