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[SCSI] megaraid_sas: add hibernation support
[deliverable/linux.git] / drivers / scsi / megaraid / megaraid_sas.h
CommitLineData
c4a3e0a5
BS		 1/*
2 *
3 * Linux MegaRAID driver for SAS based RAID controllers
4 *
5 * Copyright (c) 2003-2005 LSI Logic Corporation.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 *
12 * FILE : megaraid_sas.h
13 */
14
15#ifndef LSI_MEGARAID_SAS_H
16#define LSI_MEGARAID_SAS_H
17
a69b74d3 18/*
c4a3e0a5
BS		 19 * MegaRAID SAS Driver meta data
20 */
05e9ebbe
SP		 21#define MEGASAS_VERSION "00.00.03.10-rc5"
22#define MEGASAS_RELDATE "May 17, 2007"
23#define MEGASAS_EXT_VERSION "Thu May 17 10:09:32 PDT 2007"
0e98936c
SP		 24
25/*
26 * Device IDs
27 */
28#define PCI_DEVICE_ID_LSI_SAS1078R 0x0060
29#define PCI_DEVICE_ID_LSI_VERDE_ZCR 0x0413
30
c4a3e0a5
BS		 31/*
32 * =====================================
33 * MegaRAID SAS MFI firmware definitions
34 * =====================================
35 */
36
37/*
38 * MFI stands for MegaRAID SAS FW Interface. This is just a moniker for
39 * protocol between the software and firmware. Commands are issued using
40 * "message frames"
41 */
42
a69b74d3 43/*
c4a3e0a5
BS		 44 * FW posts its state in upper 4 bits of outbound_msg_0 register
45 */
46#define MFI_STATE_MASK 0xF0000000
47#define MFI_STATE_UNDEFINED 0x00000000
48#define MFI_STATE_BB_INIT 0x10000000
49#define MFI_STATE_FW_INIT 0x40000000
50#define MFI_STATE_WAIT_HANDSHAKE 0x60000000
51#define MFI_STATE_FW_INIT_2 0x70000000
52#define MFI_STATE_DEVICE_SCAN 0x80000000
e3bbff9f 53#define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000
c4a3e0a5
BS		 54#define MFI_STATE_FLUSH_CACHE 0xA0000000
55#define MFI_STATE_READY 0xB0000000
56#define MFI_STATE_OPERATIONAL 0xC0000000
57#define MFI_STATE_FAULT 0xF0000000
58
59#define MEGAMFI_FRAME_SIZE 64
60
a69b74d3 61/*
c4a3e0a5
BS		 62 * During FW init, clear pending cmds & reset state using inbound_msg_0
63 *
64 * ABORT : Abort all pending cmds
65 * READY : Move from OPERATIONAL to READY state; discard queue info
66 * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??)
67 * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver
e3bbff9f
SP		 68 * HOTPLUG : Resume from Hotplug
69 * MFI_STOP_ADP : Send signal to FW to stop processing
c4a3e0a5 70 */
e3bbff9f 71#define MFI_INIT_ABORT 0x00000001
c4a3e0a5
BS		 72#define MFI_INIT_READY 0x00000002
73#define MFI_INIT_MFIMODE 0x00000004
74#define MFI_INIT_CLEAR_HANDSHAKE 0x00000008
e3bbff9f
SP		 75#define MFI_INIT_HOTPLUG 0x00000010
76#define MFI_STOP_ADP 0x00000020
77#define MFI_RESET_FLAGS MFI_INIT_READY| \
78 MFI_INIT_MFIMODE| \
79 MFI_INIT_ABORT
c4a3e0a5 80
a69b74d3 81/*
c4a3e0a5
BS		 82 * MFI frame flags
83 */
84#define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000
85#define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001
86#define MFI_FRAME_SGL32 0x0000
87#define MFI_FRAME_SGL64 0x0002
88#define MFI_FRAME_SENSE32 0x0000
89#define MFI_FRAME_SENSE64 0x0004
90#define MFI_FRAME_DIR_NONE 0x0000
91#define MFI_FRAME_DIR_WRITE 0x0008
92#define MFI_FRAME_DIR_READ 0x0010
93#define MFI_FRAME_DIR_BOTH 0x0018
94
a69b74d3 95/*
c4a3e0a5
BS		 96 * Definition for cmd_status
97 */
98#define MFI_CMD_STATUS_POLL_MODE 0xFF
99
a69b74d3 100/*
c4a3e0a5
BS		 101 * MFI command opcodes
102 */
103#define MFI_CMD_INIT 0x00
104#define MFI_CMD_LD_READ 0x01
105#define MFI_CMD_LD_WRITE 0x02
106#define MFI_CMD_LD_SCSI_IO 0x03
107#define MFI_CMD_PD_SCSI_IO 0x04
108#define MFI_CMD_DCMD 0x05
109#define MFI_CMD_ABORT 0x06
110#define MFI_CMD_SMP 0x07
111#define MFI_CMD_STP 0x08
112
113#define MR_DCMD_CTRL_GET_INFO 0x01010000
114
115#define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000
116#define MR_FLUSH_CTRL_CACHE 0x01
117#define MR_FLUSH_DISK_CACHE 0x02
118
119#define MR_DCMD_CTRL_SHUTDOWN 0x01050000
31ea7088 120#define MR_DCMD_HIBERNATE_SHUTDOWN 0x01060000
c4a3e0a5
BS		 121#define MR_ENABLE_DRIVE_SPINDOWN 0x01
122
123#define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100
124#define MR_DCMD_CTRL_EVENT_GET 0x01040300
125#define MR_DCMD_CTRL_EVENT_WAIT 0x01040500
126#define MR_DCMD_LD_GET_PROPERTIES 0x03030000
127
128#define MR_DCMD_CLUSTER 0x08000000
129#define MR_DCMD_CLUSTER_RESET_ALL 0x08010100
130#define MR_DCMD_CLUSTER_RESET_LD 0x08010200
131
a69b74d3 132/*
c4a3e0a5
BS		 133 * MFI command completion codes
134 */
135enum MFI_STAT {
136 MFI_STAT_OK = 0x00,
137 MFI_STAT_INVALID_CMD = 0x01,
138 MFI_STAT_INVALID_DCMD = 0x02,
139 MFI_STAT_INVALID_PARAMETER = 0x03,
140 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04,
141 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05,
142 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06,
143 MFI_STAT_APP_IN_USE = 0x07,
144 MFI_STAT_APP_NOT_INITIALIZED = 0x08,
145 MFI_STAT_ARRAY_INDEX_INVALID = 0x09,
146 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a,
147 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b,
148 MFI_STAT_DEVICE_NOT_FOUND = 0x0c,
149 MFI_STAT_DRIVE_TOO_SMALL = 0x0d,
150 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e,
151 MFI_STAT_FLASH_BUSY = 0x0f,
152 MFI_STAT_FLASH_ERROR = 0x10,
153 MFI_STAT_FLASH_IMAGE_BAD = 0x11,
154 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12,
155 MFI_STAT_FLASH_NOT_OPEN = 0x13,
156 MFI_STAT_FLASH_NOT_STARTED = 0x14,
157 MFI_STAT_FLUSH_FAILED = 0x15,
158 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16,
159 MFI_STAT_LD_CC_IN_PROGRESS = 0x17,
160 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18,
161 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19,
162 MFI_STAT_LD_MAX_CONFIGURED = 0x1a,
163 MFI_STAT_LD_NOT_OPTIMAL = 0x1b,
164 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c,
165 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d,
166 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e,
167 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f,
168 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
169 MFI_STAT_MFC_HW_ERROR = 0x21,
170 MFI_STAT_NO_HW_PRESENT = 0x22,
171 MFI_STAT_NOT_FOUND = 0x23,
172 MFI_STAT_NOT_IN_ENCL = 0x24,
173 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25,
174 MFI_STAT_PD_TYPE_WRONG = 0x26,
175 MFI_STAT_PR_DISABLED = 0x27,
176 MFI_STAT_ROW_INDEX_INVALID = 0x28,
177 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29,
178 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a,
179 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b,
180 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c,
181 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d,
182 MFI_STAT_SCSI_IO_FAILED = 0x2e,
183 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f,
184 MFI_STAT_SHUTDOWN_FAILED = 0x30,
185 MFI_STAT_TIME_NOT_SET = 0x31,
186 MFI_STAT_WRONG_STATE = 0x32,
187 MFI_STAT_LD_OFFLINE = 0x33,
188 MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34,
189 MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35,
190 MFI_STAT_RESERVATION_IN_PROGRESS = 0x36,
191 MFI_STAT_I2C_ERRORS_DETECTED = 0x37,
192 MFI_STAT_PCI_ERRORS_DETECTED = 0x38,
193
194 MFI_STAT_INVALID_STATUS = 0xFF
195};
196
197/*
198 * Number of mailbox bytes in DCMD message frame
199 */
200#define MFI_MBOX_SIZE 12
201
202enum MR_EVT_CLASS {
203
204 MR_EVT_CLASS_DEBUG = -2,
205 MR_EVT_CLASS_PROGRESS = -1,
206 MR_EVT_CLASS_INFO = 0,
207 MR_EVT_CLASS_WARNING = 1,
208 MR_EVT_CLASS_CRITICAL = 2,
209 MR_EVT_CLASS_FATAL = 3,
210 MR_EVT_CLASS_DEAD = 4,
211
212};
213
214enum MR_EVT_LOCALE {
215
216 MR_EVT_LOCALE_LD = 0x0001,
217 MR_EVT_LOCALE_PD = 0x0002,
218 MR_EVT_LOCALE_ENCL = 0x0004,
219 MR_EVT_LOCALE_BBU = 0x0008,
220 MR_EVT_LOCALE_SAS = 0x0010,
221 MR_EVT_LOCALE_CTRL = 0x0020,
222 MR_EVT_LOCALE_CONFIG = 0x0040,
223 MR_EVT_LOCALE_CLUSTER = 0x0080,
224 MR_EVT_LOCALE_ALL = 0xffff,
225
226};
227
228enum MR_EVT_ARGS {
229
230 MR_EVT_ARGS_NONE,
231 MR_EVT_ARGS_CDB_SENSE,
232 MR_EVT_ARGS_LD,
233 MR_EVT_ARGS_LD_COUNT,
234 MR_EVT_ARGS_LD_LBA,
235 MR_EVT_ARGS_LD_OWNER,
236 MR_EVT_ARGS_LD_LBA_PD_LBA,
237 MR_EVT_ARGS_LD_PROG,
238 MR_EVT_ARGS_LD_STATE,
239 MR_EVT_ARGS_LD_STRIP,
240 MR_EVT_ARGS_PD,
241 MR_EVT_ARGS_PD_ERR,
242 MR_EVT_ARGS_PD_LBA,
243 MR_EVT_ARGS_PD_LBA_LD,
244 MR_EVT_ARGS_PD_PROG,
245 MR_EVT_ARGS_PD_STATE,
246 MR_EVT_ARGS_PCI,
247 MR_EVT_ARGS_RATE,
248 MR_EVT_ARGS_STR,
249 MR_EVT_ARGS_TIME,
250 MR_EVT_ARGS_ECC,
251
252};
253
254/*
255 * SAS controller properties
256 */
257struct megasas_ctrl_prop {
258
259 u16 seq_num;
260 u16 pred_fail_poll_interval;
261 u16 intr_throttle_count;
262 u16 intr_throttle_timeouts;
263 u8 rebuild_rate;
264 u8 patrol_read_rate;
265 u8 bgi_rate;
266 u8 cc_rate;
267 u8 recon_rate;
268 u8 cache_flush_interval;
269 u8 spinup_drv_count;
270 u8 spinup_delay;
271 u8 cluster_enable;
272 u8 coercion_mode;
273 u8 alarm_enable;
274 u8 disable_auto_rebuild;
275 u8 disable_battery_warn;
276 u8 ecc_bucket_size;
277 u16 ecc_bucket_leak_rate;
278 u8 restore_hotspare_on_insertion;
279 u8 expose_encl_devices;
280 u8 reserved[38];
281
282} __attribute__ ((packed));
283
284/*
285 * SAS controller information
286 */
287struct megasas_ctrl_info {
288
289 /*
290 * PCI device information
291 */
292 struct {
293
294 u16 vendor_id;
295 u16 device_id;
296 u16 sub_vendor_id;
297 u16 sub_device_id;
298 u8 reserved[24];
299
300 } __attribute__ ((packed)) pci;
301
302 /*
303 * Host interface information
304 */
305 struct {
306
307 u8 PCIX:1;
308 u8 PCIE:1;
309 u8 iSCSI:1;
310 u8 SAS_3G:1;
311 u8 reserved_0:4;
312 u8 reserved_1[6];
313 u8 port_count;
314 u64 port_addr[8];
315
316 } __attribute__ ((packed)) host_interface;
317
318 /*
319 * Device (backend) interface information
320 */
321 struct {
322
323 u8 SPI:1;
324 u8 SAS_3G:1;
325 u8 SATA_1_5G:1;
326 u8 SATA_3G:1;
327 u8 reserved_0:4;
328 u8 reserved_1[6];
329 u8 port_count;
330 u64 port_addr[8];
331
332 } __attribute__ ((packed)) device_interface;
333
334 /*
335 * List of components residing in flash. All str are null terminated
336 */
337 u32 image_check_word;
338 u32 image_component_count;
339
340 struct {
341
342 char name[8];
343 char version[32];
344 char build_date[16];
345 char built_time[16];
346
347 } __attribute__ ((packed)) image_component[8];
348
349 /*
350 * List of flash components that have been flashed on the card, but
351 * are not in use, pending reset of the adapter. This list will be
352 * empty if a flash operation has not occurred. All stings are null
353 * terminated
354 */
355 u32 pending_image_component_count;
356
357 struct {
358
359 char name[8];
360 char version[32];
361 char build_date[16];
362 char build_time[16];
363
364 } __attribute__ ((packed)) pending_image_component[8];
365
366 u8 max_arms;
367 u8 max_spans;
368 u8 max_arrays;
369 u8 max_lds;
370
371 char product_name[80];
372 char serial_no[32];
373
374 /*
375 * Other physical/controller/operation information. Indicates the
376 * presence of the hardware
377 */
378 struct {
379
380 u32 bbu:1;
381 u32 alarm:1;
382 u32 nvram:1;
383 u32 uart:1;
384 u32 reserved:28;
385
386 } __attribute__ ((packed)) hw_present;
387
388 u32 current_fw_time;
389
390 /*
391 * Maximum data transfer sizes
392 */
393 u16 max_concurrent_cmds;
394 u16 max_sge_count;
395 u32 max_request_size;
396
397 /*
398 * Logical and physical device counts
399 */
400 u16 ld_present_count;
401 u16 ld_degraded_count;
402 u16 ld_offline_count;
403
404 u16 pd_present_count;
405 u16 pd_disk_present_count;
406 u16 pd_disk_pred_failure_count;
407 u16 pd_disk_failed_count;
408
409 /*
410 * Memory size information
411 */
412 u16 nvram_size;
413 u16 memory_size;
414 u16 flash_size;
415
416 /*
417 * Error counters
418 */
419 u16 mem_correctable_error_count;
420 u16 mem_uncorrectable_error_count;
421
422 /*
423 * Cluster information
424 */
425 u8 cluster_permitted;
426 u8 cluster_active;
427
428 /*
429 * Additional max data transfer sizes
430 */
431 u16 max_strips_per_io;
432
433 /*
434 * Controller capabilities structures
435 */
436 struct {
437
438 u32 raid_level_0:1;
439 u32 raid_level_1:1;
440 u32 raid_level_5:1;
441 u32 raid_level_1E:1;
442 u32 raid_level_6:1;
443 u32 reserved:27;
444
445 } __attribute__ ((packed)) raid_levels;
446
447 struct {
448
449 u32 rbld_rate:1;
450 u32 cc_rate:1;
451 u32 bgi_rate:1;
452 u32 recon_rate:1;
453 u32 patrol_rate:1;
454 u32 alarm_control:1;
455 u32 cluster_supported:1;
456 u32 bbu:1;
457 u32 spanning_allowed:1;
458 u32 dedicated_hotspares:1;
459 u32 revertible_hotspares:1;
460 u32 foreign_config_import:1;
461 u32 self_diagnostic:1;
462 u32 mixed_redundancy_arr:1;
463 u32 global_hot_spares:1;
464 u32 reserved:17;
465
466 } __attribute__ ((packed)) adapter_operations;
467
468 struct {
469
470 u32 read_policy:1;
471 u32 write_policy:1;
472 u32 io_policy:1;
473 u32 access_policy:1;
474 u32 disk_cache_policy:1;
475 u32 reserved:27;
476
477 } __attribute__ ((packed)) ld_operations;
478
479 struct {
480
481 u8 min;
482 u8 max;
483 u8 reserved[2];
484
485 } __attribute__ ((packed)) stripe_sz_ops;
486
487 struct {
488
489 u32 force_online:1;
490 u32 force_offline:1;
491 u32 force_rebuild:1;
492 u32 reserved:29;
493
494 } __attribute__ ((packed)) pd_operations;
495
496 struct {
497
498 u32 ctrl_supports_sas:1;
499 u32 ctrl_supports_sata:1;
500 u32 allow_mix_in_encl:1;
501 u32 allow_mix_in_ld:1;
502 u32 allow_sata_in_cluster:1;
503 u32 reserved:27;
504
505 } __attribute__ ((packed)) pd_mix_support;
506
507 /*
508 * Define ECC single-bit-error bucket information
509 */
510 u8 ecc_bucket_count;
511 u8 reserved_2[11];
512
513 /*
514 * Include the controller properties (changeable items)
515 */
516 struct megasas_ctrl_prop properties;
517
518 /*
519 * Define FW pkg version (set in envt v'bles on OEM basis)
520 */
521 char package_version[0x60];
522
523 u8 pad[0x800 - 0x6a0];
524
525} __attribute__ ((packed));
526
527/*
528 * ===============================
529 * MegaRAID SAS driver definitions
530 * ===============================
531 */
532#define MEGASAS_MAX_PD_CHANNELS 2
533#define MEGASAS_MAX_LD_CHANNELS 2
534#define MEGASAS_MAX_CHANNELS (MEGASAS_MAX_PD_CHANNELS + \
535 MEGASAS_MAX_LD_CHANNELS)
536#define MEGASAS_MAX_DEV_PER_CHANNEL 128
537#define MEGASAS_DEFAULT_INIT_ID -1
538#define MEGASAS_MAX_LUN 8
539#define MEGASAS_MAX_LD 64
540
658dcedb
SP		 541#define MEGASAS_DBG_LVL 1
542
05e9ebbe
SP		 543#define MEGASAS_FW_BUSY 1
544
c4a3e0a5
BS		 545/*
546 * When SCSI mid-layer calls driver's reset routine, driver waits for
547 * MEGASAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note
548 * that the driver cannot _actually_ abort or reset pending commands. While
549 * it is waiting for the commands to complete, it prints a diagnostic message
550 * every MEGASAS_RESET_NOTICE_INTERVAL seconds
551 */
552#define MEGASAS_RESET_WAIT_TIME 180
2a3681e5 553#define MEGASAS_INTERNAL_CMD_WAIT_TIME 180
c4a3e0a5 554#define MEGASAS_RESET_NOTICE_INTERVAL 5
c4a3e0a5 555#define MEGASAS_IOCTL_CMD 0
05e9ebbe 556#define MEGASAS_DEFAULT_CMD_TIMEOUT 90
c4a3e0a5
BS		 557
558/*
559 * FW reports the maximum of number of commands that it can accept (maximum
560 * commands that can be outstanding) at any time. The driver must report a
561 * lower number to the mid layer because it can issue a few internal commands
562 * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs
563 * is shown below
564 */
565#define MEGASAS_INT_CMDS 32
566
567/*
568 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit
569 * SGLs based on the size of dma_addr_t
570 */
571#define IS_DMA64 (sizeof(dma_addr_t) == 8)
572
573#define MFI_OB_INTR_STATUS_MASK 0x00000002
574#define MFI_POLL_TIMEOUT_SECS 10
575
f9876f0b 576#define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000
0e98936c
SP		 577
578/*
579* register set for both 1068 and 1078 controllers
580* structure extended for 1078 registers
581*/
f9876f0b 582
c4a3e0a5 583struct megasas_register_set {
f9876f0b 584 u32 reserved_0[4]; /*0000h*/
c4a3e0a5 585
f9876f0b
SP		 586 u32 inbound_msg_0; /*0010h*/
587 u32 inbound_msg_1; /*0014h*/
588 u32 outbound_msg_0; /*0018h*/
589 u32 outbound_msg_1; /*001Ch*/
c4a3e0a5 590
f9876f0b
SP		 591 u32 inbound_doorbell; /*0020h*/
592 u32 inbound_intr_status; /*0024h*/
593 u32 inbound_intr_mask; /*0028h*/
c4a3e0a5 594
f9876f0b
SP		 595 u32 outbound_doorbell; /*002Ch*/
596 u32 outbound_intr_status; /*0030h*/
597 u32 outbound_intr_mask; /*0034h*/
c4a3e0a5 598
f9876f0b 599 u32 reserved_1[2]; /*0038h*/
c4a3e0a5 600
f9876f0b
SP		 601 u32 inbound_queue_port; /*0040h*/
602 u32 outbound_queue_port; /*0044h*/
c4a3e0a5 603
f9876f0b 604 u32 reserved_2[22]; /*0048h*/
c4a3e0a5 605
f9876f0b 606 u32 outbound_doorbell_clear; /*00A0h*/
c4a3e0a5 607
f9876f0b
SP		 608 u32 reserved_3[3]; /*00A4h*/
609
610 u32 outbound_scratch_pad ; /*00B0h*/
611
612 u32 reserved_4[3]; /*00B4h*/
613
614 u32 inbound_low_queue_port ; /*00C0h*/
615
616 u32 inbound_high_queue_port ; /*00C4h*/
617
618 u32 reserved_5; /*00C8h*/
619 u32 index_registers[820]; /*00CCh*/
c4a3e0a5
BS		 620
621} __attribute__ ((packed));
622
623struct megasas_sge32 {
624
625 u32 phys_addr;
626 u32 length;
627
628} __attribute__ ((packed));
629
630struct megasas_sge64 {
631
632 u64 phys_addr;
633 u32 length;
634
635} __attribute__ ((packed));
636
637union megasas_sgl {
638
639 struct megasas_sge32 sge32[1];
640 struct megasas_sge64 sge64[1];
641
642} __attribute__ ((packed));
643
644struct megasas_header {
645
646 u8 cmd; /*00h */
647 u8 sense_len; /*01h */
648 u8 cmd_status; /*02h */
649 u8 scsi_status; /*03h */
650
651 u8 target_id; /*04h */
652 u8 lun; /*05h */
653 u8 cdb_len; /*06h */
654 u8 sge_count; /*07h */
655
656 u32 context; /*08h */
657 u32 pad_0; /*0Ch */
658
659 u16 flags; /*10h */
660 u16 timeout; /*12h */
661 u32 data_xferlen; /*14h */
662
663} __attribute__ ((packed));
664
665union megasas_sgl_frame {
666
667 struct megasas_sge32 sge32[8];
668 struct megasas_sge64 sge64[5];
669
670} __attribute__ ((packed));
671
672struct megasas_init_frame {
673
674 u8 cmd; /*00h */
675 u8 reserved_0; /*01h */
676 u8 cmd_status; /*02h */
677
678 u8 reserved_1; /*03h */
679 u32 reserved_2; /*04h */
680
681 u32 context; /*08h */
682 u32 pad_0; /*0Ch */
683
684 u16 flags; /*10h */
685 u16 reserved_3; /*12h */
686 u32 data_xfer_len; /*14h */
687
688 u32 queue_info_new_phys_addr_lo; /*18h */
689 u32 queue_info_new_phys_addr_hi; /*1Ch */
690 u32 queue_info_old_phys_addr_lo; /*20h */
691 u32 queue_info_old_phys_addr_hi; /*24h */
692
693 u32 reserved_4[6]; /*28h */
694
695} __attribute__ ((packed));
696
697struct megasas_init_queue_info {
698
699 u32 init_flags; /*00h */
700 u32 reply_queue_entries; /*04h */
701
702 u32 reply_queue_start_phys_addr_lo; /*08h */
703 u32 reply_queue_start_phys_addr_hi; /*0Ch */
704 u32 producer_index_phys_addr_lo; /*10h */
705 u32 producer_index_phys_addr_hi; /*14h */
706 u32 consumer_index_phys_addr_lo; /*18h */
707 u32 consumer_index_phys_addr_hi; /*1Ch */
708
709} __attribute__ ((packed));
710
711struct megasas_io_frame {
712
713 u8 cmd; /*00h */
714 u8 sense_len; /*01h */
715 u8 cmd_status; /*02h */
716 u8 scsi_status; /*03h */
717
718 u8 target_id; /*04h */
719 u8 access_byte; /*05h */
720 u8 reserved_0; /*06h */
721 u8 sge_count; /*07h */
722
723 u32 context; /*08h */
724 u32 pad_0; /*0Ch */
725
726 u16 flags; /*10h */
727 u16 timeout; /*12h */
728 u32 lba_count; /*14h */
729
730 u32 sense_buf_phys_addr_lo; /*18h */
731 u32 sense_buf_phys_addr_hi; /*1Ch */
732
733 u32 start_lba_lo; /*20h */
734 u32 start_lba_hi; /*24h */
735
736 union megasas_sgl sgl; /*28h */
737
738} __attribute__ ((packed));
739
740struct megasas_pthru_frame {
741
742 u8 cmd; /*00h */
743 u8 sense_len; /*01h */
744 u8 cmd_status; /*02h */
745 u8 scsi_status; /*03h */
746
747 u8 target_id; /*04h */
748 u8 lun; /*05h */
749 u8 cdb_len; /*06h */
750 u8 sge_count; /*07h */
751
752 u32 context; /*08h */
753 u32 pad_0; /*0Ch */
754
755 u16 flags; /*10h */
756 u16 timeout; /*12h */
757 u32 data_xfer_len; /*14h */
758
759 u32 sense_buf_phys_addr_lo; /*18h */
760 u32 sense_buf_phys_addr_hi; /*1Ch */
761
762 u8 cdb[16]; /*20h */
763 union megasas_sgl sgl; /*30h */
764
765} __attribute__ ((packed));
766
767struct megasas_dcmd_frame {
768
769 u8 cmd; /*00h */
770 u8 reserved_0; /*01h */
771 u8 cmd_status; /*02h */
772 u8 reserved_1[4]; /*03h */
773 u8 sge_count; /*07h */
774
775 u32 context; /*08h */
776 u32 pad_0; /*0Ch */
777
778 u16 flags; /*10h */
779 u16 timeout; /*12h */
780
781 u32 data_xfer_len; /*14h */
782 u32 opcode; /*18h */
783
784 union { /*1Ch */
785 u8 b[12];
786 u16 s[6];
787 u32 w[3];
788 } mbox;
789
790 union megasas_sgl sgl; /*28h */
791
792} __attribute__ ((packed));
793
794struct megasas_abort_frame {
795
796 u8 cmd; /*00h */
797 u8 reserved_0; /*01h */
798 u8 cmd_status; /*02h */
799
800 u8 reserved_1; /*03h */
801 u32 reserved_2; /*04h */
802
803 u32 context; /*08h */
804 u32 pad_0; /*0Ch */
805
806 u16 flags; /*10h */
807 u16 reserved_3; /*12h */
808 u32 reserved_4; /*14h */
809
810 u32 abort_context; /*18h */
811 u32 pad_1; /*1Ch */
812
813 u32 abort_mfi_phys_addr_lo; /*20h */
814 u32 abort_mfi_phys_addr_hi; /*24h */
815
816 u32 reserved_5[6]; /*28h */
817
818} __attribute__ ((packed));
819
820struct megasas_smp_frame {
821
822 u8 cmd; /*00h */
823 u8 reserved_1; /*01h */
824 u8 cmd_status; /*02h */
825 u8 connection_status; /*03h */
826
827 u8 reserved_2[3]; /*04h */
828 u8 sge_count; /*07h */
829
830 u32 context; /*08h */
831 u32 pad_0; /*0Ch */
832
833 u16 flags; /*10h */
834 u16 timeout; /*12h */
835
836 u32 data_xfer_len; /*14h */
837 u64 sas_addr; /*18h */
838
839 union {
840 struct megasas_sge32 sge32[2]; /* [0]: resp [1]: req */
841 struct megasas_sge64 sge64[2]; /* [0]: resp [1]: req */
842 } sgl;
843
844} __attribute__ ((packed));
845
846struct megasas_stp_frame {
847
848 u8 cmd; /*00h */
849 u8 reserved_1; /*01h */
850 u8 cmd_status; /*02h */
851 u8 reserved_2; /*03h */
852
853 u8 target_id; /*04h */
854 u8 reserved_3[2]; /*05h */
855 u8 sge_count; /*07h */
856
857 u32 context; /*08h */
858 u32 pad_0; /*0Ch */
859
860 u16 flags; /*10h */
861 u16 timeout; /*12h */
862
863 u32 data_xfer_len; /*14h */
864
865 u16 fis[10]; /*18h */
866 u32 stp_flags;
867
868 union {
869 struct megasas_sge32 sge32[2]; /* [0]: resp [1]: data */
870 struct megasas_sge64 sge64[2]; /* [0]: resp [1]: data */
871 } sgl;
872
873} __attribute__ ((packed));
874
875union megasas_frame {
876
877 struct megasas_header hdr;
878 struct megasas_init_frame init;
879 struct megasas_io_frame io;
880 struct megasas_pthru_frame pthru;
881 struct megasas_dcmd_frame dcmd;
882 struct megasas_abort_frame abort;
883 struct megasas_smp_frame smp;
884 struct megasas_stp_frame stp;
885
886 u8 raw_bytes[64];
887};
888
889struct megasas_cmd;
890
891union megasas_evt_class_locale {
892
893 struct {
894 u16 locale;
895 u8 reserved;
896 s8 class;
897 } __attribute__ ((packed)) members;
898
899 u32 word;
900
901} __attribute__ ((packed));
902
903struct megasas_evt_log_info {
904 u32 newest_seq_num;
905 u32 oldest_seq_num;
906 u32 clear_seq_num;
907 u32 shutdown_seq_num;
908 u32 boot_seq_num;
909
910} __attribute__ ((packed));
911
912struct megasas_progress {
913
914 u16 progress;
915 u16 elapsed_seconds;
916
917} __attribute__ ((packed));
918
919struct megasas_evtarg_ld {
920
921 u16 target_id;
922 u8 ld_index;
923 u8 reserved;
924
925} __attribute__ ((packed));
926
927struct megasas_evtarg_pd {
928 u16 device_id;
929 u8 encl_index;
930 u8 slot_number;
931
932} __attribute__ ((packed));
933
934struct megasas_evt_detail {
935
936 u32 seq_num;
937 u32 time_stamp;
938 u32 code;
939 union megasas_evt_class_locale cl;
940 u8 arg_type;
941 u8 reserved1[15];
942
943 union {
944 struct {
945 struct megasas_evtarg_pd pd;
946 u8 cdb_length;
947 u8 sense_length;
948 u8 reserved[2];
949 u8 cdb[16];
950 u8 sense[64];
951 } __attribute__ ((packed)) cdbSense;
952
953 struct megasas_evtarg_ld ld;
954
955 struct {
956 struct megasas_evtarg_ld ld;
957 u64 count;
958 } __attribute__ ((packed)) ld_count;
959
960 struct {
961 u64 lba;
962 struct megasas_evtarg_ld ld;
963 } __attribute__ ((packed)) ld_lba;
964
965 struct {
966 struct megasas_evtarg_ld ld;
967 u32 prevOwner;
968 u32 newOwner;
969 } __attribute__ ((packed)) ld_owner;
970
971 struct {
972 u64 ld_lba;
973 u64 pd_lba;
974 struct megasas_evtarg_ld ld;
975 struct megasas_evtarg_pd pd;
976 } __attribute__ ((packed)) ld_lba_pd_lba;
977
978 struct {
979 struct megasas_evtarg_ld ld;
980 struct megasas_progress prog;
981 } __attribute__ ((packed)) ld_prog;
982
983 struct {
984 struct megasas_evtarg_ld ld;
985 u32 prev_state;
986 u32 new_state;
987 } __attribute__ ((packed)) ld_state;
988
989 struct {
990 u64 strip;
991 struct megasas_evtarg_ld ld;
992 } __attribute__ ((packed)) ld_strip;
993
994 struct megasas_evtarg_pd pd;
995
996 struct {
997 struct megasas_evtarg_pd pd;
998 u32 err;
999 } __attribute__ ((packed)) pd_err;
1000
1001 struct {
1002 u64 lba;
1003 struct megasas_evtarg_pd pd;
1004 } __attribute__ ((packed)) pd_lba;
1005
1006 struct {
1007 u64 lba;
1008 struct megasas_evtarg_pd pd;
1009 struct megasas_evtarg_ld ld;
1010 } __attribute__ ((packed)) pd_lba_ld;
1011
1012 struct {
1013 struct megasas_evtarg_pd pd;
1014 struct megasas_progress prog;
1015 } __attribute__ ((packed)) pd_prog;
1016
1017 struct {
1018 struct megasas_evtarg_pd pd;
1019 u32 prevState;
1020 u32 newState;
1021 } __attribute__ ((packed)) pd_state;
1022
1023 struct {
1024 u16 vendorId;
1025 u16 deviceId;
1026 u16 subVendorId;
1027 u16 subDeviceId;
1028 } __attribute__ ((packed)) pci;
1029
1030 u32 rate;
1031 char str[96];
1032
1033 struct {
1034 u32 rtc;
1035 u32 elapsedSeconds;
1036 } __attribute__ ((packed)) time;
1037
1038 struct {
1039 u32 ecar;
1040 u32 elog;
1041 char str[64];
1042 } __attribute__ ((packed)) ecc;
1043
1044 u8 b[96];
1045 u16 s[48];
1046 u32 w[24];
1047 u64 d[12];
1048 } args;
1049
1050 char description[128];
1051
1052} __attribute__ ((packed));
1053
1341c939
SP		 1054 struct megasas_instance_template {
1055 void (*fire_cmd)(dma_addr_t ,u32 ,struct megasas_register_set __iomem *);
1056
1057 void (*enable_intr)(struct megasas_register_set __iomem *) ;
b274cab7 1058 void (*disable_intr)(struct megasas_register_set __iomem *);
1341c939
SP		 1059
1060 int (*clear_intr)(struct megasas_register_set __iomem *);
1061
1062 u32 (*read_fw_status_reg)(struct megasas_register_set __iomem *);
1063 };
1064
c4a3e0a5
BS		 1065struct megasas_instance {
1066
1067 u32 *producer;
1068 dma_addr_t producer_h;
1069 u32 *consumer;
1070 dma_addr_t consumer_h;
1071
1072 u32 *reply_queue;
1073 dma_addr_t reply_queue_h;
1074
1075 unsigned long base_addr;
1076 struct megasas_register_set __iomem *reg_set;
1077
1078 s8 init_id;
c4a3e0a5
BS		 1079
1080 u16 max_num_sge;
1081 u16 max_fw_cmds;
1082 u32 max_sectors_per_req;
1083
1084 struct megasas_cmd **cmd_list;
1085 struct list_head cmd_pool;
1086 spinlock_t cmd_pool_lock;
1087 struct dma_pool *frame_dma_pool;
1088 struct dma_pool *sense_dma_pool;
1089
1090 struct megasas_evt_detail *evt_detail;
1091 dma_addr_t evt_detail_h;
1092 struct megasas_cmd *aen_cmd;
e5a69e27 1093 struct mutex aen_mutex;
c4a3e0a5
BS		 1094 struct semaphore ioctl_sem;
1095
1096 struct Scsi_Host *host;
1097
1098 wait_queue_head_t int_cmd_wait_q;
1099 wait_queue_head_t abort_cmd_wait_q;
1100
1101 struct pci_dev *pdev;
1102 u32 unique_id;
1103
e4a082c7 1104 atomic_t fw_outstanding;
c4a3e0a5 1105 u32 hw_crit_error;
1341c939
SP		 1106
1107 struct megasas_instance_template *instancet;
5d018ad0 1108 struct tasklet_struct isr_tasklet;
05e9ebbe
SP		 1109
1110 u8 flag;
1111 unsigned long last_time;
c4a3e0a5
BS		 1112};
1113
1114#define MEGASAS_IS_LOGICAL(scp) \
1115 (scp->device->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1
1116
1117#define MEGASAS_DEV_INDEX(inst, scp) \
1118 ((scp->device->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) + \
1119 scp->device->id
1120
1121struct megasas_cmd {
1122
1123 union megasas_frame *frame;
1124 dma_addr_t frame_phys_addr;
1125 u8 *sense;
1126 dma_addr_t sense_phys_addr;
1127
1128 u32 index;
1129 u8 sync_cmd;
1130 u8 cmd_status;
1131 u16 abort_aen;
1132
1133 struct list_head list;
1134 struct scsi_cmnd *scmd;
1135 struct megasas_instance *instance;
1136 u32 frame_count;
1137};
1138
1139#define MAX_MGMT_ADAPTERS 1024
1140#define MAX_IOCTL_SGE 16
1141
1142struct megasas_iocpacket {
1143
1144 u16 host_no;
1145 u16 __pad1;
1146 u32 sgl_off;
1147 u32 sge_count;
1148 u32 sense_off;
1149 u32 sense_len;
1150 union {
1151 u8 raw[128];
1152 struct megasas_header hdr;
1153 } frame;
1154
1155 struct iovec sgl[MAX_IOCTL_SGE];
1156
1157} __attribute__ ((packed));
1158
1159struct megasas_aen {
1160 u16 host_no;
1161 u16 __pad1;
1162 u32 seq_num;
1163 u32 class_locale_word;
1164} __attribute__ ((packed));
1165
1166#ifdef CONFIG_COMPAT
1167struct compat_megasas_iocpacket {
1168 u16 host_no;
1169 u16 __pad1;
1170 u32 sgl_off;
1171 u32 sge_count;
1172 u32 sense_off;
1173 u32 sense_len;
1174 union {
1175 u8 raw[128];
1176 struct megasas_header hdr;
1177 } frame;
1178 struct compat_iovec sgl[MAX_IOCTL_SGE];
1179} __attribute__ ((packed));
1180
0e98936c 1181#define MEGASAS_IOC_FIRMWARE32 _IOWR('M', 1, struct compat_megasas_iocpacket)
c4a3e0a5
BS		 1182#endif
1183
cb59aa6a 1184#define MEGASAS_IOC_FIRMWARE _IOWR('M', 1, struct megasas_iocpacket)
c4a3e0a5
BS		 1185#define MEGASAS_IOC_GET_AEN _IOW('M', 3, struct megasas_aen)
1186
1187struct megasas_mgmt_info {
1188
1189 u16 count;
1190 struct megasas_instance *instance[MAX_MGMT_ADAPTERS];
1191 int max_index;
1192};
1193
1194#endif /*LSI_MEGARAID_SAS_H */
Linux kernel - Deliverables
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