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megaraid_sas : Use Block layer tag support for internal command indexing
[deliverable/linux.git] / drivers / scsi / megaraid / megaraid_sas.h
CommitLineData
c4a3e0a5 1/*
3f1530c1 2 * Linux MegaRAID driver for SAS based RAID controllers
c4a3e0a5 3 *
e399065b
SS		 4 * Copyright (c) 2003-2013 LSI Corporation
5 * Copyright (c) 2013-2014 Avago Technologies
c4a3e0a5 6 *
3f1530c1 7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
c4a3e0a5 11 *
3f1530c1 12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
c4a3e0a5 16 *
3f1530c1 17 * You should have received a copy of the GNU General Public License
e399065b 18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
3f1530c1 19 *
20 * FILE: megaraid_sas.h
21 *
e399065b
SS		 22 * Authors: Avago Technologies
23 * Kashyap Desai <kashyap.desai@avagotech.com>
24 * Sumit Saxena <sumit.saxena@avagotech.com>
3f1530c1 25 *
e399065b 26 * Send feedback to: megaraidlinux.pdl@avagotech.com
3f1530c1 27 *
e399065b
SS		 28 * Mail to: Avago Technologies, 350 West Trimble Road, Building 90,
29 * San Jose, California 95131
c4a3e0a5
BS		 30 */
31
32#ifndef LSI_MEGARAID_SAS_H
33#define LSI_MEGARAID_SAS_H
34
a69b74d3 35/*
c4a3e0a5
BS		 36 * MegaRAID SAS Driver meta data
37 */
0128d5cf 38#define MEGASAS_VERSION "06.806.08.00-rc1"
0e98936c
SP		 39
40/*
41 * Device IDs
42 */
43#define PCI_DEVICE_ID_LSI_SAS1078R 0x0060
af7a5647 44#define PCI_DEVICE_ID_LSI_SAS1078DE 0x007C
0e98936c 45#define PCI_DEVICE_ID_LSI_VERDE_ZCR 0x0413
6610a6b3
YB		 46#define PCI_DEVICE_ID_LSI_SAS1078GEN2 0x0078
47#define PCI_DEVICE_ID_LSI_SAS0079GEN2 0x0079
87911122
YB		 48#define PCI_DEVICE_ID_LSI_SAS0073SKINNY 0x0073
49#define PCI_DEVICE_ID_LSI_SAS0071SKINNY 0x0071
9c915a8c 50#define PCI_DEVICE_ID_LSI_FUSION 0x005b
229fe47c 51#define PCI_DEVICE_ID_LSI_PLASMA 0x002f
36807e67 52#define PCI_DEVICE_ID_LSI_INVADER 0x005d
21d3c710 53#define PCI_DEVICE_ID_LSI_FURY 0x005f
0e98936c 54
39b72c3c
SS		 55/*
56 * Intel HBA SSDIDs
57 */
58#define MEGARAID_INTEL_RS3DC080_SSDID 0x9360
59#define MEGARAID_INTEL_RS3DC040_SSDID 0x9362
60#define MEGARAID_INTEL_RS3SC008_SSDID 0x9380
61#define MEGARAID_INTEL_RS3MC044_SSDID 0x9381
62#define MEGARAID_INTEL_RS3WC080_SSDID 0x9341
63#define MEGARAID_INTEL_RS3WC040_SSDID 0x9343
64
65/*
66 * Intel HBA branding
67 */
68#define MEGARAID_INTEL_RS3DC080_BRANDING \
69 "Intel(R) RAID Controller RS3DC080"
70#define MEGARAID_INTEL_RS3DC040_BRANDING \
71 "Intel(R) RAID Controller RS3DC040"
72#define MEGARAID_INTEL_RS3SC008_BRANDING \
73 "Intel(R) RAID Controller RS3SC008"
74#define MEGARAID_INTEL_RS3MC044_BRANDING \
75 "Intel(R) RAID Controller RS3MC044"
76#define MEGARAID_INTEL_RS3WC080_BRANDING \
77 "Intel(R) RAID Controller RS3WC080"
78#define MEGARAID_INTEL_RS3WC040_BRANDING \
79 "Intel(R) RAID Controller RS3WC040"
80
c4a3e0a5
BS		 81/*
82 * =====================================
83 * MegaRAID SAS MFI firmware definitions
84 * =====================================
85 */
86
87/*
88 * MFI stands for MegaRAID SAS FW Interface. This is just a moniker for
89 * protocol between the software and firmware. Commands are issued using
90 * "message frames"
91 */
92
a69b74d3 93/*
c4a3e0a5
BS		 94 * FW posts its state in upper 4 bits of outbound_msg_0 register
95 */
96#define MFI_STATE_MASK 0xF0000000
97#define MFI_STATE_UNDEFINED 0x00000000
98#define MFI_STATE_BB_INIT 0x10000000
99#define MFI_STATE_FW_INIT 0x40000000
100#define MFI_STATE_WAIT_HANDSHAKE 0x60000000
101#define MFI_STATE_FW_INIT_2 0x70000000
102#define MFI_STATE_DEVICE_SCAN 0x80000000
e3bbff9f 103#define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000
c4a3e0a5
BS		 104#define MFI_STATE_FLUSH_CACHE 0xA0000000
105#define MFI_STATE_READY 0xB0000000
106#define MFI_STATE_OPERATIONAL 0xC0000000
107#define MFI_STATE_FAULT 0xF0000000
fc62b3fc
SS		 108#define MFI_STATE_FORCE_OCR 0x00000080
109#define MFI_STATE_DMADONE 0x00000008
110#define MFI_STATE_CRASH_DUMP_DONE 0x00000004
7e70e733 111#define MFI_RESET_REQUIRED 0x00000001
112#define MFI_RESET_ADAPTER 0x00000002
c4a3e0a5
BS		 113#define MEGAMFI_FRAME_SIZE 64
114
a69b74d3 115/*
c4a3e0a5
BS		 116 * During FW init, clear pending cmds & reset state using inbound_msg_0
117 *
118 * ABORT : Abort all pending cmds
119 * READY : Move from OPERATIONAL to READY state; discard queue info
120 * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??)
121 * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver
e3bbff9f
SP		 122 * HOTPLUG : Resume from Hotplug
123 * MFI_STOP_ADP : Send signal to FW to stop processing
c4a3e0a5 124 */
39a98554 125#define WRITE_SEQUENCE_OFFSET (0x0000000FC) /* I20 */
126#define HOST_DIAGNOSTIC_OFFSET (0x000000F8) /* I20 */
127#define DIAG_WRITE_ENABLE (0x00000080)
128#define DIAG_RESET_ADAPTER (0x00000004)
129
130#define MFI_ADP_RESET 0x00000040
e3bbff9f 131#define MFI_INIT_ABORT 0x00000001
c4a3e0a5
BS		 132#define MFI_INIT_READY 0x00000002
133#define MFI_INIT_MFIMODE 0x00000004
134#define MFI_INIT_CLEAR_HANDSHAKE 0x00000008
e3bbff9f
SP		 135#define MFI_INIT_HOTPLUG 0x00000010
136#define MFI_STOP_ADP 0x00000020
137#define MFI_RESET_FLAGS MFI_INIT_READY| \
138 MFI_INIT_MFIMODE| \
139 MFI_INIT_ABORT
c4a3e0a5 140
a69b74d3 141/*
c4a3e0a5
BS		 142 * MFI frame flags
143 */
144#define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000
145#define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001
146#define MFI_FRAME_SGL32 0x0000
147#define MFI_FRAME_SGL64 0x0002
148#define MFI_FRAME_SENSE32 0x0000
149#define MFI_FRAME_SENSE64 0x0004
150#define MFI_FRAME_DIR_NONE 0x0000
151#define MFI_FRAME_DIR_WRITE 0x0008
152#define MFI_FRAME_DIR_READ 0x0010
153#define MFI_FRAME_DIR_BOTH 0x0018
f4c9a131 154#define MFI_FRAME_IEEE 0x0020
c4a3e0a5 155
4026e9aa
SS		 156/* Driver internal */
157#define DRV_DCMD_POLLED_MODE 0x1
158
a69b74d3 159/*
c4a3e0a5
BS		 160 * Definition for cmd_status
161 */
162#define MFI_CMD_STATUS_POLL_MODE 0xFF
163
a69b74d3 164/*
c4a3e0a5
BS		 165 * MFI command opcodes
166 */
167#define MFI_CMD_INIT 0x00
168#define MFI_CMD_LD_READ 0x01
169#define MFI_CMD_LD_WRITE 0x02
170#define MFI_CMD_LD_SCSI_IO 0x03
171#define MFI_CMD_PD_SCSI_IO 0x04
172#define MFI_CMD_DCMD 0x05
173#define MFI_CMD_ABORT 0x06
174#define MFI_CMD_SMP 0x07
175#define MFI_CMD_STP 0x08
e5f93a36 176#define MFI_CMD_INVALID 0xff
c4a3e0a5
BS		 177
178#define MR_DCMD_CTRL_GET_INFO 0x01010000
bdc6fb8d 179#define MR_DCMD_LD_GET_LIST 0x03010000
21c9e160 180#define MR_DCMD_LD_LIST_QUERY 0x03010100
c4a3e0a5
BS		 181
182#define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000
183#define MR_FLUSH_CTRL_CACHE 0x01
184#define MR_FLUSH_DISK_CACHE 0x02
185
186#define MR_DCMD_CTRL_SHUTDOWN 0x01050000
31ea7088 187#define MR_DCMD_HIBERNATE_SHUTDOWN 0x01060000
c4a3e0a5
BS		 188#define MR_ENABLE_DRIVE_SPINDOWN 0x01
189
190#define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100
191#define MR_DCMD_CTRL_EVENT_GET 0x01040300
192#define MR_DCMD_CTRL_EVENT_WAIT 0x01040500
193#define MR_DCMD_LD_GET_PROPERTIES 0x03030000
194
195#define MR_DCMD_CLUSTER 0x08000000
196#define MR_DCMD_CLUSTER_RESET_ALL 0x08010100
197#define MR_DCMD_CLUSTER_RESET_LD 0x08010200
81e403ce 198#define MR_DCMD_PD_LIST_QUERY 0x02010100
c4a3e0a5 199
fc62b3fc
SS		 200#define MR_DCMD_CTRL_SET_CRASH_DUMP_PARAMS 0x01190100
201#define MR_DRIVER_SET_APP_CRASHDUMP_MODE (0xF0010000 | 0x0600)
202
bc93d425
SS		 203/*
204 * Global functions
205 */
206extern u8 MR_ValidateMapInfo(struct megasas_instance *instance);
207
208
a69b74d3 209/*
c4a3e0a5
BS		 210 * MFI command completion codes
211 */
212enum MFI_STAT {
213 MFI_STAT_OK = 0x00,
214 MFI_STAT_INVALID_CMD = 0x01,
215 MFI_STAT_INVALID_DCMD = 0x02,
216 MFI_STAT_INVALID_PARAMETER = 0x03,
217 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04,
218 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05,
219 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06,
220 MFI_STAT_APP_IN_USE = 0x07,
221 MFI_STAT_APP_NOT_INITIALIZED = 0x08,
222 MFI_STAT_ARRAY_INDEX_INVALID = 0x09,
223 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a,
224 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b,
225 MFI_STAT_DEVICE_NOT_FOUND = 0x0c,
226 MFI_STAT_DRIVE_TOO_SMALL = 0x0d,
227 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e,
228 MFI_STAT_FLASH_BUSY = 0x0f,
229 MFI_STAT_FLASH_ERROR = 0x10,
230 MFI_STAT_FLASH_IMAGE_BAD = 0x11,
231 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12,
232 MFI_STAT_FLASH_NOT_OPEN = 0x13,
233 MFI_STAT_FLASH_NOT_STARTED = 0x14,
234 MFI_STAT_FLUSH_FAILED = 0x15,
235 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16,
236 MFI_STAT_LD_CC_IN_PROGRESS = 0x17,
237 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18,
238 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19,
239 MFI_STAT_LD_MAX_CONFIGURED = 0x1a,
240 MFI_STAT_LD_NOT_OPTIMAL = 0x1b,
241 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c,
242 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d,
243 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e,
244 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f,
245 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
246 MFI_STAT_MFC_HW_ERROR = 0x21,
247 MFI_STAT_NO_HW_PRESENT = 0x22,
248 MFI_STAT_NOT_FOUND = 0x23,
249 MFI_STAT_NOT_IN_ENCL = 0x24,
250 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25,
251 MFI_STAT_PD_TYPE_WRONG = 0x26,
252 MFI_STAT_PR_DISABLED = 0x27,
253 MFI_STAT_ROW_INDEX_INVALID = 0x28,
254 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29,
255 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a,
256 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b,
257 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c,
258 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d,
259 MFI_STAT_SCSI_IO_FAILED = 0x2e,
260 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f,
261 MFI_STAT_SHUTDOWN_FAILED = 0x30,
262 MFI_STAT_TIME_NOT_SET = 0x31,
263 MFI_STAT_WRONG_STATE = 0x32,
264 MFI_STAT_LD_OFFLINE = 0x33,
265 MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34,
266 MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35,
267 MFI_STAT_RESERVATION_IN_PROGRESS = 0x36,
268 MFI_STAT_I2C_ERRORS_DETECTED = 0x37,
269 MFI_STAT_PCI_ERRORS_DETECTED = 0x38,
36807e67 270 MFI_STAT_CONFIG_SEQ_MISMATCH = 0x67,
c4a3e0a5
BS		 271
272 MFI_STAT_INVALID_STATUS = 0xFF
273};
274
fc62b3fc
SS		 275/*
276 * Crash dump related defines
277 */
278#define MAX_CRASH_DUMP_SIZE 512
279#define CRASH_DMA_BUF_SIZE (1024 * 1024)
280
281enum MR_FW_CRASH_DUMP_STATE {
282 UNAVAILABLE = 0,
283 AVAILABLE = 1,
284 COPYING = 2,
285 COPIED = 3,
286 COPY_ERROR = 4,
287};
288
289enum _MR_CRASH_BUF_STATUS {
290 MR_CRASH_BUF_TURN_OFF = 0,
291 MR_CRASH_BUF_TURN_ON = 1,
292};
293
c4a3e0a5
BS		 294/*
295 * Number of mailbox bytes in DCMD message frame
296 */
297#define MFI_MBOX_SIZE 12
298
299enum MR_EVT_CLASS {
300
301 MR_EVT_CLASS_DEBUG = -2,
302 MR_EVT_CLASS_PROGRESS = -1,
303 MR_EVT_CLASS_INFO = 0,
304 MR_EVT_CLASS_WARNING = 1,
305 MR_EVT_CLASS_CRITICAL = 2,
306 MR_EVT_CLASS_FATAL = 3,
307 MR_EVT_CLASS_DEAD = 4,
308
309};
310
311enum MR_EVT_LOCALE {
312
313 MR_EVT_LOCALE_LD = 0x0001,
314 MR_EVT_LOCALE_PD = 0x0002,
315 MR_EVT_LOCALE_ENCL = 0x0004,
316 MR_EVT_LOCALE_BBU = 0x0008,
317 MR_EVT_LOCALE_SAS = 0x0010,
318 MR_EVT_LOCALE_CTRL = 0x0020,
319 MR_EVT_LOCALE_CONFIG = 0x0040,
320 MR_EVT_LOCALE_CLUSTER = 0x0080,
321 MR_EVT_LOCALE_ALL = 0xffff,
322
323};
324
325enum MR_EVT_ARGS {
326
327 MR_EVT_ARGS_NONE,
328 MR_EVT_ARGS_CDB_SENSE,
329 MR_EVT_ARGS_LD,
330 MR_EVT_ARGS_LD_COUNT,
331 MR_EVT_ARGS_LD_LBA,
332 MR_EVT_ARGS_LD_OWNER,
333 MR_EVT_ARGS_LD_LBA_PD_LBA,
334 MR_EVT_ARGS_LD_PROG,
335 MR_EVT_ARGS_LD_STATE,
336 MR_EVT_ARGS_LD_STRIP,
337 MR_EVT_ARGS_PD,
338 MR_EVT_ARGS_PD_ERR,
339 MR_EVT_ARGS_PD_LBA,
340 MR_EVT_ARGS_PD_LBA_LD,
341 MR_EVT_ARGS_PD_PROG,
342 MR_EVT_ARGS_PD_STATE,
343 MR_EVT_ARGS_PCI,
344 MR_EVT_ARGS_RATE,
345 MR_EVT_ARGS_STR,
346 MR_EVT_ARGS_TIME,
347 MR_EVT_ARGS_ECC,
81e403ce
YB		 348 MR_EVT_ARGS_LD_PROP,
349 MR_EVT_ARGS_PD_SPARE,
350 MR_EVT_ARGS_PD_INDEX,
351 MR_EVT_ARGS_DIAG_PASS,
352 MR_EVT_ARGS_DIAG_FAIL,
353 MR_EVT_ARGS_PD_LBA_LBA,
354 MR_EVT_ARGS_PORT_PHY,
355 MR_EVT_ARGS_PD_MISSING,
356 MR_EVT_ARGS_PD_ADDRESS,
357 MR_EVT_ARGS_BITMAP,
358 MR_EVT_ARGS_CONNECTOR,
359 MR_EVT_ARGS_PD_PD,
360 MR_EVT_ARGS_PD_FRU,
361 MR_EVT_ARGS_PD_PATHINFO,
362 MR_EVT_ARGS_PD_POWER_STATE,
363 MR_EVT_ARGS_GENERIC,
364};
c4a3e0a5 365
81e403ce
YB		 366/*
367 * define constants for device list query options
368 */
369enum MR_PD_QUERY_TYPE {
370 MR_PD_QUERY_TYPE_ALL = 0,
371 MR_PD_QUERY_TYPE_STATE = 1,
372 MR_PD_QUERY_TYPE_POWER_STATE = 2,
373 MR_PD_QUERY_TYPE_MEDIA_TYPE = 3,
374 MR_PD_QUERY_TYPE_SPEED = 4,
375 MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5,
c4a3e0a5
BS		 376};
377
21c9e160 378enum MR_LD_QUERY_TYPE {
379 MR_LD_QUERY_TYPE_ALL = 0,
380 MR_LD_QUERY_TYPE_EXPOSED_TO_HOST = 1,
381 MR_LD_QUERY_TYPE_USED_TGT_IDS = 2,
382 MR_LD_QUERY_TYPE_CLUSTER_ACCESS = 3,
383 MR_LD_QUERY_TYPE_CLUSTER_LOCALE = 4,
384};
385
386
7e8a75f4
YB		 387#define MR_EVT_CFG_CLEARED 0x0004
388#define MR_EVT_LD_STATE_CHANGE 0x0051
389#define MR_EVT_PD_INSERTED 0x005b
390#define MR_EVT_PD_REMOVED 0x0070
391#define MR_EVT_LD_CREATED 0x008a
392#define MR_EVT_LD_DELETED 0x008b
393#define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db
394#define MR_EVT_LD_OFFLINE 0x00fc
395#define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152
7e8a75f4 396
81e403ce
YB		 397enum MR_PD_STATE {
398 MR_PD_STATE_UNCONFIGURED_GOOD = 0x00,
399 MR_PD_STATE_UNCONFIGURED_BAD = 0x01,
400 MR_PD_STATE_HOT_SPARE = 0x02,
401 MR_PD_STATE_OFFLINE = 0x10,
402 MR_PD_STATE_FAILED = 0x11,
403 MR_PD_STATE_REBUILD = 0x14,
404 MR_PD_STATE_ONLINE = 0x18,
405 MR_PD_STATE_COPYBACK = 0x20,
406 MR_PD_STATE_SYSTEM = 0x40,
407 };
408
409
410 /*
411 * defines the physical drive address structure
412 */
413struct MR_PD_ADDRESS {
414 u16 deviceId;
415 u16 enclDeviceId;
416
417 union {
418 struct {
419 u8 enclIndex;
420 u8 slotNumber;
421 } mrPdAddress;
422 struct {
423 u8 enclPosition;
424 u8 enclConnectorIndex;
425 } mrEnclAddress;
426 };
427 u8 scsiDevType;
428 union {
429 u8 connectedPortBitmap;
430 u8 connectedPortNumbers;
431 };
432 u64 sasAddr[2];
433} __packed;
434
435/*
436 * defines the physical drive list structure
437 */
438struct MR_PD_LIST {
439 u32 size;
440 u32 count;
441 struct MR_PD_ADDRESS addr[1];
442} __packed;
443
444struct megasas_pd_list {
445 u16 tid;
446 u8 driveType;
447 u8 driveState;
448} __packed;
449
bdc6fb8d
YB		 450 /*
451 * defines the logical drive reference structure
452 */
453union MR_LD_REF {
454 struct {
455 u8 targetId;
456 u8 reserved;
457 u16 seqNum;
458 };
459 u32 ref;
460} __packed;
461
462/*
463 * defines the logical drive list structure
464 */
465struct MR_LD_LIST {
466 u32 ldCount;
467 u32 reserved;
468 struct {
469 union MR_LD_REF ref;
470 u8 state;
471 u8 reserved[3];
472 u64 size;
51087a86 473 } ldList[MAX_LOGICAL_DRIVES_EXT];
bdc6fb8d
YB		 474} __packed;
475
21c9e160 476struct MR_LD_TARGETID_LIST {
477 u32 size;
478 u32 count;
479 u8 pad[3];
51087a86 480 u8 targetId[MAX_LOGICAL_DRIVES_EXT];
21c9e160 481};
482
483
c4a3e0a5
BS		 484/*
485 * SAS controller properties
486 */
487struct megasas_ctrl_prop {
488
489 u16 seq_num;
490 u16 pred_fail_poll_interval;
491 u16 intr_throttle_count;
492 u16 intr_throttle_timeouts;
493 u8 rebuild_rate;
494 u8 patrol_read_rate;
495 u8 bgi_rate;
496 u8 cc_rate;
497 u8 recon_rate;
498 u8 cache_flush_interval;
499 u8 spinup_drv_count;
500 u8 spinup_delay;
501 u8 cluster_enable;
502 u8 coercion_mode;
503 u8 alarm_enable;
504 u8 disable_auto_rebuild;
505 u8 disable_battery_warn;
506 u8 ecc_bucket_size;
507 u16 ecc_bucket_leak_rate;
508 u8 restore_hotspare_on_insertion;
509 u8 expose_encl_devices;
39a98554 510 u8 maintainPdFailHistory;
511 u8 disallowHostRequestReordering;
512 u8 abortCCOnError;
513 u8 loadBalanceMode;
514 u8 disableAutoDetectBackplane;
515
516 u8 snapVDSpace;
517
518 /*
519 * Add properties that can be controlled by
520 * a bit in the following structure.
521 */
39a98554 522 struct {
94cd65dd
SS		 523#if defined(__BIG_ENDIAN_BITFIELD)
524 u32 reserved:18;
525 u32 enableJBOD:1;
526 u32 disableSpinDownHS:1;
527 u32 allowBootWithPinnedCache:1;
528 u32 disableOnlineCtrlReset:1;
529 u32 enableSecretKeyControl:1;
530 u32 autoEnhancedImport:1;
531 u32 enableSpinDownUnconfigured:1;
532 u32 SSDPatrolReadEnabled:1;
533 u32 SSDSMARTerEnabled:1;
534 u32 disableNCQ:1;
535 u32 useFdeOnly:1;
536 u32 prCorrectUnconfiguredAreas:1;
537 u32 SMARTerEnabled:1;
538 u32 copyBackDisabled:1;
539#else
540 u32 copyBackDisabled:1;
541 u32 SMARTerEnabled:1;
542 u32 prCorrectUnconfiguredAreas:1;
543 u32 useFdeOnly:1;
544 u32 disableNCQ:1;
545 u32 SSDSMARTerEnabled:1;
546 u32 SSDPatrolReadEnabled:1;
547 u32 enableSpinDownUnconfigured:1;
548 u32 autoEnhancedImport:1;
549 u32 enableSecretKeyControl:1;
550 u32 disableOnlineCtrlReset:1;
551 u32 allowBootWithPinnedCache:1;
552 u32 disableSpinDownHS:1;
553 u32 enableJBOD:1;
554 u32 reserved:18;
555#endif
39a98554 556 } OnOffProperties;
557 u8 autoSnapVDSpace;
558 u8 viewSpace;
559 u16 spinDownTime;
560 u8 reserved[24];
81e403ce 561} __packed;
c4a3e0a5
BS		 562
563/*
564 * SAS controller information
565 */
566struct megasas_ctrl_info {
567
568 /*
569 * PCI device information
570 */
571 struct {
572
573 u16 vendor_id;
574 u16 device_id;
575 u16 sub_vendor_id;
576 u16 sub_device_id;
577 u8 reserved[24];
578
579 } __attribute__ ((packed)) pci;
580
581 /*
582 * Host interface information
583 */
584 struct {
585
586 u8 PCIX:1;
587 u8 PCIE:1;
588 u8 iSCSI:1;
589 u8 SAS_3G:1;
229fe47c 590 u8 SRIOV:1;
591 u8 reserved_0:3;
c4a3e0a5
BS		 592 u8 reserved_1[6];
593 u8 port_count;
594 u64 port_addr[8];
595
596 } __attribute__ ((packed)) host_interface;
597
598 /*
599 * Device (backend) interface information
600 */
601 struct {
602
603 u8 SPI:1;
604 u8 SAS_3G:1;
605 u8 SATA_1_5G:1;
606 u8 SATA_3G:1;
607 u8 reserved_0:4;
608 u8 reserved_1[6];
609 u8 port_count;
610 u64 port_addr[8];
611
612 } __attribute__ ((packed)) device_interface;
613
614 /*
615 * List of components residing in flash. All str are null terminated
616 */
617 u32 image_check_word;
618 u32 image_component_count;
619
620 struct {
621
622 char name[8];
623 char version[32];
624 char build_date[16];
625 char built_time[16];
626
627 } __attribute__ ((packed)) image_component[8];
628
629 /*
630 * List of flash components that have been flashed on the card, but
631 * are not in use, pending reset of the adapter. This list will be
632 * empty if a flash operation has not occurred. All stings are null
633 * terminated
634 */
635 u32 pending_image_component_count;
636
637 struct {
638
639 char name[8];
640 char version[32];
641 char build_date[16];
642 char build_time[16];
643
644 } __attribute__ ((packed)) pending_image_component[8];
645
646 u8 max_arms;
647 u8 max_spans;
648 u8 max_arrays;
649 u8 max_lds;
650
651 char product_name[80];
652 char serial_no[32];
653
654 /*
655 * Other physical/controller/operation information. Indicates the
656 * presence of the hardware
657 */
658 struct {
659
660 u32 bbu:1;
661 u32 alarm:1;
662 u32 nvram:1;
663 u32 uart:1;
664 u32 reserved:28;
665
666 } __attribute__ ((packed)) hw_present;
667
668 u32 current_fw_time;
669
670 /*
671 * Maximum data transfer sizes
672 */
673 u16 max_concurrent_cmds;
674 u16 max_sge_count;
675 u32 max_request_size;
676
677 /*
678 * Logical and physical device counts
679 */
680 u16 ld_present_count;
681 u16 ld_degraded_count;
682 u16 ld_offline_count;
683
684 u16 pd_present_count;
685 u16 pd_disk_present_count;
686 u16 pd_disk_pred_failure_count;
687 u16 pd_disk_failed_count;
688
689 /*
690 * Memory size information
691 */
692 u16 nvram_size;
693 u16 memory_size;
694 u16 flash_size;
695
696 /*
697 * Error counters
698 */
699 u16 mem_correctable_error_count;
700 u16 mem_uncorrectable_error_count;
701
702 /*
703 * Cluster information
704 */
705 u8 cluster_permitted;
706 u8 cluster_active;
707
708 /*
709 * Additional max data transfer sizes
710 */
711 u16 max_strips_per_io;
712
713 /*
714 * Controller capabilities structures
715 */
716 struct {
717
718 u32 raid_level_0:1;
719 u32 raid_level_1:1;
720 u32 raid_level_5:1;
721 u32 raid_level_1E:1;
722 u32 raid_level_6:1;
723 u32 reserved:27;
724
725 } __attribute__ ((packed)) raid_levels;
726
727 struct {
728
729 u32 rbld_rate:1;
730 u32 cc_rate:1;
731 u32 bgi_rate:1;
732 u32 recon_rate:1;
733 u32 patrol_rate:1;
734 u32 alarm_control:1;
735 u32 cluster_supported:1;
736 u32 bbu:1;
737 u32 spanning_allowed:1;
738 u32 dedicated_hotspares:1;
739 u32 revertible_hotspares:1;
740 u32 foreign_config_import:1;
741 u32 self_diagnostic:1;
742 u32 mixed_redundancy_arr:1;
743 u32 global_hot_spares:1;
744 u32 reserved:17;
745
746 } __attribute__ ((packed)) adapter_operations;
747
748 struct {
749
750 u32 read_policy:1;
751 u32 write_policy:1;
752 u32 io_policy:1;
753 u32 access_policy:1;
754 u32 disk_cache_policy:1;
755 u32 reserved:27;
756
757 } __attribute__ ((packed)) ld_operations;
758
759 struct {
760
761 u8 min;
762 u8 max;
763 u8 reserved[2];
764
765 } __attribute__ ((packed)) stripe_sz_ops;
766
767 struct {
768
769 u32 force_online:1;
770 u32 force_offline:1;
771 u32 force_rebuild:1;
772 u32 reserved:29;
773
774 } __attribute__ ((packed)) pd_operations;
775
776 struct {
777
778 u32 ctrl_supports_sas:1;
779 u32 ctrl_supports_sata:1;
780 u32 allow_mix_in_encl:1;
781 u32 allow_mix_in_ld:1;
782 u32 allow_sata_in_cluster:1;
783 u32 reserved:27;
784
785 } __attribute__ ((packed)) pd_mix_support;
786
787 /*
788 * Define ECC single-bit-error bucket information
789 */
790 u8 ecc_bucket_count;
791 u8 reserved_2[11];
792
793 /*
794 * Include the controller properties (changeable items)
795 */
796 struct megasas_ctrl_prop properties;
797
798 /*
799 * Define FW pkg version (set in envt v'bles on OEM basis)
800 */
801 char package_version[0x60];
802
c4a3e0a5 803
bc93d425
SS		 804 /*
805 * If adapterOperations.supportMoreThan8Phys is set,
806 * and deviceInterface.portCount is greater than 8,
807 * SAS Addrs for first 8 ports shall be populated in
808 * deviceInterface.portAddr, and the rest shall be
809 * populated in deviceInterfacePortAddr2.
810 */
811 u64 deviceInterfacePortAddr2[8]; /*6a0h */
812 u8 reserved3[128]; /*6e0h */
813
814 struct { /*760h */
815 u16 minPdRaidLevel_0:4;
816 u16 maxPdRaidLevel_0:12;
817
818 u16 minPdRaidLevel_1:4;
819 u16 maxPdRaidLevel_1:12;
820
821 u16 minPdRaidLevel_5:4;
822 u16 maxPdRaidLevel_5:12;
823
824 u16 minPdRaidLevel_1E:4;
825 u16 maxPdRaidLevel_1E:12;
826
827 u16 minPdRaidLevel_6:4;
828 u16 maxPdRaidLevel_6:12;
829
830 u16 minPdRaidLevel_10:4;
831 u16 maxPdRaidLevel_10:12;
832
833 u16 minPdRaidLevel_50:4;
834 u16 maxPdRaidLevel_50:12;
835
836 u16 minPdRaidLevel_60:4;
837 u16 maxPdRaidLevel_60:12;
838
839 u16 minPdRaidLevel_1E_RLQ0:4;
840 u16 maxPdRaidLevel_1E_RLQ0:12;
841
842 u16 minPdRaidLevel_1E0_RLQ0:4;
843 u16 maxPdRaidLevel_1E0_RLQ0:12;
844
845 u16 reserved[6];
846 } pdsForRaidLevels;
847
848 u16 maxPds; /*780h */
849 u16 maxDedHSPs; /*782h */
850 u16 maxGlobalHSPs; /*784h */
851 u16 ddfSize; /*786h */
852 u8 maxLdsPerArray; /*788h */
853 u8 partitionsInDDF; /*789h */
854 u8 lockKeyBinding; /*78ah */
855 u8 maxPITsPerLd; /*78bh */
856 u8 maxViewsPerLd; /*78ch */
857 u8 maxTargetId; /*78dh */
858 u16 maxBvlVdSize; /*78eh */
859
860 u16 maxConfigurableSSCSize; /*790h */
861 u16 currentSSCsize; /*792h */
862
863 char expanderFwVersion[12]; /*794h */
864
865 u16 PFKTrialTimeRemaining; /*7A0h */
866
867 u16 cacheMemorySize; /*7A2h */
868
869 struct { /*7A4h */
94cd65dd 870#if defined(__BIG_ENDIAN_BITFIELD)
229fe47c 871 u32 reserved:5;
872 u32 activePassive:2;
873 u32 supportConfigAutoBalance:1;
874 u32 mpio:1;
875 u32 supportDataLDonSSCArray:1;
876 u32 supportPointInTimeProgress:1;
94cd65dd
SS		 877 u32 supportUnevenSpans:1;
878 u32 dedicatedHotSparesLimited:1;
879 u32 headlessMode:1;
880 u32 supportEmulatedDrives:1;
881 u32 supportResetNow:1;
882 u32 realTimeScheduler:1;
883 u32 supportSSDPatrolRead:1;
884 u32 supportPerfTuning:1;
885 u32 disableOnlinePFKChange:1;
886 u32 supportJBOD:1;
887 u32 supportBootTimePFKChange:1;
888 u32 supportSetLinkSpeed:1;
889 u32 supportEmergencySpares:1;
890 u32 supportSuspendResumeBGops:1;
891 u32 blockSSDWriteCacheChange:1;
892 u32 supportShieldState:1;
893 u32 supportLdBBMInfo:1;
894 u32 supportLdPIType3:1;
895 u32 supportLdPIType2:1;
896 u32 supportLdPIType1:1;
897 u32 supportPIcontroller:1;
898#else
bc93d425
SS		 899 u32 supportPIcontroller:1;
900 u32 supportLdPIType1:1;
901 u32 supportLdPIType2:1;
902 u32 supportLdPIType3:1;
903 u32 supportLdBBMInfo:1;
904 u32 supportShieldState:1;
905 u32 blockSSDWriteCacheChange:1;
906 u32 supportSuspendResumeBGops:1;
907 u32 supportEmergencySpares:1;
908 u32 supportSetLinkSpeed:1;
909 u32 supportBootTimePFKChange:1;
910 u32 supportJBOD:1;
911 u32 disableOnlinePFKChange:1;
912 u32 supportPerfTuning:1;
913 u32 supportSSDPatrolRead:1;
914 u32 realTimeScheduler:1;
915
916 u32 supportResetNow:1;
917 u32 supportEmulatedDrives:1;
918 u32 headlessMode:1;
919 u32 dedicatedHotSparesLimited:1;
920
921
922 u32 supportUnevenSpans:1;
229fe47c 923 u32 supportPointInTimeProgress:1;
924 u32 supportDataLDonSSCArray:1;
925 u32 mpio:1;
926 u32 supportConfigAutoBalance:1;
927 u32 activePassive:2;
928 u32 reserved:5;
94cd65dd 929#endif
bc93d425
SS		 930 } adapterOperations2;
931
932 u8 driverVersion[32]; /*7A8h */
933 u8 maxDAPdCountSpinup60; /*7C8h */
934 u8 temperatureROC; /*7C9h */
935 u8 temperatureCtrl; /*7CAh */
936 u8 reserved4; /*7CBh */
937 u16 maxConfigurablePds; /*7CCh */
938
939
940 u8 reserved5[2]; /*0x7CDh */
941
942 /*
943 * HA cluster information
944 */
945 struct {
51087a86
SS		 946#if defined(__BIG_ENDIAN_BITFIELD)
947 u32 reserved:26;
948 u32 premiumFeatureMismatch:1;
949 u32 ctrlPropIncompatible:1;
950 u32 fwVersionMismatch:1;
951 u32 hwIncompatible:1;
952 u32 peerIsIncompatible:1;
953 u32 peerIsPresent:1;
954#else
bc93d425
SS		 955 u32 peerIsPresent:1;
956 u32 peerIsIncompatible:1;
957 u32 hwIncompatible:1;
958 u32 fwVersionMismatch:1;
959 u32 ctrlPropIncompatible:1;
960 u32 premiumFeatureMismatch:1;
961 u32 reserved:26;
51087a86 962#endif
bc93d425
SS		 963 } cluster;
964
965 char clusterId[16]; /*7D4h */
229fe47c 966 struct {
967 u8 maxVFsSupported; /*0x7E4*/
968 u8 numVFsEnabled; /*0x7E5*/
969 u8 requestorId; /*0x7E6 0:PF, 1:VF1, 2:VF2*/
970 u8 reserved; /*0x7E7*/
971 } iov;
bc93d425 972
fc62b3fc
SS		 973 struct {
974#if defined(__BIG_ENDIAN_BITFIELD)
7497cde8
SS		 975 u32 reserved:12;
976 u32 discardCacheDuringLDDelete:1;
977 u32 supportSecurityonJBOD:1;
978 u32 supportCacheBypassModes:1;
979 u32 supportDisableSESMonitoring:1;
980 u32 supportForceFlash:1;
981 u32 supportNVDRAM:1;
982 u32 supportDrvActivityLEDSetting:1;
983 u32 supportAllowedOpsforDrvRemoval:1;
984 u32 supportHOQRebuild:1;
985 u32 supportForceTo512e:1;
986 u32 supportNVCacheErase:1;
987 u32 supportDebugQueue:1;
988 u32 supportSwZone:1;
fc62b3fc 989 u32 supportCrashDump:1;
51087a86
SS		 990 u32 supportMaxExtLDs:1;
991 u32 supportT10RebuildAssist:1;
992 u32 supportDisableImmediateIO:1;
993 u32 supportThermalPollInterval:1;
994 u32 supportPersonalityChange:2;
fc62b3fc 995#else
51087a86
SS		 996 u32 supportPersonalityChange:2;
997 u32 supportThermalPollInterval:1;
998 u32 supportDisableImmediateIO:1;
999 u32 supportT10RebuildAssist:1;
7497cde8
SS		 1000 u32 supportMaxExtLDs:1;
1001 u32 supportCrashDump:1;
1002 u32 supportSwZone:1;
1003 u32 supportDebugQueue:1;
1004 u32 supportNVCacheErase:1;
1005 u32 supportForceTo512e:1;
1006 u32 supportHOQRebuild:1;
1007 u32 supportAllowedOpsforDrvRemoval:1;
1008 u32 supportDrvActivityLEDSetting:1;
1009 u32 supportNVDRAM:1;
1010 u32 supportForceFlash:1;
1011 u32 supportDisableSESMonitoring:1;
1012 u32 supportCacheBypassModes:1;
1013 u32 supportSecurityonJBOD:1;
1014 u32 discardCacheDuringLDDelete:1;
1015 u32 reserved:12;
fc62b3fc
SS		 1016#endif
1017 } adapterOperations3;
1018
1019 u8 pad[0x800-0x7EC];
81e403ce 1020} __packed;
c4a3e0a5
BS		 1021
1022/*
1023 * ===============================
1024 * MegaRAID SAS driver definitions
1025 * ===============================
1026 */
1027#define MEGASAS_MAX_PD_CHANNELS 2
51087a86 1028#define MEGASAS_MAX_LD_CHANNELS 2
c4a3e0a5
BS		 1029#define MEGASAS_MAX_CHANNELS (MEGASAS_MAX_PD_CHANNELS + \
1030 MEGASAS_MAX_LD_CHANNELS)
1031#define MEGASAS_MAX_DEV_PER_CHANNEL 128
1032#define MEGASAS_DEFAULT_INIT_ID -1
1033#define MEGASAS_MAX_LUN 8
6bf579a3 1034#define MEGASAS_DEFAULT_CMD_PER_LUN 256
81e403ce
YB		 1035#define MEGASAS_MAX_PD (MEGASAS_MAX_PD_CHANNELS * \
1036 MEGASAS_MAX_DEV_PER_CHANNEL)
bdc6fb8d
YB		 1037#define MEGASAS_MAX_LD_IDS (MEGASAS_MAX_LD_CHANNELS * \
1038 MEGASAS_MAX_DEV_PER_CHANNEL)
c4a3e0a5 1039
1fd10685 1040#define MEGASAS_MAX_SECTORS (2*1024)
42a8d2b3 1041#define MEGASAS_MAX_SECTORS_IEEE (2*128)
658dcedb
SP		 1042#define MEGASAS_DBG_LVL 1
1043
05e9ebbe
SP		 1044#define MEGASAS_FW_BUSY 1
1045
51087a86
SS		 1046#define VD_EXT_DEBUG 0
1047
90dc9d98 1048
7497cde8
SS		 1049enum MR_SCSI_CMD_TYPE {
1050 READ_WRITE_LDIO = 0,
1051 NON_READ_WRITE_LDIO = 1,
1052 READ_WRITE_SYSPDIO = 2,
1053 NON_READ_WRITE_SYSPDIO = 3,
1054};
1055
d532dbe2 1056/* Frame Type */
1057#define IO_FRAME 0
1058#define PTHRU_FRAME 1
1059
c4a3e0a5
BS		 1060/*
1061 * When SCSI mid-layer calls driver's reset routine, driver waits for
1062 * MEGASAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note
1063 * that the driver cannot _actually_ abort or reset pending commands. While
1064 * it is waiting for the commands to complete, it prints a diagnostic message
1065 * every MEGASAS_RESET_NOTICE_INTERVAL seconds
1066 */
1067#define MEGASAS_RESET_WAIT_TIME 180
2a3681e5 1068#define MEGASAS_INTERNAL_CMD_WAIT_TIME 180
c4a3e0a5 1069#define MEGASAS_RESET_NOTICE_INTERVAL 5
c4a3e0a5 1070#define MEGASAS_IOCTL_CMD 0
05e9ebbe 1071#define MEGASAS_DEFAULT_CMD_TIMEOUT 90
c5daa6a9 1072#define MEGASAS_THROTTLE_QUEUE_DEPTH 16
90dc9d98 1073#define MEGASAS_BLOCKED_CMD_TIMEOUT 60
c4a3e0a5
BS		 1074/*
1075 * FW reports the maximum of number of commands that it can accept (maximum
1076 * commands that can be outstanding) at any time. The driver must report a
1077 * lower number to the mid layer because it can issue a few internal commands
1078 * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs
1079 * is shown below
1080 */
1081#define MEGASAS_INT_CMDS 32
7bebf5c7 1082#define MEGASAS_SKINNY_INT_CMDS 5
ae09a6c1
SS		 1083#define MEGASAS_FUSION_INTERNAL_CMDS 5
1084#define MEGASAS_FUSION_IOCTL_CMDS 3
f26ac3a1 1085#define MEGASAS_MFI_IOCTL_CMDS 27
c4a3e0a5 1086
d46a3ad6 1087#define MEGASAS_MAX_MSIX_QUEUES 128
c4a3e0a5
BS		 1088/*
1089 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit
1090 * SGLs based on the size of dma_addr_t
1091 */
1092#define IS_DMA64 (sizeof(dma_addr_t) == 8)
1093
39a98554 1094#define MFI_XSCALE_OMR0_CHANGE_INTERRUPT 0x00000001
1095
1096#define MFI_INTR_FLAG_REPLY_MESSAGE 0x00000001
1097#define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE 0x00000002
1098#define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT 0x00000004
1099
c4a3e0a5 1100#define MFI_OB_INTR_STATUS_MASK 0x00000002
14faea9f 1101#define MFI_POLL_TIMEOUT_SECS 60
229fe47c 1102#define MEGASAS_SRIOV_HEARTBEAT_INTERVAL_VF (5 * HZ)
1103#define MEGASAS_OCR_SETTLE_TIME_VF (1000 * 30)
1104#define MEGASAS_ROUTINE_WAIT_TIME_VF 300
f9876f0b 1105#define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000
6610a6b3
YB		 1106#define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001
1107#define MFI_GEN2_ENABLE_INTERRUPT_MASK (0x00000001 | 0x00000004)
87911122
YB		 1108#define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000
1109#define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001)
0e98936c 1110
39a98554 1111#define MFI_1068_PCSR_OFFSET 0x84
1112#define MFI_1068_FW_HANDSHAKE_OFFSET 0x64
1113#define MFI_1068_FW_READY 0xDDDD0000
d46a3ad6
SS		 1114
1115#define MR_MAX_REPLY_QUEUES_OFFSET 0X0000001F
1116#define MR_MAX_REPLY_QUEUES_EXT_OFFSET 0X003FC000
1117#define MR_MAX_REPLY_QUEUES_EXT_OFFSET_SHIFT 14
1118#define MR_MAX_MSIX_REG_ARRAY 16
0e98936c
SP		 1119/*
1120* register set for both 1068 and 1078 controllers
1121* structure extended for 1078 registers
1122*/
f9876f0b 1123
c4a3e0a5 1124struct megasas_register_set {
9c915a8c 1125 u32 doorbell; /*0000h*/
1126 u32 fusion_seq_offset; /*0004h*/
1127 u32 fusion_host_diag; /*0008h*/
1128 u32 reserved_01; /*000Ch*/
c4a3e0a5 1129
f9876f0b
SP		 1130 u32 inbound_msg_0; /*0010h*/
1131 u32 inbound_msg_1; /*0014h*/
1132 u32 outbound_msg_0; /*0018h*/
1133 u32 outbound_msg_1; /*001Ch*/
c4a3e0a5 1134
f9876f0b
SP		 1135 u32 inbound_doorbell; /*0020h*/
1136 u32 inbound_intr_status; /*0024h*/
1137 u32 inbound_intr_mask; /*0028h*/
c4a3e0a5 1138
f9876f0b
SP		 1139 u32 outbound_doorbell; /*002Ch*/
1140 u32 outbound_intr_status; /*0030h*/
1141 u32 outbound_intr_mask; /*0034h*/
c4a3e0a5 1142
f9876f0b 1143 u32 reserved_1[2]; /*0038h*/
c4a3e0a5 1144
f9876f0b
SP		 1145 u32 inbound_queue_port; /*0040h*/
1146 u32 outbound_queue_port; /*0044h*/
c4a3e0a5 1147
9c915a8c 1148 u32 reserved_2[9]; /*0048h*/
1149 u32 reply_post_host_index; /*006Ch*/
1150 u32 reserved_2_2[12]; /*0070h*/
c4a3e0a5 1151
f9876f0b 1152 u32 outbound_doorbell_clear; /*00A0h*/
c4a3e0a5 1153
f9876f0b
SP		 1154 u32 reserved_3[3]; /*00A4h*/
1155
1156 u32 outbound_scratch_pad ; /*00B0h*/
9c915a8c 1157 u32 outbound_scratch_pad_2; /*00B4h*/
f9876f0b 1158
9c915a8c 1159 u32 reserved_4[2]; /*00B8h*/
f9876f0b
SP		 1160
1161 u32 inbound_low_queue_port ; /*00C0h*/
1162
1163 u32 inbound_high_queue_port ; /*00C4h*/
1164
1165 u32 reserved_5; /*00C8h*/
39a98554 1166 u32 res_6[11]; /*CCh*/
1167 u32 host_diag;
1168 u32 seq_offset;
1169 u32 index_registers[807]; /*00CCh*/
c4a3e0a5
BS		 1170} __attribute__ ((packed));
1171
1172struct megasas_sge32 {
1173
1174 u32 phys_addr;
1175 u32 length;
1176
1177} __attribute__ ((packed));
1178
1179struct megasas_sge64 {
1180
1181 u64 phys_addr;
1182 u32 length;
1183
1184} __attribute__ ((packed));
1185
f4c9a131
YB		 1186struct megasas_sge_skinny {
1187 u64 phys_addr;
1188 u32 length;
1189 u32 flag;
1190} __packed;
1191
c4a3e0a5
BS		 1192union megasas_sgl {
1193
1194 struct megasas_sge32 sge32[1];
1195 struct megasas_sge64 sge64[1];
f4c9a131 1196 struct megasas_sge_skinny sge_skinny[1];
c4a3e0a5
BS		 1197
1198} __attribute__ ((packed));
1199
1200struct megasas_header {
1201
1202 u8 cmd; /*00h */
1203 u8 sense_len; /*01h */
1204 u8 cmd_status; /*02h */
1205 u8 scsi_status; /*03h */
1206
1207 u8 target_id; /*04h */
1208 u8 lun; /*05h */
1209 u8 cdb_len; /*06h */
1210 u8 sge_count; /*07h */
1211
1212 u32 context; /*08h */
1213 u32 pad_0; /*0Ch */
1214
1215 u16 flags; /*10h */
1216 u16 timeout; /*12h */
1217 u32 data_xferlen; /*14h */
1218
1219} __attribute__ ((packed));
1220
1221union megasas_sgl_frame {
1222
1223 struct megasas_sge32 sge32[8];
1224 struct megasas_sge64 sge64[5];
1225
1226} __attribute__ ((packed));
1227
d46a3ad6
SS		 1228typedef union _MFI_CAPABILITIES {
1229 struct {
94cd65dd 1230#if defined(__BIG_ENDIAN_BITFIELD)
7497cde8
SS		 1231 u32 reserved:25;
1232 u32 security_protocol_cmds_fw:1;
1233 u32 support_core_affinity:1;
d2552ebe 1234 u32 support_ndrive_r1_lb:1;
51087a86 1235 u32 support_max_255lds:1;
7497cde8 1236 u32 support_fastpath_wb:1;
94cd65dd
SS		 1237 u32 support_additional_msix:1;
1238 u32 support_fp_remote_lun:1;
1239#else
d46a3ad6
SS		 1240 u32 support_fp_remote_lun:1;
1241 u32 support_additional_msix:1;
7497cde8 1242 u32 support_fastpath_wb:1;
51087a86 1243 u32 support_max_255lds:1;
d2552ebe 1244 u32 support_ndrive_r1_lb:1;
7497cde8
SS		 1245 u32 support_core_affinity:1;
1246 u32 security_protocol_cmds_fw:1;
1247 u32 reserved:25;
94cd65dd 1248#endif
d46a3ad6
SS		 1249 } mfi_capabilities;
1250 u32 reg;
1251} MFI_CAPABILITIES;
1252
c4a3e0a5
BS		 1253struct megasas_init_frame {
1254
1255 u8 cmd; /*00h */
1256 u8 reserved_0; /*01h */
1257 u8 cmd_status; /*02h */
1258
1259 u8 reserved_1; /*03h */
d46a3ad6 1260 MFI_CAPABILITIES driver_operations; /*04h*/
c4a3e0a5
BS		 1261
1262 u32 context; /*08h */
1263 u32 pad_0; /*0Ch */
1264
1265 u16 flags; /*10h */
1266 u16 reserved_3; /*12h */
1267 u32 data_xfer_len; /*14h */
1268
1269 u32 queue_info_new_phys_addr_lo; /*18h */
1270 u32 queue_info_new_phys_addr_hi; /*1Ch */
1271 u32 queue_info_old_phys_addr_lo; /*20h */
1272 u32 queue_info_old_phys_addr_hi; /*24h */
1273
1274 u32 reserved_4[6]; /*28h */
1275
1276} __attribute__ ((packed));
1277
1278struct megasas_init_queue_info {
1279
1280 u32 init_flags; /*00h */
1281 u32 reply_queue_entries; /*04h */
1282
1283 u32 reply_queue_start_phys_addr_lo; /*08h */
1284 u32 reply_queue_start_phys_addr_hi; /*0Ch */
1285 u32 producer_index_phys_addr_lo; /*10h */
1286 u32 producer_index_phys_addr_hi; /*14h */
1287 u32 consumer_index_phys_addr_lo; /*18h */
1288 u32 consumer_index_phys_addr_hi; /*1Ch */
1289
1290} __attribute__ ((packed));
1291
1292struct megasas_io_frame {
1293
1294 u8 cmd; /*00h */
1295 u8 sense_len; /*01h */
1296 u8 cmd_status; /*02h */
1297 u8 scsi_status; /*03h */
1298
1299 u8 target_id; /*04h */
1300 u8 access_byte; /*05h */
1301 u8 reserved_0; /*06h */
1302 u8 sge_count; /*07h */
1303
1304 u32 context; /*08h */
1305 u32 pad_0; /*0Ch */
1306
1307 u16 flags; /*10h */
1308 u16 timeout; /*12h */
1309 u32 lba_count; /*14h */
1310
1311 u32 sense_buf_phys_addr_lo; /*18h */
1312 u32 sense_buf_phys_addr_hi; /*1Ch */
1313
1314 u32 start_lba_lo; /*20h */
1315 u32 start_lba_hi; /*24h */
1316
1317 union megasas_sgl sgl; /*28h */
1318
1319} __attribute__ ((packed));
1320
1321struct megasas_pthru_frame {
1322
1323 u8 cmd; /*00h */
1324 u8 sense_len; /*01h */
1325 u8 cmd_status; /*02h */
1326 u8 scsi_status; /*03h */
1327
1328 u8 target_id; /*04h */
1329 u8 lun; /*05h */
1330 u8 cdb_len; /*06h */
1331 u8 sge_count; /*07h */
1332
1333 u32 context; /*08h */
1334 u32 pad_0; /*0Ch */
1335
1336 u16 flags; /*10h */
1337 u16 timeout; /*12h */
1338 u32 data_xfer_len; /*14h */
1339
1340 u32 sense_buf_phys_addr_lo; /*18h */
1341 u32 sense_buf_phys_addr_hi; /*1Ch */
1342
1343 u8 cdb[16]; /*20h */
1344 union megasas_sgl sgl; /*30h */
1345
1346} __attribute__ ((packed));
1347
1348struct megasas_dcmd_frame {
1349
1350 u8 cmd; /*00h */
1351 u8 reserved_0; /*01h */
1352 u8 cmd_status; /*02h */
1353 u8 reserved_1[4]; /*03h */
1354 u8 sge_count; /*07h */
1355
1356 u32 context; /*08h */
1357 u32 pad_0; /*0Ch */
1358
1359 u16 flags; /*10h */
1360 u16 timeout; /*12h */
1361
1362 u32 data_xfer_len; /*14h */
1363 u32 opcode; /*18h */
1364
1365 union { /*1Ch */
1366 u8 b[12];
1367 u16 s[6];
1368 u32 w[3];
1369 } mbox;
1370
1371 union megasas_sgl sgl; /*28h */
1372
1373} __attribute__ ((packed));
1374
1375struct megasas_abort_frame {
1376
1377 u8 cmd; /*00h */
1378 u8 reserved_0; /*01h */
1379 u8 cmd_status; /*02h */
1380
1381 u8 reserved_1; /*03h */
1382 u32 reserved_2; /*04h */
1383
1384 u32 context; /*08h */
1385 u32 pad_0; /*0Ch */
1386
1387 u16 flags; /*10h */
1388 u16 reserved_3; /*12h */
1389 u32 reserved_4; /*14h */
1390
1391 u32 abort_context; /*18h */
1392 u32 pad_1; /*1Ch */
1393
1394 u32 abort_mfi_phys_addr_lo; /*20h */
1395 u32 abort_mfi_phys_addr_hi; /*24h */
1396
1397 u32 reserved_5[6]; /*28h */
1398
1399} __attribute__ ((packed));
1400
1401struct megasas_smp_frame {
1402
1403 u8 cmd; /*00h */
1404 u8 reserved_1; /*01h */
1405 u8 cmd_status; /*02h */
1406 u8 connection_status; /*03h */
1407
1408 u8 reserved_2[3]; /*04h */
1409 u8 sge_count; /*07h */
1410
1411 u32 context; /*08h */
1412 u32 pad_0; /*0Ch */
1413
1414 u16 flags; /*10h */
1415 u16 timeout; /*12h */
1416
1417 u32 data_xfer_len; /*14h */
1418 u64 sas_addr; /*18h */
1419
1420 union {
1421 struct megasas_sge32 sge32[2]; /* [0]: resp [1]: req */
1422 struct megasas_sge64 sge64[2]; /* [0]: resp [1]: req */
1423 } sgl;
1424
1425} __attribute__ ((packed));
1426
1427struct megasas_stp_frame {
1428
1429 u8 cmd; /*00h */
1430 u8 reserved_1; /*01h */
1431 u8 cmd_status; /*02h */
1432 u8 reserved_2; /*03h */
1433
1434 u8 target_id; /*04h */
1435 u8 reserved_3[2]; /*05h */
1436 u8 sge_count; /*07h */
1437
1438 u32 context; /*08h */
1439 u32 pad_0; /*0Ch */
1440
1441 u16 flags; /*10h */
1442 u16 timeout; /*12h */
1443
1444 u32 data_xfer_len; /*14h */
1445
1446 u16 fis[10]; /*18h */
1447 u32 stp_flags;
1448
1449 union {
1450 struct megasas_sge32 sge32[2]; /* [0]: resp [1]: data */
1451 struct megasas_sge64 sge64[2]; /* [0]: resp [1]: data */
1452 } sgl;
1453
1454} __attribute__ ((packed));
1455
1456union megasas_frame {
1457
1458 struct megasas_header hdr;
1459 struct megasas_init_frame init;
1460 struct megasas_io_frame io;
1461 struct megasas_pthru_frame pthru;
1462 struct megasas_dcmd_frame dcmd;
1463 struct megasas_abort_frame abort;
1464 struct megasas_smp_frame smp;
1465 struct megasas_stp_frame stp;
1466
1467 u8 raw_bytes[64];
1468};
1469
1470struct megasas_cmd;
1471
1472union megasas_evt_class_locale {
1473
1474 struct {
be26374b 1475#ifndef __BIG_ENDIAN_BITFIELD
c4a3e0a5
BS		 1476 u16 locale;
1477 u8 reserved;
1478 s8 class;
be26374b
SS		 1479#else
1480 s8 class;
1481 u8 reserved;
1482 u16 locale;
1483#endif
c4a3e0a5
BS		 1484 } __attribute__ ((packed)) members;
1485
1486 u32 word;
1487
1488} __attribute__ ((packed));
1489
1490struct megasas_evt_log_info {
1491 u32 newest_seq_num;
1492 u32 oldest_seq_num;
1493 u32 clear_seq_num;
1494 u32 shutdown_seq_num;
1495 u32 boot_seq_num;
1496
1497} __attribute__ ((packed));
1498
1499struct megasas_progress {
1500
1501 u16 progress;
1502 u16 elapsed_seconds;
1503
1504} __attribute__ ((packed));
1505
1506struct megasas_evtarg_ld {
1507
1508 u16 target_id;
1509 u8 ld_index;
1510 u8 reserved;
1511
1512} __attribute__ ((packed));
1513
1514struct megasas_evtarg_pd {
1515 u16 device_id;
1516 u8 encl_index;
1517 u8 slot_number;
1518
1519} __attribute__ ((packed));
1520
1521struct megasas_evt_detail {
1522
1523 u32 seq_num;
1524 u32 time_stamp;
1525 u32 code;
1526 union megasas_evt_class_locale cl;
1527 u8 arg_type;
1528 u8 reserved1[15];
1529
1530 union {
1531 struct {
1532 struct megasas_evtarg_pd pd;
1533 u8 cdb_length;
1534 u8 sense_length;
1535 u8 reserved[2];
1536 u8 cdb[16];
1537 u8 sense[64];
1538 } __attribute__ ((packed)) cdbSense;
1539
1540 struct megasas_evtarg_ld ld;
1541
1542 struct {
1543 struct megasas_evtarg_ld ld;
1544 u64 count;
1545 } __attribute__ ((packed)) ld_count;
1546
1547 struct {
1548 u64 lba;
1549 struct megasas_evtarg_ld ld;
1550 } __attribute__ ((packed)) ld_lba;
1551
1552 struct {
1553 struct megasas_evtarg_ld ld;
1554 u32 prevOwner;
1555 u32 newOwner;
1556 } __attribute__ ((packed)) ld_owner;
1557
1558 struct {
1559 u64 ld_lba;
1560 u64 pd_lba;
1561 struct megasas_evtarg_ld ld;
1562 struct megasas_evtarg_pd pd;
1563 } __attribute__ ((packed)) ld_lba_pd_lba;
1564
1565 struct {
1566 struct megasas_evtarg_ld ld;
1567 struct megasas_progress prog;
1568 } __attribute__ ((packed)) ld_prog;
1569
1570 struct {
1571 struct megasas_evtarg_ld ld;
1572 u32 prev_state;
1573 u32 new_state;
1574 } __attribute__ ((packed)) ld_state;
1575
1576 struct {
1577 u64 strip;
1578 struct megasas_evtarg_ld ld;
1579 } __attribute__ ((packed)) ld_strip;
1580
1581 struct megasas_evtarg_pd pd;
1582
1583 struct {
1584 struct megasas_evtarg_pd pd;
1585 u32 err;
1586 } __attribute__ ((packed)) pd_err;
1587
1588 struct {
1589 u64 lba;
1590 struct megasas_evtarg_pd pd;
1591 } __attribute__ ((packed)) pd_lba;
1592
1593 struct {
1594 u64 lba;
1595 struct megasas_evtarg_pd pd;
1596 struct megasas_evtarg_ld ld;
1597 } __attribute__ ((packed)) pd_lba_ld;
1598
1599 struct {
1600 struct megasas_evtarg_pd pd;
1601 struct megasas_progress prog;
1602 } __attribute__ ((packed)) pd_prog;
1603
1604 struct {
1605 struct megasas_evtarg_pd pd;
1606 u32 prevState;
1607 u32 newState;
1608 } __attribute__ ((packed)) pd_state;
1609
1610 struct {
1611 u16 vendorId;
1612 u16 deviceId;
1613 u16 subVendorId;
1614 u16 subDeviceId;
1615 } __attribute__ ((packed)) pci;
1616
1617 u32 rate;
1618 char str[96];
1619
1620 struct {
1621 u32 rtc;
1622 u32 elapsedSeconds;
1623 } __attribute__ ((packed)) time;
1624
1625 struct {
1626 u32 ecar;
1627 u32 elog;
1628 char str[64];
1629 } __attribute__ ((packed)) ecc;
1630
1631 u8 b[96];
1632 u16 s[48];
1633 u32 w[24];
1634 u64 d[12];
1635 } args;
1636
1637 char description[128];
1638
1639} __attribute__ ((packed));
1640
7e8a75f4 1641struct megasas_aen_event {
c1d390d8 1642 struct delayed_work hotplug_work;
7e8a75f4
YB		 1643 struct megasas_instance *instance;
1644};
1645
c8e858fe 1646struct megasas_irq_context {
1647 struct megasas_instance *instance;
1648 u32 MSIxIndex;
1649};
1650
c4a3e0a5
BS		 1651struct megasas_instance {
1652
1653 u32 *producer;
1654 dma_addr_t producer_h;
1655 u32 *consumer;
1656 dma_addr_t consumer_h;
229fe47c 1657 struct MR_LD_VF_AFFILIATION *vf_affiliation;
1658 dma_addr_t vf_affiliation_h;
1659 struct MR_LD_VF_AFFILIATION_111 *vf_affiliation_111;
1660 dma_addr_t vf_affiliation_111_h;
1661 struct MR_CTRL_HB_HOST_MEM *hb_host_mem;
1662 dma_addr_t hb_host_mem_h;
c4a3e0a5
BS		 1663
1664 u32 *reply_queue;
1665 dma_addr_t reply_queue_h;
1666
fc62b3fc
SS		 1667 u32 *crash_dump_buf;
1668 dma_addr_t crash_dump_h;
1669 void *crash_buf[MAX_CRASH_DUMP_SIZE];
1670 u32 crash_buf_pages;
1671 unsigned int fw_crash_buffer_size;
1672 unsigned int fw_crash_state;
1673 unsigned int fw_crash_buffer_offset;
1674 u32 drv_buf_index;
1675 u32 drv_buf_alloc;
1676 u32 crash_dump_fw_support;
1677 u32 crash_dump_drv_support;
1678 u32 crash_dump_app_support;
7497cde8 1679 u32 secure_jbod_support;
fc62b3fc
SS		 1680 spinlock_t crashdump_lock;
1681
c4a3e0a5 1682 struct megasas_register_set __iomem *reg_set;
d46a3ad6 1683 u32 *reply_post_host_index_addr[MR_MAX_MSIX_REG_ARRAY];
81e403ce 1684 struct megasas_pd_list pd_list[MEGASAS_MAX_PD];
999ece0a 1685 struct megasas_pd_list local_pd_list[MEGASAS_MAX_PD];
7497cde8 1686 u8 ld_ids[MEGASAS_MAX_LD_IDS];
c4a3e0a5 1687 s8 init_id;
c4a3e0a5
BS		 1688
1689 u16 max_num_sge;
1690 u16 max_fw_cmds;
9c915a8c 1691 u16 max_mfi_cmds;
ae09a6c1 1692 u16 max_scsi_cmds;
c4a3e0a5 1693 u32 max_sectors_per_req;
7e8a75f4 1694 struct megasas_aen_event *ev;
c4a3e0a5
BS		 1695
1696 struct megasas_cmd **cmd_list;
1697 struct list_head cmd_pool;
39a98554 1698 /* used to sync fire the cmd to fw */
90dc9d98 1699 spinlock_t mfi_pool_lock;
39a98554 1700 /* used to sync fire the cmd to fw */
1701 spinlock_t hba_lock;
7343eb65 1702 /* used to synch producer, consumer ptrs in dpc */
1703 spinlock_t completion_lock;
c4a3e0a5
BS		 1704 struct dma_pool *frame_dma_pool;
1705 struct dma_pool *sense_dma_pool;
1706
1707 struct megasas_evt_detail *evt_detail;
1708 dma_addr_t evt_detail_h;
1709 struct megasas_cmd *aen_cmd;
e5a69e27 1710 struct mutex aen_mutex;
c4a3e0a5
BS		 1711 struct semaphore ioctl_sem;
1712
1713 struct Scsi_Host *host;
1714
1715 wait_queue_head_t int_cmd_wait_q;
1716 wait_queue_head_t abort_cmd_wait_q;
1717
1718 struct pci_dev *pdev;
1719 u32 unique_id;
39a98554 1720 u32 fw_support_ieee;
c4a3e0a5 1721
e4a082c7 1722 atomic_t fw_outstanding;
39a98554 1723 atomic_t fw_reset_no_pci_access;
1341c939
SP		 1724
1725 struct megasas_instance_template *instancet;
5d018ad0 1726 struct tasklet_struct isr_tasklet;
39a98554 1727 struct work_struct work_init;
fc62b3fc 1728 struct work_struct crash_init;
05e9ebbe
SP		 1729
1730 u8 flag;
c3518837 1731 u8 unload;
f4c9a131 1732 u8 flag_ieee;
39a98554 1733 u8 issuepend_done;
1734 u8 disableOnlineCtrlReset;
bc93d425 1735 u8 UnevenSpanSupport;
51087a86
SS		 1736
1737 u8 supportmax256vd;
1738 u16 fw_supported_vd_count;
1739 u16 fw_supported_pd_count;
1740
1741 u16 drv_supported_vd_count;
1742 u16 drv_supported_pd_count;
1743
39a98554 1744 u8 adprecovery;
05e9ebbe 1745 unsigned long last_time;
39a98554 1746 u32 mfiStatus;
1747 u32 last_seq_num;
ad84db2e 1748
39a98554 1749 struct list_head internal_reset_pending_q;
80d9da98 1750
25985edc 1751 /* Ptr to hba specific information */
9c915a8c 1752 void *ctrl_context;
51087a86
SS		 1753 u32 ctrl_context_pages;
1754 struct megasas_ctrl_info *ctrl_info;
c8e858fe 1755 unsigned int msix_vectors;
1756 struct msix_entry msixentry[MEGASAS_MAX_MSIX_QUEUES];
1757 struct megasas_irq_context irq_context[MEGASAS_MAX_MSIX_QUEUES];
9c915a8c 1758 u64 map_id;
1759 struct megasas_cmd *map_update_cmd;
b6d5d880 1760 unsigned long bar;
9c915a8c 1761 long reset_flags;
1762 struct mutex reset_mutex;
229fe47c 1763 struct timer_list sriov_heartbeat_timer;
1764 char skip_heartbeat_timer_del;
1765 u8 requestorId;
229fe47c 1766 char PlasmaFW111;
1767 char mpio;
ae09a6c1 1768 u16 throttlequeuedepth;
d46a3ad6 1769 u8 mask_interrupts;
404a8a1a 1770 u8 is_imr;
39a98554 1771};
229fe47c 1772struct MR_LD_VF_MAP {
1773 u32 size;
1774 union MR_LD_REF ref;
1775 u8 ldVfCount;
1776 u8 reserved[6];
1777 u8 policy[1];
1778};
1779
1780struct MR_LD_VF_AFFILIATION {
1781 u32 size;
1782 u8 ldCount;
1783 u8 vfCount;
1784 u8 thisVf;
1785 u8 reserved[9];
1786 struct MR_LD_VF_MAP map[1];
1787};
1788
1789/* Plasma 1.11 FW backward compatibility structures */
1790#define IOV_111_OFFSET 0x7CE
1791#define MAX_VIRTUAL_FUNCTIONS 8
4cbfea88 1792#define MR_LD_ACCESS_HIDDEN 15
229fe47c 1793
1794struct IOV_111 {
1795 u8 maxVFsSupported;
1796 u8 numVFsEnabled;
1797 u8 requestorId;
1798 u8 reserved[5];
1799};
1800
1801struct MR_LD_VF_MAP_111 {
1802 u8 targetId;
1803 u8 reserved[3];
1804 u8 policy[MAX_VIRTUAL_FUNCTIONS];
1805};
1806
1807struct MR_LD_VF_AFFILIATION_111 {
1808 u8 vdCount;
1809 u8 vfCount;
1810 u8 thisVf;
1811 u8 reserved[5];
1812 struct MR_LD_VF_MAP_111 map[MAX_LOGICAL_DRIVES];
1813};
1814
1815struct MR_CTRL_HB_HOST_MEM {
1816 struct {
1817 u32 fwCounter; /* Firmware heart beat counter */
1818 struct {
1819 u32 debugmode:1; /* 1=Firmware is in debug mode.
1820 Heart beat will not be updated. */
1821 u32 reserved:31;
1822 } debug;
1823 u32 reserved_fw[6];
1824 u32 driverCounter; /* Driver heart beat counter. 0x20 */
1825 u32 reserved_driver[7];
1826 } HB;
1827 u8 pad[0x400-0x40];
1828};
39a98554 1829
1830enum {
1831 MEGASAS_HBA_OPERATIONAL = 0,
1832 MEGASAS_ADPRESET_SM_INFAULT = 1,
1833 MEGASAS_ADPRESET_SM_FW_RESET_SUCCESS = 2,
1834 MEGASAS_ADPRESET_SM_OPERATIONAL = 3,
1835 MEGASAS_HW_CRITICAL_ERROR = 4,
229fe47c 1836 MEGASAS_ADPRESET_SM_POLLING = 5,
39a98554 1837 MEGASAS_ADPRESET_INPROG_SIGN = 0xDEADDEAD,
c4a3e0a5
BS		 1838};
1839
0c79e681
YB		 1840struct megasas_instance_template {
1841 void (*fire_cmd)(struct megasas_instance *, dma_addr_t, \
1842 u32, struct megasas_register_set __iomem *);
1843
d46a3ad6
SS		 1844 void (*enable_intr)(struct megasas_instance *);
1845 void (*disable_intr)(struct megasas_instance *);
0c79e681
YB		 1846
1847 int (*clear_intr)(struct megasas_register_set __iomem *);
1848
1849 u32 (*read_fw_status_reg)(struct megasas_register_set __iomem *);
39a98554 1850 int (*adp_reset)(struct megasas_instance *, \
1851 struct megasas_register_set __iomem *);
1852 int (*check_reset)(struct megasas_instance *, \
1853 struct megasas_register_set __iomem *);
cd50ba8e 1854 irqreturn_t (*service_isr)(int irq, void *devp);
1855 void (*tasklet)(unsigned long);
1856 u32 (*init_adapter)(struct megasas_instance *);
1857 u32 (*build_and_issue_cmd) (struct megasas_instance *,
1858 struct scsi_cmnd *);
1859 void (*issue_dcmd) (struct megasas_instance *instance,
1860 struct megasas_cmd *cmd);
0c79e681
YB		 1861};
1862
c4a3e0a5
BS		 1863#define MEGASAS_IS_LOGICAL(scp) \
1864 (scp->device->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1
1865
4a5c814d
SS		 1866#define MEGASAS_DEV_INDEX(scp) \
1867 (((scp->device->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) + \
1868 scp->device->id)
1869
1870#define MEGASAS_PD_INDEX(scp) \
1871 ((scp->device->channel * MEGASAS_MAX_DEV_PER_CHANNEL) + \
1872 scp->device->id)
c4a3e0a5
BS		 1873
1874struct megasas_cmd {
1875
1876 union megasas_frame *frame;
1877 dma_addr_t frame_phys_addr;
1878 u8 *sense;
1879 dma_addr_t sense_phys_addr;
1880
1881 u32 index;
1882 u8 sync_cmd;
1883 u8 cmd_status;
39a98554 1884 u8 abort_aen;
1885 u8 retry_for_fw_reset;
1886
c4a3e0a5
BS		 1887
1888 struct list_head list;
1889 struct scsi_cmnd *scmd;
4026e9aa 1890 u8 flags;
90dc9d98 1891
c4a3e0a5 1892 struct megasas_instance *instance;
9c915a8c 1893 union {
1894 struct {
1895 u16 smid;
1896 u16 resvd;
1897 } context;
1898 u32 frame_count;
1899 };
c4a3e0a5
BS		 1900};
1901
1902#define MAX_MGMT_ADAPTERS 1024
1903#define MAX_IOCTL_SGE 16
1904
1905struct megasas_iocpacket {
1906
1907 u16 host_no;
1908 u16 __pad1;
1909 u32 sgl_off;
1910 u32 sge_count;
1911 u32 sense_off;
1912 u32 sense_len;
1913 union {
1914 u8 raw[128];
1915 struct megasas_header hdr;
1916 } frame;
1917
1918 struct iovec sgl[MAX_IOCTL_SGE];
1919
1920} __attribute__ ((packed));
1921
1922struct megasas_aen {
1923 u16 host_no;
1924 u16 __pad1;
1925 u32 seq_num;
1926 u32 class_locale_word;
1927} __attribute__ ((packed));
1928
1929#ifdef CONFIG_COMPAT
1930struct compat_megasas_iocpacket {
1931 u16 host_no;
1932 u16 __pad1;
1933 u32 sgl_off;
1934 u32 sge_count;
1935 u32 sense_off;
1936 u32 sense_len;
1937 union {
1938 u8 raw[128];
1939 struct megasas_header hdr;
1940 } frame;
1941 struct compat_iovec sgl[MAX_IOCTL_SGE];
1942} __attribute__ ((packed));
1943
0e98936c 1944#define MEGASAS_IOC_FIRMWARE32 _IOWR('M', 1, struct compat_megasas_iocpacket)
c4a3e0a5
BS		 1945#endif
1946
cb59aa6a 1947#define MEGASAS_IOC_FIRMWARE _IOWR('M', 1, struct megasas_iocpacket)
c4a3e0a5
BS		 1948#define MEGASAS_IOC_GET_AEN _IOW('M', 3, struct megasas_aen)
1949
1950struct megasas_mgmt_info {
1951
1952 u16 count;
1953 struct megasas_instance *instance[MAX_MGMT_ADAPTERS];
1954 int max_index;
1955};
1956
21c9e160 1957u8
1958MR_BuildRaidContext(struct megasas_instance *instance,
1959 struct IO_REQUEST_INFO *io_info,
1960 struct RAID_CONTEXT *pRAID_Context,
51087a86
SS		 1961 struct MR_DRV_RAID_MAP_ALL *map, u8 **raidLUN);
1962u8 MR_TargetIdToLdGet(u32 ldTgtId, struct MR_DRV_RAID_MAP_ALL *map);
1963struct MR_LD_RAID *MR_LdRaidGet(u32 ld, struct MR_DRV_RAID_MAP_ALL *map);
1964u16 MR_ArPdGet(u32 ar, u32 arm, struct MR_DRV_RAID_MAP_ALL *map);
1965u16 MR_LdSpanArrayGet(u32 ld, u32 span, struct MR_DRV_RAID_MAP_ALL *map);
1966u16 MR_PdDevHandleGet(u32 pd, struct MR_DRV_RAID_MAP_ALL *map);
1967u16 MR_GetLDTgtId(u32 ld, struct MR_DRV_RAID_MAP_ALL *map);
1968
d2552ebe
SS		 1969u16 get_updated_dev_handle(struct megasas_instance *instance,
1970 struct LD_LOAD_BALANCE_INFO *lbInfo, struct IO_REQUEST_INFO *in_info);
51087a86
SS		 1971void mr_update_load_balance_params(struct MR_DRV_RAID_MAP_ALL *map,
1972 struct LD_LOAD_BALANCE_INFO *lbInfo);
d009b576 1973int megasas_get_ctrl_info(struct megasas_instance *instance);
fc62b3fc 1974int megasas_set_crash_dump_params(struct megasas_instance *instance,
51087a86 1975 u8 crash_buf_state);
fc62b3fc
SS		 1976void megasas_free_host_crash_buffer(struct megasas_instance *instance);
1977void megasas_fusion_crash_dump_wq(struct work_struct *work);
51087a86 1978
90dc9d98
SS		 1979void megasas_return_cmd_fusion(struct megasas_instance *instance,
1980 struct megasas_cmd_fusion *cmd);
1981int megasas_issue_blocked_cmd(struct megasas_instance *instance,
1982 struct megasas_cmd *cmd, int timeout);
1983void __megasas_return_cmd(struct megasas_instance *instance,
1984 struct megasas_cmd *cmd);
1985
1986void megasas_return_mfi_mpt_pthr(struct megasas_instance *instance,
1987 struct megasas_cmd *cmd_mfi, struct megasas_cmd_fusion *cmd_fusion);
7497cde8 1988int megasas_cmd_type(struct scsi_cmnd *cmd);
90dc9d98 1989
c4a3e0a5 1990#endif /*LSI_MEGARAID_SAS_H */
Linux kernel - Deliverables
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