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[SCSI] megaraid_sas: Add new megaraid SAS 2 controller support to the driver
[deliverable/linux.git] / drivers / scsi / megaraid / megaraid_sas.h
CommitLineData
c4a3e0a5
BS		 1/*
2 *
3 * Linux MegaRAID driver for SAS based RAID controllers
4 *
f28cd7cf 5 * Copyright (c) 2003-2005 LSI Corporation.
c4a3e0a5
BS		 6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 *
12 * FILE : megaraid_sas.h
13 */
14
15#ifndef LSI_MEGARAID_SAS_H
16#define LSI_MEGARAID_SAS_H
17
a69b74d3 18/*
c4a3e0a5
BS		 19 * MegaRAID SAS Driver meta data
20 */
24541f99
YB		 21#define MEGASAS_VERSION "00.00.04.01"
22#define MEGASAS_RELDATE "July 24, 2008"
23#define MEGASAS_EXT_VERSION "Thu July 24 11:41:51 PST 2008"
0e98936c
SP		 24
25/*
26 * Device IDs
27 */
28#define PCI_DEVICE_ID_LSI_SAS1078R 0x0060
af7a5647 29#define PCI_DEVICE_ID_LSI_SAS1078DE 0x007C
0e98936c 30#define PCI_DEVICE_ID_LSI_VERDE_ZCR 0x0413
6610a6b3
YB		 31#define PCI_DEVICE_ID_LSI_SAS1078GEN2 0x0078
32#define PCI_DEVICE_ID_LSI_SAS0079GEN2 0x0079
87911122
YB		 33#define PCI_DEVICE_ID_LSI_SAS0073SKINNY 0x0073
34#define PCI_DEVICE_ID_LSI_SAS0071SKINNY 0x0071
0e98936c 35
c4a3e0a5
BS		 36/*
37 * =====================================
38 * MegaRAID SAS MFI firmware definitions
39 * =====================================
40 */
41
42/*
43 * MFI stands for MegaRAID SAS FW Interface. This is just a moniker for
44 * protocol between the software and firmware. Commands are issued using
45 * "message frames"
46 */
47
a69b74d3 48/*
c4a3e0a5
BS		 49 * FW posts its state in upper 4 bits of outbound_msg_0 register
50 */
51#define MFI_STATE_MASK 0xF0000000
52#define MFI_STATE_UNDEFINED 0x00000000
53#define MFI_STATE_BB_INIT 0x10000000
54#define MFI_STATE_FW_INIT 0x40000000
55#define MFI_STATE_WAIT_HANDSHAKE 0x60000000
56#define MFI_STATE_FW_INIT_2 0x70000000
57#define MFI_STATE_DEVICE_SCAN 0x80000000
e3bbff9f 58#define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000
c4a3e0a5
BS		 59#define MFI_STATE_FLUSH_CACHE 0xA0000000
60#define MFI_STATE_READY 0xB0000000
61#define MFI_STATE_OPERATIONAL 0xC0000000
62#define MFI_STATE_FAULT 0xF0000000
63
64#define MEGAMFI_FRAME_SIZE 64
65
a69b74d3 66/*
c4a3e0a5
BS		 67 * During FW init, clear pending cmds & reset state using inbound_msg_0
68 *
69 * ABORT : Abort all pending cmds
70 * READY : Move from OPERATIONAL to READY state; discard queue info
71 * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??)
72 * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver
e3bbff9f
SP		 73 * HOTPLUG : Resume from Hotplug
74 * MFI_STOP_ADP : Send signal to FW to stop processing
c4a3e0a5 75 */
e3bbff9f 76#define MFI_INIT_ABORT 0x00000001
c4a3e0a5
BS		 77#define MFI_INIT_READY 0x00000002
78#define MFI_INIT_MFIMODE 0x00000004
79#define MFI_INIT_CLEAR_HANDSHAKE 0x00000008
e3bbff9f
SP		 80#define MFI_INIT_HOTPLUG 0x00000010
81#define MFI_STOP_ADP 0x00000020
82#define MFI_RESET_FLAGS MFI_INIT_READY| \
83 MFI_INIT_MFIMODE| \
84 MFI_INIT_ABORT
c4a3e0a5 85
a69b74d3 86/*
c4a3e0a5
BS		 87 * MFI frame flags
88 */
89#define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000
90#define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001
91#define MFI_FRAME_SGL32 0x0000
92#define MFI_FRAME_SGL64 0x0002
93#define MFI_FRAME_SENSE32 0x0000
94#define MFI_FRAME_SENSE64 0x0004
95#define MFI_FRAME_DIR_NONE 0x0000
96#define MFI_FRAME_DIR_WRITE 0x0008
97#define MFI_FRAME_DIR_READ 0x0010
98#define MFI_FRAME_DIR_BOTH 0x0018
99
a69b74d3 100/*
c4a3e0a5
BS		 101 * Definition for cmd_status
102 */
103#define MFI_CMD_STATUS_POLL_MODE 0xFF
104
a69b74d3 105/*
c4a3e0a5
BS		 106 * MFI command opcodes
107 */
108#define MFI_CMD_INIT 0x00
109#define MFI_CMD_LD_READ 0x01
110#define MFI_CMD_LD_WRITE 0x02
111#define MFI_CMD_LD_SCSI_IO 0x03
112#define MFI_CMD_PD_SCSI_IO 0x04
113#define MFI_CMD_DCMD 0x05
114#define MFI_CMD_ABORT 0x06
115#define MFI_CMD_SMP 0x07
116#define MFI_CMD_STP 0x08
117
118#define MR_DCMD_CTRL_GET_INFO 0x01010000
119
120#define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000
121#define MR_FLUSH_CTRL_CACHE 0x01
122#define MR_FLUSH_DISK_CACHE 0x02
123
124#define MR_DCMD_CTRL_SHUTDOWN 0x01050000
31ea7088 125#define MR_DCMD_HIBERNATE_SHUTDOWN 0x01060000
c4a3e0a5
BS		 126#define MR_ENABLE_DRIVE_SPINDOWN 0x01
127
128#define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100
129#define MR_DCMD_CTRL_EVENT_GET 0x01040300
130#define MR_DCMD_CTRL_EVENT_WAIT 0x01040500
131#define MR_DCMD_LD_GET_PROPERTIES 0x03030000
132
133#define MR_DCMD_CLUSTER 0x08000000
134#define MR_DCMD_CLUSTER_RESET_ALL 0x08010100
135#define MR_DCMD_CLUSTER_RESET_LD 0x08010200
136
a69b74d3 137/*
c4a3e0a5
BS		 138 * MFI command completion codes
139 */
140enum MFI_STAT {
141 MFI_STAT_OK = 0x00,
142 MFI_STAT_INVALID_CMD = 0x01,
143 MFI_STAT_INVALID_DCMD = 0x02,
144 MFI_STAT_INVALID_PARAMETER = 0x03,
145 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04,
146 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05,
147 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06,
148 MFI_STAT_APP_IN_USE = 0x07,
149 MFI_STAT_APP_NOT_INITIALIZED = 0x08,
150 MFI_STAT_ARRAY_INDEX_INVALID = 0x09,
151 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a,
152 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b,
153 MFI_STAT_DEVICE_NOT_FOUND = 0x0c,
154 MFI_STAT_DRIVE_TOO_SMALL = 0x0d,
155 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e,
156 MFI_STAT_FLASH_BUSY = 0x0f,
157 MFI_STAT_FLASH_ERROR = 0x10,
158 MFI_STAT_FLASH_IMAGE_BAD = 0x11,
159 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12,
160 MFI_STAT_FLASH_NOT_OPEN = 0x13,
161 MFI_STAT_FLASH_NOT_STARTED = 0x14,
162 MFI_STAT_FLUSH_FAILED = 0x15,
163 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16,
164 MFI_STAT_LD_CC_IN_PROGRESS = 0x17,
165 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18,
166 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19,
167 MFI_STAT_LD_MAX_CONFIGURED = 0x1a,
168 MFI_STAT_LD_NOT_OPTIMAL = 0x1b,
169 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c,
170 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d,
171 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e,
172 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f,
173 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
174 MFI_STAT_MFC_HW_ERROR = 0x21,
175 MFI_STAT_NO_HW_PRESENT = 0x22,
176 MFI_STAT_NOT_FOUND = 0x23,
177 MFI_STAT_NOT_IN_ENCL = 0x24,
178 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25,
179 MFI_STAT_PD_TYPE_WRONG = 0x26,
180 MFI_STAT_PR_DISABLED = 0x27,
181 MFI_STAT_ROW_INDEX_INVALID = 0x28,
182 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29,
183 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a,
184 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b,
185 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c,
186 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d,
187 MFI_STAT_SCSI_IO_FAILED = 0x2e,
188 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f,
189 MFI_STAT_SHUTDOWN_FAILED = 0x30,
190 MFI_STAT_TIME_NOT_SET = 0x31,
191 MFI_STAT_WRONG_STATE = 0x32,
192 MFI_STAT_LD_OFFLINE = 0x33,
193 MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34,
194 MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35,
195 MFI_STAT_RESERVATION_IN_PROGRESS = 0x36,
196 MFI_STAT_I2C_ERRORS_DETECTED = 0x37,
197 MFI_STAT_PCI_ERRORS_DETECTED = 0x38,
198
199 MFI_STAT_INVALID_STATUS = 0xFF
200};
201
202/*
203 * Number of mailbox bytes in DCMD message frame
204 */
205#define MFI_MBOX_SIZE 12
206
207enum MR_EVT_CLASS {
208
209 MR_EVT_CLASS_DEBUG = -2,
210 MR_EVT_CLASS_PROGRESS = -1,
211 MR_EVT_CLASS_INFO = 0,
212 MR_EVT_CLASS_WARNING = 1,
213 MR_EVT_CLASS_CRITICAL = 2,
214 MR_EVT_CLASS_FATAL = 3,
215 MR_EVT_CLASS_DEAD = 4,
216
217};
218
219enum MR_EVT_LOCALE {
220
221 MR_EVT_LOCALE_LD = 0x0001,
222 MR_EVT_LOCALE_PD = 0x0002,
223 MR_EVT_LOCALE_ENCL = 0x0004,
224 MR_EVT_LOCALE_BBU = 0x0008,
225 MR_EVT_LOCALE_SAS = 0x0010,
226 MR_EVT_LOCALE_CTRL = 0x0020,
227 MR_EVT_LOCALE_CONFIG = 0x0040,
228 MR_EVT_LOCALE_CLUSTER = 0x0080,
229 MR_EVT_LOCALE_ALL = 0xffff,
230
231};
232
233enum MR_EVT_ARGS {
234
235 MR_EVT_ARGS_NONE,
236 MR_EVT_ARGS_CDB_SENSE,
237 MR_EVT_ARGS_LD,
238 MR_EVT_ARGS_LD_COUNT,
239 MR_EVT_ARGS_LD_LBA,
240 MR_EVT_ARGS_LD_OWNER,
241 MR_EVT_ARGS_LD_LBA_PD_LBA,
242 MR_EVT_ARGS_LD_PROG,
243 MR_EVT_ARGS_LD_STATE,
244 MR_EVT_ARGS_LD_STRIP,
245 MR_EVT_ARGS_PD,
246 MR_EVT_ARGS_PD_ERR,
247 MR_EVT_ARGS_PD_LBA,
248 MR_EVT_ARGS_PD_LBA_LD,
249 MR_EVT_ARGS_PD_PROG,
250 MR_EVT_ARGS_PD_STATE,
251 MR_EVT_ARGS_PCI,
252 MR_EVT_ARGS_RATE,
253 MR_EVT_ARGS_STR,
254 MR_EVT_ARGS_TIME,
255 MR_EVT_ARGS_ECC,
256
257};
258
259/*
260 * SAS controller properties
261 */
262struct megasas_ctrl_prop {
263
264 u16 seq_num;
265 u16 pred_fail_poll_interval;
266 u16 intr_throttle_count;
267 u16 intr_throttle_timeouts;
268 u8 rebuild_rate;
269 u8 patrol_read_rate;
270 u8 bgi_rate;
271 u8 cc_rate;
272 u8 recon_rate;
273 u8 cache_flush_interval;
274 u8 spinup_drv_count;
275 u8 spinup_delay;
276 u8 cluster_enable;
277 u8 coercion_mode;
278 u8 alarm_enable;
279 u8 disable_auto_rebuild;
280 u8 disable_battery_warn;
281 u8 ecc_bucket_size;
282 u16 ecc_bucket_leak_rate;
283 u8 restore_hotspare_on_insertion;
284 u8 expose_encl_devices;
285 u8 reserved[38];
286
287} __attribute__ ((packed));
288
289/*
290 * SAS controller information
291 */
292struct megasas_ctrl_info {
293
294 /*
295 * PCI device information
296 */
297 struct {
298
299 u16 vendor_id;
300 u16 device_id;
301 u16 sub_vendor_id;
302 u16 sub_device_id;
303 u8 reserved[24];
304
305 } __attribute__ ((packed)) pci;
306
307 /*
308 * Host interface information
309 */
310 struct {
311
312 u8 PCIX:1;
313 u8 PCIE:1;
314 u8 iSCSI:1;
315 u8 SAS_3G:1;
316 u8 reserved_0:4;
317 u8 reserved_1[6];
318 u8 port_count;
319 u64 port_addr[8];
320
321 } __attribute__ ((packed)) host_interface;
322
323 /*
324 * Device (backend) interface information
325 */
326 struct {
327
328 u8 SPI:1;
329 u8 SAS_3G:1;
330 u8 SATA_1_5G:1;
331 u8 SATA_3G:1;
332 u8 reserved_0:4;
333 u8 reserved_1[6];
334 u8 port_count;
335 u64 port_addr[8];
336
337 } __attribute__ ((packed)) device_interface;
338
339 /*
340 * List of components residing in flash. All str are null terminated
341 */
342 u32 image_check_word;
343 u32 image_component_count;
344
345 struct {
346
347 char name[8];
348 char version[32];
349 char build_date[16];
350 char built_time[16];
351
352 } __attribute__ ((packed)) image_component[8];
353
354 /*
355 * List of flash components that have been flashed on the card, but
356 * are not in use, pending reset of the adapter. This list will be
357 * empty if a flash operation has not occurred. All stings are null
358 * terminated
359 */
360 u32 pending_image_component_count;
361
362 struct {
363
364 char name[8];
365 char version[32];
366 char build_date[16];
367 char build_time[16];
368
369 } __attribute__ ((packed)) pending_image_component[8];
370
371 u8 max_arms;
372 u8 max_spans;
373 u8 max_arrays;
374 u8 max_lds;
375
376 char product_name[80];
377 char serial_no[32];
378
379 /*
380 * Other physical/controller/operation information. Indicates the
381 * presence of the hardware
382 */
383 struct {
384
385 u32 bbu:1;
386 u32 alarm:1;
387 u32 nvram:1;
388 u32 uart:1;
389 u32 reserved:28;
390
391 } __attribute__ ((packed)) hw_present;
392
393 u32 current_fw_time;
394
395 /*
396 * Maximum data transfer sizes
397 */
398 u16 max_concurrent_cmds;
399 u16 max_sge_count;
400 u32 max_request_size;
401
402 /*
403 * Logical and physical device counts
404 */
405 u16 ld_present_count;
406 u16 ld_degraded_count;
407 u16 ld_offline_count;
408
409 u16 pd_present_count;
410 u16 pd_disk_present_count;
411 u16 pd_disk_pred_failure_count;
412 u16 pd_disk_failed_count;
413
414 /*
415 * Memory size information
416 */
417 u16 nvram_size;
418 u16 memory_size;
419 u16 flash_size;
420
421 /*
422 * Error counters
423 */
424 u16 mem_correctable_error_count;
425 u16 mem_uncorrectable_error_count;
426
427 /*
428 * Cluster information
429 */
430 u8 cluster_permitted;
431 u8 cluster_active;
432
433 /*
434 * Additional max data transfer sizes
435 */
436 u16 max_strips_per_io;
437
438 /*
439 * Controller capabilities structures
440 */
441 struct {
442
443 u32 raid_level_0:1;
444 u32 raid_level_1:1;
445 u32 raid_level_5:1;
446 u32 raid_level_1E:1;
447 u32 raid_level_6:1;
448 u32 reserved:27;
449
450 } __attribute__ ((packed)) raid_levels;
451
452 struct {
453
454 u32 rbld_rate:1;
455 u32 cc_rate:1;
456 u32 bgi_rate:1;
457 u32 recon_rate:1;
458 u32 patrol_rate:1;
459 u32 alarm_control:1;
460 u32 cluster_supported:1;
461 u32 bbu:1;
462 u32 spanning_allowed:1;
463 u32 dedicated_hotspares:1;
464 u32 revertible_hotspares:1;
465 u32 foreign_config_import:1;
466 u32 self_diagnostic:1;
467 u32 mixed_redundancy_arr:1;
468 u32 global_hot_spares:1;
469 u32 reserved:17;
470
471 } __attribute__ ((packed)) adapter_operations;
472
473 struct {
474
475 u32 read_policy:1;
476 u32 write_policy:1;
477 u32 io_policy:1;
478 u32 access_policy:1;
479 u32 disk_cache_policy:1;
480 u32 reserved:27;
481
482 } __attribute__ ((packed)) ld_operations;
483
484 struct {
485
486 u8 min;
487 u8 max;
488 u8 reserved[2];
489
490 } __attribute__ ((packed)) stripe_sz_ops;
491
492 struct {
493
494 u32 force_online:1;
495 u32 force_offline:1;
496 u32 force_rebuild:1;
497 u32 reserved:29;
498
499 } __attribute__ ((packed)) pd_operations;
500
501 struct {
502
503 u32 ctrl_supports_sas:1;
504 u32 ctrl_supports_sata:1;
505 u32 allow_mix_in_encl:1;
506 u32 allow_mix_in_ld:1;
507 u32 allow_sata_in_cluster:1;
508 u32 reserved:27;
509
510 } __attribute__ ((packed)) pd_mix_support;
511
512 /*
513 * Define ECC single-bit-error bucket information
514 */
515 u8 ecc_bucket_count;
516 u8 reserved_2[11];
517
518 /*
519 * Include the controller properties (changeable items)
520 */
521 struct megasas_ctrl_prop properties;
522
523 /*
524 * Define FW pkg version (set in envt v'bles on OEM basis)
525 */
526 char package_version[0x60];
527
528 u8 pad[0x800 - 0x6a0];
529
530} __attribute__ ((packed));
531
532/*
533 * ===============================
534 * MegaRAID SAS driver definitions
535 * ===============================
536 */
537#define MEGASAS_MAX_PD_CHANNELS 2
538#define MEGASAS_MAX_LD_CHANNELS 2
539#define MEGASAS_MAX_CHANNELS (MEGASAS_MAX_PD_CHANNELS + \
540 MEGASAS_MAX_LD_CHANNELS)
541#define MEGASAS_MAX_DEV_PER_CHANNEL 128
542#define MEGASAS_DEFAULT_INIT_ID -1
543#define MEGASAS_MAX_LUN 8
544#define MEGASAS_MAX_LD 64
545
658dcedb
SP		 546#define MEGASAS_DBG_LVL 1
547
05e9ebbe
SP		 548#define MEGASAS_FW_BUSY 1
549
d532dbe2 550/* Frame Type */
551#define IO_FRAME 0
552#define PTHRU_FRAME 1
553
c4a3e0a5
BS		 554/*
555 * When SCSI mid-layer calls driver's reset routine, driver waits for
556 * MEGASAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note
557 * that the driver cannot _actually_ abort or reset pending commands. While
558 * it is waiting for the commands to complete, it prints a diagnostic message
559 * every MEGASAS_RESET_NOTICE_INTERVAL seconds
560 */
561#define MEGASAS_RESET_WAIT_TIME 180
2a3681e5 562#define MEGASAS_INTERNAL_CMD_WAIT_TIME 180
c4a3e0a5 563#define MEGASAS_RESET_NOTICE_INTERVAL 5
c4a3e0a5 564#define MEGASAS_IOCTL_CMD 0
05e9ebbe 565#define MEGASAS_DEFAULT_CMD_TIMEOUT 90
c4a3e0a5
BS		 566
567/*
568 * FW reports the maximum of number of commands that it can accept (maximum
569 * commands that can be outstanding) at any time. The driver must report a
570 * lower number to the mid layer because it can issue a few internal commands
571 * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs
572 * is shown below
573 */
574#define MEGASAS_INT_CMDS 32
575
576/*
577 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit
578 * SGLs based on the size of dma_addr_t
579 */
580#define IS_DMA64 (sizeof(dma_addr_t) == 8)
581
582#define MFI_OB_INTR_STATUS_MASK 0x00000002
14faea9f 583#define MFI_POLL_TIMEOUT_SECS 60
ad84db2e 584#define MEGASAS_COMPLETION_TIMER_INTERVAL (HZ/10)
c4a3e0a5 585
f9876f0b 586#define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000
6610a6b3
YB		 587#define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001
588#define MFI_GEN2_ENABLE_INTERRUPT_MASK (0x00000001 | 0x00000004)
87911122
YB		 589#define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000
590#define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001)
0e98936c
SP		 591
592/*
593* register set for both 1068 and 1078 controllers
594* structure extended for 1078 registers
595*/
f9876f0b 596
c4a3e0a5 597struct megasas_register_set {
f9876f0b 598 u32 reserved_0[4]; /*0000h*/
c4a3e0a5 599
f9876f0b
SP		 600 u32 inbound_msg_0; /*0010h*/
601 u32 inbound_msg_1; /*0014h*/
602 u32 outbound_msg_0; /*0018h*/
603 u32 outbound_msg_1; /*001Ch*/
c4a3e0a5 604
f9876f0b
SP		 605 u32 inbound_doorbell; /*0020h*/
606 u32 inbound_intr_status; /*0024h*/
607 u32 inbound_intr_mask; /*0028h*/
c4a3e0a5 608
f9876f0b
SP		 609 u32 outbound_doorbell; /*002Ch*/
610 u32 outbound_intr_status; /*0030h*/
611 u32 outbound_intr_mask; /*0034h*/
c4a3e0a5 612
f9876f0b 613 u32 reserved_1[2]; /*0038h*/
c4a3e0a5 614
f9876f0b
SP		 615 u32 inbound_queue_port; /*0040h*/
616 u32 outbound_queue_port; /*0044h*/
c4a3e0a5 617
f9876f0b 618 u32 reserved_2[22]; /*0048h*/
c4a3e0a5 619
f9876f0b 620 u32 outbound_doorbell_clear; /*00A0h*/
c4a3e0a5 621
f9876f0b
SP		 622 u32 reserved_3[3]; /*00A4h*/
623
624 u32 outbound_scratch_pad ; /*00B0h*/
625
626 u32 reserved_4[3]; /*00B4h*/
627
628 u32 inbound_low_queue_port ; /*00C0h*/
629
630 u32 inbound_high_queue_port ; /*00C4h*/
631
632 u32 reserved_5; /*00C8h*/
633 u32 index_registers[820]; /*00CCh*/
c4a3e0a5
BS		 634
635} __attribute__ ((packed));
636
637struct megasas_sge32 {
638
639 u32 phys_addr;
640 u32 length;
641
642} __attribute__ ((packed));
643
644struct megasas_sge64 {
645
646 u64 phys_addr;
647 u32 length;
648
649} __attribute__ ((packed));
650
651union megasas_sgl {
652
653 struct megasas_sge32 sge32[1];
654 struct megasas_sge64 sge64[1];
655
656} __attribute__ ((packed));
657
658struct megasas_header {
659
660 u8 cmd; /*00h */
661 u8 sense_len; /*01h */
662 u8 cmd_status; /*02h */
663 u8 scsi_status; /*03h */
664
665 u8 target_id; /*04h */
666 u8 lun; /*05h */
667 u8 cdb_len; /*06h */
668 u8 sge_count; /*07h */
669
670 u32 context; /*08h */
671 u32 pad_0; /*0Ch */
672
673 u16 flags; /*10h */
674 u16 timeout; /*12h */
675 u32 data_xferlen; /*14h */
676
677} __attribute__ ((packed));
678
679union megasas_sgl_frame {
680
681 struct megasas_sge32 sge32[8];
682 struct megasas_sge64 sge64[5];
683
684} __attribute__ ((packed));
685
686struct megasas_init_frame {
687
688 u8 cmd; /*00h */
689 u8 reserved_0; /*01h */
690 u8 cmd_status; /*02h */
691
692 u8 reserved_1; /*03h */
693 u32 reserved_2; /*04h */
694
695 u32 context; /*08h */
696 u32 pad_0; /*0Ch */
697
698 u16 flags; /*10h */
699 u16 reserved_3; /*12h */
700 u32 data_xfer_len; /*14h */
701
702 u32 queue_info_new_phys_addr_lo; /*18h */
703 u32 queue_info_new_phys_addr_hi; /*1Ch */
704 u32 queue_info_old_phys_addr_lo; /*20h */
705 u32 queue_info_old_phys_addr_hi; /*24h */
706
707 u32 reserved_4[6]; /*28h */
708
709} __attribute__ ((packed));
710
711struct megasas_init_queue_info {
712
713 u32 init_flags; /*00h */
714 u32 reply_queue_entries; /*04h */
715
716 u32 reply_queue_start_phys_addr_lo; /*08h */
717 u32 reply_queue_start_phys_addr_hi; /*0Ch */
718 u32 producer_index_phys_addr_lo; /*10h */
719 u32 producer_index_phys_addr_hi; /*14h */
720 u32 consumer_index_phys_addr_lo; /*18h */
721 u32 consumer_index_phys_addr_hi; /*1Ch */
722
723} __attribute__ ((packed));
724
725struct megasas_io_frame {
726
727 u8 cmd; /*00h */
728 u8 sense_len; /*01h */
729 u8 cmd_status; /*02h */
730 u8 scsi_status; /*03h */
731
732 u8 target_id; /*04h */
733 u8 access_byte; /*05h */
734 u8 reserved_0; /*06h */
735 u8 sge_count; /*07h */
736
737 u32 context; /*08h */
738 u32 pad_0; /*0Ch */
739
740 u16 flags; /*10h */
741 u16 timeout; /*12h */
742 u32 lba_count; /*14h */
743
744 u32 sense_buf_phys_addr_lo; /*18h */
745 u32 sense_buf_phys_addr_hi; /*1Ch */
746
747 u32 start_lba_lo; /*20h */
748 u32 start_lba_hi; /*24h */
749
750 union megasas_sgl sgl; /*28h */
751
752} __attribute__ ((packed));
753
754struct megasas_pthru_frame {
755
756 u8 cmd; /*00h */
757 u8 sense_len; /*01h */
758 u8 cmd_status; /*02h */
759 u8 scsi_status; /*03h */
760
761 u8 target_id; /*04h */
762 u8 lun; /*05h */
763 u8 cdb_len; /*06h */
764 u8 sge_count; /*07h */
765
766 u32 context; /*08h */
767 u32 pad_0; /*0Ch */
768
769 u16 flags; /*10h */
770 u16 timeout; /*12h */
771 u32 data_xfer_len; /*14h */
772
773 u32 sense_buf_phys_addr_lo; /*18h */
774 u32 sense_buf_phys_addr_hi; /*1Ch */
775
776 u8 cdb[16]; /*20h */
777 union megasas_sgl sgl; /*30h */
778
779} __attribute__ ((packed));
780
781struct megasas_dcmd_frame {
782
783 u8 cmd; /*00h */
784 u8 reserved_0; /*01h */
785 u8 cmd_status; /*02h */
786 u8 reserved_1[4]; /*03h */
787 u8 sge_count; /*07h */
788
789 u32 context; /*08h */
790 u32 pad_0; /*0Ch */
791
792 u16 flags; /*10h */
793 u16 timeout; /*12h */
794
795 u32 data_xfer_len; /*14h */
796 u32 opcode; /*18h */
797
798 union { /*1Ch */
799 u8 b[12];
800 u16 s[6];
801 u32 w[3];
802 } mbox;
803
804 union megasas_sgl sgl; /*28h */
805
806} __attribute__ ((packed));
807
808struct megasas_abort_frame {
809
810 u8 cmd; /*00h */
811 u8 reserved_0; /*01h */
812 u8 cmd_status; /*02h */
813
814 u8 reserved_1; /*03h */
815 u32 reserved_2; /*04h */
816
817 u32 context; /*08h */
818 u32 pad_0; /*0Ch */
819
820 u16 flags; /*10h */
821 u16 reserved_3; /*12h */
822 u32 reserved_4; /*14h */
823
824 u32 abort_context; /*18h */
825 u32 pad_1; /*1Ch */
826
827 u32 abort_mfi_phys_addr_lo; /*20h */
828 u32 abort_mfi_phys_addr_hi; /*24h */
829
830 u32 reserved_5[6]; /*28h */
831
832} __attribute__ ((packed));
833
834struct megasas_smp_frame {
835
836 u8 cmd; /*00h */
837 u8 reserved_1; /*01h */
838 u8 cmd_status; /*02h */
839 u8 connection_status; /*03h */
840
841 u8 reserved_2[3]; /*04h */
842 u8 sge_count; /*07h */
843
844 u32 context; /*08h */
845 u32 pad_0; /*0Ch */
846
847 u16 flags; /*10h */
848 u16 timeout; /*12h */
849
850 u32 data_xfer_len; /*14h */
851 u64 sas_addr; /*18h */
852
853 union {
854 struct megasas_sge32 sge32[2]; /* [0]: resp [1]: req */
855 struct megasas_sge64 sge64[2]; /* [0]: resp [1]: req */
856 } sgl;
857
858} __attribute__ ((packed));
859
860struct megasas_stp_frame {
861
862 u8 cmd; /*00h */
863 u8 reserved_1; /*01h */
864 u8 cmd_status; /*02h */
865 u8 reserved_2; /*03h */
866
867 u8 target_id; /*04h */
868 u8 reserved_3[2]; /*05h */
869 u8 sge_count; /*07h */
870
871 u32 context; /*08h */
872 u32 pad_0; /*0Ch */
873
874 u16 flags; /*10h */
875 u16 timeout; /*12h */
876
877 u32 data_xfer_len; /*14h */
878
879 u16 fis[10]; /*18h */
880 u32 stp_flags;
881
882 union {
883 struct megasas_sge32 sge32[2]; /* [0]: resp [1]: data */
884 struct megasas_sge64 sge64[2]; /* [0]: resp [1]: data */
885 } sgl;
886
887} __attribute__ ((packed));
888
889union megasas_frame {
890
891 struct megasas_header hdr;
892 struct megasas_init_frame init;
893 struct megasas_io_frame io;
894 struct megasas_pthru_frame pthru;
895 struct megasas_dcmd_frame dcmd;
896 struct megasas_abort_frame abort;
897 struct megasas_smp_frame smp;
898 struct megasas_stp_frame stp;
899
900 u8 raw_bytes[64];
901};
902
903struct megasas_cmd;
904
905union megasas_evt_class_locale {
906
907 struct {
908 u16 locale;
909 u8 reserved;
910 s8 class;
911 } __attribute__ ((packed)) members;
912
913 u32 word;
914
915} __attribute__ ((packed));
916
917struct megasas_evt_log_info {
918 u32 newest_seq_num;
919 u32 oldest_seq_num;
920 u32 clear_seq_num;
921 u32 shutdown_seq_num;
922 u32 boot_seq_num;
923
924} __attribute__ ((packed));
925
926struct megasas_progress {
927
928 u16 progress;
929 u16 elapsed_seconds;
930
931} __attribute__ ((packed));
932
933struct megasas_evtarg_ld {
934
935 u16 target_id;
936 u8 ld_index;
937 u8 reserved;
938
939} __attribute__ ((packed));
940
941struct megasas_evtarg_pd {
942 u16 device_id;
943 u8 encl_index;
944 u8 slot_number;
945
946} __attribute__ ((packed));
947
948struct megasas_evt_detail {
949
950 u32 seq_num;
951 u32 time_stamp;
952 u32 code;
953 union megasas_evt_class_locale cl;
954 u8 arg_type;
955 u8 reserved1[15];
956
957 union {
958 struct {
959 struct megasas_evtarg_pd pd;
960 u8 cdb_length;
961 u8 sense_length;
962 u8 reserved[2];
963 u8 cdb[16];
964 u8 sense[64];
965 } __attribute__ ((packed)) cdbSense;
966
967 struct megasas_evtarg_ld ld;
968
969 struct {
970 struct megasas_evtarg_ld ld;
971 u64 count;
972 } __attribute__ ((packed)) ld_count;
973
974 struct {
975 u64 lba;
976 struct megasas_evtarg_ld ld;
977 } __attribute__ ((packed)) ld_lba;
978
979 struct {
980 struct megasas_evtarg_ld ld;
981 u32 prevOwner;
982 u32 newOwner;
983 } __attribute__ ((packed)) ld_owner;
984
985 struct {
986 u64 ld_lba;
987 u64 pd_lba;
988 struct megasas_evtarg_ld ld;
989 struct megasas_evtarg_pd pd;
990 } __attribute__ ((packed)) ld_lba_pd_lba;
991
992 struct {
993 struct megasas_evtarg_ld ld;
994 struct megasas_progress prog;
995 } __attribute__ ((packed)) ld_prog;
996
997 struct {
998 struct megasas_evtarg_ld ld;
999 u32 prev_state;
1000 u32 new_state;
1001 } __attribute__ ((packed)) ld_state;
1002
1003 struct {
1004 u64 strip;
1005 struct megasas_evtarg_ld ld;
1006 } __attribute__ ((packed)) ld_strip;
1007
1008 struct megasas_evtarg_pd pd;
1009
1010 struct {
1011 struct megasas_evtarg_pd pd;
1012 u32 err;
1013 } __attribute__ ((packed)) pd_err;
1014
1015 struct {
1016 u64 lba;
1017 struct megasas_evtarg_pd pd;
1018 } __attribute__ ((packed)) pd_lba;
1019
1020 struct {
1021 u64 lba;
1022 struct megasas_evtarg_pd pd;
1023 struct megasas_evtarg_ld ld;
1024 } __attribute__ ((packed)) pd_lba_ld;
1025
1026 struct {
1027 struct megasas_evtarg_pd pd;
1028 struct megasas_progress prog;
1029 } __attribute__ ((packed)) pd_prog;
1030
1031 struct {
1032 struct megasas_evtarg_pd pd;
1033 u32 prevState;
1034 u32 newState;
1035 } __attribute__ ((packed)) pd_state;
1036
1037 struct {
1038 u16 vendorId;
1039 u16 deviceId;
1040 u16 subVendorId;
1041 u16 subDeviceId;
1042 } __attribute__ ((packed)) pci;
1043
1044 u32 rate;
1045 char str[96];
1046
1047 struct {
1048 u32 rtc;
1049 u32 elapsedSeconds;
1050 } __attribute__ ((packed)) time;
1051
1052 struct {
1053 u32 ecar;
1054 u32 elog;
1055 char str[64];
1056 } __attribute__ ((packed)) ecc;
1057
1058 u8 b[96];
1059 u16 s[48];
1060 u32 w[24];
1061 u64 d[12];
1062 } args;
1063
1064 char description[128];
1065
1066} __attribute__ ((packed));
1067
1341c939
SP		 1068 struct megasas_instance_template {
1069 void (*fire_cmd)(dma_addr_t ,u32 ,struct megasas_register_set __iomem *);
1070
1071 void (*enable_intr)(struct megasas_register_set __iomem *) ;
b274cab7 1072 void (*disable_intr)(struct megasas_register_set __iomem *);
1341c939
SP		 1073
1074 int (*clear_intr)(struct megasas_register_set __iomem *);
1075
1076 u32 (*read_fw_status_reg)(struct megasas_register_set __iomem *);
1077 };
1078
c4a3e0a5
BS		 1079struct megasas_instance {
1080
1081 u32 *producer;
1082 dma_addr_t producer_h;
1083 u32 *consumer;
1084 dma_addr_t consumer_h;
1085
1086 u32 *reply_queue;
1087 dma_addr_t reply_queue_h;
1088
1089 unsigned long base_addr;
1090 struct megasas_register_set __iomem *reg_set;
1091
1092 s8 init_id;
c4a3e0a5
BS		 1093
1094 u16 max_num_sge;
1095 u16 max_fw_cmds;
1096 u32 max_sectors_per_req;
1097
1098 struct megasas_cmd **cmd_list;
1099 struct list_head cmd_pool;
1100 spinlock_t cmd_pool_lock;
7343eb65 1101 /* used to synch producer, consumer ptrs in dpc */
1102 spinlock_t completion_lock;
c4a3e0a5
BS		 1103 struct dma_pool *frame_dma_pool;
1104 struct dma_pool *sense_dma_pool;
1105
1106 struct megasas_evt_detail *evt_detail;
1107 dma_addr_t evt_detail_h;
1108 struct megasas_cmd *aen_cmd;
e5a69e27 1109 struct mutex aen_mutex;
c4a3e0a5
BS		 1110 struct semaphore ioctl_sem;
1111
1112 struct Scsi_Host *host;
1113
1114 wait_queue_head_t int_cmd_wait_q;
1115 wait_queue_head_t abort_cmd_wait_q;
1116
1117 struct pci_dev *pdev;
1118 u32 unique_id;
1119
e4a082c7 1120 atomic_t fw_outstanding;
c4a3e0a5 1121 u32 hw_crit_error;
1341c939
SP		 1122
1123 struct megasas_instance_template *instancet;
5d018ad0 1124 struct tasklet_struct isr_tasklet;
05e9ebbe
SP		 1125
1126 u8 flag;
c3518837 1127 u8 unload;
05e9ebbe 1128 unsigned long last_time;
ad84db2e 1129
1130 struct timer_list io_completion_timer;
c4a3e0a5
BS		 1131};
1132
1133#define MEGASAS_IS_LOGICAL(scp) \
1134 (scp->device->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1
1135
1136#define MEGASAS_DEV_INDEX(inst, scp) \
1137 ((scp->device->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) + \
1138 scp->device->id
1139
1140struct megasas_cmd {
1141
1142 union megasas_frame *frame;
1143 dma_addr_t frame_phys_addr;
1144 u8 *sense;
1145 dma_addr_t sense_phys_addr;
1146
1147 u32 index;
1148 u8 sync_cmd;
1149 u8 cmd_status;
1150 u16 abort_aen;
1151
1152 struct list_head list;
1153 struct scsi_cmnd *scmd;
1154 struct megasas_instance *instance;
1155 u32 frame_count;
1156};
1157
1158#define MAX_MGMT_ADAPTERS 1024
1159#define MAX_IOCTL_SGE 16
1160
1161struct megasas_iocpacket {
1162
1163 u16 host_no;
1164 u16 __pad1;
1165 u32 sgl_off;
1166 u32 sge_count;
1167 u32 sense_off;
1168 u32 sense_len;
1169 union {
1170 u8 raw[128];
1171 struct megasas_header hdr;
1172 } frame;
1173
1174 struct iovec sgl[MAX_IOCTL_SGE];
1175
1176} __attribute__ ((packed));
1177
1178struct megasas_aen {
1179 u16 host_no;
1180 u16 __pad1;
1181 u32 seq_num;
1182 u32 class_locale_word;
1183} __attribute__ ((packed));
1184
1185#ifdef CONFIG_COMPAT
1186struct compat_megasas_iocpacket {
1187 u16 host_no;
1188 u16 __pad1;
1189 u32 sgl_off;
1190 u32 sge_count;
1191 u32 sense_off;
1192 u32 sense_len;
1193 union {
1194 u8 raw[128];
1195 struct megasas_header hdr;
1196 } frame;
1197 struct compat_iovec sgl[MAX_IOCTL_SGE];
1198} __attribute__ ((packed));
1199
0e98936c 1200#define MEGASAS_IOC_FIRMWARE32 _IOWR('M', 1, struct compat_megasas_iocpacket)
c4a3e0a5
BS		 1201#endif
1202
cb59aa6a 1203#define MEGASAS_IOC_FIRMWARE _IOWR('M', 1, struct megasas_iocpacket)
c4a3e0a5
BS		 1204#define MEGASAS_IOC_GET_AEN _IOW('M', 3, struct megasas_aen)
1205
1206struct megasas_mgmt_info {
1207
1208 u16 count;
1209 struct megasas_instance *instance[MAX_MGMT_ADAPTERS];
1210 int max_index;
1211};
1212
1213#endif /*LSI_MEGARAID_SAS_H */
Linux kernel - Deliverables
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