Commit | Line | Data |
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9c915a8c | 1 | /* |
2 | * Linux MegaRAID driver for SAS based RAID controllers | |
3 | * | |
e399065b SS |
4 | * Copyright (c) 2009-2013 LSI Corporation |
5 | * Copyright (c) 2013-2014 Avago Technologies | |
9c915a8c | 6 | * |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; either version 2 | |
10 | * of the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
e399065b | 18 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
9c915a8c | 19 | * |
20 | * FILE: megaraid_sas_fp.c | |
21 | * | |
e399065b | 22 | * Authors: Avago Technologies |
9c915a8c | 23 | * Sumant Patro |
24 | * Varad Talamacki | |
25 | * Manoj Jose | |
e399065b SS |
26 | * Kashyap Desai <kashyap.desai@avagotech.com> |
27 | * Sumit Saxena <sumit.saxena@avagotech.com> | |
9c915a8c | 28 | * |
e399065b | 29 | * Send feedback to: megaraidlinux.pdl@avagotech.com |
9c915a8c | 30 | * |
e399065b SS |
31 | * Mail to: Avago Technologies, 350 West Trimble Road, Building 90, |
32 | * San Jose, California 95131 | |
9c915a8c | 33 | */ |
34 | ||
35 | #include <linux/kernel.h> | |
36 | #include <linux/types.h> | |
37 | #include <linux/pci.h> | |
38 | #include <linux/list.h> | |
39 | #include <linux/moduleparam.h> | |
40 | #include <linux/module.h> | |
41 | #include <linux/spinlock.h> | |
42 | #include <linux/interrupt.h> | |
43 | #include <linux/delay.h> | |
9c915a8c | 44 | #include <linux/uio.h> |
45 | #include <linux/uaccess.h> | |
46 | #include <linux/fs.h> | |
47 | #include <linux/compat.h> | |
48 | #include <linux/blkdev.h> | |
49 | #include <linux/poll.h> | |
50 | ||
51 | #include <scsi/scsi.h> | |
52 | #include <scsi/scsi_cmnd.h> | |
53 | #include <scsi/scsi_device.h> | |
54 | #include <scsi/scsi_host.h> | |
55 | ||
56 | #include "megaraid_sas_fusion.h" | |
36807e67 | 57 | #include "megaraid_sas.h" |
9c915a8c | 58 | #include <asm/div64.h> |
59 | ||
d2552ebe SS |
60 | #define LB_PENDING_CMDS_DEFAULT 4 |
61 | static unsigned int lb_pending_cmds = LB_PENDING_CMDS_DEFAULT; | |
62 | module_param(lb_pending_cmds, int, S_IRUGO); | |
63 | MODULE_PARM_DESC(lb_pending_cmds, "Change raid-1 load balancing outstanding " | |
64 | "threshold. Valid Values are 1-128. Default: 4"); | |
65 | ||
66 | ||
9c915a8c | 67 | #define ABS_DIFF(a, b) (((a) > (b)) ? ((a) - (b)) : ((b) - (a))) |
68 | #define MR_LD_STATE_OPTIMAL 3 | |
69 | #define FALSE 0 | |
70 | #define TRUE 1 | |
71 | ||
bc93d425 SS |
72 | #define SPAN_DEBUG 0 |
73 | #define SPAN_ROW_SIZE(map, ld, index_) (MR_LdSpanPtrGet(ld, index_, map)->spanRowSize) | |
74 | #define SPAN_ROW_DATA_SIZE(map_, ld, index_) (MR_LdSpanPtrGet(ld, index_, map)->spanRowDataSize) | |
75 | #define SPAN_INVALID 0xff | |
76 | ||
9c915a8c | 77 | /* Prototypes */ |
51087a86 | 78 | static void mr_update_span_set(struct MR_DRV_RAID_MAP_ALL *map, |
bc93d425 SS |
79 | PLD_SPAN_INFO ldSpanInfo); |
80 | static u8 mr_spanset_get_phy_params(struct megasas_instance *instance, u32 ld, | |
81 | u64 stripRow, u16 stripRef, struct IO_REQUEST_INFO *io_info, | |
51087a86 | 82 | struct RAID_CONTEXT *pRAID_Context, struct MR_DRV_RAID_MAP_ALL *map); |
bc93d425 | 83 | static u64 get_row_from_strip(struct megasas_instance *instance, u32 ld, |
51087a86 | 84 | u64 strip, struct MR_DRV_RAID_MAP_ALL *map); |
9c915a8c | 85 | |
86 | u32 mega_mod64(u64 dividend, u32 divisor) | |
87 | { | |
88 | u64 d; | |
89 | u32 remainder; | |
90 | ||
91 | if (!divisor) | |
92 | printk(KERN_ERR "megasas : DIVISOR is zero, in div fn\n"); | |
93 | d = dividend; | |
94 | remainder = do_div(d, divisor); | |
95 | return remainder; | |
96 | } | |
97 | ||
98 | /** | |
99 | * @param dividend : Dividend | |
100 | * @param divisor : Divisor | |
101 | * | |
102 | * @return quotient | |
103 | **/ | |
104 | u64 mega_div64_32(uint64_t dividend, uint32_t divisor) | |
105 | { | |
106 | u32 remainder; | |
107 | u64 d; | |
108 | ||
109 | if (!divisor) | |
110 | printk(KERN_ERR "megasas : DIVISOR is zero in mod fn\n"); | |
111 | ||
112 | d = dividend; | |
113 | remainder = do_div(d, divisor); | |
114 | ||
115 | return d; | |
116 | } | |
117 | ||
51087a86 | 118 | struct MR_LD_RAID *MR_LdRaidGet(u32 ld, struct MR_DRV_RAID_MAP_ALL *map) |
9c915a8c | 119 | { |
120 | return &map->raidMap.ldSpanMap[ld].ldRaid; | |
121 | } | |
122 | ||
123 | static struct MR_SPAN_BLOCK_INFO *MR_LdSpanInfoGet(u32 ld, | |
51087a86 | 124 | struct MR_DRV_RAID_MAP_ALL |
9c915a8c | 125 | *map) |
126 | { | |
127 | return &map->raidMap.ldSpanMap[ld].spanBlock[0]; | |
128 | } | |
129 | ||
51087a86 | 130 | static u8 MR_LdDataArmGet(u32 ld, u32 armIdx, struct MR_DRV_RAID_MAP_ALL *map) |
9c915a8c | 131 | { |
132 | return map->raidMap.ldSpanMap[ld].dataArmMap[armIdx]; | |
133 | } | |
134 | ||
51087a86 | 135 | u16 MR_ArPdGet(u32 ar, u32 arm, struct MR_DRV_RAID_MAP_ALL *map) |
9c915a8c | 136 | { |
94cd65dd | 137 | return le16_to_cpu(map->raidMap.arMapInfo[ar].pd[arm]); |
9c915a8c | 138 | } |
139 | ||
51087a86 | 140 | u16 MR_LdSpanArrayGet(u32 ld, u32 span, struct MR_DRV_RAID_MAP_ALL *map) |
9c915a8c | 141 | { |
94cd65dd | 142 | return le16_to_cpu(map->raidMap.ldSpanMap[ld].spanBlock[span].span.arrayRef); |
9c915a8c | 143 | } |
144 | ||
51087a86 | 145 | u16 MR_PdDevHandleGet(u32 pd, struct MR_DRV_RAID_MAP_ALL *map) |
9c915a8c | 146 | { |
147 | return map->raidMap.devHndlInfo[pd].curDevHdl; | |
148 | } | |
149 | ||
51087a86 | 150 | u16 MR_GetLDTgtId(u32 ld, struct MR_DRV_RAID_MAP_ALL *map) |
9c915a8c | 151 | { |
be26374b | 152 | return le16_to_cpu(map->raidMap.ldSpanMap[ld].ldRaid.targetId); |
9c915a8c | 153 | } |
154 | ||
51087a86 | 155 | u8 MR_TargetIdToLdGet(u32 ldTgtId, struct MR_DRV_RAID_MAP_ALL *map) |
9c915a8c | 156 | { |
be26374b | 157 | return map->raidMap.ldTgtIdToLd[ldTgtId]; |
9c915a8c | 158 | } |
159 | ||
160 | static struct MR_LD_SPAN *MR_LdSpanPtrGet(u32 ld, u32 span, | |
51087a86 | 161 | struct MR_DRV_RAID_MAP_ALL *map) |
9c915a8c | 162 | { |
163 | return &map->raidMap.ldSpanMap[ld].spanBlock[span].span; | |
164 | } | |
165 | ||
51087a86 SS |
166 | /* |
167 | * This function will Populate Driver Map using firmware raid map | |
168 | */ | |
169 | void MR_PopulateDrvRaidMap(struct megasas_instance *instance) | |
170 | { | |
171 | struct fusion_context *fusion = instance->ctrl_context; | |
172 | struct MR_FW_RAID_MAP_ALL *fw_map_old = NULL; | |
173 | struct MR_FW_RAID_MAP *pFwRaidMap = NULL; | |
174 | int i; | |
175 | ||
176 | ||
177 | struct MR_DRV_RAID_MAP_ALL *drv_map = | |
178 | fusion->ld_drv_map[(instance->map_id & 1)]; | |
179 | struct MR_DRV_RAID_MAP *pDrvRaidMap = &drv_map->raidMap; | |
180 | ||
181 | if (instance->supportmax256vd) { | |
182 | memcpy(fusion->ld_drv_map[instance->map_id & 1], | |
183 | fusion->ld_map[instance->map_id & 1], | |
184 | fusion->current_map_sz); | |
185 | /* New Raid map will not set totalSize, so keep expected value | |
186 | * for legacy code in ValidateMapInfo | |
187 | */ | |
6e755ddc SS |
188 | pDrvRaidMap->totalSize = |
189 | cpu_to_le32(sizeof(struct MR_FW_RAID_MAP_EXT)); | |
51087a86 SS |
190 | } else { |
191 | fw_map_old = (struct MR_FW_RAID_MAP_ALL *) | |
192 | fusion->ld_map[(instance->map_id & 1)]; | |
193 | pFwRaidMap = &fw_map_old->raidMap; | |
194 | ||
195 | #if VD_EXT_DEBUG | |
6e755ddc | 196 | for (i = 0; i < le16_to_cpu(pFwRaidMap->ldCount); i++) { |
51087a86 SS |
197 | dev_dbg(&instance->pdev->dev, "(%d) :Index 0x%x " |
198 | "Target Id 0x%x Seq Num 0x%x Size 0/%llx\n", | |
199 | instance->unique_id, i, | |
200 | fw_map_old->raidMap.ldSpanMap[i].ldRaid.targetId, | |
201 | fw_map_old->raidMap.ldSpanMap[i].ldRaid.seqNum, | |
202 | fw_map_old->raidMap.ldSpanMap[i].ldRaid.size); | |
203 | } | |
204 | #endif | |
205 | ||
206 | memset(drv_map, 0, fusion->drv_map_sz); | |
207 | pDrvRaidMap->totalSize = pFwRaidMap->totalSize; | |
6e755ddc | 208 | pDrvRaidMap->ldCount = (__le16)pFwRaidMap->ldCount; |
51087a86 SS |
209 | pDrvRaidMap->fpPdIoTimeoutSec = pFwRaidMap->fpPdIoTimeoutSec; |
210 | for (i = 0; i < MAX_RAIDMAP_LOGICAL_DRIVES + MAX_RAIDMAP_VIEWS; i++) | |
211 | pDrvRaidMap->ldTgtIdToLd[i] = | |
212 | (u8)pFwRaidMap->ldTgtIdToLd[i]; | |
6e755ddc | 213 | for (i = 0; i < le16_to_cpu(pDrvRaidMap->ldCount); i++) { |
51087a86 SS |
214 | pDrvRaidMap->ldSpanMap[i] = pFwRaidMap->ldSpanMap[i]; |
215 | #if VD_EXT_DEBUG | |
216 | dev_dbg(&instance->pdev->dev, | |
217 | "pFwRaidMap->ldSpanMap[%d].ldRaid.targetId 0x%x " | |
218 | "pFwRaidMap->ldSpanMap[%d].ldRaid.seqNum 0x%x " | |
219 | "size 0x%x\n", i, i, | |
220 | pFwRaidMap->ldSpanMap[i].ldRaid.targetId, | |
221 | pFwRaidMap->ldSpanMap[i].ldRaid.seqNum, | |
222 | (u32)pFwRaidMap->ldSpanMap[i].ldRaid.rowSize); | |
223 | dev_dbg(&instance->pdev->dev, | |
224 | "pDrvRaidMap->ldSpanMap[%d].ldRaid.targetId 0x%x " | |
225 | "pDrvRaidMap->ldSpanMap[%d].ldRaid.seqNum 0x%x " | |
226 | "size 0x%x\n", i, i, | |
227 | pDrvRaidMap->ldSpanMap[i].ldRaid.targetId, | |
228 | pDrvRaidMap->ldSpanMap[i].ldRaid.seqNum, | |
229 | (u32)pDrvRaidMap->ldSpanMap[i].ldRaid.rowSize); | |
230 | dev_dbg(&instance->pdev->dev, "Driver raid map all %p " | |
231 | "raid map %p LD RAID MAP %p/%p\n", drv_map, | |
232 | pDrvRaidMap, &pFwRaidMap->ldSpanMap[i].ldRaid, | |
233 | &pDrvRaidMap->ldSpanMap[i].ldRaid); | |
234 | #endif | |
235 | } | |
236 | memcpy(pDrvRaidMap->arMapInfo, pFwRaidMap->arMapInfo, | |
237 | sizeof(struct MR_ARRAY_INFO) * MAX_RAIDMAP_ARRAYS); | |
238 | memcpy(pDrvRaidMap->devHndlInfo, pFwRaidMap->devHndlInfo, | |
239 | sizeof(struct MR_DEV_HANDLE_INFO) * | |
240 | MAX_RAIDMAP_PHYSICAL_DEVICES); | |
241 | } | |
242 | } | |
243 | ||
9c915a8c | 244 | /* |
245 | * This function will validate Map info data provided by FW | |
246 | */ | |
bc93d425 | 247 | u8 MR_ValidateMapInfo(struct megasas_instance *instance) |
9c915a8c | 248 | { |
51087a86 SS |
249 | struct fusion_context *fusion; |
250 | struct MR_DRV_RAID_MAP_ALL *drv_map; | |
251 | struct MR_DRV_RAID_MAP *pDrvRaidMap; | |
252 | struct LD_LOAD_BALANCE_INFO *lbInfo; | |
253 | PLD_SPAN_INFO ldSpanInfo; | |
94cd65dd SS |
254 | struct MR_LD_RAID *raid; |
255 | int ldCount, num_lds; | |
256 | u16 ld; | |
51087a86 | 257 | u32 expected_size; |
94cd65dd | 258 | |
9c915a8c | 259 | |
51087a86 SS |
260 | MR_PopulateDrvRaidMap(instance); |
261 | ||
262 | fusion = instance->ctrl_context; | |
263 | drv_map = fusion->ld_drv_map[(instance->map_id & 1)]; | |
264 | pDrvRaidMap = &drv_map->raidMap; | |
265 | ||
266 | lbInfo = fusion->load_balance_info; | |
267 | ldSpanInfo = fusion->log_to_span; | |
268 | ||
269 | if (instance->supportmax256vd) | |
270 | expected_size = sizeof(struct MR_FW_RAID_MAP_EXT); | |
271 | else | |
272 | expected_size = | |
273 | (sizeof(struct MR_FW_RAID_MAP) - sizeof(struct MR_LD_SPAN_MAP) + | |
6e755ddc | 274 | (sizeof(struct MR_LD_SPAN_MAP) * le16_to_cpu(pDrvRaidMap->ldCount))); |
51087a86 SS |
275 | |
276 | if (le32_to_cpu(pDrvRaidMap->totalSize) != expected_size) { | |
277 | dev_err(&instance->pdev->dev, "map info structure size 0x%x is not matching with ld count\n", | |
278 | (unsigned int) expected_size); | |
279 | dev_err(&instance->pdev->dev, "megasas: span map %x, pDrvRaidMap->totalSize : %x\n", | |
280 | (unsigned int)sizeof(struct MR_LD_SPAN_MAP), | |
281 | le32_to_cpu(pDrvRaidMap->totalSize)); | |
9c915a8c | 282 | return 0; |
283 | } | |
284 | ||
bc93d425 | 285 | if (instance->UnevenSpanSupport) |
51087a86 | 286 | mr_update_span_set(drv_map, ldSpanInfo); |
bc93d425 | 287 | |
51087a86 | 288 | mr_update_load_balance_params(drv_map, lbInfo); |
9c915a8c | 289 | |
6e755ddc | 290 | num_lds = le16_to_cpu(drv_map->raidMap.ldCount); |
94cd65dd SS |
291 | |
292 | /*Convert Raid capability values to CPU arch */ | |
293 | for (ldCount = 0; ldCount < num_lds; ldCount++) { | |
51087a86 SS |
294 | ld = MR_TargetIdToLdGet(ldCount, drv_map); |
295 | raid = MR_LdRaidGet(ld, drv_map); | |
94cd65dd SS |
296 | le32_to_cpus((u32 *)&raid->capability); |
297 | } | |
298 | ||
9c915a8c | 299 | return 1; |
300 | } | |
301 | ||
302 | u32 MR_GetSpanBlock(u32 ld, u64 row, u64 *span_blk, | |
51087a86 | 303 | struct MR_DRV_RAID_MAP_ALL *map) |
9c915a8c | 304 | { |
305 | struct MR_SPAN_BLOCK_INFO *pSpanBlock = MR_LdSpanInfoGet(ld, map); | |
306 | struct MR_QUAD_ELEMENT *quad; | |
307 | struct MR_LD_RAID *raid = MR_LdRaidGet(ld, map); | |
308 | u32 span, j; | |
309 | ||
310 | for (span = 0; span < raid->spanDepth; span++, pSpanBlock++) { | |
311 | ||
94cd65dd | 312 | for (j = 0; j < le32_to_cpu(pSpanBlock->block_span_info.noElements); j++) { |
9c915a8c | 313 | quad = &pSpanBlock->block_span_info.quad[j]; |
314 | ||
94cd65dd | 315 | if (le32_to_cpu(quad->diff) == 0) |
bc93d425 | 316 | return SPAN_INVALID; |
94cd65dd SS |
317 | if (le64_to_cpu(quad->logStart) <= row && row <= |
318 | le64_to_cpu(quad->logEnd) && (mega_mod64(row - le64_to_cpu(quad->logStart), | |
319 | le32_to_cpu(quad->diff))) == 0) { | |
9c915a8c | 320 | if (span_blk != NULL) { |
321 | u64 blk, debugBlk; | |
94cd65dd | 322 | blk = mega_div64_32((row-le64_to_cpu(quad->logStart)), le32_to_cpu(quad->diff)); |
9c915a8c | 323 | debugBlk = blk; |
324 | ||
94cd65dd | 325 | blk = (blk + le64_to_cpu(quad->offsetInSpan)) << raid->stripeShift; |
9c915a8c | 326 | *span_blk = blk; |
327 | } | |
328 | return span; | |
329 | } | |
330 | } | |
331 | } | |
bc93d425 SS |
332 | return SPAN_INVALID; |
333 | } | |
334 | ||
335 | /* | |
336 | ****************************************************************************** | |
337 | * | |
338 | * Function to print info about span set created in driver from FW raid map | |
339 | * | |
340 | * Inputs : | |
341 | * map - LD map | |
342 | * ldSpanInfo - ldSpanInfo per HBA instance | |
343 | */ | |
344 | #if SPAN_DEBUG | |
51087a86 SS |
345 | static int getSpanInfo(struct MR_DRV_RAID_MAP_ALL *map, |
346 | PLD_SPAN_INFO ldSpanInfo) | |
bc93d425 SS |
347 | { |
348 | ||
349 | u8 span; | |
350 | u32 element; | |
351 | struct MR_LD_RAID *raid; | |
352 | LD_SPAN_SET *span_set; | |
353 | struct MR_QUAD_ELEMENT *quad; | |
354 | int ldCount; | |
355 | u16 ld; | |
356 | ||
51087a86 | 357 | for (ldCount = 0; ldCount < MAX_LOGICAL_DRIVES_EXT; ldCount++) { |
bc93d425 | 358 | ld = MR_TargetIdToLdGet(ldCount, map); |
51087a86 | 359 | if (ld >= MAX_LOGICAL_DRIVES_EXT) |
bc93d425 SS |
360 | continue; |
361 | raid = MR_LdRaidGet(ld, map); | |
362 | dev_dbg(&instance->pdev->dev, "LD %x: span_depth=%x\n", | |
363 | ld, raid->spanDepth); | |
364 | for (span = 0; span < raid->spanDepth; span++) | |
365 | dev_dbg(&instance->pdev->dev, "Span=%x," | |
366 | " number of quads=%x\n", span, | |
94cd65dd SS |
367 | le32_to_cpu(map->raidMap.ldSpanMap[ld].spanBlock[span]. |
368 | block_span_info.noElements)); | |
bc93d425 SS |
369 | for (element = 0; element < MAX_QUAD_DEPTH; element++) { |
370 | span_set = &(ldSpanInfo[ld].span_set[element]); | |
371 | if (span_set->span_row_data_width == 0) | |
372 | break; | |
373 | ||
374 | dev_dbg(&instance->pdev->dev, "Span Set %x:" | |
375 | "width=%x, diff=%x\n", element, | |
376 | (unsigned int)span_set->span_row_data_width, | |
377 | (unsigned int)span_set->diff); | |
378 | dev_dbg(&instance->pdev->dev, "logical LBA" | |
379 | "start=0x%08lx, end=0x%08lx\n", | |
380 | (long unsigned int)span_set->log_start_lba, | |
381 | (long unsigned int)span_set->log_end_lba); | |
382 | dev_dbg(&instance->pdev->dev, "span row start=0x%08lx," | |
383 | " end=0x%08lx\n", | |
384 | (long unsigned int)span_set->span_row_start, | |
385 | (long unsigned int)span_set->span_row_end); | |
386 | dev_dbg(&instance->pdev->dev, "data row start=0x%08lx," | |
387 | " end=0x%08lx\n", | |
388 | (long unsigned int)span_set->data_row_start, | |
389 | (long unsigned int)span_set->data_row_end); | |
390 | dev_dbg(&instance->pdev->dev, "data strip start=0x%08lx," | |
391 | " end=0x%08lx\n", | |
392 | (long unsigned int)span_set->data_strip_start, | |
393 | (long unsigned int)span_set->data_strip_end); | |
394 | ||
395 | for (span = 0; span < raid->spanDepth; span++) { | |
94cd65dd SS |
396 | if (le32_to_cpu(map->raidMap.ldSpanMap[ld].spanBlock[span]. |
397 | block_span_info.noElements) >= | |
bc93d425 SS |
398 | element + 1) { |
399 | quad = &map->raidMap.ldSpanMap[ld]. | |
400 | spanBlock[span].block_span_info. | |
401 | quad[element]; | |
402 | dev_dbg(&instance->pdev->dev, "Span=%x," | |
403 | "Quad=%x, diff=%x\n", span, | |
94cd65dd | 404 | element, le32_to_cpu(quad->diff)); |
bc93d425 SS |
405 | dev_dbg(&instance->pdev->dev, |
406 | "offset_in_span=0x%08lx\n", | |
94cd65dd | 407 | (long unsigned int)le64_to_cpu(quad->offsetInSpan)); |
bc93d425 SS |
408 | dev_dbg(&instance->pdev->dev, |
409 | "logical start=0x%08lx, end=0x%08lx\n", | |
94cd65dd SS |
410 | (long unsigned int)le64_to_cpu(quad->logStart), |
411 | (long unsigned int)le64_to_cpu(quad->logEnd)); | |
bc93d425 SS |
412 | } |
413 | } | |
414 | } | |
415 | } | |
416 | return 0; | |
417 | } | |
418 | #endif | |
419 | ||
420 | /* | |
421 | ****************************************************************************** | |
422 | * | |
423 | * This routine calculates the Span block for given row using spanset. | |
424 | * | |
425 | * Inputs : | |
426 | * instance - HBA instance | |
427 | * ld - Logical drive number | |
428 | * row - Row number | |
429 | * map - LD map | |
430 | * | |
431 | * Outputs : | |
432 | * | |
433 | * span - Span number | |
434 | * block - Absolute Block number in the physical disk | |
435 | * div_error - Devide error code. | |
436 | */ | |
437 | ||
438 | u32 mr_spanset_get_span_block(struct megasas_instance *instance, | |
51087a86 | 439 | u32 ld, u64 row, u64 *span_blk, struct MR_DRV_RAID_MAP_ALL *map) |
bc93d425 SS |
440 | { |
441 | struct fusion_context *fusion = instance->ctrl_context; | |
442 | struct MR_LD_RAID *raid = MR_LdRaidGet(ld, map); | |
443 | LD_SPAN_SET *span_set; | |
444 | struct MR_QUAD_ELEMENT *quad; | |
445 | u32 span, info; | |
446 | PLD_SPAN_INFO ldSpanInfo = fusion->log_to_span; | |
447 | ||
448 | for (info = 0; info < MAX_QUAD_DEPTH; info++) { | |
449 | span_set = &(ldSpanInfo[ld].span_set[info]); | |
450 | ||
451 | if (span_set->span_row_data_width == 0) | |
452 | break; | |
453 | ||
454 | if (row > span_set->data_row_end) | |
455 | continue; | |
456 | ||
457 | for (span = 0; span < raid->spanDepth; span++) | |
94cd65dd SS |
458 | if (le32_to_cpu(map->raidMap.ldSpanMap[ld].spanBlock[span]. |
459 | block_span_info.noElements) >= info+1) { | |
bc93d425 SS |
460 | quad = &map->raidMap.ldSpanMap[ld]. |
461 | spanBlock[span]. | |
462 | block_span_info.quad[info]; | |
6e755ddc | 463 | if (le32_to_cpu(quad->diff) == 0) |
bc93d425 | 464 | return SPAN_INVALID; |
94cd65dd SS |
465 | if (le64_to_cpu(quad->logStart) <= row && |
466 | row <= le64_to_cpu(quad->logEnd) && | |
467 | (mega_mod64(row - le64_to_cpu(quad->logStart), | |
468 | le32_to_cpu(quad->diff))) == 0) { | |
bc93d425 SS |
469 | if (span_blk != NULL) { |
470 | u64 blk; | |
471 | blk = mega_div64_32 | |
94cd65dd SS |
472 | ((row - le64_to_cpu(quad->logStart)), |
473 | le32_to_cpu(quad->diff)); | |
474 | blk = (blk + le64_to_cpu(quad->offsetInSpan)) | |
bc93d425 SS |
475 | << raid->stripeShift; |
476 | *span_blk = blk; | |
477 | } | |
478 | return span; | |
479 | } | |
480 | } | |
481 | } | |
482 | return SPAN_INVALID; | |
483 | } | |
484 | ||
485 | /* | |
486 | ****************************************************************************** | |
487 | * | |
488 | * This routine calculates the row for given strip using spanset. | |
489 | * | |
490 | * Inputs : | |
491 | * instance - HBA instance | |
492 | * ld - Logical drive number | |
493 | * Strip - Strip | |
494 | * map - LD map | |
495 | * | |
496 | * Outputs : | |
497 | * | |
498 | * row - row associated with strip | |
499 | */ | |
500 | ||
501 | static u64 get_row_from_strip(struct megasas_instance *instance, | |
51087a86 | 502 | u32 ld, u64 strip, struct MR_DRV_RAID_MAP_ALL *map) |
bc93d425 SS |
503 | { |
504 | struct fusion_context *fusion = instance->ctrl_context; | |
505 | struct MR_LD_RAID *raid = MR_LdRaidGet(ld, map); | |
506 | LD_SPAN_SET *span_set; | |
507 | PLD_SPAN_INFO ldSpanInfo = fusion->log_to_span; | |
508 | u32 info, strip_offset, span, span_offset; | |
509 | u64 span_set_Strip, span_set_Row, retval; | |
510 | ||
511 | for (info = 0; info < MAX_QUAD_DEPTH; info++) { | |
512 | span_set = &(ldSpanInfo[ld].span_set[info]); | |
513 | ||
514 | if (span_set->span_row_data_width == 0) | |
515 | break; | |
516 | if (strip > span_set->data_strip_end) | |
517 | continue; | |
518 | ||
519 | span_set_Strip = strip - span_set->data_strip_start; | |
520 | strip_offset = mega_mod64(span_set_Strip, | |
521 | span_set->span_row_data_width); | |
522 | span_set_Row = mega_div64_32(span_set_Strip, | |
523 | span_set->span_row_data_width) * span_set->diff; | |
524 | for (span = 0, span_offset = 0; span < raid->spanDepth; span++) | |
94cd65dd | 525 | if (le32_to_cpu(map->raidMap.ldSpanMap[ld].spanBlock[span]. |
6e755ddc | 526 | block_span_info.noElements) >= info+1) { |
bc93d425 SS |
527 | if (strip_offset >= |
528 | span_set->strip_offset[span]) | |
529 | span_offset++; | |
530 | else | |
531 | break; | |
532 | } | |
533 | #if SPAN_DEBUG | |
534 | dev_info(&instance->pdev->dev, "Strip 0x%llx," | |
535 | "span_set_Strip 0x%llx, span_set_Row 0x%llx" | |
536 | "data width 0x%llx span offset 0x%x\n", strip, | |
537 | (unsigned long long)span_set_Strip, | |
538 | (unsigned long long)span_set_Row, | |
539 | (unsigned long long)span_set->span_row_data_width, | |
540 | span_offset); | |
541 | dev_info(&instance->pdev->dev, "For strip 0x%llx" | |
542 | "row is 0x%llx\n", strip, | |
543 | (unsigned long long) span_set->data_row_start + | |
544 | (unsigned long long) span_set_Row + (span_offset - 1)); | |
545 | #endif | |
546 | retval = (span_set->data_row_start + span_set_Row + | |
547 | (span_offset - 1)); | |
548 | return retval; | |
549 | } | |
550 | return -1LLU; | |
551 | } | |
552 | ||
553 | ||
554 | /* | |
555 | ****************************************************************************** | |
556 | * | |
557 | * This routine calculates the Start Strip for given row using spanset. | |
558 | * | |
559 | * Inputs : | |
560 | * instance - HBA instance | |
561 | * ld - Logical drive number | |
562 | * row - Row number | |
563 | * map - LD map | |
564 | * | |
565 | * Outputs : | |
566 | * | |
567 | * Strip - Start strip associated with row | |
568 | */ | |
569 | ||
570 | static u64 get_strip_from_row(struct megasas_instance *instance, | |
51087a86 | 571 | u32 ld, u64 row, struct MR_DRV_RAID_MAP_ALL *map) |
bc93d425 SS |
572 | { |
573 | struct fusion_context *fusion = instance->ctrl_context; | |
574 | struct MR_LD_RAID *raid = MR_LdRaidGet(ld, map); | |
575 | LD_SPAN_SET *span_set; | |
576 | struct MR_QUAD_ELEMENT *quad; | |
577 | PLD_SPAN_INFO ldSpanInfo = fusion->log_to_span; | |
578 | u32 span, info; | |
579 | u64 strip; | |
580 | ||
581 | for (info = 0; info < MAX_QUAD_DEPTH; info++) { | |
582 | span_set = &(ldSpanInfo[ld].span_set[info]); | |
583 | ||
584 | if (span_set->span_row_data_width == 0) | |
585 | break; | |
586 | if (row > span_set->data_row_end) | |
587 | continue; | |
588 | ||
589 | for (span = 0; span < raid->spanDepth; span++) | |
94cd65dd SS |
590 | if (le32_to_cpu(map->raidMap.ldSpanMap[ld].spanBlock[span]. |
591 | block_span_info.noElements) >= info+1) { | |
bc93d425 SS |
592 | quad = &map->raidMap.ldSpanMap[ld]. |
593 | spanBlock[span].block_span_info.quad[info]; | |
94cd65dd SS |
594 | if (le64_to_cpu(quad->logStart) <= row && |
595 | row <= le64_to_cpu(quad->logEnd) && | |
596 | mega_mod64((row - le64_to_cpu(quad->logStart)), | |
597 | le32_to_cpu(quad->diff)) == 0) { | |
bc93d425 SS |
598 | strip = mega_div64_32 |
599 | (((row - span_set->data_row_start) | |
94cd65dd SS |
600 | - le64_to_cpu(quad->logStart)), |
601 | le32_to_cpu(quad->diff)); | |
bc93d425 SS |
602 | strip *= span_set->span_row_data_width; |
603 | strip += span_set->data_strip_start; | |
604 | strip += span_set->strip_offset[span]; | |
605 | return strip; | |
606 | } | |
607 | } | |
608 | } | |
609 | dev_err(&instance->pdev->dev, "get_strip_from_row" | |
610 | "returns invalid strip for ld=%x, row=%lx\n", | |
611 | ld, (long unsigned int)row); | |
612 | return -1; | |
613 | } | |
614 | ||
615 | /* | |
616 | ****************************************************************************** | |
617 | * | |
618 | * This routine calculates the Physical Arm for given strip using spanset. | |
619 | * | |
620 | * Inputs : | |
621 | * instance - HBA instance | |
622 | * ld - Logical drive number | |
623 | * strip - Strip | |
624 | * map - LD map | |
625 | * | |
626 | * Outputs : | |
627 | * | |
628 | * Phys Arm - Phys Arm associated with strip | |
629 | */ | |
630 | ||
631 | static u32 get_arm_from_strip(struct megasas_instance *instance, | |
51087a86 | 632 | u32 ld, u64 strip, struct MR_DRV_RAID_MAP_ALL *map) |
bc93d425 SS |
633 | { |
634 | struct fusion_context *fusion = instance->ctrl_context; | |
635 | struct MR_LD_RAID *raid = MR_LdRaidGet(ld, map); | |
636 | LD_SPAN_SET *span_set; | |
637 | PLD_SPAN_INFO ldSpanInfo = fusion->log_to_span; | |
638 | u32 info, strip_offset, span, span_offset, retval; | |
639 | ||
640 | for (info = 0 ; info < MAX_QUAD_DEPTH; info++) { | |
641 | span_set = &(ldSpanInfo[ld].span_set[info]); | |
642 | ||
643 | if (span_set->span_row_data_width == 0) | |
644 | break; | |
645 | if (strip > span_set->data_strip_end) | |
646 | continue; | |
647 | ||
648 | strip_offset = (uint)mega_mod64 | |
649 | ((strip - span_set->data_strip_start), | |
650 | span_set->span_row_data_width); | |
651 | ||
652 | for (span = 0, span_offset = 0; span < raid->spanDepth; span++) | |
94cd65dd SS |
653 | if (le32_to_cpu(map->raidMap.ldSpanMap[ld].spanBlock[span]. |
654 | block_span_info.noElements) >= info+1) { | |
bc93d425 SS |
655 | if (strip_offset >= |
656 | span_set->strip_offset[span]) | |
657 | span_offset = | |
658 | span_set->strip_offset[span]; | |
659 | else | |
660 | break; | |
661 | } | |
662 | #if SPAN_DEBUG | |
663 | dev_info(&instance->pdev->dev, "get_arm_from_strip:" | |
664 | "for ld=0x%x strip=0x%lx arm is 0x%x\n", ld, | |
665 | (long unsigned int)strip, (strip_offset - span_offset)); | |
666 | #endif | |
667 | retval = (strip_offset - span_offset); | |
668 | return retval; | |
669 | } | |
670 | ||
671 | dev_err(&instance->pdev->dev, "get_arm_from_strip" | |
672 | "returns invalid arm for ld=%x strip=%lx\n", | |
673 | ld, (long unsigned int)strip); | |
674 | ||
675 | return -1; | |
676 | } | |
677 | ||
678 | /* This Function will return Phys arm */ | |
679 | u8 get_arm(struct megasas_instance *instance, u32 ld, u8 span, u64 stripe, | |
51087a86 | 680 | struct MR_DRV_RAID_MAP_ALL *map) |
bc93d425 SS |
681 | { |
682 | struct MR_LD_RAID *raid = MR_LdRaidGet(ld, map); | |
683 | /* Need to check correct default value */ | |
684 | u32 arm = 0; | |
685 | ||
686 | switch (raid->level) { | |
687 | case 0: | |
688 | case 5: | |
689 | case 6: | |
690 | arm = mega_mod64(stripe, SPAN_ROW_SIZE(map, ld, span)); | |
691 | break; | |
692 | case 1: | |
693 | /* start with logical arm */ | |
694 | arm = get_arm_from_strip(instance, ld, stripe, map); | |
fec3c1b4 | 695 | if (arm != -1U) |
bc93d425 SS |
696 | arm *= 2; |
697 | break; | |
698 | } | |
699 | ||
700 | return arm; | |
701 | } | |
702 | ||
703 | ||
704 | /* | |
705 | ****************************************************************************** | |
706 | * | |
707 | * This routine calculates the arm, span and block for the specified stripe and | |
708 | * reference in stripe using spanset | |
709 | * | |
710 | * Inputs : | |
711 | * | |
712 | * ld - Logical drive number | |
713 | * stripRow - Stripe number | |
714 | * stripRef - Reference in stripe | |
715 | * | |
716 | * Outputs : | |
717 | * | |
718 | * span - Span number | |
719 | * block - Absolute Block number in the physical disk | |
720 | */ | |
721 | static u8 mr_spanset_get_phy_params(struct megasas_instance *instance, u32 ld, | |
722 | u64 stripRow, u16 stripRef, struct IO_REQUEST_INFO *io_info, | |
723 | struct RAID_CONTEXT *pRAID_Context, | |
51087a86 | 724 | struct MR_DRV_RAID_MAP_ALL *map) |
bc93d425 SS |
725 | { |
726 | struct MR_LD_RAID *raid = MR_LdRaidGet(ld, map); | |
727 | u32 pd, arRef; | |
728 | u8 physArm, span; | |
729 | u64 row; | |
730 | u8 retval = TRUE; | |
731 | u8 do_invader = 0; | |
732 | u64 *pdBlock = &io_info->pdBlock; | |
733 | u16 *pDevHandle = &io_info->devHandle; | |
734 | u32 logArm, rowMod, armQ, arm; | |
735 | ||
736 | if ((instance->pdev->device == PCI_DEVICE_ID_LSI_INVADER || | |
737 | instance->pdev->device == PCI_DEVICE_ID_LSI_FURY)) | |
738 | do_invader = 1; | |
739 | ||
740 | /*Get row and span from io_info for Uneven Span IO.*/ | |
741 | row = io_info->start_row; | |
742 | span = io_info->start_span; | |
743 | ||
744 | ||
745 | if (raid->level == 6) { | |
746 | logArm = get_arm_from_strip(instance, ld, stripRow, map); | |
fec3c1b4 | 747 | if (logArm == -1U) |
bc93d425 SS |
748 | return FALSE; |
749 | rowMod = mega_mod64(row, SPAN_ROW_SIZE(map, ld, span)); | |
750 | armQ = SPAN_ROW_SIZE(map, ld, span) - 1 - rowMod; | |
751 | arm = armQ + 1 + logArm; | |
752 | if (arm >= SPAN_ROW_SIZE(map, ld, span)) | |
753 | arm -= SPAN_ROW_SIZE(map, ld, span); | |
754 | physArm = (u8)arm; | |
755 | } else | |
756 | /* Calculate the arm */ | |
757 | physArm = get_arm(instance, ld, span, stripRow, map); | |
758 | if (physArm == 0xFF) | |
759 | return FALSE; | |
760 | ||
761 | arRef = MR_LdSpanArrayGet(ld, span, map); | |
762 | pd = MR_ArPdGet(arRef, physArm, map); | |
763 | ||
764 | if (pd != MR_PD_INVALID) | |
765 | *pDevHandle = MR_PdDevHandleGet(pd, map); | |
766 | else { | |
767 | *pDevHandle = MR_PD_INVALID; | |
768 | if ((raid->level >= 5) && | |
769 | (!do_invader || (do_invader && | |
770 | (raid->regTypeReqOnRead != REGION_TYPE_UNUSED)))) | |
771 | pRAID_Context->regLockFlags = REGION_TYPE_EXCLUSIVE; | |
772 | else if (raid->level == 1) { | |
773 | pd = MR_ArPdGet(arRef, physArm + 1, map); | |
774 | if (pd != MR_PD_INVALID) | |
775 | *pDevHandle = MR_PdDevHandleGet(pd, map); | |
776 | } | |
777 | } | |
778 | ||
94cd65dd | 779 | *pdBlock += stripRef + le64_to_cpu(MR_LdSpanPtrGet(ld, span, map)->startBlk); |
bc93d425 SS |
780 | pRAID_Context->spanArm = (span << RAID_CTX_SPANARM_SPAN_SHIFT) | |
781 | physArm; | |
d2552ebe | 782 | io_info->span_arm = pRAID_Context->spanArm; |
bc93d425 | 783 | return retval; |
9c915a8c | 784 | } |
785 | ||
786 | /* | |
787 | ****************************************************************************** | |
788 | * | |
789 | * This routine calculates the arm, span and block for the specified stripe and | |
790 | * reference in stripe. | |
791 | * | |
792 | * Inputs : | |
793 | * | |
794 | * ld - Logical drive number | |
795 | * stripRow - Stripe number | |
796 | * stripRef - Reference in stripe | |
797 | * | |
798 | * Outputs : | |
799 | * | |
800 | * span - Span number | |
801 | * block - Absolute Block number in the physical disk | |
802 | */ | |
36807e67 | 803 | u8 MR_GetPhyParams(struct megasas_instance *instance, u32 ld, u64 stripRow, |
bc93d425 SS |
804 | u16 stripRef, struct IO_REQUEST_INFO *io_info, |
805 | struct RAID_CONTEXT *pRAID_Context, | |
51087a86 | 806 | struct MR_DRV_RAID_MAP_ALL *map) |
9c915a8c | 807 | { |
808 | struct MR_LD_RAID *raid = MR_LdRaidGet(ld, map); | |
809 | u32 pd, arRef; | |
810 | u8 physArm, span; | |
811 | u64 row; | |
812 | u8 retval = TRUE; | |
21d3c710 | 813 | u8 do_invader = 0; |
bc93d425 SS |
814 | u64 *pdBlock = &io_info->pdBlock; |
815 | u16 *pDevHandle = &io_info->devHandle; | |
21d3c710 SS |
816 | |
817 | if ((instance->pdev->device == PCI_DEVICE_ID_LSI_INVADER || | |
818 | instance->pdev->device == PCI_DEVICE_ID_LSI_FURY)) | |
819 | do_invader = 1; | |
9c915a8c | 820 | |
821 | row = mega_div64_32(stripRow, raid->rowDataSize); | |
822 | ||
823 | if (raid->level == 6) { | |
824 | /* logical arm within row */ | |
825 | u32 logArm = mega_mod64(stripRow, raid->rowDataSize); | |
826 | u32 rowMod, armQ, arm; | |
827 | ||
828 | if (raid->rowSize == 0) | |
829 | return FALSE; | |
830 | /* get logical row mod */ | |
831 | rowMod = mega_mod64(row, raid->rowSize); | |
832 | armQ = raid->rowSize-1-rowMod; /* index of Q drive */ | |
833 | arm = armQ+1+logArm; /* data always logically follows Q */ | |
834 | if (arm >= raid->rowSize) /* handle wrap condition */ | |
835 | arm -= raid->rowSize; | |
836 | physArm = (u8)arm; | |
837 | } else { | |
838 | if (raid->modFactor == 0) | |
839 | return FALSE; | |
840 | physArm = MR_LdDataArmGet(ld, mega_mod64(stripRow, | |
841 | raid->modFactor), | |
842 | map); | |
843 | } | |
844 | ||
845 | if (raid->spanDepth == 1) { | |
846 | span = 0; | |
847 | *pdBlock = row << raid->stripeShift; | |
848 | } else { | |
bc93d425 SS |
849 | span = (u8)MR_GetSpanBlock(ld, row, pdBlock, map); |
850 | if (span == SPAN_INVALID) | |
9c915a8c | 851 | return FALSE; |
852 | } | |
853 | ||
854 | /* Get the array on which this span is present */ | |
855 | arRef = MR_LdSpanArrayGet(ld, span, map); | |
856 | pd = MR_ArPdGet(arRef, physArm, map); /* Get the pd */ | |
857 | ||
858 | if (pd != MR_PD_INVALID) | |
859 | /* Get dev handle from Pd. */ | |
860 | *pDevHandle = MR_PdDevHandleGet(pd, map); | |
861 | else { | |
862 | *pDevHandle = MR_PD_INVALID; /* set dev handle as invalid. */ | |
36807e67 | 863 | if ((raid->level >= 5) && |
21d3c710 SS |
864 | (!do_invader || (do_invader && |
865 | (raid->regTypeReqOnRead != REGION_TYPE_UNUSED)))) | |
9c915a8c | 866 | pRAID_Context->regLockFlags = REGION_TYPE_EXCLUSIVE; |
867 | else if (raid->level == 1) { | |
868 | /* Get alternate Pd. */ | |
869 | pd = MR_ArPdGet(arRef, physArm + 1, map); | |
870 | if (pd != MR_PD_INVALID) | |
871 | /* Get dev handle from Pd */ | |
872 | *pDevHandle = MR_PdDevHandleGet(pd, map); | |
873 | } | |
9c915a8c | 874 | } |
875 | ||
94cd65dd | 876 | *pdBlock += stripRef + le64_to_cpu(MR_LdSpanPtrGet(ld, span, map)->startBlk); |
9c915a8c | 877 | pRAID_Context->spanArm = (span << RAID_CTX_SPANARM_SPAN_SHIFT) | |
878 | physArm; | |
d2552ebe | 879 | io_info->span_arm = pRAID_Context->spanArm; |
9c915a8c | 880 | return retval; |
881 | } | |
882 | ||
883 | /* | |
884 | ****************************************************************************** | |
885 | * | |
886 | * MR_BuildRaidContext function | |
887 | * | |
888 | * This function will initiate command processing. The start/end row and strip | |
889 | * information is calculated then the lock is acquired. | |
890 | * This function will return 0 if region lock was acquired OR return num strips | |
891 | */ | |
892 | u8 | |
36807e67 | 893 | MR_BuildRaidContext(struct megasas_instance *instance, |
894 | struct IO_REQUEST_INFO *io_info, | |
9c915a8c | 895 | struct RAID_CONTEXT *pRAID_Context, |
51087a86 | 896 | struct MR_DRV_RAID_MAP_ALL *map, u8 **raidLUN) |
9c915a8c | 897 | { |
898 | struct MR_LD_RAID *raid; | |
899 | u32 ld, stripSize, stripe_mask; | |
900 | u64 endLba, endStrip, endRow, start_row, start_strip; | |
901 | u64 regStart; | |
902 | u32 regSize; | |
903 | u8 num_strips, numRows; | |
904 | u16 ref_in_start_stripe, ref_in_end_stripe; | |
905 | u64 ldStartBlock; | |
906 | u32 numBlocks, ldTgtId; | |
907 | u8 isRead; | |
908 | u8 retval = 0; | |
bc93d425 SS |
909 | u8 startlba_span = SPAN_INVALID; |
910 | u64 *pdBlock = &io_info->pdBlock; | |
9c915a8c | 911 | |
912 | ldStartBlock = io_info->ldStartBlock; | |
913 | numBlocks = io_info->numBlocks; | |
914 | ldTgtId = io_info->ldTgtId; | |
915 | isRead = io_info->isRead; | |
bc93d425 SS |
916 | io_info->IoforUnevenSpan = 0; |
917 | io_info->start_span = SPAN_INVALID; | |
9c915a8c | 918 | |
919 | ld = MR_TargetIdToLdGet(ldTgtId, map); | |
920 | raid = MR_LdRaidGet(ld, map); | |
921 | ||
bc93d425 SS |
922 | /* |
923 | * if rowDataSize @RAID map and spanRowDataSize @SPAN INFO are zero | |
924 | * return FALSE | |
925 | */ | |
926 | if (raid->rowDataSize == 0) { | |
927 | if (MR_LdSpanPtrGet(ld, 0, map)->spanRowDataSize == 0) | |
928 | return FALSE; | |
929 | else if (instance->UnevenSpanSupport) { | |
930 | io_info->IoforUnevenSpan = 1; | |
931 | } else { | |
932 | dev_info(&instance->pdev->dev, | |
933 | "raid->rowDataSize is 0, but has SPAN[0]" | |
934 | "rowDataSize = 0x%0x," | |
935 | "but there is _NO_ UnevenSpanSupport\n", | |
936 | MR_LdSpanPtrGet(ld, 0, map)->spanRowDataSize); | |
937 | return FALSE; | |
938 | } | |
939 | } | |
940 | ||
9c915a8c | 941 | stripSize = 1 << raid->stripeShift; |
942 | stripe_mask = stripSize-1; | |
bc93d425 SS |
943 | |
944 | ||
9c915a8c | 945 | /* |
946 | * calculate starting row and stripe, and number of strips and rows | |
947 | */ | |
948 | start_strip = ldStartBlock >> raid->stripeShift; | |
949 | ref_in_start_stripe = (u16)(ldStartBlock & stripe_mask); | |
950 | endLba = ldStartBlock + numBlocks - 1; | |
951 | ref_in_end_stripe = (u16)(endLba & stripe_mask); | |
952 | endStrip = endLba >> raid->stripeShift; | |
953 | num_strips = (u8)(endStrip - start_strip + 1); /* End strip */ | |
bc93d425 SS |
954 | |
955 | if (io_info->IoforUnevenSpan) { | |
956 | start_row = get_row_from_strip(instance, ld, start_strip, map); | |
957 | endRow = get_row_from_strip(instance, ld, endStrip, map); | |
958 | if (start_row == -1ULL || endRow == -1ULL) { | |
959 | dev_info(&instance->pdev->dev, "return from %s %d." | |
960 | "Send IO w/o region lock.\n", | |
961 | __func__, __LINE__); | |
962 | return FALSE; | |
963 | } | |
964 | ||
965 | if (raid->spanDepth == 1) { | |
966 | startlba_span = 0; | |
967 | *pdBlock = start_row << raid->stripeShift; | |
968 | } else | |
969 | startlba_span = (u8)mr_spanset_get_span_block(instance, | |
970 | ld, start_row, pdBlock, map); | |
971 | if (startlba_span == SPAN_INVALID) { | |
972 | dev_info(&instance->pdev->dev, "return from %s %d" | |
973 | "for row 0x%llx,start strip %llx" | |
974 | "endSrip %llx\n", __func__, __LINE__, | |
975 | (unsigned long long)start_row, | |
976 | (unsigned long long)start_strip, | |
977 | (unsigned long long)endStrip); | |
978 | return FALSE; | |
979 | } | |
980 | io_info->start_span = startlba_span; | |
981 | io_info->start_row = start_row; | |
982 | #if SPAN_DEBUG | |
983 | dev_dbg(&instance->pdev->dev, "Check Span number from %s %d" | |
984 | "for row 0x%llx, start strip 0x%llx end strip 0x%llx" | |
985 | " span 0x%x\n", __func__, __LINE__, | |
986 | (unsigned long long)start_row, | |
987 | (unsigned long long)start_strip, | |
988 | (unsigned long long)endStrip, startlba_span); | |
989 | dev_dbg(&instance->pdev->dev, "start_row 0x%llx endRow 0x%llx" | |
990 | "Start span 0x%x\n", (unsigned long long)start_row, | |
991 | (unsigned long long)endRow, startlba_span); | |
992 | #endif | |
993 | } else { | |
994 | start_row = mega_div64_32(start_strip, raid->rowDataSize); | |
995 | endRow = mega_div64_32(endStrip, raid->rowDataSize); | |
996 | } | |
997 | numRows = (u8)(endRow - start_row + 1); | |
9c915a8c | 998 | |
999 | /* | |
1000 | * calculate region info. | |
1001 | */ | |
1002 | ||
1003 | /* assume region is at the start of the first row */ | |
1004 | regStart = start_row << raid->stripeShift; | |
1005 | /* assume this IO needs the full row - we'll adjust if not true */ | |
1006 | regSize = stripSize; | |
1007 | ||
c1529fa2 | 1008 | /* Check if we can send this I/O via FastPath */ |
1009 | if (raid->capability.fpCapable) { | |
1010 | if (isRead) | |
1011 | io_info->fpOkForIo = (raid->capability.fpReadCapable && | |
1012 | ((num_strips == 1) || | |
1013 | raid->capability. | |
1014 | fpReadAcrossStripe)); | |
1015 | else | |
1016 | io_info->fpOkForIo = (raid->capability.fpWriteCapable && | |
1017 | ((num_strips == 1) || | |
1018 | raid->capability. | |
1019 | fpWriteAcrossStripe)); | |
1020 | } else | |
9c915a8c | 1021 | io_info->fpOkForIo = FALSE; |
9c915a8c | 1022 | |
1023 | if (numRows == 1) { | |
1024 | /* single-strip IOs can always lock only the data needed */ | |
1025 | if (num_strips == 1) { | |
1026 | regStart += ref_in_start_stripe; | |
1027 | regSize = numBlocks; | |
1028 | } | |
1029 | /* multi-strip IOs always need to full stripe locked */ | |
bc93d425 SS |
1030 | } else if (io_info->IoforUnevenSpan == 0) { |
1031 | /* | |
1032 | * For Even span region lock optimization. | |
1033 | * If the start strip is the last in the start row | |
1034 | */ | |
9c915a8c | 1035 | if (start_strip == (start_row + 1) * raid->rowDataSize - 1) { |
9c915a8c | 1036 | regStart += ref_in_start_stripe; |
9c915a8c | 1037 | /* initialize count to sectors from startref to end |
1038 | of strip */ | |
bc93d425 | 1039 | regSize = stripSize - ref_in_start_stripe; |
9c915a8c | 1040 | } |
1041 | ||
bc93d425 | 1042 | /* add complete rows in the middle of the transfer */ |
9c915a8c | 1043 | if (numRows > 2) |
9c915a8c | 1044 | regSize += (numRows-2) << raid->stripeShift; |
1045 | ||
bc93d425 | 1046 | /* if IO ends within first strip of last row*/ |
9c915a8c | 1047 | if (endStrip == endRow*raid->rowDataSize) |
1048 | regSize += ref_in_end_stripe+1; | |
1049 | else | |
1050 | regSize += stripSize; | |
bc93d425 SS |
1051 | } else { |
1052 | /* | |
1053 | * For Uneven span region lock optimization. | |
1054 | * If the start strip is the last in the start row | |
1055 | */ | |
1056 | if (start_strip == (get_strip_from_row(instance, ld, start_row, map) + | |
1057 | SPAN_ROW_DATA_SIZE(map, ld, startlba_span) - 1)) { | |
1058 | regStart += ref_in_start_stripe; | |
1059 | /* initialize count to sectors from | |
1060 | * startRef to end of strip | |
1061 | */ | |
1062 | regSize = stripSize - ref_in_start_stripe; | |
1063 | } | |
1064 | /* Add complete rows in the middle of the transfer*/ | |
1065 | ||
1066 | if (numRows > 2) | |
1067 | /* Add complete rows in the middle of the transfer*/ | |
1068 | regSize += (numRows-2) << raid->stripeShift; | |
1069 | ||
1070 | /* if IO ends within first strip of last row */ | |
1071 | if (endStrip == get_strip_from_row(instance, ld, endRow, map)) | |
1072 | regSize += ref_in_end_stripe + 1; | |
1073 | else | |
1074 | regSize += stripSize; | |
9c915a8c | 1075 | } |
1076 | ||
26a077e7 | 1077 | pRAID_Context->timeoutValue = |
1078 | cpu_to_le16(raid->fpIoTimeoutForLd ? | |
1079 | raid->fpIoTimeoutForLd : | |
1080 | map->raidMap.fpPdIoTimeoutSec); | |
21d3c710 SS |
1081 | if ((instance->pdev->device == PCI_DEVICE_ID_LSI_INVADER) || |
1082 | (instance->pdev->device == PCI_DEVICE_ID_LSI_FURY)) | |
36807e67 | 1083 | pRAID_Context->regLockFlags = (isRead) ? |
1084 | raid->regTypeReqOnRead : raid->regTypeReqOnWrite; | |
1085 | else | |
1086 | pRAID_Context->regLockFlags = (isRead) ? | |
1087 | REGION_TYPE_SHARED_READ : raid->regTypeReqOnWrite; | |
9c915a8c | 1088 | pRAID_Context->VirtualDiskTgtId = raid->targetId; |
94cd65dd SS |
1089 | pRAID_Context->regLockRowLBA = cpu_to_le64(regStart); |
1090 | pRAID_Context->regLockLength = cpu_to_le32(regSize); | |
9c915a8c | 1091 | pRAID_Context->configSeqNum = raid->seqNum; |
21c9e160 | 1092 | /* save pointer to raid->LUN array */ |
1093 | *raidLUN = raid->LUN; | |
1094 | ||
9c915a8c | 1095 | |
1096 | /*Get Phy Params only if FP capable, or else leave it to MR firmware | |
1097 | to do the calculation.*/ | |
1098 | if (io_info->fpOkForIo) { | |
bc93d425 SS |
1099 | retval = io_info->IoforUnevenSpan ? |
1100 | mr_spanset_get_phy_params(instance, ld, | |
1101 | start_strip, ref_in_start_stripe, | |
1102 | io_info, pRAID_Context, map) : | |
1103 | MR_GetPhyParams(instance, ld, start_strip, | |
1104 | ref_in_start_stripe, io_info, | |
1105 | pRAID_Context, map); | |
1106 | /* If IO on an invalid Pd, then FP is not possible.*/ | |
9c915a8c | 1107 | if (io_info->devHandle == MR_PD_INVALID) |
1108 | io_info->fpOkForIo = FALSE; | |
1109 | return retval; | |
1110 | } else if (isRead) { | |
1111 | uint stripIdx; | |
1112 | for (stripIdx = 0; stripIdx < num_strips; stripIdx++) { | |
bc93d425 SS |
1113 | retval = io_info->IoforUnevenSpan ? |
1114 | mr_spanset_get_phy_params(instance, ld, | |
1115 | start_strip + stripIdx, | |
1116 | ref_in_start_stripe, io_info, | |
1117 | pRAID_Context, map) : | |
1118 | MR_GetPhyParams(instance, ld, | |
1119 | start_strip + stripIdx, ref_in_start_stripe, | |
1120 | io_info, pRAID_Context, map); | |
1121 | if (!retval) | |
9c915a8c | 1122 | return TRUE; |
1123 | } | |
1124 | } | |
bc93d425 SS |
1125 | |
1126 | #if SPAN_DEBUG | |
1127 | /* Just for testing what arm we get for strip.*/ | |
1128 | if (io_info->IoforUnevenSpan) | |
1129 | get_arm_from_strip(instance, ld, start_strip, map); | |
1130 | #endif | |
9c915a8c | 1131 | return TRUE; |
1132 | } | |
1133 | ||
bc93d425 SS |
1134 | /* |
1135 | ****************************************************************************** | |
1136 | * | |
1137 | * This routine pepare spanset info from Valid Raid map and store it into | |
1138 | * local copy of ldSpanInfo per instance data structure. | |
1139 | * | |
1140 | * Inputs : | |
1141 | * map - LD map | |
1142 | * ldSpanInfo - ldSpanInfo per HBA instance | |
1143 | * | |
1144 | */ | |
51087a86 | 1145 | void mr_update_span_set(struct MR_DRV_RAID_MAP_ALL *map, |
d2552ebe | 1146 | PLD_SPAN_INFO ldSpanInfo) |
bc93d425 SS |
1147 | { |
1148 | u8 span, count; | |
1149 | u32 element, span_row_width; | |
1150 | u64 span_row; | |
1151 | struct MR_LD_RAID *raid; | |
1152 | LD_SPAN_SET *span_set, *span_set_prev; | |
1153 | struct MR_QUAD_ELEMENT *quad; | |
1154 | int ldCount; | |
1155 | u16 ld; | |
1156 | ||
1157 | ||
51087a86 | 1158 | for (ldCount = 0; ldCount < MAX_LOGICAL_DRIVES_EXT; ldCount++) { |
bc93d425 | 1159 | ld = MR_TargetIdToLdGet(ldCount, map); |
51087a86 | 1160 | if (ld >= MAX_LOGICAL_DRIVES_EXT) |
bc93d425 SS |
1161 | continue; |
1162 | raid = MR_LdRaidGet(ld, map); | |
1163 | for (element = 0; element < MAX_QUAD_DEPTH; element++) { | |
1164 | for (span = 0; span < raid->spanDepth; span++) { | |
94cd65dd SS |
1165 | if (le32_to_cpu(map->raidMap.ldSpanMap[ld].spanBlock[span]. |
1166 | block_span_info.noElements) < | |
bc93d425 SS |
1167 | element + 1) |
1168 | continue; | |
1169 | span_set = &(ldSpanInfo[ld].span_set[element]); | |
1170 | quad = &map->raidMap.ldSpanMap[ld]. | |
1171 | spanBlock[span].block_span_info. | |
1172 | quad[element]; | |
1173 | ||
94cd65dd | 1174 | span_set->diff = le32_to_cpu(quad->diff); |
bc93d425 SS |
1175 | |
1176 | for (count = 0, span_row_width = 0; | |
1177 | count < raid->spanDepth; count++) { | |
94cd65dd | 1178 | if (le32_to_cpu(map->raidMap.ldSpanMap[ld]. |
bc93d425 SS |
1179 | spanBlock[count]. |
1180 | block_span_info. | |
94cd65dd | 1181 | noElements) >= element + 1) { |
bc93d425 SS |
1182 | span_set->strip_offset[count] = |
1183 | span_row_width; | |
1184 | span_row_width += | |
1185 | MR_LdSpanPtrGet | |
1186 | (ld, count, map)->spanRowDataSize; | |
1187 | printk(KERN_INFO "megasas:" | |
1188 | "span %x rowDataSize %x\n", | |
1189 | count, MR_LdSpanPtrGet | |
1190 | (ld, count, map)->spanRowDataSize); | |
1191 | } | |
1192 | } | |
1193 | ||
1194 | span_set->span_row_data_width = span_row_width; | |
94cd65dd SS |
1195 | span_row = mega_div64_32(((le64_to_cpu(quad->logEnd) - |
1196 | le64_to_cpu(quad->logStart)) + le32_to_cpu(quad->diff)), | |
1197 | le32_to_cpu(quad->diff)); | |
bc93d425 SS |
1198 | |
1199 | if (element == 0) { | |
1200 | span_set->log_start_lba = 0; | |
1201 | span_set->log_end_lba = | |
1202 | ((span_row << raid->stripeShift) | |
1203 | * span_row_width) - 1; | |
1204 | ||
1205 | span_set->span_row_start = 0; | |
1206 | span_set->span_row_end = span_row - 1; | |
1207 | ||
1208 | span_set->data_strip_start = 0; | |
1209 | span_set->data_strip_end = | |
1210 | (span_row * span_row_width) - 1; | |
1211 | ||
1212 | span_set->data_row_start = 0; | |
1213 | span_set->data_row_end = | |
94cd65dd | 1214 | (span_row * le32_to_cpu(quad->diff)) - 1; |
bc93d425 SS |
1215 | } else { |
1216 | span_set_prev = &(ldSpanInfo[ld]. | |
1217 | span_set[element - 1]); | |
1218 | span_set->log_start_lba = | |
1219 | span_set_prev->log_end_lba + 1; | |
1220 | span_set->log_end_lba = | |
1221 | span_set->log_start_lba + | |
1222 | ((span_row << raid->stripeShift) | |
1223 | * span_row_width) - 1; | |
1224 | ||
1225 | span_set->span_row_start = | |
1226 | span_set_prev->span_row_end + 1; | |
1227 | span_set->span_row_end = | |
1228 | span_set->span_row_start + span_row - 1; | |
1229 | ||
1230 | span_set->data_strip_start = | |
1231 | span_set_prev->data_strip_end + 1; | |
1232 | span_set->data_strip_end = | |
1233 | span_set->data_strip_start + | |
1234 | (span_row * span_row_width) - 1; | |
1235 | ||
1236 | span_set->data_row_start = | |
1237 | span_set_prev->data_row_end + 1; | |
1238 | span_set->data_row_end = | |
1239 | span_set->data_row_start + | |
94cd65dd | 1240 | (span_row * le32_to_cpu(quad->diff)) - 1; |
bc93d425 SS |
1241 | } |
1242 | break; | |
1243 | } | |
1244 | if (span == raid->spanDepth) | |
1245 | break; | |
1246 | } | |
1247 | } | |
1248 | #if SPAN_DEBUG | |
1249 | getSpanInfo(map, ldSpanInfo); | |
1250 | #endif | |
1251 | ||
1252 | } | |
1253 | ||
d2552ebe SS |
1254 | void mr_update_load_balance_params(struct MR_DRV_RAID_MAP_ALL *drv_map, |
1255 | struct LD_LOAD_BALANCE_INFO *lbInfo) | |
9c915a8c | 1256 | { |
1257 | int ldCount; | |
1258 | u16 ld; | |
1259 | struct MR_LD_RAID *raid; | |
1260 | ||
d2552ebe SS |
1261 | if (lb_pending_cmds > 128 || lb_pending_cmds < 1) |
1262 | lb_pending_cmds = LB_PENDING_CMDS_DEFAULT; | |
1263 | ||
51087a86 | 1264 | for (ldCount = 0; ldCount < MAX_LOGICAL_DRIVES_EXT; ldCount++) { |
d2552ebe | 1265 | ld = MR_TargetIdToLdGet(ldCount, drv_map); |
51087a86 | 1266 | if (ld >= MAX_LOGICAL_DRIVES_EXT) { |
9c915a8c | 1267 | lbInfo[ldCount].loadBalanceFlag = 0; |
1268 | continue; | |
1269 | } | |
1270 | ||
d2552ebe SS |
1271 | raid = MR_LdRaidGet(ld, drv_map); |
1272 | if ((raid->level != 1) || | |
1273 | (raid->ldState != MR_LD_STATE_OPTIMAL)) { | |
9c915a8c | 1274 | lbInfo[ldCount].loadBalanceFlag = 0; |
d2552ebe SS |
1275 | continue; |
1276 | } | |
1277 | lbInfo[ldCount].loadBalanceFlag = 1; | |
9c915a8c | 1278 | } |
1279 | } | |
1280 | ||
d2552ebe SS |
1281 | u8 megasas_get_best_arm_pd(struct megasas_instance *instance, |
1282 | struct LD_LOAD_BALANCE_INFO *lbInfo, struct IO_REQUEST_INFO *io_info) | |
9c915a8c | 1283 | { |
d2552ebe SS |
1284 | struct fusion_context *fusion; |
1285 | struct MR_LD_RAID *raid; | |
1286 | struct MR_DRV_RAID_MAP_ALL *drv_map; | |
1287 | u16 pend0, pend1, ld; | |
9c915a8c | 1288 | u64 diff0, diff1; |
d2552ebe SS |
1289 | u8 bestArm, pd0, pd1, span, arm; |
1290 | u32 arRef, span_row_size; | |
1291 | ||
1292 | u64 block = io_info->ldStartBlock; | |
1293 | u32 count = io_info->numBlocks; | |
1294 | ||
1295 | span = ((io_info->span_arm & RAID_CTX_SPANARM_SPAN_MASK) | |
1296 | >> RAID_CTX_SPANARM_SPAN_SHIFT); | |
1297 | arm = (io_info->span_arm & RAID_CTX_SPANARM_ARM_MASK); | |
1298 | ||
1299 | ||
1300 | fusion = instance->ctrl_context; | |
1301 | drv_map = fusion->ld_drv_map[(instance->map_id & 1)]; | |
1302 | ld = MR_TargetIdToLdGet(io_info->ldTgtId, drv_map); | |
1303 | raid = MR_LdRaidGet(ld, drv_map); | |
1304 | span_row_size = instance->UnevenSpanSupport ? | |
1305 | SPAN_ROW_SIZE(drv_map, ld, span) : raid->rowSize; | |
1306 | ||
1307 | arRef = MR_LdSpanArrayGet(ld, span, drv_map); | |
1308 | pd0 = MR_ArPdGet(arRef, arm, drv_map); | |
1309 | pd1 = MR_ArPdGet(arRef, (arm + 1) >= span_row_size ? | |
1310 | (arm + 1 - span_row_size) : arm + 1, drv_map); | |
9c915a8c | 1311 | |
1312 | /* get the pending cmds for the data and mirror arms */ | |
d2552ebe SS |
1313 | pend0 = atomic_read(&lbInfo->scsi_pending_cmds[pd0]); |
1314 | pend1 = atomic_read(&lbInfo->scsi_pending_cmds[pd1]); | |
9c915a8c | 1315 | |
1316 | /* Determine the disk whose head is nearer to the req. block */ | |
d2552ebe SS |
1317 | diff0 = ABS_DIFF(block, lbInfo->last_accessed_block[pd0]); |
1318 | diff1 = ABS_DIFF(block, lbInfo->last_accessed_block[pd1]); | |
1319 | bestArm = (diff0 <= diff1 ? arm : arm ^ 1); | |
9c915a8c | 1320 | |
d2552ebe SS |
1321 | if ((bestArm == arm && pend0 > pend1 + lb_pending_cmds) || |
1322 | (bestArm != arm && pend1 > pend0 + lb_pending_cmds)) | |
9c915a8c | 1323 | bestArm ^= 1; |
1324 | ||
1325 | /* Update the last accessed block on the correct pd */ | |
d2552ebe SS |
1326 | io_info->pd_after_lb = (bestArm == arm) ? pd0 : pd1; |
1327 | lbInfo->last_accessed_block[io_info->pd_after_lb] = block + count - 1; | |
1328 | io_info->span_arm = (span << RAID_CTX_SPANARM_SPAN_SHIFT) | bestArm; | |
1329 | #if SPAN_DEBUG | |
1330 | if (arm != bestArm) | |
1331 | dev_dbg(&instance->pdev->dev, "LSI Debug R1 Load balance " | |
1332 | "occur - span 0x%x arm 0x%x bestArm 0x%x " | |
1333 | "io_info->span_arm 0x%x\n", | |
1334 | span, arm, bestArm, io_info->span_arm); | |
1335 | #endif | |
1336 | return io_info->pd_after_lb; | |
9c915a8c | 1337 | } |
1338 | ||
d2552ebe SS |
1339 | u16 get_updated_dev_handle(struct megasas_instance *instance, |
1340 | struct LD_LOAD_BALANCE_INFO *lbInfo, struct IO_REQUEST_INFO *io_info) | |
9c915a8c | 1341 | { |
d2552ebe | 1342 | u8 arm_pd; |
9c915a8c | 1343 | u16 devHandle; |
d2552ebe SS |
1344 | struct fusion_context *fusion; |
1345 | struct MR_DRV_RAID_MAP_ALL *drv_map; | |
9c915a8c | 1346 | |
d2552ebe SS |
1347 | fusion = instance->ctrl_context; |
1348 | drv_map = fusion->ld_drv_map[(instance->map_id & 1)]; | |
9c915a8c | 1349 | |
d2552ebe SS |
1350 | /* get best new arm (PD ID) */ |
1351 | arm_pd = megasas_get_best_arm_pd(instance, lbInfo, io_info); | |
1352 | devHandle = MR_PdDevHandleGet(arm_pd, drv_map); | |
1353 | atomic_inc(&lbInfo->scsi_pending_cmds[arm_pd]); | |
9c915a8c | 1354 | return devHandle; |
1355 | } |