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9c915a8c | 1 | /* |
2 | * Linux MegaRAID driver for SAS based RAID controllers | |
3 | * | |
e399065b SS |
4 | * Copyright (c) 2009-2013 LSI Corporation |
5 | * Copyright (c) 2013-2014 Avago Technologies | |
9c915a8c | 6 | * |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; either version 2 | |
10 | * of the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
e399065b | 18 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
9c915a8c | 19 | * |
20 | * FILE: megaraid_sas_fusion.h | |
21 | * | |
e399065b | 22 | * Authors: Avago Technologies |
9c915a8c | 23 | * Manoj Jose |
24 | * Sumant Patro | |
e399065b SS |
25 | * Kashyap Desai <kashyap.desai@avagotech.com> |
26 | * Sumit Saxena <sumit.saxena@avagotech.com> | |
9c915a8c | 27 | * |
e399065b | 28 | * Send feedback to: megaraidlinux.pdl@avagotech.com |
9c915a8c | 29 | * |
e399065b SS |
30 | * Mail to: Avago Technologies, 350 West Trimble Road, Building 90, |
31 | * San Jose, California 95131 | |
9c915a8c | 32 | */ |
33 | ||
34 | #ifndef _MEGARAID_SAS_FUSION_H_ | |
35 | #define _MEGARAID_SAS_FUSION_H_ | |
36 | ||
37 | /* Fusion defines */ | |
38 | #define MEGASAS_MAX_SZ_CHAIN_FRAME 1024 | |
39 | #define MFI_FUSION_ENABLE_INTERRUPT_MASK (0x00000009) | |
40 | #define MEGA_MPI2_RAID_DEFAULT_IO_FRAME_SIZE 256 | |
41 | #define MEGASAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0 | |
42 | #define MEGASAS_MPI2_FUNCTION_LD_IO_REQUEST 0xF1 | |
43 | #define MEGASAS_LOAD_BALANCE_FLAG 0x1 | |
44 | #define MEGASAS_DCMD_MBOX_PEND_FLAG 0x1 | |
45 | #define HOST_DIAG_WRITE_ENABLE 0x80 | |
46 | #define HOST_DIAG_RESET_ADAPTER 0x4 | |
47 | #define MEGASAS_FUSION_MAX_RESET_TRIES 3 | |
d46a3ad6 | 48 | #define MAX_MSIX_QUEUES_FUSION 128 |
9c915a8c | 49 | |
36807e67 | 50 | /* Invader defines */ |
51 | #define MPI2_TYPE_CUDA 0x2 | |
52 | #define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH 0x4000 | |
53 | #define MR_RL_FLAGS_GRANT_DESTINATION_CPU0 0x00 | |
54 | #define MR_RL_FLAGS_GRANT_DESTINATION_CPU1 0x10 | |
55 | #define MR_RL_FLAGS_GRANT_DESTINATION_CUDA 0x80 | |
56 | #define MR_RL_FLAGS_SEQ_NUM_ENABLE 0x8 | |
57 | ||
9c915a8c | 58 | /* T10 PI defines */ |
59 | #define MR_PROT_INFO_TYPE_CONTROLLER 0x8 | |
60 | #define MEGASAS_SCSI_VARIABLE_LENGTH_CMD 0x7f | |
61 | #define MEGASAS_SCSI_SERVICE_ACTION_READ32 0x9 | |
62 | #define MEGASAS_SCSI_SERVICE_ACTION_WRITE32 0xB | |
63 | #define MEGASAS_SCSI_ADDL_CDB_LEN 0x18 | |
64 | #define MEGASAS_RD_WR_PROTECT_CHECK_ALL 0x20 | |
65 | #define MEGASAS_RD_WR_PROTECT_CHECK_NONE 0x60 | |
9c915a8c | 66 | |
d46a3ad6 SS |
67 | #define MPI2_SUP_REPLY_POST_HOST_INDEX_OFFSET (0x0000030C) |
68 | #define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C) | |
69 | ||
9c915a8c | 70 | /* |
71 | * Raid context flags | |
72 | */ | |
73 | ||
74 | #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_SHIFT 0x4 | |
75 | #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_MASK 0x30 | |
76 | enum MR_RAID_FLAGS_IO_SUB_TYPE { | |
77 | MR_RAID_FLAGS_IO_SUB_TYPE_NONE = 0, | |
78 | MR_RAID_FLAGS_IO_SUB_TYPE_SYSTEM_PD = 1, | |
79 | }; | |
80 | ||
81 | /* | |
82 | * Request descriptor types | |
83 | */ | |
84 | #define MEGASAS_REQ_DESCRIPT_FLAGS_LD_IO 0x7 | |
85 | #define MEGASAS_REQ_DESCRIPT_FLAGS_MFA 0x1 | |
36807e67 | 86 | #define MEGASAS_REQ_DESCRIPT_FLAGS_NO_LOCK 0x2 |
9c915a8c | 87 | #define MEGASAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT 1 |
88 | ||
89 | #define MEGASAS_FP_CMD_LEN 16 | |
90 | #define MEGASAS_FUSION_IN_RESET 0 | |
db4fc864 | 91 | #define THRESHOLD_REPLY_COUNT 50 |
9c915a8c | 92 | |
93 | /* | |
3948ff8b | 94 | * Raid Context structure which describes MegaRAID specific IO Parameters |
9c915a8c | 95 | * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames |
96 | */ | |
97 | ||
98 | struct RAID_CONTEXT { | |
94cd65dd SS |
99 | #if defined(__BIG_ENDIAN_BITFIELD) |
100 | u8 nseg:4; | |
101 | u8 Type:4; | |
102 | #else | |
36807e67 | 103 | u8 Type:4; |
104 | u8 nseg:4; | |
94cd65dd | 105 | #endif |
36807e67 | 106 | u8 resvd0; |
9c915a8c | 107 | u16 timeoutValue; |
108 | u8 regLockFlags; | |
109 | u8 resvd1; | |
110 | u16 VirtualDiskTgtId; | |
111 | u64 regLockRowLBA; | |
112 | u32 regLockLength; | |
113 | u16 nextLMId; | |
114 | u8 exStatus; | |
115 | u8 status; | |
116 | u8 RAIDFlags; | |
117 | u8 numSGE; | |
118 | u16 configSeqNum; | |
119 | u8 spanArm; | |
120 | u8 resvd2[3]; | |
121 | }; | |
122 | ||
123 | #define RAID_CTX_SPANARM_ARM_SHIFT (0) | |
124 | #define RAID_CTX_SPANARM_ARM_MASK (0x1f) | |
125 | ||
126 | #define RAID_CTX_SPANARM_SPAN_SHIFT (5) | |
127 | #define RAID_CTX_SPANARM_SPAN_MASK (0xE0) | |
128 | ||
129 | /* | |
130 | * define region lock types | |
131 | */ | |
132 | enum REGION_TYPE { | |
133 | REGION_TYPE_UNUSED = 0, | |
134 | REGION_TYPE_SHARED_READ = 1, | |
135 | REGION_TYPE_SHARED_WRITE = 2, | |
136 | REGION_TYPE_EXCLUSIVE = 3, | |
137 | }; | |
138 | ||
139 | /* MPI2 defines */ | |
140 | #define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */ | |
141 | #define MPI2_WHOINIT_HOST_DRIVER (0x04) | |
142 | #define MPI2_VERSION_MAJOR (0x02) | |
143 | #define MPI2_VERSION_MINOR (0x00) | |
144 | #define MPI2_VERSION_MAJOR_MASK (0xFF00) | |
145 | #define MPI2_VERSION_MAJOR_SHIFT (8) | |
146 | #define MPI2_VERSION_MINOR_MASK (0x00FF) | |
147 | #define MPI2_VERSION_MINOR_SHIFT (0) | |
148 | #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ | |
149 | MPI2_VERSION_MINOR) | |
150 | #define MPI2_HEADER_VERSION_UNIT (0x10) | |
151 | #define MPI2_HEADER_VERSION_DEV (0x00) | |
152 | #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) | |
153 | #define MPI2_HEADER_VERSION_UNIT_SHIFT (8) | |
154 | #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF) | |
155 | #define MPI2_HEADER_VERSION_DEV_SHIFT (0) | |
156 | #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | \ | |
157 | MPI2_HEADER_VERSION_DEV) | |
158 | #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) | |
159 | #define MPI2_SCSIIO_EEDPFLAGS_INC_PRI_REFTAG (0x8000) | |
160 | #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REFTAG (0x0400) | |
161 | #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REMOVE_OP (0x0003) | |
162 | #define MPI2_SCSIIO_EEDPFLAGS_CHECK_APPTAG (0x0200) | |
163 | #define MPI2_SCSIIO_EEDPFLAGS_CHECK_GUARD (0x0100) | |
164 | #define MPI2_SCSIIO_EEDPFLAGS_INSERT_OP (0x0004) | |
165 | #define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */ | |
166 | #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06) | |
167 | #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00) | |
168 | #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02) | |
169 | #define MPI2_SCSIIO_CONTROL_WRITE (0x01000000) | |
170 | #define MPI2_SCSIIO_CONTROL_READ (0x02000000) | |
171 | #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E) | |
172 | #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F) | |
173 | #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00) | |
174 | #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F) | |
175 | #define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0) | |
176 | #define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004) | |
177 | #define MPI2_WRSEQ_1ST_KEY_VALUE (0xF) | |
178 | #define MPI2_WRSEQ_2ND_KEY_VALUE (0x4) | |
179 | #define MPI2_WRSEQ_3RD_KEY_VALUE (0xB) | |
180 | #define MPI2_WRSEQ_4TH_KEY_VALUE (0x2) | |
181 | #define MPI2_WRSEQ_5TH_KEY_VALUE (0x7) | |
182 | #define MPI2_WRSEQ_6TH_KEY_VALUE (0xD) | |
183 | ||
184 | struct MPI25_IEEE_SGE_CHAIN64 { | |
185 | u64 Address; | |
186 | u32 Length; | |
187 | u16 Reserved1; | |
188 | u8 NextChainOffset; | |
189 | u8 Flags; | |
190 | }; | |
191 | ||
192 | struct MPI2_SGE_SIMPLE_UNION { | |
193 | u32 FlagsLength; | |
194 | union { | |
195 | u32 Address32; | |
196 | u64 Address64; | |
197 | } u; | |
198 | }; | |
199 | ||
200 | struct MPI2_SCSI_IO_CDB_EEDP32 { | |
201 | u8 CDB[20]; /* 0x00 */ | |
202 | u32 PrimaryReferenceTag; /* 0x14 */ | |
203 | u16 PrimaryApplicationTag; /* 0x18 */ | |
204 | u16 PrimaryApplicationTagMask; /* 0x1A */ | |
205 | u32 TransferLength; /* 0x1C */ | |
206 | }; | |
207 | ||
208 | struct MPI2_SGE_CHAIN_UNION { | |
209 | u16 Length; | |
210 | u8 NextChainOffset; | |
211 | u8 Flags; | |
212 | union { | |
213 | u32 Address32; | |
214 | u64 Address64; | |
215 | } u; | |
216 | }; | |
217 | ||
218 | struct MPI2_IEEE_SGE_SIMPLE32 { | |
219 | u32 Address; | |
220 | u32 FlagsLength; | |
221 | }; | |
222 | ||
223 | struct MPI2_IEEE_SGE_CHAIN32 { | |
224 | u32 Address; | |
225 | u32 FlagsLength; | |
226 | }; | |
227 | ||
228 | struct MPI2_IEEE_SGE_SIMPLE64 { | |
229 | u64 Address; | |
230 | u32 Length; | |
231 | u16 Reserved1; | |
232 | u8 Reserved2; | |
233 | u8 Flags; | |
234 | }; | |
235 | ||
236 | struct MPI2_IEEE_SGE_CHAIN64 { | |
237 | u64 Address; | |
238 | u32 Length; | |
239 | u16 Reserved1; | |
240 | u8 Reserved2; | |
241 | u8 Flags; | |
242 | }; | |
243 | ||
244 | union MPI2_IEEE_SGE_SIMPLE_UNION { | |
245 | struct MPI2_IEEE_SGE_SIMPLE32 Simple32; | |
246 | struct MPI2_IEEE_SGE_SIMPLE64 Simple64; | |
247 | }; | |
248 | ||
249 | union MPI2_IEEE_SGE_CHAIN_UNION { | |
250 | struct MPI2_IEEE_SGE_CHAIN32 Chain32; | |
251 | struct MPI2_IEEE_SGE_CHAIN64 Chain64; | |
252 | }; | |
253 | ||
254 | union MPI2_SGE_IO_UNION { | |
255 | struct MPI2_SGE_SIMPLE_UNION MpiSimple; | |
256 | struct MPI2_SGE_CHAIN_UNION MpiChain; | |
257 | union MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; | |
258 | union MPI2_IEEE_SGE_CHAIN_UNION IeeeChain; | |
259 | }; | |
260 | ||
261 | union MPI2_SCSI_IO_CDB_UNION { | |
262 | u8 CDB32[32]; | |
263 | struct MPI2_SCSI_IO_CDB_EEDP32 EEDP32; | |
264 | struct MPI2_SGE_SIMPLE_UNION SGE; | |
265 | }; | |
266 | ||
267 | /* | |
268 | * RAID SCSI IO Request Message | |
269 | * Total SGE count will be one less than _MPI2_SCSI_IO_REQUEST | |
270 | */ | |
271 | struct MPI2_RAID_SCSI_IO_REQUEST { | |
272 | u16 DevHandle; /* 0x00 */ | |
273 | u8 ChainOffset; /* 0x02 */ | |
274 | u8 Function; /* 0x03 */ | |
275 | u16 Reserved1; /* 0x04 */ | |
276 | u8 Reserved2; /* 0x06 */ | |
277 | u8 MsgFlags; /* 0x07 */ | |
278 | u8 VP_ID; /* 0x08 */ | |
279 | u8 VF_ID; /* 0x09 */ | |
280 | u16 Reserved3; /* 0x0A */ | |
281 | u32 SenseBufferLowAddress; /* 0x0C */ | |
282 | u16 SGLFlags; /* 0x10 */ | |
283 | u8 SenseBufferLength; /* 0x12 */ | |
284 | u8 Reserved4; /* 0x13 */ | |
285 | u8 SGLOffset0; /* 0x14 */ | |
286 | u8 SGLOffset1; /* 0x15 */ | |
287 | u8 SGLOffset2; /* 0x16 */ | |
288 | u8 SGLOffset3; /* 0x17 */ | |
289 | u32 SkipCount; /* 0x18 */ | |
290 | u32 DataLength; /* 0x1C */ | |
291 | u32 BidirectionalDataLength; /* 0x20 */ | |
292 | u16 IoFlags; /* 0x24 */ | |
293 | u16 EEDPFlags; /* 0x26 */ | |
294 | u32 EEDPBlockSize; /* 0x28 */ | |
295 | u32 SecondaryReferenceTag; /* 0x2C */ | |
296 | u16 SecondaryApplicationTag; /* 0x30 */ | |
297 | u16 ApplicationTagTranslationMask; /* 0x32 */ | |
298 | u8 LUN[8]; /* 0x34 */ | |
299 | u32 Control; /* 0x3C */ | |
300 | union MPI2_SCSI_IO_CDB_UNION CDB; /* 0x40 */ | |
301 | struct RAID_CONTEXT RaidContext; /* 0x60 */ | |
302 | union MPI2_SGE_IO_UNION SGL; /* 0x80 */ | |
303 | }; | |
304 | ||
305 | /* | |
306 | * MPT RAID MFA IO Descriptor. | |
307 | */ | |
308 | struct MEGASAS_RAID_MFA_IO_REQUEST_DESCRIPTOR { | |
309 | u32 RequestFlags:8; | |
200aed58 SS |
310 | u32 MessageAddress1:24; |
311 | u32 MessageAddress2; | |
9c915a8c | 312 | }; |
313 | ||
314 | /* Default Request Descriptor */ | |
315 | struct MPI2_DEFAULT_REQUEST_DESCRIPTOR { | |
316 | u8 RequestFlags; /* 0x00 */ | |
317 | u8 MSIxIndex; /* 0x01 */ | |
318 | u16 SMID; /* 0x02 */ | |
319 | u16 LMID; /* 0x04 */ | |
320 | u16 DescriptorTypeDependent; /* 0x06 */ | |
321 | }; | |
322 | ||
323 | /* High Priority Request Descriptor */ | |
324 | struct MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR { | |
325 | u8 RequestFlags; /* 0x00 */ | |
326 | u8 MSIxIndex; /* 0x01 */ | |
327 | u16 SMID; /* 0x02 */ | |
328 | u16 LMID; /* 0x04 */ | |
329 | u16 Reserved1; /* 0x06 */ | |
330 | }; | |
331 | ||
332 | /* SCSI IO Request Descriptor */ | |
333 | struct MPI2_SCSI_IO_REQUEST_DESCRIPTOR { | |
334 | u8 RequestFlags; /* 0x00 */ | |
335 | u8 MSIxIndex; /* 0x01 */ | |
336 | u16 SMID; /* 0x02 */ | |
337 | u16 LMID; /* 0x04 */ | |
338 | u16 DevHandle; /* 0x06 */ | |
339 | }; | |
340 | ||
341 | /* SCSI Target Request Descriptor */ | |
342 | struct MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR { | |
343 | u8 RequestFlags; /* 0x00 */ | |
344 | u8 MSIxIndex; /* 0x01 */ | |
345 | u16 SMID; /* 0x02 */ | |
346 | u16 LMID; /* 0x04 */ | |
347 | u16 IoIndex; /* 0x06 */ | |
348 | }; | |
349 | ||
350 | /* RAID Accelerator Request Descriptor */ | |
351 | struct MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR { | |
352 | u8 RequestFlags; /* 0x00 */ | |
353 | u8 MSIxIndex; /* 0x01 */ | |
354 | u16 SMID; /* 0x02 */ | |
355 | u16 LMID; /* 0x04 */ | |
356 | u16 Reserved; /* 0x06 */ | |
357 | }; | |
358 | ||
359 | /* union of Request Descriptors */ | |
360 | union MEGASAS_REQUEST_DESCRIPTOR_UNION { | |
361 | struct MPI2_DEFAULT_REQUEST_DESCRIPTOR Default; | |
362 | struct MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority; | |
363 | struct MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO; | |
364 | struct MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget; | |
365 | struct MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator; | |
366 | struct MEGASAS_RAID_MFA_IO_REQUEST_DESCRIPTOR MFAIo; | |
367 | union { | |
368 | struct { | |
369 | u32 low; | |
370 | u32 high; | |
371 | } u; | |
372 | u64 Words; | |
373 | }; | |
374 | }; | |
375 | ||
376 | /* Default Reply Descriptor */ | |
377 | struct MPI2_DEFAULT_REPLY_DESCRIPTOR { | |
378 | u8 ReplyFlags; /* 0x00 */ | |
379 | u8 MSIxIndex; /* 0x01 */ | |
380 | u16 DescriptorTypeDependent1; /* 0x02 */ | |
381 | u32 DescriptorTypeDependent2; /* 0x04 */ | |
382 | }; | |
383 | ||
384 | /* Address Reply Descriptor */ | |
385 | struct MPI2_ADDRESS_REPLY_DESCRIPTOR { | |
386 | u8 ReplyFlags; /* 0x00 */ | |
387 | u8 MSIxIndex; /* 0x01 */ | |
388 | u16 SMID; /* 0x02 */ | |
389 | u32 ReplyFrameAddress; /* 0x04 */ | |
390 | }; | |
391 | ||
392 | /* SCSI IO Success Reply Descriptor */ | |
393 | struct MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR { | |
394 | u8 ReplyFlags; /* 0x00 */ | |
395 | u8 MSIxIndex; /* 0x01 */ | |
396 | u16 SMID; /* 0x02 */ | |
397 | u16 TaskTag; /* 0x04 */ | |
398 | u16 Reserved1; /* 0x06 */ | |
399 | }; | |
400 | ||
401 | /* TargetAssist Success Reply Descriptor */ | |
402 | struct MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR { | |
403 | u8 ReplyFlags; /* 0x00 */ | |
404 | u8 MSIxIndex; /* 0x01 */ | |
405 | u16 SMID; /* 0x02 */ | |
406 | u8 SequenceNumber; /* 0x04 */ | |
407 | u8 Reserved1; /* 0x05 */ | |
408 | u16 IoIndex; /* 0x06 */ | |
409 | }; | |
410 | ||
411 | /* Target Command Buffer Reply Descriptor */ | |
412 | struct MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR { | |
413 | u8 ReplyFlags; /* 0x00 */ | |
414 | u8 MSIxIndex; /* 0x01 */ | |
415 | u8 VP_ID; /* 0x02 */ | |
416 | u8 Flags; /* 0x03 */ | |
417 | u16 InitiatorDevHandle; /* 0x04 */ | |
418 | u16 IoIndex; /* 0x06 */ | |
419 | }; | |
420 | ||
421 | /* RAID Accelerator Success Reply Descriptor */ | |
422 | struct MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR { | |
423 | u8 ReplyFlags; /* 0x00 */ | |
424 | u8 MSIxIndex; /* 0x01 */ | |
425 | u16 SMID; /* 0x02 */ | |
426 | u32 Reserved; /* 0x04 */ | |
427 | }; | |
428 | ||
429 | /* union of Reply Descriptors */ | |
430 | union MPI2_REPLY_DESCRIPTORS_UNION { | |
431 | struct MPI2_DEFAULT_REPLY_DESCRIPTOR Default; | |
432 | struct MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply; | |
433 | struct MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess; | |
434 | struct MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess; | |
435 | struct MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer; | |
436 | struct MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR | |
437 | RAIDAcceleratorSuccess; | |
438 | u64 Words; | |
439 | }; | |
440 | ||
441 | /* IOCInit Request message */ | |
442 | struct MPI2_IOC_INIT_REQUEST { | |
443 | u8 WhoInit; /* 0x00 */ | |
444 | u8 Reserved1; /* 0x01 */ | |
445 | u8 ChainOffset; /* 0x02 */ | |
446 | u8 Function; /* 0x03 */ | |
447 | u16 Reserved2; /* 0x04 */ | |
448 | u8 Reserved3; /* 0x06 */ | |
449 | u8 MsgFlags; /* 0x07 */ | |
450 | u8 VP_ID; /* 0x08 */ | |
451 | u8 VF_ID; /* 0x09 */ | |
452 | u16 Reserved4; /* 0x0A */ | |
453 | u16 MsgVersion; /* 0x0C */ | |
454 | u16 HeaderVersion; /* 0x0E */ | |
455 | u32 Reserved5; /* 0x10 */ | |
456 | u16 Reserved6; /* 0x14 */ | |
457 | u8 Reserved7; /* 0x16 */ | |
458 | u8 HostMSIxVectors; /* 0x17 */ | |
459 | u16 Reserved8; /* 0x18 */ | |
460 | u16 SystemRequestFrameSize; /* 0x1A */ | |
461 | u16 ReplyDescriptorPostQueueDepth; /* 0x1C */ | |
462 | u16 ReplyFreeQueueDepth; /* 0x1E */ | |
463 | u32 SenseBufferAddressHigh; /* 0x20 */ | |
464 | u32 SystemReplyAddressHigh; /* 0x24 */ | |
465 | u64 SystemRequestFrameBaseAddress; /* 0x28 */ | |
466 | u64 ReplyDescriptorPostQueueAddress;/* 0x30 */ | |
467 | u64 ReplyFreeQueueAddress; /* 0x38 */ | |
468 | u64 TimeStamp; /* 0x40 */ | |
469 | }; | |
470 | ||
471 | /* mrpriv defines */ | |
472 | #define MR_PD_INVALID 0xFFFF | |
473 | #define MAX_SPAN_DEPTH 8 | |
bc93d425 | 474 | #define MAX_QUAD_DEPTH MAX_SPAN_DEPTH |
9c915a8c | 475 | #define MAX_RAIDMAP_SPAN_DEPTH (MAX_SPAN_DEPTH) |
476 | #define MAX_ROW_SIZE 32 | |
477 | #define MAX_RAIDMAP_ROW_SIZE (MAX_ROW_SIZE) | |
478 | #define MAX_LOGICAL_DRIVES 64 | |
51087a86 | 479 | #define MAX_LOGICAL_DRIVES_EXT 256 |
9c915a8c | 480 | #define MAX_RAIDMAP_LOGICAL_DRIVES (MAX_LOGICAL_DRIVES) |
481 | #define MAX_RAIDMAP_VIEWS (MAX_LOGICAL_DRIVES) | |
482 | #define MAX_ARRAYS 128 | |
483 | #define MAX_RAIDMAP_ARRAYS (MAX_ARRAYS) | |
51087a86 SS |
484 | #define MAX_ARRAYS_EXT 256 |
485 | #define MAX_API_ARRAYS_EXT (MAX_ARRAYS_EXT) | |
9c915a8c | 486 | #define MAX_PHYSICAL_DEVICES 256 |
487 | #define MAX_RAIDMAP_PHYSICAL_DEVICES (MAX_PHYSICAL_DEVICES) | |
488 | #define MR_DCMD_LD_MAP_GET_INFO 0x0300e101 | |
229fe47c | 489 | #define MR_DCMD_CTRL_SHARED_HOST_MEM_ALLOC 0x010e8485 /* SR-IOV HB alloc*/ |
490 | #define MR_DCMD_LD_VF_MAP_GET_ALL_LDS_111 0x03200200 | |
491 | #define MR_DCMD_LD_VF_MAP_GET_ALL_LDS 0x03150200 | |
9c915a8c | 492 | |
493 | struct MR_DEV_HANDLE_INFO { | |
494 | u16 curDevHdl; | |
495 | u8 validHandles; | |
496 | u8 reserved; | |
497 | u16 devHandle[2]; | |
498 | }; | |
499 | ||
500 | struct MR_ARRAY_INFO { | |
501 | u16 pd[MAX_RAIDMAP_ROW_SIZE]; | |
502 | }; | |
503 | ||
504 | struct MR_QUAD_ELEMENT { | |
505 | u64 logStart; | |
506 | u64 logEnd; | |
507 | u64 offsetInSpan; | |
508 | u32 diff; | |
509 | u32 reserved1; | |
510 | }; | |
511 | ||
512 | struct MR_SPAN_INFO { | |
513 | u32 noElements; | |
514 | u32 reserved1; | |
515 | struct MR_QUAD_ELEMENT quad[MAX_RAIDMAP_SPAN_DEPTH]; | |
516 | }; | |
517 | ||
518 | struct MR_LD_SPAN { | |
519 | u64 startBlk; | |
520 | u64 numBlks; | |
521 | u16 arrayRef; | |
bc93d425 SS |
522 | u8 spanRowSize; |
523 | u8 spanRowDataSize; | |
524 | u8 reserved[4]; | |
9c915a8c | 525 | }; |
526 | ||
527 | struct MR_SPAN_BLOCK_INFO { | |
528 | u64 num_rows; | |
529 | struct MR_LD_SPAN span; | |
530 | struct MR_SPAN_INFO block_span_info; | |
531 | }; | |
532 | ||
533 | struct MR_LD_RAID { | |
534 | struct { | |
94cd65dd SS |
535 | #if defined(__BIG_ENDIAN_BITFIELD) |
536 | u32 reserved4:7; | |
537 | u32 fpNonRWCapable:1; | |
538 | u32 fpReadAcrossStripe:1; | |
539 | u32 fpWriteAcrossStripe:1; | |
540 | u32 fpReadCapable:1; | |
541 | u32 fpWriteCapable:1; | |
542 | u32 encryptionType:8; | |
543 | u32 pdPiMode:4; | |
544 | u32 ldPiMode:4; | |
545 | u32 reserved5:3; | |
546 | u32 fpCapable:1; | |
547 | #else | |
9c915a8c | 548 | u32 fpCapable:1; |
549 | u32 reserved5:3; | |
550 | u32 ldPiMode:4; | |
551 | u32 pdPiMode:4; | |
552 | u32 encryptionType:8; | |
553 | u32 fpWriteCapable:1; | |
554 | u32 fpReadCapable:1; | |
555 | u32 fpWriteAcrossStripe:1; | |
556 | u32 fpReadAcrossStripe:1; | |
21c9e160 | 557 | u32 fpNonRWCapable:1; |
558 | u32 reserved4:7; | |
94cd65dd | 559 | #endif |
9c915a8c | 560 | } capability; |
561 | u32 reserved6; | |
562 | u64 size; | |
563 | u8 spanDepth; | |
564 | u8 level; | |
565 | u8 stripeShift; | |
566 | u8 rowSize; | |
567 | u8 rowDataSize; | |
568 | u8 writeMode; | |
569 | u8 PRL; | |
570 | u8 SRL; | |
571 | u16 targetId; | |
572 | u8 ldState; | |
573 | u8 regTypeReqOnWrite; | |
574 | u8 modFactor; | |
36807e67 | 575 | u8 regTypeReqOnRead; |
9c915a8c | 576 | u16 seqNum; |
577 | ||
578 | struct { | |
579 | u32 ldSyncRequired:1; | |
580 | u32 reserved:31; | |
581 | } flags; | |
582 | ||
21c9e160 | 583 | u8 LUN[8]; /* 0x24 8 byte LUN field used for SCSI IO's */ |
584 | u8 fpIoTimeoutForLd;/*0x2C timeout value used by driver in FP IO*/ | |
585 | u8 reserved3[0x80-0x2D]; /* 0x2D */ | |
9c915a8c | 586 | }; |
587 | ||
588 | struct MR_LD_SPAN_MAP { | |
589 | struct MR_LD_RAID ldRaid; | |
590 | u8 dataArmMap[MAX_RAIDMAP_ROW_SIZE]; | |
591 | struct MR_SPAN_BLOCK_INFO spanBlock[MAX_RAIDMAP_SPAN_DEPTH]; | |
592 | }; | |
593 | ||
594 | struct MR_FW_RAID_MAP { | |
595 | u32 totalSize; | |
596 | union { | |
597 | struct { | |
598 | u32 maxLd; | |
599 | u32 maxSpanDepth; | |
600 | u32 maxRowSize; | |
601 | u32 maxPdCount; | |
602 | u32 maxArrays; | |
603 | } validationInfo; | |
604 | u32 version[5]; | |
9c915a8c | 605 | }; |
606 | ||
607 | u32 ldCount; | |
608 | u32 Reserved1; | |
609 | u8 ldTgtIdToLd[MAX_RAIDMAP_LOGICAL_DRIVES+ | |
610 | MAX_RAIDMAP_VIEWS]; | |
611 | u8 fpPdIoTimeoutSec; | |
612 | u8 reserved2[7]; | |
613 | struct MR_ARRAY_INFO arMapInfo[MAX_RAIDMAP_ARRAYS]; | |
614 | struct MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES]; | |
615 | struct MR_LD_SPAN_MAP ldSpanMap[1]; | |
616 | }; | |
617 | ||
618 | struct IO_REQUEST_INFO { | |
619 | u64 ldStartBlock; | |
620 | u32 numBlocks; | |
621 | u16 ldTgtId; | |
622 | u8 isRead; | |
623 | u16 devHandle; | |
624 | u64 pdBlock; | |
625 | u8 fpOkForIo; | |
bc93d425 SS |
626 | u8 IoforUnevenSpan; |
627 | u8 start_span; | |
628 | u8 reserved; | |
629 | u64 start_row; | |
d2552ebe SS |
630 | u8 span_arm; /* span[7:5], arm[4:0] */ |
631 | u8 pd_after_lb; | |
9c915a8c | 632 | }; |
633 | ||
634 | struct MR_LD_TARGET_SYNC { | |
635 | u8 targetId; | |
636 | u8 reserved; | |
637 | u16 seqNum; | |
638 | }; | |
639 | ||
640 | #define IEEE_SGE_FLAGS_ADDR_MASK (0x03) | |
641 | #define IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) | |
642 | #define IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) | |
643 | #define IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02) | |
644 | #define IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) | |
645 | #define IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80) | |
646 | #define IEEE_SGE_FLAGS_END_OF_LIST (0x40) | |
647 | ||
648 | struct megasas_register_set; | |
649 | struct megasas_instance; | |
650 | ||
651 | union desc_word { | |
652 | u64 word; | |
653 | struct { | |
654 | u32 low; | |
655 | u32 high; | |
656 | } u; | |
657 | }; | |
658 | ||
659 | struct megasas_cmd_fusion { | |
660 | struct MPI2_RAID_SCSI_IO_REQUEST *io_request; | |
661 | dma_addr_t io_request_phys_addr; | |
662 | ||
663 | union MPI2_SGE_IO_UNION *sg_frame; | |
664 | dma_addr_t sg_frame_phys_addr; | |
665 | ||
666 | u8 *sense; | |
667 | dma_addr_t sense_phys_addr; | |
668 | ||
669 | struct list_head list; | |
670 | struct scsi_cmnd *scmd; | |
671 | struct megasas_instance *instance; | |
672 | ||
673 | u8 retry_for_fw_reset; | |
674 | union MEGASAS_REQUEST_DESCRIPTOR_UNION *request_desc; | |
675 | ||
676 | /* | |
677 | * Context for a MFI frame. | |
678 | * Used to get the mfi cmd from list when a MFI cmd is completed | |
679 | */ | |
680 | u32 sync_cmd_idx; | |
681 | u32 index; | |
682 | u8 flags; | |
d2552ebe | 683 | u8 pd_r1_lb; |
9c915a8c | 684 | }; |
685 | ||
686 | struct LD_LOAD_BALANCE_INFO { | |
687 | u8 loadBalanceFlag; | |
688 | u8 reserved1; | |
d2552ebe SS |
689 | atomic_t scsi_pending_cmds[MAX_PHYSICAL_DEVICES]; |
690 | u64 last_accessed_block[MAX_PHYSICAL_DEVICES]; | |
9c915a8c | 691 | }; |
692 | ||
bc93d425 SS |
693 | /* SPAN_SET is info caclulated from span info from Raid map per LD */ |
694 | typedef struct _LD_SPAN_SET { | |
695 | u64 log_start_lba; | |
696 | u64 log_end_lba; | |
697 | u64 span_row_start; | |
698 | u64 span_row_end; | |
699 | u64 data_strip_start; | |
700 | u64 data_strip_end; | |
701 | u64 data_row_start; | |
702 | u64 data_row_end; | |
703 | u8 strip_offset[MAX_SPAN_DEPTH]; | |
704 | u32 span_row_data_width; | |
705 | u32 diff; | |
706 | u32 reserved[2]; | |
707 | } LD_SPAN_SET, *PLD_SPAN_SET; | |
708 | ||
709 | typedef struct LOG_BLOCK_SPAN_INFO { | |
710 | LD_SPAN_SET span_set[MAX_SPAN_DEPTH]; | |
711 | } LD_SPAN_INFO, *PLD_SPAN_INFO; | |
712 | ||
9c915a8c | 713 | struct MR_FW_RAID_MAP_ALL { |
714 | struct MR_FW_RAID_MAP raidMap; | |
715 | struct MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES - 1]; | |
716 | } __attribute__ ((packed)); | |
717 | ||
51087a86 SS |
718 | struct MR_DRV_RAID_MAP { |
719 | /* total size of this structure, including this field. | |
720 | * This feild will be manupulated by driver for ext raid map, | |
721 | * else pick the value from firmware raid map. | |
722 | */ | |
723 | u32 totalSize; | |
724 | ||
725 | union { | |
726 | struct { | |
727 | u32 maxLd; | |
728 | u32 maxSpanDepth; | |
729 | u32 maxRowSize; | |
730 | u32 maxPdCount; | |
731 | u32 maxArrays; | |
732 | } validationInfo; | |
733 | u32 version[5]; | |
734 | }; | |
735 | ||
736 | /* timeout value used by driver in FP IOs*/ | |
737 | u8 fpPdIoTimeoutSec; | |
738 | u8 reserved2[7]; | |
739 | ||
740 | u16 ldCount; | |
741 | u16 arCount; | |
742 | u16 spanCount; | |
743 | u16 reserve3; | |
744 | ||
745 | struct MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES]; | |
746 | u8 ldTgtIdToLd[MAX_LOGICAL_DRIVES_EXT]; | |
747 | struct MR_ARRAY_INFO arMapInfo[MAX_API_ARRAYS_EXT]; | |
748 | struct MR_LD_SPAN_MAP ldSpanMap[1]; | |
749 | ||
750 | }; | |
751 | ||
752 | /* Driver raid map size is same as raid map ext | |
753 | * MR_DRV_RAID_MAP_ALL is created to sync with old raid. | |
754 | * And it is mainly for code re-use purpose. | |
755 | */ | |
756 | struct MR_DRV_RAID_MAP_ALL { | |
757 | ||
758 | struct MR_DRV_RAID_MAP raidMap; | |
759 | struct MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES_EXT - 1]; | |
760 | } __packed; | |
761 | ||
762 | ||
763 | ||
764 | struct MR_FW_RAID_MAP_EXT { | |
765 | /* Not usred in new map */ | |
766 | u32 reserved; | |
767 | ||
768 | union { | |
769 | struct { | |
770 | u32 maxLd; | |
771 | u32 maxSpanDepth; | |
772 | u32 maxRowSize; | |
773 | u32 maxPdCount; | |
774 | u32 maxArrays; | |
775 | } validationInfo; | |
776 | u32 version[5]; | |
777 | }; | |
778 | ||
779 | u8 fpPdIoTimeoutSec; | |
780 | u8 reserved2[7]; | |
781 | ||
782 | u16 ldCount; | |
783 | u16 arCount; | |
784 | u16 spanCount; | |
785 | u16 reserve3; | |
786 | ||
787 | struct MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES]; | |
788 | u8 ldTgtIdToLd[MAX_LOGICAL_DRIVES_EXT]; | |
789 | struct MR_ARRAY_INFO arMapInfo[MAX_API_ARRAYS_EXT]; | |
790 | struct MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES_EXT]; | |
791 | }; | |
792 | ||
9c915a8c | 793 | struct fusion_context { |
794 | struct megasas_cmd_fusion **cmd_list; | |
795 | struct list_head cmd_pool; | |
796 | ||
90dc9d98 | 797 | spinlock_t mpt_pool_lock; |
9c915a8c | 798 | |
799 | dma_addr_t req_frames_desc_phys; | |
800 | u8 *req_frames_desc; | |
801 | ||
802 | struct dma_pool *io_request_frames_pool; | |
803 | dma_addr_t io_request_frames_phys; | |
804 | u8 *io_request_frames; | |
805 | ||
806 | struct dma_pool *sg_dma_pool; | |
807 | struct dma_pool *sense_dma_pool; | |
808 | ||
809 | dma_addr_t reply_frames_desc_phys; | |
810 | union MPI2_REPLY_DESCRIPTORS_UNION *reply_frames_desc; | |
811 | struct dma_pool *reply_frames_desc_pool; | |
812 | ||
c8e858fe | 813 | u16 last_reply_idx[MAX_MSIX_QUEUES_FUSION]; |
9c915a8c | 814 | |
815 | u32 reply_q_depth; | |
816 | u32 request_alloc_sz; | |
817 | u32 reply_alloc_sz; | |
818 | u32 io_frames_alloc_sz; | |
819 | ||
820 | u16 max_sge_in_main_msg; | |
821 | u16 max_sge_in_chain; | |
822 | ||
823 | u8 chain_offset_io_request; | |
824 | u8 chain_offset_mfi_pthru; | |
825 | ||
826 | struct MR_FW_RAID_MAP_ALL *ld_map[2]; | |
827 | dma_addr_t ld_map_phys[2]; | |
828 | ||
51087a86 SS |
829 | /*Non dma-able memory. Driver local copy.*/ |
830 | struct MR_DRV_RAID_MAP_ALL *ld_drv_map[2]; | |
831 | ||
832 | u32 max_map_sz; | |
833 | u32 current_map_sz; | |
51087a86 SS |
834 | u32 drv_map_sz; |
835 | u32 drv_map_pages; | |
9c915a8c | 836 | u8 fast_path_io; |
51087a86 SS |
837 | struct LD_LOAD_BALANCE_INFO load_balance_info[MAX_LOGICAL_DRIVES_EXT]; |
838 | LD_SPAN_INFO log_to_span[MAX_LOGICAL_DRIVES_EXT]; | |
9c915a8c | 839 | }; |
840 | ||
841 | union desc_value { | |
842 | u64 word; | |
843 | struct { | |
844 | u32 low; | |
845 | u32 high; | |
846 | } u; | |
847 | }; | |
848 | ||
51087a86 | 849 | |
9c915a8c | 850 | #endif /* _MEGARAID_SAS_FUSION_H_ */ |