projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
libsas: enable FPDMA SEND/RECEIVE
[deliverable/linux.git] / drivers / scsi / mvsas / mv_sas.c
CommitLineData
b5762948 1/*
20b09c29
AY		 2 * Marvell 88SE64xx/88SE94xx main function
3 *
4 * Copyright 2007 Red Hat, Inc.
5 * Copyright 2008 Marvell. <kewei@marvell.com>
0b15fb1f 6 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
20b09c29
AY		 7 *
8 * This file is licensed under GPLv2.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; version 2 of the
13 * License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
23 * USA
24*/
b5762948 25
dd4969a8 26#include "mv_sas.h"
b5762948 27
dd4969a8
JG		 28static int mvs_find_tag(struct mvs_info *mvi, struct sas_task *task, u32 *tag)
29{
30 if (task->lldd_task) {
31 struct mvs_slot_info *slot;
f9da3be5 32 slot = task->lldd_task;
20b09c29 33 *tag = slot->slot_tag;
dd4969a8
JG		 34 return 1;
35 }
36 return 0;
37}
8f261aaf 38
20b09c29 39void mvs_tag_clear(struct mvs_info *mvi, u32 tag)
dd4969a8 40{
b89e8f53 41 void *bitmap = mvi->tags;
dd4969a8
JG		 42 clear_bit(tag, bitmap);
43}
8f261aaf 44
20b09c29 45void mvs_tag_free(struct mvs_info *mvi, u32 tag)
dd4969a8
JG		 46{
47 mvs_tag_clear(mvi, tag);
48}
8f261aaf 49
20b09c29 50void mvs_tag_set(struct mvs_info *mvi, unsigned int tag)
dd4969a8 51{
b89e8f53 52 void *bitmap = mvi->tags;
dd4969a8
JG		 53 set_bit(tag, bitmap);
54}
8f261aaf 55
20b09c29 56inline int mvs_tag_alloc(struct mvs_info *mvi, u32 *tag_out)
dd4969a8
JG		 57{
58 unsigned int index, tag;
b89e8f53 59 void *bitmap = mvi->tags;
b5762948 60
20b09c29 61 index = find_first_zero_bit(bitmap, mvi->tags_num);
dd4969a8 62 tag = index;
20b09c29 63 if (tag >= mvi->tags_num)
dd4969a8
JG		 64 return -SAS_QUEUE_FULL;
65 mvs_tag_set(mvi, tag);
66 *tag_out = tag;
67 return 0;
68}
b5762948 69
dd4969a8
JG		 70void mvs_tag_init(struct mvs_info *mvi)
71{
72 int i;
20b09c29 73 for (i = 0; i < mvi->tags_num; ++i)
dd4969a8
JG		 74 mvs_tag_clear(mvi, i);
75}
b5762948 76
20b09c29
AY		 77struct mvs_info *mvs_find_dev_mvi(struct domain_device *dev)
78{
79 unsigned long i = 0, j = 0, hi = 0;
80 struct sas_ha_struct *sha = dev->port->ha;
81 struct mvs_info *mvi = NULL;
82 struct asd_sas_phy *phy;
83
84 while (sha->sas_port[i]) {
85 if (sha->sas_port[i] == dev->port) {
86 phy = container_of(sha->sas_port[i]->phy_list.next,
87 struct asd_sas_phy, port_phy_el);
88 j = 0;
89 while (sha->sas_phy[j]) {
90 if (sha->sas_phy[j] == phy)
91 break;
92 j++;
93 }
94 break;
95 }
96 i++;
97 }
98 hi = j/((struct mvs_prv_info *)sha->lldd_ha)->n_phy;
99 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[hi];
8f261aaf 100
20b09c29 101 return mvi;
8f261aaf 102
20b09c29 103}
8f261aaf 104
20b09c29
AY		 105int mvs_find_dev_phyno(struct domain_device *dev, int *phyno)
106{
107 unsigned long i = 0, j = 0, n = 0, num = 0;
9870d9a2
AY		 108 struct mvs_device *mvi_dev = (struct mvs_device *)dev->lldd_dev;
109 struct mvs_info *mvi = mvi_dev->mvi_info;
20b09c29
AY		 110 struct sas_ha_struct *sha = dev->port->ha;
111
112 while (sha->sas_port[i]) {
113 if (sha->sas_port[i] == dev->port) {
114 struct asd_sas_phy *phy;
115 list_for_each_entry(phy,
116 &sha->sas_port[i]->phy_list, port_phy_el) {
117 j = 0;
118 while (sha->sas_phy[j]) {
119 if (sha->sas_phy[j] == phy)
120 break;
121 j++;
122 }
123 phyno[n] = (j >= mvi->chip->n_phy) ?
124 (j - mvi->chip->n_phy) : j;
125 num++;
126 n++;
dd4969a8 127 }
dd4969a8
JG		 128 break;
129 }
20b09c29
AY		 130 i++;
131 }
132 return num;
133}
134
534ff101
XY		 135struct mvs_device *mvs_find_dev_by_reg_set(struct mvs_info *mvi,
136 u8 reg_set)
137{
138 u32 dev_no;
139 for (dev_no = 0; dev_no < MVS_MAX_DEVICES; dev_no++) {
140 if (mvi->devices[dev_no].taskfileset == MVS_ID_NOT_MAPPED)
141 continue;
142
143 if (mvi->devices[dev_no].taskfileset == reg_set)
144 return &mvi->devices[dev_no];
145 }
146 return NULL;
147}
148
20b09c29
AY		 149static inline void mvs_free_reg_set(struct mvs_info *mvi,
150 struct mvs_device *dev)
151{
152 if (!dev) {
153 mv_printk("device has been free.\n");
154 return;
155 }
20b09c29
AY		 156 if (dev->taskfileset == MVS_ID_NOT_MAPPED)
157 return;
158 MVS_CHIP_DISP->free_reg_set(mvi, &dev->taskfileset);
159}
160
161static inline u8 mvs_assign_reg_set(struct mvs_info *mvi,
162 struct mvs_device *dev)
163{
164 if (dev->taskfileset != MVS_ID_NOT_MAPPED)
165 return 0;
166 return MVS_CHIP_DISP->assign_reg_set(mvi, &dev->taskfileset);
167}
168
169void mvs_phys_reset(struct mvs_info *mvi, u32 phy_mask, int hard)
170{
171 u32 no;
172 for_each_phy(phy_mask, phy_mask, no) {
173 if (!(phy_mask & 1))
174 continue;
175 MVS_CHIP_DISP->phy_reset(mvi, no, hard);
176 }
177}
178
20b09c29
AY		 179int mvs_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func,
180 void *funcdata)
181{
182 int rc = 0, phy_id = sas_phy->id;
183 u32 tmp, i = 0, hi;
184 struct sas_ha_struct *sha = sas_phy->ha;
185 struct mvs_info *mvi = NULL;
186
187 while (sha->sas_phy[i]) {
188 if (sha->sas_phy[i] == sas_phy)
189 break;
190 i++;
191 }
192 hi = i/((struct mvs_prv_info *)sha->lldd_ha)->n_phy;
193 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[hi];
194
195 switch (func) {
196 case PHY_FUNC_SET_LINK_RATE:
197 MVS_CHIP_DISP->phy_set_link_rate(mvi, phy_id, funcdata);
198 break;
8f261aaf 199
dd4969a8 200 case PHY_FUNC_HARD_RESET:
20b09c29 201 tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, phy_id);
dd4969a8
JG		 202 if (tmp & PHY_RST_HARD)
203 break;
a4632aae 204 MVS_CHIP_DISP->phy_reset(mvi, phy_id, MVS_HARD_RESET);
dd4969a8 205 break;
b5762948 206
dd4969a8 207 case PHY_FUNC_LINK_RESET:
20b09c29 208 MVS_CHIP_DISP->phy_enable(mvi, phy_id);
a4632aae 209 MVS_CHIP_DISP->phy_reset(mvi, phy_id, MVS_SOFT_RESET);
dd4969a8 210 break;
b5762948 211
dd4969a8 212 case PHY_FUNC_DISABLE:
20b09c29
AY		 213 MVS_CHIP_DISP->phy_disable(mvi, phy_id);
214 break;
dd4969a8
JG		 215 case PHY_FUNC_RELEASE_SPINUP_HOLD:
216 default:
ac013ed1 217 rc = -ENOSYS;
b5762948 218 }
20b09c29 219 msleep(200);
b5762948
JG		 220 return rc;
221}
222
6f039790
GKH		 223void mvs_set_sas_addr(struct mvs_info *mvi, int port_id, u32 off_lo,
224 u32 off_hi, u64 sas_addr)
20b09c29
AY		 225{
226 u32 lo = (u32)sas_addr;
227 u32 hi = (u32)(sas_addr>>32);
228
229 MVS_CHIP_DISP->write_port_cfg_addr(mvi, port_id, off_lo);
230 MVS_CHIP_DISP->write_port_cfg_data(mvi, port_id, lo);
231 MVS_CHIP_DISP->write_port_cfg_addr(mvi, port_id, off_hi);
232 MVS_CHIP_DISP->write_port_cfg_data(mvi, port_id, hi);
233}
234
dd4969a8 235static void mvs_bytes_dmaed(struct mvs_info *mvi, int i)
ee1f1c2e 236{
dd4969a8 237 struct mvs_phy *phy = &mvi->phy[i];
20b09c29
AY		 238 struct asd_sas_phy *sas_phy = &phy->sas_phy;
239 struct sas_ha_struct *sas_ha;
dd4969a8
JG		 240 if (!phy->phy_attached)
241 return;
242
20b09c29
AY		 243 if (!(phy->att_dev_info & PORT_DEV_TRGT_MASK)
244 && phy->phy_type & PORT_TYPE_SAS) {
245 return;
246 }
247
248 sas_ha = mvi->sas;
249 sas_ha->notify_phy_event(sas_phy, PHYE_OOB_DONE);
250
dd4969a8
JG		 251 if (sas_phy->phy) {
252 struct sas_phy *sphy = sas_phy->phy;
253
254 sphy->negotiated_linkrate = sas_phy->linkrate;
255 sphy->minimum_linkrate = phy->minimum_linkrate;
256 sphy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
257 sphy->maximum_linkrate = phy->maximum_linkrate;
20b09c29 258 sphy->maximum_linkrate_hw = MVS_CHIP_DISP->phy_max_link_rate();
ee1f1c2e 259 }
ee1f1c2e 260
dd4969a8
JG		 261 if (phy->phy_type & PORT_TYPE_SAS) {
262 struct sas_identify_frame *id;
b5762948 263
dd4969a8
JG		 264 id = (struct sas_identify_frame *)phy->frame_rcvd;
265 id->dev_type = phy->identify.device_type;
266 id->initiator_bits = SAS_PROTOCOL_ALL;
267 id->target_bits = phy->identify.target_port_protocols;
477f6d19
XY		 268
269 /* direct attached SAS device */
270 if (phy->att_dev_info & PORT_SSP_TRGT_MASK) {
271 MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_PHY_STAT);
272 MVS_CHIP_DISP->write_port_cfg_data(mvi, i, 0x00);
273 }
dd4969a8 274 } else if (phy->phy_type & PORT_TYPE_SATA) {
20b09c29 275 /*Nothing*/
dd4969a8 276 }
20b09c29
AY		 277 mv_dprintk("phy %d byte dmaded.\n", i + mvi->id * mvi->chip->n_phy);
278
279 sas_phy->frame_rcvd_size = phy->frame_rcvd_size;
280
281 mvi->sas->notify_port_event(sas_phy,
dd4969a8 282 PORTE_BYTES_DMAED);
ee1f1c2e
KW		 283}
284
dd4969a8 285void mvs_scan_start(struct Scsi_Host *shost)
b5762948 286{
20b09c29
AY		 287 int i, j;
288 unsigned short core_nr;
289 struct mvs_info *mvi;
290 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
84fbd0ce 291 struct mvs_prv_info *mvs_prv = sha->lldd_ha;
20b09c29
AY		 292
293 core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
dd4969a8 294
20b09c29
AY		 295 for (j = 0; j < core_nr; j++) {
296 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[j];
297 for (i = 0; i < mvi->chip->n_phy; ++i)
298 mvs_bytes_dmaed(mvi, i);
dd4969a8 299 }
84fbd0ce 300 mvs_prv->scan_finished = 1;
b5762948
JG		 301}
302
dd4969a8 303int mvs_scan_finished(struct Scsi_Host *shost, unsigned long time)
b5762948 304{
84fbd0ce
XY		 305 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
306 struct mvs_prv_info *mvs_prv = sha->lldd_ha;
307
308 if (mvs_prv->scan_finished == 0)
dd4969a8 309 return 0;
84fbd0ce 310
b1124cd3 311 sas_drain_work(sha);
dd4969a8 312 return 1;
b5762948
JG		 313}
314
dd4969a8
JG		 315static int mvs_task_prep_smp(struct mvs_info *mvi,
316 struct mvs_task_exec_info *tei)
b5762948 317{
dd4969a8 318 int elem, rc, i;
7c237c5f 319 struct sas_ha_struct *sha = mvi->sas;
dd4969a8
JG		 320 struct sas_task *task = tei->task;
321 struct mvs_cmd_hdr *hdr = tei->hdr;
20b09c29
AY		 322 struct domain_device *dev = task->dev;
323 struct asd_sas_port *sas_port = dev->port;
7c237c5f
XY		 324 struct sas_phy *sphy = dev->phy;
325 struct asd_sas_phy *sas_phy = sha->sas_phy[sphy->number];
dd4969a8
JG		 326 struct scatterlist *sg_req, *sg_resp;
327 u32 req_len, resp_len, tag = tei->tag;
328 void *buf_tmp;
329 u8 *buf_oaf;
330 dma_addr_t buf_tmp_dma;
20b09c29 331 void *buf_prd;
dd4969a8 332 struct mvs_slot_info *slot = &mvi->slot_info[tag];
dd4969a8 333 u32 flags = (tei->n_elem << MCH_PRD_LEN_SHIFT);
b89e8f53 334
dd4969a8
JG		 335 /*
336 * DMA-map SMP request, response buffers
337 */
338 sg_req = &task->smp_task.smp_req;
20b09c29 339 elem = dma_map_sg(mvi->dev, sg_req, 1, PCI_DMA_TODEVICE);
dd4969a8
JG		 340 if (!elem)
341 return -ENOMEM;
342 req_len = sg_dma_len(sg_req);
b5762948 343
dd4969a8 344 sg_resp = &task->smp_task.smp_resp;
20b09c29 345 elem = dma_map_sg(mvi->dev, sg_resp, 1, PCI_DMA_FROMDEVICE);
dd4969a8
JG		 346 if (!elem) {
347 rc = -ENOMEM;
348 goto err_out;
349 }
20b09c29 350 resp_len = SB_RFB_MAX;
b5762948 351
dd4969a8
JG		 352 /* must be in dwords */
353 if ((req_len & 0x3) || (resp_len & 0x3)) {
354 rc = -EINVAL;
355 goto err_out_2;
b5762948
JG		 356 }
357
dd4969a8
JG		 358 /*
359 * arrange MVS_SLOT_BUF_SZ-sized DMA buffer according to our needs
360 */
b5762948 361
20b09c29 362 /* region 1: command table area (MVS_SSP_CMD_SZ bytes) ***** */
dd4969a8
JG		 363 buf_tmp = slot->buf;
364 buf_tmp_dma = slot->buf_dma;
b5762948 365
dd4969a8 366 hdr->cmd_tbl = cpu_to_le64(sg_dma_address(sg_req));
b5762948 367
dd4969a8
JG		 368 /* region 2: open address frame area (MVS_OAF_SZ bytes) ********* */
369 buf_oaf = buf_tmp;
370 hdr->open_frame = cpu_to_le64(buf_tmp_dma);
b5762948 371
dd4969a8
JG		 372 buf_tmp += MVS_OAF_SZ;
373 buf_tmp_dma += MVS_OAF_SZ;
b5762948 374
20b09c29 375 /* region 3: PRD table *********************************** */
dd4969a8
JG		 376 buf_prd = buf_tmp;
377 if (tei->n_elem)
378 hdr->prd_tbl = cpu_to_le64(buf_tmp_dma);
379 else
380 hdr->prd_tbl = 0;
b5762948 381
20b09c29 382 i = MVS_CHIP_DISP->prd_size() * tei->n_elem;
dd4969a8
JG		 383 buf_tmp += i;
384 buf_tmp_dma += i;
b5762948 385
dd4969a8
JG		 386 /* region 4: status buffer (larger the PRD, smaller this buf) ****** */
387 slot->response = buf_tmp;
388 hdr->status_buf = cpu_to_le64(buf_tmp_dma);
20b09c29
AY		 389 if (mvi->flags & MVF_FLAG_SOC)
390 hdr->reserved[0] = 0;
b5762948 391
dd4969a8
JG		 392 /*
393 * Fill in TX ring and command slot header
394 */
395 slot->tx = mvi->tx_prod;
396 mvi->tx[mvi->tx_prod] = cpu_to_le32((TXQ_CMD_SMP << TXQ_CMD_SHIFT) |
397 TXQ_MODE_I | tag |
7c237c5f 398 (MVS_PHY_ID << TXQ_PHY_SHIFT));
b5762948 399
dd4969a8
JG		 400 hdr->flags |= flags;
401 hdr->lens = cpu_to_le32(((resp_len / 4) << 16) | ((req_len - 4) / 4));
402 hdr->tags = cpu_to_le32(tag);
403 hdr->data_len = 0;
b5762948 404
dd4969a8 405 /* generate open address frame hdr (first 12 bytes) */
20b09c29
AY		 406 /* initiator, SMP, ftype 1h */
407 buf_oaf[0] = (1 << 7) | (PROTOCOL_SMP << 4) | 0x01;
6ceae7c6 408 buf_oaf[1] = min(sas_port->linkrate, dev->linkrate) & 0xf;
dd4969a8 409 *(u16 *)(buf_oaf + 2) = 0xFFFF; /* SAS SPEC */
20b09c29 410 memcpy(buf_oaf + 4, dev->sas_addr, SAS_ADDR_SIZE);
dd4969a8
JG		 411
412 /* fill in PRD (scatter/gather) table, if any */
20b09c29 413 MVS_CHIP_DISP->make_prd(task->scatter, tei->n_elem, buf_prd);
b5762948
JG		 414
415 return 0;
416
dd4969a8 417err_out_2:
20b09c29 418 dma_unmap_sg(mvi->dev, &tei->task->smp_task.smp_resp, 1,
dd4969a8 419 PCI_DMA_FROMDEVICE);
b5762948 420err_out:
20b09c29 421 dma_unmap_sg(mvi->dev, &tei->task->smp_task.smp_req, 1,
dd4969a8 422 PCI_DMA_TODEVICE);
8f261aaf 423 return rc;
8f261aaf
KW		 424}
425
dd4969a8 426static u32 mvs_get_ncq_tag(struct sas_task *task, u32 *tag)
8f261aaf 427{
dd4969a8 428 struct ata_queued_cmd *qc = task->uldd_task;
8f261aaf 429
dd4969a8
JG		 430 if (qc) {
431 if (qc->tf.command == ATA_CMD_FPDMA_WRITE ||
ef026b18
HR		 432 qc->tf.command == ATA_CMD_FPDMA_READ ||
433 qc->tf.command == ATA_CMD_FPDMA_RECV ||
434 qc->tf.command == ATA_CMD_FPDMA_SEND) {
dd4969a8
JG		 435 *tag = qc->tag;
436 return 1;
437 }
8f261aaf 438 }
8f261aaf 439
dd4969a8 440 return 0;
8f261aaf
KW		 441}
442
dd4969a8
JG		 443static int mvs_task_prep_ata(struct mvs_info *mvi,
444 struct mvs_task_exec_info *tei)
b5762948
JG		 445{
446 struct sas_task *task = tei->task;
447 struct domain_device *dev = task->dev;
f9da3be5 448 struct mvs_device *mvi_dev = dev->lldd_dev;
b5762948
JG		 449 struct mvs_cmd_hdr *hdr = tei->hdr;
450 struct asd_sas_port *sas_port = dev->port;
8f261aaf 451 struct mvs_slot_info *slot;
20b09c29
AY		 452 void *buf_prd;
453 u32 tag = tei->tag, hdr_tag;
454 u32 flags, del_q;
b5762948
JG		 455 void *buf_tmp;
456 u8 *buf_cmd, *buf_oaf;
457 dma_addr_t buf_tmp_dma;
8f261aaf
KW		 458 u32 i, req_len, resp_len;
459 const u32 max_resp_len = SB_RFB_MAX;
460
20b09c29
AY		 461 if (mvs_assign_reg_set(mvi, mvi_dev) == MVS_ID_NOT_MAPPED) {
462 mv_dprintk("Have not enough regiset for dev %d.\n",
463 mvi_dev->device_id);
8f261aaf 464 return -EBUSY;
20b09c29 465 }
8f261aaf
KW		 466 slot = &mvi->slot_info[tag];
467 slot->tx = mvi->tx_prod;
20b09c29
AY		 468 del_q = TXQ_MODE_I | tag |
469 (TXQ_CMD_STP << TXQ_CMD_SHIFT) |
56cbd0cc 470 ((sas_port->phy_mask & TXQ_PHY_MASK) << TXQ_PHY_SHIFT) |
20b09c29
AY		 471 (mvi_dev->taskfileset << TXQ_SRS_SHIFT);
472 mvi->tx[mvi->tx_prod] = cpu_to_le32(del_q);
473
20b09c29
AY		 474 if (task->data_dir == DMA_FROM_DEVICE)
475 flags = (MVS_CHIP_DISP->prd_count() << MCH_PRD_LEN_SHIFT);
476 else
477 flags = (tei->n_elem << MCH_PRD_LEN_SHIFT);
8882f081 478
b5762948
JG		 479 if (task->ata_task.use_ncq)
480 flags |= MCH_FPDMA;
1cbd772d 481 if (dev->sata_dev.class == ATA_DEV_ATAPI) {
8f261aaf
KW		 482 if (task->ata_task.fis.command != ATA_CMD_ID_ATAPI)
483 flags |= MCH_ATAPI;
484 }
485
b5762948 486 hdr->flags = cpu_to_le32(flags);
8f261aaf 487
20b09c29
AY		 488 if (task->ata_task.use_ncq && mvs_get_ncq_tag(task, &hdr_tag))
489 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
4e52fc0a 490 else
20b09c29
AY		 491 hdr_tag = tag;
492
493 hdr->tags = cpu_to_le32(hdr_tag);
494
b5762948
JG		 495 hdr->data_len = cpu_to_le32(task->total_xfer_len);
496
497 /*
498 * arrange MVS_SLOT_BUF_SZ-sized DMA buffer according to our needs
499 */
b5762948 500
8f261aaf
KW		 501 /* region 1: command table area (MVS_ATA_CMD_SZ bytes) ************** */
502 buf_cmd = buf_tmp = slot->buf;
b5762948
JG		 503 buf_tmp_dma = slot->buf_dma;
504
505 hdr->cmd_tbl = cpu_to_le64(buf_tmp_dma);
506
507 buf_tmp += MVS_ATA_CMD_SZ;
508 buf_tmp_dma += MVS_ATA_CMD_SZ;
509
8f261aaf 510 /* region 2: open address frame area (MVS_OAF_SZ bytes) ********* */
b5762948
JG		 511 /* used for STP. unused for SATA? */
512 buf_oaf = buf_tmp;
513 hdr->open_frame = cpu_to_le64(buf_tmp_dma);
514
515 buf_tmp += MVS_OAF_SZ;
516 buf_tmp_dma += MVS_OAF_SZ;
517
8f261aaf 518 /* region 3: PRD table ********************************************* */
b5762948 519 buf_prd = buf_tmp;
20b09c29 520
8f261aaf
KW		 521 if (tei->n_elem)
522 hdr->prd_tbl = cpu_to_le64(buf_tmp_dma);
523 else
524 hdr->prd_tbl = 0;
20b09c29 525 i = MVS_CHIP_DISP->prd_size() * MVS_CHIP_DISP->prd_count();
b5762948 526
b5762948
JG		 527 buf_tmp += i;
528 buf_tmp_dma += i;
529
8f261aaf 530 /* region 4: status buffer (larger the PRD, smaller this buf) ****** */
b5762948
JG		 531 slot->response = buf_tmp;
532 hdr->status_buf = cpu_to_le64(buf_tmp_dma);
20b09c29
AY		 533 if (mvi->flags & MVF_FLAG_SOC)
534 hdr->reserved[0] = 0;
b5762948 535
8f261aaf 536 req_len = sizeof(struct host_to_dev_fis);
b5762948 537 resp_len = MVS_SLOT_BUF_SZ - MVS_ATA_CMD_SZ -
8f261aaf 538 sizeof(struct mvs_err_info) - i;
b5762948
JG		 539
540 /* request, response lengths */
8f261aaf 541 resp_len = min(resp_len, max_resp_len);
b5762948
JG		 542 hdr->lens = cpu_to_le32(((resp_len / 4) << 16) | (req_len / 4));
543
20b09c29
AY		 544 if (likely(!task->ata_task.device_control_reg_update))
545 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
b5762948 546 /* fill in command FIS and ATAPI CDB */
8f261aaf 547 memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
1cbd772d 548 if (dev->sata_dev.class == ATA_DEV_ATAPI)
8f261aaf
KW		 549 memcpy(buf_cmd + STP_ATAPI_CMD,
550 task->ata_task.atapi_packet, 16);
551
552 /* generate open address frame hdr (first 12 bytes) */
20b09c29
AY		 553 /* initiator, STP, ftype 1h */
554 buf_oaf[0] = (1 << 7) | (PROTOCOL_STP << 4) | 0x1;
6ceae7c6 555 buf_oaf[1] = min(sas_port->linkrate, dev->linkrate) & 0xf;
20b09c29
AY		 556 *(u16 *)(buf_oaf + 2) = cpu_to_be16(mvi_dev->device_id + 1);
557 memcpy(buf_oaf + 4, dev->sas_addr, SAS_ADDR_SIZE);
b5762948
JG		 558
559 /* fill in PRD (scatter/gather) table, if any */
20b09c29 560 MVS_CHIP_DISP->make_prd(task->scatter, tei->n_elem, buf_prd);
8882f081 561
20b09c29 562 if (task->data_dir == DMA_FROM_DEVICE)
8882f081 563 MVS_CHIP_DISP->dma_fix(mvi, sas_port->phy_mask,
20b09c29 564 TRASH_BUCKET_SIZE, tei->n_elem, buf_prd);
8882f081 565
b5762948
JG		 566 return 0;
567}
568
569static int mvs_task_prep_ssp(struct mvs_info *mvi,
20b09c29
AY		 570 struct mvs_task_exec_info *tei, int is_tmf,
571 struct mvs_tmf_task *tmf)
b5762948
JG		 572{
573 struct sas_task *task = tei->task;
b5762948 574 struct mvs_cmd_hdr *hdr = tei->hdr;
8f261aaf 575 struct mvs_port *port = tei->port;
20b09c29 576 struct domain_device *dev = task->dev;
f9da3be5 577 struct mvs_device *mvi_dev = dev->lldd_dev;
20b09c29 578 struct asd_sas_port *sas_port = dev->port;
b5762948 579 struct mvs_slot_info *slot;
20b09c29 580 void *buf_prd;
b5762948
JG		 581 struct ssp_frame_hdr *ssp_hdr;
582 void *buf_tmp;
583 u8 *buf_cmd, *buf_oaf, fburst = 0;
584 dma_addr_t buf_tmp_dma;
585 u32 flags;
8f261aaf
KW		 586 u32 resp_len, req_len, i, tag = tei->tag;
587 const u32 max_resp_len = SB_RFB_MAX;
20b09c29 588 u32 phy_mask;
b5762948
JG		 589
590 slot = &mvi->slot_info[tag];
591
20b09c29
AY		 592 phy_mask = ((port->wide_port_phymap) ? port->wide_port_phymap :
593 sas_port->phy_mask) & TXQ_PHY_MASK;
594
8f261aaf
KW		 595 slot->tx = mvi->tx_prod;
596 mvi->tx[mvi->tx_prod] = cpu_to_le32(TXQ_MODE_I | tag |
597 (TXQ_CMD_SSP << TXQ_CMD_SHIFT) |
4e52fc0a 598 (phy_mask << TXQ_PHY_SHIFT));
b5762948
JG		 599
600 flags = MCH_RETRY;
601 if (task->ssp_task.enable_first_burst) {
602 flags |= MCH_FBURST;
603 fburst = (1 << 7);
604 }
2b288133
AY		 605 if (is_tmf)
606 flags |= (MCH_SSP_FR_TASK << MCH_SSP_FR_TYPE_SHIFT);
84fbd0ce
XY		 607 else
608 flags |= (MCH_SSP_FR_CMD << MCH_SSP_FR_TYPE_SHIFT);
609
2b288133 610 hdr->flags = cpu_to_le32(flags | (tei->n_elem << MCH_PRD_LEN_SHIFT));
b5762948
JG		 611 hdr->tags = cpu_to_le32(tag);
612 hdr->data_len = cpu_to_le32(task->total_xfer_len);
613
614 /*
615 * arrange MVS_SLOT_BUF_SZ-sized DMA buffer according to our needs
616 */
b5762948 617
8f261aaf
KW		 618 /* region 1: command table area (MVS_SSP_CMD_SZ bytes) ************** */
619 buf_cmd = buf_tmp = slot->buf;
b5762948
JG		 620 buf_tmp_dma = slot->buf_dma;
621
622 hdr->cmd_tbl = cpu_to_le64(buf_tmp_dma);
623
624 buf_tmp += MVS_SSP_CMD_SZ;
625 buf_tmp_dma += MVS_SSP_CMD_SZ;
626
8f261aaf 627 /* region 2: open address frame area (MVS_OAF_SZ bytes) ********* */
b5762948
JG		 628 buf_oaf = buf_tmp;
629 hdr->open_frame = cpu_to_le64(buf_tmp_dma);
630
631 buf_tmp += MVS_OAF_SZ;
632 buf_tmp_dma += MVS_OAF_SZ;
633
8f261aaf 634 /* region 3: PRD table ********************************************* */
b5762948 635 buf_prd = buf_tmp;
8f261aaf
KW		 636 if (tei->n_elem)
637 hdr->prd_tbl = cpu_to_le64(buf_tmp_dma);
638 else
639 hdr->prd_tbl = 0;
b5762948 640
20b09c29 641 i = MVS_CHIP_DISP->prd_size() * tei->n_elem;
b5762948
JG		 642 buf_tmp += i;
643 buf_tmp_dma += i;
644
8f261aaf 645 /* region 4: status buffer (larger the PRD, smaller this buf) ****** */
b5762948
JG		 646 slot->response = buf_tmp;
647 hdr->status_buf = cpu_to_le64(buf_tmp_dma);
20b09c29
AY		 648 if (mvi->flags & MVF_FLAG_SOC)
649 hdr->reserved[0] = 0;
b5762948 650
b5762948 651 resp_len = MVS_SLOT_BUF_SZ - MVS_SSP_CMD_SZ - MVS_OAF_SZ -
8f261aaf
KW		 652 sizeof(struct mvs_err_info) - i;
653 resp_len = min(resp_len, max_resp_len);
654
655 req_len = sizeof(struct ssp_frame_hdr) + 28;
b5762948
JG		 656
657 /* request, response lengths */
658 hdr->lens = cpu_to_le32(((resp_len / 4) << 16) | (req_len / 4));
659
660 /* generate open address frame hdr (first 12 bytes) */
20b09c29
AY		 661 /* initiator, SSP, ftype 1h */
662 buf_oaf[0] = (1 << 7) | (PROTOCOL_SSP << 4) | 0x1;
6ceae7c6 663 buf_oaf[1] = min(sas_port->linkrate, dev->linkrate) & 0xf;
20b09c29
AY		 664 *(u16 *)(buf_oaf + 2) = cpu_to_be16(mvi_dev->device_id + 1);
665 memcpy(buf_oaf + 4, dev->sas_addr, SAS_ADDR_SIZE);
b5762948 666
8f261aaf
KW		 667 /* fill in SSP frame header (Command Table.SSP frame header) */
668 ssp_hdr = (struct ssp_frame_hdr *)buf_cmd;
20b09c29
AY		 669
670 if (is_tmf)
671 ssp_hdr->frame_type = SSP_TASK;
672 else
673 ssp_hdr->frame_type = SSP_COMMAND;
674
675 memcpy(ssp_hdr->hashed_dest_addr, dev->hashed_sas_addr,
b5762948
JG		 676 HASHED_SAS_ADDR_SIZE);
677 memcpy(ssp_hdr->hashed_src_addr,
20b09c29 678 dev->hashed_sas_addr, HASHED_SAS_ADDR_SIZE);
b5762948
JG		 679 ssp_hdr->tag = cpu_to_be16(tag);
680
20b09c29 681 /* fill in IU for TASK and Command Frame */
b5762948
JG		 682 buf_cmd += sizeof(*ssp_hdr);
683 memcpy(buf_cmd, &task->ssp_task.LUN, 8);
b5762948 684
20b09c29
AY		 685 if (ssp_hdr->frame_type != SSP_TASK) {
686 buf_cmd[9] = fburst | task->ssp_task.task_attr |
687 (task->ssp_task.task_prio << 3);
e73823f7
JB		 688 memcpy(buf_cmd + 12, task->ssp_task.cmd->cmnd,
689 task->ssp_task.cmd->cmd_len);
20b09c29
AY		 690 } else{
691 buf_cmd[10] = tmf->tmf;
692 switch (tmf->tmf) {
693 case TMF_ABORT_TASK:
694 case TMF_QUERY_TASK:
695 buf_cmd[12] =
696 (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
697 buf_cmd[13] =
698 tmf->tag_of_task_to_be_managed & 0xff;
699 break;
700 default:
701 break;
702 }
b5762948 703 }
20b09c29
AY		 704 /* fill in PRD (scatter/gather) table, if any */
705 MVS_CHIP_DISP->make_prd(task->scatter, tei->n_elem, buf_prd);
b5762948
JG		 706 return 0;
707}
708
aa9f8328 709#define DEV_IS_GONE(mvi_dev) ((!mvi_dev || (mvi_dev->dev_type == SAS_PHY_UNUSED)))
0b15fb1f
XY		 710static int mvs_task_prep(struct sas_task *task, struct mvs_info *mvi, int is_tmf,
711 struct mvs_tmf_task *tmf, int *pass)
b5762948 712{
8f261aaf 713 struct domain_device *dev = task->dev;
0b15fb1f 714 struct mvs_device *mvi_dev = dev->lldd_dev;
b5762948 715 struct mvs_task_exec_info tei;
4e52fc0a 716 struct mvs_slot_info *slot;
0b15fb1f
XY		 717 u32 tag = 0xdeadbeef, n_elem = 0;
718 int rc = 0;
b5762948 719
20b09c29 720 if (!dev->port) {
0b15fb1f 721 struct task_status_struct *tsm = &task->task_status;
20b09c29
AY		 722
723 tsm->resp = SAS_TASK_UNDELIVERED;
724 tsm->stat = SAS_PHY_DOWN;
0b15fb1f
XY		 725 /*
726 * libsas will use dev->port, should
727 * not call task_done for sata
728 */
aa9f8328 729 if (dev->dev_type != SAS_SATA_DEV)
0b15fb1f
XY		 730 task->task_done(task);
731 return rc;
20b09c29
AY		 732 }
733
0b15fb1f
XY		 734 if (DEV_IS_GONE(mvi_dev)) {
735 if (mvi_dev)
736 mv_dprintk("device %d not ready.\n",
737 mvi_dev->device_id);
738 else
739 mv_dprintk("device %016llx not ready.\n",
740 SAS_ADDR(dev->sas_addr));
20b09c29 741
7789cd39
LB		 742 rc = SAS_PHY_DOWN;
743 return rc;
0b15fb1f
XY		 744 }
745 tei.port = dev->port->lldd_port;
746 if (tei.port && !tei.port->port_attached && !tmf) {
747 if (sas_protocol_ata(task->task_proto)) {
748 struct task_status_struct *ts = &task->task_status;
749 mv_dprintk("SATA/STP port %d does not attach"
750 "device.\n", dev->port->id);
751 ts->resp = SAS_TASK_COMPLETE;
752 ts->stat = SAS_PHY_DOWN;
20b09c29 753
0b15fb1f 754 task->task_done(task);
dd4969a8 755
dd4969a8 756 } else {
0b15fb1f
XY		 757 struct task_status_struct *ts = &task->task_status;
758 mv_dprintk("SAS port %d does not attach"
759 "device.\n", dev->port->id);
760 ts->resp = SAS_TASK_UNDELIVERED;
761 ts->stat = SAS_PHY_DOWN;
762 task->task_done(task);
dd4969a8 763 }
0b15fb1f
XY		 764 return rc;
765 }
dd4969a8 766
0b15fb1f
XY		 767 if (!sas_protocol_ata(task->task_proto)) {
768 if (task->num_scatter) {
769 n_elem = dma_map_sg(mvi->dev,
770 task->scatter,
771 task->num_scatter,
772 task->data_dir);
773 if (!n_elem) {
774 rc = -ENOMEM;
775 goto prep_out;
776 }
777 }
778 } else {
779 n_elem = task->num_scatter;
780 }
20b09c29 781
0b15fb1f
XY		 782 rc = mvs_tag_alloc(mvi, &tag);
783 if (rc)
784 goto err_out;
20b09c29 785
0b15fb1f 786 slot = &mvi->slot_info[tag];
20b09c29 787
0b15fb1f
XY		 788 task->lldd_task = NULL;
789 slot->n_elem = n_elem;
790 slot->slot_tag = tag;
791
792 slot->buf = pci_pool_alloc(mvi->dma_pool, GFP_ATOMIC, &slot->buf_dma);
793 if (!slot->buf)
794 goto err_out_tag;
795 memset(slot->buf, 0, MVS_SLOT_BUF_SZ);
796
797 tei.task = task;
798 tei.hdr = &mvi->slot[tag];
799 tei.tag = tag;
800 tei.n_elem = n_elem;
801 switch (task->task_proto) {
802 case SAS_PROTOCOL_SMP:
803 rc = mvs_task_prep_smp(mvi, &tei);
804 break;
805 case SAS_PROTOCOL_SSP:
806 rc = mvs_task_prep_ssp(mvi, &tei, is_tmf, tmf);
807 break;
808 case SAS_PROTOCOL_SATA:
809 case SAS_PROTOCOL_STP:
810 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
811 rc = mvs_task_prep_ata(mvi, &tei);
812 break;
813 default:
814 dev_printk(KERN_ERR, mvi->dev,
815 "unknown sas_task proto: 0x%x\n",
816 task->task_proto);
817 rc = -EINVAL;
818 break;
819 }
dd4969a8 820
0b15fb1f
XY		 821 if (rc) {
822 mv_dprintk("rc is %x\n", rc);
823 goto err_out_slot_buf;
824 }
825 slot->task = task;
826 slot->port = tei.port;
827 task->lldd_task = slot;
828 list_add_tail(&slot->entry, &tei.port->list);
829 spin_lock(&task->task_state_lock);
830 task->task_state_flags |= SAS_TASK_AT_INITIATOR;
831 spin_unlock(&task->task_state_lock);
832
0b15fb1f
XY		 833 mvi_dev->running_req++;
834 ++(*pass);
835 mvi->tx_prod = (mvi->tx_prod + 1) & (MVS_CHIP_SLOT_SZ - 1);
9dc9fd94 836
0b15fb1f 837 return rc;
dd4969a8 838
0b15fb1f
XY		 839err_out_slot_buf:
840 pci_pool_free(mvi->dma_pool, slot->buf, slot->buf_dma);
dd4969a8
JG		 841err_out_tag:
842 mvs_tag_free(mvi, tag);
843err_out:
20b09c29 844
0b15fb1f
XY		 845 dev_printk(KERN_ERR, mvi->dev, "mvsas prep failed[%d]!\n", rc);
846 if (!sas_protocol_ata(task->task_proto))
dd4969a8 847 if (n_elem)
0b15fb1f
XY		 848 dma_unmap_sg(mvi->dev, task->scatter, n_elem,
849 task->data_dir);
850prep_out:
851 return rc;
852}
853
79855d17 854static int mvs_task_exec(struct sas_task *task, gfp_t gfp_flags,
0b15fb1f
XY		 855 struct completion *completion, int is_tmf,
856 struct mvs_tmf_task *tmf)
857{
0b15fb1f
XY		 858 struct mvs_info *mvi = NULL;
859 u32 rc = 0;
860 u32 pass = 0;
861 unsigned long flags = 0;
862
863 mvi = ((struct mvs_device *)task->dev->lldd_dev)->mvi_info;
864
0b15fb1f
XY		 865 spin_lock_irqsave(&mvi->lock, flags);
866 rc = mvs_task_prep(task, mvi, is_tmf, tmf, &pass);
867 if (rc)
868 dev_printk(KERN_ERR, mvi->dev, "mvsas exec failed[%d]!\n", rc);
869
870 if (likely(pass))
871 MVS_CHIP_DISP->start_delivery(mvi, (mvi->tx_prod - 1) &
872 (MVS_CHIP_SLOT_SZ - 1));
0b84b709 873 spin_unlock_irqrestore(&mvi->lock, flags);
0b15fb1f 874
0b15fb1f
XY		 875 return rc;
876}
877
79855d17 878int mvs_queue_command(struct sas_task *task, gfp_t gfp_flags)
20b09c29 879{
79855d17 880 return mvs_task_exec(task, gfp_flags, NULL, 0, NULL);
20b09c29
AY		 881}
882
dd4969a8
JG		 883static void mvs_slot_free(struct mvs_info *mvi, u32 rx_desc)
884{
885 u32 slot_idx = rx_desc & RXQ_SLOT_MASK;
886 mvs_tag_clear(mvi, slot_idx);
887}
888
889static void mvs_slot_task_free(struct mvs_info *mvi, struct sas_task *task,
890 struct mvs_slot_info *slot, u32 slot_idx)
891{
22805217
DM		 892 if (!slot)
893 return;
20b09c29
AY		 894 if (!slot->task)
895 return;
dd4969a8
JG		 896 if (!sas_protocol_ata(task->task_proto))
897 if (slot->n_elem)
20b09c29 898 dma_unmap_sg(mvi->dev, task->scatter,
dd4969a8
JG		 899 slot->n_elem, task->data_dir);
900
901 switch (task->task_proto) {
902 case SAS_PROTOCOL_SMP:
20b09c29 903 dma_unmap_sg(mvi->dev, &task->smp_task.smp_resp, 1,
dd4969a8 904 PCI_DMA_FROMDEVICE);
20b09c29 905 dma_unmap_sg(mvi->dev, &task->smp_task.smp_req, 1,
dd4969a8
JG		 906 PCI_DMA_TODEVICE);
907 break;
908
909 case SAS_PROTOCOL_SATA:
910 case SAS_PROTOCOL_STP:
911 case SAS_PROTOCOL_SSP:
912 default:
913 /* do nothing */
914 break;
915 }
0b15fb1f
XY		 916
917 if (slot->buf) {
918 pci_pool_free(mvi->dma_pool, slot->buf, slot->buf_dma);
919 slot->buf = NULL;
920 }
20b09c29 921 list_del_init(&slot->entry);
dd4969a8
JG		 922 task->lldd_task = NULL;
923 slot->task = NULL;
924 slot->port = NULL;
20b09c29
AY		 925 slot->slot_tag = 0xFFFFFFFF;
926 mvs_slot_free(mvi, slot_idx);
dd4969a8
JG		 927}
928
84fbd0ce 929static void mvs_update_wideport(struct mvs_info *mvi, int phy_no)
dd4969a8 930{
84fbd0ce 931 struct mvs_phy *phy = &mvi->phy[phy_no];
dd4969a8
JG		 932 struct mvs_port *port = phy->port;
933 int j, no;
934
20b09c29
AY		 935 for_each_phy(port->wide_port_phymap, j, no) {
936 if (j & 1) {
937 MVS_CHIP_DISP->write_port_cfg_addr(mvi, no,
938 PHYR_WIDE_PORT);
939 MVS_CHIP_DISP->write_port_cfg_data(mvi, no,
dd4969a8
JG		 940 port->wide_port_phymap);
941 } else {
20b09c29
AY		 942 MVS_CHIP_DISP->write_port_cfg_addr(mvi, no,
943 PHYR_WIDE_PORT);
944 MVS_CHIP_DISP->write_port_cfg_data(mvi, no,
945 0);
dd4969a8 946 }
20b09c29 947 }
dd4969a8
JG		 948}
949
950static u32 mvs_is_phy_ready(struct mvs_info *mvi, int i)
951{
952 u32 tmp;
953 struct mvs_phy *phy = &mvi->phy[i];
20b09c29 954 struct mvs_port *port = phy->port;
dd4969a8 955
20b09c29 956 tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, i);
dd4969a8
JG		 957 if ((tmp & PHY_READY_MASK) && !(phy->irq_status & PHYEV_POOF)) {
958 if (!port)
959 phy->phy_attached = 1;
960 return tmp;
961 }
962
963 if (port) {
964 if (phy->phy_type & PORT_TYPE_SAS) {
965 port->wide_port_phymap &= ~(1U << i);
966 if (!port->wide_port_phymap)
967 port->port_attached = 0;
968 mvs_update_wideport(mvi, i);
969 } else if (phy->phy_type & PORT_TYPE_SATA)
970 port->port_attached = 0;
dd4969a8
JG		 971 phy->port = NULL;
972 phy->phy_attached = 0;
973 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
974 }
975 return 0;
976}
977
978static void *mvs_get_d2h_reg(struct mvs_info *mvi, int i, void *buf)
979{
980 u32 *s = (u32 *) buf;
981
982 if (!s)
983 return NULL;
984
20b09c29 985 MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG3);
84fbd0ce 986 s[3] = cpu_to_le32(MVS_CHIP_DISP->read_port_cfg_data(mvi, i));
dd4969a8 987
20b09c29 988 MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG2);
84fbd0ce 989 s[2] = cpu_to_le32(MVS_CHIP_DISP->read_port_cfg_data(mvi, i));
dd4969a8 990
20b09c29 991 MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG1);
84fbd0ce 992 s[1] = cpu_to_le32(MVS_CHIP_DISP->read_port_cfg_data(mvi, i));
dd4969a8 993
20b09c29 994 MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG0);
84fbd0ce 995 s[0] = cpu_to_le32(MVS_CHIP_DISP->read_port_cfg_data(mvi, i));
20b09c29 996
20b09c29
AY		 997 if (((s[1] & 0x00FFFFFF) == 0x00EB1401) && (*(u8 *)&s[3] == 0x01))
998 s[1] = 0x00EB1401 | (*((u8 *)&s[1] + 3) & 0x10);
dd4969a8 999
f9da3be5 1000 return s;
dd4969a8
JG		 1001}
1002
1003static u32 mvs_is_sig_fis_received(u32 irq_status)
1004{
1005 return irq_status & PHYEV_SIG_FIS;
1006}
1007
8882f081
XY		 1008static void mvs_sig_remove_timer(struct mvs_phy *phy)
1009{
1010 if (phy->timer.function)
1011 del_timer(&phy->timer);
1012 phy->timer.function = NULL;
1013}
1014
20b09c29 1015void mvs_update_phyinfo(struct mvs_info *mvi, int i, int get_st)
dd4969a8
JG		 1016{
1017 struct mvs_phy *phy = &mvi->phy[i];
20b09c29 1018 struct sas_identify_frame *id;
b5762948 1019
20b09c29 1020 id = (struct sas_identify_frame *)phy->frame_rcvd;
b5762948 1021
dd4969a8 1022 if (get_st) {
20b09c29 1023 phy->irq_status = MVS_CHIP_DISP->read_port_irq_stat(mvi, i);
dd4969a8
JG		 1024 phy->phy_status = mvs_is_phy_ready(mvi, i);
1025 }
8f261aaf 1026
dd4969a8 1027 if (phy->phy_status) {
20b09c29
AY		 1028 int oob_done = 0;
1029 struct asd_sas_phy *sas_phy = &mvi->phy[i].sas_phy;
b5762948 1030
20b09c29
AY		 1031 oob_done = MVS_CHIP_DISP->oob_done(mvi, i);
1032
1033 MVS_CHIP_DISP->fix_phy_info(mvi, i, id);
1034 if (phy->phy_type & PORT_TYPE_SATA) {
1035 phy->identify.target_port_protocols = SAS_PROTOCOL_STP;
1036 if (mvs_is_sig_fis_received(phy->irq_status)) {
8882f081 1037 mvs_sig_remove_timer(phy);
20b09c29
AY		 1038 phy->phy_attached = 1;
1039 phy->att_dev_sas_addr =
1040 i + mvi->id * mvi->chip->n_phy;
1041 if (oob_done)
1042 sas_phy->oob_mode = SATA_OOB_MODE;
1043 phy->frame_rcvd_size =
1044 sizeof(struct dev_to_host_fis);
f9da3be5 1045 mvs_get_d2h_reg(mvi, i, id);
20b09c29
AY		 1046 } else {
1047 u32 tmp;
1048 dev_printk(KERN_DEBUG, mvi->dev,
1049 "Phy%d : No sig fis\n", i);
1050 tmp = MVS_CHIP_DISP->read_port_irq_mask(mvi, i);
1051 MVS_CHIP_DISP->write_port_irq_mask(mvi, i,
1052 tmp | PHYEV_SIG_FIS);
1053 phy->phy_attached = 0;
1054 phy->phy_type &= ~PORT_TYPE_SATA;
20b09c29
AY		 1055 goto out_done;
1056 }
9dc9fd94 1057 } else if (phy->phy_type & PORT_TYPE_SAS
20b09c29
AY		 1058 || phy->att_dev_info & PORT_SSP_INIT_MASK) {
1059 phy->phy_attached = 1;
dd4969a8 1060 phy->identify.device_type =
20b09c29 1061 phy->att_dev_info & PORT_DEV_TYPE_MASK;
b5762948 1062
aa9f8328 1063 if (phy->identify.device_type == SAS_END_DEVICE)
dd4969a8
JG		 1064 phy->identify.target_port_protocols =
1065 SAS_PROTOCOL_SSP;
aa9f8328 1066 else if (phy->identify.device_type != SAS_PHY_UNUSED)
dd4969a8
JG		 1067 phy->identify.target_port_protocols =
1068 SAS_PROTOCOL_SMP;
20b09c29 1069 if (oob_done)
dd4969a8
JG		 1070 sas_phy->oob_mode = SAS_OOB_MODE;
1071 phy->frame_rcvd_size =
1072 sizeof(struct sas_identify_frame);
dd4969a8 1073 }
20b09c29
AY		 1074 memcpy(sas_phy->attached_sas_addr,
1075 &phy->att_dev_sas_addr, SAS_ADDR_SIZE);
b5762948 1076
20b09c29
AY		 1077 if (MVS_CHIP_DISP->phy_work_around)
1078 MVS_CHIP_DISP->phy_work_around(mvi, i);
dd4969a8 1079 }
84fbd0ce 1080 mv_dprintk("phy %d attach dev info is %x\n",
20b09c29 1081 i + mvi->id * mvi->chip->n_phy, phy->att_dev_info);
84fbd0ce 1082 mv_dprintk("phy %d attach sas addr is %llx\n",
20b09c29 1083 i + mvi->id * mvi->chip->n_phy, phy->att_dev_sas_addr);
4e52fc0a 1084out_done:
dd4969a8 1085 if (get_st)
20b09c29 1086 MVS_CHIP_DISP->write_port_irq_stat(mvi, i, phy->irq_status);
b5762948
JG		 1087}
1088
20b09c29 1089static void mvs_port_notify_formed(struct asd_sas_phy *sas_phy, int lock)
8f261aaf 1090{
dd4969a8 1091 struct sas_ha_struct *sas_ha = sas_phy->ha;
20b09c29 1092 struct mvs_info *mvi = NULL; int i = 0, hi;
dd4969a8 1093 struct mvs_phy *phy = sas_phy->lldd_phy;
20b09c29
AY		 1094 struct asd_sas_port *sas_port = sas_phy->port;
1095 struct mvs_port *port;
1096 unsigned long flags = 0;
1097 if (!sas_port)
1098 return;
8f261aaf 1099
20b09c29
AY		 1100 while (sas_ha->sas_phy[i]) {
1101 if (sas_ha->sas_phy[i] == sas_phy)
1102 break;
1103 i++;
1104 }
1105 hi = i/((struct mvs_prv_info *)sas_ha->lldd_ha)->n_phy;
1106 mvi = ((struct mvs_prv_info *)sas_ha->lldd_ha)->mvi[hi];
84fbd0ce
XY		 1107 if (i >= mvi->chip->n_phy)
1108 port = &mvi->port[i - mvi->chip->n_phy];
20b09c29 1109 else
84fbd0ce 1110 port = &mvi->port[i];
20b09c29
AY		 1111 if (lock)
1112 spin_lock_irqsave(&mvi->lock, flags);
dd4969a8
JG		 1113 port->port_attached = 1;
1114 phy->port = port;
0b15fb1f 1115 sas_port->lldd_port = port;
dd4969a8
JG		 1116 if (phy->phy_type & PORT_TYPE_SAS) {
1117 port->wide_port_phymap = sas_port->phy_mask;
20b09c29 1118 mv_printk("set wide port phy map %x\n", sas_port->phy_mask);
dd4969a8 1119 mvs_update_wideport(mvi, sas_phy->id);
477f6d19
XY		 1120
1121 /* direct attached SAS device */
1122 if (phy->att_dev_info & PORT_SSP_TRGT_MASK) {
1123 MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_PHY_STAT);
1124 MVS_CHIP_DISP->write_port_cfg_data(mvi, i, 0x04);
1125 }
8f261aaf 1126 }
20b09c29
AY		 1127 if (lock)
1128 spin_unlock_irqrestore(&mvi->lock, flags);
dd4969a8
JG		 1129}
1130
20b09c29 1131static void mvs_port_notify_deformed(struct asd_sas_phy *sas_phy, int lock)
dd4969a8 1132{
9dc9fd94
S		 1133 struct domain_device *dev;
1134 struct mvs_phy *phy = sas_phy->lldd_phy;
1135 struct mvs_info *mvi = phy->mvi;
1136 struct asd_sas_port *port = sas_phy->port;
1137 int phy_no = 0;
1138
1139 while (phy != &mvi->phy[phy_no]) {
1140 phy_no++;
1141 if (phy_no >= MVS_MAX_PHYS)
1142 return;
1143 }
1144 list_for_each_entry(dev, &port->dev_list, dev_list_node)
84fbd0ce 1145 mvs_do_release_task(phy->mvi, phy_no, dev);
9dc9fd94 1146
dd4969a8
JG		 1147}
1148
dd4969a8 1149
20b09c29
AY		 1150void mvs_port_formed(struct asd_sas_phy *sas_phy)
1151{
1152 mvs_port_notify_formed(sas_phy, 1);
dd4969a8
JG		 1153}
1154
20b09c29 1155void mvs_port_deformed(struct asd_sas_phy *sas_phy)
dd4969a8 1156{
20b09c29
AY		 1157 mvs_port_notify_deformed(sas_phy, 1);
1158}
8f261aaf 1159
20b09c29
AY		 1160struct mvs_device *mvs_alloc_dev(struct mvs_info *mvi)
1161{
1162 u32 dev;
1163 for (dev = 0; dev < MVS_MAX_DEVICES; dev++) {
aa9f8328 1164 if (mvi->devices[dev].dev_type == SAS_PHY_UNUSED) {
20b09c29
AY		 1165 mvi->devices[dev].device_id = dev;
1166 return &mvi->devices[dev];
1167 }
8f261aaf 1168 }
8121ed42 1169
20b09c29
AY		 1170 if (dev == MVS_MAX_DEVICES)
1171 mv_printk("max support %d devices, ignore ..\n",
1172 MVS_MAX_DEVICES);
1173
1174 return NULL;
8f261aaf
KW		 1175}
1176
20b09c29 1177void mvs_free_dev(struct mvs_device *mvi_dev)
b5762948 1178{
20b09c29
AY		 1179 u32 id = mvi_dev->device_id;
1180 memset(mvi_dev, 0, sizeof(*mvi_dev));
1181 mvi_dev->device_id = id;
aa9f8328 1182 mvi_dev->dev_type = SAS_PHY_UNUSED;
20b09c29
AY		 1183 mvi_dev->dev_status = MVS_DEV_NORMAL;
1184 mvi_dev->taskfileset = MVS_ID_NOT_MAPPED;
1185}
b5762948 1186
20b09c29
AY		 1187int mvs_dev_found_notify(struct domain_device *dev, int lock)
1188{
1189 unsigned long flags = 0;
1190 int res = 0;
1191 struct mvs_info *mvi = NULL;
1192 struct domain_device *parent_dev = dev->parent;
1193 struct mvs_device *mvi_device;
b5762948 1194
20b09c29 1195 mvi = mvs_find_dev_mvi(dev);
b5762948 1196
20b09c29
AY		 1197 if (lock)
1198 spin_lock_irqsave(&mvi->lock, flags);
1199
1200 mvi_device = mvs_alloc_dev(mvi);
1201 if (!mvi_device) {
1202 res = -1;
1203 goto found_out;
b5762948 1204 }
f9da3be5 1205 dev->lldd_dev = mvi_device;
9dc9fd94 1206 mvi_device->dev_status = MVS_DEV_NORMAL;
20b09c29 1207 mvi_device->dev_type = dev->dev_type;
9870d9a2 1208 mvi_device->mvi_info = mvi;
84fbd0ce 1209 mvi_device->sas_device = dev;
20b09c29
AY		 1210 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) {
1211 int phy_id;
1212 u8 phy_num = parent_dev->ex_dev.num_phys;
1213 struct ex_phy *phy;
1214 for (phy_id = 0; phy_id < phy_num; phy_id++) {
1215 phy = &parent_dev->ex_dev.ex_phy[phy_id];
1216 if (SAS_ADDR(phy->attached_sas_addr) ==
1217 SAS_ADDR(dev->sas_addr)) {
1218 mvi_device->attached_phy = phy_id;
1219 break;
1220 }
1221 }
b5762948 1222
20b09c29
AY		 1223 if (phy_id == phy_num) {
1224 mv_printk("Error: no attached dev:%016llx"
1225 "at ex:%016llx.\n",
1226 SAS_ADDR(dev->sas_addr),
1227 SAS_ADDR(parent_dev->sas_addr));
1228 res = -1;
1229 }
dd4969a8 1230 }
b5762948 1231
20b09c29
AY		 1232found_out:
1233 if (lock)
1234 spin_unlock_irqrestore(&mvi->lock, flags);
1235 return res;
1236}
b5762948 1237
20b09c29
AY		 1238int mvs_dev_found(struct domain_device *dev)
1239{
1240 return mvs_dev_found_notify(dev, 1);
1241}
b5762948 1242
9dc9fd94 1243void mvs_dev_gone_notify(struct domain_device *dev)
20b09c29
AY		 1244{
1245 unsigned long flags = 0;
f9da3be5 1246 struct mvs_device *mvi_dev = dev->lldd_dev;
eaa015d2 1247 struct mvs_info *mvi;
b5762948 1248
eaa015d2 1249 if (!mvi_dev) {
20b09c29 1250 mv_dprintk("found dev has gone.\n");
eaa015d2 1251 return;
b5762948 1252 }
eaa015d2
RS		 1253
1254 mvi = mvi_dev->mvi_info;
1255
1256 spin_lock_irqsave(&mvi->lock, flags);
1257
1258 mv_dprintk("found dev[%d:%x] is gone.\n",
1259 mvi_dev->device_id, mvi_dev->dev_type);
1260 mvs_release_task(mvi, dev);
1261 mvs_free_reg_set(mvi, mvi_dev);
1262 mvs_free_dev(mvi_dev);
1263
20b09c29 1264 dev->lldd_dev = NULL;
84fbd0ce 1265 mvi_dev->sas_device = NULL;
b5762948 1266
9dc9fd94 1267 spin_unlock_irqrestore(&mvi->lock, flags);
b5762948
JG		 1268}
1269
b5762948 1270
20b09c29
AY		 1271void mvs_dev_gone(struct domain_device *dev)
1272{
9dc9fd94 1273 mvs_dev_gone_notify(dev);
20b09c29 1274}
b5762948 1275
20b09c29
AY		 1276static void mvs_task_done(struct sas_task *task)
1277{
f0bf750c 1278 if (!del_timer(&task->slow_task->timer))
20b09c29 1279 return;
f0bf750c 1280 complete(&task->slow_task->completion);
b5762948 1281}
b5762948 1282
20b09c29 1283static void mvs_tmf_timedout(unsigned long data)
b5762948 1284{
20b09c29 1285 struct sas_task *task = (struct sas_task *)data;
8f261aaf 1286
20b09c29 1287 task->task_state_flags |= SAS_TASK_STATE_ABORTED;
f0bf750c 1288 complete(&task->slow_task->completion);
20b09c29 1289}
8f261aaf 1290
20b09c29
AY		 1291#define MVS_TASK_TIMEOUT 20
1292static int mvs_exec_internal_tmf_task(struct domain_device *dev,
1293 void *parameter, u32 para_len, struct mvs_tmf_task *tmf)
1294{
1295 int res, retry;
1296 struct sas_task *task = NULL;
8f261aaf 1297
20b09c29 1298 for (retry = 0; retry < 3; retry++) {
f0bf750c 1299 task = sas_alloc_slow_task(GFP_KERNEL);
20b09c29
AY		 1300 if (!task)
1301 return -ENOMEM;
8f261aaf 1302
20b09c29
AY		 1303 task->dev = dev;
1304 task->task_proto = dev->tproto;
8f261aaf 1305
20b09c29
AY		 1306 memcpy(&task->ssp_task, parameter, para_len);
1307 task->task_done = mvs_task_done;
8f261aaf 1308
f0bf750c
DW		 1309 task->slow_task->timer.data = (unsigned long) task;
1310 task->slow_task->timer.function = mvs_tmf_timedout;
1311 task->slow_task->timer.expires = jiffies + MVS_TASK_TIMEOUT*HZ;
1312 add_timer(&task->slow_task->timer);
8f261aaf 1313
79855d17 1314 res = mvs_task_exec(task, GFP_KERNEL, NULL, 1, tmf);
8f261aaf 1315
20b09c29 1316 if (res) {
f0bf750c 1317 del_timer(&task->slow_task->timer);
6d3be300 1318 mv_printk("executing internal task failed:%d\n", res);
20b09c29
AY		 1319 goto ex_err;
1320 }
8f261aaf 1321
f0bf750c 1322 wait_for_completion(&task->slow_task->completion);
84fbd0ce 1323 res = TMF_RESP_FUNC_FAILED;
20b09c29
AY		 1324 /* Even TMF timed out, return direct. */
1325 if ((task->task_state_flags & SAS_TASK_STATE_ABORTED)) {
1326 if (!(task->task_state_flags & SAS_TASK_STATE_DONE)) {
1327 mv_printk("TMF task[%x] timeout.\n", tmf->tmf);
1328 goto ex_err;
1329 }
1330 }
8f261aaf 1331
20b09c29 1332 if (task->task_status.resp == SAS_TASK_COMPLETE &&
df64d3ca 1333 task->task_status.stat == SAM_STAT_GOOD) {
20b09c29
AY		 1334 res = TMF_RESP_FUNC_COMPLETE;
1335 break;
1336 }
b5762948 1337
20b09c29
AY		 1338 if (task->task_status.resp == SAS_TASK_COMPLETE &&
1339 task->task_status.stat == SAS_DATA_UNDERRUN) {
1340 /* no error, but return the number of bytes of
1341 * underrun */
1342 res = task->task_status.residual;
1343 break;
1344 }
b5762948 1345
20b09c29
AY		 1346 if (task->task_status.resp == SAS_TASK_COMPLETE &&
1347 task->task_status.stat == SAS_DATA_OVERRUN) {
1348 mv_dprintk("blocked task error.\n");
1349 res = -EMSGSIZE;
1350 break;
1351 } else {
1352 mv_dprintk(" task to dev %016llx response: 0x%x "
1353 "status 0x%x\n",
1354 SAS_ADDR(dev->sas_addr),
1355 task->task_status.resp,
1356 task->task_status.stat);
4fcf812c 1357 sas_free_task(task);
20b09c29 1358 task = NULL;
b5762948 1359
dd4969a8 1360 }
dd4969a8 1361 }
20b09c29
AY		 1362ex_err:
1363 BUG_ON(retry == 3 && task != NULL);
4fcf812c 1364 sas_free_task(task);
20b09c29 1365 return res;
dd4969a8 1366}
b5762948 1367
20b09c29
AY		 1368static int mvs_debug_issue_ssp_tmf(struct domain_device *dev,
1369 u8 *lun, struct mvs_tmf_task *tmf)
dd4969a8 1370{
20b09c29 1371 struct sas_ssp_task ssp_task;
20b09c29
AY		 1372 if (!(dev->tproto & SAS_PROTOCOL_SSP))
1373 return TMF_RESP_FUNC_ESUPP;
b5762948 1374
84fbd0ce 1375 memcpy(ssp_task.LUN, lun, 8);
b5762948 1376
20b09c29
AY		 1377 return mvs_exec_internal_tmf_task(dev, &ssp_task,
1378 sizeof(ssp_task), tmf);
1379}
8f261aaf 1380
8f261aaf 1381
20b09c29
AY		 1382/* Standard mandates link reset for ATA (type 0)
1383 and hard reset for SSP (type 1) , only for RECOVERY */
1384static int mvs_debug_I_T_nexus_reset(struct domain_device *dev)
1385{
1386 int rc;
f41a0c44 1387 struct sas_phy *phy = sas_get_local_phy(dev);
aa9f8328 1388 int reset_type = (dev->dev_type == SAS_SATA_DEV ||
20b09c29
AY		 1389 (dev->tproto & SAS_PROTOCOL_STP)) ? 0 : 1;
1390 rc = sas_phy_reset(phy, reset_type);
f41a0c44 1391 sas_put_local_phy(phy);
20b09c29
AY		 1392 msleep(2000);
1393 return rc;
1394}
8f261aaf 1395
20b09c29
AY		 1396/* mandatory SAM-3 */
1397int mvs_lu_reset(struct domain_device *dev, u8 *lun)
1398{
1399 unsigned long flags;
84fbd0ce 1400 int rc = TMF_RESP_FUNC_FAILED;
20b09c29 1401 struct mvs_tmf_task tmf_task;
f9da3be5 1402 struct mvs_device * mvi_dev = dev->lldd_dev;
9870d9a2 1403 struct mvs_info *mvi = mvi_dev->mvi_info;
20b09c29
AY		 1404
1405 tmf_task.tmf = TMF_LU_RESET;
1406 mvi_dev->dev_status = MVS_DEV_EH;
1407 rc = mvs_debug_issue_ssp_tmf(dev, lun, &tmf_task);
1408 if (rc == TMF_RESP_FUNC_COMPLETE) {
20b09c29 1409 spin_lock_irqsave(&mvi->lock, flags);
84fbd0ce 1410 mvs_release_task(mvi, dev);
20b09c29 1411 spin_unlock_irqrestore(&mvi->lock, flags);
dd4969a8 1412 }
20b09c29
AY		 1413 /* If failed, fall-through I_T_Nexus reset */
1414 mv_printk("%s for device[%x]:rc= %d\n", __func__,
1415 mvi_dev->device_id, rc);
1416 return rc;
1417}
8f261aaf 1418
20b09c29
AY		 1419int mvs_I_T_nexus_reset(struct domain_device *dev)
1420{
1421 unsigned long flags;
9dc9fd94
S		 1422 int rc = TMF_RESP_FUNC_FAILED;
1423 struct mvs_device * mvi_dev = (struct mvs_device *)dev->lldd_dev;
9870d9a2 1424 struct mvs_info *mvi = mvi_dev->mvi_info;
20b09c29
AY		 1425
1426 if (mvi_dev->dev_status != MVS_DEV_EH)
1427 return TMF_RESP_FUNC_COMPLETE;
84fbd0ce
XY		 1428 else
1429 mvi_dev->dev_status = MVS_DEV_NORMAL;
20b09c29
AY		 1430 rc = mvs_debug_I_T_nexus_reset(dev);
1431 mv_printk("%s for device[%x]:rc= %d\n",
1432 __func__, mvi_dev->device_id, rc);
1433
20b09c29 1434 spin_lock_irqsave(&mvi->lock, flags);
9dc9fd94 1435 mvs_release_task(mvi, dev);
20b09c29
AY		 1436 spin_unlock_irqrestore(&mvi->lock, flags);
1437
1438 return rc;
1439}
1440/* optional SAM-3 */
1441int mvs_query_task(struct sas_task *task)
1442{
1443 u32 tag;
1444 struct scsi_lun lun;
1445 struct mvs_tmf_task tmf_task;
1446 int rc = TMF_RESP_FUNC_FAILED;
1447
1448 if (task->lldd_task && task->task_proto & SAS_PROTOCOL_SSP) {
1449 struct scsi_cmnd * cmnd = (struct scsi_cmnd *)task->uldd_task;
1450 struct domain_device *dev = task->dev;
9870d9a2
AY		 1451 struct mvs_device *mvi_dev = (struct mvs_device *)dev->lldd_dev;
1452 struct mvs_info *mvi = mvi_dev->mvi_info;
20b09c29
AY		 1453
1454 int_to_scsilun(cmnd->device->lun, &lun);
1455 rc = mvs_find_tag(mvi, task, &tag);
1456 if (rc == 0) {
1457 rc = TMF_RESP_FUNC_FAILED;
dd4969a8 1458 return rc;
20b09c29 1459 }
8f261aaf 1460
20b09c29
AY		 1461 tmf_task.tmf = TMF_QUERY_TASK;
1462 tmf_task.tag_of_task_to_be_managed = cpu_to_le16(tag);
8f261aaf 1463
20b09c29
AY		 1464 rc = mvs_debug_issue_ssp_tmf(dev, lun.scsi_lun, &tmf_task);
1465 switch (rc) {
1466 /* The task is still in Lun, release it then */
1467 case TMF_RESP_FUNC_SUCC:
1468 /* The task is not in Lun or failed, reset the phy */
1469 case TMF_RESP_FUNC_FAILED:
1470 case TMF_RESP_FUNC_COMPLETE:
1471 break;
1472 }
dd4969a8 1473 }
20b09c29
AY		 1474 mv_printk("%s:rc= %d\n", __func__, rc);
1475 return rc;
8f261aaf
KW		 1476}
1477
20b09c29
AY		 1478/* mandatory SAM-3, still need free task/slot info */
1479int mvs_abort_task(struct sas_task *task)
8f261aaf 1480{
20b09c29
AY		 1481 struct scsi_lun lun;
1482 struct mvs_tmf_task tmf_task;
1483 struct domain_device *dev = task->dev;
9870d9a2 1484 struct mvs_device *mvi_dev = (struct mvs_device *)dev->lldd_dev;
24ae163e 1485 struct mvs_info *mvi;
20b09c29
AY		 1486 int rc = TMF_RESP_FUNC_FAILED;
1487 unsigned long flags;
1488 u32 tag;
9870d9a2 1489
9dc9fd94 1490 if (!mvi_dev) {
84fbd0ce
XY		 1491 mv_printk("Device has removed\n");
1492 return TMF_RESP_FUNC_FAILED;
9dc9fd94
S		 1493 }
1494
24ae163e
JS		 1495 mvi = mvi_dev->mvi_info;
1496
20b09c29
AY		 1497 spin_lock_irqsave(&task->task_state_lock, flags);
1498 if (task->task_state_flags & SAS_TASK_STATE_DONE) {
1499 spin_unlock_irqrestore(&task->task_state_lock, flags);
1500 rc = TMF_RESP_FUNC_COMPLETE;
1501 goto out;
dd4969a8 1502 }
20b09c29 1503 spin_unlock_irqrestore(&task->task_state_lock, flags);
9dc9fd94 1504 mvi_dev->dev_status = MVS_DEV_EH;
20b09c29
AY		 1505 if (task->lldd_task && task->task_proto & SAS_PROTOCOL_SSP) {
1506 struct scsi_cmnd * cmnd = (struct scsi_cmnd *)task->uldd_task;
1507
1508 int_to_scsilun(cmnd->device->lun, &lun);
1509 rc = mvs_find_tag(mvi, task, &tag);
1510 if (rc == 0) {
1511 mv_printk("No such tag in %s\n", __func__);
1512 rc = TMF_RESP_FUNC_FAILED;
1513 return rc;
1514 }
8f261aaf 1515
20b09c29
AY		 1516 tmf_task.tmf = TMF_ABORT_TASK;
1517 tmf_task.tag_of_task_to_be_managed = cpu_to_le16(tag);
8f261aaf 1518
20b09c29 1519 rc = mvs_debug_issue_ssp_tmf(dev, lun.scsi_lun, &tmf_task);
8f261aaf 1520
20b09c29
AY		 1521 /* if successful, clear the task and callback forwards.*/
1522 if (rc == TMF_RESP_FUNC_COMPLETE) {
1523 u32 slot_no;
1524 struct mvs_slot_info *slot;
8f261aaf 1525
20b09c29 1526 if (task->lldd_task) {
f9da3be5 1527 slot = task->lldd_task;
20b09c29 1528 slot_no = (u32) (slot - mvi->slot_info);
9dc9fd94 1529 spin_lock_irqsave(&mvi->lock, flags);
20b09c29 1530 mvs_slot_complete(mvi, slot_no, 1);
9dc9fd94 1531 spin_unlock_irqrestore(&mvi->lock, flags);
20b09c29
AY		 1532 }
1533 }
9dc9fd94 1534
20b09c29
AY		 1535 } else if (task->task_proto & SAS_PROTOCOL_SATA ||
1536 task->task_proto & SAS_PROTOCOL_STP) {
aa9f8328 1537 if (SAS_SATA_DEV == dev->dev_type) {
9dc9fd94 1538 struct mvs_slot_info *slot = task->lldd_task;
9dc9fd94 1539 u32 slot_idx = (u32)(slot - mvi->slot_info);
84fbd0ce 1540 mv_dprintk("mvs_abort_task() mvi=%p task=%p "
9dc9fd94
S		 1541 "slot=%p slot_idx=x%x\n",
1542 mvi, task, slot, slot_idx);
95ab0003 1543 task->task_state_flags |= SAS_TASK_STATE_ABORTED;
9dc9fd94 1544 mvs_slot_task_free(mvi, task, slot, slot_idx);
84fbd0ce
XY		 1545 rc = TMF_RESP_FUNC_COMPLETE;
1546 goto out;
9dc9fd94 1547 }
8f261aaf 1548
20b09c29
AY		 1549 }
1550out:
1551 if (rc != TMF_RESP_FUNC_COMPLETE)
1552 mv_printk("%s:rc= %d\n", __func__, rc);
dd4969a8 1553 return rc;
8f261aaf
KW		 1554}
1555
20b09c29 1556int mvs_abort_task_set(struct domain_device *dev, u8 *lun)
8f261aaf 1557{
20b09c29
AY		 1558 int rc = TMF_RESP_FUNC_FAILED;
1559 struct mvs_tmf_task tmf_task;
8f261aaf 1560
20b09c29
AY		 1561 tmf_task.tmf = TMF_ABORT_TASK_SET;
1562 rc = mvs_debug_issue_ssp_tmf(dev, lun, &tmf_task);
dd4969a8 1563
20b09c29 1564 return rc;
8f261aaf
KW		 1565}
1566
20b09c29 1567int mvs_clear_aca(struct domain_device *dev, u8 *lun)
8f261aaf 1568{
20b09c29
AY		 1569 int rc = TMF_RESP_FUNC_FAILED;
1570 struct mvs_tmf_task tmf_task;
8f261aaf 1571
20b09c29
AY		 1572 tmf_task.tmf = TMF_CLEAR_ACA;
1573 rc = mvs_debug_issue_ssp_tmf(dev, lun, &tmf_task);
8f261aaf 1574
20b09c29
AY		 1575 return rc;
1576}
8f261aaf 1577
20b09c29
AY		 1578int mvs_clear_task_set(struct domain_device *dev, u8 *lun)
1579{
1580 int rc = TMF_RESP_FUNC_FAILED;
1581 struct mvs_tmf_task tmf_task;
8f261aaf 1582
20b09c29
AY		 1583 tmf_task.tmf = TMF_CLEAR_TASK_SET;
1584 rc = mvs_debug_issue_ssp_tmf(dev, lun, &tmf_task);
8f261aaf 1585
20b09c29 1586 return rc;
dd4969a8 1587}
8f261aaf 1588
20b09c29
AY		 1589static int mvs_sata_done(struct mvs_info *mvi, struct sas_task *task,
1590 u32 slot_idx, int err)
dd4969a8 1591{
f9da3be5 1592 struct mvs_device *mvi_dev = task->dev->lldd_dev;
20b09c29
AY		 1593 struct task_status_struct *tstat = &task->task_status;
1594 struct ata_task_resp *resp = (struct ata_task_resp *)tstat->buf;
df64d3ca 1595 int stat = SAM_STAT_GOOD;
e9ff91b6 1596
8f261aaf 1597
20b09c29
AY		 1598 resp->frame_len = sizeof(struct dev_to_host_fis);
1599 memcpy(&resp->ending_fis[0],
1600 SATA_RECEIVED_D2H_FIS(mvi_dev->taskfileset),
1601 sizeof(struct dev_to_host_fis));
1602 tstat->buf_valid_size = sizeof(*resp);
9dc9fd94
S		 1603 if (unlikely(err)) {
1604 if (unlikely(err & CMD_ISS_STPD))
1605 stat = SAS_OPEN_REJECT;
1606 else
1607 stat = SAS_PROTO_RESPONSE;
1608 }
1609
20b09c29 1610 return stat;
8f261aaf
KW		 1611}
1612
a4632aae
XY		 1613void mvs_set_sense(u8 *buffer, int len, int d_sense,
1614 int key, int asc, int ascq)
1615{
1616 memset(buffer, 0, len);
1617
1618 if (d_sense) {
1619 /* Descriptor format */
1620 if (len < 4) {
1621 mv_printk("Length %d of sense buffer too small to "
1622 "fit sense %x:%x:%x", len, key, asc, ascq);
1623 }
1624
1625 buffer[0] = 0x72; /* Response Code */
1626 if (len > 1)
1627 buffer[1] = key; /* Sense Key */
1628 if (len > 2)
1629 buffer[2] = asc; /* ASC */
1630 if (len > 3)
1631 buffer[3] = ascq; /* ASCQ */
1632 } else {
1633 if (len < 14) {
1634 mv_printk("Length %d of sense buffer too small to "
1635 "fit sense %x:%x:%x", len, key, asc, ascq);
1636 }
1637
1638 buffer[0] = 0x70; /* Response Code */
1639 if (len > 2)
1640 buffer[2] = key; /* Sense Key */
1641 if (len > 7)
1642 buffer[7] = 0x0a; /* Additional Sense Length */
1643 if (len > 12)
1644 buffer[12] = asc; /* ASC */
1645 if (len > 13)
1646 buffer[13] = ascq; /* ASCQ */
1647 }
1648
1649 return;
1650}
1651
1652void mvs_fill_ssp_resp_iu(struct ssp_response_iu *iu,
1653 u8 key, u8 asc, u8 asc_q)
1654{
1655 iu->datapres = 2;
1656 iu->response_data_len = 0;
1657 iu->sense_data_len = 17;
1658 iu->status = 02;
1659 mvs_set_sense(iu->sense_data, 17, 0,
1660 key, asc, asc_q);
1661}
1662
20b09c29
AY		 1663static int mvs_slot_err(struct mvs_info *mvi, struct sas_task *task,
1664 u32 slot_idx)
8f261aaf 1665{
20b09c29
AY		 1666 struct mvs_slot_info *slot = &mvi->slot_info[slot_idx];
1667 int stat;
84fbd0ce 1668 u32 err_dw0 = le32_to_cpu(*(u32 *)slot->response);
a4632aae 1669 u32 err_dw1 = le32_to_cpu(*((u32 *)slot->response + 1));
20b09c29
AY		 1670 u32 tfs = 0;
1671 enum mvs_port_type type = PORT_TYPE_SAS;
8f261aaf 1672
20b09c29
AY		 1673 if (err_dw0 & CMD_ISS_STPD)
1674 MVS_CHIP_DISP->issue_stop(mvi, type, tfs);
1675
1676 MVS_CHIP_DISP->command_active(mvi, slot_idx);
b5762948 1677
df64d3ca 1678 stat = SAM_STAT_CHECK_CONDITION;
dd4969a8 1679 switch (task->task_proto) {
dd4969a8 1680 case SAS_PROTOCOL_SSP:
a4632aae 1681 {
20b09c29 1682 stat = SAS_ABORTED_TASK;
a4632aae
XY		 1683 if ((err_dw0 & NO_DEST) || err_dw1 & bit(31)) {
1684 struct ssp_response_iu *iu = slot->response +
1685 sizeof(struct mvs_err_info);
1686 mvs_fill_ssp_resp_iu(iu, NOT_READY, 0x04, 01);
1687 sas_ssp_task_response(mvi->dev, task, iu);
1688 stat = SAM_STAT_CHECK_CONDITION;
1689 }
1690 if (err_dw1 & bit(31))
1691 mv_printk("reuse same slot, retry command.\n");
20b09c29 1692 break;
a4632aae 1693 }
20b09c29 1694 case SAS_PROTOCOL_SMP:
df64d3ca 1695 stat = SAM_STAT_CHECK_CONDITION;
dd4969a8 1696 break;
20b09c29 1697
dd4969a8
JG		 1698 case SAS_PROTOCOL_SATA:
1699 case SAS_PROTOCOL_STP:
20b09c29
AY		 1700 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
1701 {
20b09c29 1702 task->ata_task.use_ncq = 0;
84fbd0ce 1703 stat = SAS_PROTO_RESPONSE;
9dc9fd94 1704 mvs_sata_done(mvi, task, slot_idx, err_dw0);
dd4969a8 1705 }
20b09c29 1706 break;
dd4969a8
JG		 1707 default:
1708 break;
1709 }
1710
20b09c29 1711 return stat;
e9ff91b6
KW		 1712}
1713
20b09c29 1714int mvs_slot_complete(struct mvs_info *mvi, u32 rx_desc, u32 flags)
b5762948 1715{
20b09c29
AY		 1716 u32 slot_idx = rx_desc & RXQ_SLOT_MASK;
1717 struct mvs_slot_info *slot = &mvi->slot_info[slot_idx];
1718 struct sas_task *task = slot->task;
1719 struct mvs_device *mvi_dev = NULL;
1720 struct task_status_struct *tstat;
9dc9fd94
S		 1721 struct domain_device *dev;
1722 u32 aborted;
20b09c29 1723
20b09c29
AY		 1724 void *to;
1725 enum exec_status sts;
1726
9dc9fd94 1727 if (unlikely(!task || !task->lldd_task || !task->dev))
20b09c29
AY		 1728 return -1;
1729
1730 tstat = &task->task_status;
9dc9fd94
S		 1731 dev = task->dev;
1732 mvi_dev = dev->lldd_dev;
b5762948 1733
20b09c29
AY		 1734 spin_lock(&task->task_state_lock);
1735 task->task_state_flags &=
1736 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
1737 task->task_state_flags |= SAS_TASK_STATE_DONE;
1738 /* race condition*/
1739 aborted = task->task_state_flags & SAS_TASK_STATE_ABORTED;
1740 spin_unlock(&task->task_state_lock);
1741
1742 memset(tstat, 0, sizeof(*tstat));
1743 tstat->resp = SAS_TASK_COMPLETE;
1744
1745 if (unlikely(aborted)) {
1746 tstat->stat = SAS_ABORTED_TASK;
9dc9fd94
S		 1747 if (mvi_dev && mvi_dev->running_req)
1748 mvi_dev->running_req--;
20b09c29
AY		 1749 if (sas_protocol_ata(task->task_proto))
1750 mvs_free_reg_set(mvi, mvi_dev);
1751
1752 mvs_slot_task_free(mvi, task, slot, slot_idx);
1753 return -1;
b5762948
JG		 1754 }
1755
e144f7ef 1756 /* when no device attaching, go ahead and complete by error handling*/
9dc9fd94
S		 1757 if (unlikely(!mvi_dev || flags)) {
1758 if (!mvi_dev)
1759 mv_dprintk("port has not device.\n");
20b09c29
AY		 1760 tstat->stat = SAS_PHY_DOWN;
1761 goto out;
1762 }
b5762948 1763
53a983c4
JB		 1764 /*
1765 * error info record present; slot->response is 32 bit aligned but may
1766 * not be 64 bit aligned, so check for zero in two 32 bit reads
1767 */
1768 if (unlikely((rx_desc & RXQ_ERR)
1769 && (*((u32 *)slot->response)
1770 || *(((u32 *)slot->response) + 1)))) {
84fbd0ce
XY		 1771 mv_dprintk("port %d slot %d rx_desc %X has error info"
1772 "%016llX.\n", slot->port->sas_port.id, slot_idx,
53a983c4 1773 rx_desc, get_unaligned_le64(slot->response));
20b09c29 1774 tstat->stat = mvs_slot_err(mvi, task, slot_idx);
9dc9fd94 1775 tstat->resp = SAS_TASK_COMPLETE;
20b09c29 1776 goto out;
b5762948
JG		 1777 }
1778
20b09c29
AY		 1779 switch (task->task_proto) {
1780 case SAS_PROTOCOL_SSP:
1781 /* hw says status == 0, datapres == 0 */
1782 if (rx_desc & RXQ_GOOD) {
df64d3ca 1783 tstat->stat = SAM_STAT_GOOD;
20b09c29
AY		 1784 tstat->resp = SAS_TASK_COMPLETE;
1785 }
1786 /* response frame present */
1787 else if (rx_desc & RXQ_RSP) {
1788 struct ssp_response_iu *iu = slot->response +
1789 sizeof(struct mvs_err_info);
1790 sas_ssp_task_response(mvi->dev, task, iu);
1791 } else
df64d3ca 1792 tstat->stat = SAM_STAT_CHECK_CONDITION;
20b09c29 1793 break;
b5762948 1794
20b09c29
AY		 1795 case SAS_PROTOCOL_SMP: {
1796 struct scatterlist *sg_resp = &task->smp_task.smp_resp;
df64d3ca 1797 tstat->stat = SAM_STAT_GOOD;
77dfce07 1798 to = kmap_atomic(sg_page(sg_resp));
20b09c29
AY		 1799 memcpy(to + sg_resp->offset,
1800 slot->response + sizeof(struct mvs_err_info),
1801 sg_dma_len(sg_resp));
77dfce07 1802 kunmap_atomic(to);
20b09c29
AY		 1803 break;
1804 }
8f261aaf 1805
20b09c29
AY		 1806 case SAS_PROTOCOL_SATA:
1807 case SAS_PROTOCOL_STP:
1808 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: {
1809 tstat->stat = mvs_sata_done(mvi, task, slot_idx, 0);
1810 break;
1811 }
b5762948 1812
20b09c29 1813 default:
df64d3ca 1814 tstat->stat = SAM_STAT_CHECK_CONDITION;
20b09c29
AY		 1815 break;
1816 }
9dc9fd94
S		 1817 if (!slot->port->port_attached) {
1818 mv_dprintk("port %d has removed.\n", slot->port->sas_port.id);
1819 tstat->stat = SAS_PHY_DOWN;
1820 }
1821
b5762948 1822
20b09c29 1823out:
9dc9fd94
S		 1824 if (mvi_dev && mvi_dev->running_req) {
1825 mvi_dev->running_req--;
1826 if (sas_protocol_ata(task->task_proto) && !mvi_dev->running_req)
0f980a87
AY		 1827 mvs_free_reg_set(mvi, mvi_dev);
1828 }
20b09c29
AY		 1829 mvs_slot_task_free(mvi, task, slot, slot_idx);
1830 sts = tstat->stat;
8f261aaf 1831
20b09c29
AY		 1832 spin_unlock(&mvi->lock);
1833 if (task->task_done)
1834 task->task_done(task);
84fbd0ce 1835
20b09c29 1836 spin_lock(&mvi->lock);
b5762948 1837
20b09c29
AY		 1838 return sts;
1839}
b5762948 1840
9dc9fd94 1841void mvs_do_release_task(struct mvs_info *mvi,
20b09c29
AY		 1842 int phy_no, struct domain_device *dev)
1843{
9dc9fd94 1844 u32 slot_idx;
20b09c29
AY		 1845 struct mvs_phy *phy;
1846 struct mvs_port *port;
1847 struct mvs_slot_info *slot, *slot2;
b5762948 1848
20b09c29
AY		 1849 phy = &mvi->phy[phy_no];
1850 port = phy->port;
1851 if (!port)
1852 return;
9dc9fd94
S		 1853 /* clean cmpl queue in case request is already finished */
1854 mvs_int_rx(mvi, false);
1855
1856
b5762948 1857
20b09c29
AY		 1858 list_for_each_entry_safe(slot, slot2, &port->list, entry) {
1859 struct sas_task *task;
1860 slot_idx = (u32) (slot - mvi->slot_info);
1861 task = slot->task;
b5762948 1862
20b09c29
AY		 1863 if (dev && task->dev != dev)
1864 continue;
8f261aaf 1865
20b09c29
AY		 1866 mv_printk("Release slot [%x] tag[%x], task [%p]:\n",
1867 slot_idx, slot->slot_tag, task);
9dc9fd94 1868 MVS_CHIP_DISP->command_active(mvi, slot_idx);
b5762948 1869
20b09c29 1870 mvs_slot_complete(mvi, slot_idx, 1);
b5762948 1871 }
20b09c29 1872}
b5762948 1873
9dc9fd94
S		 1874void mvs_release_task(struct mvs_info *mvi,
1875 struct domain_device *dev)
1876{
1877 int i, phyno[WIDE_PORT_MAX_PHY], num;
9dc9fd94
S		 1878 num = mvs_find_dev_phyno(dev, phyno);
1879 for (i = 0; i < num; i++)
1880 mvs_do_release_task(mvi, phyno[i], dev);
1881}
1882
20b09c29
AY		 1883static void mvs_phy_disconnected(struct mvs_phy *phy)
1884{
1885 phy->phy_attached = 0;
1886 phy->att_dev_info = 0;
1887 phy->att_dev_sas_addr = 0;
1888}
1889
1890static void mvs_work_queue(struct work_struct *work)
1891{
1892 struct delayed_work *dw = container_of(work, struct delayed_work, work);
1893 struct mvs_wq *mwq = container_of(dw, struct mvs_wq, work_q);
1894 struct mvs_info *mvi = mwq->mvi;
1895 unsigned long flags;
a4632aae
XY		 1896 u32 phy_no = (unsigned long) mwq->data;
1897 struct sas_ha_struct *sas_ha = mvi->sas;
1898 struct mvs_phy *phy = &mvi->phy[phy_no];
1899 struct asd_sas_phy *sas_phy = &phy->sas_phy;
b5762948 1900
20b09c29
AY		 1901 spin_lock_irqsave(&mvi->lock, flags);
1902 if (mwq->handler & PHY_PLUG_EVENT) {
20b09c29
AY		 1903
1904 if (phy->phy_event & PHY_PLUG_OUT) {
1905 u32 tmp;
1906 struct sas_identify_frame *id;
1907 id = (struct sas_identify_frame *)phy->frame_rcvd;
1908 tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, phy_no);
1909 phy->phy_event &= ~PHY_PLUG_OUT;
1910 if (!(tmp & PHY_READY_MASK)) {
1911 sas_phy_disconnected(sas_phy);
1912 mvs_phy_disconnected(phy);
1913 sas_ha->notify_phy_event(sas_phy,
1914 PHYE_LOSS_OF_SIGNAL);
1915 mv_dprintk("phy%d Removed Device\n", phy_no);
1916 } else {
1917 MVS_CHIP_DISP->detect_porttype(mvi, phy_no);
1918 mvs_update_phyinfo(mvi, phy_no, 1);
1919 mvs_bytes_dmaed(mvi, phy_no);
1920 mvs_port_notify_formed(sas_phy, 0);
1921 mv_dprintk("phy%d Attached Device\n", phy_no);
1922 }
1923 }
a4632aae
XY		 1924 } else if (mwq->handler & EXP_BRCT_CHG) {
1925 phy->phy_event &= ~EXP_BRCT_CHG;
1926 sas_ha->notify_port_event(sas_phy,
1927 PORTE_BROADCAST_RCVD);
1928 mv_dprintk("phy%d Got Broadcast Change\n", phy_no);
20b09c29
AY		 1929 }
1930 list_del(&mwq->entry);
1931 spin_unlock_irqrestore(&mvi->lock, flags);
1932 kfree(mwq);
1933}
8f261aaf 1934
20b09c29
AY		 1935static int mvs_handle_event(struct mvs_info *mvi, void *data, int handler)
1936{
1937 struct mvs_wq *mwq;
1938 int ret = 0;
1939
1940 mwq = kmalloc(sizeof(struct mvs_wq), GFP_ATOMIC);
1941 if (mwq) {
1942 mwq->mvi = mvi;
1943 mwq->data = data;
1944 mwq->handler = handler;
1945 MV_INIT_DELAYED_WORK(&mwq->work_q, mvs_work_queue, mwq);
1946 list_add_tail(&mwq->entry, &mvi->wq_list);
1947 schedule_delayed_work(&mwq->work_q, HZ * 2);
1948 } else
1949 ret = -ENOMEM;
1950
1951 return ret;
1952}
b5762948 1953
20b09c29
AY		 1954static void mvs_sig_time_out(unsigned long tphy)
1955{
1956 struct mvs_phy *phy = (struct mvs_phy *)tphy;
1957 struct mvs_info *mvi = phy->mvi;
1958 u8 phy_no;
1959
1960 for (phy_no = 0; phy_no < mvi->chip->n_phy; phy_no++) {
1961 if (&mvi->phy[phy_no] == phy) {
1962 mv_dprintk("Get signature time out, reset phy %d\n",
1963 phy_no+mvi->id*mvi->chip->n_phy);
a4632aae 1964 MVS_CHIP_DISP->phy_reset(mvi, phy_no, MVS_HARD_RESET);
20b09c29 1965 }
b5762948 1966 }
20b09c29 1967}
b5762948 1968
20b09c29
AY		 1969void mvs_int_port(struct mvs_info *mvi, int phy_no, u32 events)
1970{
1971 u32 tmp;
20b09c29 1972 struct mvs_phy *phy = &mvi->phy[phy_no];
8f261aaf 1973
20b09c29 1974 phy->irq_status = MVS_CHIP_DISP->read_port_irq_stat(mvi, phy_no);
84fbd0ce
XY		 1975 MVS_CHIP_DISP->write_port_irq_stat(mvi, phy_no, phy->irq_status);
1976 mv_dprintk("phy %d ctrl sts=0x%08X.\n", phy_no+mvi->id*mvi->chip->n_phy,
20b09c29 1977 MVS_CHIP_DISP->read_phy_ctl(mvi, phy_no));
84fbd0ce 1978 mv_dprintk("phy %d irq sts = 0x%08X\n", phy_no+mvi->id*mvi->chip->n_phy,
20b09c29 1979 phy->irq_status);
8f261aaf 1980
20b09c29
AY		 1981 /*
1982 * events is port event now ,
1983 * we need check the interrupt status which belongs to per port.
1984 */
b5762948 1985
9dc9fd94 1986 if (phy->irq_status & PHYEV_DCDR_ERR) {
84fbd0ce 1987 mv_dprintk("phy %d STP decoding error.\n",
9dc9fd94
S		 1988 phy_no + mvi->id*mvi->chip->n_phy);
1989 }
20b09c29
AY		 1990
1991 if (phy->irq_status & PHYEV_POOF) {
84fbd0ce 1992 mdelay(500);
20b09c29
AY		 1993 if (!(phy->phy_event & PHY_PLUG_OUT)) {
1994 int dev_sata = phy->phy_type & PORT_TYPE_SATA;
1995 int ready;
9dc9fd94 1996 mvs_do_release_task(mvi, phy_no, NULL);
20b09c29 1997 phy->phy_event |= PHY_PLUG_OUT;
9dc9fd94 1998 MVS_CHIP_DISP->clear_srs_irq(mvi, 0, 1);
20b09c29
AY		 1999 mvs_handle_event(mvi,
2000 (void *)(unsigned long)phy_no,
2001 PHY_PLUG_EVENT);
2002 ready = mvs_is_phy_ready(mvi, phy_no);
20b09c29
AY		 2003 if (ready || dev_sata) {
2004 if (MVS_CHIP_DISP->stp_reset)
2005 MVS_CHIP_DISP->stp_reset(mvi,
2006 phy_no);
2007 else
2008 MVS_CHIP_DISP->phy_reset(mvi,
a4632aae 2009 phy_no, MVS_SOFT_RESET);
20b09c29
AY		 2010 return;
2011 }
2012 }
2013 }
b5762948 2014
20b09c29
AY		 2015 if (phy->irq_status & PHYEV_COMWAKE) {
2016 tmp = MVS_CHIP_DISP->read_port_irq_mask(mvi, phy_no);
2017 MVS_CHIP_DISP->write_port_irq_mask(mvi, phy_no,
2018 tmp | PHYEV_SIG_FIS);
2019 if (phy->timer.function == NULL) {
2020 phy->timer.data = (unsigned long)phy;
2021 phy->timer.function = mvs_sig_time_out;
84fbd0ce 2022 phy->timer.expires = jiffies + 5*HZ;
20b09c29
AY		 2023 add_timer(&phy->timer);
2024 }
2025 }
2026 if (phy->irq_status & (PHYEV_SIG_FIS | PHYEV_ID_DONE)) {
2027 phy->phy_status = mvs_is_phy_ready(mvi, phy_no);
20b09c29
AY		 2028 mv_dprintk("notify plug in on phy[%d]\n", phy_no);
2029 if (phy->phy_status) {
2030 mdelay(10);
2031 MVS_CHIP_DISP->detect_porttype(mvi, phy_no);
2032 if (phy->phy_type & PORT_TYPE_SATA) {
2033 tmp = MVS_CHIP_DISP->read_port_irq_mask(
2034 mvi, phy_no);
2035 tmp &= ~PHYEV_SIG_FIS;
2036 MVS_CHIP_DISP->write_port_irq_mask(mvi,
2037 phy_no, tmp);
2038 }
2039 mvs_update_phyinfo(mvi, phy_no, 0);
9dc9fd94 2040 if (phy->phy_type & PORT_TYPE_SAS) {
a4632aae 2041 MVS_CHIP_DISP->phy_reset(mvi, phy_no, MVS_PHY_TUNE);
9dc9fd94
S		 2042 mdelay(10);
2043 }
2044
20b09c29
AY		 2045 mvs_bytes_dmaed(mvi, phy_no);
2046 /* whether driver is going to handle hot plug */
2047 if (phy->phy_event & PHY_PLUG_OUT) {
a4632aae 2048 mvs_port_notify_formed(&phy->sas_phy, 0);
20b09c29
AY		 2049 phy->phy_event &= ~PHY_PLUG_OUT;
2050 }
2051 } else {
2052 mv_dprintk("plugin interrupt but phy%d is gone\n",
2053 phy_no + mvi->id*mvi->chip->n_phy);
2054 }
2055 } else if (phy->irq_status & PHYEV_BROAD_CH) {
84fbd0ce 2056 mv_dprintk("phy %d broadcast change.\n",
20b09c29 2057 phy_no + mvi->id*mvi->chip->n_phy);
a4632aae
XY		 2058 mvs_handle_event(mvi, (void *)(unsigned long)phy_no,
2059 EXP_BRCT_CHG);
20b09c29 2060 }
b5762948
JG		 2061}
2062
20b09c29 2063int mvs_int_rx(struct mvs_info *mvi, bool self_clear)
b5762948 2064{
20b09c29
AY		 2065 u32 rx_prod_idx, rx_desc;
2066 bool attn = false;
b5762948 2067
20b09c29
AY		 2068 /* the first dword in the RX ring is special: it contains
2069 * a mirror of the hardware's RX producer index, so that
2070 * we don't have to stall the CPU reading that register.
2071 * The actual RX ring is offset by one dword, due to this.
2072 */
2073 rx_prod_idx = mvi->rx_cons;
2074 mvi->rx_cons = le32_to_cpu(mvi->rx[0]);
2075 if (mvi->rx_cons == 0xfff) /* h/w hasn't touched RX ring yet */
2076 return 0;
b5762948 2077
20b09c29
AY		 2078 /* The CMPL_Q may come late, read from register and try again
2079 * note: if coalescing is enabled,
2080 * it will need to read from register every time for sure
2081 */
2082 if (unlikely(mvi->rx_cons == rx_prod_idx))
2083 mvi->rx_cons = MVS_CHIP_DISP->rx_update(mvi) & RX_RING_SZ_MASK;
2084
2085 if (mvi->rx_cons == rx_prod_idx)
2086 return 0;
2087
2088 while (mvi->rx_cons != rx_prod_idx) {
2089 /* increment our internal RX consumer pointer */
2090 rx_prod_idx = (rx_prod_idx + 1) & (MVS_RX_RING_SZ - 1);
2091 rx_desc = le32_to_cpu(mvi->rx[rx_prod_idx + 1]);
2092
2093 if (likely(rx_desc & RXQ_DONE))
2094 mvs_slot_complete(mvi, rx_desc, 0);
2095 if (rx_desc & RXQ_ATTN) {
2096 attn = true;
2097 } else if (rx_desc & RXQ_ERR) {
2098 if (!(rx_desc & RXQ_DONE))
2099 mvs_slot_complete(mvi, rx_desc, 0);
2100 } else if (rx_desc & RXQ_SLOT_RESET) {
2101 mvs_slot_free(mvi, rx_desc);
2102 }
2103 }
2104
2105 if (attn && self_clear)
2106 MVS_CHIP_DISP->int_full(mvi);
2107 return 0;
b5762948
JG		 2108}
2109
c56f5f1d
WW		 2110int mvs_gpio_write(struct sas_ha_struct *sha, u8 reg_type, u8 reg_index,
2111 u8 reg_count, u8 *write_data)
2112{
2113 struct mvs_prv_info *mvs_prv = sha->lldd_ha;
2114 struct mvs_info *mvi = mvs_prv->mvi[0];
2115
2116 if (MVS_CHIP_DISP->gpio_write) {
2117 return MVS_CHIP_DISP->gpio_write(mvs_prv, reg_type,
2118 reg_index, reg_count, write_data);
2119 }
2120
2121 return -ENOSYS;
2122}
Linux kernel - Deliverables
This page took 0.740438 seconds and 5 git commands to generate.