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dd4969a8 | 1 | /* |
20b09c29 AY |
2 | * Marvell 88SE64xx/88SE94xx main function head file |
3 | * | |
4 | * Copyright 2007 Red Hat, Inc. | |
5 | * Copyright 2008 Marvell. <kewei@marvell.com> | |
6 | * | |
7 | * This file is licensed under GPLv2. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; version 2 of the | |
12 | * License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
17 | * General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 | |
22 | * USA | |
23 | */ | |
dd4969a8 JG |
24 | |
25 | #ifndef _MV_SAS_H_ | |
26 | #define _MV_SAS_H_ | |
27 | ||
28 | #include <linux/kernel.h> | |
29 | #include <linux/module.h> | |
30 | #include <linux/spinlock.h> | |
31 | #include <linux/delay.h> | |
32 | #include <linux/types.h> | |
33 | #include <linux/ctype.h> | |
34 | #include <linux/dma-mapping.h> | |
35 | #include <linux/pci.h> | |
36 | #include <linux/platform_device.h> | |
37 | #include <linux/interrupt.h> | |
38 | #include <linux/irq.h> | |
5a0e3ad6 | 39 | #include <linux/slab.h> |
dd4969a8 JG |
40 | #include <linux/vmalloc.h> |
41 | #include <scsi/libsas.h> | |
42 | #include <scsi/scsi_tcq.h> | |
43 | #include <scsi/sas_ata.h> | |
44 | #include <linux/version.h> | |
45 | #include "mv_defs.h" | |
46 | ||
20b09c29 AY |
47 | #define DRV_NAME "mvsas" |
48 | #define DRV_VERSION "0.8.2" | |
49 | #define _MV_DUMP 0 | |
dd4969a8 | 50 | #define MVS_ID_NOT_MAPPED 0x7f |
20b09c29 AY |
51 | /* #define DISABLE_HOTPLUG_DMA_FIX */ |
52 | #define MAX_EXP_RUNNING_REQ 2 | |
53 | #define WIDE_PORT_MAX_PHY 4 | |
54 | #define MV_DISABLE_NCQ 0 | |
55 | #define mv_printk(fmt, arg ...) \ | |
56 | printk(KERN_DEBUG"%s %d:" fmt, __FILE__, __LINE__, ## arg) | |
57 | #ifdef MV_DEBUG | |
58 | #define mv_dprintk(format, arg...) \ | |
59 | printk(KERN_DEBUG"%s %d:" format, __FILE__, __LINE__, ## arg) | |
60 | #else | |
61 | #define mv_dprintk(format, arg...) | |
62 | #endif | |
63 | #define MV_MAX_U32 0xffffffff | |
64 | ||
65 | extern struct mvs_tgt_initiator mvs_tgt; | |
66 | extern struct mvs_info *tgt_mvi; | |
67 | extern const struct mvs_dispatch mvs_64xx_dispatch; | |
68 | extern const struct mvs_dispatch mvs_94xx_dispatch; | |
69 | ||
70 | #define DEV_IS_EXPANDER(type) \ | |
71 | ((type == EDGE_DEV) || (type == FANOUT_DEV)) | |
dd4969a8 | 72 | |
20b09c29 AY |
73 | #define bit(n) ((u32)1 << n) |
74 | ||
75 | #define for_each_phy(__lseq_mask, __mc, __lseq) \ | |
76 | for ((__mc) = (__lseq_mask), (__lseq) = 0; \ | |
77 | (__mc) != 0 ; \ | |
dd4969a8 JG |
78 | (++__lseq), (__mc) >>= 1) |
79 | ||
20b09c29 AY |
80 | #define MV_INIT_DELAYED_WORK(w, f, d) INIT_DELAYED_WORK(w, f) |
81 | #define UNASSOC_D2H_FIS(id) \ | |
82 | ((void *) mvi->rx_fis + 0x100 * id) | |
83 | #define SATA_RECEIVED_FIS_LIST(reg_set) \ | |
84 | ((void *) mvi->rx_fis + mvi->chip->fis_offs + 0x100 * reg_set) | |
85 | #define SATA_RECEIVED_SDB_FIS(reg_set) \ | |
86 | (SATA_RECEIVED_FIS_LIST(reg_set) + 0x58) | |
87 | #define SATA_RECEIVED_D2H_FIS(reg_set) \ | |
88 | (SATA_RECEIVED_FIS_LIST(reg_set) + 0x40) | |
89 | #define SATA_RECEIVED_PIO_FIS(reg_set) \ | |
90 | (SATA_RECEIVED_FIS_LIST(reg_set) + 0x20) | |
91 | #define SATA_RECEIVED_DMA_FIS(reg_set) \ | |
92 | (SATA_RECEIVED_FIS_LIST(reg_set) + 0x00) | |
93 | ||
94 | enum dev_status { | |
95 | MVS_DEV_NORMAL = 0x0, | |
96 | MVS_DEV_EH = 0x1, | |
97 | }; | |
98 | ||
99 | ||
100 | struct mvs_info; | |
101 | ||
102 | struct mvs_dispatch { | |
103 | char *name; | |
104 | int (*chip_init)(struct mvs_info *mvi); | |
105 | int (*spi_init)(struct mvs_info *mvi); | |
106 | int (*chip_ioremap)(struct mvs_info *mvi); | |
107 | void (*chip_iounmap)(struct mvs_info *mvi); | |
108 | irqreturn_t (*isr)(struct mvs_info *mvi, int irq, u32 stat); | |
109 | u32 (*isr_status)(struct mvs_info *mvi, int irq); | |
110 | void (*interrupt_enable)(struct mvs_info *mvi); | |
111 | void (*interrupt_disable)(struct mvs_info *mvi); | |
112 | ||
113 | u32 (*read_phy_ctl)(struct mvs_info *mvi, u32 port); | |
114 | void (*write_phy_ctl)(struct mvs_info *mvi, u32 port, u32 val); | |
115 | ||
116 | u32 (*read_port_cfg_data)(struct mvs_info *mvi, u32 port); | |
117 | void (*write_port_cfg_data)(struct mvs_info *mvi, u32 port, u32 val); | |
118 | void (*write_port_cfg_addr)(struct mvs_info *mvi, u32 port, u32 addr); | |
119 | ||
120 | u32 (*read_port_vsr_data)(struct mvs_info *mvi, u32 port); | |
121 | void (*write_port_vsr_data)(struct mvs_info *mvi, u32 port, u32 val); | |
122 | void (*write_port_vsr_addr)(struct mvs_info *mvi, u32 port, u32 addr); | |
123 | ||
124 | u32 (*read_port_irq_stat)(struct mvs_info *mvi, u32 port); | |
125 | void (*write_port_irq_stat)(struct mvs_info *mvi, u32 port, u32 val); | |
126 | ||
127 | u32 (*read_port_irq_mask)(struct mvs_info *mvi, u32 port); | |
128 | void (*write_port_irq_mask)(struct mvs_info *mvi, u32 port, u32 val); | |
129 | ||
130 | void (*get_sas_addr)(void *buf, u32 buflen); | |
131 | void (*command_active)(struct mvs_info *mvi, u32 slot_idx); | |
132 | void (*issue_stop)(struct mvs_info *mvi, enum mvs_port_type type, | |
133 | u32 tfs); | |
134 | void (*start_delivery)(struct mvs_info *mvi, u32 tx); | |
135 | u32 (*rx_update)(struct mvs_info *mvi); | |
136 | void (*int_full)(struct mvs_info *mvi); | |
137 | u8 (*assign_reg_set)(struct mvs_info *mvi, u8 *tfs); | |
138 | void (*free_reg_set)(struct mvs_info *mvi, u8 *tfs); | |
139 | u32 (*prd_size)(void); | |
140 | u32 (*prd_count)(void); | |
141 | void (*make_prd)(struct scatterlist *scatter, int nr, void *prd); | |
142 | void (*detect_porttype)(struct mvs_info *mvi, int i); | |
143 | int (*oob_done)(struct mvs_info *mvi, int i); | |
144 | void (*fix_phy_info)(struct mvs_info *mvi, int i, | |
145 | struct sas_identify_frame *id); | |
146 | void (*phy_work_around)(struct mvs_info *mvi, int i); | |
147 | void (*phy_set_link_rate)(struct mvs_info *mvi, u32 phy_id, | |
148 | struct sas_phy_linkrates *rates); | |
149 | u32 (*phy_max_link_rate)(void); | |
150 | void (*phy_disable)(struct mvs_info *mvi, u32 phy_id); | |
151 | void (*phy_enable)(struct mvs_info *mvi, u32 phy_id); | |
152 | void (*phy_reset)(struct mvs_info *mvi, u32 phy_id, int hard); | |
153 | void (*stp_reset)(struct mvs_info *mvi, u32 phy_id); | |
154 | void (*clear_active_cmds)(struct mvs_info *mvi); | |
155 | u32 (*spi_read_data)(struct mvs_info *mvi); | |
156 | void (*spi_write_data)(struct mvs_info *mvi, u32 data); | |
157 | int (*spi_buildcmd)(struct mvs_info *mvi, | |
158 | u32 *dwCmd, | |
159 | u8 cmd, | |
160 | u8 read, | |
161 | u8 length, | |
162 | u32 addr | |
163 | ); | |
164 | int (*spi_issuecmd)(struct mvs_info *mvi, u32 cmd); | |
165 | int (*spi_waitdataready)(struct mvs_info *mvi, u32 timeout); | |
166 | #ifndef DISABLE_HOTPLUG_DMA_FIX | |
167 | void (*dma_fix)(dma_addr_t buf_dma, int buf_len, int from, void *prd); | |
168 | #endif | |
169 | ||
170 | }; | |
171 | ||
dd4969a8 | 172 | struct mvs_chip_info { |
20b09c29 AY |
173 | u32 n_host; |
174 | u32 n_phy; | |
175 | u32 fis_offs; | |
176 | u32 fis_count; | |
177 | u32 srs_sz; | |
178 | u32 slot_width; | |
179 | const struct mvs_dispatch *dispatch; | |
dd4969a8 | 180 | }; |
20b09c29 AY |
181 | #define MVS_CHIP_SLOT_SZ (1U << mvi->chip->slot_width) |
182 | #define MVS_RX_FISL_SZ \ | |
183 | (mvi->chip->fis_offs + (mvi->chip->fis_count * 0x100)) | |
184 | #define MVS_CHIP_DISP (mvi->chip->dispatch) | |
dd4969a8 JG |
185 | |
186 | struct mvs_err_info { | |
187 | __le32 flags; | |
188 | __le32 flags2; | |
189 | }; | |
190 | ||
191 | struct mvs_cmd_hdr { | |
192 | __le32 flags; /* PRD tbl len; SAS, SATA ctl */ | |
193 | __le32 lens; /* cmd, max resp frame len */ | |
194 | __le32 tags; /* targ port xfer tag; tag */ | |
195 | __le32 data_len; /* data xfer len */ | |
20b09c29 | 196 | __le64 cmd_tbl; /* command table address */ |
dd4969a8 JG |
197 | __le64 open_frame; /* open addr frame address */ |
198 | __le64 status_buf; /* status buffer address */ | |
199 | __le64 prd_tbl; /* PRD tbl address */ | |
200 | __le32 reserved[4]; | |
201 | }; | |
202 | ||
203 | struct mvs_port { | |
204 | struct asd_sas_port sas_port; | |
205 | u8 port_attached; | |
dd4969a8 JG |
206 | u8 wide_port_phymap; |
207 | struct list_head list; | |
208 | }; | |
209 | ||
210 | struct mvs_phy { | |
20b09c29 | 211 | struct mvs_info *mvi; |
dd4969a8 JG |
212 | struct mvs_port *port; |
213 | struct asd_sas_phy sas_phy; | |
214 | struct sas_identify identify; | |
215 | struct scsi_device *sdev; | |
20b09c29 | 216 | struct timer_list timer; |
dd4969a8 JG |
217 | u64 dev_sas_addr; |
218 | u64 att_dev_sas_addr; | |
219 | u32 att_dev_info; | |
220 | u32 dev_info; | |
221 | u32 phy_type; | |
222 | u32 phy_status; | |
223 | u32 irq_status; | |
224 | u32 frame_rcvd_size; | |
225 | u8 frame_rcvd[32]; | |
226 | u8 phy_attached; | |
20b09c29 AY |
227 | u8 phy_mode; |
228 | u8 reserved[2]; | |
229 | u32 phy_event; | |
dd4969a8 JG |
230 | enum sas_linkrate minimum_linkrate; |
231 | enum sas_linkrate maximum_linkrate; | |
232 | }; | |
233 | ||
20b09c29 | 234 | struct mvs_device { |
9870d9a2 | 235 | struct list_head dev_entry; |
20b09c29 | 236 | enum sas_dev_type dev_type; |
9870d9a2 | 237 | struct mvs_info *mvi_info; |
20b09c29 AY |
238 | struct domain_device *sas_device; |
239 | u32 attached_phy; | |
240 | u32 device_id; | |
241 | u32 runing_req; | |
242 | u8 taskfileset; | |
243 | u8 dev_status; | |
244 | u16 reserved; | |
20b09c29 AY |
245 | }; |
246 | ||
dd4969a8 | 247 | struct mvs_slot_info { |
20b09c29 AY |
248 | struct list_head entry; |
249 | union { | |
250 | struct sas_task *task; | |
251 | void *tdata; | |
252 | }; | |
dd4969a8 JG |
253 | u32 n_elem; |
254 | u32 tx; | |
20b09c29 | 255 | u32 slot_tag; |
dd4969a8 JG |
256 | |
257 | /* DMA buffer for storing cmd tbl, open addr frame, status buffer, | |
258 | * and PRD table | |
259 | */ | |
260 | void *buf; | |
261 | dma_addr_t buf_dma; | |
262 | #if _MV_DUMP | |
263 | u32 cmd_size; | |
264 | #endif | |
dd4969a8 JG |
265 | void *response; |
266 | struct mvs_port *port; | |
20b09c29 AY |
267 | struct mvs_device *device; |
268 | void *open_frame; | |
dd4969a8 JG |
269 | }; |
270 | ||
271 | struct mvs_info { | |
272 | unsigned long flags; | |
273 | ||
274 | /* host-wide lock */ | |
275 | spinlock_t lock; | |
276 | ||
277 | /* our device */ | |
278 | struct pci_dev *pdev; | |
20b09c29 | 279 | struct device *dev; |
dd4969a8 JG |
280 | |
281 | /* enhanced mode registers */ | |
282 | void __iomem *regs; | |
283 | ||
20b09c29 AY |
284 | /* peripheral or soc registers */ |
285 | void __iomem *regs_ex; | |
dd4969a8 JG |
286 | u8 sas_addr[SAS_ADDR_SIZE]; |
287 | ||
288 | /* SCSI/SAS glue */ | |
20b09c29 | 289 | struct sas_ha_struct *sas; |
dd4969a8 JG |
290 | struct Scsi_Host *shost; |
291 | ||
292 | /* TX (delivery) DMA ring */ | |
293 | __le32 *tx; | |
294 | dma_addr_t tx_dma; | |
295 | ||
296 | /* cached next-producer idx */ | |
297 | u32 tx_prod; | |
298 | ||
299 | /* RX (completion) DMA ring */ | |
20b09c29 | 300 | __le32 *rx; |
dd4969a8 JG |
301 | dma_addr_t rx_dma; |
302 | ||
303 | /* RX consumer idx */ | |
304 | u32 rx_cons; | |
305 | ||
306 | /* RX'd FIS area */ | |
307 | __le32 *rx_fis; | |
308 | dma_addr_t rx_fis_dma; | |
309 | ||
310 | /* DMA command header slots */ | |
311 | struct mvs_cmd_hdr *slot; | |
312 | dma_addr_t slot_dma; | |
313 | ||
20b09c29 | 314 | u32 chip_id; |
dd4969a8 JG |
315 | const struct mvs_chip_info *chip; |
316 | ||
20b09c29 | 317 | int tags_num; |
77db27cd | 318 | DECLARE_BITMAP(tags, MVS_SLOTS); |
20b09c29 | 319 | /* further per-slot information */ |
dd4969a8 JG |
320 | struct mvs_phy phy[MVS_MAX_PHYS]; |
321 | struct mvs_port port[MVS_MAX_PHYS]; | |
20b09c29 AY |
322 | u32 irq; |
323 | u32 exp_req; | |
324 | u32 id; | |
325 | u64 sata_reg_set; | |
326 | struct list_head *hba_list; | |
327 | struct list_head soc_entry; | |
328 | struct list_head wq_list; | |
329 | unsigned long instance; | |
330 | u16 flashid; | |
331 | u32 flashsize; | |
332 | u32 flashsectSize; | |
333 | ||
334 | void *addon; | |
335 | struct mvs_device devices[MVS_MAX_DEVICES]; | |
336 | #ifndef DISABLE_HOTPLUG_DMA_FIX | |
337 | void *bulk_buffer; | |
338 | dma_addr_t bulk_buffer_dma; | |
339 | #define TRASH_BUCKET_SIZE 0x20000 | |
dd4969a8 | 340 | #endif |
20b09c29 AY |
341 | struct mvs_slot_info slot_info[0]; |
342 | }; | |
343 | ||
344 | struct mvs_prv_info{ | |
345 | u8 n_host; | |
346 | u8 n_phy; | |
347 | u16 reserve; | |
348 | struct mvs_info *mvi[2]; | |
349 | }; | |
350 | ||
351 | struct mvs_wq { | |
352 | struct delayed_work work_q; | |
353 | struct mvs_info *mvi; | |
354 | void *data; | |
355 | int handler; | |
356 | struct list_head entry; | |
dd4969a8 JG |
357 | }; |
358 | ||
20b09c29 AY |
359 | struct mvs_task_exec_info { |
360 | struct sas_task *task; | |
361 | struct mvs_cmd_hdr *hdr; | |
362 | struct mvs_port *port; | |
363 | u32 tag; | |
364 | int n_elem; | |
365 | }; | |
366 | ||
367 | ||
368 | /******************** function prototype *********************/ | |
369 | void mvs_get_sas_addr(void *buf, u32 buflen); | |
370 | void mvs_tag_clear(struct mvs_info *mvi, u32 tag); | |
371 | void mvs_tag_free(struct mvs_info *mvi, u32 tag); | |
372 | void mvs_tag_set(struct mvs_info *mvi, unsigned int tag); | |
373 | int mvs_tag_alloc(struct mvs_info *mvi, u32 *tag_out); | |
374 | void mvs_tag_init(struct mvs_info *mvi); | |
375 | void mvs_iounmap(void __iomem *regs); | |
376 | int mvs_ioremap(struct mvs_info *mvi, int bar, int bar_ex); | |
377 | void mvs_phys_reset(struct mvs_info *mvi, u32 phy_mask, int hard); | |
dd4969a8 JG |
378 | int mvs_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func, |
379 | void *funcdata); | |
20b09c29 AY |
380 | void __devinit mvs_set_sas_addr(struct mvs_info *mvi, int port_id, |
381 | u32 off_lo, u32 off_hi, u64 sas_addr); | |
382 | int mvs_slave_alloc(struct scsi_device *scsi_dev); | |
dd4969a8 JG |
383 | int mvs_slave_configure(struct scsi_device *sdev); |
384 | void mvs_scan_start(struct Scsi_Host *shost); | |
385 | int mvs_scan_finished(struct Scsi_Host *shost, unsigned long time); | |
20b09c29 AY |
386 | int mvs_queue_command(struct sas_task *task, const int num, |
387 | gfp_t gfp_flags); | |
388 | int mvs_abort_task(struct sas_task *task); | |
389 | int mvs_abort_task_set(struct domain_device *dev, u8 *lun); | |
390 | int mvs_clear_aca(struct domain_device *dev, u8 *lun); | |
391 | int mvs_clear_task_set(struct domain_device *dev, u8 * lun); | |
dd4969a8 | 392 | void mvs_port_formed(struct asd_sas_phy *sas_phy); |
20b09c29 AY |
393 | void mvs_port_deformed(struct asd_sas_phy *sas_phy); |
394 | int mvs_dev_found(struct domain_device *dev); | |
395 | void mvs_dev_gone(struct domain_device *dev); | |
396 | int mvs_lu_reset(struct domain_device *dev, u8 *lun); | |
397 | int mvs_slot_complete(struct mvs_info *mvi, u32 rx_desc, u32 flags); | |
dd4969a8 | 398 | int mvs_I_T_nexus_reset(struct domain_device *dev); |
20b09c29 AY |
399 | int mvs_query_task(struct sas_task *task); |
400 | void mvs_release_task(struct mvs_info *mvi, int phy_no, | |
401 | struct domain_device *dev); | |
402 | void mvs_int_port(struct mvs_info *mvi, int phy_no, u32 events); | |
403 | void mvs_update_phyinfo(struct mvs_info *mvi, int i, int get_st); | |
404 | int mvs_int_rx(struct mvs_info *mvi, bool self_clear); | |
405 | void mvs_hexdump(u32 size, u8 *data, u32 baseaddr); | |
dd4969a8 | 406 | #endif |
20b09c29 | 407 |