[deliverable/linux.git] / drivers / scsi / mvsas / mv_sas.h

/*
 * Marvell 88SE64xx/88SE94xx main function head file
 *
 * Copyright 2007 Red Hat, Inc.
 * Copyright 2008 Marvell. <kewei@marvell.com>
 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
 *
 * This file is licensed under GPLv2.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; version 2 of the
 * License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
 * USA
*/

#ifndef _MV_SAS_H_
#define _MV_SAS_H_

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/spinlock.h>
#include <linux/delay.h>
#include <linux/types.h>
#include <linux/ctype.h>
#include <linux/dma-mapping.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/slab.h>
#include <linux/vmalloc.h>
#include <scsi/libsas.h>
#include <scsi/scsi.h>
#include <scsi/scsi_tcq.h>
#include <scsi/sas_ata.h>
#include <linux/version.h>
#include "mv_defs.h"

#define DRV_NAME		"mvsas"
#define DRV_VERSION		"0.8.2"
#define MVS_ID_NOT_MAPPED	0x7f
#define WIDE_PORT_MAX_PHY		4
#define mv_printk(fmt, arg ...)	\
	printk(KERN_DEBUG"%s %d:" fmt, __FILE__, __LINE__, ## arg)
#ifdef MV_DEBUG
#define mv_dprintk(format, arg...)	\
	printk(KERN_DEBUG"%s %d:" format, __FILE__, __LINE__, ## arg)
#else
#define mv_dprintk(format, arg...)
#endif
#define MV_MAX_U32			0xffffffff

extern int interrupt_coalescing;
extern struct mvs_tgt_initiator mvs_tgt;
extern struct mvs_info *tgt_mvi;
extern const struct mvs_dispatch mvs_64xx_dispatch;
extern const struct mvs_dispatch mvs_94xx_dispatch;
extern struct kmem_cache *mvs_task_list_cache;

#define DEV_IS_EXPANDER(type)	\
	((type == EDGE_DEV) || (type == FANOUT_DEV))

#define bit(n) ((u32)1 << n)

#define for_each_phy(__lseq_mask, __mc, __lseq)			\
	for ((__mc) = (__lseq_mask), (__lseq) = 0;		\
					(__mc) != 0 ;		\
					(++__lseq), (__mc) >>= 1)

#define MV_INIT_DELAYED_WORK(w, f, d)	INIT_DELAYED_WORK(w, f)
#define UNASSOC_D2H_FIS(id)		\
	((void *) mvi->rx_fis + 0x100 * id)
#define SATA_RECEIVED_FIS_LIST(reg_set)	\
	((void *) mvi->rx_fis + mvi->chip->fis_offs + 0x100 * reg_set)
#define SATA_RECEIVED_SDB_FIS(reg_set)	\
	(SATA_RECEIVED_FIS_LIST(reg_set) + 0x58)
#define SATA_RECEIVED_D2H_FIS(reg_set)	\
	(SATA_RECEIVED_FIS_LIST(reg_set) + 0x40)
#define SATA_RECEIVED_PIO_FIS(reg_set)	\
	(SATA_RECEIVED_FIS_LIST(reg_set) + 0x20)
#define SATA_RECEIVED_DMA_FIS(reg_set)	\
	(SATA_RECEIVED_FIS_LIST(reg_set) + 0x00)

enum dev_status {
	MVS_DEV_NORMAL = 0x0,
	MVS_DEV_EH	= 0x1,
};

enum dev_reset {
	MVS_SOFT_RESET	= 0,
	MVS_HARD_RESET	= 1,
	MVS_PHY_TUNE	= 2,
};

struct mvs_info;

struct mvs_dispatch {
	char *name;
	int (*chip_init)(struct mvs_info *mvi);
	int (*spi_init)(struct mvs_info *mvi);
	int (*chip_ioremap)(struct mvs_info *mvi);
	void (*chip_iounmap)(struct mvs_info *mvi);
	irqreturn_t (*isr)(struct mvs_info *mvi, int irq, u32 stat);
	u32 (*isr_status)(struct mvs_info *mvi, int irq);
	void (*interrupt_enable)(struct mvs_info *mvi);
	void (*interrupt_disable)(struct mvs_info *mvi);

	u32 (*read_phy_ctl)(struct mvs_info *mvi, u32 port);
	void (*write_phy_ctl)(struct mvs_info *mvi, u32 port, u32 val);

	u32 (*read_port_cfg_data)(struct mvs_info *mvi, u32 port);
	void (*write_port_cfg_data)(struct mvs_info *mvi, u32 port, u32 val);
	void (*write_port_cfg_addr)(struct mvs_info *mvi, u32 port, u32 addr);

	u32 (*read_port_vsr_data)(struct mvs_info *mvi, u32 port);
	void (*write_port_vsr_data)(struct mvs_info *mvi, u32 port, u32 val);
	void (*write_port_vsr_addr)(struct mvs_info *mvi, u32 port, u32 addr);

	u32 (*read_port_irq_stat)(struct mvs_info *mvi, u32 port);
	void (*write_port_irq_stat)(struct mvs_info *mvi, u32 port, u32 val);

	u32 (*read_port_irq_mask)(struct mvs_info *mvi, u32 port);
	void (*write_port_irq_mask)(struct mvs_info *mvi, u32 port, u32 val);

	void (*command_active)(struct mvs_info *mvi, u32 slot_idx);
	void (*clear_srs_irq)(struct mvs_info *mvi, u8 reg_set, u8 clear_all);
	void (*issue_stop)(struct mvs_info *mvi, enum mvs_port_type type,
				u32 tfs);
	void (*start_delivery)(struct mvs_info *mvi, u32 tx);
	u32 (*rx_update)(struct mvs_info *mvi);
	void (*int_full)(struct mvs_info *mvi);
	u8 (*assign_reg_set)(struct mvs_info *mvi, u8 *tfs);
	void (*free_reg_set)(struct mvs_info *mvi, u8 *tfs);
	u32 (*prd_size)(void);
	u32 (*prd_count)(void);
	void (*make_prd)(struct scatterlist *scatter, int nr, void *prd);
	void (*detect_porttype)(struct mvs_info *mvi, int i);
	int (*oob_done)(struct mvs_info *mvi, int i);
	void (*fix_phy_info)(struct mvs_info *mvi, int i,
				struct sas_identify_frame *id);
	void (*phy_work_around)(struct mvs_info *mvi, int i);
	void (*phy_set_link_rate)(struct mvs_info *mvi, u32 phy_id,
				struct sas_phy_linkrates *rates);
	u32 (*phy_max_link_rate)(void);
	void (*phy_disable)(struct mvs_info *mvi, u32 phy_id);
	void (*phy_enable)(struct mvs_info *mvi, u32 phy_id);
	void (*phy_reset)(struct mvs_info *mvi, u32 phy_id, int hard);
	void (*stp_reset)(struct mvs_info *mvi, u32 phy_id);
	void (*clear_active_cmds)(struct mvs_info *mvi);
	u32 (*spi_read_data)(struct mvs_info *mvi);
	void (*spi_write_data)(struct mvs_info *mvi, u32 data);
	int (*spi_buildcmd)(struct mvs_info *mvi,
						u32      *dwCmd,
						u8       cmd,
						u8       read,
						u8       length,
						u32      addr
						);
	int (*spi_issuecmd)(struct mvs_info *mvi, u32 cmd);
	int (*spi_waitdataready)(struct mvs_info *mvi, u32 timeout);
	void (*dma_fix)(struct mvs_info *mvi, u32 phy_mask,
				int buf_len, int from, void *prd);
	void (*tune_interrupt)(struct mvs_info *mvi, u32 time);
	void (*non_spec_ncq_error)(struct mvs_info *mvi);

};

struct mvs_chip_info {
	u32 		n_host;
	u32 		n_phy;
	u32 		fis_offs;
	u32 		fis_count;
	u32 		srs_sz;
	u32		sg_width;
	u32 		slot_width;
	const struct mvs_dispatch *dispatch;
};
#define MVS_MAX_SG		(1U << mvi->chip->sg_width)
#define MVS_CHIP_SLOT_SZ	(1U << mvi->chip->slot_width)
#define MVS_RX_FISL_SZ		\
	(mvi->chip->fis_offs + (mvi->chip->fis_count * 0x100))
#define MVS_CHIP_DISP		(mvi->chip->dispatch)

struct mvs_err_info {
	__le32			flags;
	__le32			flags2;
};

struct mvs_cmd_hdr {
	__le32			flags;	/* PRD tbl len; SAS, SATA ctl */
	__le32			lens;	/* cmd, max resp frame len */
	__le32			tags;	/* targ port xfer tag; tag */
	__le32			data_len;	/* data xfer len */
	__le64			cmd_tbl;  	/* command table address */
	__le64			open_frame;	/* open addr frame address */
	__le64			status_buf;	/* status buffer address */
	__le64			prd_tbl;		/* PRD tbl address */
	__le32			reserved[4];
};

struct mvs_port {
	struct asd_sas_port	sas_port;
	u8			port_attached;
	u8			wide_port_phymap;
	struct list_head	list;
};

struct mvs_phy {
	struct mvs_info 		*mvi;
	struct mvs_port		*port;
	struct asd_sas_phy	sas_phy;
	struct sas_identify	identify;
	struct scsi_device	*sdev;
	struct timer_list timer;
	u64		dev_sas_addr;
	u64		att_dev_sas_addr;
	u32		att_dev_info;
	u32		dev_info;
	u32		phy_type;
	u32		phy_status;
	u32		irq_status;
	u32		frame_rcvd_size;
	u8		frame_rcvd[32];
	u8		phy_attached;
	u8		phy_mode;
	u8		reserved[2];
	u32		phy_event;
	enum sas_linkrate	minimum_linkrate;
	enum sas_linkrate	maximum_linkrate;
};

struct mvs_device {
	struct list_head		dev_entry;
	enum sas_dev_type dev_type;
	struct mvs_info *mvi_info;
	struct domain_device *sas_device;
	struct timer_list timer;
	u32 attached_phy;
	u32 device_id;
	u32 running_req;
	u8 taskfileset;
	u8 dev_status;
	u16 reserved;
};

/* Generate  PHY tunning parameters */
struct phy_tuning {
	/* 1 bit,  transmitter emphasis enable	*/
	u8	trans_emp_en:1;
	/* 4 bits, transmitter emphasis amplitude */
	u8	trans_emp_amp:4;
	/* 3 bits, reserved space */
	u8	Reserved_2bit_1:3;
	/* 5 bits, transmitter amplitude */
	u8	trans_amp:5;
	/* 2 bits, transmitter amplitude adjust */
	u8	trans_amp_adj:2;
	/* 1 bit, reserved space */
	u8	resv_2bit_2:1;
	/* 2 bytes, reserved space */
	u8	reserved[2];
};

struct ffe_control {
	/* 4 bits,  FFE Capacitor Select  (value range 0~F)  */
	u8 ffe_cap_sel:4;
	/* 3 bits,  FFE Resistor Select (value range 0~7) */
	u8 ffe_rss_sel:3;
	/* 1 bit reserve*/
	u8 reserved:1;
};

/*
 * HBA_Info_Page is saved in Flash/NVRAM, total 256 bytes.
 * The data area is valid only Signature="MRVL".
 * If any member fills with 0xFF, the member is invalid.
 */
struct hba_info_page {
	/* Dword 0 */
	/* 4 bytes, structure signature,should be "MRVL" at first initial */
	u8 signature[4];

	/* Dword 1-13 */
	u32 reserved1[13];

	/* Dword 14-29 */
	/* 64 bytes, SAS address for each port */
	u64 sas_addr[8];

	/* Dword 30-31 */
	/* 8 bytes for vanir 8 port PHY FFE seeting
	 * BIT 0~3 : FFE Capacitor select(value range 0~F)
	 * BIT 4~6 : FFE Resistor select(value range 0~7)
	 * BIT 7: reserve.
	 */

	struct ffe_control  ffe_ctl[8];
	/* Dword 32 -43 */
	u32 reserved2[12];

	/* Dword 44-45 */
	/* 8 bytes,  0:  1.5G, 1: 3.0G, should be 0x01 at first initial */
	u8 phy_rate[8];

	/* Dword 46-53 */
	/* 32 bytes, PHY tuning parameters for each PHY*/
	struct phy_tuning   phy_tuning[8];

	/* Dword 54-63 */
	u32 reserved3[10];
};	/* total 256 bytes */

struct mvs_slot_info {
	struct list_head entry;
	union {
		struct sas_task *task;
		void *tdata;
	};
	u32 n_elem;
	u32 tx;
	u32 slot_tag;

	/* DMA buffer for storing cmd tbl, open addr frame, status buffer,
	 * and PRD table
	 */
	void *buf;
	dma_addr_t buf_dma;
	void *response;
	struct mvs_port *port;
	struct mvs_device	*device;
	void *open_frame;
};

struct mvs_info {
	unsigned long flags;

	/* host-wide lock */
	spinlock_t lock;

	/* our device */
	struct pci_dev *pdev;
	struct device *dev;

	/* enhanced mode registers */
	void __iomem *regs;

	/* peripheral or soc registers */
	void __iomem *regs_ex;
	u8 sas_addr[SAS_ADDR_SIZE];

	/* SCSI/SAS glue */
	struct sas_ha_struct *sas;
	struct Scsi_Host *shost;

	/* TX (delivery) DMA ring */
	__le32 *tx;
	dma_addr_t tx_dma;

	/* cached next-producer idx */
	u32 tx_prod;

	/* RX (completion) DMA ring */
	__le32	*rx;
	dma_addr_t rx_dma;

	/* RX consumer idx */
	u32 rx_cons;

	/* RX'd FIS area */
	__le32 *rx_fis;
	dma_addr_t rx_fis_dma;

	/* DMA command header slots */
	struct mvs_cmd_hdr *slot;
	dma_addr_t slot_dma;

	u32 chip_id;
	const struct mvs_chip_info *chip;

	int tags_num;
	unsigned long *tags;
	/* further per-slot information */
	struct mvs_phy phy[MVS_MAX_PHYS];
	struct mvs_port port[MVS_MAX_PHYS];
	u32 id;
	u64 sata_reg_set;
	struct list_head *hba_list;
	struct list_head soc_entry;
	struct list_head wq_list;
	unsigned long instance;
	u16 flashid;
	u32 flashsize;
	u32 flashsectSize;

	void *addon;
	struct hba_info_page hba_info_param;
	struct mvs_device	devices[MVS_MAX_DEVICES];
	void *bulk_buffer;
	dma_addr_t bulk_buffer_dma;
	void *bulk_buffer1;
	dma_addr_t bulk_buffer_dma1;
#define TRASH_BUCKET_SIZE    	0x20000
	void *dma_pool;
	struct mvs_slot_info slot_info[0];
};

struct mvs_prv_info{
	u8 n_host;
	u8 n_phy;
	u16 reserve;
	struct mvs_info *mvi[2];
};

struct mvs_wq {
	struct delayed_work work_q;
	struct mvs_info *mvi;
	void *data;
	int handler;
	struct list_head entry;
};

struct mvs_task_exec_info {
	struct sas_task *task;
	struct mvs_cmd_hdr *hdr;
	struct mvs_port *port;
	u32 tag;
	int n_elem;
};

struct mvs_task_list {
	struct sas_task *task;
	struct list_head list;
};


/******************** function prototype *********************/
void mvs_get_sas_addr(void *buf, u32 buflen);
void mvs_tag_clear(struct mvs_info *mvi, u32 tag);
void mvs_tag_free(struct mvs_info *mvi, u32 tag);
void mvs_tag_set(struct mvs_info *mvi, unsigned int tag);
int mvs_tag_alloc(struct mvs_info *mvi, u32 *tag_out);
void mvs_tag_init(struct mvs_info *mvi);
void mvs_iounmap(void __iomem *regs);
int mvs_ioremap(struct mvs_info *mvi, int bar, int bar_ex);
void mvs_phys_reset(struct mvs_info *mvi, u32 phy_mask, int hard);
int mvs_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func,
			void *funcdata);
void __devinit mvs_set_sas_addr(struct mvs_info *mvi, int port_id,
				u32 off_lo, u32 off_hi, u64 sas_addr);
int mvs_slave_alloc(struct scsi_device *scsi_dev);
int mvs_slave_configure(struct scsi_device *sdev);
void mvs_scan_start(struct Scsi_Host *shost);
int mvs_scan_finished(struct Scsi_Host *shost, unsigned long time);
int mvs_queue_command(struct sas_task *task, const int num,
			gfp_t gfp_flags);
int mvs_abort_task(struct sas_task *task);
int mvs_abort_task_set(struct domain_device *dev, u8 *lun);
int mvs_clear_aca(struct domain_device *dev, u8 *lun);
int mvs_clear_task_set(struct domain_device *dev, u8 * lun);
void mvs_port_formed(struct asd_sas_phy *sas_phy);
void mvs_port_deformed(struct asd_sas_phy *sas_phy);
int mvs_dev_found(struct domain_device *dev);
void mvs_dev_gone(struct domain_device *dev);
int mvs_lu_reset(struct domain_device *dev, u8 *lun);
int mvs_slot_complete(struct mvs_info *mvi, u32 rx_desc, u32 flags);
int mvs_I_T_nexus_reset(struct domain_device *dev);
int mvs_query_task(struct sas_task *task);
void mvs_release_task(struct mvs_info *mvi,
			struct domain_device *dev);
void mvs_do_release_task(struct mvs_info *mvi, int phy_no,
			struct domain_device *dev);
void mvs_int_port(struct mvs_info *mvi, int phy_no, u32 events);
void mvs_update_phyinfo(struct mvs_info *mvi, int i, int get_st);
int mvs_int_rx(struct mvs_info *mvi, bool self_clear);
struct mvs_device *mvs_find_dev_by_reg_set(struct mvs_info *mvi, u8 reg_set);
#endif
Commit	Line	Data
dd4969a8	1	/*
20b09c29 AY	2	* Marvell 88SE64xx/88SE94xx main function head file
	3	*
	4	* Copyright 2007 Red Hat, Inc.
	5	* Copyright 2008 Marvell. <kewei@marvell.com>
0b15fb1f	6	* Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
20b09c29 AY	7	*
	8	* This file is licensed under GPLv2.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; version 2 of the
	13	* License.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	18	* General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
	23	* USA
	24	*/
dd4969a8 JG	25
	26	#ifndef _MV_SAS_H_
	27	#define _MV_SAS_H_
	28
	29	#include <linux/kernel.h>
	30	#include <linux/module.h>
	31	#include <linux/spinlock.h>
	32	#include <linux/delay.h>
	33	#include <linux/types.h>
	34	#include <linux/ctype.h>
	35	#include <linux/dma-mapping.h>
	36	#include <linux/pci.h>
	37	#include <linux/platform_device.h>
	38	#include <linux/interrupt.h>
	39	#include <linux/irq.h>
5a0e3ad6	40	#include <linux/slab.h>
dd4969a8 JG	41	#include <linux/vmalloc.h>
dd4969a8 JG	42	#include <scsi/libsas.h>
9dc9fd94	43	#include <scsi/scsi.h>
dd4969a8 JG	44	#include <scsi/scsi_tcq.h>
	45	#include <scsi/sas_ata.h>
	46	#include <linux/version.h>
	47	#include "mv_defs.h"
	48
20b09c29 AY	49	#define DRV_NAME "mvsas"
20b09c29 AY	50	#define DRV_VERSION "0.8.2"
dd4969a8	51	#define MVS_ID_NOT_MAPPED 0x7f
20b09c29	52	#define WIDE_PORT_MAX_PHY 4
20b09c29 AY	53	#define mv_printk(fmt, arg ...) \
	54	printk(KERN_DEBUG"%s %d:" fmt, __FILE__, __LINE__, ## arg)
	55	#ifdef MV_DEBUG
	56	#define mv_dprintk(format, arg...) \
	57	printk(KERN_DEBUG"%s %d:" format, __FILE__, __LINE__, ## arg)
	58	#else
	59	#define mv_dprintk(format, arg...)
	60	#endif
	61	#define MV_MAX_U32 0xffffffff
	62
83c7b61c	63	extern int interrupt_coalescing;
20b09c29 AY	64	extern struct mvs_tgt_initiator mvs_tgt;
	65	extern struct mvs_info *tgt_mvi;
	66	extern const struct mvs_dispatch mvs_64xx_dispatch;
	67	extern const struct mvs_dispatch mvs_94xx_dispatch;
0b15fb1f	68	extern struct kmem_cache *mvs_task_list_cache;
20b09c29 AY	69
	70	#define DEV_IS_EXPANDER(type) \
	71	((type == EDGE_DEV) \|\| (type == FANOUT_DEV))
dd4969a8	72
20b09c29 AY	73	#define bit(n) ((u32)1 << n)
	74
	75	#define for_each_phy(__lseq_mask, __mc, __lseq) \
	76	for ((__mc) = (__lseq_mask), (__lseq) = 0; \
	77	(__mc) != 0 ; \
dd4969a8 JG	78	(++__lseq), (__mc) >>= 1)
dd4969a8 JG	79
20b09c29 AY	80	#define MV_INIT_DELAYED_WORK(w, f, d) INIT_DELAYED_WORK(w, f)
	81	#define UNASSOC_D2H_FIS(id) \
	82	((void ) mvi->rx_fis + 0x100 id)
	83	#define SATA_RECEIVED_FIS_LIST(reg_set) \
	84	((void ) mvi->rx_fis + mvi->chip->fis_offs + 0x100 reg_set)
	85	#define SATA_RECEIVED_SDB_FIS(reg_set) \
	86	(SATA_RECEIVED_FIS_LIST(reg_set) + 0x58)
	87	#define SATA_RECEIVED_D2H_FIS(reg_set) \
	88	(SATA_RECEIVED_FIS_LIST(reg_set) + 0x40)
	89	#define SATA_RECEIVED_PIO_FIS(reg_set) \
	90	(SATA_RECEIVED_FIS_LIST(reg_set) + 0x20)
	91	#define SATA_RECEIVED_DMA_FIS(reg_set) \
	92	(SATA_RECEIVED_FIS_LIST(reg_set) + 0x00)
	93
	94	enum dev_status {
	95	MVS_DEV_NORMAL = 0x0,
	96	MVS_DEV_EH = 0x1,
	97	};
	98
a4632aae XY	99	enum dev_reset {
	100	MVS_SOFT_RESET = 0,
	101	MVS_HARD_RESET = 1,
	102	MVS_PHY_TUNE = 2,
	103	};
20b09c29 AY	104
	105	struct mvs_info;
	106
	107	struct mvs_dispatch {
	108	char *name;
	109	int (chip_init)(struct mvs_info mvi);
	110	int (spi_init)(struct mvs_info mvi);
	111	int (chip_ioremap)(struct mvs_info mvi);
	112	void (chip_iounmap)(struct mvs_info mvi);
	113	irqreturn_t (isr)(struct mvs_info mvi, int irq, u32 stat);
	114	u32 (isr_status)(struct mvs_info mvi, int irq);
	115	void (interrupt_enable)(struct mvs_info mvi);
	116	void (interrupt_disable)(struct mvs_info mvi);
	117
	118	u32 (read_phy_ctl)(struct mvs_info mvi, u32 port);
	119	void (write_phy_ctl)(struct mvs_info mvi, u32 port, u32 val);
	120
	121	u32 (read_port_cfg_data)(struct mvs_info mvi, u32 port);
	122	void (write_port_cfg_data)(struct mvs_info mvi, u32 port, u32 val);
	123	void (write_port_cfg_addr)(struct mvs_info mvi, u32 port, u32 addr);
	124
	125	u32 (read_port_vsr_data)(struct mvs_info mvi, u32 port);
	126	void (write_port_vsr_data)(struct mvs_info mvi, u32 port, u32 val);
	127	void (write_port_vsr_addr)(struct mvs_info mvi, u32 port, u32 addr);
	128
	129	u32 (read_port_irq_stat)(struct mvs_info mvi, u32 port);
	130	void (write_port_irq_stat)(struct mvs_info mvi, u32 port, u32 val);
	131
	132	u32 (read_port_irq_mask)(struct mvs_info mvi, u32 port);
	133	void (write_port_irq_mask)(struct mvs_info mvi, u32 port, u32 val);
	134
20b09c29	135	void (command_active)(struct mvs_info mvi, u32 slot_idx);
9dc9fd94	136	void (clear_srs_irq)(struct mvs_info mvi, u8 reg_set, u8 clear_all);
20b09c29 AY	137	void (issue_stop)(struct mvs_info mvi, enum mvs_port_type type,
	138	u32 tfs);
	139	void (start_delivery)(struct mvs_info mvi, u32 tx);
	140	u32 (rx_update)(struct mvs_info mvi);
	141	void (int_full)(struct mvs_info mvi);
	142	u8 (assign_reg_set)(struct mvs_info mvi, u8 *tfs);
	143	void (free_reg_set)(struct mvs_info mvi, u8 *tfs);
	144	u32 (*prd_size)(void);
	145	u32 (*prd_count)(void);
	146	void (make_prd)(struct scatterlist scatter, int nr, void *prd);
	147	void (detect_porttype)(struct mvs_info mvi, int i);
	148	int (oob_done)(struct mvs_info mvi, int i);
	149	void (fix_phy_info)(struct mvs_info mvi, int i,
	150	struct sas_identify_frame *id);
	151	void (phy_work_around)(struct mvs_info mvi, int i);
	152	void (phy_set_link_rate)(struct mvs_info mvi, u32 phy_id,
	153	struct sas_phy_linkrates *rates);
	154	u32 (*phy_max_link_rate)(void);
	155	void (phy_disable)(struct mvs_info mvi, u32 phy_id);
	156	void (phy_enable)(struct mvs_info mvi, u32 phy_id);
	157	void (phy_reset)(struct mvs_info mvi, u32 phy_id, int hard);
	158	void (stp_reset)(struct mvs_info mvi, u32 phy_id);
	159	void (clear_active_cmds)(struct mvs_info mvi);
	160	u32 (spi_read_data)(struct mvs_info mvi);
	161	void (spi_write_data)(struct mvs_info mvi, u32 data);
	162	int (spi_buildcmd)(struct mvs_info mvi,
	163	u32 *dwCmd,
	164	u8 cmd,
	165	u8 read,
	166	u8 length,
	167	u32 addr
	168	);
	169	int (spi_issuecmd)(struct mvs_info mvi, u32 cmd);
	170	int (spi_waitdataready)(struct mvs_info mvi, u32 timeout);
8882f081 XY	171	void (dma_fix)(struct mvs_info mvi, u32 phy_mask,
8882f081 XY	172	int buf_len, int from, void *prd);
83c7b61c	173	void (tune_interrupt)(struct mvs_info mvi, u32 time);
534ff101	174	void (non_spec_ncq_error)(struct mvs_info mvi);
20b09c29 AY	175
	176	};
	177
dd4969a8	178	struct mvs_chip_info {
20b09c29 AY	179	u32 n_host;
	180	u32 n_phy;
	181	u32 fis_offs;
	182	u32 fis_count;
	183	u32 srs_sz;
a4632aae	184	u32 sg_width;
20b09c29 AY	185	u32 slot_width;
20b09c29 AY	186	const struct mvs_dispatch *dispatch;
dd4969a8	187	};
a4632aae	188	#define MVS_MAX_SG (1U << mvi->chip->sg_width)
20b09c29 AY	189	#define MVS_CHIP_SLOT_SZ (1U << mvi->chip->slot_width)
	190	#define MVS_RX_FISL_SZ \
	191	(mvi->chip->fis_offs + (mvi->chip->fis_count * 0x100))
	192	#define MVS_CHIP_DISP (mvi->chip->dispatch)
dd4969a8 JG	193
	194	struct mvs_err_info {
	195	__le32 flags;
	196	__le32 flags2;
	197	};
	198
	199	struct mvs_cmd_hdr {
	200	__le32 flags; /* PRD tbl len; SAS, SATA ctl */
	201	__le32 lens; /* cmd, max resp frame len */
	202	__le32 tags; /* targ port xfer tag; tag */
	203	__le32 data_len; /* data xfer len */
20b09c29	204	__le64 cmd_tbl; /* command table address */
dd4969a8 JG	205	__le64 open_frame; /* open addr frame address */
	206	__le64 status_buf; /* status buffer address */
	207	__le64 prd_tbl; /* PRD tbl address */
	208	__le32 reserved[4];
	209	};
	210
	211	struct mvs_port {
	212	struct asd_sas_port sas_port;
	213	u8 port_attached;
dd4969a8 JG	214	u8 wide_port_phymap;
	215	struct list_head list;
	216	};
	217
	218	struct mvs_phy {
20b09c29	219	struct mvs_info *mvi;
dd4969a8 JG	220	struct mvs_port *port;
	221	struct asd_sas_phy sas_phy;
	222	struct sas_identify identify;
	223	struct scsi_device *sdev;
20b09c29	224	struct timer_list timer;
dd4969a8 JG	225	u64 dev_sas_addr;
	226	u64 att_dev_sas_addr;
	227	u32 att_dev_info;
	228	u32 dev_info;
	229	u32 phy_type;
	230	u32 phy_status;
	231	u32 irq_status;
	232	u32 frame_rcvd_size;
	233	u8 frame_rcvd[32];
	234	u8 phy_attached;
20b09c29 AY	235	u8 phy_mode;
	236	u8 reserved[2];
	237	u32 phy_event;
dd4969a8 JG	238	enum sas_linkrate minimum_linkrate;
	239	enum sas_linkrate maximum_linkrate;
	240	};
	241
20b09c29	242	struct mvs_device {
9870d9a2	243	struct list_head dev_entry;
20b09c29	244	enum sas_dev_type dev_type;
9870d9a2	245	struct mvs_info *mvi_info;
20b09c29	246	struct domain_device *sas_device;
9dc9fd94	247	struct timer_list timer;
20b09c29 AY	248	u32 attached_phy;
20b09c29 AY	249	u32 device_id;
9dc9fd94	250	u32 running_req;
20b09c29 AY	251	u8 taskfileset;
	252	u8 dev_status;
	253	u16 reserved;
20b09c29 AY	254	};
20b09c29 AY	255
f1f82a91 XY	256	/* Generate PHY tunning parameters */
	257	struct phy_tuning {
	258	/* 1 bit, transmitter emphasis enable */
	259	u8 trans_emp_en:1;
	260	/* 4 bits, transmitter emphasis amplitude */
	261	u8 trans_emp_amp:4;
	262	/* 3 bits, reserved space */
	263	u8 Reserved_2bit_1:3;
	264	/* 5 bits, transmitter amplitude */
	265	u8 trans_amp:5;
	266	/* 2 bits, transmitter amplitude adjust */
	267	u8 trans_amp_adj:2;
	268	/* 1 bit, reserved space */
	269	u8 resv_2bit_2:1;
	270	/* 2 bytes, reserved space */
	271	u8 reserved[2];
	272	};
	273
	274	struct ffe_control {
	275	/* 4 bits, FFE Capacitor Select (value range 0~F) */
	276	u8 ffe_cap_sel:4;
	277	/* 3 bits, FFE Resistor Select (value range 0~7) */
	278	u8 ffe_rss_sel:3;
	279	/* 1 bit reserve*/
	280	u8 reserved:1;
	281	};
	282
	283	/*
	284	* HBA_Info_Page is saved in Flash/NVRAM, total 256 bytes.
	285	* The data area is valid only Signature="MRVL".
	286	* If any member fills with 0xFF, the member is invalid.
	287	*/
	288	struct hba_info_page {
	289	/* Dword 0 */
	290	/* 4 bytes, structure signature,should be "MRVL" at first initial */
	291	u8 signature[4];
	292
	293	/* Dword 1-13 */
	294	u32 reserved1[13];
	295
	296	/* Dword 14-29 */
	297	/* 64 bytes, SAS address for each port */
	298	u64 sas_addr[8];
	299
	300	/* Dword 30-31 */
	301	/* 8 bytes for vanir 8 port PHY FFE seeting
	302	* BIT 0~3 : FFE Capacitor select(value range 0~F)
	303	* BIT 4~6 : FFE Resistor select(value range 0~7)
	304	* BIT 7: reserve.
	305	*/
	306
	307	struct ffe_control ffe_ctl[8];
	308	/* Dword 32 -43 */
	309	u32 reserved2[12];
	310
	311	/* Dword 44-45 */
	312	/* 8 bytes, 0: 1.5G, 1: 3.0G, should be 0x01 at first initial */
	313	u8 phy_rate[8];
	314
	315	/* Dword 46-53 */
	316	/* 32 bytes, PHY tuning parameters for each PHY*/
	317	struct phy_tuning phy_tuning[8];
	318
	319	/* Dword 54-63 */
320	u32 reserved3[10];
321	}; /* total 256 bytes */
322
dd4969a8	323	struct mvs_slot_info {
20b09c29 AY	324	struct list_head entry;
	325	union {
	326	struct sas_task *task;
	327	void *tdata;
	328	};
dd4969a8 JG	329	u32 n_elem;
dd4969a8 JG	330	u32 tx;
20b09c29	331	u32 slot_tag;
dd4969a8 JG	332
	333	/* DMA buffer for storing cmd tbl, open addr frame, status buffer,
	334	* and PRD table
	335	*/
	336	void *buf;
	337	dma_addr_t buf_dma;
dd4969a8 JG	338	void *response;
dd4969a8 JG	339	struct mvs_port *port;
20b09c29 AY	340	struct mvs_device *device;
20b09c29 AY	341	void *open_frame;
dd4969a8 JG	342	};
	343
	344	struct mvs_info {
	345	unsigned long flags;
	346
	347	/* host-wide lock */
	348	spinlock_t lock;
	349
	350	/* our device */
	351	struct pci_dev *pdev;
20b09c29	352	struct device *dev;
dd4969a8 JG	353
	354	/* enhanced mode registers */
	355	void __iomem *regs;
	356
20b09c29 AY	357	/* peripheral or soc registers */
20b09c29 AY	358	void __iomem *regs_ex;
dd4969a8 JG	359	u8 sas_addr[SAS_ADDR_SIZE];
	360
	361	/* SCSI/SAS glue */
20b09c29	362	struct sas_ha_struct *sas;
dd4969a8 JG	363	struct Scsi_Host *shost;
	364
	365	/* TX (delivery) DMA ring */
	366	__le32 *tx;
	367	dma_addr_t tx_dma;
	368
	369	/* cached next-producer idx */
	370	u32 tx_prod;
	371
	372	/* RX (completion) DMA ring */
20b09c29	373	__le32 *rx;
dd4969a8 JG	374	dma_addr_t rx_dma;
	375
	376	/* RX consumer idx */
	377	u32 rx_cons;
	378
	379	/* RX'd FIS area */
	380	__le32 *rx_fis;
	381	dma_addr_t rx_fis_dma;
	382
	383	/* DMA command header slots */
	384	struct mvs_cmd_hdr *slot;
	385	dma_addr_t slot_dma;
	386
20b09c29	387	u32 chip_id;
dd4969a8 JG	388	const struct mvs_chip_info *chip;
dd4969a8 JG	389
20b09c29	390	int tags_num;
b89e8f53	391	unsigned long *tags;
20b09c29	392	/* further per-slot information */
dd4969a8 JG	393	struct mvs_phy phy[MVS_MAX_PHYS];
dd4969a8 JG	394	struct mvs_port port[MVS_MAX_PHYS];
20b09c29 AY	395	u32 id;
	396	u64 sata_reg_set;
	397	struct list_head *hba_list;
	398	struct list_head soc_entry;
	399	struct list_head wq_list;
	400	unsigned long instance;
	401	u16 flashid;
	402	u32 flashsize;
	403	u32 flashsectSize;
	404
	405	void *addon;
f1f82a91	406	struct hba_info_page hba_info_param;
20b09c29	407	struct mvs_device devices[MVS_MAX_DEVICES];
20b09c29 AY	408	void *bulk_buffer;
20b09c29 AY	409	dma_addr_t bulk_buffer_dma;
8882f081 XY	410	void *bulk_buffer1;
8882f081 XY	411	dma_addr_t bulk_buffer_dma1;
20b09c29	412	#define TRASH_BUCKET_SIZE 0x20000
0b15fb1f	413	void *dma_pool;
20b09c29 AY	414	struct mvs_slot_info slot_info[0];
	415	};
	416
	417	struct mvs_prv_info{
	418	u8 n_host;
	419	u8 n_phy;
	420	u16 reserve;
	421	struct mvs_info *mvi[2];
	422	};
	423
	424	struct mvs_wq {
	425	struct delayed_work work_q;
	426	struct mvs_info *mvi;
	427	void *data;
	428	int handler;
	429	struct list_head entry;
dd4969a8 JG	430	};
dd4969a8 JG	431
20b09c29 AY	432	struct mvs_task_exec_info {
	433	struct sas_task *task;
	434	struct mvs_cmd_hdr *hdr;
	435	struct mvs_port *port;
	436	u32 tag;
	437	int n_elem;
	438	};
	439
0b15fb1f XY	440	struct mvs_task_list {
	441	struct sas_task *task;
	442	struct list_head list;
	443	};
	444
20b09c29 AY	445
	446	/****************** function prototype *******************/
	447	void mvs_get_sas_addr(void *buf, u32 buflen);
	448	void mvs_tag_clear(struct mvs_info *mvi, u32 tag);
	449	void mvs_tag_free(struct mvs_info *mvi, u32 tag);
	450	void mvs_tag_set(struct mvs_info *mvi, unsigned int tag);
	451	int mvs_tag_alloc(struct mvs_info mvi, u32 tag_out);
	452	void mvs_tag_init(struct mvs_info *mvi);
	453	void mvs_iounmap(void __iomem *regs);
	454	int mvs_ioremap(struct mvs_info *mvi, int bar, int bar_ex);
	455	void mvs_phys_reset(struct mvs_info *mvi, u32 phy_mask, int hard);
dd4969a8 JG	456	int mvs_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func,
dd4969a8 JG	457	void *funcdata);
20b09c29 AY	458	void __devinit mvs_set_sas_addr(struct mvs_info *mvi, int port_id,
	459	u32 off_lo, u32 off_hi, u64 sas_addr);
	460	int mvs_slave_alloc(struct scsi_device *scsi_dev);
dd4969a8 JG	461	int mvs_slave_configure(struct scsi_device *sdev);
	462	void mvs_scan_start(struct Scsi_Host *shost);
	463	int mvs_scan_finished(struct Scsi_Host *shost, unsigned long time);
20b09c29 AY	464	int mvs_queue_command(struct sas_task *task, const int num,
	465	gfp_t gfp_flags);
	466	int mvs_abort_task(struct sas_task *task);
	467	int mvs_abort_task_set(struct domain_device dev, u8 lun);
	468	int mvs_clear_aca(struct domain_device dev, u8 lun);
	469	int mvs_clear_task_set(struct domain_device dev, u8 lun);
dd4969a8	470	void mvs_port_formed(struct asd_sas_phy *sas_phy);
20b09c29 AY	471	void mvs_port_deformed(struct asd_sas_phy *sas_phy);
	472	int mvs_dev_found(struct domain_device *dev);
	473	void mvs_dev_gone(struct domain_device *dev);
	474	int mvs_lu_reset(struct domain_device dev, u8 lun);
	475	int mvs_slot_complete(struct mvs_info *mvi, u32 rx_desc, u32 flags);
dd4969a8	476	int mvs_I_T_nexus_reset(struct domain_device *dev);
20b09c29	477	int mvs_query_task(struct sas_task *task);
9dc9fd94 S	478	void mvs_release_task(struct mvs_info *mvi,
	479	struct domain_device *dev);
	480	void mvs_do_release_task(struct mvs_info *mvi, int phy_no,
20b09c29 AY	481	struct domain_device *dev);
	482	void mvs_int_port(struct mvs_info *mvi, int phy_no, u32 events);
	483	void mvs_update_phyinfo(struct mvs_info *mvi, int i, int get_st);
	484	int mvs_int_rx(struct mvs_info *mvi, bool self_clear);
534ff101	485	struct mvs_device mvs_find_dev_by_reg_set(struct mvs_info mvi, u8 reg_set);
dd4969a8	486	#endif
20b09c29	487