Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
fa90c54f | 2 | * QLogic Fibre Channel HBA Driver |
01e58d8e | 3 | * Copyright (c) 2003-2008 QLogic Corporation |
1da177e4 | 4 | * |
fa90c54f | 5 | * See LICENSE.qla2xxx for copyright and licensing details. |
1da177e4 LT |
6 | */ |
7 | #include "qla_def.h" | |
8 | ||
9 | #include <linux/delay.h> | |
10 | ||
a7a167bf | 11 | static inline void |
7b867cf7 | 12 | qla2xxx_prep_dump(struct qla_hw_data *ha, struct qla2xxx_fw_dump *fw_dump) |
a7a167bf AV |
13 | { |
14 | fw_dump->fw_major_version = htonl(ha->fw_major_version); | |
15 | fw_dump->fw_minor_version = htonl(ha->fw_minor_version); | |
16 | fw_dump->fw_subminor_version = htonl(ha->fw_subminor_version); | |
17 | fw_dump->fw_attributes = htonl(ha->fw_attributes); | |
18 | ||
19 | fw_dump->vendor = htonl(ha->pdev->vendor); | |
20 | fw_dump->device = htonl(ha->pdev->device); | |
21 | fw_dump->subsystem_vendor = htonl(ha->pdev->subsystem_vendor); | |
22 | fw_dump->subsystem_device = htonl(ha->pdev->subsystem_device); | |
23 | } | |
24 | ||
25 | static inline void * | |
73208dfd | 26 | qla2xxx_copy_queues(struct qla_hw_data *ha, void *ptr) |
a7a167bf | 27 | { |
73208dfd AC |
28 | struct req_que *req = ha->req_q_map[0]; |
29 | struct rsp_que *rsp = ha->rsp_q_map[0]; | |
a7a167bf | 30 | /* Request queue. */ |
7b867cf7 | 31 | memcpy(ptr, req->ring, req->length * |
a7a167bf AV |
32 | sizeof(request_t)); |
33 | ||
34 | /* Response queue. */ | |
7b867cf7 AC |
35 | ptr += req->length * sizeof(request_t); |
36 | memcpy(ptr, rsp->ring, rsp->length * | |
a7a167bf AV |
37 | sizeof(response_t)); |
38 | ||
7b867cf7 | 39 | return ptr + (rsp->length * sizeof(response_t)); |
a7a167bf | 40 | } |
1da177e4 | 41 | |
c3a2f0df | 42 | static int |
7b867cf7 | 43 | qla24xx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint32_t *ram, |
c5722708 | 44 | uint32_t ram_dwords, void **nxt) |
c3a2f0df AV |
45 | { |
46 | int rval; | |
c5722708 AV |
47 | uint32_t cnt, stat, timer, dwords, idx; |
48 | uint16_t mb0; | |
c3a2f0df | 49 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; |
c5722708 AV |
50 | dma_addr_t dump_dma = ha->gid_list_dma; |
51 | uint32_t *dump = (uint32_t *)ha->gid_list; | |
c3a2f0df AV |
52 | |
53 | rval = QLA_SUCCESS; | |
c5722708 | 54 | mb0 = 0; |
c3a2f0df | 55 | |
c5722708 | 56 | WRT_REG_WORD(®->mailbox0, MBC_DUMP_RISC_RAM_EXTENDED); |
c3a2f0df AV |
57 | clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); |
58 | ||
c5722708 AV |
59 | dwords = GID_LIST_SIZE / 4; |
60 | for (cnt = 0; cnt < ram_dwords && rval == QLA_SUCCESS; | |
61 | cnt += dwords, addr += dwords) { | |
62 | if (cnt + dwords > ram_dwords) | |
63 | dwords = ram_dwords - cnt; | |
c3a2f0df | 64 | |
c5722708 AV |
65 | WRT_REG_WORD(®->mailbox1, LSW(addr)); |
66 | WRT_REG_WORD(®->mailbox8, MSW(addr)); | |
c3a2f0df | 67 | |
c5722708 AV |
68 | WRT_REG_WORD(®->mailbox2, MSW(dump_dma)); |
69 | WRT_REG_WORD(®->mailbox3, LSW(dump_dma)); | |
70 | WRT_REG_WORD(®->mailbox6, MSW(MSD(dump_dma))); | |
71 | WRT_REG_WORD(®->mailbox7, LSW(MSD(dump_dma))); | |
c3a2f0df | 72 | |
c5722708 AV |
73 | WRT_REG_WORD(®->mailbox4, MSW(dwords)); |
74 | WRT_REG_WORD(®->mailbox5, LSW(dwords)); | |
c3a2f0df AV |
75 | WRT_REG_DWORD(®->hccr, HCCRX_SET_HOST_INT); |
76 | ||
77 | for (timer = 6000000; timer; timer--) { | |
78 | /* Check for pending interrupts. */ | |
79 | stat = RD_REG_DWORD(®->host_status); | |
80 | if (stat & HSRX_RISC_INT) { | |
81 | stat &= 0xff; | |
82 | ||
83 | if (stat == 0x1 || stat == 0x2 || | |
84 | stat == 0x10 || stat == 0x11) { | |
85 | set_bit(MBX_INTERRUPT, | |
86 | &ha->mbx_cmd_flags); | |
87 | ||
c5722708 | 88 | mb0 = RD_REG_WORD(®->mailbox0); |
c3a2f0df AV |
89 | |
90 | WRT_REG_DWORD(®->hccr, | |
91 | HCCRX_CLR_RISC_INT); | |
92 | RD_REG_DWORD(®->hccr); | |
93 | break; | |
94 | } | |
95 | ||
96 | /* Clear this intr; it wasn't a mailbox intr */ | |
97 | WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_INT); | |
98 | RD_REG_DWORD(®->hccr); | |
99 | } | |
100 | udelay(5); | |
101 | } | |
102 | ||
103 | if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { | |
c5722708 AV |
104 | rval = mb0 & MBS_MASK; |
105 | for (idx = 0; idx < dwords; idx++) | |
106 | ram[cnt + idx] = swab32(dump[idx]); | |
c3a2f0df AV |
107 | } else { |
108 | rval = QLA_FUNCTION_FAILED; | |
109 | } | |
110 | } | |
111 | ||
c5722708 | 112 | *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL; |
c3a2f0df AV |
113 | return rval; |
114 | } | |
115 | ||
c5722708 | 116 | static int |
7b867cf7 | 117 | qla24xx_dump_memory(struct qla_hw_data *ha, uint32_t *code_ram, |
c5722708 AV |
118 | uint32_t cram_size, void **nxt) |
119 | { | |
120 | int rval; | |
121 | ||
122 | /* Code RAM. */ | |
123 | rval = qla24xx_dump_ram(ha, 0x20000, code_ram, cram_size / 4, nxt); | |
124 | if (rval != QLA_SUCCESS) | |
125 | return rval; | |
126 | ||
127 | /* External Memory. */ | |
128 | return qla24xx_dump_ram(ha, 0x100000, *nxt, | |
129 | ha->fw_memory_size - 0x100000 + 1, nxt); | |
130 | } | |
131 | ||
c81d04c9 AV |
132 | static uint32_t * |
133 | qla24xx_read_window(struct device_reg_24xx __iomem *reg, uint32_t iobase, | |
134 | uint32_t count, uint32_t *buf) | |
135 | { | |
136 | uint32_t __iomem *dmp_reg; | |
137 | ||
138 | WRT_REG_DWORD(®->iobase_addr, iobase); | |
139 | dmp_reg = ®->iobase_window; | |
140 | while (count--) | |
141 | *buf++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
142 | ||
143 | return buf; | |
144 | } | |
145 | ||
146 | static inline int | |
147 | qla24xx_pause_risc(struct device_reg_24xx __iomem *reg) | |
148 | { | |
149 | int rval = QLA_SUCCESS; | |
150 | uint32_t cnt; | |
151 | ||
c3b058af AV |
152 | if (RD_REG_DWORD(®->hccr) & HCCRX_RISC_PAUSE) |
153 | return rval; | |
154 | ||
155 | WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_PAUSE); | |
156 | for (cnt = 30000; (RD_REG_DWORD(®->hccr) & HCCRX_RISC_PAUSE) == 0 && | |
157 | rval == QLA_SUCCESS; cnt--) { | |
158 | if (cnt) | |
159 | udelay(100); | |
160 | else | |
161 | rval = QLA_FUNCTION_TIMEOUT; | |
c81d04c9 AV |
162 | } |
163 | ||
164 | return rval; | |
165 | } | |
166 | ||
167 | static int | |
7b867cf7 | 168 | qla24xx_soft_reset(struct qla_hw_data *ha) |
c81d04c9 AV |
169 | { |
170 | int rval = QLA_SUCCESS; | |
171 | uint32_t cnt; | |
172 | uint16_t mb0, wd; | |
173 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; | |
174 | ||
175 | /* Reset RISC. */ | |
176 | WRT_REG_DWORD(®->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); | |
177 | for (cnt = 0; cnt < 30000; cnt++) { | |
178 | if ((RD_REG_DWORD(®->ctrl_status) & CSRX_DMA_ACTIVE) == 0) | |
179 | break; | |
180 | ||
181 | udelay(10); | |
182 | } | |
183 | ||
184 | WRT_REG_DWORD(®->ctrl_status, | |
185 | CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); | |
186 | pci_read_config_word(ha->pdev, PCI_COMMAND, &wd); | |
187 | ||
188 | udelay(100); | |
189 | /* Wait for firmware to complete NVRAM accesses. */ | |
190 | mb0 = (uint32_t) RD_REG_WORD(®->mailbox0); | |
191 | for (cnt = 10000 ; cnt && mb0; cnt--) { | |
192 | udelay(5); | |
193 | mb0 = (uint32_t) RD_REG_WORD(®->mailbox0); | |
194 | barrier(); | |
195 | } | |
196 | ||
197 | /* Wait for soft-reset to complete. */ | |
198 | for (cnt = 0; cnt < 30000; cnt++) { | |
199 | if ((RD_REG_DWORD(®->ctrl_status) & | |
200 | CSRX_ISP_SOFT_RESET) == 0) | |
201 | break; | |
202 | ||
203 | udelay(10); | |
204 | } | |
205 | WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_RESET); | |
206 | RD_REG_DWORD(®->hccr); /* PCI Posting. */ | |
207 | ||
208 | for (cnt = 30000; RD_REG_WORD(®->mailbox0) != 0 && | |
209 | rval == QLA_SUCCESS; cnt--) { | |
210 | if (cnt) | |
211 | udelay(100); | |
212 | else | |
213 | rval = QLA_FUNCTION_TIMEOUT; | |
214 | } | |
215 | ||
216 | return rval; | |
217 | } | |
218 | ||
c5722708 | 219 | static int |
7b867cf7 AC |
220 | qla2xxx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint16_t *ram, |
221 | uint16_t ram_words, void **nxt) | |
c5722708 AV |
222 | { |
223 | int rval; | |
224 | uint32_t cnt, stat, timer, words, idx; | |
225 | uint16_t mb0; | |
226 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; | |
227 | dma_addr_t dump_dma = ha->gid_list_dma; | |
228 | uint16_t *dump = (uint16_t *)ha->gid_list; | |
229 | ||
230 | rval = QLA_SUCCESS; | |
231 | mb0 = 0; | |
232 | ||
233 | WRT_MAILBOX_REG(ha, reg, 0, MBC_DUMP_RISC_RAM_EXTENDED); | |
234 | clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); | |
235 | ||
236 | words = GID_LIST_SIZE / 2; | |
237 | for (cnt = 0; cnt < ram_words && rval == QLA_SUCCESS; | |
238 | cnt += words, addr += words) { | |
239 | if (cnt + words > ram_words) | |
240 | words = ram_words - cnt; | |
241 | ||
242 | WRT_MAILBOX_REG(ha, reg, 1, LSW(addr)); | |
243 | WRT_MAILBOX_REG(ha, reg, 8, MSW(addr)); | |
244 | ||
245 | WRT_MAILBOX_REG(ha, reg, 2, MSW(dump_dma)); | |
246 | WRT_MAILBOX_REG(ha, reg, 3, LSW(dump_dma)); | |
247 | WRT_MAILBOX_REG(ha, reg, 6, MSW(MSD(dump_dma))); | |
248 | WRT_MAILBOX_REG(ha, reg, 7, LSW(MSD(dump_dma))); | |
249 | ||
250 | WRT_MAILBOX_REG(ha, reg, 4, words); | |
251 | WRT_REG_WORD(®->hccr, HCCR_SET_HOST_INT); | |
252 | ||
253 | for (timer = 6000000; timer; timer--) { | |
254 | /* Check for pending interrupts. */ | |
255 | stat = RD_REG_DWORD(®->u.isp2300.host_status); | |
256 | if (stat & HSR_RISC_INT) { | |
257 | stat &= 0xff; | |
258 | ||
259 | if (stat == 0x1 || stat == 0x2) { | |
260 | set_bit(MBX_INTERRUPT, | |
261 | &ha->mbx_cmd_flags); | |
262 | ||
263 | mb0 = RD_MAILBOX_REG(ha, reg, 0); | |
264 | ||
265 | /* Release mailbox registers. */ | |
266 | WRT_REG_WORD(®->semaphore, 0); | |
267 | WRT_REG_WORD(®->hccr, | |
268 | HCCR_CLR_RISC_INT); | |
269 | RD_REG_WORD(®->hccr); | |
270 | break; | |
271 | } else if (stat == 0x10 || stat == 0x11) { | |
272 | set_bit(MBX_INTERRUPT, | |
273 | &ha->mbx_cmd_flags); | |
274 | ||
275 | mb0 = RD_MAILBOX_REG(ha, reg, 0); | |
276 | ||
277 | WRT_REG_WORD(®->hccr, | |
278 | HCCR_CLR_RISC_INT); | |
279 | RD_REG_WORD(®->hccr); | |
280 | break; | |
281 | } | |
282 | ||
283 | /* clear this intr; it wasn't a mailbox intr */ | |
284 | WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT); | |
285 | RD_REG_WORD(®->hccr); | |
286 | } | |
287 | udelay(5); | |
288 | } | |
289 | ||
290 | if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { | |
291 | rval = mb0 & MBS_MASK; | |
292 | for (idx = 0; idx < words; idx++) | |
293 | ram[cnt + idx] = swab16(dump[idx]); | |
294 | } else { | |
295 | rval = QLA_FUNCTION_FAILED; | |
296 | } | |
297 | } | |
298 | ||
299 | *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL; | |
300 | return rval; | |
301 | } | |
302 | ||
c81d04c9 AV |
303 | static inline void |
304 | qla2xxx_read_window(struct device_reg_2xxx __iomem *reg, uint32_t count, | |
305 | uint16_t *buf) | |
306 | { | |
307 | uint16_t __iomem *dmp_reg = ®->u.isp2300.fb_cmd; | |
308 | ||
309 | while (count--) | |
310 | *buf++ = htons(RD_REG_WORD(dmp_reg++)); | |
311 | } | |
312 | ||
1da177e4 LT |
313 | /** |
314 | * qla2300_fw_dump() - Dumps binary data from the 2300 firmware. | |
315 | * @ha: HA context | |
316 | * @hardware_locked: Called with the hardware_lock | |
317 | */ | |
318 | void | |
7b867cf7 | 319 | qla2300_fw_dump(scsi_qla_host_t *vha, int hardware_locked) |
1da177e4 LT |
320 | { |
321 | int rval; | |
c5722708 | 322 | uint32_t cnt; |
7b867cf7 | 323 | struct qla_hw_data *ha = vha->hw; |
3d71644c | 324 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
1da177e4 LT |
325 | uint16_t __iomem *dmp_reg; |
326 | unsigned long flags; | |
327 | struct qla2300_fw_dump *fw; | |
c5722708 | 328 | void *nxt; |
73208dfd | 329 | struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); |
1da177e4 | 330 | |
1da177e4 LT |
331 | flags = 0; |
332 | ||
333 | if (!hardware_locked) | |
334 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
335 | ||
d4e3e04d | 336 | if (!ha->fw_dump) { |
1da177e4 | 337 | qla_printk(KERN_WARNING, ha, |
d4e3e04d | 338 | "No buffer available for dump!!!\n"); |
1da177e4 LT |
339 | goto qla2300_fw_dump_failed; |
340 | } | |
341 | ||
d4e3e04d | 342 | if (ha->fw_dumped) { |
1da177e4 | 343 | qla_printk(KERN_WARNING, ha, |
d4e3e04d AV |
344 | "Firmware has been previously dumped (%p) -- ignoring " |
345 | "request...\n", ha->fw_dump); | |
1da177e4 LT |
346 | goto qla2300_fw_dump_failed; |
347 | } | |
a7a167bf AV |
348 | fw = &ha->fw_dump->isp.isp23; |
349 | qla2xxx_prep_dump(ha, ha->fw_dump); | |
1da177e4 LT |
350 | |
351 | rval = QLA_SUCCESS; | |
a7a167bf | 352 | fw->hccr = htons(RD_REG_WORD(®->hccr)); |
1da177e4 LT |
353 | |
354 | /* Pause RISC. */ | |
fa2a1ce5 | 355 | WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); |
1da177e4 LT |
356 | if (IS_QLA2300(ha)) { |
357 | for (cnt = 30000; | |
358 | (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 && | |
359 | rval == QLA_SUCCESS; cnt--) { | |
360 | if (cnt) | |
361 | udelay(100); | |
362 | else | |
363 | rval = QLA_FUNCTION_TIMEOUT; | |
364 | } | |
365 | } else { | |
366 | RD_REG_WORD(®->hccr); /* PCI Posting. */ | |
367 | udelay(10); | |
368 | } | |
369 | ||
370 | if (rval == QLA_SUCCESS) { | |
c81d04c9 | 371 | dmp_reg = ®->flash_address; |
fa2a1ce5 | 372 | for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++) |
a7a167bf | 373 | fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 | 374 | |
c81d04c9 | 375 | dmp_reg = ®->u.isp2300.req_q_in; |
fa2a1ce5 | 376 | for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2; cnt++) |
a7a167bf | 377 | fw->risc_host_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 | 378 | |
c81d04c9 | 379 | dmp_reg = ®->u.isp2300.mailbox0; |
fa2a1ce5 | 380 | for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) |
a7a167bf | 381 | fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 LT |
382 | |
383 | WRT_REG_WORD(®->ctrl_status, 0x40); | |
c81d04c9 | 384 | qla2xxx_read_window(reg, 32, fw->resp_dma_reg); |
1da177e4 LT |
385 | |
386 | WRT_REG_WORD(®->ctrl_status, 0x50); | |
c81d04c9 | 387 | qla2xxx_read_window(reg, 48, fw->dma_reg); |
1da177e4 LT |
388 | |
389 | WRT_REG_WORD(®->ctrl_status, 0x00); | |
c81d04c9 | 390 | dmp_reg = ®->risc_hw; |
fa2a1ce5 | 391 | for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++) |
a7a167bf | 392 | fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 | 393 | |
fa2a1ce5 | 394 | WRT_REG_WORD(®->pcr, 0x2000); |
c81d04c9 | 395 | qla2xxx_read_window(reg, 16, fw->risc_gp0_reg); |
1da177e4 | 396 | |
fa2a1ce5 | 397 | WRT_REG_WORD(®->pcr, 0x2200); |
c81d04c9 | 398 | qla2xxx_read_window(reg, 16, fw->risc_gp1_reg); |
1da177e4 | 399 | |
fa2a1ce5 | 400 | WRT_REG_WORD(®->pcr, 0x2400); |
c81d04c9 | 401 | qla2xxx_read_window(reg, 16, fw->risc_gp2_reg); |
1da177e4 | 402 | |
fa2a1ce5 | 403 | WRT_REG_WORD(®->pcr, 0x2600); |
c81d04c9 | 404 | qla2xxx_read_window(reg, 16, fw->risc_gp3_reg); |
1da177e4 | 405 | |
fa2a1ce5 | 406 | WRT_REG_WORD(®->pcr, 0x2800); |
c81d04c9 | 407 | qla2xxx_read_window(reg, 16, fw->risc_gp4_reg); |
1da177e4 | 408 | |
fa2a1ce5 | 409 | WRT_REG_WORD(®->pcr, 0x2A00); |
c81d04c9 | 410 | qla2xxx_read_window(reg, 16, fw->risc_gp5_reg); |
1da177e4 | 411 | |
fa2a1ce5 | 412 | WRT_REG_WORD(®->pcr, 0x2C00); |
c81d04c9 | 413 | qla2xxx_read_window(reg, 16, fw->risc_gp6_reg); |
1da177e4 | 414 | |
fa2a1ce5 | 415 | WRT_REG_WORD(®->pcr, 0x2E00); |
c81d04c9 | 416 | qla2xxx_read_window(reg, 16, fw->risc_gp7_reg); |
1da177e4 | 417 | |
fa2a1ce5 | 418 | WRT_REG_WORD(®->ctrl_status, 0x10); |
c81d04c9 | 419 | qla2xxx_read_window(reg, 64, fw->frame_buf_hdw_reg); |
1da177e4 | 420 | |
fa2a1ce5 | 421 | WRT_REG_WORD(®->ctrl_status, 0x20); |
c81d04c9 | 422 | qla2xxx_read_window(reg, 64, fw->fpm_b0_reg); |
1da177e4 | 423 | |
fa2a1ce5 | 424 | WRT_REG_WORD(®->ctrl_status, 0x30); |
c81d04c9 | 425 | qla2xxx_read_window(reg, 64, fw->fpm_b1_reg); |
1da177e4 LT |
426 | |
427 | /* Reset RISC. */ | |
428 | WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET); | |
429 | for (cnt = 0; cnt < 30000; cnt++) { | |
430 | if ((RD_REG_WORD(®->ctrl_status) & | |
431 | CSR_ISP_SOFT_RESET) == 0) | |
432 | break; | |
433 | ||
434 | udelay(10); | |
435 | } | |
436 | } | |
437 | ||
438 | if (!IS_QLA2300(ha)) { | |
439 | for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 && | |
440 | rval == QLA_SUCCESS; cnt--) { | |
441 | if (cnt) | |
442 | udelay(100); | |
443 | else | |
444 | rval = QLA_FUNCTION_TIMEOUT; | |
445 | } | |
446 | } | |
447 | ||
c5722708 AV |
448 | /* Get RISC SRAM. */ |
449 | if (rval == QLA_SUCCESS) | |
450 | rval = qla2xxx_dump_ram(ha, 0x800, fw->risc_ram, | |
451 | sizeof(fw->risc_ram) / 2, &nxt); | |
1da177e4 | 452 | |
c5722708 AV |
453 | /* Get stack SRAM. */ |
454 | if (rval == QLA_SUCCESS) | |
455 | rval = qla2xxx_dump_ram(ha, 0x10000, fw->stack_ram, | |
456 | sizeof(fw->stack_ram) / 2, &nxt); | |
1da177e4 | 457 | |
c5722708 AV |
458 | /* Get data SRAM. */ |
459 | if (rval == QLA_SUCCESS) | |
460 | rval = qla2xxx_dump_ram(ha, 0x11000, fw->data_ram, | |
461 | ha->fw_memory_size - 0x11000 + 1, &nxt); | |
1da177e4 | 462 | |
a7a167bf | 463 | if (rval == QLA_SUCCESS) |
73208dfd | 464 | qla2xxx_copy_queues(ha, nxt); |
a7a167bf | 465 | |
1da177e4 LT |
466 | if (rval != QLA_SUCCESS) { |
467 | qla_printk(KERN_WARNING, ha, | |
468 | "Failed to dump firmware (%x)!!!\n", rval); | |
d4e3e04d | 469 | ha->fw_dumped = 0; |
1da177e4 | 470 | |
1da177e4 LT |
471 | } else { |
472 | qla_printk(KERN_INFO, ha, | |
473 | "Firmware dump saved to temp buffer (%ld/%p).\n", | |
73208dfd | 474 | base_vha->host_no, ha->fw_dump); |
d4e3e04d | 475 | ha->fw_dumped = 1; |
1da177e4 LT |
476 | } |
477 | ||
478 | qla2300_fw_dump_failed: | |
479 | if (!hardware_locked) | |
480 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
481 | } | |
482 | ||
1da177e4 LT |
483 | /** |
484 | * qla2100_fw_dump() - Dumps binary data from the 2100/2200 firmware. | |
485 | * @ha: HA context | |
486 | * @hardware_locked: Called with the hardware_lock | |
487 | */ | |
488 | void | |
7b867cf7 | 489 | qla2100_fw_dump(scsi_qla_host_t *vha, int hardware_locked) |
1da177e4 LT |
490 | { |
491 | int rval; | |
492 | uint32_t cnt, timer; | |
493 | uint16_t risc_address; | |
494 | uint16_t mb0, mb2; | |
7b867cf7 | 495 | struct qla_hw_data *ha = vha->hw; |
3d71644c | 496 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
1da177e4 LT |
497 | uint16_t __iomem *dmp_reg; |
498 | unsigned long flags; | |
499 | struct qla2100_fw_dump *fw; | |
73208dfd | 500 | struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); |
1da177e4 LT |
501 | |
502 | risc_address = 0; | |
503 | mb0 = mb2 = 0; | |
504 | flags = 0; | |
505 | ||
506 | if (!hardware_locked) | |
507 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
508 | ||
d4e3e04d | 509 | if (!ha->fw_dump) { |
1da177e4 | 510 | qla_printk(KERN_WARNING, ha, |
d4e3e04d | 511 | "No buffer available for dump!!!\n"); |
1da177e4 LT |
512 | goto qla2100_fw_dump_failed; |
513 | } | |
514 | ||
d4e3e04d | 515 | if (ha->fw_dumped) { |
1da177e4 | 516 | qla_printk(KERN_WARNING, ha, |
d4e3e04d AV |
517 | "Firmware has been previously dumped (%p) -- ignoring " |
518 | "request...\n", ha->fw_dump); | |
1da177e4 LT |
519 | goto qla2100_fw_dump_failed; |
520 | } | |
a7a167bf AV |
521 | fw = &ha->fw_dump->isp.isp21; |
522 | qla2xxx_prep_dump(ha, ha->fw_dump); | |
1da177e4 LT |
523 | |
524 | rval = QLA_SUCCESS; | |
a7a167bf | 525 | fw->hccr = htons(RD_REG_WORD(®->hccr)); |
1da177e4 LT |
526 | |
527 | /* Pause RISC. */ | |
fa2a1ce5 | 528 | WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); |
1da177e4 LT |
529 | for (cnt = 30000; (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 && |
530 | rval == QLA_SUCCESS; cnt--) { | |
531 | if (cnt) | |
532 | udelay(100); | |
533 | else | |
534 | rval = QLA_FUNCTION_TIMEOUT; | |
535 | } | |
536 | if (rval == QLA_SUCCESS) { | |
c81d04c9 | 537 | dmp_reg = ®->flash_address; |
fa2a1ce5 | 538 | for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++) |
a7a167bf | 539 | fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 | 540 | |
c81d04c9 | 541 | dmp_reg = ®->u.isp2100.mailbox0; |
1da177e4 | 542 | for (cnt = 0; cnt < ha->mbx_count; cnt++) { |
c81d04c9 AV |
543 | if (cnt == 8) |
544 | dmp_reg = ®->u_end.isp2200.mailbox8; | |
545 | ||
a7a167bf | 546 | fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 LT |
547 | } |
548 | ||
c81d04c9 | 549 | dmp_reg = ®->u.isp2100.unused_2[0]; |
fa2a1ce5 | 550 | for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++) |
a7a167bf | 551 | fw->dma_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 LT |
552 | |
553 | WRT_REG_WORD(®->ctrl_status, 0x00); | |
c81d04c9 | 554 | dmp_reg = ®->risc_hw; |
fa2a1ce5 | 555 | for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++) |
a7a167bf | 556 | fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 | 557 | |
fa2a1ce5 | 558 | WRT_REG_WORD(®->pcr, 0x2000); |
c81d04c9 | 559 | qla2xxx_read_window(reg, 16, fw->risc_gp0_reg); |
1da177e4 | 560 | |
fa2a1ce5 | 561 | WRT_REG_WORD(®->pcr, 0x2100); |
c81d04c9 | 562 | qla2xxx_read_window(reg, 16, fw->risc_gp1_reg); |
1da177e4 | 563 | |
fa2a1ce5 | 564 | WRT_REG_WORD(®->pcr, 0x2200); |
c81d04c9 | 565 | qla2xxx_read_window(reg, 16, fw->risc_gp2_reg); |
1da177e4 | 566 | |
fa2a1ce5 | 567 | WRT_REG_WORD(®->pcr, 0x2300); |
c81d04c9 | 568 | qla2xxx_read_window(reg, 16, fw->risc_gp3_reg); |
1da177e4 | 569 | |
fa2a1ce5 | 570 | WRT_REG_WORD(®->pcr, 0x2400); |
c81d04c9 | 571 | qla2xxx_read_window(reg, 16, fw->risc_gp4_reg); |
1da177e4 | 572 | |
fa2a1ce5 | 573 | WRT_REG_WORD(®->pcr, 0x2500); |
c81d04c9 | 574 | qla2xxx_read_window(reg, 16, fw->risc_gp5_reg); |
1da177e4 | 575 | |
fa2a1ce5 | 576 | WRT_REG_WORD(®->pcr, 0x2600); |
c81d04c9 | 577 | qla2xxx_read_window(reg, 16, fw->risc_gp6_reg); |
1da177e4 | 578 | |
fa2a1ce5 | 579 | WRT_REG_WORD(®->pcr, 0x2700); |
c81d04c9 | 580 | qla2xxx_read_window(reg, 16, fw->risc_gp7_reg); |
1da177e4 | 581 | |
fa2a1ce5 | 582 | WRT_REG_WORD(®->ctrl_status, 0x10); |
c81d04c9 | 583 | qla2xxx_read_window(reg, 16, fw->frame_buf_hdw_reg); |
1da177e4 | 584 | |
fa2a1ce5 | 585 | WRT_REG_WORD(®->ctrl_status, 0x20); |
c81d04c9 | 586 | qla2xxx_read_window(reg, 64, fw->fpm_b0_reg); |
1da177e4 | 587 | |
fa2a1ce5 | 588 | WRT_REG_WORD(®->ctrl_status, 0x30); |
c81d04c9 | 589 | qla2xxx_read_window(reg, 64, fw->fpm_b1_reg); |
1da177e4 LT |
590 | |
591 | /* Reset the ISP. */ | |
592 | WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET); | |
593 | } | |
594 | ||
595 | for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 && | |
596 | rval == QLA_SUCCESS; cnt--) { | |
597 | if (cnt) | |
598 | udelay(100); | |
599 | else | |
600 | rval = QLA_FUNCTION_TIMEOUT; | |
601 | } | |
602 | ||
603 | /* Pause RISC. */ | |
604 | if (rval == QLA_SUCCESS && (IS_QLA2200(ha) || (IS_QLA2100(ha) && | |
605 | (RD_REG_WORD(®->mctr) & (BIT_1 | BIT_0)) != 0))) { | |
606 | ||
fa2a1ce5 | 607 | WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); |
1da177e4 LT |
608 | for (cnt = 30000; |
609 | (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 && | |
610 | rval == QLA_SUCCESS; cnt--) { | |
611 | if (cnt) | |
612 | udelay(100); | |
613 | else | |
614 | rval = QLA_FUNCTION_TIMEOUT; | |
615 | } | |
616 | if (rval == QLA_SUCCESS) { | |
617 | /* Set memory configuration and timing. */ | |
618 | if (IS_QLA2100(ha)) | |
619 | WRT_REG_WORD(®->mctr, 0xf1); | |
620 | else | |
621 | WRT_REG_WORD(®->mctr, 0xf2); | |
622 | RD_REG_WORD(®->mctr); /* PCI Posting. */ | |
623 | ||
624 | /* Release RISC. */ | |
625 | WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC); | |
626 | } | |
627 | } | |
628 | ||
629 | if (rval == QLA_SUCCESS) { | |
630 | /* Get RISC SRAM. */ | |
631 | risc_address = 0x1000; | |
632 | WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD); | |
633 | clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); | |
634 | } | |
635 | for (cnt = 0; cnt < sizeof(fw->risc_ram) / 2 && rval == QLA_SUCCESS; | |
636 | cnt++, risc_address++) { | |
637 | WRT_MAILBOX_REG(ha, reg, 1, risc_address); | |
638 | WRT_REG_WORD(®->hccr, HCCR_SET_HOST_INT); | |
639 | ||
640 | for (timer = 6000000; timer != 0; timer--) { | |
641 | /* Check for pending interrupts. */ | |
642 | if (RD_REG_WORD(®->istatus) & ISR_RISC_INT) { | |
643 | if (RD_REG_WORD(®->semaphore) & BIT_0) { | |
644 | set_bit(MBX_INTERRUPT, | |
645 | &ha->mbx_cmd_flags); | |
646 | ||
647 | mb0 = RD_MAILBOX_REG(ha, reg, 0); | |
648 | mb2 = RD_MAILBOX_REG(ha, reg, 2); | |
649 | ||
650 | WRT_REG_WORD(®->semaphore, 0); | |
651 | WRT_REG_WORD(®->hccr, | |
652 | HCCR_CLR_RISC_INT); | |
653 | RD_REG_WORD(®->hccr); | |
654 | break; | |
655 | } | |
656 | WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT); | |
657 | RD_REG_WORD(®->hccr); | |
658 | } | |
659 | udelay(5); | |
660 | } | |
661 | ||
662 | if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { | |
663 | rval = mb0 & MBS_MASK; | |
a7a167bf | 664 | fw->risc_ram[cnt] = htons(mb2); |
1da177e4 LT |
665 | } else { |
666 | rval = QLA_FUNCTION_FAILED; | |
667 | } | |
668 | } | |
669 | ||
a7a167bf | 670 | if (rval == QLA_SUCCESS) |
73208dfd | 671 | qla2xxx_copy_queues(ha, &fw->risc_ram[cnt]); |
a7a167bf | 672 | |
1da177e4 LT |
673 | if (rval != QLA_SUCCESS) { |
674 | qla_printk(KERN_WARNING, ha, | |
675 | "Failed to dump firmware (%x)!!!\n", rval); | |
d4e3e04d | 676 | ha->fw_dumped = 0; |
1da177e4 | 677 | |
1da177e4 LT |
678 | } else { |
679 | qla_printk(KERN_INFO, ha, | |
680 | "Firmware dump saved to temp buffer (%ld/%p).\n", | |
73208dfd | 681 | base_vha->host_no, ha->fw_dump); |
d4e3e04d | 682 | ha->fw_dumped = 1; |
1da177e4 LT |
683 | } |
684 | ||
685 | qla2100_fw_dump_failed: | |
686 | if (!hardware_locked) | |
687 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
688 | } | |
689 | ||
6d9b61ed | 690 | void |
7b867cf7 | 691 | qla24xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) |
6d9b61ed AV |
692 | { |
693 | int rval; | |
c3a2f0df | 694 | uint32_t cnt; |
6d9b61ed | 695 | uint32_t risc_address; |
7b867cf7 | 696 | struct qla_hw_data *ha = vha->hw; |
6d9b61ed AV |
697 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; |
698 | uint32_t __iomem *dmp_reg; | |
699 | uint32_t *iter_reg; | |
700 | uint16_t __iomem *mbx_reg; | |
701 | unsigned long flags; | |
702 | struct qla24xx_fw_dump *fw; | |
703 | uint32_t ext_mem_cnt; | |
c3a2f0df | 704 | void *nxt; |
73208dfd | 705 | struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); |
6d9b61ed AV |
706 | |
707 | risc_address = ext_mem_cnt = 0; | |
6d9b61ed AV |
708 | flags = 0; |
709 | ||
710 | if (!hardware_locked) | |
711 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
712 | ||
d4e3e04d | 713 | if (!ha->fw_dump) { |
6d9b61ed AV |
714 | qla_printk(KERN_WARNING, ha, |
715 | "No buffer available for dump!!!\n"); | |
716 | goto qla24xx_fw_dump_failed; | |
717 | } | |
718 | ||
719 | if (ha->fw_dumped) { | |
720 | qla_printk(KERN_WARNING, ha, | |
721 | "Firmware has been previously dumped (%p) -- ignoring " | |
d4e3e04d | 722 | "request...\n", ha->fw_dump); |
6d9b61ed AV |
723 | goto qla24xx_fw_dump_failed; |
724 | } | |
a7a167bf AV |
725 | fw = &ha->fw_dump->isp.isp24; |
726 | qla2xxx_prep_dump(ha, ha->fw_dump); | |
6d9b61ed | 727 | |
a7a167bf | 728 | fw->host_status = htonl(RD_REG_DWORD(®->host_status)); |
6d9b61ed AV |
729 | |
730 | /* Pause RISC. */ | |
c81d04c9 AV |
731 | rval = qla24xx_pause_risc(reg); |
732 | if (rval != QLA_SUCCESS) | |
733 | goto qla24xx_fw_dump_failed_0; | |
734 | ||
735 | /* Host interface registers. */ | |
736 | dmp_reg = ®->flash_addr; | |
737 | for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) | |
738 | fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); | |
739 | ||
740 | /* Disable interrupts. */ | |
741 | WRT_REG_DWORD(®->ictrl, 0); | |
742 | RD_REG_DWORD(®->ictrl); | |
743 | ||
744 | /* Shadow registers. */ | |
745 | WRT_REG_DWORD(®->iobase_addr, 0x0F70); | |
746 | RD_REG_DWORD(®->iobase_addr); | |
747 | WRT_REG_DWORD(®->iobase_select, 0xB0000000); | |
748 | fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
749 | ||
750 | WRT_REG_DWORD(®->iobase_select, 0xB0100000); | |
751 | fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
752 | ||
753 | WRT_REG_DWORD(®->iobase_select, 0xB0200000); | |
754 | fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
755 | ||
756 | WRT_REG_DWORD(®->iobase_select, 0xB0300000); | |
757 | fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
758 | ||
759 | WRT_REG_DWORD(®->iobase_select, 0xB0400000); | |
760 | fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
761 | ||
762 | WRT_REG_DWORD(®->iobase_select, 0xB0500000); | |
763 | fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
764 | ||
765 | WRT_REG_DWORD(®->iobase_select, 0xB0600000); | |
766 | fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
767 | ||
768 | /* Mailbox registers. */ | |
769 | mbx_reg = ®->mailbox0; | |
770 | for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) | |
771 | fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++)); | |
772 | ||
773 | /* Transfer sequence registers. */ | |
774 | iter_reg = fw->xseq_gp_reg; | |
775 | iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg); | |
776 | iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg); | |
777 | iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg); | |
778 | iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg); | |
779 | iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg); | |
780 | iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg); | |
781 | iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg); | |
782 | qla24xx_read_window(reg, 0xBF70, 16, iter_reg); | |
783 | ||
784 | qla24xx_read_window(reg, 0xBFE0, 16, fw->xseq_0_reg); | |
785 | qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg); | |
786 | ||
787 | /* Receive sequence registers. */ | |
788 | iter_reg = fw->rseq_gp_reg; | |
789 | iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg); | |
790 | iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg); | |
791 | iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg); | |
792 | iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg); | |
793 | iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg); | |
794 | iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg); | |
795 | iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg); | |
796 | qla24xx_read_window(reg, 0xFF70, 16, iter_reg); | |
797 | ||
798 | qla24xx_read_window(reg, 0xFFD0, 16, fw->rseq_0_reg); | |
799 | qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg); | |
800 | qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg); | |
801 | ||
802 | /* Command DMA registers. */ | |
803 | qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg); | |
804 | ||
805 | /* Queues. */ | |
806 | iter_reg = fw->req0_dma_reg; | |
807 | iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg); | |
808 | dmp_reg = ®->iobase_q; | |
809 | for (cnt = 0; cnt < 7; cnt++) | |
810 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
811 | ||
812 | iter_reg = fw->resp0_dma_reg; | |
813 | iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg); | |
814 | dmp_reg = ®->iobase_q; | |
815 | for (cnt = 0; cnt < 7; cnt++) | |
816 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
817 | ||
818 | iter_reg = fw->req1_dma_reg; | |
819 | iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg); | |
820 | dmp_reg = ®->iobase_q; | |
821 | for (cnt = 0; cnt < 7; cnt++) | |
822 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
823 | ||
824 | /* Transmit DMA registers. */ | |
825 | iter_reg = fw->xmt0_dma_reg; | |
826 | iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg); | |
827 | qla24xx_read_window(reg, 0x7610, 16, iter_reg); | |
828 | ||
829 | iter_reg = fw->xmt1_dma_reg; | |
830 | iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg); | |
831 | qla24xx_read_window(reg, 0x7630, 16, iter_reg); | |
832 | ||
833 | iter_reg = fw->xmt2_dma_reg; | |
834 | iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg); | |
835 | qla24xx_read_window(reg, 0x7650, 16, iter_reg); | |
836 | ||
837 | iter_reg = fw->xmt3_dma_reg; | |
838 | iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg); | |
839 | qla24xx_read_window(reg, 0x7670, 16, iter_reg); | |
840 | ||
841 | iter_reg = fw->xmt4_dma_reg; | |
842 | iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg); | |
843 | qla24xx_read_window(reg, 0x7690, 16, iter_reg); | |
844 | ||
845 | qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg); | |
846 | ||
847 | /* Receive DMA registers. */ | |
848 | iter_reg = fw->rcvt0_data_dma_reg; | |
849 | iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg); | |
850 | qla24xx_read_window(reg, 0x7710, 16, iter_reg); | |
851 | ||
852 | iter_reg = fw->rcvt1_data_dma_reg; | |
853 | iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg); | |
854 | qla24xx_read_window(reg, 0x7730, 16, iter_reg); | |
855 | ||
856 | /* RISC registers. */ | |
857 | iter_reg = fw->risc_gp_reg; | |
858 | iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg); | |
859 | iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg); | |
860 | iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg); | |
861 | iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg); | |
862 | iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg); | |
863 | iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg); | |
864 | iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg); | |
865 | qla24xx_read_window(reg, 0x0F70, 16, iter_reg); | |
866 | ||
867 | /* Local memory controller registers. */ | |
868 | iter_reg = fw->lmc_reg; | |
869 | iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg); | |
870 | iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg); | |
871 | iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg); | |
872 | iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg); | |
873 | iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg); | |
874 | iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg); | |
875 | qla24xx_read_window(reg, 0x3060, 16, iter_reg); | |
876 | ||
877 | /* Fibre Protocol Module registers. */ | |
878 | iter_reg = fw->fpm_hdw_reg; | |
879 | iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg); | |
880 | iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg); | |
881 | iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg); | |
882 | iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg); | |
883 | iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg); | |
884 | iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg); | |
885 | iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg); | |
886 | iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg); | |
887 | iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg); | |
888 | iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg); | |
889 | iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg); | |
890 | qla24xx_read_window(reg, 0x40B0, 16, iter_reg); | |
891 | ||
892 | /* Frame Buffer registers. */ | |
893 | iter_reg = fw->fb_hdw_reg; | |
894 | iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg); | |
895 | iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg); | |
896 | iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg); | |
897 | iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg); | |
898 | iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg); | |
899 | iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg); | |
900 | iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg); | |
901 | iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg); | |
902 | iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg); | |
903 | iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg); | |
904 | qla24xx_read_window(reg, 0x61B0, 16, iter_reg); | |
905 | ||
906 | rval = qla24xx_soft_reset(ha); | |
907 | if (rval != QLA_SUCCESS) | |
908 | goto qla24xx_fw_dump_failed_0; | |
909 | ||
910 | rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram), | |
c5722708 | 911 | &nxt); |
c81d04c9 AV |
912 | if (rval != QLA_SUCCESS) |
913 | goto qla24xx_fw_dump_failed_0; | |
914 | ||
73208dfd | 915 | nxt = qla2xxx_copy_queues(ha, nxt); |
c81d04c9 AV |
916 | if (ha->eft) |
917 | memcpy(nxt, ha->eft, ntohl(ha->fw_dump->eft_size)); | |
918 | ||
919 | qla24xx_fw_dump_failed_0: | |
c3a2f0df AV |
920 | if (rval != QLA_SUCCESS) { |
921 | qla_printk(KERN_WARNING, ha, | |
922 | "Failed to dump firmware (%x)!!!\n", rval); | |
923 | ha->fw_dumped = 0; | |
6d9b61ed | 924 | |
c3a2f0df AV |
925 | } else { |
926 | qla_printk(KERN_INFO, ha, | |
927 | "Firmware dump saved to temp buffer (%ld/%p).\n", | |
73208dfd | 928 | base_vha->host_no, ha->fw_dump); |
c3a2f0df AV |
929 | ha->fw_dumped = 1; |
930 | } | |
6d9b61ed | 931 | |
c3a2f0df AV |
932 | qla24xx_fw_dump_failed: |
933 | if (!hardware_locked) | |
934 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
935 | } | |
6d9b61ed | 936 | |
c3a2f0df | 937 | void |
7b867cf7 | 938 | qla25xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) |
c3a2f0df AV |
939 | { |
940 | int rval; | |
941 | uint32_t cnt; | |
942 | uint32_t risc_address; | |
7b867cf7 | 943 | struct qla_hw_data *ha = vha->hw; |
c3a2f0df | 944 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; |
73208dfd | 945 | struct device_reg_25xxmq __iomem *reg25; |
c3a2f0df AV |
946 | uint32_t __iomem *dmp_reg; |
947 | uint32_t *iter_reg; | |
948 | uint16_t __iomem *mbx_reg; | |
949 | unsigned long flags; | |
950 | struct qla25xx_fw_dump *fw; | |
951 | uint32_t ext_mem_cnt; | |
952 | void *nxt; | |
df613b96 | 953 | struct qla2xxx_fce_chain *fcec; |
73208dfd AC |
954 | struct qla2xxx_mq_chain *mq = NULL; |
955 | uint32_t qreg_size; | |
956 | uint8_t req_cnt, rsp_cnt, que_cnt; | |
957 | uint32_t que_idx; | |
958 | struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); | |
6d9b61ed | 959 | |
c3a2f0df AV |
960 | risc_address = ext_mem_cnt = 0; |
961 | flags = 0; | |
6d9b61ed | 962 | |
c3a2f0df AV |
963 | if (!hardware_locked) |
964 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
6d9b61ed | 965 | |
c3a2f0df AV |
966 | if (!ha->fw_dump) { |
967 | qla_printk(KERN_WARNING, ha, | |
968 | "No buffer available for dump!!!\n"); | |
969 | goto qla25xx_fw_dump_failed; | |
970 | } | |
6d9b61ed | 971 | |
c3a2f0df AV |
972 | if (ha->fw_dumped) { |
973 | qla_printk(KERN_WARNING, ha, | |
974 | "Firmware has been previously dumped (%p) -- ignoring " | |
975 | "request...\n", ha->fw_dump); | |
976 | goto qla25xx_fw_dump_failed; | |
977 | } | |
978 | fw = &ha->fw_dump->isp.isp25; | |
979 | qla2xxx_prep_dump(ha, ha->fw_dump); | |
b5836927 | 980 | ha->fw_dump->version = __constant_htonl(2); |
6d9b61ed | 981 | |
c3a2f0df | 982 | fw->host_status = htonl(RD_REG_DWORD(®->host_status)); |
6d9b61ed | 983 | |
c3a2f0df | 984 | /* Pause RISC. */ |
c81d04c9 AV |
985 | rval = qla24xx_pause_risc(reg); |
986 | if (rval != QLA_SUCCESS) | |
987 | goto qla25xx_fw_dump_failed_0; | |
988 | ||
b5836927 AV |
989 | /* Host/Risc registers. */ |
990 | iter_reg = fw->host_risc_reg; | |
991 | iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg); | |
992 | qla24xx_read_window(reg, 0x7010, 16, iter_reg); | |
993 | ||
994 | /* PCIe registers. */ | |
995 | WRT_REG_DWORD(®->iobase_addr, 0x7C00); | |
996 | RD_REG_DWORD(®->iobase_addr); | |
997 | WRT_REG_DWORD(®->iobase_window, 0x01); | |
998 | dmp_reg = ®->iobase_c4; | |
999 | fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++)); | |
1000 | fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++)); | |
1001 | fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg)); | |
1002 | fw->pcie_regs[3] = htonl(RD_REG_DWORD(®->iobase_window)); | |
73208dfd AC |
1003 | |
1004 | /* Multi queue registers */ | |
1005 | if (ha->mqenable) { | |
1006 | qreg_size = sizeof(struct qla2xxx_mq_chain); | |
1007 | mq = kzalloc(qreg_size, GFP_KERNEL); | |
1008 | if (!mq) | |
1009 | goto qla25xx_fw_dump_failed_0; | |
1010 | req_cnt = find_first_zero_bit(ha->req_qid_map, ha->max_queues); | |
1011 | rsp_cnt = find_first_zero_bit(ha->rsp_qid_map, ha->max_queues); | |
1012 | que_cnt = req_cnt > rsp_cnt ? req_cnt : rsp_cnt; | |
1013 | mq->count = htonl(que_cnt); | |
1014 | mq->chain_size = htonl(qreg_size); | |
1015 | mq->type = __constant_htonl(DUMP_CHAIN_MQ); | |
1016 | for (cnt = 0; cnt < que_cnt; cnt++) { | |
1017 | reg25 = (struct device_reg_25xxmq *) ((void *) | |
1018 | ha->mqiobase + cnt * QLA_QUE_PAGE); | |
1019 | que_idx = cnt * 4; | |
1020 | mq->qregs[que_idx] = htonl(reg25->req_q_in); | |
1021 | mq->qregs[que_idx+1] = htonl(reg25->req_q_out); | |
1022 | mq->qregs[que_idx+2] = htonl(reg25->rsp_q_in); | |
1023 | mq->qregs[que_idx+3] = htonl(reg25->rsp_q_out); | |
1024 | } | |
1025 | } | |
b5836927 AV |
1026 | WRT_REG_DWORD(®->iobase_window, 0x00); |
1027 | RD_REG_DWORD(®->iobase_window); | |
1028 | ||
c81d04c9 AV |
1029 | /* Host interface registers. */ |
1030 | dmp_reg = ®->flash_addr; | |
1031 | for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) | |
1032 | fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); | |
1033 | ||
1034 | /* Disable interrupts. */ | |
1035 | WRT_REG_DWORD(®->ictrl, 0); | |
1036 | RD_REG_DWORD(®->ictrl); | |
1037 | ||
1038 | /* Shadow registers. */ | |
1039 | WRT_REG_DWORD(®->iobase_addr, 0x0F70); | |
1040 | RD_REG_DWORD(®->iobase_addr); | |
1041 | WRT_REG_DWORD(®->iobase_select, 0xB0000000); | |
1042 | fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1043 | ||
1044 | WRT_REG_DWORD(®->iobase_select, 0xB0100000); | |
1045 | fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1046 | ||
1047 | WRT_REG_DWORD(®->iobase_select, 0xB0200000); | |
1048 | fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1049 | ||
1050 | WRT_REG_DWORD(®->iobase_select, 0xB0300000); | |
1051 | fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1052 | ||
1053 | WRT_REG_DWORD(®->iobase_select, 0xB0400000); | |
1054 | fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1055 | ||
1056 | WRT_REG_DWORD(®->iobase_select, 0xB0500000); | |
1057 | fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1058 | ||
1059 | WRT_REG_DWORD(®->iobase_select, 0xB0600000); | |
1060 | fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1061 | ||
1062 | WRT_REG_DWORD(®->iobase_select, 0xB0700000); | |
1063 | fw->shadow_reg[7] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1064 | ||
1065 | WRT_REG_DWORD(®->iobase_select, 0xB0800000); | |
1066 | fw->shadow_reg[8] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1067 | ||
1068 | WRT_REG_DWORD(®->iobase_select, 0xB0900000); | |
1069 | fw->shadow_reg[9] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1070 | ||
1071 | WRT_REG_DWORD(®->iobase_select, 0xB0A00000); | |
1072 | fw->shadow_reg[10] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1073 | ||
1074 | /* RISC I/O register. */ | |
1075 | WRT_REG_DWORD(®->iobase_addr, 0x0010); | |
1076 | fw->risc_io_reg = htonl(RD_REG_DWORD(®->iobase_window)); | |
1077 | ||
1078 | /* Mailbox registers. */ | |
1079 | mbx_reg = ®->mailbox0; | |
1080 | for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) | |
1081 | fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++)); | |
1082 | ||
1083 | /* Transfer sequence registers. */ | |
1084 | iter_reg = fw->xseq_gp_reg; | |
1085 | iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg); | |
1086 | iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg); | |
1087 | iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg); | |
1088 | iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg); | |
1089 | iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg); | |
1090 | iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg); | |
1091 | iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg); | |
1092 | qla24xx_read_window(reg, 0xBF70, 16, iter_reg); | |
1093 | ||
1094 | iter_reg = fw->xseq_0_reg; | |
1095 | iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg); | |
1096 | iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg); | |
1097 | qla24xx_read_window(reg, 0xBFE0, 16, iter_reg); | |
1098 | ||
1099 | qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg); | |
1100 | ||
1101 | /* Receive sequence registers. */ | |
1102 | iter_reg = fw->rseq_gp_reg; | |
1103 | iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg); | |
1104 | iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg); | |
1105 | iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg); | |
1106 | iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg); | |
1107 | iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg); | |
1108 | iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg); | |
1109 | iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg); | |
1110 | qla24xx_read_window(reg, 0xFF70, 16, iter_reg); | |
1111 | ||
1112 | iter_reg = fw->rseq_0_reg; | |
1113 | iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg); | |
1114 | qla24xx_read_window(reg, 0xFFD0, 16, iter_reg); | |
1115 | ||
1116 | qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg); | |
1117 | qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg); | |
1118 | ||
1119 | /* Auxiliary sequence registers. */ | |
1120 | iter_reg = fw->aseq_gp_reg; | |
1121 | iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg); | |
1122 | iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg); | |
1123 | iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg); | |
1124 | iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg); | |
1125 | iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg); | |
1126 | iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg); | |
1127 | iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg); | |
1128 | qla24xx_read_window(reg, 0xB070, 16, iter_reg); | |
1129 | ||
1130 | iter_reg = fw->aseq_0_reg; | |
1131 | iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg); | |
1132 | qla24xx_read_window(reg, 0xB0D0, 16, iter_reg); | |
1133 | ||
1134 | qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg); | |
1135 | qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg); | |
1136 | ||
1137 | /* Command DMA registers. */ | |
1138 | qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg); | |
1139 | ||
1140 | /* Queues. */ | |
1141 | iter_reg = fw->req0_dma_reg; | |
1142 | iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg); | |
1143 | dmp_reg = ®->iobase_q; | |
1144 | for (cnt = 0; cnt < 7; cnt++) | |
1145 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1146 | ||
1147 | iter_reg = fw->resp0_dma_reg; | |
1148 | iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg); | |
1149 | dmp_reg = ®->iobase_q; | |
1150 | for (cnt = 0; cnt < 7; cnt++) | |
1151 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1152 | ||
1153 | iter_reg = fw->req1_dma_reg; | |
1154 | iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg); | |
1155 | dmp_reg = ®->iobase_q; | |
1156 | for (cnt = 0; cnt < 7; cnt++) | |
1157 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1158 | ||
1159 | /* Transmit DMA registers. */ | |
1160 | iter_reg = fw->xmt0_dma_reg; | |
1161 | iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg); | |
1162 | qla24xx_read_window(reg, 0x7610, 16, iter_reg); | |
1163 | ||
1164 | iter_reg = fw->xmt1_dma_reg; | |
1165 | iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg); | |
1166 | qla24xx_read_window(reg, 0x7630, 16, iter_reg); | |
1167 | ||
1168 | iter_reg = fw->xmt2_dma_reg; | |
1169 | iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg); | |
1170 | qla24xx_read_window(reg, 0x7650, 16, iter_reg); | |
1171 | ||
1172 | iter_reg = fw->xmt3_dma_reg; | |
1173 | iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg); | |
1174 | qla24xx_read_window(reg, 0x7670, 16, iter_reg); | |
1175 | ||
1176 | iter_reg = fw->xmt4_dma_reg; | |
1177 | iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg); | |
1178 | qla24xx_read_window(reg, 0x7690, 16, iter_reg); | |
1179 | ||
1180 | qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg); | |
1181 | ||
1182 | /* Receive DMA registers. */ | |
1183 | iter_reg = fw->rcvt0_data_dma_reg; | |
1184 | iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg); | |
1185 | qla24xx_read_window(reg, 0x7710, 16, iter_reg); | |
1186 | ||
1187 | iter_reg = fw->rcvt1_data_dma_reg; | |
1188 | iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg); | |
1189 | qla24xx_read_window(reg, 0x7730, 16, iter_reg); | |
1190 | ||
1191 | /* RISC registers. */ | |
1192 | iter_reg = fw->risc_gp_reg; | |
1193 | iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg); | |
1194 | iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg); | |
1195 | iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg); | |
1196 | iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg); | |
1197 | iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg); | |
1198 | iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg); | |
1199 | iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg); | |
1200 | qla24xx_read_window(reg, 0x0F70, 16, iter_reg); | |
1201 | ||
1202 | /* Local memory controller registers. */ | |
1203 | iter_reg = fw->lmc_reg; | |
1204 | iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg); | |
1205 | iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg); | |
1206 | iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg); | |
1207 | iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg); | |
1208 | iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg); | |
1209 | iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg); | |
1210 | iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg); | |
1211 | qla24xx_read_window(reg, 0x3070, 16, iter_reg); | |
1212 | ||
1213 | /* Fibre Protocol Module registers. */ | |
1214 | iter_reg = fw->fpm_hdw_reg; | |
1215 | iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg); | |
1216 | iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg); | |
1217 | iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg); | |
1218 | iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg); | |
1219 | iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg); | |
1220 | iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg); | |
1221 | iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg); | |
1222 | iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg); | |
1223 | iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg); | |
1224 | iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg); | |
1225 | iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg); | |
1226 | qla24xx_read_window(reg, 0x40B0, 16, iter_reg); | |
1227 | ||
1228 | /* Frame Buffer registers. */ | |
1229 | iter_reg = fw->fb_hdw_reg; | |
1230 | iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg); | |
1231 | iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg); | |
1232 | iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg); | |
1233 | iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg); | |
1234 | iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg); | |
1235 | iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg); | |
1236 | iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg); | |
1237 | iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg); | |
1238 | iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg); | |
1239 | iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg); | |
1240 | iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg); | |
1241 | qla24xx_read_window(reg, 0x6F00, 16, iter_reg); | |
1242 | ||
1243 | rval = qla24xx_soft_reset(ha); | |
1244 | if (rval != QLA_SUCCESS) | |
1245 | goto qla25xx_fw_dump_failed_0; | |
1246 | ||
1247 | rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram), | |
c5722708 | 1248 | &nxt); |
c81d04c9 AV |
1249 | if (rval != QLA_SUCCESS) |
1250 | goto qla25xx_fw_dump_failed_0; | |
1251 | ||
df613b96 | 1252 | /* Fibre Channel Trace Buffer. */ |
73208dfd | 1253 | nxt = qla2xxx_copy_queues(ha, nxt); |
c81d04c9 AV |
1254 | if (ha->eft) |
1255 | memcpy(nxt, ha->eft, ntohl(ha->fw_dump->eft_size)); | |
1256 | ||
df613b96 AV |
1257 | /* Fibre Channel Event Buffer. */ |
1258 | if (!ha->fce) | |
1259 | goto qla25xx_fw_dump_failed_0; | |
1260 | ||
1261 | ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT); | |
1262 | ||
73208dfd AC |
1263 | if (ha->mqenable) { |
1264 | nxt = nxt + ntohl(ha->fw_dump->eft_size); | |
1265 | memcpy(nxt, mq, qreg_size); | |
1266 | kfree(mq); | |
1267 | fcec = nxt + qreg_size; | |
1268 | } else { | |
1269 | fcec = nxt + ntohl(ha->fw_dump->eft_size); | |
1270 | } | |
df613b96 AV |
1271 | fcec->type = __constant_htonl(DUMP_CHAIN_FCE | DUMP_CHAIN_LAST); |
1272 | fcec->chain_size = htonl(sizeof(struct qla2xxx_fce_chain) + | |
1273 | fce_calc_size(ha->fce_bufs)); | |
1274 | fcec->size = htonl(fce_calc_size(ha->fce_bufs)); | |
1275 | fcec->addr_l = htonl(LSD(ha->fce_dma)); | |
1276 | fcec->addr_h = htonl(MSD(ha->fce_dma)); | |
1277 | ||
1278 | iter_reg = fcec->eregs; | |
1279 | for (cnt = 0; cnt < 8; cnt++) | |
1280 | *iter_reg++ = htonl(ha->fce_mb[cnt]); | |
1281 | ||
1282 | memcpy(iter_reg, ha->fce, ntohl(fcec->size)); | |
1283 | ||
c81d04c9 | 1284 | qla25xx_fw_dump_failed_0: |
c3a2f0df AV |
1285 | if (rval != QLA_SUCCESS) { |
1286 | qla_printk(KERN_WARNING, ha, | |
1287 | "Failed to dump firmware (%x)!!!\n", rval); | |
1288 | ha->fw_dumped = 0; | |
6d9b61ed AV |
1289 | |
1290 | } else { | |
1291 | qla_printk(KERN_INFO, ha, | |
1292 | "Firmware dump saved to temp buffer (%ld/%p).\n", | |
73208dfd | 1293 | base_vha->host_no, ha->fw_dump); |
6d9b61ed AV |
1294 | ha->fw_dumped = 1; |
1295 | } | |
1296 | ||
c3a2f0df | 1297 | qla25xx_fw_dump_failed: |
6d9b61ed AV |
1298 | if (!hardware_locked) |
1299 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1300 | } | |
1da177e4 LT |
1301 | /****************************************************************************/ |
1302 | /* Driver Debug Functions. */ | |
1303 | /****************************************************************************/ | |
1304 | ||
fa2a1ce5 | 1305 | void |
7b867cf7 | 1306 | qla2x00_dump_regs(scsi_qla_host_t *vha) |
1da177e4 | 1307 | { |
6afd9763 | 1308 | int i; |
7b867cf7 | 1309 | struct qla_hw_data *ha = vha->hw; |
3d71644c | 1310 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
6afd9763 AV |
1311 | struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; |
1312 | uint16_t __iomem *mbx_reg; | |
1313 | ||
1314 | mbx_reg = IS_FWI2_CAPABLE(ha) ? ®24->mailbox0: | |
1315 | MAILBOX_REG(ha, reg, 0); | |
1da177e4 LT |
1316 | |
1317 | printk("Mailbox registers:\n"); | |
6afd9763 | 1318 | for (i = 0; i < 6; i++) |
7b867cf7 | 1319 | printk("scsi(%ld): mbox %d 0x%04x \n", vha->host_no, i, |
6afd9763 | 1320 | RD_REG_WORD(mbx_reg++)); |
1da177e4 LT |
1321 | } |
1322 | ||
1323 | ||
1324 | void | |
fa2a1ce5 | 1325 | qla2x00_dump_buffer(uint8_t * b, uint32_t size) |
1da177e4 LT |
1326 | { |
1327 | uint32_t cnt; | |
1328 | uint8_t c; | |
1329 | ||
1330 | printk(" 0 1 2 3 4 5 6 7 8 9 " | |
1331 | "Ah Bh Ch Dh Eh Fh\n"); | |
1332 | printk("----------------------------------------" | |
1333 | "----------------------\n"); | |
1334 | ||
1335 | for (cnt = 0; cnt < size;) { | |
1336 | c = *b++; | |
1337 | printk("%02x",(uint32_t) c); | |
1338 | cnt++; | |
1339 | if (!(cnt % 16)) | |
1340 | printk("\n"); | |
1341 | else | |
1342 | printk(" "); | |
1343 | } | |
1344 | if (cnt % 16) | |
1345 | printk("\n"); | |
1346 | } | |
73208dfd AC |
1347 | |
1348 |