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[SCSI] qla2xxx: Select correct request queue for error type IOCB for ISPFX00.
[deliverable/linux.git] / drivers / scsi / qla2xxx / qla_init.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
1e63395c 3 * Copyright (c) 2003-2013 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
73208dfd 8#include "qla_gbl.h"
1da177e4
LT		 9
10#include <linux/delay.h>
5a0e3ad6 11#include <linux/slab.h>
0107109e 12#include <linux/vmalloc.h>
1da177e4
LT		 13
14#include "qla_devtbl.h"
15
4e08df3f
DM		 16#ifdef CONFIG_SPARC
17#include <asm/prom.h>
4e08df3f
DM		 18#endif
19
2d70c103
NB		 20#include <target/target_core_base.h>
21#include "qla_target.h"
22
1da177e4
LT		 23/*
24* QLogic ISP2x00 Hardware Support Function Prototypes.
25*/
1da177e4 26static int qla2x00_isp_firmware(scsi_qla_host_t *);
1da177e4 27static int qla2x00_setup_chip(scsi_qla_host_t *);
1da177e4
LT		 28static int qla2x00_fw_ready(scsi_qla_host_t *);
29static int qla2x00_configure_hba(scsi_qla_host_t *);
1da177e4
LT		 30static int qla2x00_configure_loop(scsi_qla_host_t *);
31static int qla2x00_configure_local_loop(scsi_qla_host_t *);
1da177e4
LT		 32static int qla2x00_configure_fabric(scsi_qla_host_t *);
33static int qla2x00_find_all_fabric_devs(scsi_qla_host_t *, struct list_head *);
1da177e4
LT		 34static int qla2x00_fabric_dev_login(scsi_qla_host_t *, fc_port_t *,
35 uint16_t *);
1da177e4
LT		 36
37static int qla2x00_restart_isp(scsi_qla_host_t *);
1da177e4 38
4d4df193
HK		 39static struct qla_chip_state_84xx *qla84xx_get_chip(struct scsi_qla_host *);
40static int qla84xx_init_chip(scsi_qla_host_t *);
73208dfd 41static int qla25xx_init_queues(struct qla_hw_data *);
4d4df193 42
ac280b67
AV		 43/* SRB Extensions ---------------------------------------------------------- */
44
9ba56b95
GM		 45void
46qla2x00_sp_timeout(unsigned long __data)
ac280b67
AV		 47{
48 srb_t *sp = (srb_t *)__data;
4916392b 49 struct srb_iocb *iocb;
ac280b67
AV		 50 fc_port_t *fcport = sp->fcport;
51 struct qla_hw_data *ha = fcport->vha->hw;
52 struct req_que *req;
53 unsigned long flags;
54
55 spin_lock_irqsave(&ha->hardware_lock, flags);
56 req = ha->req_q_map[0];
57 req->outstanding_cmds[sp->handle] = NULL;
9ba56b95 58 iocb = &sp->u.iocb_cmd;
4916392b 59 iocb->timeout(sp);
9ba56b95 60 sp->free(fcport->vha, sp);
6ac52608 61 spin_unlock_irqrestore(&ha->hardware_lock, flags);
ac280b67
AV		 62}
63
9ba56b95
GM		 64void
65qla2x00_sp_free(void *data, void *ptr)
ac280b67 66{
9ba56b95
GM		 67 srb_t *sp = (srb_t *)ptr;
68 struct srb_iocb *iocb = &sp->u.iocb_cmd;
69 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
ac280b67 70
4d97cc53 71 del_timer(&iocb->timer);
b00ee7d7 72 qla2x00_rel_sp(vha, sp);
ac280b67
AV		 73}
74
ac280b67
AV		 75/* Asynchronous Login/Logout Routines -------------------------------------- */
76
a9b6f722 77unsigned long
5b91490e
AV		 78qla2x00_get_async_timeout(struct scsi_qla_host *vha)
79{
80 unsigned long tmo;
81 struct qla_hw_data *ha = vha->hw;
82
83 /* Firmware should use switch negotiated r_a_tov for timeout. */
84 tmo = ha->r_a_tov / 10 * 2;
8ae6d9c7
GM		 85 if (IS_QLAFX00(ha)) {
86 tmo = FX00_DEF_RATOV * 2;
87 } else if (!IS_FWI2_CAPABLE(ha)) {
5b91490e
AV		 88 /*
89 * Except for earlier ISPs where the timeout is seeded from the
90 * initialization control block.
91 */
92 tmo = ha->login_timeout;
93 }
94 return tmo;
95}
ac280b67
AV		 96
97static void
9ba56b95 98qla2x00_async_iocb_timeout(void *data)
ac280b67 99{
9ba56b95 100 srb_t *sp = (srb_t *)data;
ac280b67 101 fc_port_t *fcport = sp->fcport;
ac280b67 102
7c3df132 103 ql_dbg(ql_dbg_disc, fcport->vha, 0x2071,
cfb0919c 104 "Async-%s timeout - hdl=%x portid=%02x%02x%02x.\n",
9ba56b95 105 sp->name, sp->handle, fcport->d_id.b.domain, fcport->d_id.b.area,
7c3df132 106 fcport->d_id.b.al_pa);
ac280b67 107
5ff1d584 108 fcport->flags &= ~FCF_ASYNC_SENT;
9ba56b95
GM		 109 if (sp->type == SRB_LOGIN_CMD) {
110 struct srb_iocb *lio = &sp->u.iocb_cmd;
ac280b67 111 qla2x00_post_async_logout_work(fcport->vha, fcport, NULL);
6ac52608
AV		 112 /* Retry as needed. */
113 lio->u.logio.data[0] = MBS_COMMAND_ERROR;
114 lio->u.logio.data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
115 QLA_LOGIO_LOGIN_RETRIED : 0;
116 qla2x00_post_async_login_done_work(fcport->vha, fcport,
117 lio->u.logio.data);
118 }
ac280b67
AV		 119}
120
99b0bec7 121static void
9ba56b95 122qla2x00_async_login_sp_done(void *data, void *ptr, int res)
99b0bec7 123{
9ba56b95
GM		 124 srb_t *sp = (srb_t *)ptr;
125 struct srb_iocb *lio = &sp->u.iocb_cmd;
126 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
127
128 if (!test_bit(UNLOADING, &vha->dpc_flags))
129 qla2x00_post_async_login_done_work(sp->fcport->vha, sp->fcport,
130 lio->u.logio.data);
131 sp->free(sp->fcport->vha, sp);
99b0bec7
AV		 132}
133
ac280b67
AV		 134int
135qla2x00_async_login(struct scsi_qla_host *vha, fc_port_t *fcport,
136 uint16_t *data)
137{
ac280b67 138 srb_t *sp;
4916392b 139 struct srb_iocb *lio;
ac280b67
AV		 140 int rval;
141
142 rval = QLA_FUNCTION_FAILED;
9ba56b95 143 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 144 if (!sp)
145 goto done;
146
9ba56b95
GM		 147 sp->type = SRB_LOGIN_CMD;
148 sp->name = "login";
149 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
150
151 lio = &sp->u.iocb_cmd;
3822263e 152 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 153 sp->done = qla2x00_async_login_sp_done;
4916392b 154 lio->u.logio.flags |= SRB_LOGIN_COND_PLOGI;
ac280b67 155 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
4916392b 156 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
ac280b67
AV		 157 rval = qla2x00_start_sp(sp);
158 if (rval != QLA_SUCCESS)
159 goto done_free_sp;
160
7c3df132 161 ql_dbg(ql_dbg_disc, vha, 0x2072,
cfb0919c
CD		 162 "Async-login - hdl=%x, loopid=%x portid=%02x%02x%02x "
163 "retries=%d.\n", sp->handle, fcport->loop_id,
164 fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa,
165 fcport->login_retry);
ac280b67
AV		 166 return rval;
167
168done_free_sp:
9ba56b95 169 sp->free(fcport->vha, sp);
ac280b67
AV		 170done:
171 return rval;
172}
173
99b0bec7 174static void
9ba56b95 175qla2x00_async_logout_sp_done(void *data, void *ptr, int res)
99b0bec7 176{
9ba56b95
GM		 177 srb_t *sp = (srb_t *)ptr;
178 struct srb_iocb *lio = &sp->u.iocb_cmd;
179 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
180
181 if (!test_bit(UNLOADING, &vha->dpc_flags))
182 qla2x00_post_async_logout_done_work(sp->fcport->vha, sp->fcport,
183 lio->u.logio.data);
184 sp->free(sp->fcport->vha, sp);
99b0bec7
AV		 185}
186
ac280b67
AV		 187int
188qla2x00_async_logout(struct scsi_qla_host *vha, fc_port_t *fcport)
189{
ac280b67 190 srb_t *sp;
4916392b 191 struct srb_iocb *lio;
ac280b67
AV		 192 int rval;
193
194 rval = QLA_FUNCTION_FAILED;
9ba56b95 195 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 196 if (!sp)
197 goto done;
198
9ba56b95
GM		 199 sp->type = SRB_LOGOUT_CMD;
200 sp->name = "logout";
201 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
202
203 lio = &sp->u.iocb_cmd;
3822263e 204 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 205 sp->done = qla2x00_async_logout_sp_done;
ac280b67
AV		 206 rval = qla2x00_start_sp(sp);
207 if (rval != QLA_SUCCESS)
208 goto done_free_sp;
209
7c3df132 210 ql_dbg(ql_dbg_disc, vha, 0x2070,
cfb0919c
CD		 211 "Async-logout - hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
212 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
213 fcport->d_id.b.area, fcport->d_id.b.al_pa);
ac280b67
AV		 214 return rval;
215
216done_free_sp:
9ba56b95 217 sp->free(fcport->vha, sp);
ac280b67
AV		 218done:
219 return rval;
220}
221
5ff1d584 222static void
9ba56b95 223qla2x00_async_adisc_sp_done(void *data, void *ptr, int res)
5ff1d584 224{
9ba56b95
GM		 225 srb_t *sp = (srb_t *)ptr;
226 struct srb_iocb *lio = &sp->u.iocb_cmd;
227 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
228
229 if (!test_bit(UNLOADING, &vha->dpc_flags))
230 qla2x00_post_async_adisc_done_work(sp->fcport->vha, sp->fcport,
231 lio->u.logio.data);
232 sp->free(sp->fcport->vha, sp);
5ff1d584
AV		 233}
234
235int
236qla2x00_async_adisc(struct scsi_qla_host *vha, fc_port_t *fcport,
237 uint16_t *data)
238{
5ff1d584 239 srb_t *sp;
4916392b 240 struct srb_iocb *lio;
5ff1d584
AV		 241 int rval;
242
243 rval = QLA_FUNCTION_FAILED;
9ba56b95 244 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
5ff1d584
AV		 245 if (!sp)
246 goto done;
247
9ba56b95
GM		 248 sp->type = SRB_ADISC_CMD;
249 sp->name = "adisc";
250 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
251
252 lio = &sp->u.iocb_cmd;
3822263e 253 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 254 sp->done = qla2x00_async_adisc_sp_done;
5ff1d584 255 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
4916392b 256 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
5ff1d584
AV		 257 rval = qla2x00_start_sp(sp);
258 if (rval != QLA_SUCCESS)
259 goto done_free_sp;
260
7c3df132 261 ql_dbg(ql_dbg_disc, vha, 0x206f,
cfb0919c
CD		 262 "Async-adisc - hdl=%x loopid=%x portid=%02x%02x%02x.\n",
263 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
264 fcport->d_id.b.area, fcport->d_id.b.al_pa);
5ff1d584
AV		 265 return rval;
266
267done_free_sp:
9ba56b95 268 sp->free(fcport->vha, sp);
5ff1d584
AV		 269done:
270 return rval;
271}
272
3822263e 273static void
9ba56b95 274qla2x00_async_tm_cmd_done(void *data, void *ptr, int res)
3822263e 275{
9ba56b95
GM		 276 srb_t *sp = (srb_t *)ptr;
277 struct srb_iocb *iocb = &sp->u.iocb_cmd;
278 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
279 uint32_t flags;
280 uint16_t lun;
281 int rval;
3822263e 282
9ba56b95
GM		 283 if (!test_bit(UNLOADING, &vha->dpc_flags)) {
284 flags = iocb->u.tmf.flags;
285 lun = (uint16_t)iocb->u.tmf.lun;
286
287 /* Issue Marker IOCB */
288 rval = qla2x00_marker(vha, vha->hw->req_q_map[0],
289 vha->hw->rsp_q_map[0], sp->fcport->loop_id, lun,
290 flags == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID);
291
292 if ((rval != QLA_SUCCESS) || iocb->u.tmf.data) {
293 ql_dbg(ql_dbg_taskm, vha, 0x8030,
294 "TM IOCB failed (%x).\n", rval);
295 }
296 }
297 sp->free(sp->fcport->vha, sp);
3822263e
MI		 298}
299
300int
9ba56b95 301qla2x00_async_tm_cmd(fc_port_t *fcport, uint32_t tm_flags, uint32_t lun,
3822263e
MI		 302 uint32_t tag)
303{
304 struct scsi_qla_host *vha = fcport->vha;
3822263e 305 srb_t *sp;
3822263e
MI		 306 struct srb_iocb *tcf;
307 int rval;
308
309 rval = QLA_FUNCTION_FAILED;
9ba56b95 310 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
3822263e
MI		 311 if (!sp)
312 goto done;
313
9ba56b95
GM		 314 sp->type = SRB_TM_CMD;
315 sp->name = "tmf";
316 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
317
318 tcf = &sp->u.iocb_cmd;
319 tcf->u.tmf.flags = tm_flags;
3822263e
MI		 320 tcf->u.tmf.lun = lun;
321 tcf->u.tmf.data = tag;
322 tcf->timeout = qla2x00_async_iocb_timeout;
9ba56b95 323 sp->done = qla2x00_async_tm_cmd_done;
3822263e
MI		 324
325 rval = qla2x00_start_sp(sp);
326 if (rval != QLA_SUCCESS)
327 goto done_free_sp;
328
7c3df132 329 ql_dbg(ql_dbg_taskm, vha, 0x802f,
cfb0919c
CD		 330 "Async-tmf hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
331 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
332 fcport->d_id.b.area, fcport->d_id.b.al_pa);
3822263e
MI		 333 return rval;
334
335done_free_sp:
9ba56b95 336 sp->free(fcport->vha, sp);
3822263e
MI		 337done:
338 return rval;
339}
340
4916392b 341void
ac280b67
AV		 342qla2x00_async_login_done(struct scsi_qla_host *vha, fc_port_t *fcport,
343 uint16_t *data)
344{
345 int rval;
ac280b67
AV		 346
347 switch (data[0]) {
348 case MBS_COMMAND_COMPLETE:
a4f92a32
AV		 349 /*
350 * Driver must validate login state - If PRLI not complete,
351 * force a relogin attempt via implicit LOGO, PLOGI, and PRLI
352 * requests.
353 */
354 rval = qla2x00_get_port_database(vha, fcport, 0);
0eba25df
AE		 355 if (rval == QLA_NOT_LOGGED_IN) {
356 fcport->flags &= ~FCF_ASYNC_SENT;
357 fcport->flags |= FCF_LOGIN_NEEDED;
358 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
359 break;
360 }
361
a4f92a32
AV		 362 if (rval != QLA_SUCCESS) {
363 qla2x00_post_async_logout_work(vha, fcport, NULL);
364 qla2x00_post_async_login_work(vha, fcport, NULL);
365 break;
366 }
99b0bec7 367 if (fcport->flags & FCF_FCP2_DEVICE) {
5ff1d584
AV		 368 qla2x00_post_async_adisc_work(vha, fcport, data);
369 break;
99b0bec7
AV		 370 }
371 qla2x00_update_fcport(vha, fcport);
ac280b67
AV		 372 break;
373 case MBS_COMMAND_ERROR:
5ff1d584 374 fcport->flags &= ~FCF_ASYNC_SENT;
ac280b67
AV		 375 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
376 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
377 else
80d79440 378 qla2x00_mark_device_lost(vha, fcport, 1, 0);
ac280b67
AV		 379 break;
380 case MBS_PORT_ID_USED:
381 fcport->loop_id = data[1];
6ac52608 382 qla2x00_post_async_logout_work(vha, fcport, NULL);
ac280b67
AV		 383 qla2x00_post_async_login_work(vha, fcport, NULL);
384 break;
385 case MBS_LOOP_ID_USED:
386 fcport->loop_id++;
387 rval = qla2x00_find_new_loop_id(vha, fcport);
388 if (rval != QLA_SUCCESS) {
5ff1d584 389 fcport->flags &= ~FCF_ASYNC_SENT;
80d79440 390 qla2x00_mark_device_lost(vha, fcport, 1, 0);
ac280b67
AV		 391 break;
392 }
393 qla2x00_post_async_login_work(vha, fcport, NULL);
394 break;
395 }
4916392b 396 return;
ac280b67
AV		 397}
398
4916392b 399void
ac280b67
AV		 400qla2x00_async_logout_done(struct scsi_qla_host *vha, fc_port_t *fcport,
401 uint16_t *data)
402{
403 qla2x00_mark_device_lost(vha, fcport, 1, 0);
4916392b 404 return;
ac280b67
AV		 405}
406
4916392b 407void
5ff1d584
AV		 408qla2x00_async_adisc_done(struct scsi_qla_host *vha, fc_port_t *fcport,
409 uint16_t *data)
410{
411 if (data[0] == MBS_COMMAND_COMPLETE) {
412 qla2x00_update_fcport(vha, fcport);
413
4916392b 414 return;
5ff1d584
AV		 415 }
416
417 /* Retry login. */
418 fcport->flags &= ~FCF_ASYNC_SENT;
419 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
420 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
421 else
80d79440 422 qla2x00_mark_device_lost(vha, fcport, 1, 0);
5ff1d584 423
4916392b 424 return;
5ff1d584
AV		 425}
426
1da177e4
LT		 427/****************************************************************************/
428/* QLogic ISP2x00 Hardware Support Functions. */
429/****************************************************************************/
430
fa492630 431static int
7d613ac6
SV		 432qla83xx_nic_core_fw_load(scsi_qla_host_t *vha)
433{
434 int rval = QLA_SUCCESS;
435 struct qla_hw_data *ha = vha->hw;
436 uint32_t idc_major_ver, idc_minor_ver;
711aa7f7 437 uint16_t config[4];
7d613ac6
SV		 438
439 qla83xx_idc_lock(vha, 0);
440
441 /* SV: TODO: Assign initialization timeout from
442 * flash-info / other param
443 */
444 ha->fcoe_dev_init_timeout = QLA83XX_IDC_INITIALIZATION_TIMEOUT;
445 ha->fcoe_reset_timeout = QLA83XX_IDC_RESET_ACK_TIMEOUT;
446
447 /* Set our fcoe function presence */
448 if (__qla83xx_set_drv_presence(vha) != QLA_SUCCESS) {
449 ql_dbg(ql_dbg_p3p, vha, 0xb077,
450 "Error while setting DRV-Presence.\n");
451 rval = QLA_FUNCTION_FAILED;
452 goto exit;
453 }
454
455 /* Decide the reset ownership */
456 qla83xx_reset_ownership(vha);
457
458 /*
459 * On first protocol driver load:
460 * Init-Owner: Set IDC-Major-Version and Clear IDC-Lock-Recovery
461 * register.
462 * Others: Check compatibility with current IDC Major version.
463 */
464 qla83xx_rd_reg(vha, QLA83XX_IDC_MAJOR_VERSION, &idc_major_ver);
465 if (ha->flags.nic_core_reset_owner) {
466 /* Set IDC Major version */
467 idc_major_ver = QLA83XX_SUPP_IDC_MAJOR_VERSION;
468 qla83xx_wr_reg(vha, QLA83XX_IDC_MAJOR_VERSION, idc_major_ver);
469
470 /* Clearing IDC-Lock-Recovery register */
471 qla83xx_wr_reg(vha, QLA83XX_IDC_LOCK_RECOVERY, 0);
472 } else if (idc_major_ver != QLA83XX_SUPP_IDC_MAJOR_VERSION) {
473 /*
474 * Clear further IDC participation if we are not compatible with
475 * the current IDC Major Version.
476 */
477 ql_log(ql_log_warn, vha, 0xb07d,
478 "Failing load, idc_major_ver=%d, expected_major_ver=%d.\n",
479 idc_major_ver, QLA83XX_SUPP_IDC_MAJOR_VERSION);
480 __qla83xx_clear_drv_presence(vha);
481 rval = QLA_FUNCTION_FAILED;
482 goto exit;
483 }
484 /* Each function sets its supported Minor version. */
485 qla83xx_rd_reg(vha, QLA83XX_IDC_MINOR_VERSION, &idc_minor_ver);
486 idc_minor_ver |= (QLA83XX_SUPP_IDC_MINOR_VERSION << (ha->portnum * 2));
487 qla83xx_wr_reg(vha, QLA83XX_IDC_MINOR_VERSION, idc_minor_ver);
488
711aa7f7
SK		 489 if (ha->flags.nic_core_reset_owner) {
490 memset(config, 0, sizeof(config));
491 if (!qla81xx_get_port_config(vha, config))
492 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
493 QLA8XXX_DEV_READY);
494 }
495
7d613ac6
SV		 496 rval = qla83xx_idc_state_handler(vha);
497
498exit:
499 qla83xx_idc_unlock(vha, 0);
500
501 return rval;
502}
503
1da177e4
LT		 504/*
505* qla2x00_initialize_adapter
506* Initialize board.
507*
508* Input:
509* ha = adapter block pointer.
510*
511* Returns:
512* 0 = success
513*/
514int
e315cd28 515qla2x00_initialize_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 516{
517 int rval;
e315cd28 518 struct qla_hw_data *ha = vha->hw;
73208dfd 519 struct req_que *req = ha->req_q_map[0];
2533cf67 520
1da177e4 521 /* Clear adapter flags. */
e315cd28 522 vha->flags.online = 0;
2533cf67 523 ha->flags.chip_reset_done = 0;
e315cd28 524 vha->flags.reset_active = 0;
85880801
AV		 525 ha->flags.pci_channel_io_perm_failure = 0;
526 ha->flags.eeh_busy = 0;
fabbb8df 527 vha->qla_stats.jiffies_at_last_reset = get_jiffies_64();
e315cd28
AC		 528 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
529 atomic_set(&vha->loop_state, LOOP_DOWN);
530 vha->device_flags = DFLG_NO_CABLE;
531 vha->dpc_flags = 0;
532 vha->flags.management_server_logged_in = 0;
533 vha->marker_needed = 0;
1da177e4
LT		 534 ha->isp_abort_cnt = 0;
535 ha->beacon_blink_led = 0;
536
73208dfd
AC		 537 set_bit(0, ha->req_qid_map);
538 set_bit(0, ha->rsp_qid_map);
539
cfb0919c 540 ql_dbg(ql_dbg_init, vha, 0x0040,
7c3df132 541 "Configuring PCI space...\n");
e315cd28 542 rval = ha->isp_ops->pci_config(vha);
1da177e4 543 if (rval) {
7c3df132
SK		 544 ql_log(ql_log_warn, vha, 0x0044,
545 "Unable to configure PCI space.\n");
1da177e4
LT		 546 return (rval);
547 }
548
e315cd28 549 ha->isp_ops->reset_chip(vha);
1da177e4 550
e315cd28 551 rval = qla2xxx_get_flash_info(vha);
c00d8994 552 if (rval) {
7c3df132
SK		 553 ql_log(ql_log_fatal, vha, 0x004f,
554 "Unable to validate FLASH data.\n");
7ec0effd
AD		 555 return rval;
556 }
557
558 if (IS_QLA8044(ha)) {
559 qla8044_read_reset_template(vha);
560
561 /* NOTE: If ql2xdontresethba==1, set IDC_CTRL DONTRESET_BIT0.
562 * If DONRESET_BIT0 is set, drivers should not set dev_state
563 * to NEED_RESET. But if NEED_RESET is set, drivers should
564 * should honor the reset. */
565 if (ql2xdontresethba == 1)
566 qla8044_set_idc_dontreset(vha);
c00d8994
AV		 567 }
568
73208dfd 569 ha->isp_ops->get_flash_version(vha, req->ring);
cfb0919c 570 ql_dbg(ql_dbg_init, vha, 0x0061,
7c3df132 571 "Configure NVRAM parameters...\n");
0107109e 572
e315cd28 573 ha->isp_ops->nvram_config(vha);
1da177e4 574
d4c760c2
AV		 575 if (ha->flags.disable_serdes) {
576 /* Mask HBA via NVRAM settings? */
7c3df132 577 ql_log(ql_log_info, vha, 0x0077,
7b833558 578 "Masking HBA WWPN %8phN (via NVRAM).\n", vha->port_name);
d4c760c2
AV		 579 return QLA_FUNCTION_FAILED;
580 }
581
cfb0919c 582 ql_dbg(ql_dbg_init, vha, 0x0078,
7c3df132 583 "Verifying loaded RISC code...\n");
1da177e4 584
e315cd28
AC		 585 if (qla2x00_isp_firmware(vha) != QLA_SUCCESS) {
586 rval = ha->isp_ops->chip_diag(vha);
d19044c3
AV		 587 if (rval)
588 return (rval);
e315cd28 589 rval = qla2x00_setup_chip(vha);
d19044c3
AV		 590 if (rval)
591 return (rval);
1da177e4 592 }
a9083016 593
4d4df193 594 if (IS_QLA84XX(ha)) {
e315cd28 595 ha->cs84xx = qla84xx_get_chip(vha);
4d4df193 596 if (!ha->cs84xx) {
7c3df132 597 ql_log(ql_log_warn, vha, 0x00d0,
4d4df193
HK		 598 "Unable to configure ISP84XX.\n");
599 return QLA_FUNCTION_FAILED;
600 }
601 }
2d70c103
NB		 602
603 if (qla_ini_mode_enabled(vha))
604 rval = qla2x00_init_rings(vha);
605
2533cf67 606 ha->flags.chip_reset_done = 1;
1da177e4 607
9a069e19 608 if (rval == QLA_SUCCESS && IS_QLA84XX(ha)) {
6c452a45 609 /* Issue verify 84xx FW IOCB to complete 84xx initialization */
9a069e19
GM		 610 rval = qla84xx_init_chip(vha);
611 if (rval != QLA_SUCCESS) {
7c3df132
SK		 612 ql_log(ql_log_warn, vha, 0x00d4,
613 "Unable to initialize ISP84XX.\n");
9a069e19
GM		 614 qla84xx_put_chip(vha);
615 }
616 }
617
7d613ac6
SV		 618 /* Load the NIC Core f/w if we are the first protocol driver. */
619 if (IS_QLA8031(ha)) {
620 rval = qla83xx_nic_core_fw_load(vha);
621 if (rval)
622 ql_log(ql_log_warn, vha, 0x0124,
623 "Error in initializing NIC Core f/w.\n");
624 }
625
2f0f3f4f
MI		 626 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha))
627 qla24xx_read_fcp_prio_cfg(vha);
09ff701a 628
c46e65c7
JC		 629 if (IS_P3P_TYPE(ha))
630 qla82xx_set_driver_version(vha, QLA2XXX_VERSION);
631 else
632 qla25xx_set_driver_version(vha, QLA2XXX_VERSION);
633
1da177e4
LT		 634 return (rval);
635}
636
637/**
abbd8870 638 * qla2100_pci_config() - Setup ISP21xx PCI configuration registers.
1da177e4
LT		 639 * @ha: HA context
640 *
641 * Returns 0 on success.
642 */
abbd8870 643int
e315cd28 644qla2100_pci_config(scsi_qla_host_t *vha)
1da177e4 645{
a157b101 646 uint16_t w;
abbd8870 647 unsigned long flags;
e315cd28 648 struct qla_hw_data *ha = vha->hw;
3d71644c 649 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 650
1da177e4 651 pci_set_master(ha->pdev);
af6177d8 652 pci_try_set_mwi(ha->pdev);
1da177e4 653
1da177e4 654 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 655 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
abbd8870
AV		 656 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
657
737faece 658 pci_disable_rom(ha->pdev);
1da177e4
LT		 659
660 /* Get PCI bus information. */
661 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 662 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
1da177e4
LT		 663 spin_unlock_irqrestore(&ha->hardware_lock, flags);
664
abbd8870
AV		 665 return QLA_SUCCESS;
666}
1da177e4 667
abbd8870
AV		 668/**
669 * qla2300_pci_config() - Setup ISP23xx PCI configuration registers.
670 * @ha: HA context
671 *
672 * Returns 0 on success.
673 */
674int
e315cd28 675qla2300_pci_config(scsi_qla_host_t *vha)
abbd8870 676{
a157b101 677 uint16_t w;
abbd8870
AV		 678 unsigned long flags = 0;
679 uint32_t cnt;
e315cd28 680 struct qla_hw_data *ha = vha->hw;
3d71644c 681 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 682
abbd8870 683 pci_set_master(ha->pdev);
af6177d8 684 pci_try_set_mwi(ha->pdev);
1da177e4 685
abbd8870 686 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 687 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
1da177e4 688
abbd8870
AV		 689 if (IS_QLA2322(ha) || IS_QLA6322(ha))
690 w &= ~PCI_COMMAND_INTX_DISABLE;
a157b101 691 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
1da177e4 692
abbd8870
AV		 693 /*
694 * If this is a 2300 card and not 2312, reset the
695 * COMMAND_INVALIDATE due to a bug in the 2300. Unfortunately,
696 * the 2310 also reports itself as a 2300 so we need to get the
697 * fb revision level -- a 6 indicates it really is a 2300 and
698 * not a 2310.
699 */
700 if (IS_QLA2300(ha)) {
701 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 702
abbd8870 703 /* Pause RISC. */
3d71644c 704 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
abbd8870 705 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 706 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
abbd8870 707 break;
1da177e4 708
abbd8870
AV		 709 udelay(10);
710 }
1da177e4 711
abbd8870 712 /* Select FPM registers. */
3d71644c
AV		 713 WRT_REG_WORD(&reg->ctrl_status, 0x20);
714 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 715
716 /* Get the fb rev level */
3d71644c 717 ha->fb_rev = RD_FB_CMD_REG(ha, reg);
abbd8870
AV		 718
719 if (ha->fb_rev == FPM_2300)
a157b101 720 pci_clear_mwi(ha->pdev);
abbd8870
AV		 721
722 /* Deselect FPM registers. */
3d71644c
AV		 723 WRT_REG_WORD(&reg->ctrl_status, 0x0);
724 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 725
726 /* Release RISC module. */
3d71644c 727 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
abbd8870 728 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 729 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0)
abbd8870
AV		 730 break;
731
732 udelay(10);
1da177e4 733 }
1da177e4 734
abbd8870
AV		 735 spin_unlock_irqrestore(&ha->hardware_lock, flags);
736 }
1da177e4 737
abbd8870
AV		 738 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
739
737faece 740 pci_disable_rom(ha->pdev);
1da177e4 741
abbd8870
AV		 742 /* Get PCI bus information. */
743 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 744 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 745 spin_unlock_irqrestore(&ha->hardware_lock, flags);
746
747 return QLA_SUCCESS;
1da177e4
LT		 748}
749
0107109e
AV		 750/**
751 * qla24xx_pci_config() - Setup ISP24xx PCI configuration registers.
752 * @ha: HA context
753 *
754 * Returns 0 on success.
755 */
756int
e315cd28 757qla24xx_pci_config(scsi_qla_host_t *vha)
0107109e 758{
a157b101 759 uint16_t w;
0107109e 760 unsigned long flags = 0;
e315cd28 761 struct qla_hw_data *ha = vha->hw;
0107109e 762 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
0107109e
AV		 763
764 pci_set_master(ha->pdev);
af6177d8 765 pci_try_set_mwi(ha->pdev);
0107109e
AV		 766
767 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 768 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
0107109e
AV		 769 w &= ~PCI_COMMAND_INTX_DISABLE;
770 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
771
772 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
773
774 /* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */
f85ec187
AV		 775 if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX))
776 pcix_set_mmrbc(ha->pdev, 2048);
0107109e
AV		 777
778 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 779 if (pci_is_pcie(ha->pdev))
5ffd3a52 780 pcie_set_readrq(ha->pdev, 4096);
0107109e 781
737faece 782 pci_disable_rom(ha->pdev);
0107109e 783
44c10138 784 ha->chip_revision = ha->pdev->revision;
a8488abe 785
0107109e
AV		 786 /* Get PCI bus information. */
787 spin_lock_irqsave(&ha->hardware_lock, flags);
788 ha->pci_attr = RD_REG_DWORD(&reg->ctrl_status);
789 spin_unlock_irqrestore(&ha->hardware_lock, flags);
790
791 return QLA_SUCCESS;
792}
793
c3a2f0df
AV		 794/**
795 * qla25xx_pci_config() - Setup ISP25xx PCI configuration registers.
796 * @ha: HA context
797 *
798 * Returns 0 on success.
799 */
800int
e315cd28 801qla25xx_pci_config(scsi_qla_host_t *vha)
c3a2f0df
AV		 802{
803 uint16_t w;
e315cd28 804 struct qla_hw_data *ha = vha->hw;
c3a2f0df
AV		 805
806 pci_set_master(ha->pdev);
807 pci_try_set_mwi(ha->pdev);
808
809 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
810 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
811 w &= ~PCI_COMMAND_INTX_DISABLE;
812 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
813
814 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 815 if (pci_is_pcie(ha->pdev))
5ffd3a52 816 pcie_set_readrq(ha->pdev, 4096);
c3a2f0df 817
737faece 818 pci_disable_rom(ha->pdev);
c3a2f0df
AV		 819
820 ha->chip_revision = ha->pdev->revision;
821
822 return QLA_SUCCESS;
823}
824
1da177e4
LT		 825/**
826 * qla2x00_isp_firmware() - Choose firmware image.
827 * @ha: HA context
828 *
829 * Returns 0 on success.
830 */
831static int
e315cd28 832qla2x00_isp_firmware(scsi_qla_host_t *vha)
1da177e4
LT		 833{
834 int rval;
42e421b1
AV		 835 uint16_t loop_id, topo, sw_cap;
836 uint8_t domain, area, al_pa;
e315cd28 837 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 838
839 /* Assume loading risc code */
fa2a1ce5 840 rval = QLA_FUNCTION_FAILED;
1da177e4
LT		 841
842 if (ha->flags.disable_risc_code_load) {
7c3df132 843 ql_log(ql_log_info, vha, 0x0079, "RISC CODE NOT loaded.\n");
1da177e4
LT		 844
845 /* Verify checksum of loaded RISC code. */
e315cd28 846 rval = qla2x00_verify_checksum(vha, ha->fw_srisc_address);
42e421b1
AV		 847 if (rval == QLA_SUCCESS) {
848 /* And, verify we are not in ROM code. */
e315cd28 849 rval = qla2x00_get_adapter_id(vha, &loop_id, &al_pa,
42e421b1
AV		 850 &area, &domain, &topo, &sw_cap);
851 }
1da177e4
LT		 852 }
853
7c3df132
SK		 854 if (rval)
855 ql_dbg(ql_dbg_init, vha, 0x007a,
856 "**** Load RISC code ****.\n");
1da177e4
LT		 857
858 return (rval);
859}
860
861/**
862 * qla2x00_reset_chip() - Reset ISP chip.
863 * @ha: HA context
864 *
865 * Returns 0 on success.
866 */
abbd8870 867void
e315cd28 868qla2x00_reset_chip(scsi_qla_host_t *vha)
1da177e4
LT		 869{
870 unsigned long flags = 0;
e315cd28 871 struct qla_hw_data *ha = vha->hw;
3d71644c 872 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 873 uint32_t cnt;
1da177e4
LT		 874 uint16_t cmd;
875
85880801
AV		 876 if (unlikely(pci_channel_offline(ha->pdev)))
877 return;
878
fd34f556 879 ha->isp_ops->disable_intrs(ha);
1da177e4
LT		 880
881 spin_lock_irqsave(&ha->hardware_lock, flags);
882
883 /* Turn off master enable */
884 cmd = 0;
885 pci_read_config_word(ha->pdev, PCI_COMMAND, &cmd);
886 cmd &= ~PCI_COMMAND_MASTER;
887 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
888
889 if (!IS_QLA2100(ha)) {
890 /* Pause RISC. */
891 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
892 if (IS_QLA2200(ha) || IS_QLA2300(ha)) {
893 for (cnt = 0; cnt < 30000; cnt++) {
894 if ((RD_REG_WORD(&reg->hccr) &
895 HCCR_RISC_PAUSE) != 0)
896 break;
897 udelay(100);
898 }
899 } else {
900 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
901 udelay(10);
902 }
903
904 /* Select FPM registers. */
905 WRT_REG_WORD(&reg->ctrl_status, 0x20);
906 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
907
908 /* FPM Soft Reset. */
909 WRT_REG_WORD(&reg->fpm_diag_config, 0x100);
910 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
911
912 /* Toggle Fpm Reset. */
913 if (!IS_QLA2200(ha)) {
914 WRT_REG_WORD(&reg->fpm_diag_config, 0x0);
915 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
916 }
917
918 /* Select frame buffer registers. */
919 WRT_REG_WORD(&reg->ctrl_status, 0x10);
920 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
921
922 /* Reset frame buffer FIFOs. */
923 if (IS_QLA2200(ha)) {
924 WRT_FB_CMD_REG(ha, reg, 0xa000);
925 RD_FB_CMD_REG(ha, reg); /* PCI Posting. */
926 } else {
927 WRT_FB_CMD_REG(ha, reg, 0x00fc);
928
929 /* Read back fb_cmd until zero or 3 seconds max */
930 for (cnt = 0; cnt < 3000; cnt++) {
931 if ((RD_FB_CMD_REG(ha, reg) & 0xff) == 0)
932 break;
933 udelay(100);
934 }
935 }
936
937 /* Select RISC module registers. */
938 WRT_REG_WORD(&reg->ctrl_status, 0);
939 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
940
941 /* Reset RISC processor. */
942 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
943 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
944
945 /* Release RISC processor. */
946 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
947 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
948 }
949
950 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
951 WRT_REG_WORD(&reg->hccr, HCCR_CLR_HOST_INT);
952
953 /* Reset ISP chip. */
954 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
955
956 /* Wait for RISC to recover from reset. */
957 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
958 /*
959 * It is necessary to for a delay here since the card doesn't
960 * respond to PCI reads during a reset. On some architectures
961 * this will result in an MCA.
962 */
963 udelay(20);
964 for (cnt = 30000; cnt; cnt--) {
965 if ((RD_REG_WORD(&reg->ctrl_status) &
966 CSR_ISP_SOFT_RESET) == 0)
967 break;
968 udelay(100);
969 }
970 } else
971 udelay(10);
972
973 /* Reset RISC processor. */
974 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
975
976 WRT_REG_WORD(&reg->semaphore, 0);
977
978 /* Release RISC processor. */
979 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
980 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
981
982 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
983 for (cnt = 0; cnt < 30000; cnt++) {
ffb39f03 984 if (RD_MAILBOX_REG(ha, reg, 0) != MBS_BUSY)
1da177e4 985 break;
1da177e4
LT		 986
987 udelay(100);
988 }
989 } else
990 udelay(100);
991
992 /* Turn on master enable */
993 cmd |= PCI_COMMAND_MASTER;
994 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
995
996 /* Disable RISC pause on FPM parity error. */
997 if (!IS_QLA2100(ha)) {
998 WRT_REG_WORD(&reg->hccr, HCCR_DISABLE_PARITY_PAUSE);
999 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
1000 }
1001
1002 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1003}
1004
b1d46989
MI		 1005/**
1006 * qla81xx_reset_mpi() - Reset's MPI FW via Write MPI Register MBC.
1007 *
1008 * Returns 0 on success.
1009 */
fa492630 1010static int
b1d46989
MI		 1011qla81xx_reset_mpi(scsi_qla_host_t *vha)
1012{
1013 uint16_t mb[4] = {0x1010, 0, 1, 0};
1014
6246b8a1
GM		 1015 if (!IS_QLA81XX(vha->hw))
1016 return QLA_SUCCESS;
1017
b1d46989
MI		 1018 return qla81xx_write_mpi_register(vha, mb);
1019}
1020
0107109e 1021/**
88c26663 1022 * qla24xx_reset_risc() - Perform full reset of ISP24xx RISC.
0107109e
AV		 1023 * @ha: HA context
1024 *
1025 * Returns 0 on success.
1026 */
88c26663 1027static inline void
e315cd28 1028qla24xx_reset_risc(scsi_qla_host_t *vha)
0107109e
AV		 1029{
1030 unsigned long flags = 0;
e315cd28 1031 struct qla_hw_data *ha = vha->hw;
0107109e
AV		 1032 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1033 uint32_t cnt, d2;
335a1cc9 1034 uint16_t wd;
b1d46989 1035 static int abts_cnt; /* ISP abort retry counts */
0107109e 1036
0107109e
AV		 1037 spin_lock_irqsave(&ha->hardware_lock, flags);
1038
1039 /* Reset RISC. */
1040 WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
1041 for (cnt = 0; cnt < 30000; cnt++) {
1042 if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
1043 break;
1044
1045 udelay(10);
1046 }
1047
1048 WRT_REG_DWORD(&reg->ctrl_status,
1049 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
335a1cc9 1050 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
88c26663 1051
335a1cc9 1052 udelay(100);
88c26663 1053 /* Wait for firmware to complete NVRAM accesses. */
88c26663
AV		 1054 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1055 for (cnt = 10000 ; cnt && d2; cnt--) {
1056 udelay(5);
1057 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1058 barrier();
1059 }
1060
335a1cc9 1061 /* Wait for soft-reset to complete. */
0107109e
AV		 1062 d2 = RD_REG_DWORD(&reg->ctrl_status);
1063 for (cnt = 6000000 ; cnt && (d2 & CSRX_ISP_SOFT_RESET); cnt--) {
1064 udelay(5);
1065 d2 = RD_REG_DWORD(&reg->ctrl_status);
1066 barrier();
1067 }
1068
b1d46989
MI		 1069 /* If required, do an MPI FW reset now */
1070 if (test_and_clear_bit(MPI_RESET_NEEDED, &vha->dpc_flags)) {
1071 if (qla81xx_reset_mpi(vha) != QLA_SUCCESS) {
1072 if (++abts_cnt < 5) {
1073 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1074 set_bit(MPI_RESET_NEEDED, &vha->dpc_flags);
1075 } else {
1076 /*
1077 * We exhausted the ISP abort retries. We have to
1078 * set the board offline.
1079 */
1080 abts_cnt = 0;
1081 vha->flags.online = 0;
1082 }
1083 }
1084 }
1085
0107109e
AV		 1086 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
1087 RD_REG_DWORD(&reg->hccr);
1088
1089 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
1090 RD_REG_DWORD(&reg->hccr);
1091
1092 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
1093 RD_REG_DWORD(&reg->hccr);
1094
1095 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1096 for (cnt = 6000000 ; cnt && d2; cnt--) {
1097 udelay(5);
1098 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1099 barrier();
1100 }
1101
1102 spin_unlock_irqrestore(&ha->hardware_lock, flags);
124f85e6
AV		 1103
1104 if (IS_NOPOLLING_TYPE(ha))
1105 ha->isp_ops->enable_intrs(ha);
0107109e
AV		 1106}
1107
4ea2c9c7
JC		 1108static void
1109qla25xx_read_risc_sema_reg(scsi_qla_host_t *vha, uint32_t *data)
1110{
1111 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
1112
1113 WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
1114 *data = RD_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET);
1115
1116}
1117
1118static void
1119qla25xx_write_risc_sema_reg(scsi_qla_host_t *vha, uint32_t data)
1120{
1121 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
1122
1123 WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
1124 WRT_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET, data);
1125}
1126
1127static void
1128qla25xx_manipulate_risc_semaphore(scsi_qla_host_t *vha)
1129{
1130 struct qla_hw_data *ha = vha->hw;
1131 uint32_t wd32 = 0;
1132 uint delta_msec = 100;
1133 uint elapsed_msec = 0;
1134 uint timeout_msec;
1135 ulong n;
1136
1137 if (!IS_QLA25XX(ha) && !IS_QLA2031(ha))
1138 return;
1139
1140attempt:
1141 timeout_msec = TIMEOUT_SEMAPHORE;
1142 n = timeout_msec / delta_msec;
1143 while (n--) {
1144 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_SET);
1145 qla25xx_read_risc_sema_reg(vha, &wd32);
1146 if (wd32 & RISC_SEMAPHORE)
1147 break;
1148 msleep(delta_msec);
1149 elapsed_msec += delta_msec;
1150 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
1151 goto force;
1152 }
1153
1154 if (!(wd32 & RISC_SEMAPHORE))
1155 goto force;
1156
1157 if (!(wd32 & RISC_SEMAPHORE_FORCE))
1158 goto acquired;
1159
1160 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_CLR);
1161 timeout_msec = TIMEOUT_SEMAPHORE_FORCE;
1162 n = timeout_msec / delta_msec;
1163 while (n--) {
1164 qla25xx_read_risc_sema_reg(vha, &wd32);
1165 if (!(wd32 & RISC_SEMAPHORE_FORCE))
1166 break;
1167 msleep(delta_msec);
1168 elapsed_msec += delta_msec;
1169 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
1170 goto force;
1171 }
1172
1173 if (wd32 & RISC_SEMAPHORE_FORCE)
1174 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_CLR);
1175
1176 goto attempt;
1177
1178force:
1179 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_SET);
1180
1181acquired:
1182 return;
1183}
1184
88c26663
AV		 1185/**
1186 * qla24xx_reset_chip() - Reset ISP24xx chip.
1187 * @ha: HA context
1188 *
1189 * Returns 0 on success.
1190 */
1191void
e315cd28 1192qla24xx_reset_chip(scsi_qla_host_t *vha)
88c26663 1193{
e315cd28 1194 struct qla_hw_data *ha = vha->hw;
85880801
AV		 1195
1196 if (pci_channel_offline(ha->pdev) &&
1197 ha->flags.pci_channel_io_perm_failure) {
1198 return;
1199 }
1200
fd34f556 1201 ha->isp_ops->disable_intrs(ha);
88c26663 1202
4ea2c9c7
JC		 1203 qla25xx_manipulate_risc_semaphore(vha);
1204
88c26663 1205 /* Perform RISC reset. */
e315cd28 1206 qla24xx_reset_risc(vha);
88c26663
AV		 1207}
1208
1da177e4
LT		 1209/**
1210 * qla2x00_chip_diag() - Test chip for proper operation.
1211 * @ha: HA context
1212 *
1213 * Returns 0 on success.
1214 */
abbd8870 1215int
e315cd28 1216qla2x00_chip_diag(scsi_qla_host_t *vha)
1da177e4
LT		 1217{
1218 int rval;
e315cd28 1219 struct qla_hw_data *ha = vha->hw;
3d71644c 1220 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 1221 unsigned long flags = 0;
1222 uint16_t data;
1223 uint32_t cnt;
1224 uint16_t mb[5];
73208dfd 1225 struct req_que *req = ha->req_q_map[0];
1da177e4
LT		 1226
1227 /* Assume a failed state */
1228 rval = QLA_FUNCTION_FAILED;
1229
7c3df132
SK		 1230 ql_dbg(ql_dbg_init, vha, 0x007b,
1231 "Testing device at %lx.\n", (u_long)&reg->flash_address);
1da177e4
LT		 1232
1233 spin_lock_irqsave(&ha->hardware_lock, flags);
1234
1235 /* Reset ISP chip. */
1236 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
1237
1238 /*
1239 * We need to have a delay here since the card will not respond while
1240 * in reset causing an MCA on some architectures.
1241 */
1242 udelay(20);
1243 data = qla2x00_debounce_register(&reg->ctrl_status);
1244 for (cnt = 6000000 ; cnt && (data & CSR_ISP_SOFT_RESET); cnt--) {
1245 udelay(5);
1246 data = RD_REG_WORD(&reg->ctrl_status);
1247 barrier();
1248 }
1249
1250 if (!cnt)
1251 goto chip_diag_failed;
1252
7c3df132
SK		 1253 ql_dbg(ql_dbg_init, vha, 0x007c,
1254 "Reset register cleared by chip reset.\n");
1da177e4
LT		 1255
1256 /* Reset RISC processor. */
1257 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
1258 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
1259
1260 /* Workaround for QLA2312 PCI parity error */
1261 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1262 data = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 0));
1263 for (cnt = 6000000; cnt && (data == MBS_BUSY); cnt--) {
1264 udelay(5);
1265 data = RD_MAILBOX_REG(ha, reg, 0);
fa2a1ce5 1266 barrier();
1da177e4
LT		 1267 }
1268 } else
1269 udelay(10);
1270
1271 if (!cnt)
1272 goto chip_diag_failed;
1273
1274 /* Check product ID of chip */
7c3df132 1275 ql_dbg(ql_dbg_init, vha, 0x007d, "Checking product Id of chip.\n");
1da177e4
LT		 1276
1277 mb[1] = RD_MAILBOX_REG(ha, reg, 1);
1278 mb[2] = RD_MAILBOX_REG(ha, reg, 2);
1279 mb[3] = RD_MAILBOX_REG(ha, reg, 3);
1280 mb[4] = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 4));
1281 if (mb[1] != PROD_ID_1 || (mb[2] != PROD_ID_2 && mb[2] != PROD_ID_2a) ||
1282 mb[3] != PROD_ID_3) {
7c3df132
SK		 1283 ql_log(ql_log_warn, vha, 0x0062,
1284 "Wrong product ID = 0x%x,0x%x,0x%x.\n",
1285 mb[1], mb[2], mb[3]);
1da177e4
LT		 1286
1287 goto chip_diag_failed;
1288 }
1289 ha->product_id[0] = mb[1];
1290 ha->product_id[1] = mb[2];
1291 ha->product_id[2] = mb[3];
1292 ha->product_id[3] = mb[4];
1293
1294 /* Adjust fw RISC transfer size */
73208dfd 1295 if (req->length > 1024)
1da177e4
LT		 1296 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1024;
1297 else
1298 ha->fw_transfer_size = REQUEST_ENTRY_SIZE *
73208dfd 1299 req->length;
1da177e4
LT		 1300
1301 if (IS_QLA2200(ha) &&
1302 RD_MAILBOX_REG(ha, reg, 7) == QLA2200A_RISC_ROM_VER) {
1303 /* Limit firmware transfer size with a 2200A */
7c3df132 1304 ql_dbg(ql_dbg_init, vha, 0x007e, "Found QLA2200A Chip.\n");
1da177e4 1305
ea5b6382 1306 ha->device_type |= DT_ISP2200A;
1da177e4
LT		 1307 ha->fw_transfer_size = 128;
1308 }
1309
1310 /* Wrap Incoming Mailboxes Test. */
1311 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1312
7c3df132 1313 ql_dbg(ql_dbg_init, vha, 0x007f, "Checking mailboxes.\n");
e315cd28 1314 rval = qla2x00_mbx_reg_test(vha);
7c3df132
SK		 1315 if (rval)
1316 ql_log(ql_log_warn, vha, 0x0080,
1317 "Failed mailbox send register test.\n");
1318 else
1da177e4
LT		 1319 /* Flag a successful rval */
1320 rval = QLA_SUCCESS;
1da177e4
LT		 1321 spin_lock_irqsave(&ha->hardware_lock, flags);
1322
1323chip_diag_failed:
1324 if (rval)
7c3df132
SK		 1325 ql_log(ql_log_info, vha, 0x0081,
1326 "Chip diagnostics **** FAILED ****.\n");
1da177e4
LT		 1327
1328 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1329
1330 return (rval);
1331}
1332
0107109e
AV		 1333/**
1334 * qla24xx_chip_diag() - Test ISP24xx for proper operation.
1335 * @ha: HA context
1336 *
1337 * Returns 0 on success.
1338 */
1339int
e315cd28 1340qla24xx_chip_diag(scsi_qla_host_t *vha)
0107109e
AV		 1341{
1342 int rval;
e315cd28 1343 struct qla_hw_data *ha = vha->hw;
73208dfd 1344 struct req_que *req = ha->req_q_map[0];
0107109e 1345
7ec0effd 1346 if (IS_P3P_TYPE(ha))
a9083016
GM		 1347 return QLA_SUCCESS;
1348
73208dfd 1349 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
0107109e 1350
e315cd28 1351 rval = qla2x00_mbx_reg_test(vha);
0107109e 1352 if (rval) {
7c3df132
SK		 1353 ql_log(ql_log_warn, vha, 0x0082,
1354 "Failed mailbox send register test.\n");
0107109e
AV		 1355 } else {
1356 /* Flag a successful rval */
1357 rval = QLA_SUCCESS;
1358 }
1359
1360 return rval;
1361}
1362
a7a167bf 1363void
e315cd28 1364qla2x00_alloc_fw_dump(scsi_qla_host_t *vha)
0107109e 1365{
a7a167bf
AV		 1366 int rval;
1367 uint32_t dump_size, fixed_size, mem_size, req_q_size, rsp_q_size,
73208dfd 1368 eft_size, fce_size, mq_size;
df613b96
AV		 1369 dma_addr_t tc_dma;
1370 void *tc;
e315cd28 1371 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 1372 struct req_que *req = ha->req_q_map[0];
1373 struct rsp_que *rsp = ha->rsp_q_map[0];
a7a167bf
AV		 1374
1375 if (ha->fw_dump) {
7c3df132
SK		 1376 ql_dbg(ql_dbg_init, vha, 0x00bd,
1377 "Firmware dump already allocated.\n");
a7a167bf
AV		 1378 return;
1379 }
d4e3e04d 1380
0107109e 1381 ha->fw_dumped = 0;
73208dfd 1382 fixed_size = mem_size = eft_size = fce_size = mq_size = 0;
d4e3e04d 1383 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
a7a167bf 1384 fixed_size = sizeof(struct qla2100_fw_dump);
d4e3e04d 1385 } else if (IS_QLA23XX(ha)) {
a7a167bf
AV		 1386 fixed_size = offsetof(struct qla2300_fw_dump, data_ram);
1387 mem_size = (ha->fw_memory_size - 0x11000 + 1) *
1388 sizeof(uint16_t);
e428924c 1389 } else if (IS_FWI2_CAPABLE(ha)) {
6246b8a1
GM		 1390 if (IS_QLA83XX(ha))
1391 fixed_size = offsetof(struct qla83xx_fw_dump, ext_mem);
1392 else if (IS_QLA81XX(ha))
3a03eb79
AV		 1393 fixed_size = offsetof(struct qla81xx_fw_dump, ext_mem);
1394 else if (IS_QLA25XX(ha))
1395 fixed_size = offsetof(struct qla25xx_fw_dump, ext_mem);
1396 else
1397 fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem);
a7a167bf
AV		 1398 mem_size = (ha->fw_memory_size - 0x100000 + 1) *
1399 sizeof(uint32_t);
050c9bb1 1400 if (ha->mqenable) {
6246b8a1
GM		 1401 if (!IS_QLA83XX(ha))
1402 mq_size = sizeof(struct qla2xxx_mq_chain);
050c9bb1
GM		 1403 /*
1404 * Allocate maximum buffer size for all queues.
1405 * Resizing must be done at end-of-dump processing.
1406 */
1407 mq_size += ha->max_req_queues *
1408 (req->length * sizeof(request_t));
1409 mq_size += ha->max_rsp_queues *
1410 (rsp->length * sizeof(response_t));
1411 }
00876ae8 1412 if (ha->tgt.atio_ring)
2d70c103 1413 mq_size += ha->tgt.atio_q_length * sizeof(request_t);
df613b96 1414 /* Allocate memory for Fibre Channel Event Buffer. */
6246b8a1 1415 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha))
436a7b11 1416 goto try_eft;
df613b96
AV		 1417
1418 tc = dma_alloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma,
1419 GFP_KERNEL);
1420 if (!tc) {
7c3df132
SK		 1421 ql_log(ql_log_warn, vha, 0x00be,
1422 "Unable to allocate (%d KB) for FCE.\n",
1423 FCE_SIZE / 1024);
17d98630 1424 goto try_eft;
df613b96
AV		 1425 }
1426
1427 memset(tc, 0, FCE_SIZE);
e315cd28 1428 rval = qla2x00_enable_fce_trace(vha, tc_dma, FCE_NUM_BUFFERS,
df613b96
AV		 1429 ha->fce_mb, &ha->fce_bufs);
1430 if (rval) {
7c3df132
SK		 1431 ql_log(ql_log_warn, vha, 0x00bf,
1432 "Unable to initialize FCE (%d).\n", rval);
df613b96
AV		 1433 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, tc,
1434 tc_dma);
1435 ha->flags.fce_enabled = 0;
17d98630 1436 goto try_eft;
df613b96 1437 }
cfb0919c 1438 ql_dbg(ql_dbg_init, vha, 0x00c0,
7c3df132 1439 "Allocate (%d KB) for FCE...\n", FCE_SIZE / 1024);
df613b96 1440
7d9dade3 1441 fce_size = sizeof(struct qla2xxx_fce_chain) + FCE_SIZE;
df613b96
AV		 1442 ha->flags.fce_enabled = 1;
1443 ha->fce_dma = tc_dma;
1444 ha->fce = tc;
436a7b11
AV		 1445try_eft:
1446 /* Allocate memory for Extended Trace Buffer. */
1447 tc = dma_alloc_coherent(&ha->pdev->dev, EFT_SIZE, &tc_dma,
1448 GFP_KERNEL);
1449 if (!tc) {
7c3df132
SK		 1450 ql_log(ql_log_warn, vha, 0x00c1,
1451 "Unable to allocate (%d KB) for EFT.\n",
1452 EFT_SIZE / 1024);
436a7b11
AV		 1453 goto cont_alloc;
1454 }
1455
1456 memset(tc, 0, EFT_SIZE);
e315cd28 1457 rval = qla2x00_enable_eft_trace(vha, tc_dma, EFT_NUM_BUFFERS);
436a7b11 1458 if (rval) {
7c3df132
SK		 1459 ql_log(ql_log_warn, vha, 0x00c2,
1460 "Unable to initialize EFT (%d).\n", rval);
436a7b11
AV		 1461 dma_free_coherent(&ha->pdev->dev, EFT_SIZE, tc,
1462 tc_dma);
1463 goto cont_alloc;
1464 }
cfb0919c 1465 ql_dbg(ql_dbg_init, vha, 0x00c3,
7c3df132 1466 "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024);
436a7b11
AV		 1467
1468 eft_size = EFT_SIZE;
1469 ha->eft_dma = tc_dma;
1470 ha->eft = tc;
d4e3e04d 1471 }
a7a167bf 1472cont_alloc:
73208dfd
AC		 1473 req_q_size = req->length * sizeof(request_t);
1474 rsp_q_size = rsp->length * sizeof(response_t);
a7a167bf
AV		 1475
1476 dump_size = offsetof(struct qla2xxx_fw_dump, isp);
2afa19a9 1477 dump_size += fixed_size + mem_size + req_q_size + rsp_q_size + eft_size;
bb99de67
AV		 1478 ha->chain_offset = dump_size;
1479 dump_size += mq_size + fce_size;
d4e3e04d
AV		 1480
1481 ha->fw_dump = vmalloc(dump_size);
a7a167bf 1482 if (!ha->fw_dump) {
7c3df132
SK		 1483 ql_log(ql_log_warn, vha, 0x00c4,
1484 "Unable to allocate (%d KB) for firmware dump.\n",
1485 dump_size / 1024);
a7a167bf 1486
e30d1756
MI		 1487 if (ha->fce) {
1488 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
1489 ha->fce_dma);
1490 ha->fce = NULL;
1491 ha->fce_dma = 0;
1492 }
1493
a7a167bf
AV		 1494 if (ha->eft) {
1495 dma_free_coherent(&ha->pdev->dev, eft_size, ha->eft,
1496 ha->eft_dma);
1497 ha->eft = NULL;
1498 ha->eft_dma = 0;
1499 }
1500 return;
1501 }
cfb0919c 1502 ql_dbg(ql_dbg_init, vha, 0x00c5,
7c3df132 1503 "Allocated (%d KB) for firmware dump.\n", dump_size / 1024);
a7a167bf
AV		 1504
1505 ha->fw_dump_len = dump_size;
1506 ha->fw_dump->signature[0] = 'Q';
1507 ha->fw_dump->signature[1] = 'L';
1508 ha->fw_dump->signature[2] = 'G';
1509 ha->fw_dump->signature[3] = 'C';
1510 ha->fw_dump->version = __constant_htonl(1);
1511
1512 ha->fw_dump->fixed_size = htonl(fixed_size);
1513 ha->fw_dump->mem_size = htonl(mem_size);
1514 ha->fw_dump->req_q_size = htonl(req_q_size);
1515 ha->fw_dump->rsp_q_size = htonl(rsp_q_size);
1516
1517 ha->fw_dump->eft_size = htonl(eft_size);
1518 ha->fw_dump->eft_addr_l = htonl(LSD(ha->eft_dma));
1519 ha->fw_dump->eft_addr_h = htonl(MSD(ha->eft_dma));
1520
1521 ha->fw_dump->header_size =
1522 htonl(offsetof(struct qla2xxx_fw_dump, isp));
0107109e
AV		 1523}
1524
18e7555a
AV		 1525static int
1526qla81xx_mpi_sync(scsi_qla_host_t *vha)
1527{
1528#define MPS_MASK 0xe0
1529 int rval;
1530 uint16_t dc;
1531 uint32_t dw;
18e7555a
AV		 1532
1533 if (!IS_QLA81XX(vha->hw))
1534 return QLA_SUCCESS;
1535
1536 rval = qla2x00_write_ram_word(vha, 0x7c00, 1);
1537 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1538 ql_log(ql_log_warn, vha, 0x0105,
1539 "Unable to acquire semaphore.\n");
18e7555a
AV		 1540 goto done;
1541 }
1542
1543 pci_read_config_word(vha->hw->pdev, 0x54, &dc);
1544 rval = qla2x00_read_ram_word(vha, 0x7a15, &dw);
1545 if (rval != QLA_SUCCESS) {
7c3df132 1546 ql_log(ql_log_warn, vha, 0x0067, "Unable to read sync.\n");
18e7555a
AV		 1547 goto done_release;
1548 }
1549
1550 dc &= MPS_MASK;
1551 if (dc == (dw & MPS_MASK))
1552 goto done_release;
1553
1554 dw &= ~MPS_MASK;
1555 dw |= dc;
1556 rval = qla2x00_write_ram_word(vha, 0x7a15, dw);
1557 if (rval != QLA_SUCCESS) {
7c3df132 1558 ql_log(ql_log_warn, vha, 0x0114, "Unable to gain sync.\n");
18e7555a
AV		 1559 }
1560
1561done_release:
1562 rval = qla2x00_write_ram_word(vha, 0x7c00, 0);
1563 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1564 ql_log(ql_log_warn, vha, 0x006d,
1565 "Unable to release semaphore.\n");
18e7555a
AV		 1566 }
1567
1568done:
1569 return rval;
1570}
1571
8d93f550
CD		 1572int
1573qla2x00_alloc_outstanding_cmds(struct qla_hw_data *ha, struct req_que *req)
1574{
1575 /* Don't try to reallocate the array */
1576 if (req->outstanding_cmds)
1577 return QLA_SUCCESS;
1578
1579 if (!IS_FWI2_CAPABLE(ha) || (ha->mqiobase &&
1580 (ql2xmultique_tag || ql2xmaxqueues > 1)))
1581 req->num_outstanding_cmds = DEFAULT_OUTSTANDING_COMMANDS;
1582 else {
1583 if (ha->fw_xcb_count <= ha->fw_iocb_count)
1584 req->num_outstanding_cmds = ha->fw_xcb_count;
1585 else
1586 req->num_outstanding_cmds = ha->fw_iocb_count;
1587 }
1588
1589 req->outstanding_cmds = kzalloc(sizeof(srb_t *) *
1590 req->num_outstanding_cmds, GFP_KERNEL);
1591
1592 if (!req->outstanding_cmds) {
1593 /*
1594 * Try to allocate a minimal size just so we can get through
1595 * initialization.
1596 */
1597 req->num_outstanding_cmds = MIN_OUTSTANDING_COMMANDS;
1598 req->outstanding_cmds = kzalloc(sizeof(srb_t *) *
1599 req->num_outstanding_cmds, GFP_KERNEL);
1600
1601 if (!req->outstanding_cmds) {
1602 ql_log(ql_log_fatal, NULL, 0x0126,
1603 "Failed to allocate memory for "
1604 "outstanding_cmds for req_que %p.\n", req);
1605 req->num_outstanding_cmds = 0;
1606 return QLA_FUNCTION_FAILED;
1607 }
1608 }
1609
1610 return QLA_SUCCESS;
1611}
1612
1da177e4
LT		 1613/**
1614 * qla2x00_setup_chip() - Load and start RISC firmware.
1615 * @ha: HA context
1616 *
1617 * Returns 0 on success.
1618 */
1619static int
e315cd28 1620qla2x00_setup_chip(scsi_qla_host_t *vha)
1da177e4 1621{
0107109e
AV		 1622 int rval;
1623 uint32_t srisc_address = 0;
e315cd28 1624 struct qla_hw_data *ha = vha->hw;
3db0652e
AV		 1625 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1626 unsigned long flags;
dda772e8 1627 uint16_t fw_major_version;
3db0652e 1628
7ec0effd 1629 if (IS_P3P_TYPE(ha)) {
a9083016 1630 rval = ha->isp_ops->load_risc(vha, &srisc_address);
14e303d9
AV		 1631 if (rval == QLA_SUCCESS) {
1632 qla2x00_stop_firmware(vha);
a9083016 1633 goto enable_82xx_npiv;
14e303d9 1634 } else
b963752f 1635 goto failed;
a9083016
GM		 1636 }
1637
3db0652e
AV		 1638 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
1639 /* Disable SRAM, Instruction RAM and GP RAM parity. */
1640 spin_lock_irqsave(&ha->hardware_lock, flags);
1641 WRT_REG_WORD(&reg->hccr, (HCCR_ENABLE_PARITY + 0x0));
1642 RD_REG_WORD(&reg->hccr);
1643 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1644 }
1da177e4 1645
18e7555a
AV		 1646 qla81xx_mpi_sync(vha);
1647
1da177e4 1648 /* Load firmware sequences */
e315cd28 1649 rval = ha->isp_ops->load_risc(vha, &srisc_address);
0107109e 1650 if (rval == QLA_SUCCESS) {
7c3df132
SK		 1651 ql_dbg(ql_dbg_init, vha, 0x00c9,
1652 "Verifying Checksum of loaded RISC code.\n");
1da177e4 1653
e315cd28 1654 rval = qla2x00_verify_checksum(vha, srisc_address);
1da177e4
LT		 1655 if (rval == QLA_SUCCESS) {
1656 /* Start firmware execution. */
7c3df132
SK		 1657 ql_dbg(ql_dbg_init, vha, 0x00ca,
1658 "Starting firmware.\n");
1da177e4 1659
e315cd28 1660 rval = qla2x00_execute_fw(vha, srisc_address);
1da177e4 1661 /* Retrieve firmware information. */
dda772e8 1662 if (rval == QLA_SUCCESS) {
a9083016 1663enable_82xx_npiv:
dda772e8 1664 fw_major_version = ha->fw_major_version;
7ec0effd 1665 if (IS_P3P_TYPE(ha))
3173167f 1666 qla82xx_check_md_needed(vha);
6246b8a1
GM		 1667 else
1668 rval = qla2x00_get_fw_version(vha);
ca9e9c3e
AV		 1669 if (rval != QLA_SUCCESS)
1670 goto failed;
2c3dfe3f 1671 ha->flags.npiv_supported = 0;
e315cd28 1672 if (IS_QLA2XXX_MIDTYPE(ha) &&
946fb891 1673 (ha->fw_attributes & BIT_2)) {
2c3dfe3f 1674 ha->flags.npiv_supported = 1;
4d0ea247
SJ		 1675 if ((!ha->max_npiv_vports) ||
1676 ((ha->max_npiv_vports + 1) %
eb66dc60 1677 MIN_MULTI_ID_FABRIC))
4d0ea247 1678 ha->max_npiv_vports =
eb66dc60 1679 MIN_MULTI_ID_FABRIC - 1;
4d0ea247 1680 }
24a08138 1681 qla2x00_get_resource_cnts(vha, NULL,
8d93f550 1682 &ha->fw_xcb_count, NULL, &ha->fw_iocb_count,
f3a0a77e 1683 &ha->max_npiv_vports, NULL);
d743de66 1684
8d93f550
CD		 1685 /*
1686 * Allocate the array of outstanding commands
1687 * now that we know the firmware resources.
1688 */
1689 rval = qla2x00_alloc_outstanding_cmds(ha,
1690 vha->req);
1691 if (rval != QLA_SUCCESS)
1692 goto failed;
1693
be5ea3cf 1694 if (!fw_major_version && ql2xallocfwdump
7ec0effd 1695 && !(IS_P3P_TYPE(ha)))
08de2844 1696 qla2x00_alloc_fw_dump(vha);
3b6e5b9d
CD		 1697 } else {
1698 goto failed;
1da177e4
LT		 1699 }
1700 } else {
7c3df132
SK		 1701 ql_log(ql_log_fatal, vha, 0x00cd,
1702 "ISP Firmware failed checksum.\n");
1703 goto failed;
1da177e4 1704 }
c74d88a4
AV		 1705 } else
1706 goto failed;
1da177e4 1707
3db0652e
AV		 1708 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
1709 /* Enable proper parity. */
1710 spin_lock_irqsave(&ha->hardware_lock, flags);
1711 if (IS_QLA2300(ha))
1712 /* SRAM parity */
1713 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x1);
1714 else
1715 /* SRAM, Instruction RAM and GP RAM parity */
1716 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x7);
1717 RD_REG_WORD(&reg->hccr);
1718 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1719 }
1720
6246b8a1
GM		 1721 if (IS_QLA83XX(ha))
1722 goto skip_fac_check;
1723
1d2874de
JC		 1724 if (rval == QLA_SUCCESS && IS_FAC_REQUIRED(ha)) {
1725 uint32_t size;
1726
1727 rval = qla81xx_fac_get_sector_size(vha, &size);
1728 if (rval == QLA_SUCCESS) {
1729 ha->flags.fac_supported = 1;
1730 ha->fdt_block_size = size << 2;
1731 } else {
7c3df132 1732 ql_log(ql_log_warn, vha, 0x00ce,
1d2874de
JC		 1733 "Unsupported FAC firmware (%d.%02d.%02d).\n",
1734 ha->fw_major_version, ha->fw_minor_version,
1735 ha->fw_subminor_version);
6246b8a1
GM		 1736skip_fac_check:
1737 if (IS_QLA83XX(ha)) {
1738 ha->flags.fac_supported = 0;
1739 rval = QLA_SUCCESS;
1740 }
1d2874de
JC		 1741 }
1742 }
ca9e9c3e 1743failed:
1da177e4 1744 if (rval) {
7c3df132
SK		 1745 ql_log(ql_log_fatal, vha, 0x00cf,
1746 "Setup chip ****FAILED****.\n");
1da177e4
LT		 1747 }
1748
1749 return (rval);
1750}
1751
1752/**
1753 * qla2x00_init_response_q_entries() - Initializes response queue entries.
1754 * @ha: HA context
1755 *
1756 * Beginning of request ring has initialization control block already built
1757 * by nvram config routine.
1758 *
1759 * Returns 0 on success.
1760 */
73208dfd
AC		 1761void
1762qla2x00_init_response_q_entries(struct rsp_que *rsp)
1da177e4
LT		 1763{
1764 uint16_t cnt;
1765 response_t *pkt;
1766
2afa19a9
AC		 1767 rsp->ring_ptr = rsp->ring;
1768 rsp->ring_index = 0;
1769 rsp->status_srb = NULL;
e315cd28
AC		 1770 pkt = rsp->ring_ptr;
1771 for (cnt = 0; cnt < rsp->length; cnt++) {
1da177e4
LT		 1772 pkt->signature = RESPONSE_PROCESSED;
1773 pkt++;
1774 }
1da177e4
LT		 1775}
1776
1777/**
1778 * qla2x00_update_fw_options() - Read and process firmware options.
1779 * @ha: HA context
1780 *
1781 * Returns 0 on success.
1782 */
abbd8870 1783void
e315cd28 1784qla2x00_update_fw_options(scsi_qla_host_t *vha)
1da177e4
LT		 1785{
1786 uint16_t swing, emphasis, tx_sens, rx_sens;
e315cd28 1787 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 1788
1789 memset(ha->fw_options, 0, sizeof(ha->fw_options));
e315cd28 1790 qla2x00_get_fw_options(vha, ha->fw_options);
1da177e4
LT		 1791
1792 if (IS_QLA2100(ha) || IS_QLA2200(ha))
1793 return;
1794
1795 /* Serial Link options. */
7c3df132
SK		 1796 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0115,
1797 "Serial link options.\n");
1798 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0109,
1799 (uint8_t *)&ha->fw_seriallink_options,
1800 sizeof(ha->fw_seriallink_options));
1da177e4
LT		 1801
1802 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1803 if (ha->fw_seriallink_options[3] & BIT_2) {
1804 ha->fw_options[1] |= FO1_SET_EMPHASIS_SWING;
1805
1806 /* 1G settings */
1807 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0);
1808 emphasis = (ha->fw_seriallink_options[2] &
1809 (BIT_4 | BIT_3)) >> 3;
1810 tx_sens = ha->fw_seriallink_options[0] &
fa2a1ce5 1811 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 1812 rx_sens = (ha->fw_seriallink_options[0] &
1813 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
1814 ha->fw_options[10] = (emphasis << 14) | (swing << 8);
1815 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
1816 if (rx_sens == 0x0)
1817 rx_sens = 0x3;
1818 ha->fw_options[10] |= (tx_sens << 4) | rx_sens;
1819 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
1820 ha->fw_options[10] |= BIT_5 |
1821 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
1822 (tx_sens & (BIT_1 | BIT_0));
1823
1824 /* 2G settings */
1825 swing = (ha->fw_seriallink_options[2] &
1826 (BIT_7 | BIT_6 | BIT_5)) >> 5;
1827 emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0);
1828 tx_sens = ha->fw_seriallink_options[1] &
fa2a1ce5 1829 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 1830 rx_sens = (ha->fw_seriallink_options[1] &
1831 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
1832 ha->fw_options[11] = (emphasis << 14) | (swing << 8);
1833 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
1834 if (rx_sens == 0x0)
1835 rx_sens = 0x3;
1836 ha->fw_options[11] |= (tx_sens << 4) | rx_sens;
1837 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
1838 ha->fw_options[11] |= BIT_5 |
1839 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
1840 (tx_sens & (BIT_1 | BIT_0));
1841 }
1842
1843 /* FCP2 options. */
1844 /* Return command IOCBs without waiting for an ABTS to complete. */
1845 ha->fw_options[3] |= BIT_13;
1846
1847 /* LED scheme. */
1848 if (ha->flags.enable_led_scheme)
1849 ha->fw_options[2] |= BIT_12;
1850
48c02fde 1851 /* Detect ISP6312. */
1852 if (IS_QLA6312(ha))
1853 ha->fw_options[2] |= BIT_13;
1854
1da177e4 1855 /* Update firmware options. */
e315cd28 1856 qla2x00_set_fw_options(vha, ha->fw_options);
1da177e4
LT		 1857}
1858
0107109e 1859void
e315cd28 1860qla24xx_update_fw_options(scsi_qla_host_t *vha)
0107109e
AV		 1861{
1862 int rval;
e315cd28 1863 struct qla_hw_data *ha = vha->hw;
0107109e 1864
7ec0effd 1865 if (IS_P3P_TYPE(ha))
a9083016
GM		 1866 return;
1867
0107109e 1868 /* Update Serial Link options. */
f94097ed 1869 if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0)
0107109e
AV		 1870 return;
1871
e315cd28 1872 rval = qla2x00_set_serdes_params(vha,
f94097ed 1873 le16_to_cpu(ha->fw_seriallink_options24[1]),
1874 le16_to_cpu(ha->fw_seriallink_options24[2]),
1875 le16_to_cpu(ha->fw_seriallink_options24[3]));
0107109e 1876 if (rval != QLA_SUCCESS) {
7c3df132 1877 ql_log(ql_log_warn, vha, 0x0104,
0107109e
AV		 1878 "Unable to update Serial Link options (%x).\n", rval);
1879 }
1880}
1881
abbd8870 1882void
e315cd28 1883qla2x00_config_rings(struct scsi_qla_host *vha)
abbd8870 1884{
e315cd28 1885 struct qla_hw_data *ha = vha->hw;
3d71644c 1886 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
73208dfd
AC		 1887 struct req_que *req = ha->req_q_map[0];
1888 struct rsp_que *rsp = ha->rsp_q_map[0];
abbd8870
AV		 1889
1890 /* Setup ring parameters in initialization control block. */
1891 ha->init_cb->request_q_outpointer = __constant_cpu_to_le16(0);
1892 ha->init_cb->response_q_inpointer = __constant_cpu_to_le16(0);
e315cd28
AC		 1893 ha->init_cb->request_q_length = cpu_to_le16(req->length);
1894 ha->init_cb->response_q_length = cpu_to_le16(rsp->length);
1895 ha->init_cb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
1896 ha->init_cb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
1897 ha->init_cb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
1898 ha->init_cb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
abbd8870
AV		 1899
1900 WRT_REG_WORD(ISP_REQ_Q_IN(ha, reg), 0);
1901 WRT_REG_WORD(ISP_REQ_Q_OUT(ha, reg), 0);
1902 WRT_REG_WORD(ISP_RSP_Q_IN(ha, reg), 0);
1903 WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), 0);
1904 RD_REG_WORD(ISP_RSP_Q_OUT(ha, reg)); /* PCI Posting. */
1905}
1906
0107109e 1907void
e315cd28 1908qla24xx_config_rings(struct scsi_qla_host *vha)
0107109e 1909{
e315cd28 1910 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 1911 device_reg_t __iomem *reg = ISP_QUE_REG(ha, 0);
1912 struct device_reg_2xxx __iomem *ioreg = &ha->iobase->isp;
1913 struct qla_msix_entry *msix;
0107109e 1914 struct init_cb_24xx *icb;
73208dfd
AC		 1915 uint16_t rid = 0;
1916 struct req_que *req = ha->req_q_map[0];
1917 struct rsp_que *rsp = ha->rsp_q_map[0];
0107109e 1918
6246b8a1 1919 /* Setup ring parameters in initialization control block. */
0107109e
AV		 1920 icb = (struct init_cb_24xx *)ha->init_cb;
1921 icb->request_q_outpointer = __constant_cpu_to_le16(0);
1922 icb->response_q_inpointer = __constant_cpu_to_le16(0);
e315cd28
AC		 1923 icb->request_q_length = cpu_to_le16(req->length);
1924 icb->response_q_length = cpu_to_le16(rsp->length);
1925 icb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
1926 icb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
1927 icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
1928 icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
0107109e 1929
2d70c103
NB		 1930 /* Setup ATIO queue dma pointers for target mode */
1931 icb->atio_q_inpointer = __constant_cpu_to_le16(0);
1932 icb->atio_q_length = cpu_to_le16(ha->tgt.atio_q_length);
1933 icb->atio_q_address[0] = cpu_to_le32(LSD(ha->tgt.atio_dma));
1934 icb->atio_q_address[1] = cpu_to_le32(MSD(ha->tgt.atio_dma));
1935
6246b8a1 1936 if (ha->mqenable || IS_QLA83XX(ha)) {
73208dfd
AC		 1937 icb->qos = __constant_cpu_to_le16(QLA_DEFAULT_QUE_QOS);
1938 icb->rid = __constant_cpu_to_le16(rid);
1939 if (ha->flags.msix_enabled) {
1940 msix = &ha->msix_entries[1];
7c3df132
SK		 1941 ql_dbg(ql_dbg_init, vha, 0x00fd,
1942 "Registering vector 0x%x for base que.\n",
1943 msix->entry);
73208dfd
AC		 1944 icb->msix = cpu_to_le16(msix->entry);
1945 }
1946 /* Use alternate PCI bus number */
1947 if (MSB(rid))
1948 icb->firmware_options_2 |=
1949 __constant_cpu_to_le32(BIT_19);
1950 /* Use alternate PCI devfn */
1951 if (LSB(rid))
1952 icb->firmware_options_2 |=
1953 __constant_cpu_to_le32(BIT_18);
1954
3155754a 1955 /* Use Disable MSIX Handshake mode for capable adapters */
6246b8a1
GM		 1956 if ((ha->fw_attributes & BIT_6) && (IS_MSIX_NACK_CAPABLE(ha)) &&
1957 (ha->flags.msix_enabled)) {
3155754a
AC		 1958 icb->firmware_options_2 &=
1959 __constant_cpu_to_le32(~BIT_22);
1960 ha->flags.disable_msix_handshake = 1;
7c3df132
SK		 1961 ql_dbg(ql_dbg_init, vha, 0x00fe,
1962 "MSIX Handshake Disable Mode turned on.\n");
3155754a
AC		 1963 } else {
1964 icb->firmware_options_2 |=
1965 __constant_cpu_to_le32(BIT_22);
1966 }
73208dfd 1967 icb->firmware_options_2 |= __constant_cpu_to_le32(BIT_23);
73208dfd
AC		 1968
1969 WRT_REG_DWORD(&reg->isp25mq.req_q_in, 0);
1970 WRT_REG_DWORD(&reg->isp25mq.req_q_out, 0);
1971 WRT_REG_DWORD(&reg->isp25mq.rsp_q_in, 0);
1972 WRT_REG_DWORD(&reg->isp25mq.rsp_q_out, 0);
1973 } else {
1974 WRT_REG_DWORD(&reg->isp24.req_q_in, 0);
1975 WRT_REG_DWORD(&reg->isp24.req_q_out, 0);
1976 WRT_REG_DWORD(&reg->isp24.rsp_q_in, 0);
1977 WRT_REG_DWORD(&reg->isp24.rsp_q_out, 0);
1978 }
aa230bc5 1979 qlt_24xx_config_rings(vha);
2d70c103 1980
73208dfd
AC		 1981 /* PCI posting */
1982 RD_REG_DWORD(&ioreg->hccr);
0107109e
AV		 1983}
1984
1da177e4
LT		 1985/**
1986 * qla2x00_init_rings() - Initializes firmware.
1987 * @ha: HA context
1988 *
1989 * Beginning of request ring has initialization control block already built
1990 * by nvram config routine.
1991 *
1992 * Returns 0 on success.
1993 */
8ae6d9c7 1994int
e315cd28 1995qla2x00_init_rings(scsi_qla_host_t *vha)
1da177e4
LT		 1996{
1997 int rval;
1998 unsigned long flags = 0;
29bdccbe 1999 int cnt, que;
e315cd28 2000 struct qla_hw_data *ha = vha->hw;
29bdccbe
AC		 2001 struct req_que *req;
2002 struct rsp_que *rsp;
2c3dfe3f
SJ		 2003 struct mid_init_cb_24xx *mid_init_cb =
2004 (struct mid_init_cb_24xx *) ha->init_cb;
1da177e4
LT		 2005
2006 spin_lock_irqsave(&ha->hardware_lock, flags);
2007
2008 /* Clear outstanding commands array. */
2afa19a9 2009 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe
AC		 2010 req = ha->req_q_map[que];
2011 if (!req)
2012 continue;
8d93f550 2013 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++)
29bdccbe 2014 req->outstanding_cmds[cnt] = NULL;
1da177e4 2015
2afa19a9 2016 req->current_outstanding_cmd = 1;
1da177e4 2017
29bdccbe
AC		 2018 /* Initialize firmware. */
2019 req->ring_ptr = req->ring;
2020 req->ring_index = 0;
2021 req->cnt = req->length;
2022 }
1da177e4 2023
2afa19a9 2024 for (que = 0; que < ha->max_rsp_queues; que++) {
29bdccbe
AC		 2025 rsp = ha->rsp_q_map[que];
2026 if (!rsp)
2027 continue;
29bdccbe 2028 /* Initialize response queue entries */
8ae6d9c7
GM		 2029 if (IS_QLAFX00(ha))
2030 qlafx00_init_response_q_entries(rsp);
2031 else
2032 qla2x00_init_response_q_entries(rsp);
29bdccbe 2033 }
1da177e4 2034
2d70c103
NB		 2035 ha->tgt.atio_ring_ptr = ha->tgt.atio_ring;
2036 ha->tgt.atio_ring_index = 0;
2037 /* Initialize ATIO queue entries */
2038 qlt_init_atio_q_entries(vha);
2039
e315cd28 2040 ha->isp_ops->config_rings(vha);
1da177e4
LT		 2041
2042 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2043
8ae6d9c7
GM		 2044 ql_dbg(ql_dbg_init, vha, 0x00d1, "Issue init firmware.\n");
2045
2046 if (IS_QLAFX00(ha)) {
2047 rval = qlafx00_init_firmware(vha, ha->init_cb_size);
2048 goto next_check;
2049 }
2050
1da177e4 2051 /* Update any ISP specific firmware options before initialization. */
e315cd28 2052 ha->isp_ops->update_fw_options(vha);
1da177e4 2053
605aa2bc 2054 if (ha->flags.npiv_supported) {
45980cc2 2055 if (ha->operating_mode == LOOP && !IS_CNA_CAPABLE(ha))
605aa2bc 2056 ha->max_npiv_vports = MIN_MULTI_ID_FABRIC - 1;
c48339de 2057 mid_init_cb->count = cpu_to_le16(ha->max_npiv_vports);
605aa2bc
LC		 2058 }
2059
24a08138
AV		 2060 if (IS_FWI2_CAPABLE(ha)) {
2061 mid_init_cb->options = __constant_cpu_to_le16(BIT_1);
2062 mid_init_cb->init_cb.execution_throttle =
2063 cpu_to_le16(ha->fw_xcb_count);
2064 }
2c3dfe3f 2065
e315cd28 2066 rval = qla2x00_init_firmware(vha, ha->init_cb_size);
8ae6d9c7 2067next_check:
1da177e4 2068 if (rval) {
7c3df132
SK		 2069 ql_log(ql_log_fatal, vha, 0x00d2,
2070 "Init Firmware **** FAILED ****.\n");
1da177e4 2071 } else {
7c3df132
SK		 2072 ql_dbg(ql_dbg_init, vha, 0x00d3,
2073 "Init Firmware -- success.\n");
1da177e4
LT		 2074 }
2075
2076 return (rval);
2077}
2078
2079/**
2080 * qla2x00_fw_ready() - Waits for firmware ready.
2081 * @ha: HA context
2082 *
2083 * Returns 0 on success.
2084 */
2085static int
e315cd28 2086qla2x00_fw_ready(scsi_qla_host_t *vha)
1da177e4
LT		 2087{
2088 int rval;
4d4df193 2089 unsigned long wtime, mtime, cs84xx_time;
1da177e4
LT		 2090 uint16_t min_wait; /* Minimum wait time if loop is down */
2091 uint16_t wait_time; /* Wait time if loop is coming ready */
656e8912 2092 uint16_t state[5];
e315cd28 2093 struct qla_hw_data *ha = vha->hw;
1da177e4 2094
8ae6d9c7
GM		 2095 if (IS_QLAFX00(vha->hw))
2096 return qlafx00_fw_ready(vha);
2097
1da177e4
LT		 2098 rval = QLA_SUCCESS;
2099
2100 /* 20 seconds for loop down. */
fa2a1ce5 2101 min_wait = 20;
1da177e4
LT		 2102
2103 /*
2104 * Firmware should take at most one RATOV to login, plus 5 seconds for
2105 * our own processing.
2106 */
2107 if ((wait_time = (ha->retry_count*ha->login_timeout) + 5) < min_wait) {
2108 wait_time = min_wait;
2109 }
2110
2111 /* Min wait time if loop down */
2112 mtime = jiffies + (min_wait * HZ);
2113
2114 /* wait time before firmware ready */
2115 wtime = jiffies + (wait_time * HZ);
2116
2117 /* Wait for ISP to finish LIP */
e315cd28 2118 if (!vha->flags.init_done)
7c3df132
SK		 2119 ql_log(ql_log_info, vha, 0x801e,
2120 "Waiting for LIP to complete.\n");
1da177e4
LT		 2121
2122 do {
5b939038 2123 memset(state, -1, sizeof(state));
e315cd28 2124 rval = qla2x00_get_firmware_state(vha, state);
1da177e4 2125 if (rval == QLA_SUCCESS) {
4d4df193 2126 if (state[0] < FSTATE_LOSS_OF_SYNC) {
e315cd28 2127 vha->device_flags &= ~DFLG_NO_CABLE;
1da177e4 2128 }
4d4df193 2129 if (IS_QLA84XX(ha) && state[0] != FSTATE_READY) {
7c3df132
SK		 2130 ql_dbg(ql_dbg_taskm, vha, 0x801f,
2131 "fw_state=%x 84xx=%x.\n", state[0],
2132 state[2]);
4d4df193
HK		 2133 if ((state[2] & FSTATE_LOGGED_IN) &&
2134 (state[2] & FSTATE_WAITING_FOR_VERIFY)) {
7c3df132
SK		 2135 ql_dbg(ql_dbg_taskm, vha, 0x8028,
2136 "Sending verify iocb.\n");
4d4df193
HK		 2137
2138 cs84xx_time = jiffies;
e315cd28 2139 rval = qla84xx_init_chip(vha);
7c3df132
SK		 2140 if (rval != QLA_SUCCESS) {
2141 ql_log(ql_log_warn,
cfb0919c 2142 vha, 0x8007,
7c3df132 2143 "Init chip failed.\n");
4d4df193 2144 break;
7c3df132 2145 }
4d4df193
HK		 2146
2147 /* Add time taken to initialize. */
2148 cs84xx_time = jiffies - cs84xx_time;
2149 wtime += cs84xx_time;
2150 mtime += cs84xx_time;
cfb0919c 2151 ql_dbg(ql_dbg_taskm, vha, 0x8008,
7c3df132
SK		 2152 "Increasing wait time by %ld. "
2153 "New time %ld.\n", cs84xx_time,
2154 wtime);
4d4df193
HK		 2155 }
2156 } else if (state[0] == FSTATE_READY) {
7c3df132
SK		 2157 ql_dbg(ql_dbg_taskm, vha, 0x8037,
2158 "F/W Ready - OK.\n");
1da177e4 2159
e315cd28 2160 qla2x00_get_retry_cnt(vha, &ha->retry_count,
1da177e4
LT		 2161 &ha->login_timeout, &ha->r_a_tov);
2162
2163 rval = QLA_SUCCESS;
2164 break;
2165 }
2166
2167 rval = QLA_FUNCTION_FAILED;
2168
e315cd28 2169 if (atomic_read(&vha->loop_down_timer) &&
4d4df193 2170 state[0] != FSTATE_READY) {
1da177e4 2171 /* Loop down. Timeout on min_wait for states
fa2a1ce5
AV		 2172 * other than Wait for Login.
2173 */
1da177e4 2174 if (time_after_eq(jiffies, mtime)) {
7c3df132 2175 ql_log(ql_log_info, vha, 0x8038,
1da177e4
LT		 2176 "Cable is unplugged...\n");
2177
e315cd28 2178 vha->device_flags |= DFLG_NO_CABLE;
1da177e4
LT		 2179 break;
2180 }
2181 }
2182 } else {
2183 /* Mailbox cmd failed. Timeout on min_wait. */
cdbb0a4f 2184 if (time_after_eq(jiffies, mtime) ||
7190575f 2185 ha->flags.isp82xx_fw_hung)
1da177e4
LT		 2186 break;
2187 }
2188
2189 if (time_after_eq(jiffies, wtime))
2190 break;
2191
2192 /* Delay for a while */
2193 msleep(500);
1da177e4
LT		 2194 } while (1);
2195
7c3df132
SK		 2196 ql_dbg(ql_dbg_taskm, vha, 0x803a,
2197 "fw_state=%x (%x, %x, %x, %x) " "curr time=%lx.\n", state[0],
2198 state[1], state[2], state[3], state[4], jiffies);
1da177e4 2199
cfb0919c 2200 if (rval && !(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132
SK		 2201 ql_log(ql_log_warn, vha, 0x803b,
2202 "Firmware ready **** FAILED ****.\n");
1da177e4
LT		 2203 }
2204
2205 return (rval);
2206}
2207
2208/*
2209* qla2x00_configure_hba
2210* Setup adapter context.
2211*
2212* Input:
2213* ha = adapter state pointer.
2214*
2215* Returns:
2216* 0 = success
2217*
2218* Context:
2219* Kernel context.
2220*/
2221static int
e315cd28 2222qla2x00_configure_hba(scsi_qla_host_t *vha)
1da177e4
LT		 2223{
2224 int rval;
2225 uint16_t loop_id;
2226 uint16_t topo;
2c3dfe3f 2227 uint16_t sw_cap;
1da177e4
LT		 2228 uint8_t al_pa;
2229 uint8_t area;
2230 uint8_t domain;
2231 char connect_type[22];
e315cd28 2232 struct qla_hw_data *ha = vha->hw;
f24b5cb8 2233 unsigned long flags;
61e1b269 2234 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4
LT		 2235
2236 /* Get host addresses. */
e315cd28 2237 rval = qla2x00_get_adapter_id(vha,
2c3dfe3f 2238 &loop_id, &al_pa, &area, &domain, &topo, &sw_cap);
1da177e4 2239 if (rval != QLA_SUCCESS) {
e315cd28 2240 if (LOOP_TRANSITION(vha) || atomic_read(&ha->loop_down_timer) ||
6246b8a1 2241 IS_CNA_CAPABLE(ha) ||
33135aa2 2242 (rval == QLA_COMMAND_ERROR && loop_id == 0x7)) {
7c3df132
SK		 2243 ql_dbg(ql_dbg_disc, vha, 0x2008,
2244 "Loop is in a transition state.\n");
33135aa2 2245 } else {
7c3df132
SK		 2246 ql_log(ql_log_warn, vha, 0x2009,
2247 "Unable to get host loop ID.\n");
61e1b269
JC		 2248 if (IS_FWI2_CAPABLE(ha) && (vha == base_vha) &&
2249 (rval == QLA_COMMAND_ERROR && loop_id == 0x1b)) {
2250 ql_log(ql_log_warn, vha, 0x1151,
2251 "Doing link init.\n");
2252 if (qla24xx_link_initialize(vha) == QLA_SUCCESS)
2253 return rval;
2254 }
e315cd28 2255 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
33135aa2 2256 }
1da177e4
LT		 2257 return (rval);
2258 }
2259
2260 if (topo == 4) {
7c3df132
SK		 2261 ql_log(ql_log_info, vha, 0x200a,
2262 "Cannot get topology - retrying.\n");
1da177e4
LT		 2263 return (QLA_FUNCTION_FAILED);
2264 }
2265
e315cd28 2266 vha->loop_id = loop_id;
1da177e4
LT		 2267
2268 /* initialize */
2269 ha->min_external_loopid = SNS_FIRST_LOOP_ID;
2270 ha->operating_mode = LOOP;
2c3dfe3f 2271 ha->switch_cap = 0;
1da177e4
LT		 2272
2273 switch (topo) {
2274 case 0:
7c3df132 2275 ql_dbg(ql_dbg_disc, vha, 0x200b, "HBA in NL topology.\n");
1da177e4
LT		 2276 ha->current_topology = ISP_CFG_NL;
2277 strcpy(connect_type, "(Loop)");
2278 break;
2279
2280 case 1:
7c3df132 2281 ql_dbg(ql_dbg_disc, vha, 0x200c, "HBA in FL topology.\n");
2c3dfe3f 2282 ha->switch_cap = sw_cap;
1da177e4
LT		 2283 ha->current_topology = ISP_CFG_FL;
2284 strcpy(connect_type, "(FL_Port)");
2285 break;
2286
2287 case 2:
7c3df132 2288 ql_dbg(ql_dbg_disc, vha, 0x200d, "HBA in N P2P topology.\n");
1da177e4
LT		 2289 ha->operating_mode = P2P;
2290 ha->current_topology = ISP_CFG_N;
2291 strcpy(connect_type, "(N_Port-to-N_Port)");
2292 break;
2293
2294 case 3:
7c3df132 2295 ql_dbg(ql_dbg_disc, vha, 0x200e, "HBA in F P2P topology.\n");
2c3dfe3f 2296 ha->switch_cap = sw_cap;
1da177e4
LT		 2297 ha->operating_mode = P2P;
2298 ha->current_topology = ISP_CFG_F;
2299 strcpy(connect_type, "(F_Port)");
2300 break;
2301
2302 default:
7c3df132
SK		 2303 ql_dbg(ql_dbg_disc, vha, 0x200f,
2304 "HBA in unknown topology %x, using NL.\n", topo);
1da177e4
LT		 2305 ha->current_topology = ISP_CFG_NL;
2306 strcpy(connect_type, "(Loop)");
2307 break;
2308 }
2309
2310 /* Save Host port and loop ID. */
2311 /* byte order - Big Endian */
e315cd28
AC		 2312 vha->d_id.b.domain = domain;
2313 vha->d_id.b.area = area;
2314 vha->d_id.b.al_pa = al_pa;
1da177e4 2315
f24b5cb8 2316 spin_lock_irqsave(&ha->vport_slock, flags);
2d70c103 2317 qlt_update_vp_map(vha, SET_AL_PA);
f24b5cb8 2318 spin_unlock_irqrestore(&ha->vport_slock, flags);
2d70c103 2319
e315cd28 2320 if (!vha->flags.init_done)
7c3df132
SK		 2321 ql_log(ql_log_info, vha, 0x2010,
2322 "Topology - %s, Host Loop address 0x%x.\n",
e315cd28 2323 connect_type, vha->loop_id);
1da177e4 2324
1da177e4
LT		 2325 return(rval);
2326}
2327
a9083016 2328inline void
e315cd28
AC		 2329qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len,
2330 char *def)
9bb9fcf2
AV		 2331{
2332 char *st, *en;
2333 uint16_t index;
e315cd28 2334 struct qla_hw_data *ha = vha->hw;
ab671149 2335 int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
6246b8a1 2336 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha);
9bb9fcf2
AV		 2337
2338 if (memcmp(model, BINZERO, len) != 0) {
2339 strncpy(ha->model_number, model, len);
2340 st = en = ha->model_number;
2341 en += len - 1;
2342 while (en > st) {
2343 if (*en != 0x20 && *en != 0x00)
2344 break;
2345 *en-- = '\0';
2346 }
2347
2348 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 2349 if (use_tbl &&
2350 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2 2351 index < QLA_MODEL_NAMES)
1ee27146
JC		 2352 strncpy(ha->model_desc,
2353 qla2x00_model_name[index * 2 + 1],
2354 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 2355 } else {
2356 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 2357 if (use_tbl &&
2358 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2
AV		 2359 index < QLA_MODEL_NAMES) {
2360 strcpy(ha->model_number,
2361 qla2x00_model_name[index * 2]);
1ee27146
JC		 2362 strncpy(ha->model_desc,
2363 qla2x00_model_name[index * 2 + 1],
2364 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 2365 } else {
2366 strcpy(ha->model_number, def);
2367 }
2368 }
1ee27146 2369 if (IS_FWI2_CAPABLE(ha))
e315cd28 2370 qla2xxx_get_vpd_field(vha, "\x82", ha->model_desc,
1ee27146 2371 sizeof(ha->model_desc));
9bb9fcf2
AV		 2372}
2373
4e08df3f
DM		 2374/* On sparc systems, obtain port and node WWN from firmware
2375 * properties.
2376 */
e315cd28 2377static void qla2xxx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, nvram_t *nv)
4e08df3f
DM		 2378{
2379#ifdef CONFIG_SPARC
e315cd28 2380 struct qla_hw_data *ha = vha->hw;
4e08df3f 2381 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 2382 struct device_node *dp = pci_device_to_OF_node(pdev);
2383 const u8 *val;
4e08df3f
DM		 2384 int len;
2385
2386 val = of_get_property(dp, "port-wwn", &len);
2387 if (val && len >= WWN_SIZE)
2388 memcpy(nv->port_name, val, WWN_SIZE);
2389
2390 val = of_get_property(dp, "node-wwn", &len);
2391 if (val && len >= WWN_SIZE)
2392 memcpy(nv->node_name, val, WWN_SIZE);
2393#endif
2394}
2395
1da177e4
LT		 2396/*
2397* NVRAM configuration for ISP 2xxx
2398*
2399* Input:
2400* ha = adapter block pointer.
2401*
2402* Output:
2403* initialization control block in response_ring
2404* host adapters parameters in host adapter block
2405*
2406* Returns:
2407* 0 = success.
2408*/
abbd8870 2409int
e315cd28 2410qla2x00_nvram_config(scsi_qla_host_t *vha)
1da177e4 2411{
4e08df3f 2412 int rval;
0107109e
AV		 2413 uint8_t chksum = 0;
2414 uint16_t cnt;
2415 uint8_t *dptr1, *dptr2;
e315cd28 2416 struct qla_hw_data *ha = vha->hw;
0107109e 2417 init_cb_t *icb = ha->init_cb;
281afe19
SJ		 2418 nvram_t *nv = ha->nvram;
2419 uint8_t *ptr = ha->nvram;
3d71644c 2420 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 2421
4e08df3f
DM		 2422 rval = QLA_SUCCESS;
2423
1da177e4 2424 /* Determine NVRAM starting address. */
0107109e 2425 ha->nvram_size = sizeof(nvram_t);
1da177e4
LT		 2426 ha->nvram_base = 0;
2427 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha))
2428 if ((RD_REG_WORD(&reg->ctrl_status) >> 14) == 1)
2429 ha->nvram_base = 0x80;
2430
2431 /* Get NVRAM data and calculate checksum. */
e315cd28 2432 ha->isp_ops->read_nvram(vha, ptr, ha->nvram_base, ha->nvram_size);
0107109e
AV		 2433 for (cnt = 0, chksum = 0; cnt < ha->nvram_size; cnt++)
2434 chksum += *ptr++;
1da177e4 2435
7c3df132
SK		 2436 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010f,
2437 "Contents of NVRAM.\n");
2438 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0110,
2439 (uint8_t *)nv, ha->nvram_size);
1da177e4
LT		 2440
2441 /* Bad NVRAM data, set defaults parameters. */
2442 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' ||
2443 nv->id[2] != 'P' || nv->id[3] != ' ' || nv->nvram_version < 1) {
2444 /* Reset NVRAM data. */
7c3df132 2445 ql_log(ql_log_warn, vha, 0x0064,
9e336520 2446 "Inconsistent NVRAM "
7c3df132
SK		 2447 "detected: checksum=0x%x id=%c version=0x%x.\n",
2448 chksum, nv->id[0], nv->nvram_version);
2449 ql_log(ql_log_warn, vha, 0x0065,
2450 "Falling back to "
2451 "functioning (yet invalid -- WWPN) defaults.\n");
4e08df3f
DM		 2452
2453 /*
2454 * Set default initialization control block.
2455 */
2456 memset(nv, 0, ha->nvram_size);
2457 nv->parameter_block_version = ICB_VERSION;
2458
2459 if (IS_QLA23XX(ha)) {
2460 nv->firmware_options[0] = BIT_2 | BIT_1;
2461 nv->firmware_options[1] = BIT_7 | BIT_5;
2462 nv->add_firmware_options[0] = BIT_5;
2463 nv->add_firmware_options[1] = BIT_5 | BIT_4;
2464 nv->frame_payload_size = __constant_cpu_to_le16(2048);
2465 nv->special_options[1] = BIT_7;
2466 } else if (IS_QLA2200(ha)) {
2467 nv->firmware_options[0] = BIT_2 | BIT_1;
2468 nv->firmware_options[1] = BIT_7 | BIT_5;
2469 nv->add_firmware_options[0] = BIT_5;
2470 nv->add_firmware_options[1] = BIT_5 | BIT_4;
2471 nv->frame_payload_size = __constant_cpu_to_le16(1024);
2472 } else if (IS_QLA2100(ha)) {
2473 nv->firmware_options[0] = BIT_3 | BIT_1;
2474 nv->firmware_options[1] = BIT_5;
2475 nv->frame_payload_size = __constant_cpu_to_le16(1024);
2476 }
2477
2478 nv->max_iocb_allocation = __constant_cpu_to_le16(256);
2479 nv->execution_throttle = __constant_cpu_to_le16(16);
2480 nv->retry_count = 8;
2481 nv->retry_delay = 1;
2482
2483 nv->port_name[0] = 33;
2484 nv->port_name[3] = 224;
2485 nv->port_name[4] = 139;
2486
e315cd28 2487 qla2xxx_nvram_wwn_from_ofw(vha, nv);
4e08df3f
DM		 2488
2489 nv->login_timeout = 4;
2490
2491 /*
2492 * Set default host adapter parameters
2493 */
2494 nv->host_p[1] = BIT_2;
2495 nv->reset_delay = 5;
2496 nv->port_down_retry_count = 8;
2497 nv->max_luns_per_target = __constant_cpu_to_le16(8);
2498 nv->link_down_timeout = 60;
2499
2500 rval = 1;
1da177e4
LT		 2501 }
2502
2503#if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2)
2504 /*
2505 * The SN2 does not provide BIOS emulation which means you can't change
2506 * potentially bogus BIOS settings. Force the use of default settings
2507 * for link rate and frame size. Hope that the rest of the settings
2508 * are valid.
2509 */
2510 if (ia64_platform_is("sn2")) {
2511 nv->frame_payload_size = __constant_cpu_to_le16(2048);
2512 if (IS_QLA23XX(ha))
2513 nv->special_options[1] = BIT_7;
2514 }
2515#endif
2516
2517 /* Reset Initialization control block */
0107109e 2518 memset(icb, 0, ha->init_cb_size);
1da177e4
LT		 2519
2520 /*
2521 * Setup driver NVRAM options.
2522 */
2523 nv->firmware_options[0] |= (BIT_6 | BIT_1);
2524 nv->firmware_options[0] &= ~(BIT_5 | BIT_4);
2525 nv->firmware_options[1] |= (BIT_5 | BIT_0);
2526 nv->firmware_options[1] &= ~BIT_4;
2527
2528 if (IS_QLA23XX(ha)) {
2529 nv->firmware_options[0] |= BIT_2;
2530 nv->firmware_options[0] &= ~BIT_3;
2d70c103 2531 nv->special_options[0] &= ~BIT_6;
0107109e 2532 nv->add_firmware_options[1] |= BIT_5 | BIT_4;
1da177e4
LT		 2533
2534 if (IS_QLA2300(ha)) {
2535 if (ha->fb_rev == FPM_2310) {
2536 strcpy(ha->model_number, "QLA2310");
2537 } else {
2538 strcpy(ha->model_number, "QLA2300");
2539 }
2540 } else {
e315cd28 2541 qla2x00_set_model_info(vha, nv->model_number,
9bb9fcf2 2542 sizeof(nv->model_number), "QLA23xx");
1da177e4
LT		 2543 }
2544 } else if (IS_QLA2200(ha)) {
2545 nv->firmware_options[0] |= BIT_2;
2546 /*
2547 * 'Point-to-point preferred, else loop' is not a safe
2548 * connection mode setting.
2549 */
2550 if ((nv->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) ==
2551 (BIT_5 | BIT_4)) {
2552 /* Force 'loop preferred, else point-to-point'. */
2553 nv->add_firmware_options[0] &= ~(BIT_6 | BIT_5 | BIT_4);
2554 nv->add_firmware_options[0] |= BIT_5;
2555 }
2556 strcpy(ha->model_number, "QLA22xx");
2557 } else /*if (IS_QLA2100(ha))*/ {
2558 strcpy(ha->model_number, "QLA2100");
2559 }
2560
2561 /*
2562 * Copy over NVRAM RISC parameter block to initialization control block.
2563 */
2564 dptr1 = (uint8_t *)icb;
2565 dptr2 = (uint8_t *)&nv->parameter_block_version;
2566 cnt = (uint8_t *)&icb->request_q_outpointer - (uint8_t *)&icb->version;
2567 while (cnt--)
2568 *dptr1++ = *dptr2++;
2569
2570 /* Copy 2nd half. */
2571 dptr1 = (uint8_t *)icb->add_firmware_options;
2572 cnt = (uint8_t *)icb->reserved_3 - (uint8_t *)icb->add_firmware_options;
2573 while (cnt--)
2574 *dptr1++ = *dptr2++;
2575
5341e868
AV		 2576 /* Use alternate WWN? */
2577 if (nv->host_p[1] & BIT_7) {
2578 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
2579 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
2580 }
2581
1da177e4
LT		 2582 /* Prepare nodename */
2583 if ((icb->firmware_options[1] & BIT_6) == 0) {
2584 /*
2585 * Firmware will apply the following mask if the nodename was
2586 * not provided.
2587 */
2588 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
2589 icb->node_name[0] &= 0xF0;
2590 }
2591
2592 /*
2593 * Set host adapter parameters.
2594 */
3ce8866c
SK		 2595
2596 /*
2597 * BIT_7 in the host-parameters section allows for modification to
2598 * internal driver logging.
2599 */
0181944f 2600 if (nv->host_p[0] & BIT_7)
cfb0919c 2601 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
1da177e4
LT		 2602 ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0);
2603 /* Always load RISC code on non ISP2[12]00 chips. */
2604 if (!IS_QLA2100(ha) && !IS_QLA2200(ha))
2605 ha->flags.disable_risc_code_load = 0;
2606 ha->flags.enable_lip_reset = ((nv->host_p[1] & BIT_1) ? 1 : 0);
2607 ha->flags.enable_lip_full_login = ((nv->host_p[1] & BIT_2) ? 1 : 0);
2608 ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0);
06c22bd1 2609 ha->flags.enable_led_scheme = (nv->special_options[1] & BIT_4) ? 1 : 0;
d4c760c2 2610 ha->flags.disable_serdes = 0;
1da177e4
LT		 2611
2612 ha->operating_mode =
2613 (icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4;
2614
2615 memcpy(ha->fw_seriallink_options, nv->seriallink_options,
2616 sizeof(ha->fw_seriallink_options));
2617
2618 /* save HBA serial number */
2619 ha->serial0 = icb->port_name[5];
2620 ha->serial1 = icb->port_name[6];
2621 ha->serial2 = icb->port_name[7];
e315cd28
AC		 2622 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
2623 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
1da177e4
LT		 2624
2625 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
2626
2627 ha->retry_count = nv->retry_count;
2628
2629 /* Set minimum login_timeout to 4 seconds. */
5b91490e 2630 if (nv->login_timeout != ql2xlogintimeout)
1da177e4
LT		 2631 nv->login_timeout = ql2xlogintimeout;
2632 if (nv->login_timeout < 4)
2633 nv->login_timeout = 4;
2634 ha->login_timeout = nv->login_timeout;
2635 icb->login_timeout = nv->login_timeout;
2636
00a537b8
AV		 2637 /* Set minimum RATOV to 100 tenths of a second. */
2638 ha->r_a_tov = 100;
1da177e4 2639
1da177e4
LT		 2640 ha->loop_reset_delay = nv->reset_delay;
2641
1da177e4
LT		 2642 /* Link Down Timeout = 0:
2643 *
2644 * When Port Down timer expires we will start returning
2645 * I/O's to OS with "DID_NO_CONNECT".
2646 *
2647 * Link Down Timeout != 0:
2648 *
2649 * The driver waits for the link to come up after link down
2650 * before returning I/Os to OS with "DID_NO_CONNECT".
fa2a1ce5 2651 */
1da177e4
LT		 2652 if (nv->link_down_timeout == 0) {
2653 ha->loop_down_abort_time =
354d6b21 2654 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
1da177e4
LT		 2655 } else {
2656 ha->link_down_timeout = nv->link_down_timeout;
2657 ha->loop_down_abort_time =
2658 (LOOP_DOWN_TIME - ha->link_down_timeout);
fa2a1ce5 2659 }
1da177e4 2660
1da177e4
LT		 2661 /*
2662 * Need enough time to try and get the port back.
2663 */
2664 ha->port_down_retry_count = nv->port_down_retry_count;
2665 if (qlport_down_retry)
2666 ha->port_down_retry_count = qlport_down_retry;
2667 /* Set login_retry_count */
2668 ha->login_retry_count = nv->retry_count;
2669 if (ha->port_down_retry_count == nv->port_down_retry_count &&
2670 ha->port_down_retry_count > 3)
2671 ha->login_retry_count = ha->port_down_retry_count;
2672 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
2673 ha->login_retry_count = ha->port_down_retry_count;
2674 if (ql2xloginretrycount)
2675 ha->login_retry_count = ql2xloginretrycount;
2676
1da177e4
LT		 2677 icb->lun_enables = __constant_cpu_to_le16(0);
2678 icb->command_resource_count = 0;
2679 icb->immediate_notify_resource_count = 0;
2680 icb->timeout = __constant_cpu_to_le16(0);
2681
2682 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
2683 /* Enable RIO */
2684 icb->firmware_options[0] &= ~BIT_3;
2685 icb->add_firmware_options[0] &=
2686 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
2687 icb->add_firmware_options[0] |= BIT_2;
2688 icb->response_accumulation_timer = 3;
2689 icb->interrupt_delay_timer = 5;
2690
e315cd28 2691 vha->flags.process_response_queue = 1;
1da177e4 2692 } else {
4fdfefe5 2693 /* Enable ZIO. */
e315cd28 2694 if (!vha->flags.init_done) {
4fdfefe5
AV		 2695 ha->zio_mode = icb->add_firmware_options[0] &
2696 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
2697 ha->zio_timer = icb->interrupt_delay_timer ?
2698 icb->interrupt_delay_timer: 2;
2699 }
1da177e4
LT		 2700 icb->add_firmware_options[0] &=
2701 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
e315cd28 2702 vha->flags.process_response_queue = 0;
4fdfefe5 2703 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d 2704 ha->zio_mode = QLA_ZIO_MODE_6;
2705
7c3df132 2706 ql_log(ql_log_info, vha, 0x0068,
4fdfefe5
AV		 2707 "ZIO mode %d enabled; timer delay (%d us).\n",
2708 ha->zio_mode, ha->zio_timer * 100);
1da177e4 2709
4fdfefe5
AV		 2710 icb->add_firmware_options[0] |= (uint8_t)ha->zio_mode;
2711 icb->interrupt_delay_timer = (uint8_t)ha->zio_timer;
e315cd28 2712 vha->flags.process_response_queue = 1;
1da177e4
LT		 2713 }
2714 }
2715
4e08df3f 2716 if (rval) {
7c3df132
SK		 2717 ql_log(ql_log_warn, vha, 0x0069,
2718 "NVRAM configuration failed.\n");
4e08df3f
DM		 2719 }
2720 return (rval);
1da177e4
LT		 2721}
2722
19a7b4ae
JSEC		 2723static void
2724qla2x00_rport_del(void *data)
2725{
2726 fc_port_t *fcport = data;
d97994dc 2727 struct fc_rport *rport;
2d70c103 2728 scsi_qla_host_t *vha = fcport->vha;
044d78e1 2729 unsigned long flags;
d97994dc 2730
044d78e1 2731 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
ac280b67 2732 rport = fcport->drport ? fcport->drport: fcport->rport;
d97994dc 2733 fcport->drport = NULL;
044d78e1 2734 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
2d70c103 2735 if (rport) {
d97994dc 2736 fc_remote_port_delete(rport);
2d70c103
NB		 2737 /*
2738 * Release the target mode FC NEXUS in qla_target.c code
2739 * if target mod is enabled.
2740 */
2741 qlt_fc_port_deleted(vha, fcport);
2742 }
19a7b4ae
JSEC		 2743}
2744
1da177e4
LT		 2745/**
2746 * qla2x00_alloc_fcport() - Allocate a generic fcport.
2747 * @ha: HA context
2748 * @flags: allocation flags
2749 *
2750 * Returns a pointer to the allocated fcport, or NULL, if none available.
2751 */
9a069e19 2752fc_port_t *
e315cd28 2753qla2x00_alloc_fcport(scsi_qla_host_t *vha, gfp_t flags)
1da177e4
LT		 2754{
2755 fc_port_t *fcport;
2756
bbfbbbc1
MK		 2757 fcport = kzalloc(sizeof(fc_port_t), flags);
2758 if (!fcport)
2759 return NULL;
1da177e4
LT		 2760
2761 /* Setup fcport template structure. */
e315cd28 2762 fcport->vha = vha;
1da177e4
LT		 2763 fcport->port_type = FCT_UNKNOWN;
2764 fcport->loop_id = FC_NO_LOOP_ID;
ec426e10 2765 qla2x00_set_fcport_state(fcport, FCS_UNCONFIGURED);
ad3e0eda 2766 fcport->supported_classes = FC_COS_UNSPECIFIED;
1da177e4 2767
bbfbbbc1 2768 return fcport;
1da177e4
LT		 2769}
2770
2771/*
2772 * qla2x00_configure_loop
2773 * Updates Fibre Channel Device Database with what is actually on loop.
2774 *
2775 * Input:
2776 * ha = adapter block pointer.
2777 *
2778 * Returns:
2779 * 0 = success.
2780 * 1 = error.
2781 * 2 = database was full and device was not configured.
2782 */
2783static int
e315cd28 2784qla2x00_configure_loop(scsi_qla_host_t *vha)
1da177e4
LT		 2785{
2786 int rval;
2787 unsigned long flags, save_flags;
e315cd28 2788 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 2789 rval = QLA_SUCCESS;
2790
2791 /* Get Initiator ID */
e315cd28
AC		 2792 if (test_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags)) {
2793 rval = qla2x00_configure_hba(vha);
1da177e4 2794 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2795 ql_dbg(ql_dbg_disc, vha, 0x2013,
2796 "Unable to configure HBA.\n");
1da177e4
LT		 2797 return (rval);
2798 }
2799 }
2800
e315cd28 2801 save_flags = flags = vha->dpc_flags;
7c3df132
SK		 2802 ql_dbg(ql_dbg_disc, vha, 0x2014,
2803 "Configure loop -- dpc flags = 0x%lx.\n", flags);
1da177e4
LT		 2804
2805 /*
2806 * If we have both an RSCN and PORT UPDATE pending then handle them
2807 * both at the same time.
2808 */
e315cd28
AC		 2809 clear_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2810 clear_bit(RSCN_UPDATE, &vha->dpc_flags);
1da177e4 2811
3064ff39
MH		 2812 qla2x00_get_data_rate(vha);
2813
1da177e4
LT		 2814 /* Determine what we need to do */
2815 if (ha->current_topology == ISP_CFG_FL &&
2816 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
2817
1da177e4
LT		 2818 set_bit(RSCN_UPDATE, &flags);
2819
2820 } else if (ha->current_topology == ISP_CFG_F &&
2821 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
2822
1da177e4
LT		 2823 set_bit(RSCN_UPDATE, &flags);
2824 clear_bit(LOCAL_LOOP_UPDATE, &flags);
21333b48
AV		 2825
2826 } else if (ha->current_topology == ISP_CFG_N) {
2827 clear_bit(RSCN_UPDATE, &flags);
1da177e4 2828
e315cd28 2829 } else if (!vha->flags.online ||
1da177e4
LT		 2830 (test_bit(ABORT_ISP_ACTIVE, &flags))) {
2831
1da177e4
LT		 2832 set_bit(RSCN_UPDATE, &flags);
2833 set_bit(LOCAL_LOOP_UPDATE, &flags);
2834 }
2835
2836 if (test_bit(LOCAL_LOOP_UPDATE, &flags)) {
7c3df132
SK		 2837 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
2838 ql_dbg(ql_dbg_disc, vha, 0x2015,
2839 "Loop resync needed, failing.\n");
1da177e4 2840 rval = QLA_FUNCTION_FAILED;
642ef983 2841 } else
e315cd28 2842 rval = qla2x00_configure_local_loop(vha);
1da177e4
LT		 2843 }
2844
2845 if (rval == QLA_SUCCESS && test_bit(RSCN_UPDATE, &flags)) {
7c3df132
SK		 2846 if (LOOP_TRANSITION(vha)) {
2847 ql_dbg(ql_dbg_disc, vha, 0x201e,
2848 "Needs RSCN update and loop transition.\n");
1da177e4 2849 rval = QLA_FUNCTION_FAILED;
7c3df132 2850 }
e315cd28
AC		 2851 else
2852 rval = qla2x00_configure_fabric(vha);
1da177e4
LT		 2853 }
2854
2855 if (rval == QLA_SUCCESS) {
e315cd28
AC		 2856 if (atomic_read(&vha->loop_down_timer) ||
2857 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4
LT		 2858 rval = QLA_FUNCTION_FAILED;
2859 } else {
e315cd28 2860 atomic_set(&vha->loop_state, LOOP_READY);
7c3df132
SK		 2861 ql_dbg(ql_dbg_disc, vha, 0x2069,
2862 "LOOP READY.\n");
1da177e4
LT		 2863 }
2864 }
2865
2866 if (rval) {
7c3df132
SK		 2867 ql_dbg(ql_dbg_disc, vha, 0x206a,
2868 "%s *** FAILED ***.\n", __func__);
1da177e4 2869 } else {
7c3df132
SK		 2870 ql_dbg(ql_dbg_disc, vha, 0x206b,
2871 "%s: exiting normally.\n", __func__);
1da177e4
LT		 2872 }
2873
cc3ef7bc 2874 /* Restore state if a resync event occurred during processing */
e315cd28 2875 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4 2876 if (test_bit(LOCAL_LOOP_UPDATE, &save_flags))
e315cd28 2877 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
f4658b6c 2878 if (test_bit(RSCN_UPDATE, &save_flags)) {
e315cd28 2879 set_bit(RSCN_UPDATE, &vha->dpc_flags);
f4658b6c 2880 }
1da177e4
LT		 2881 }
2882
2883 return (rval);
2884}
2885
2886
2887
2888/*
2889 * qla2x00_configure_local_loop
2890 * Updates Fibre Channel Device Database with local loop devices.
2891 *
2892 * Input:
2893 * ha = adapter block pointer.
2894 *
2895 * Returns:
2896 * 0 = success.
2897 */
2898static int
e315cd28 2899qla2x00_configure_local_loop(scsi_qla_host_t *vha)
1da177e4
LT		 2900{
2901 int rval, rval2;
2902 int found_devs;
2903 int found;
2904 fc_port_t *fcport, *new_fcport;
2905
2906 uint16_t index;
2907 uint16_t entries;
2908 char *id_iter;
2909 uint16_t loop_id;
2910 uint8_t domain, area, al_pa;
e315cd28 2911 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 2912
2913 found_devs = 0;
2914 new_fcport = NULL;
642ef983 2915 entries = MAX_FIBRE_DEVICES_LOOP;
1da177e4 2916
1da177e4 2917 /* Get list of logged in devices. */
642ef983 2918 memset(ha->gid_list, 0, qla2x00_gid_list_size(ha));
e315cd28 2919 rval = qla2x00_get_id_list(vha, ha->gid_list, ha->gid_list_dma,
1da177e4
LT		 2920 &entries);
2921 if (rval != QLA_SUCCESS)
2922 goto cleanup_allocation;
2923
7c3df132
SK		 2924 ql_dbg(ql_dbg_disc, vha, 0x2017,
2925 "Entries in ID list (%d).\n", entries);
2926 ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha, 0x2075,
2927 (uint8_t *)ha->gid_list,
2928 entries * sizeof(struct gid_list_info));
1da177e4
LT		 2929
2930 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 2931 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 2932 if (new_fcport == NULL) {
7c3df132
SK		 2933 ql_log(ql_log_warn, vha, 0x2018,
2934 "Memory allocation failed for fcport.\n");
1da177e4
LT		 2935 rval = QLA_MEMORY_ALLOC_FAILED;
2936 goto cleanup_allocation;
2937 }
2938 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
2939
2940 /*
2941 * Mark local devices that were present with FCF_DEVICE_LOST for now.
2942 */
e315cd28 2943 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 2944 if (atomic_read(&fcport->state) == FCS_ONLINE &&
2945 fcport->port_type != FCT_BROADCAST &&
2946 (fcport->flags & FCF_FABRIC_DEVICE) == 0) {
2947
7c3df132
SK		 2948 ql_dbg(ql_dbg_disc, vha, 0x2019,
2949 "Marking port lost loop_id=0x%04x.\n",
2950 fcport->loop_id);
1da177e4 2951
ec426e10 2952 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 2953 }
2954 }
2955
2956 /* Add devices to port list. */
2957 id_iter = (char *)ha->gid_list;
2958 for (index = 0; index < entries; index++) {
2959 domain = ((struct gid_list_info *)id_iter)->domain;
2960 area = ((struct gid_list_info *)id_iter)->area;
2961 al_pa = ((struct gid_list_info *)id_iter)->al_pa;
abbd8870 2962 if (IS_QLA2100(ha) || IS_QLA2200(ha))
1da177e4
LT		 2963 loop_id = (uint16_t)
2964 ((struct gid_list_info *)id_iter)->loop_id_2100;
abbd8870 2965 else
1da177e4
LT		 2966 loop_id = le16_to_cpu(
2967 ((struct gid_list_info *)id_iter)->loop_id);
abbd8870 2968 id_iter += ha->gid_list_info_size;
1da177e4
LT		 2969
2970 /* Bypass reserved domain fields. */
2971 if ((domain & 0xf0) == 0xf0)
2972 continue;
2973
2974 /* Bypass if not same domain and area of adapter. */
f7d289f6 2975 if (area && domain &&
e315cd28 2976 (area != vha->d_id.b.area || domain != vha->d_id.b.domain))
1da177e4
LT		 2977 continue;
2978
2979 /* Bypass invalid local loop ID. */
2980 if (loop_id > LAST_LOCAL_LOOP_ID)
2981 continue;
2982
370d550e
AE		 2983 memset(new_fcport, 0, sizeof(fc_port_t));
2984
1da177e4
LT		 2985 /* Fill in member data. */
2986 new_fcport->d_id.b.domain = domain;
2987 new_fcport->d_id.b.area = area;
2988 new_fcport->d_id.b.al_pa = al_pa;
2989 new_fcport->loop_id = loop_id;
e315cd28 2990 rval2 = qla2x00_get_port_database(vha, new_fcport, 0);
1da177e4 2991 if (rval2 != QLA_SUCCESS) {
7c3df132
SK		 2992 ql_dbg(ql_dbg_disc, vha, 0x201a,
2993 "Failed to retrieve fcport information "
2994 "-- get_port_database=%x, loop_id=0x%04x.\n",
2995 rval2, new_fcport->loop_id);
2996 ql_dbg(ql_dbg_disc, vha, 0x201b,
2997 "Scheduling resync.\n");
e315cd28 2998 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4
LT		 2999 continue;
3000 }
3001
3002 /* Check for matching device in port list. */
3003 found = 0;
3004 fcport = NULL;
e315cd28 3005 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 3006 if (memcmp(new_fcport->port_name, fcport->port_name,
3007 WWN_SIZE))
3008 continue;
3009
ddb9b126 3010 fcport->flags &= ~FCF_FABRIC_DEVICE;
1da177e4
LT		 3011 fcport->loop_id = new_fcport->loop_id;
3012 fcport->port_type = new_fcport->port_type;
3013 fcport->d_id.b24 = new_fcport->d_id.b24;
3014 memcpy(fcport->node_name, new_fcport->node_name,
3015 WWN_SIZE);
3016
3017 found++;
3018 break;
3019 }
3020
3021 if (!found) {
3022 /* New device, add to fcports list. */
e315cd28 3023 list_add_tail(&new_fcport->list, &vha->vp_fcports);
1da177e4
LT		 3024
3025 /* Allocate a new replacement fcport. */
3026 fcport = new_fcport;
e315cd28 3027 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3028 if (new_fcport == NULL) {
7c3df132
SK		 3029 ql_log(ql_log_warn, vha, 0x201c,
3030 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 3031 rval = QLA_MEMORY_ALLOC_FAILED;
3032 goto cleanup_allocation;
3033 }
3034 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
3035 }
3036
d8b45213 3037 /* Base iIDMA settings on HBA port speed. */
a3cbdfad 3038 fcport->fp_speed = ha->link_data_rate;
d8b45213 3039
e315cd28 3040 qla2x00_update_fcport(vha, fcport);
1da177e4
LT		 3041
3042 found_devs++;
3043 }
3044
3045cleanup_allocation:
c9475cb0 3046 kfree(new_fcport);
1da177e4
LT		 3047
3048 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3049 ql_dbg(ql_dbg_disc, vha, 0x201d,
3050 "Configure local loop error exit: rval=%x.\n", rval);
1da177e4
LT		 3051 }
3052
1da177e4
LT		 3053 return (rval);
3054}
3055
d8b45213 3056static void
e315cd28 3057qla2x00_iidma_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
d8b45213 3058{
d8b45213 3059 int rval;
1bb39548 3060 uint16_t mb[4];
e315cd28 3061 struct qla_hw_data *ha = vha->hw;
d8b45213 3062
c76f2c01 3063 if (!IS_IIDMA_CAPABLE(ha))
d8b45213
AV		 3064 return;
3065
c9afb9a2
GM		 3066 if (atomic_read(&fcport->state) != FCS_ONLINE)
3067 return;
3068
39bd9622
AV		 3069 if (fcport->fp_speed == PORT_SPEED_UNKNOWN ||
3070 fcport->fp_speed > ha->link_data_rate)
d8b45213
AV		 3071 return;
3072
e315cd28 3073 rval = qla2x00_set_idma_speed(vha, fcport->loop_id, fcport->fp_speed,
a3cbdfad 3074 mb);
d8b45213 3075 if (rval != QLA_SUCCESS) {
7c3df132 3076 ql_dbg(ql_dbg_disc, vha, 0x2004,
7b833558
OK		 3077 "Unable to adjust iIDMA %8phN -- %04x %x %04x %04x.\n",
3078 fcport->port_name, rval, fcport->fp_speed, mb[0], mb[1]);
d8b45213 3079 } else {
7c3df132 3080 ql_dbg(ql_dbg_disc, vha, 0x2005,
7b833558 3081 "iIDMA adjusted to %s GB/s on %8phN.\n",
d0297c9a 3082 qla2x00_get_link_speed_str(ha, fcport->fp_speed),
7b833558 3083 fcport->port_name);
d8b45213
AV		 3084 }
3085}
3086
23be331d 3087static void
e315cd28 3088qla2x00_reg_remote_port(scsi_qla_host_t *vha, fc_port_t *fcport)
8482e118 3089{
3090 struct fc_rport_identifiers rport_ids;
bdf79621 3091 struct fc_rport *rport;
044d78e1 3092 unsigned long flags;
8482e118 3093
ac280b67 3094 qla2x00_rport_del(fcport);
8482e118 3095
f8b02a85
AV		 3096 rport_ids.node_name = wwn_to_u64(fcport->node_name);
3097 rport_ids.port_name = wwn_to_u64(fcport->port_name);
8482e118 3098 rport_ids.port_id = fcport->d_id.b.domain << 16 |
3099 fcport->d_id.b.area << 8 | fcport->d_id.b.al_pa;
77d74143 3100 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
e315cd28 3101 fcport->rport = rport = fc_remote_port_add(vha->host, 0, &rport_ids);
77d74143 3102 if (!rport) {
7c3df132
SK		 3103 ql_log(ql_log_warn, vha, 0x2006,
3104 "Unable to allocate fc remote port.\n");
77d74143
AV		 3105 return;
3106 }
2d70c103
NB		 3107 /*
3108 * Create target mode FC NEXUS in qla_target.c if target mode is
3109 * enabled..
3110 */
3111 qlt_fc_port_added(vha, fcport);
3112
044d78e1 3113 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
19a7b4ae 3114 *((fc_port_t **)rport->dd_data) = fcport;
044d78e1 3115 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
d97994dc 3116
ad3e0eda 3117 rport->supported_classes = fcport->supported_classes;
77d74143 3118
8482e118 3119 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
3120 if (fcport->port_type == FCT_INITIATOR)
3121 rport_ids.roles |= FC_RPORT_ROLE_FCP_INITIATOR;
3122 if (fcport->port_type == FCT_TARGET)
3123 rport_ids.roles |= FC_RPORT_ROLE_FCP_TARGET;
77d74143 3124 fc_remote_port_rolechg(rport, rport_ids.roles);
1da177e4
LT		 3125}
3126
23be331d
AB		 3127/*
3128 * qla2x00_update_fcport
3129 * Updates device on list.
3130 *
3131 * Input:
3132 * ha = adapter block pointer.
3133 * fcport = port structure pointer.
3134 *
3135 * Return:
3136 * 0 - Success
3137 * BIT_0 - error
3138 *
3139 * Context:
3140 * Kernel context.
3141 */
3142void
e315cd28 3143qla2x00_update_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
23be331d 3144{
e315cd28 3145 fcport->vha = vha;
8ae6d9c7
GM		 3146
3147 if (IS_QLAFX00(vha->hw)) {
3148 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
3149 qla2x00_reg_remote_port(vha, fcport);
3150 return;
3151 }
23be331d 3152 fcport->login_retry = 0;
5ff1d584 3153 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
23be331d 3154
1f93da52 3155 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
e315cd28 3156 qla2x00_iidma_fcport(vha, fcport);
21090cbe 3157 qla24xx_update_fcport_fcp_prio(vha, fcport);
e315cd28 3158 qla2x00_reg_remote_port(vha, fcport);
23be331d
AB		 3159}
3160
1da177e4
LT		 3161/*
3162 * qla2x00_configure_fabric
3163 * Setup SNS devices with loop ID's.
3164 *
3165 * Input:
3166 * ha = adapter block pointer.
3167 *
3168 * Returns:
3169 * 0 = success.
3170 * BIT_0 = error
3171 */
3172static int
e315cd28 3173qla2x00_configure_fabric(scsi_qla_host_t *vha)
1da177e4 3174{
b3b02e6e 3175 int rval;
e452ceb6 3176 fc_port_t *fcport, *fcptemp;
1da177e4
LT		 3177 uint16_t next_loopid;
3178 uint16_t mb[MAILBOX_REGISTER_COUNT];
0107109e 3179 uint16_t loop_id;
1da177e4 3180 LIST_HEAD(new_fcports);
e315cd28
AC		 3181 struct qla_hw_data *ha = vha->hw;
3182 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1da177e4
LT		 3183
3184 /* If FL port exists, then SNS is present */
e428924c 3185 if (IS_FWI2_CAPABLE(ha))
0107109e
AV		 3186 loop_id = NPH_F_PORT;
3187 else
3188 loop_id = SNS_FL_PORT;
e315cd28 3189 rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_node_name, 1);
1da177e4 3190 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3191 ql_dbg(ql_dbg_disc, vha, 0x201f,
3192 "MBX_GET_PORT_NAME failed, No FL Port.\n");
1da177e4 3193
e315cd28 3194 vha->device_flags &= ~SWITCH_FOUND;
1da177e4
LT		 3195 return (QLA_SUCCESS);
3196 }
e315cd28 3197 vha->device_flags |= SWITCH_FOUND;
1da177e4 3198
1da177e4 3199 do {
cca5335c
AV		 3200 /* FDMI support. */
3201 if (ql2xfdmienable &&
e315cd28
AC		 3202 test_and_clear_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags))
3203 qla2x00_fdmi_register(vha);
cca5335c 3204
1da177e4 3205 /* Ensure we are logged into the SNS. */
e428924c 3206 if (IS_FWI2_CAPABLE(ha))
0107109e
AV		 3207 loop_id = NPH_SNS;
3208 else
3209 loop_id = SIMPLE_NAME_SERVER;
0b91d116
CD		 3210 rval = ha->isp_ops->fabric_login(vha, loop_id, 0xff, 0xff,
3211 0xfc, mb, BIT_1|BIT_0);
3212 if (rval != QLA_SUCCESS) {
3213 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
e452ceb6 3214 return rval;
0b91d116 3215 }
1da177e4 3216 if (mb[0] != MBS_COMMAND_COMPLETE) {
7c3df132
SK		 3217 ql_dbg(ql_dbg_disc, vha, 0x2042,
3218 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x "
3219 "mb[6]=%x mb[7]=%x.\n", loop_id, mb[0], mb[1],
3220 mb[2], mb[6], mb[7]);
1da177e4
LT		 3221 return (QLA_SUCCESS);
3222 }
3223
e315cd28
AC		 3224 if (test_and_clear_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags)) {
3225 if (qla2x00_rft_id(vha)) {
1da177e4 3226 /* EMPTY */
7c3df132
SK		 3227 ql_dbg(ql_dbg_disc, vha, 0x2045,
3228 "Register FC-4 TYPE failed.\n");
1da177e4 3229 }
e315cd28 3230 if (qla2x00_rff_id(vha)) {
1da177e4 3231 /* EMPTY */
7c3df132
SK		 3232 ql_dbg(ql_dbg_disc, vha, 0x2049,
3233 "Register FC-4 Features failed.\n");
1da177e4 3234 }
e315cd28 3235 if (qla2x00_rnn_id(vha)) {
1da177e4 3236 /* EMPTY */
7c3df132
SK		 3237 ql_dbg(ql_dbg_disc, vha, 0x204f,
3238 "Register Node Name failed.\n");
e315cd28 3239 } else if (qla2x00_rsnn_nn(vha)) {
1da177e4 3240 /* EMPTY */
7c3df132
SK		 3241 ql_dbg(ql_dbg_disc, vha, 0x2053,
3242 "Register Symobilic Node Name failed.\n");
1da177e4
LT		 3243 }
3244 }
3245
827210ba
JC		 3246#define QLA_FCPORT_SCAN 1
3247#define QLA_FCPORT_FOUND 2
3248
3249 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3250 fcport->scan_state = QLA_FCPORT_SCAN;
3251 }
3252
e315cd28 3253 rval = qla2x00_find_all_fabric_devs(vha, &new_fcports);
1da177e4
LT		 3254 if (rval != QLA_SUCCESS)
3255 break;
3256
e452ceb6
JC		 3257 /*
3258 * Logout all previous fabric devices marked lost, except
3259 * FCP2 devices.
3260 */
e315cd28
AC		 3261 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3262 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
1da177e4
LT		 3263 break;
3264
3265 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0)
3266 continue;
3267
827210ba 3268 if (fcport->scan_state == QLA_FCPORT_SCAN &&
b3b02e6e 3269 atomic_read(&fcport->state) == FCS_ONLINE) {
e315cd28 3270 qla2x00_mark_device_lost(vha, fcport,
d97994dc 3271 ql2xplogiabsentdevice, 0);
1da177e4 3272 if (fcport->loop_id != FC_NO_LOOP_ID &&
f08b7251 3273 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
1da177e4
LT		 3274 fcport->port_type != FCT_INITIATOR &&
3275 fcport->port_type != FCT_BROADCAST) {
e315cd28 3276 ha->isp_ops->fabric_logout(vha,
1c7c6357
AV		 3277 fcport->loop_id,
3278 fcport->d_id.b.domain,
3279 fcport->d_id.b.area,
3280 fcport->d_id.b.al_pa);
e452ceb6 3281 fcport->loop_id = FC_NO_LOOP_ID;
1da177e4
LT		 3282 }
3283 }
e452ceb6 3284 }
1da177e4 3285
e452ceb6
JC		 3286 /* Starting free loop ID. */
3287 next_loopid = ha->min_external_loopid;
3288
3289 /*
3290 * Scan through our port list and login entries that need to be
3291 * logged in.
3292 */
3293 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3294 if (atomic_read(&vha->loop_down_timer) ||
3295 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
3296 break;
3297
3298 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0 ||
3299 (fcport->flags & FCF_LOGIN_NEEDED) == 0)
3300 continue;
3301
3302 if (fcport->loop_id == FC_NO_LOOP_ID) {
3303 fcport->loop_id = next_loopid;
3304 rval = qla2x00_find_new_loop_id(
3305 base_vha, fcport);
3306 if (rval != QLA_SUCCESS) {
3307 /* Ran out of IDs to use */
3308 break;
1da177e4
LT		 3309 }
3310 }
e452ceb6
JC		 3311 /* Login and update database */
3312 qla2x00_fabric_dev_login(vha, fcport, &next_loopid);
3313 }
3314
3315 /* Exit if out of loop IDs. */
3316 if (rval != QLA_SUCCESS) {
3317 break;
3318 }
3319
3320 /*
3321 * Login and add the new devices to our port list.
3322 */
3323 list_for_each_entry_safe(fcport, fcptemp, &new_fcports, list) {
3324 if (atomic_read(&vha->loop_down_timer) ||
3325 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
3326 break;
3327
3328 /* Find a new loop ID to use. */
3329 fcport->loop_id = next_loopid;
3330 rval = qla2x00_find_new_loop_id(base_vha, fcport);
3331 if (rval != QLA_SUCCESS) {
3332 /* Ran out of IDs to use */
3333 break;
3334 }
1da177e4 3335
bdf79621 3336 /* Login and update database */
e315cd28 3337 qla2x00_fabric_dev_login(vha, fcport, &next_loopid);
e452ceb6
JC		 3338
3339 list_move_tail(&fcport->list, &vha->vp_fcports);
1da177e4
LT		 3340 }
3341 } while (0);
3342
e452ceb6
JC		 3343 /* Free all new device structures not processed. */
3344 list_for_each_entry_safe(fcport, fcptemp, &new_fcports, list) {
3345 list_del(&fcport->list);
3346 kfree(fcport);
3347 }
3348
1da177e4 3349 if (rval) {
7c3df132
SK		 3350 ql_dbg(ql_dbg_disc, vha, 0x2068,
3351 "Configure fabric error exit rval=%d.\n", rval);
1da177e4
LT		 3352 }
3353
3354 return (rval);
3355}
3356
1da177e4
LT		 3357/*
3358 * qla2x00_find_all_fabric_devs
3359 *
3360 * Input:
3361 * ha = adapter block pointer.
3362 * dev = database device entry pointer.
3363 *
3364 * Returns:
3365 * 0 = success.
3366 *
3367 * Context:
3368 * Kernel context.
3369 */
3370static int
e315cd28
AC		 3371qla2x00_find_all_fabric_devs(scsi_qla_host_t *vha,
3372 struct list_head *new_fcports)
1da177e4
LT		 3373{
3374 int rval;
3375 uint16_t loop_id;
3376 fc_port_t *fcport, *new_fcport, *fcptemp;
3377 int found;
3378
3379 sw_info_t *swl;
3380 int swl_idx;
3381 int first_dev, last_dev;
1516ef44 3382 port_id_t wrap = {}, nxt_d_id;
e315cd28 3383 struct qla_hw_data *ha = vha->hw;
bb4cf5b7 3384 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1da177e4
LT		 3385
3386 rval = QLA_SUCCESS;
3387
3388 /* Try GID_PT to get device list, else GAN. */
7a67735b 3389 if (!ha->swl)
642ef983 3390 ha->swl = kcalloc(ha->max_fibre_devices, sizeof(sw_info_t),
7a67735b
AV		 3391 GFP_KERNEL);
3392 swl = ha->swl;
bbfbbbc1 3393 if (!swl) {
1da177e4 3394 /*EMPTY*/
7c3df132
SK		 3395 ql_dbg(ql_dbg_disc, vha, 0x2054,
3396 "GID_PT allocations failed, fallback on GA_NXT.\n");
1da177e4 3397 } else {
642ef983 3398 memset(swl, 0, ha->max_fibre_devices * sizeof(sw_info_t));
e315cd28 3399 if (qla2x00_gid_pt(vha, swl) != QLA_SUCCESS) {
1da177e4 3400 swl = NULL;
e315cd28 3401 } else if (qla2x00_gpn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 3402 swl = NULL;
e315cd28 3403 } else if (qla2x00_gnn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 3404 swl = NULL;
e5896bd5 3405 } else if (ql2xiidmaenable &&
e315cd28
AC		 3406 qla2x00_gfpn_id(vha, swl) == QLA_SUCCESS) {
3407 qla2x00_gpsc(vha, swl);
1da177e4 3408 }
e8c72ba5
CD		 3409
3410 /* If other queries succeeded probe for FC-4 type */
3411 if (swl)
3412 qla2x00_gff_id(vha, swl);
1da177e4
LT		 3413 }
3414 swl_idx = 0;
3415
3416 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 3417 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3418 if (new_fcport == NULL) {
7c3df132
SK		 3419 ql_log(ql_log_warn, vha, 0x205e,
3420 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 3421 return (QLA_MEMORY_ALLOC_FAILED);
3422 }
3423 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
1da177e4
LT		 3424 /* Set start port ID scan at adapter ID. */
3425 first_dev = 1;
3426 last_dev = 0;
3427
3428 /* Starting free loop ID. */
e315cd28
AC		 3429 loop_id = ha->min_external_loopid;
3430 for (; loop_id <= ha->max_loop_id; loop_id++) {
3431 if (qla2x00_is_reserved_id(vha, loop_id))
1da177e4
LT		 3432 continue;
3433
3a6478df
GM		 3434 if (ha->current_topology == ISP_CFG_FL &&
3435 (atomic_read(&vha->loop_down_timer) ||
3436 LOOP_TRANSITION(vha))) {
bb2d52b2
AV		 3437 atomic_set(&vha->loop_down_timer, 0);
3438 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
3439 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
1da177e4 3440 break;
bb2d52b2 3441 }
1da177e4
LT		 3442
3443 if (swl != NULL) {
3444 if (last_dev) {
3445 wrap.b24 = new_fcport->d_id.b24;
3446 } else {
3447 new_fcport->d_id.b24 = swl[swl_idx].d_id.b24;
3448 memcpy(new_fcport->node_name,
3449 swl[swl_idx].node_name, WWN_SIZE);
3450 memcpy(new_fcport->port_name,
3451 swl[swl_idx].port_name, WWN_SIZE);
d8b45213
AV		 3452 memcpy(new_fcport->fabric_port_name,
3453 swl[swl_idx].fabric_port_name, WWN_SIZE);
3454 new_fcport->fp_speed = swl[swl_idx].fp_speed;
e8c72ba5 3455 new_fcport->fc4_type = swl[swl_idx].fc4_type;
1da177e4
LT		 3456
3457 if (swl[swl_idx].d_id.b.rsvd_1 != 0) {
3458 last_dev = 1;
3459 }
3460 swl_idx++;
3461 }
3462 } else {
3463 /* Send GA_NXT to the switch */
e315cd28 3464 rval = qla2x00_ga_nxt(vha, new_fcport);
1da177e4 3465 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3466 ql_log(ql_log_warn, vha, 0x2064,
3467 "SNS scan failed -- assuming "
3468 "zero-entry result.\n");
1da177e4
LT		 3469 list_for_each_entry_safe(fcport, fcptemp,
3470 new_fcports, list) {
3471 list_del(&fcport->list);
3472 kfree(fcport);
3473 }
3474 rval = QLA_SUCCESS;
3475 break;
3476 }
3477 }
3478
3479 /* If wrap on switch device list, exit. */
3480 if (first_dev) {
3481 wrap.b24 = new_fcport->d_id.b24;
3482 first_dev = 0;
3483 } else if (new_fcport->d_id.b24 == wrap.b24) {
7c3df132
SK		 3484 ql_dbg(ql_dbg_disc, vha, 0x2065,
3485 "Device wrap (%02x%02x%02x).\n",
3486 new_fcport->d_id.b.domain,
3487 new_fcport->d_id.b.area,
3488 new_fcport->d_id.b.al_pa);
1da177e4
LT		 3489 break;
3490 }
3491
2c3dfe3f 3492 /* Bypass if same physical adapter. */
e315cd28 3493 if (new_fcport->d_id.b24 == base_vha->d_id.b24)
1da177e4
LT		 3494 continue;
3495
2c3dfe3f 3496 /* Bypass virtual ports of the same host. */
bb4cf5b7
CD		 3497 if (qla2x00_is_a_vp_did(vha, new_fcport->d_id.b24))
3498 continue;
2c3dfe3f 3499
f7d289f6
AV		 3500 /* Bypass if same domain and area of adapter. */
3501 if (((new_fcport->d_id.b24 & 0xffff00) ==
e315cd28 3502 (vha->d_id.b24 & 0xffff00)) && ha->current_topology ==
f7d289f6
AV		 3503 ISP_CFG_FL)
3504 continue;
3505
1da177e4
LT		 3506 /* Bypass reserved domain fields. */
3507 if ((new_fcport->d_id.b.domain & 0xf0) == 0xf0)
3508 continue;
3509
e8c72ba5 3510 /* Bypass ports whose FCP-4 type is not FCP_SCSI */
4da26e16
CD		 3511 if (ql2xgffidenable &&
3512 (new_fcport->fc4_type != FC4_TYPE_FCP_SCSI &&
3513 new_fcport->fc4_type != FC4_TYPE_UNKNOWN))
e8c72ba5
CD		 3514 continue;
3515
1da177e4
LT		 3516 /* Locate matching device in database. */
3517 found = 0;
e315cd28 3518 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 3519 if (memcmp(new_fcport->port_name, fcport->port_name,
3520 WWN_SIZE))
3521 continue;
3522
827210ba 3523 fcport->scan_state = QLA_FCPORT_FOUND;
b3b02e6e 3524
1da177e4
LT		 3525 found++;
3526
d8b45213
AV		 3527 /* Update port state. */
3528 memcpy(fcport->fabric_port_name,
3529 new_fcport->fabric_port_name, WWN_SIZE);
3530 fcport->fp_speed = new_fcport->fp_speed;
3531
1da177e4
LT		 3532 /*
3533 * If address the same and state FCS_ONLINE, nothing
3534 * changed.
3535 */
3536 if (fcport->d_id.b24 == new_fcport->d_id.b24 &&
3537 atomic_read(&fcport->state) == FCS_ONLINE) {
3538 break;
3539 }
3540
3541 /*
3542 * If device was not a fabric device before.
3543 */
3544 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) {
3545 fcport->d_id.b24 = new_fcport->d_id.b24;
5f16b331 3546 qla2x00_clear_loop_id(fcport);
1da177e4
LT		 3547 fcport->flags |= (FCF_FABRIC_DEVICE |
3548 FCF_LOGIN_NEEDED);
1da177e4
LT		 3549 break;
3550 }
3551
3552 /*
3553 * Port ID changed or device was marked to be updated;
3554 * Log it out if still logged in and mark it for
3555 * relogin later.
3556 */
3557 fcport->d_id.b24 = new_fcport->d_id.b24;
3558 fcport->flags |= FCF_LOGIN_NEEDED;
3559 if (fcport->loop_id != FC_NO_LOOP_ID &&
f08b7251 3560 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
0eba25df 3561 (fcport->flags & FCF_ASYNC_SENT) == 0 &&
1da177e4
LT		 3562 fcport->port_type != FCT_INITIATOR &&
3563 fcport->port_type != FCT_BROADCAST) {
e315cd28 3564 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3565 fcport->d_id.b.domain, fcport->d_id.b.area,
3566 fcport->d_id.b.al_pa);
5f16b331 3567 qla2x00_clear_loop_id(fcport);
1da177e4
LT		 3568 }
3569
3570 break;
3571 }
3572
3573 if (found)
3574 continue;
1da177e4
LT		 3575 /* If device was not in our fcports list, then add it. */
3576 list_add_tail(&new_fcport->list, new_fcports);
3577
3578 /* Allocate a new replacement fcport. */
3579 nxt_d_id.b24 = new_fcport->d_id.b24;
e315cd28 3580 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3581 if (new_fcport == NULL) {
7c3df132
SK		 3582 ql_log(ql_log_warn, vha, 0x2066,
3583 "Memory allocation failed for fcport.\n");
1da177e4
LT		 3584 return (QLA_MEMORY_ALLOC_FAILED);
3585 }
3586 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
3587 new_fcport->d_id.b24 = nxt_d_id.b24;
3588 }
3589
c9475cb0 3590 kfree(new_fcport);
1da177e4 3591
1da177e4
LT		 3592 return (rval);
3593}
3594
3595/*
3596 * qla2x00_find_new_loop_id
3597 * Scan through our port list and find a new usable loop ID.
3598 *
3599 * Input:
3600 * ha: adapter state pointer.
3601 * dev: port structure pointer.
3602 *
3603 * Returns:
3604 * qla2x00 local function return status code.
3605 *
3606 * Context:
3607 * Kernel context.
3608 */
03bcfb57 3609int
e315cd28 3610qla2x00_find_new_loop_id(scsi_qla_host_t *vha, fc_port_t *dev)
1da177e4
LT		 3611{
3612 int rval;
e315cd28 3613 struct qla_hw_data *ha = vha->hw;
feafb7b1 3614 unsigned long flags = 0;
1da177e4
LT		 3615
3616 rval = QLA_SUCCESS;
3617
5f16b331 3618 spin_lock_irqsave(&ha->vport_slock, flags);
1da177e4 3619
5f16b331
CD		 3620 dev->loop_id = find_first_zero_bit(ha->loop_id_map,
3621 LOOPID_MAP_SIZE);
3622 if (dev->loop_id >= LOOPID_MAP_SIZE ||
3623 qla2x00_is_reserved_id(vha, dev->loop_id)) {
3624 dev->loop_id = FC_NO_LOOP_ID;
3625 rval = QLA_FUNCTION_FAILED;
3626 } else
3627 set_bit(dev->loop_id, ha->loop_id_map);
1da177e4 3628
5f16b331 3629 spin_unlock_irqrestore(&ha->vport_slock, flags);
1da177e4 3630
5f16b331
CD		 3631 if (rval == QLA_SUCCESS)
3632 ql_dbg(ql_dbg_disc, dev->vha, 0x2086,
3633 "Assigning new loopid=%x, portid=%x.\n",
3634 dev->loop_id, dev->d_id.b24);
3635 else
3636 ql_log(ql_log_warn, dev->vha, 0x2087,
3637 "No loop_id's available, portid=%x.\n",
3638 dev->d_id.b24);
1da177e4
LT		 3639
3640 return (rval);
3641}
3642
1da177e4
LT		 3643/*
3644 * qla2x00_fabric_dev_login
3645 * Login fabric target device and update FC port database.
3646 *
3647 * Input:
3648 * ha: adapter state pointer.
3649 * fcport: port structure list pointer.
3650 * next_loopid: contains value of a new loop ID that can be used
3651 * by the next login attempt.
3652 *
3653 * Returns:
3654 * qla2x00 local function return status code.
3655 *
3656 * Context:
3657 * Kernel context.
3658 */
3659static int
e315cd28 3660qla2x00_fabric_dev_login(scsi_qla_host_t *vha, fc_port_t *fcport,
1da177e4
LT		 3661 uint16_t *next_loopid)
3662{
3663 int rval;
3664 int retry;
0107109e 3665 uint8_t opts;
e315cd28 3666 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 3667
3668 rval = QLA_SUCCESS;
3669 retry = 0;
3670
ac280b67 3671 if (IS_ALOGIO_CAPABLE(ha)) {
5ff1d584
AV		 3672 if (fcport->flags & FCF_ASYNC_SENT)
3673 return rval;
3674 fcport->flags |= FCF_ASYNC_SENT;
ac280b67
AV		 3675 rval = qla2x00_post_async_login_work(vha, fcport, NULL);
3676 if (!rval)
3677 return rval;
3678 }
3679
5ff1d584 3680 fcport->flags &= ~FCF_ASYNC_SENT;
e315cd28 3681 rval = qla2x00_fabric_login(vha, fcport, next_loopid);
1da177e4 3682 if (rval == QLA_SUCCESS) {
f08b7251 3683 /* Send an ADISC to FCP2 devices.*/
0107109e 3684 opts = 0;
f08b7251 3685 if (fcport->flags & FCF_FCP2_DEVICE)
0107109e 3686 opts |= BIT_1;
e315cd28 3687 rval = qla2x00_get_port_database(vha, fcport, opts);
1da177e4 3688 if (rval != QLA_SUCCESS) {
e315cd28 3689 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3690 fcport->d_id.b.domain, fcport->d_id.b.area,
3691 fcport->d_id.b.al_pa);
e315cd28 3692 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4 3693 } else {
e315cd28 3694 qla2x00_update_fcport(vha, fcport);
1da177e4 3695 }
0b91d116
CD		 3696 } else {
3697 /* Retry Login. */
3698 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4
LT		 3699 }
3700
3701 return (rval);
3702}
3703
3704/*
3705 * qla2x00_fabric_login
3706 * Issue fabric login command.
3707 *
3708 * Input:
3709 * ha = adapter block pointer.
3710 * device = pointer to FC device type structure.
3711 *
3712 * Returns:
3713 * 0 - Login successfully
3714 * 1 - Login failed
3715 * 2 - Initiator device
3716 * 3 - Fatal error
3717 */
3718int
e315cd28 3719qla2x00_fabric_login(scsi_qla_host_t *vha, fc_port_t *fcport,
1da177e4
LT		 3720 uint16_t *next_loopid)
3721{
3722 int rval;
3723 int retry;
3724 uint16_t tmp_loopid;
3725 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28 3726 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 3727
3728 retry = 0;
3729 tmp_loopid = 0;
3730
3731 for (;;) {
7c3df132
SK		 3732 ql_dbg(ql_dbg_disc, vha, 0x2000,
3733 "Trying Fabric Login w/loop id 0x%04x for port "
3734 "%02x%02x%02x.\n",
3735 fcport->loop_id, fcport->d_id.b.domain,
3736 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 3737
3738 /* Login fcport on switch. */
0b91d116 3739 rval = ha->isp_ops->fabric_login(vha, fcport->loop_id,
1da177e4
LT		 3740 fcport->d_id.b.domain, fcport->d_id.b.area,
3741 fcport->d_id.b.al_pa, mb, BIT_0);
0b91d116
CD		 3742 if (rval != QLA_SUCCESS) {
3743 return rval;
3744 }
1da177e4
LT		 3745 if (mb[0] == MBS_PORT_ID_USED) {
3746 /*
3747 * Device has another loop ID. The firmware team
0107109e
AV		 3748 * recommends the driver perform an implicit login with
3749 * the specified ID again. The ID we just used is save
3750 * here so we return with an ID that can be tried by
3751 * the next login.
1da177e4
LT		 3752 */
3753 retry++;
3754 tmp_loopid = fcport->loop_id;
3755 fcport->loop_id = mb[1];
3756
7c3df132
SK		 3757 ql_dbg(ql_dbg_disc, vha, 0x2001,
3758 "Fabric Login: port in use - next loop "
3759 "id=0x%04x, port id= %02x%02x%02x.\n",
1da177e4 3760 fcport->loop_id, fcport->d_id.b.domain,
7c3df132 3761 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 3762
3763 } else if (mb[0] == MBS_COMMAND_COMPLETE) {
3764 /*
3765 * Login succeeded.
3766 */
3767 if (retry) {
3768 /* A retry occurred before. */
3769 *next_loopid = tmp_loopid;
3770 } else {
3771 /*
3772 * No retry occurred before. Just increment the
3773 * ID value for next login.
3774 */
3775 *next_loopid = (fcport->loop_id + 1);
3776 }
3777
3778 if (mb[1] & BIT_0) {
3779 fcport->port_type = FCT_INITIATOR;
3780 } else {
3781 fcport->port_type = FCT_TARGET;
3782 if (mb[1] & BIT_1) {
8474f3a0 3783 fcport->flags |= FCF_FCP2_DEVICE;
1da177e4
LT		 3784 }
3785 }
3786
ad3e0eda
AV		 3787 if (mb[10] & BIT_0)
3788 fcport->supported_classes |= FC_COS_CLASS2;
3789 if (mb[10] & BIT_1)
3790 fcport->supported_classes |= FC_COS_CLASS3;
3791
2d70c103
NB		 3792 if (IS_FWI2_CAPABLE(ha)) {
3793 if (mb[10] & BIT_7)
3794 fcport->flags |=
3795 FCF_CONF_COMP_SUPPORTED;
3796 }
3797
1da177e4
LT		 3798 rval = QLA_SUCCESS;
3799 break;
3800 } else if (mb[0] == MBS_LOOP_ID_USED) {
3801 /*
3802 * Loop ID already used, try next loop ID.
3803 */
3804 fcport->loop_id++;
e315cd28 3805 rval = qla2x00_find_new_loop_id(vha, fcport);
1da177e4
LT		 3806 if (rval != QLA_SUCCESS) {
3807 /* Ran out of loop IDs to use */
3808 break;
3809 }
3810 } else if (mb[0] == MBS_COMMAND_ERROR) {
3811 /*
3812 * Firmware possibly timed out during login. If NO
3813 * retries are left to do then the device is declared
3814 * dead.
3815 */
3816 *next_loopid = fcport->loop_id;
e315cd28 3817 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3818 fcport->d_id.b.domain, fcport->d_id.b.area,
3819 fcport->d_id.b.al_pa);
e315cd28 3820 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4
LT		 3821
3822 rval = 1;
3823 break;
3824 } else {
3825 /*
3826 * unrecoverable / not handled error
3827 */
7c3df132
SK		 3828 ql_dbg(ql_dbg_disc, vha, 0x2002,
3829 "Failed=%x port_id=%02x%02x%02x loop_id=%x "
3830 "jiffies=%lx.\n", mb[0], fcport->d_id.b.domain,
3831 fcport->d_id.b.area, fcport->d_id.b.al_pa,
3832 fcport->loop_id, jiffies);
1da177e4
LT		 3833
3834 *next_loopid = fcport->loop_id;
e315cd28 3835 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3836 fcport->d_id.b.domain, fcport->d_id.b.area,
3837 fcport->d_id.b.al_pa);
5f16b331 3838 qla2x00_clear_loop_id(fcport);
0eedfcf0 3839 fcport->login_retry = 0;
1da177e4
LT		 3840
3841 rval = 3;
3842 break;
3843 }
3844 }
3845
3846 return (rval);
3847}
3848
3849/*
3850 * qla2x00_local_device_login
3851 * Issue local device login command.
3852 *
3853 * Input:
3854 * ha = adapter block pointer.
3855 * loop_id = loop id of device to login to.
3856 *
3857 * Returns (Where's the #define!!!!):
3858 * 0 - Login successfully
3859 * 1 - Login failed
3860 * 3 - Fatal error
3861 */
3862int
e315cd28 3863qla2x00_local_device_login(scsi_qla_host_t *vha, fc_port_t *fcport)
1da177e4
LT		 3864{
3865 int rval;
3866 uint16_t mb[MAILBOX_REGISTER_COUNT];
3867
3868 memset(mb, 0, sizeof(mb));
e315cd28 3869 rval = qla2x00_login_local_device(vha, fcport, mb, BIT_0);
1da177e4
LT		 3870 if (rval == QLA_SUCCESS) {
3871 /* Interrogate mailbox registers for any errors */
3872 if (mb[0] == MBS_COMMAND_ERROR)
3873 rval = 1;
3874 else if (mb[0] == MBS_COMMAND_PARAMETER_ERROR)
3875 /* device not in PCB table */
3876 rval = 3;
3877 }
3878
3879 return (rval);
3880}
3881
3882/*
3883 * qla2x00_loop_resync
3884 * Resync with fibre channel devices.
3885 *
3886 * Input:
3887 * ha = adapter block pointer.
3888 *
3889 * Returns:
3890 * 0 = success
3891 */
3892int
e315cd28 3893qla2x00_loop_resync(scsi_qla_host_t *vha)
1da177e4 3894{
73208dfd 3895 int rval = QLA_SUCCESS;
1da177e4 3896 uint32_t wait_time;
67c2e93a
AC		 3897 struct req_que *req;
3898 struct rsp_que *rsp;
3899
7163ea81 3900 if (vha->hw->flags.cpu_affinity_enabled)
67c2e93a
AC		 3901 req = vha->hw->req_q_map[0];
3902 else
3903 req = vha->req;
3904 rsp = req->rsp;
1da177e4 3905
e315cd28
AC		 3906 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
3907 if (vha->flags.online) {
3908 if (!(rval = qla2x00_fw_ready(vha))) {
1da177e4
LT		 3909 /* Wait at most MAX_TARGET RSCNs for a stable link. */
3910 wait_time = 256;
3911 do {
8ae6d9c7
GM		 3912 if (!IS_QLAFX00(vha->hw)) {
3913 /*
3914 * Issue a marker after FW becomes
3915 * ready.
3916 */
3917 qla2x00_marker(vha, req, rsp, 0, 0,
3918 MK_SYNC_ALL);
3919 vha->marker_needed = 0;
3920 }
1da177e4
LT		 3921
3922 /* Remap devices on Loop. */
e315cd28 3923 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4 3924
8ae6d9c7
GM		 3925 if (IS_QLAFX00(vha->hw))
3926 qlafx00_configure_devices(vha);
3927 else
3928 qla2x00_configure_loop(vha);
3929
1da177e4 3930 wait_time--;
e315cd28
AC		 3931 } while (!atomic_read(&vha->loop_down_timer) &&
3932 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
3933 && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
3934 &vha->dpc_flags)));
1da177e4 3935 }
1da177e4
LT		 3936 }
3937
e315cd28 3938 if (test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
1da177e4 3939 return (QLA_FUNCTION_FAILED);
1da177e4 3940
e315cd28 3941 if (rval)
7c3df132
SK		 3942 ql_dbg(ql_dbg_disc, vha, 0x206c,
3943 "%s *** FAILED ***.\n", __func__);
1da177e4
LT		 3944
3945 return (rval);
3946}
3947
579d12b5
SK		 3948/*
3949* qla2x00_perform_loop_resync
3950* Description: This function will set the appropriate flags and call
3951* qla2x00_loop_resync. If successful loop will be resynced
3952* Arguments : scsi_qla_host_t pointer
3953* returm : Success or Failure
3954*/
3955
3956int qla2x00_perform_loop_resync(scsi_qla_host_t *ha)
3957{
3958 int32_t rval = 0;
3959
3960 if (!test_and_set_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) {
3961 /*Configure the flags so that resync happens properly*/
3962 atomic_set(&ha->loop_down_timer, 0);
3963 if (!(ha->device_flags & DFLG_NO_CABLE)) {
3964 atomic_set(&ha->loop_state, LOOP_UP);
3965 set_bit(LOCAL_LOOP_UPDATE, &ha->dpc_flags);
3966 set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags);
3967 set_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags);
3968
3969 rval = qla2x00_loop_resync(ha);
3970 } else
3971 atomic_set(&ha->loop_state, LOOP_DEAD);
3972
3973 clear_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags);
3974 }
3975
3976 return rval;
3977}
3978
d97994dc 3979void
67becc00 3980qla2x00_update_fcports(scsi_qla_host_t *base_vha)
d97994dc 3981{
3982 fc_port_t *fcport;
feafb7b1
AE		 3983 struct scsi_qla_host *vha;
3984 struct qla_hw_data *ha = base_vha->hw;
3985 unsigned long flags;
d97994dc 3986
feafb7b1 3987 spin_lock_irqsave(&ha->vport_slock, flags);
d97994dc 3988 /* Go with deferred removal of rport references. */
feafb7b1
AE		 3989 list_for_each_entry(vha, &base_vha->hw->vp_list, list) {
3990 atomic_inc(&vha->vref_count);
3991 list_for_each_entry(fcport, &vha->vp_fcports, list) {
8ae598d0 3992 if (fcport->drport &&
feafb7b1
AE		 3993 atomic_read(&fcport->state) != FCS_UNCONFIGURED) {
3994 spin_unlock_irqrestore(&ha->vport_slock, flags);
67becc00 3995 qla2x00_rport_del(fcport);
feafb7b1
AE		 3996 spin_lock_irqsave(&ha->vport_slock, flags);
3997 }
3998 }
3999 atomic_dec(&vha->vref_count);
4000 }
4001 spin_unlock_irqrestore(&ha->vport_slock, flags);
d97994dc 4002}
4003
7d613ac6
SV		 4004/* Assumes idc_lock always held on entry */
4005void
4006qla83xx_reset_ownership(scsi_qla_host_t *vha)
4007{
4008 struct qla_hw_data *ha = vha->hw;
4009 uint32_t drv_presence, drv_presence_mask;
4010 uint32_t dev_part_info1, dev_part_info2, class_type;
4011 uint32_t class_type_mask = 0x3;
4012 uint16_t fcoe_other_function = 0xffff, i;
4013
7ec0effd
AD		 4014 if (IS_QLA8044(ha)) {
4015 drv_presence = qla8044_rd_direct(vha,
4016 QLA8044_CRB_DRV_ACTIVE_INDEX);
4017 dev_part_info1 = qla8044_rd_direct(vha,
4018 QLA8044_CRB_DEV_PART_INFO_INDEX);
4019 dev_part_info2 = qla8044_rd_direct(vha,
4020 QLA8044_CRB_DEV_PART_INFO2);
4021 } else {
4022 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4023 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO1, &dev_part_info1);
4024 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO2, &dev_part_info2);
4025 }
7d613ac6
SV		 4026 for (i = 0; i < 8; i++) {
4027 class_type = ((dev_part_info1 >> (i * 4)) & class_type_mask);
4028 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
4029 (i != ha->portnum)) {
4030 fcoe_other_function = i;
4031 break;
4032 }
4033 }
4034 if (fcoe_other_function == 0xffff) {
4035 for (i = 0; i < 8; i++) {
4036 class_type = ((dev_part_info2 >> (i * 4)) &
4037 class_type_mask);
4038 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
4039 ((i + 8) != ha->portnum)) {
4040 fcoe_other_function = i + 8;
4041 break;
4042 }
4043 }
4044 }
4045 /*
4046 * Prepare drv-presence mask based on fcoe functions present.
4047 * However consider only valid physical fcoe function numbers (0-15).
4048 */
4049 drv_presence_mask = ~((1 << (ha->portnum)) |
4050 ((fcoe_other_function == 0xffff) ?
4051 0 : (1 << (fcoe_other_function))));
4052
4053 /* We are the reset owner iff:
4054 * - No other protocol drivers present.
4055 * - This is the lowest among fcoe functions. */
4056 if (!(drv_presence & drv_presence_mask) &&
4057 (ha->portnum < fcoe_other_function)) {
4058 ql_dbg(ql_dbg_p3p, vha, 0xb07f,
4059 "This host is Reset owner.\n");
4060 ha->flags.nic_core_reset_owner = 1;
4061 }
4062}
4063
fa492630 4064static int
7d613ac6
SV		 4065__qla83xx_set_drv_ack(scsi_qla_host_t *vha)
4066{
4067 int rval = QLA_SUCCESS;
4068 struct qla_hw_data *ha = vha->hw;
4069 uint32_t drv_ack;
4070
4071 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4072 if (rval == QLA_SUCCESS) {
4073 drv_ack |= (1 << ha->portnum);
4074 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
4075 }
4076
4077 return rval;
4078}
4079
fa492630 4080static int
7d613ac6
SV		 4081__qla83xx_clear_drv_ack(scsi_qla_host_t *vha)
4082{
4083 int rval = QLA_SUCCESS;
4084 struct qla_hw_data *ha = vha->hw;
4085 uint32_t drv_ack;
4086
4087 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4088 if (rval == QLA_SUCCESS) {
4089 drv_ack &= ~(1 << ha->portnum);
4090 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
4091 }
4092
4093 return rval;
4094}
4095
fa492630 4096static const char *
7d613ac6
SV		 4097qla83xx_dev_state_to_string(uint32_t dev_state)
4098{
4099 switch (dev_state) {
4100 case QLA8XXX_DEV_COLD:
4101 return "COLD/RE-INIT";
4102 case QLA8XXX_DEV_INITIALIZING:
4103 return "INITIALIZING";
4104 case QLA8XXX_DEV_READY:
4105 return "READY";
4106 case QLA8XXX_DEV_NEED_RESET:
4107 return "NEED RESET";
4108 case QLA8XXX_DEV_NEED_QUIESCENT:
4109 return "NEED QUIESCENT";
4110 case QLA8XXX_DEV_FAILED:
4111 return "FAILED";
4112 case QLA8XXX_DEV_QUIESCENT:
4113 return "QUIESCENT";
4114 default:
4115 return "Unknown";
4116 }
4117}
4118
4119/* Assumes idc-lock always held on entry */
4120void
4121qla83xx_idc_audit(scsi_qla_host_t *vha, int audit_type)
4122{
4123 struct qla_hw_data *ha = vha->hw;
4124 uint32_t idc_audit_reg = 0, duration_secs = 0;
4125
4126 switch (audit_type) {
4127 case IDC_AUDIT_TIMESTAMP:
4128 ha->idc_audit_ts = (jiffies_to_msecs(jiffies) / 1000);
4129 idc_audit_reg = (ha->portnum) |
4130 (IDC_AUDIT_TIMESTAMP << 7) | (ha->idc_audit_ts << 8);
4131 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
4132 break;
4133
4134 case IDC_AUDIT_COMPLETION:
4135 duration_secs = ((jiffies_to_msecs(jiffies) -
4136 jiffies_to_msecs(ha->idc_audit_ts)) / 1000);
4137 idc_audit_reg = (ha->portnum) |
4138 (IDC_AUDIT_COMPLETION << 7) | (duration_secs << 8);
4139 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
4140 break;
4141
4142 default:
4143 ql_log(ql_log_warn, vha, 0xb078,
4144 "Invalid audit type specified.\n");
4145 break;
4146 }
4147}
4148
4149/* Assumes idc_lock always held on entry */
fa492630 4150static int
7d613ac6
SV		 4151qla83xx_initiating_reset(scsi_qla_host_t *vha)
4152{
4153 struct qla_hw_data *ha = vha->hw;
4154 uint32_t idc_control, dev_state;
4155
4156 __qla83xx_get_idc_control(vha, &idc_control);
4157 if ((idc_control & QLA83XX_IDC_RESET_DISABLED)) {
4158 ql_log(ql_log_info, vha, 0xb080,
4159 "NIC Core reset has been disabled. idc-control=0x%x\n",
4160 idc_control);
4161 return QLA_FUNCTION_FAILED;
4162 }
4163
4164 /* Set NEED-RESET iff in READY state and we are the reset-owner */
4165 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4166 if (ha->flags.nic_core_reset_owner && dev_state == QLA8XXX_DEV_READY) {
4167 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
4168 QLA8XXX_DEV_NEED_RESET);
4169 ql_log(ql_log_info, vha, 0xb056, "HW State: NEED RESET.\n");
4170 qla83xx_idc_audit(vha, IDC_AUDIT_TIMESTAMP);
4171 } else {
4172 const char *state = qla83xx_dev_state_to_string(dev_state);
4173 ql_log(ql_log_info, vha, 0xb057, "HW State: %s.\n", state);
4174
4175 /* SV: XXX: Is timeout required here? */
4176 /* Wait for IDC state change READY -> NEED_RESET */
4177 while (dev_state == QLA8XXX_DEV_READY) {
4178 qla83xx_idc_unlock(vha, 0);
4179 msleep(200);
4180 qla83xx_idc_lock(vha, 0);
4181 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4182 }
4183 }
4184
4185 /* Send IDC ack by writing to drv-ack register */
4186 __qla83xx_set_drv_ack(vha);
4187
4188 return QLA_SUCCESS;
4189}
4190
4191int
4192__qla83xx_set_idc_control(scsi_qla_host_t *vha, uint32_t idc_control)
4193{
4194 return qla83xx_wr_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
4195}
4196
7d613ac6
SV		 4197int
4198__qla83xx_get_idc_control(scsi_qla_host_t *vha, uint32_t *idc_control)
4199{
4200 return qla83xx_rd_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
4201}
4202
fa492630 4203static int
7d613ac6
SV		 4204qla83xx_check_driver_presence(scsi_qla_host_t *vha)
4205{
4206 uint32_t drv_presence = 0;
4207 struct qla_hw_data *ha = vha->hw;
4208
4209 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4210 if (drv_presence & (1 << ha->portnum))
4211 return QLA_SUCCESS;
4212 else
4213 return QLA_TEST_FAILED;
4214}
4215
4216int
4217qla83xx_nic_core_reset(scsi_qla_host_t *vha)
4218{
4219 int rval = QLA_SUCCESS;
4220 struct qla_hw_data *ha = vha->hw;
4221
4222 ql_dbg(ql_dbg_p3p, vha, 0xb058,
4223 "Entered %s().\n", __func__);
4224
4225 if (vha->device_flags & DFLG_DEV_FAILED) {
4226 ql_log(ql_log_warn, vha, 0xb059,
4227 "Device in unrecoverable FAILED state.\n");
4228 return QLA_FUNCTION_FAILED;
4229 }
4230
4231 qla83xx_idc_lock(vha, 0);
4232
4233 if (qla83xx_check_driver_presence(vha) != QLA_SUCCESS) {
4234 ql_log(ql_log_warn, vha, 0xb05a,
4235 "Function=0x%x has been removed from IDC participation.\n",
4236 ha->portnum);
4237 rval = QLA_FUNCTION_FAILED;
4238 goto exit;
4239 }
4240
4241 qla83xx_reset_ownership(vha);
4242
4243 rval = qla83xx_initiating_reset(vha);
4244
4245 /*
4246 * Perform reset if we are the reset-owner,
4247 * else wait till IDC state changes to READY/FAILED.
4248 */
4249 if (rval == QLA_SUCCESS) {
4250 rval = qla83xx_idc_state_handler(vha);
4251
4252 if (rval == QLA_SUCCESS)
4253 ha->flags.nic_core_hung = 0;
4254 __qla83xx_clear_drv_ack(vha);
4255 }
4256
4257exit:
4258 qla83xx_idc_unlock(vha, 0);
4259
4260 ql_dbg(ql_dbg_p3p, vha, 0xb05b, "Exiting %s.\n", __func__);
4261
4262 return rval;
4263}
4264
81178772
SK		 4265int
4266qla2xxx_mctp_dump(scsi_qla_host_t *vha)
4267{
4268 struct qla_hw_data *ha = vha->hw;
4269 int rval = QLA_FUNCTION_FAILED;
4270
4271 if (!IS_MCTP_CAPABLE(ha)) {
4272 /* This message can be removed from the final version */
4273 ql_log(ql_log_info, vha, 0x506d,
4274 "This board is not MCTP capable\n");
4275 return rval;
4276 }
4277
4278 if (!ha->mctp_dump) {
4279 ha->mctp_dump = dma_alloc_coherent(&ha->pdev->dev,
4280 MCTP_DUMP_SIZE, &ha->mctp_dump_dma, GFP_KERNEL);
4281
4282 if (!ha->mctp_dump) {
4283 ql_log(ql_log_warn, vha, 0x506e,
4284 "Failed to allocate memory for mctp dump\n");
4285 return rval;
4286 }
4287 }
4288
4289#define MCTP_DUMP_STR_ADDR 0x00000000
4290 rval = qla2x00_dump_mctp_data(vha, ha->mctp_dump_dma,
4291 MCTP_DUMP_STR_ADDR, MCTP_DUMP_SIZE/4);
4292 if (rval != QLA_SUCCESS) {
4293 ql_log(ql_log_warn, vha, 0x506f,
4294 "Failed to capture mctp dump\n");
4295 } else {
4296 ql_log(ql_log_info, vha, 0x5070,
4297 "Mctp dump capture for host (%ld/%p).\n",
4298 vha->host_no, ha->mctp_dump);
4299 ha->mctp_dumped = 1;
4300 }
4301
409ee0fe 4302 if (!ha->flags.nic_core_reset_hdlr_active && !ha->portnum) {
81178772
SK		 4303 ha->flags.nic_core_reset_hdlr_active = 1;
4304 rval = qla83xx_restart_nic_firmware(vha);
4305 if (rval)
4306 /* NIC Core reset failed. */
4307 ql_log(ql_log_warn, vha, 0x5071,
4308 "Failed to restart nic firmware\n");
4309 else
4310 ql_dbg(ql_dbg_p3p, vha, 0xb084,
4311 "Restarted NIC firmware successfully.\n");
4312 ha->flags.nic_core_reset_hdlr_active = 0;
4313 }
4314
4315 return rval;
4316
4317}
4318
579d12b5 4319/*
8fcd6b8b 4320* qla2x00_quiesce_io
579d12b5
SK		 4321* Description: This function will block the new I/Os
4322* Its not aborting any I/Os as context
4323* is not destroyed during quiescence
4324* Arguments: scsi_qla_host_t
4325* return : void
4326*/
4327void
8fcd6b8b 4328qla2x00_quiesce_io(scsi_qla_host_t *vha)
579d12b5
SK		 4329{
4330 struct qla_hw_data *ha = vha->hw;
4331 struct scsi_qla_host *vp;
4332
8fcd6b8b
CD		 4333 ql_dbg(ql_dbg_dpc, vha, 0x401d,
4334 "Quiescing I/O - ha=%p.\n", ha);
579d12b5
SK		 4335
4336 atomic_set(&ha->loop_down_timer, LOOP_DOWN_TIME);
4337 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
4338 atomic_set(&vha->loop_state, LOOP_DOWN);
4339 qla2x00_mark_all_devices_lost(vha, 0);
4340 list_for_each_entry(vp, &ha->vp_list, list)
8fcd6b8b 4341 qla2x00_mark_all_devices_lost(vp, 0);
579d12b5
SK		 4342 } else {
4343 if (!atomic_read(&vha->loop_down_timer))
4344 atomic_set(&vha->loop_down_timer,
4345 LOOP_DOWN_TIME);
4346 }
4347 /* Wait for pending cmds to complete */
4348 qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST);
4349}
4350
a9083016
GM		 4351void
4352qla2x00_abort_isp_cleanup(scsi_qla_host_t *vha)
4353{
4354 struct qla_hw_data *ha = vha->hw;
579d12b5 4355 struct scsi_qla_host *vp;
feafb7b1 4356 unsigned long flags;
6aef87be 4357 fc_port_t *fcport;
a9083016 4358
e46ef004
SK		 4359 /* For ISP82XX, driver waits for completion of the commands.
4360 * online flag should be set.
4361 */
7ec0effd 4362 if (!(IS_P3P_TYPE(ha)))
e46ef004 4363 vha->flags.online = 0;
a9083016
GM		 4364 ha->flags.chip_reset_done = 0;
4365 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2be21fa2 4366 vha->qla_stats.total_isp_aborts++;
a9083016 4367
7c3df132
SK		 4368 ql_log(ql_log_info, vha, 0x00af,
4369 "Performing ISP error recovery - ha=%p.\n", ha);
a9083016 4370
e46ef004
SK		 4371 /* For ISP82XX, reset_chip is just disabling interrupts.
4372 * Driver waits for the completion of the commands.
4373 * the interrupts need to be enabled.
4374 */
7ec0effd 4375 if (!(IS_P3P_TYPE(ha)))
a9083016
GM		 4376 ha->isp_ops->reset_chip(vha);
4377
4378 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
4379 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
4380 atomic_set(&vha->loop_state, LOOP_DOWN);
4381 qla2x00_mark_all_devices_lost(vha, 0);
feafb7b1
AE		 4382
4383 spin_lock_irqsave(&ha->vport_slock, flags);
579d12b5 4384 list_for_each_entry(vp, &ha->vp_list, list) {
feafb7b1
AE		 4385 atomic_inc(&vp->vref_count);
4386 spin_unlock_irqrestore(&ha->vport_slock, flags);
4387
a9083016 4388 qla2x00_mark_all_devices_lost(vp, 0);
feafb7b1
AE		 4389
4390 spin_lock_irqsave(&ha->vport_slock, flags);
4391 atomic_dec(&vp->vref_count);
4392 }
4393 spin_unlock_irqrestore(&ha->vport_slock, flags);
a9083016
GM		 4394 } else {
4395 if (!atomic_read(&vha->loop_down_timer))
4396 atomic_set(&vha->loop_down_timer,
4397 LOOP_DOWN_TIME);
4398 }
4399
6aef87be
AV		 4400 /* Clear all async request states across all VPs. */
4401 list_for_each_entry(fcport, &vha->vp_fcports, list)
4402 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
4403 spin_lock_irqsave(&ha->vport_slock, flags);
4404 list_for_each_entry(vp, &ha->vp_list, list) {
4405 atomic_inc(&vp->vref_count);
4406 spin_unlock_irqrestore(&ha->vport_slock, flags);
4407
4408 list_for_each_entry(fcport, &vp->vp_fcports, list)
4409 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
4410
4411 spin_lock_irqsave(&ha->vport_slock, flags);
4412 atomic_dec(&vp->vref_count);
4413 }
4414 spin_unlock_irqrestore(&ha->vport_slock, flags);
4415
bddd2d65
LC		 4416 if (!ha->flags.eeh_busy) {
4417 /* Make sure for ISP 82XX IO DMA is complete */
7ec0effd 4418 if (IS_P3P_TYPE(ha)) {
7190575f 4419 qla82xx_chip_reset_cleanup(vha);
7c3df132
SK		 4420 ql_log(ql_log_info, vha, 0x00b4,
4421 "Done chip reset cleanup.\n");
a9083016 4422
e46ef004
SK		 4423 /* Done waiting for pending commands.
4424 * Reset the online flag.
4425 */
4426 vha->flags.online = 0;
4d78c973 4427 }
a9083016 4428
bddd2d65
LC		 4429 /* Requeue all commands in outstanding command list. */
4430 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
4431 }
a9083016
GM		 4432}
4433
1da177e4
LT		 4434/*
4435* qla2x00_abort_isp
4436* Resets ISP and aborts all outstanding commands.
4437*
4438* Input:
4439* ha = adapter block pointer.
4440*
4441* Returns:
4442* 0 = success
4443*/
4444int
e315cd28 4445qla2x00_abort_isp(scsi_qla_host_t *vha)
1da177e4 4446{
476e8978 4447 int rval;
1da177e4 4448 uint8_t status = 0;
e315cd28
AC		 4449 struct qla_hw_data *ha = vha->hw;
4450 struct scsi_qla_host *vp;
73208dfd 4451 struct req_que *req = ha->req_q_map[0];
feafb7b1 4452 unsigned long flags;
1da177e4 4453
e315cd28 4454 if (vha->flags.online) {
a9083016 4455 qla2x00_abort_isp_cleanup(vha);
1da177e4 4456
a6171297
SV		 4457 if (IS_QLA8031(ha)) {
4458 ql_dbg(ql_dbg_p3p, vha, 0xb05c,
4459 "Clearing fcoe driver presence.\n");
4460 if (qla83xx_clear_drv_presence(vha) != QLA_SUCCESS)
4461 ql_dbg(ql_dbg_p3p, vha, 0xb073,
4462 "Error while clearing DRV-Presence.\n");
4463 }
4464
85880801
AV		 4465 if (unlikely(pci_channel_offline(ha->pdev) &&
4466 ha->flags.pci_channel_io_perm_failure)) {
4467 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
4468 status = 0;
4469 return status;
4470 }
4471
73208dfd 4472 ha->isp_ops->get_flash_version(vha, req->ring);
30c47662 4473
e315cd28 4474 ha->isp_ops->nvram_config(vha);
1da177e4 4475
e315cd28
AC		 4476 if (!qla2x00_restart_isp(vha)) {
4477 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4 4478
e315cd28 4479 if (!atomic_read(&vha->loop_down_timer)) {
1da177e4
LT		 4480 /*
4481 * Issue marker command only when we are going
4482 * to start the I/O .
4483 */
e315cd28 4484 vha->marker_needed = 1;
1da177e4
LT		 4485 }
4486
e315cd28 4487 vha->flags.online = 1;
1da177e4 4488
fd34f556 4489 ha->isp_ops->enable_intrs(ha);
1da177e4 4490
fa2a1ce5 4491 ha->isp_abort_cnt = 0;
e315cd28 4492 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
476e8978 4493
6246b8a1
GM		 4494 if (IS_QLA81XX(ha) || IS_QLA8031(ha))
4495 qla2x00_get_fw_version(vha);
df613b96
AV		 4496 if (ha->fce) {
4497 ha->flags.fce_enabled = 1;
4498 memset(ha->fce, 0,
4499 fce_calc_size(ha->fce_bufs));
e315cd28 4500 rval = qla2x00_enable_fce_trace(vha,
df613b96
AV		 4501 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
4502 &ha->fce_bufs);
4503 if (rval) {
7c3df132 4504 ql_log(ql_log_warn, vha, 0x8033,
df613b96
AV		 4505 "Unable to reinitialize FCE "
4506 "(%d).\n", rval);
4507 ha->flags.fce_enabled = 0;
4508 }
4509 }
436a7b11
AV		 4510
4511 if (ha->eft) {
4512 memset(ha->eft, 0, EFT_SIZE);
e315cd28 4513 rval = qla2x00_enable_eft_trace(vha,
436a7b11
AV		 4514 ha->eft_dma, EFT_NUM_BUFFERS);
4515 if (rval) {
7c3df132 4516 ql_log(ql_log_warn, vha, 0x8034,
436a7b11
AV		 4517 "Unable to reinitialize EFT "
4518 "(%d).\n", rval);
4519 }
4520 }
1da177e4 4521 } else { /* failed the ISP abort */
e315cd28
AC		 4522 vha->flags.online = 1;
4523 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
1da177e4 4524 if (ha->isp_abort_cnt == 0) {
7c3df132
SK		 4525 ql_log(ql_log_fatal, vha, 0x8035,
4526 "ISP error recover failed - "
4527 "board disabled.\n");
fa2a1ce5 4528 /*
1da177e4
LT		 4529 * The next call disables the board
4530 * completely.
4531 */
e315cd28
AC		 4532 ha->isp_ops->reset_adapter(vha);
4533 vha->flags.online = 0;
1da177e4 4534 clear_bit(ISP_ABORT_RETRY,
e315cd28 4535 &vha->dpc_flags);
1da177e4
LT		 4536 status = 0;
4537 } else { /* schedule another ISP abort */
4538 ha->isp_abort_cnt--;
7c3df132
SK		 4539 ql_dbg(ql_dbg_taskm, vha, 0x8020,
4540 "ISP abort - retry remaining %d.\n",
4541 ha->isp_abort_cnt);
1da177e4
LT		 4542 status = 1;
4543 }
4544 } else {
4545 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
7c3df132
SK		 4546 ql_dbg(ql_dbg_taskm, vha, 0x8021,
4547 "ISP error recovery - retrying (%d) "
4548 "more times.\n", ha->isp_abort_cnt);
e315cd28 4549 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
1da177e4
LT		 4550 status = 1;
4551 }
4552 }
fa2a1ce5 4553
1da177e4
LT		 4554 }
4555
e315cd28 4556 if (!status) {
7c3df132 4557 ql_dbg(ql_dbg_taskm, vha, 0x8022, "%s succeeded.\n", __func__);
feafb7b1
AE		 4558
4559 spin_lock_irqsave(&ha->vport_slock, flags);
4560 list_for_each_entry(vp, &ha->vp_list, list) {
4561 if (vp->vp_idx) {
4562 atomic_inc(&vp->vref_count);
4563 spin_unlock_irqrestore(&ha->vport_slock, flags);
4564
e315cd28 4565 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 4566
4567 spin_lock_irqsave(&ha->vport_slock, flags);
4568 atomic_dec(&vp->vref_count);
4569 }
e315cd28 4570 }
feafb7b1
AE		 4571 spin_unlock_irqrestore(&ha->vport_slock, flags);
4572
7d613ac6
SV		 4573 if (IS_QLA8031(ha)) {
4574 ql_dbg(ql_dbg_p3p, vha, 0xb05d,
4575 "Setting back fcoe driver presence.\n");
4576 if (qla83xx_set_drv_presence(vha) != QLA_SUCCESS)
4577 ql_dbg(ql_dbg_p3p, vha, 0xb074,
4578 "Error while setting DRV-Presence.\n");
4579 }
e315cd28 4580 } else {
d8424f68
JP		 4581 ql_log(ql_log_warn, vha, 0x8023, "%s **** FAILED ****.\n",
4582 __func__);
1da177e4
LT		 4583 }
4584
4585 return(status);
4586}
4587
4588/*
4589* qla2x00_restart_isp
4590* restarts the ISP after a reset
4591*
4592* Input:
4593* ha = adapter block pointer.
4594*
4595* Returns:
4596* 0 = success
4597*/
4598static int
e315cd28 4599qla2x00_restart_isp(scsi_qla_host_t *vha)
1da177e4 4600{
c6b2fca8 4601 int status = 0;
1da177e4 4602 uint32_t wait_time;
e315cd28 4603 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 4604 struct req_que *req = ha->req_q_map[0];
4605 struct rsp_que *rsp = ha->rsp_q_map[0];
2d70c103 4606 unsigned long flags;
1da177e4
LT		 4607
4608 /* If firmware needs to be loaded */
e315cd28
AC		 4609 if (qla2x00_isp_firmware(vha)) {
4610 vha->flags.online = 0;
4611 status = ha->isp_ops->chip_diag(vha);
4612 if (!status)
4613 status = qla2x00_setup_chip(vha);
1da177e4
LT		 4614 }
4615
e315cd28
AC		 4616 if (!status && !(status = qla2x00_init_rings(vha))) {
4617 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
2533cf67 4618 ha->flags.chip_reset_done = 1;
73208dfd
AC		 4619 /* Initialize the queues in use */
4620 qla25xx_init_queues(ha);
4621
e315cd28
AC		 4622 status = qla2x00_fw_ready(vha);
4623 if (!status) {
7c3df132
SK		 4624 ql_dbg(ql_dbg_taskm, vha, 0x8031,
4625 "Start configure loop status = %d.\n", status);
0107109e
AV		 4626
4627 /* Issue a marker after FW becomes ready. */
73208dfd 4628 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
0107109e 4629
e315cd28 4630 vha->flags.online = 1;
2d70c103
NB		 4631
4632 /*
4633 * Process any ATIO queue entries that came in
4634 * while we weren't online.
4635 */
4636 spin_lock_irqsave(&ha->hardware_lock, flags);
4637 if (qla_tgt_mode_enabled(vha))
4638 qlt_24xx_process_atio_queue(vha);
4639 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4640
1da177e4
LT		 4641 /* Wait at most MAX_TARGET RSCNs for a stable link. */
4642 wait_time = 256;
4643 do {
e315cd28
AC		 4644 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
4645 qla2x00_configure_loop(vha);
1da177e4 4646 wait_time--;
e315cd28
AC		 4647 } while (!atomic_read(&vha->loop_down_timer) &&
4648 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
4649 && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
4650 &vha->dpc_flags)));
1da177e4
LT		 4651 }
4652
4653 /* if no cable then assume it's good */
e315cd28 4654 if ((vha->device_flags & DFLG_NO_CABLE))
1da177e4
LT		 4655 status = 0;
4656
7c3df132
SK		 4657 ql_dbg(ql_dbg_taskm, vha, 0x8032,
4658 "Configure loop done, status = 0x%x.\n", status);
1da177e4
LT		 4659 }
4660 return (status);
4661}
4662
73208dfd
AC		 4663static int
4664qla25xx_init_queues(struct qla_hw_data *ha)
4665{
4666 struct rsp_que *rsp = NULL;
4667 struct req_que *req = NULL;
4668 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
4669 int ret = -1;
4670 int i;
4671
2afa19a9 4672 for (i = 1; i < ha->max_rsp_queues; i++) {
73208dfd
AC		 4673 rsp = ha->rsp_q_map[i];
4674 if (rsp) {
4675 rsp->options &= ~BIT_0;
618a7523 4676 ret = qla25xx_init_rsp_que(base_vha, rsp);
73208dfd 4677 if (ret != QLA_SUCCESS)
7c3df132
SK		 4678 ql_dbg(ql_dbg_init, base_vha, 0x00ff,
4679 "%s Rsp que: %d init failed.\n",
4680 __func__, rsp->id);
73208dfd 4681 else
7c3df132
SK		 4682 ql_dbg(ql_dbg_init, base_vha, 0x0100,
4683 "%s Rsp que: %d inited.\n",
4684 __func__, rsp->id);
73208dfd 4685 }
2afa19a9
AC		 4686 }
4687 for (i = 1; i < ha->max_req_queues; i++) {
73208dfd
AC		 4688 req = ha->req_q_map[i];
4689 if (req) {
29bdccbe 4690 /* Clear outstanding commands array. */
73208dfd 4691 req->options &= ~BIT_0;
618a7523 4692 ret = qla25xx_init_req_que(base_vha, req);
73208dfd 4693 if (ret != QLA_SUCCESS)
7c3df132
SK		 4694 ql_dbg(ql_dbg_init, base_vha, 0x0101,
4695 "%s Req que: %d init failed.\n",
4696 __func__, req->id);
73208dfd 4697 else
7c3df132
SK		 4698 ql_dbg(ql_dbg_init, base_vha, 0x0102,
4699 "%s Req que: %d inited.\n",
4700 __func__, req->id);
73208dfd
AC		 4701 }
4702 }
4703 return ret;
4704}
4705
1da177e4
LT		 4706/*
4707* qla2x00_reset_adapter
4708* Reset adapter.
4709*
4710* Input:
4711* ha = adapter block pointer.
4712*/
abbd8870 4713void
e315cd28 4714qla2x00_reset_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 4715{
4716 unsigned long flags = 0;
e315cd28 4717 struct qla_hw_data *ha = vha->hw;
3d71644c 4718 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 4719
e315cd28 4720 vha->flags.online = 0;
fd34f556 4721 ha->isp_ops->disable_intrs(ha);
1da177e4 4722
1da177e4
LT		 4723 spin_lock_irqsave(&ha->hardware_lock, flags);
4724 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
4725 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
4726 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
4727 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
4728 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4729}
0107109e
AV		 4730
4731void
e315cd28 4732qla24xx_reset_adapter(scsi_qla_host_t *vha)
0107109e
AV		 4733{
4734 unsigned long flags = 0;
e315cd28 4735 struct qla_hw_data *ha = vha->hw;
0107109e
AV		 4736 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
4737
7ec0effd 4738 if (IS_P3P_TYPE(ha))
a9083016
GM		 4739 return;
4740
e315cd28 4741 vha->flags.online = 0;
fd34f556 4742 ha->isp_ops->disable_intrs(ha);
0107109e
AV		 4743
4744 spin_lock_irqsave(&ha->hardware_lock, flags);
4745 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
4746 RD_REG_DWORD(&reg->hccr);
4747 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
4748 RD_REG_DWORD(&reg->hccr);
4749 spin_unlock_irqrestore(&ha->hardware_lock, flags);
09ff36d3
AV		 4750
4751 if (IS_NOPOLLING_TYPE(ha))
4752 ha->isp_ops->enable_intrs(ha);
0107109e
AV		 4753}
4754
4e08df3f
DM		 4755/* On sparc systems, obtain port and node WWN from firmware
4756 * properties.
4757 */
e315cd28
AC		 4758static void qla24xx_nvram_wwn_from_ofw(scsi_qla_host_t *vha,
4759 struct nvram_24xx *nv)
4e08df3f
DM		 4760{
4761#ifdef CONFIG_SPARC
e315cd28 4762 struct qla_hw_data *ha = vha->hw;
4e08df3f 4763 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 4764 struct device_node *dp = pci_device_to_OF_node(pdev);
4765 const u8 *val;
4e08df3f
DM		 4766 int len;
4767
4768 val = of_get_property(dp, "port-wwn", &len);
4769 if (val && len >= WWN_SIZE)
4770 memcpy(nv->port_name, val, WWN_SIZE);
4771
4772 val = of_get_property(dp, "node-wwn", &len);
4773 if (val && len >= WWN_SIZE)
4774 memcpy(nv->node_name, val, WWN_SIZE);
4775#endif
4776}
4777
0107109e 4778int
e315cd28 4779qla24xx_nvram_config(scsi_qla_host_t *vha)
0107109e 4780{
4e08df3f 4781 int rval;
0107109e
AV		 4782 struct init_cb_24xx *icb;
4783 struct nvram_24xx *nv;
4784 uint32_t *dptr;
4785 uint8_t *dptr1, *dptr2;
4786 uint32_t chksum;
4787 uint16_t cnt;
e315cd28 4788 struct qla_hw_data *ha = vha->hw;
0107109e 4789
4e08df3f 4790 rval = QLA_SUCCESS;
0107109e 4791 icb = (struct init_cb_24xx *)ha->init_cb;
281afe19 4792 nv = ha->nvram;
0107109e
AV		 4793
4794 /* Determine NVRAM starting address. */
e5b68a61
AC		 4795 if (ha->flags.port0) {
4796 ha->nvram_base = FA_NVRAM_FUNC0_ADDR;
4797 ha->vpd_base = FA_NVRAM_VPD0_ADDR;
4798 } else {
0107109e 4799 ha->nvram_base = FA_NVRAM_FUNC1_ADDR;
6f641790 4800 ha->vpd_base = FA_NVRAM_VPD1_ADDR;
4801 }
e5b68a61
AC		 4802 ha->nvram_size = sizeof(struct nvram_24xx);
4803 ha->vpd_size = FA_NVRAM_VPD_SIZE;
0107109e 4804
281afe19
SJ		 4805 /* Get VPD data into cache */
4806 ha->vpd = ha->nvram + VPD_OFFSET;
e315cd28 4807 ha->isp_ops->read_nvram(vha, (uint8_t *)ha->vpd,
281afe19
SJ		 4808 ha->nvram_base - FA_NVRAM_FUNC0_ADDR, FA_NVRAM_VPD_SIZE * 4);
4809
4810 /* Get NVRAM data into cache and calculate checksum. */
0107109e 4811 dptr = (uint32_t *)nv;
e315cd28 4812 ha->isp_ops->read_nvram(vha, (uint8_t *)dptr, ha->nvram_base,
0107109e
AV		 4813 ha->nvram_size);
4814 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++)
4815 chksum += le32_to_cpu(*dptr++);
4816
7c3df132
SK		 4817 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x006a,
4818 "Contents of NVRAM\n");
4819 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010d,
4820 (uint8_t *)nv, ha->nvram_size);
0107109e
AV		 4821
4822 /* Bad NVRAM data, set defaults parameters. */
4823 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
4824 || nv->id[3] != ' ' ||
4825 nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) {
4826 /* Reset NVRAM data. */
7c3df132 4827 ql_log(ql_log_warn, vha, 0x006b,
9e336520 4828 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
7c3df132
SK		 4829 "version=0x%x.\n", chksum, nv->id[0], nv->nvram_version);
4830 ql_log(ql_log_warn, vha, 0x006c,
4831 "Falling back to functioning (yet invalid -- WWPN) "
4832 "defaults.\n");
4e08df3f
DM		 4833
4834 /*
4835 * Set default initialization control block.
4836 */
4837 memset(nv, 0, ha->nvram_size);
4838 nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION);
4839 nv->version = __constant_cpu_to_le16(ICB_VERSION);
4840 nv->frame_payload_size = __constant_cpu_to_le16(2048);
4841 nv->execution_throttle = __constant_cpu_to_le16(0xFFFF);
4842 nv->exchange_count = __constant_cpu_to_le16(0);
4843 nv->hard_address = __constant_cpu_to_le16(124);
4844 nv->port_name[0] = 0x21;
e5b68a61 4845 nv->port_name[1] = 0x00 + ha->port_no;
4e08df3f
DM		 4846 nv->port_name[2] = 0x00;
4847 nv->port_name[3] = 0xe0;
4848 nv->port_name[4] = 0x8b;
4849 nv->port_name[5] = 0x1c;
4850 nv->port_name[6] = 0x55;
4851 nv->port_name[7] = 0x86;
4852 nv->node_name[0] = 0x20;
4853 nv->node_name[1] = 0x00;
4854 nv->node_name[2] = 0x00;
4855 nv->node_name[3] = 0xe0;
4856 nv->node_name[4] = 0x8b;
4857 nv->node_name[5] = 0x1c;
4858 nv->node_name[6] = 0x55;
4859 nv->node_name[7] = 0x86;
e315cd28 4860 qla24xx_nvram_wwn_from_ofw(vha, nv);
4e08df3f
DM		 4861 nv->login_retry_count = __constant_cpu_to_le16(8);
4862 nv->interrupt_delay_timer = __constant_cpu_to_le16(0);
4863 nv->login_timeout = __constant_cpu_to_le16(0);
4864 nv->firmware_options_1 =
4865 __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
4866 nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4);
4867 nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12);
4868 nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13);
4869 nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10);
4870 nv->efi_parameters = __constant_cpu_to_le32(0);
4871 nv->reset_delay = 5;
4872 nv->max_luns_per_target = __constant_cpu_to_le16(128);
4873 nv->port_down_retry_count = __constant_cpu_to_le16(30);
4874 nv->link_down_timeout = __constant_cpu_to_le16(30);
4875
4876 rval = 1;
0107109e
AV		 4877 }
4878
2d70c103
NB		 4879 if (!qla_ini_mode_enabled(vha)) {
4880 /* Don't enable full login after initial LIP */
4881 nv->firmware_options_1 &= __constant_cpu_to_le32(~BIT_13);
4882 /* Don't enable LIP full login for initiator */
4883 nv->host_p &= __constant_cpu_to_le32(~BIT_10);
4884 }
4885
4886 qlt_24xx_config_nvram_stage1(vha, nv);
4887
0107109e 4888 /* Reset Initialization control block */
e315cd28 4889 memset(icb, 0, ha->init_cb_size);
0107109e
AV		 4890
4891 /* Copy 1st segment. */
4892 dptr1 = (uint8_t *)icb;
4893 dptr2 = (uint8_t *)&nv->version;
4894 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
4895 while (cnt--)
4896 *dptr1++ = *dptr2++;
4897
4898 icb->login_retry_count = nv->login_retry_count;
3ea66e28 4899 icb->link_down_on_nos = nv->link_down_on_nos;
0107109e
AV		 4900
4901 /* Copy 2nd segment. */
4902 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
4903 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
4904 cnt = (uint8_t *)&icb->reserved_3 -
4905 (uint8_t *)&icb->interrupt_delay_timer;
4906 while (cnt--)
4907 *dptr1++ = *dptr2++;
4908
4909 /*
4910 * Setup driver NVRAM options.
4911 */
e315cd28 4912 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
9bb9fcf2 4913 "QLA2462");
0107109e 4914
2d70c103
NB		 4915 qlt_24xx_config_nvram_stage2(vha, icb);
4916
5341e868 4917 if (nv->host_p & __constant_cpu_to_le32(BIT_15)) {
2d70c103 4918 /* Use alternate WWN? */
5341e868
AV		 4919 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
4920 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
4921 }
4922
0107109e 4923 /* Prepare nodename */
fd0e7e4d 4924 if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) {
0107109e
AV		 4925 /*
4926 * Firmware will apply the following mask if the nodename was
4927 * not provided.
4928 */
4929 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
4930 icb->node_name[0] &= 0xF0;
4931 }
4932
4933 /* Set host adapter parameters. */
4934 ha->flags.disable_risc_code_load = 0;
0c8c39af
AV		 4935 ha->flags.enable_lip_reset = 0;
4936 ha->flags.enable_lip_full_login =
4937 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
4938 ha->flags.enable_target_reset =
4939 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
0107109e 4940 ha->flags.enable_led_scheme = 0;
d4c760c2 4941 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
0107109e 4942
fd0e7e4d
AV		 4943 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
4944 (BIT_6 | BIT_5 | BIT_4)) >> 4;
0107109e
AV		 4945
4946 memcpy(ha->fw_seriallink_options24, nv->seriallink_options,
4947 sizeof(ha->fw_seriallink_options24));
4948
4949 /* save HBA serial number */
4950 ha->serial0 = icb->port_name[5];
4951 ha->serial1 = icb->port_name[6];
4952 ha->serial2 = icb->port_name[7];
e315cd28
AC		 4953 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
4954 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
0107109e 4955
bc8fb3cb 4956 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
4957
0107109e
AV		 4958 ha->retry_count = le16_to_cpu(nv->login_retry_count);
4959
4960 /* Set minimum login_timeout to 4 seconds. */
4961 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
4962 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
4963 if (le16_to_cpu(nv->login_timeout) < 4)
4964 nv->login_timeout = __constant_cpu_to_le16(4);
4965 ha->login_timeout = le16_to_cpu(nv->login_timeout);
c6852c4c 4966 icb->login_timeout = nv->login_timeout;
0107109e 4967
00a537b8
AV		 4968 /* Set minimum RATOV to 100 tenths of a second. */
4969 ha->r_a_tov = 100;
0107109e
AV		 4970
4971 ha->loop_reset_delay = nv->reset_delay;
4972
4973 /* Link Down Timeout = 0:
4974 *
4975 * When Port Down timer expires we will start returning
4976 * I/O's to OS with "DID_NO_CONNECT".
4977 *
4978 * Link Down Timeout != 0:
4979 *
4980 * The driver waits for the link to come up after link down
4981 * before returning I/Os to OS with "DID_NO_CONNECT".
4982 */
4983 if (le16_to_cpu(nv->link_down_timeout) == 0) {
4984 ha->loop_down_abort_time =
4985 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
4986 } else {
4987 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
4988 ha->loop_down_abort_time =
4989 (LOOP_DOWN_TIME - ha->link_down_timeout);
4990 }
4991
4992 /* Need enough time to try and get the port back. */
4993 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
4994 if (qlport_down_retry)
4995 ha->port_down_retry_count = qlport_down_retry;
4996
4997 /* Set login_retry_count */
4998 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
4999 if (ha->port_down_retry_count ==
5000 le16_to_cpu(nv->port_down_retry_count) &&
5001 ha->port_down_retry_count > 3)
5002 ha->login_retry_count = ha->port_down_retry_count;
5003 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
5004 ha->login_retry_count = ha->port_down_retry_count;
5005 if (ql2xloginretrycount)
5006 ha->login_retry_count = ql2xloginretrycount;
5007
4fdfefe5 5008 /* Enable ZIO. */
e315cd28 5009 if (!vha->flags.init_done) {
4fdfefe5
AV		 5010 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
5011 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
5012 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
5013 le16_to_cpu(icb->interrupt_delay_timer): 2;
5014 }
5015 icb->firmware_options_2 &= __constant_cpu_to_le32(
5016 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
e315cd28 5017 vha->flags.process_response_queue = 0;
4fdfefe5 5018 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d 5019 ha->zio_mode = QLA_ZIO_MODE_6;
5020
7c3df132 5021 ql_log(ql_log_info, vha, 0x006f,
4fdfefe5
AV		 5022 "ZIO mode %d enabled; timer delay (%d us).\n",
5023 ha->zio_mode, ha->zio_timer * 100);
5024
5025 icb->firmware_options_2 |= cpu_to_le32(
5026 (uint32_t)ha->zio_mode);
5027 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
e315cd28 5028 vha->flags.process_response_queue = 1;
4fdfefe5
AV		 5029 }
5030
4e08df3f 5031 if (rval) {
7c3df132
SK		 5032 ql_log(ql_log_warn, vha, 0x0070,
5033 "NVRAM configuration failed.\n");
4e08df3f
DM		 5034 }
5035 return (rval);
0107109e
AV		 5036}
5037
413975a0 5038static int
cbc8eb67
AV		 5039qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr,
5040 uint32_t faddr)
d1c61909 5041{
73208dfd 5042 int rval = QLA_SUCCESS;
d1c61909 5043 int segments, fragment;
d1c61909
AV		 5044 uint32_t *dcode, dlen;
5045 uint32_t risc_addr;
5046 uint32_t risc_size;
5047 uint32_t i;
e315cd28 5048 struct qla_hw_data *ha = vha->hw;
73208dfd 5049 struct req_que *req = ha->req_q_map[0];
eaac30be 5050
7c3df132 5051 ql_dbg(ql_dbg_init, vha, 0x008b,
cfb0919c 5052 "FW: Loading firmware from flash (%x).\n", faddr);
eaac30be 5053
d1c61909
AV		 5054 rval = QLA_SUCCESS;
5055
5056 segments = FA_RISC_CODE_SEGMENTS;
73208dfd 5057 dcode = (uint32_t *)req->ring;
d1c61909
AV		 5058 *srisc_addr = 0;
5059
5060 /* Validate firmware image by checking version. */
e315cd28 5061 qla24xx_read_flash_data(vha, dcode, faddr + 4, 4);
d1c61909
AV		 5062 for (i = 0; i < 4; i++)
5063 dcode[i] = be32_to_cpu(dcode[i]);
5064 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
5065 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
5066 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
5067 dcode[3] == 0)) {
7c3df132
SK		 5068 ql_log(ql_log_fatal, vha, 0x008c,
5069 "Unable to verify the integrity of flash firmware "
5070 "image.\n");
5071 ql_log(ql_log_fatal, vha, 0x008d,
5072 "Firmware data: %08x %08x %08x %08x.\n",
5073 dcode[0], dcode[1], dcode[2], dcode[3]);
d1c61909
AV		 5074
5075 return QLA_FUNCTION_FAILED;
5076 }
5077
5078 while (segments && rval == QLA_SUCCESS) {
5079 /* Read segment's load information. */
e315cd28 5080 qla24xx_read_flash_data(vha, dcode, faddr, 4);
d1c61909
AV		 5081
5082 risc_addr = be32_to_cpu(dcode[2]);
5083 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
5084 risc_size = be32_to_cpu(dcode[3]);
5085
5086 fragment = 0;
5087 while (risc_size > 0 && rval == QLA_SUCCESS) {
5088 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
5089 if (dlen > risc_size)
5090 dlen = risc_size;
5091
7c3df132
SK		 5092 ql_dbg(ql_dbg_init, vha, 0x008e,
5093 "Loading risc segment@ risc addr %x "
5094 "number of dwords 0x%x offset 0x%x.\n",
5095 risc_addr, dlen, faddr);
d1c61909 5096
e315cd28 5097 qla24xx_read_flash_data(vha, dcode, faddr, dlen);
d1c61909
AV		 5098 for (i = 0; i < dlen; i++)
5099 dcode[i] = swab32(dcode[i]);
5100
73208dfd 5101 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
d1c61909
AV		 5102 dlen);
5103 if (rval) {
7c3df132
SK		 5104 ql_log(ql_log_fatal, vha, 0x008f,
5105 "Failed to load segment %d of firmware.\n",
5106 fragment);
d1c61909
AV		 5107 break;
5108 }
5109
5110 faddr += dlen;
5111 risc_addr += dlen;
5112 risc_size -= dlen;
5113 fragment++;
5114 }
5115
5116 /* Next segment. */
5117 segments--;
5118 }
5119
5120 return rval;
5121}
5122
e9454a88 5123#define QLA_FW_URL "http://ldriver.qlogic.com/firmware/"
d1c61909 5124
0107109e 5125int
e315cd28 5126qla2x00_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5433383e
AV		 5127{
5128 int rval;
5129 int i, fragment;
5130 uint16_t *wcode, *fwcode;
5131 uint32_t risc_addr, risc_size, fwclen, wlen, *seg;
5132 struct fw_blob *blob;
e315cd28 5133 struct qla_hw_data *ha = vha->hw;
73208dfd 5134 struct req_que *req = ha->req_q_map[0];
5433383e
AV		 5135
5136 /* Load firmware blob. */
e315cd28 5137 blob = qla2x00_request_firmware(vha);
5433383e 5138 if (!blob) {
7c3df132
SK		 5139 ql_log(ql_log_info, vha, 0x0083,
5140 "Fimware image unavailable.\n");
5141 ql_log(ql_log_info, vha, 0x0084,
5142 "Firmware images can be retrieved from: "QLA_FW_URL ".\n");
5433383e
AV		 5143 return QLA_FUNCTION_FAILED;
5144 }
5145
5146 rval = QLA_SUCCESS;
5147
73208dfd 5148 wcode = (uint16_t *)req->ring;
5433383e
AV		 5149 *srisc_addr = 0;
5150 fwcode = (uint16_t *)blob->fw->data;
5151 fwclen = 0;
5152
5153 /* Validate firmware image by checking version. */
5154 if (blob->fw->size < 8 * sizeof(uint16_t)) {
7c3df132
SK		 5155 ql_log(ql_log_fatal, vha, 0x0085,
5156 "Unable to verify integrity of firmware image (%Zd).\n",
5433383e
AV		 5157 blob->fw->size);
5158 goto fail_fw_integrity;
5159 }
5160 for (i = 0; i < 4; i++)
5161 wcode[i] = be16_to_cpu(fwcode[i + 4]);
5162 if ((wcode[0] == 0xffff && wcode[1] == 0xffff && wcode[2] == 0xffff &&
5163 wcode[3] == 0xffff) || (wcode[0] == 0 && wcode[1] == 0 &&
5164 wcode[2] == 0 && wcode[3] == 0)) {
7c3df132
SK		 5165 ql_log(ql_log_fatal, vha, 0x0086,
5166 "Unable to verify integrity of firmware image.\n");
5167 ql_log(ql_log_fatal, vha, 0x0087,
5168 "Firmware data: %04x %04x %04x %04x.\n",
5169 wcode[0], wcode[1], wcode[2], wcode[3]);
5433383e
AV		 5170 goto fail_fw_integrity;
5171 }
5172
5173 seg = blob->segs;
5174 while (*seg && rval == QLA_SUCCESS) {
5175 risc_addr = *seg;
5176 *srisc_addr = *srisc_addr == 0 ? *seg : *srisc_addr;
5177 risc_size = be16_to_cpu(fwcode[3]);
5178
5179 /* Validate firmware image size. */
5180 fwclen += risc_size * sizeof(uint16_t);
5181 if (blob->fw->size < fwclen) {
7c3df132 5182 ql_log(ql_log_fatal, vha, 0x0088,
5433383e 5183 "Unable to verify integrity of firmware image "
7c3df132 5184 "(%Zd).\n", blob->fw->size);
5433383e
AV		 5185 goto fail_fw_integrity;
5186 }
5187
5188 fragment = 0;
5189 while (risc_size > 0 && rval == QLA_SUCCESS) {
5190 wlen = (uint16_t)(ha->fw_transfer_size >> 1);
5191 if (wlen > risc_size)
5192 wlen = risc_size;
7c3df132
SK		 5193 ql_dbg(ql_dbg_init, vha, 0x0089,
5194 "Loading risc segment@ risc addr %x number of "
5195 "words 0x%x.\n", risc_addr, wlen);
5433383e
AV		 5196
5197 for (i = 0; i < wlen; i++)
5198 wcode[i] = swab16(fwcode[i]);
5199
73208dfd 5200 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
5433383e
AV		 5201 wlen);
5202 if (rval) {
7c3df132
SK		 5203 ql_log(ql_log_fatal, vha, 0x008a,
5204 "Failed to load segment %d of firmware.\n",
5205 fragment);
5433383e
AV		 5206 break;
5207 }
5208
5209 fwcode += wlen;
5210 risc_addr += wlen;
5211 risc_size -= wlen;
5212 fragment++;
5213 }
5214
5215 /* Next segment. */
5216 seg++;
5217 }
5218 return rval;
5219
5220fail_fw_integrity:
5221 return QLA_FUNCTION_FAILED;
5222}
5223
eaac30be
AV		 5224static int
5225qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr)
0107109e
AV		 5226{
5227 int rval;
5228 int segments, fragment;
5229 uint32_t *dcode, dlen;
5230 uint32_t risc_addr;
5231 uint32_t risc_size;
5232 uint32_t i;
5433383e 5233 struct fw_blob *blob;
0107109e 5234 uint32_t *fwcode, fwclen;
e315cd28 5235 struct qla_hw_data *ha = vha->hw;
73208dfd 5236 struct req_que *req = ha->req_q_map[0];
0107109e 5237
5433383e 5238 /* Load firmware blob. */
e315cd28 5239 blob = qla2x00_request_firmware(vha);
5433383e 5240 if (!blob) {
7c3df132
SK		 5241 ql_log(ql_log_warn, vha, 0x0090,
5242 "Fimware image unavailable.\n");
5243 ql_log(ql_log_warn, vha, 0x0091,
5244 "Firmware images can be retrieved from: "
5245 QLA_FW_URL ".\n");
d1c61909 5246
eaac30be 5247 return QLA_FUNCTION_FAILED;
0107109e
AV		 5248 }
5249
cfb0919c
CD		 5250 ql_dbg(ql_dbg_init, vha, 0x0092,
5251 "FW: Loading via request-firmware.\n");
eaac30be 5252
0107109e
AV		 5253 rval = QLA_SUCCESS;
5254
5255 segments = FA_RISC_CODE_SEGMENTS;
73208dfd 5256 dcode = (uint32_t *)req->ring;
0107109e 5257 *srisc_addr = 0;
5433383e 5258 fwcode = (uint32_t *)blob->fw->data;
0107109e
AV		 5259 fwclen = 0;
5260
5261 /* Validate firmware image by checking version. */
5433383e 5262 if (blob->fw->size < 8 * sizeof(uint32_t)) {
7c3df132
SK		 5263 ql_log(ql_log_fatal, vha, 0x0093,
5264 "Unable to verify integrity of firmware image (%Zd).\n",
5433383e 5265 blob->fw->size);
0107109e
AV		 5266 goto fail_fw_integrity;
5267 }
5268 for (i = 0; i < 4; i++)
5269 dcode[i] = be32_to_cpu(fwcode[i + 4]);
5270 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
5271 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
5272 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
5273 dcode[3] == 0)) {
7c3df132
SK		 5274 ql_log(ql_log_fatal, vha, 0x0094,
5275 "Unable to verify integrity of firmware image (%Zd).\n",
5276 blob->fw->size);
5277 ql_log(ql_log_fatal, vha, 0x0095,
5278 "Firmware data: %08x %08x %08x %08x.\n",
5279 dcode[0], dcode[1], dcode[2], dcode[3]);
0107109e
AV		 5280 goto fail_fw_integrity;
5281 }
5282
5283 while (segments && rval == QLA_SUCCESS) {
5284 risc_addr = be32_to_cpu(fwcode[2]);
5285 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
5286 risc_size = be32_to_cpu(fwcode[3]);
5287
5288 /* Validate firmware image size. */
5289 fwclen += risc_size * sizeof(uint32_t);
5433383e 5290 if (blob->fw->size < fwclen) {
7c3df132 5291 ql_log(ql_log_fatal, vha, 0x0096,
5433383e 5292 "Unable to verify integrity of firmware image "
7c3df132 5293 "(%Zd).\n", blob->fw->size);
5433383e 5294
0107109e
AV		 5295 goto fail_fw_integrity;
5296 }
5297
5298 fragment = 0;
5299 while (risc_size > 0 && rval == QLA_SUCCESS) {
5300 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
5301 if (dlen > risc_size)
5302 dlen = risc_size;
5303
7c3df132
SK		 5304 ql_dbg(ql_dbg_init, vha, 0x0097,
5305 "Loading risc segment@ risc addr %x "
5306 "number of dwords 0x%x.\n", risc_addr, dlen);
0107109e
AV		 5307
5308 for (i = 0; i < dlen; i++)
5309 dcode[i] = swab32(fwcode[i]);
5310
73208dfd 5311 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
590f98e5 5312 dlen);
0107109e 5313 if (rval) {
7c3df132
SK		 5314 ql_log(ql_log_fatal, vha, 0x0098,
5315 "Failed to load segment %d of firmware.\n",
5316 fragment);
0107109e
AV		 5317 break;
5318 }
5319
5320 fwcode += dlen;
5321 risc_addr += dlen;
5322 risc_size -= dlen;
5323 fragment++;
5324 }
5325
5326 /* Next segment. */
5327 segments--;
5328 }
0107109e
AV		 5329 return rval;
5330
5331fail_fw_integrity:
0107109e 5332 return QLA_FUNCTION_FAILED;
0107109e 5333}
18c6c127 5334
eaac30be
AV		 5335int
5336qla24xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5337{
5338 int rval;
5339
e337d907
AV		 5340 if (ql2xfwloadbin == 1)
5341 return qla81xx_load_risc(vha, srisc_addr);
5342
eaac30be
AV		 5343 /*
5344 * FW Load priority:
5345 * 1) Firmware via request-firmware interface (.bin file).
5346 * 2) Firmware residing in flash.
5347 */
5348 rval = qla24xx_load_risc_blob(vha, srisc_addr);
5349 if (rval == QLA_SUCCESS)
5350 return rval;
5351
cbc8eb67
AV		 5352 return qla24xx_load_risc_flash(vha, srisc_addr,
5353 vha->hw->flt_region_fw);
eaac30be
AV		 5354}
5355
5356int
5357qla81xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5358{
5359 int rval;
cbc8eb67 5360 struct qla_hw_data *ha = vha->hw;
eaac30be 5361
e337d907 5362 if (ql2xfwloadbin == 2)
cbc8eb67 5363 goto try_blob_fw;
e337d907 5364
eaac30be
AV		 5365 /*
5366 * FW Load priority:
5367 * 1) Firmware residing in flash.
5368 * 2) Firmware via request-firmware interface (.bin file).
cbc8eb67 5369 * 3) Golden-Firmware residing in flash -- limited operation.
eaac30be 5370 */
cbc8eb67 5371 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw);
eaac30be
AV		 5372 if (rval == QLA_SUCCESS)
5373 return rval;
5374
cbc8eb67
AV		 5375try_blob_fw:
5376 rval = qla24xx_load_risc_blob(vha, srisc_addr);
5377 if (rval == QLA_SUCCESS || !ha->flt_region_gold_fw)
5378 return rval;
5379
7c3df132
SK		 5380 ql_log(ql_log_info, vha, 0x0099,
5381 "Attempting to fallback to golden firmware.\n");
cbc8eb67
AV		 5382 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_gold_fw);
5383 if (rval != QLA_SUCCESS)
5384 return rval;
5385
7c3df132 5386 ql_log(ql_log_info, vha, 0x009a, "Update operational firmware.\n");
cbc8eb67 5387 ha->flags.running_gold_fw = 1;
cbc8eb67 5388 return rval;
eaac30be
AV		 5389}
5390
18c6c127 5391void
e315cd28 5392qla2x00_try_to_stop_firmware(scsi_qla_host_t *vha)
18c6c127
AV		 5393{
5394 int ret, retries;
e315cd28 5395 struct qla_hw_data *ha = vha->hw;
18c6c127 5396
85880801
AV		 5397 if (ha->flags.pci_channel_io_perm_failure)
5398 return;
e428924c 5399 if (!IS_FWI2_CAPABLE(ha))
18c6c127 5400 return;
75edf81d
AV		 5401 if (!ha->fw_major_version)
5402 return;
18c6c127 5403
e315cd28 5404 ret = qla2x00_stop_firmware(vha);
7c7f1f29 5405 for (retries = 5; ret != QLA_SUCCESS && ret != QLA_FUNCTION_TIMEOUT &&
b469a7cb 5406 ret != QLA_INVALID_COMMAND && retries ; retries--) {
e315cd28
AC		 5407 ha->isp_ops->reset_chip(vha);
5408 if (ha->isp_ops->chip_diag(vha) != QLA_SUCCESS)
18c6c127 5409 continue;
e315cd28 5410 if (qla2x00_setup_chip(vha) != QLA_SUCCESS)
18c6c127 5411 continue;
7c3df132
SK		 5412 ql_log(ql_log_info, vha, 0x8015,
5413 "Attempting retry of stop-firmware command.\n");
e315cd28 5414 ret = qla2x00_stop_firmware(vha);
18c6c127
AV		 5415 }
5416}
2c3dfe3f
SJ		 5417
5418int
e315cd28 5419qla24xx_configure_vhba(scsi_qla_host_t *vha)
2c3dfe3f
SJ		 5420{
5421 int rval = QLA_SUCCESS;
0b91d116 5422 int rval2;
2c3dfe3f 5423 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28
AC		 5424 struct qla_hw_data *ha = vha->hw;
5425 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
67c2e93a
AC		 5426 struct req_que *req;
5427 struct rsp_que *rsp;
2c3dfe3f 5428
e315cd28 5429 if (!vha->vp_idx)
2c3dfe3f
SJ		 5430 return -EINVAL;
5431
e315cd28 5432 rval = qla2x00_fw_ready(base_vha);
7163ea81 5433 if (ha->flags.cpu_affinity_enabled)
67c2e93a
AC		 5434 req = ha->req_q_map[0];
5435 else
5436 req = vha->req;
5437 rsp = req->rsp;
5438
2c3dfe3f 5439 if (rval == QLA_SUCCESS) {
e315cd28 5440 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
73208dfd 5441 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
2c3dfe3f
SJ		 5442 }
5443
e315cd28 5444 vha->flags.management_server_logged_in = 0;
2c3dfe3f
SJ		 5445
5446 /* Login to SNS first */
0b91d116
CD		 5447 rval2 = ha->isp_ops->fabric_login(vha, NPH_SNS, 0xff, 0xff, 0xfc, mb,
5448 BIT_1);
5449 if (rval2 != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) {
5450 if (rval2 == QLA_MEMORY_ALLOC_FAILED)
5451 ql_dbg(ql_dbg_init, vha, 0x0120,
5452 "Failed SNS login: loop_id=%x, rval2=%d\n",
5453 NPH_SNS, rval2);
5454 else
5455 ql_dbg(ql_dbg_init, vha, 0x0103,
5456 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x "
5457 "mb[2]=%x mb[6]=%x mb[7]=%x.\n",
5458 NPH_SNS, mb[0], mb[1], mb[2], mb[6], mb[7]);
2c3dfe3f
SJ		 5459 return (QLA_FUNCTION_FAILED);
5460 }
5461
e315cd28
AC		 5462 atomic_set(&vha->loop_down_timer, 0);
5463 atomic_set(&vha->loop_state, LOOP_UP);
5464 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5465 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
5466 rval = qla2x00_loop_resync(base_vha);
2c3dfe3f
SJ		 5467
5468 return rval;
5469}
4d4df193
HK		 5470
5471/* 84XX Support **************************************************************/
5472
5473static LIST_HEAD(qla_cs84xx_list);
5474static DEFINE_MUTEX(qla_cs84xx_mutex);
5475
5476static struct qla_chip_state_84xx *
e315cd28 5477qla84xx_get_chip(struct scsi_qla_host *vha)
4d4df193
HK		 5478{
5479 struct qla_chip_state_84xx *cs84xx;
e315cd28 5480 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 5481
5482 mutex_lock(&qla_cs84xx_mutex);
5483
5484 /* Find any shared 84xx chip. */
5485 list_for_each_entry(cs84xx, &qla_cs84xx_list, list) {
5486 if (cs84xx->bus == ha->pdev->bus) {
5487 kref_get(&cs84xx->kref);
5488 goto done;
5489 }
5490 }
5491
5492 cs84xx = kzalloc(sizeof(*cs84xx), GFP_KERNEL);
5493 if (!cs84xx)
5494 goto done;
5495
5496 kref_init(&cs84xx->kref);
5497 spin_lock_init(&cs84xx->access_lock);
5498 mutex_init(&cs84xx->fw_update_mutex);
5499 cs84xx->bus = ha->pdev->bus;
5500
5501 list_add_tail(&cs84xx->list, &qla_cs84xx_list);
5502done:
5503 mutex_unlock(&qla_cs84xx_mutex);
5504 return cs84xx;
5505}
5506
5507static void
5508__qla84xx_chip_release(struct kref *kref)
5509{
5510 struct qla_chip_state_84xx *cs84xx =
5511 container_of(kref, struct qla_chip_state_84xx, kref);
5512
5513 mutex_lock(&qla_cs84xx_mutex);
5514 list_del(&cs84xx->list);
5515 mutex_unlock(&qla_cs84xx_mutex);
5516 kfree(cs84xx);
5517}
5518
5519void
e315cd28 5520qla84xx_put_chip(struct scsi_qla_host *vha)
4d4df193 5521{
e315cd28 5522 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 5523 if (ha->cs84xx)
5524 kref_put(&ha->cs84xx->kref, __qla84xx_chip_release);
5525}
5526
5527static int
e315cd28 5528qla84xx_init_chip(scsi_qla_host_t *vha)
4d4df193
HK		 5529{
5530 int rval;
5531 uint16_t status[2];
e315cd28 5532 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 5533
5534 mutex_lock(&ha->cs84xx->fw_update_mutex);
5535
e315cd28 5536 rval = qla84xx_verify_chip(vha, status);
4d4df193
HK		 5537
5538 mutex_unlock(&ha->cs84xx->fw_update_mutex);
5539
5540 return rval != QLA_SUCCESS || status[0] ? QLA_FUNCTION_FAILED:
5541 QLA_SUCCESS;
5542}
3a03eb79
AV		 5543
5544/* 81XX Support **************************************************************/
5545
5546int
5547qla81xx_nvram_config(scsi_qla_host_t *vha)
5548{
5549 int rval;
5550 struct init_cb_81xx *icb;
5551 struct nvram_81xx *nv;
5552 uint32_t *dptr;
5553 uint8_t *dptr1, *dptr2;
5554 uint32_t chksum;
5555 uint16_t cnt;
5556 struct qla_hw_data *ha = vha->hw;
5557
5558 rval = QLA_SUCCESS;
5559 icb = (struct init_cb_81xx *)ha->init_cb;
5560 nv = ha->nvram;
5561
5562 /* Determine NVRAM starting address. */
5563 ha->nvram_size = sizeof(struct nvram_81xx);
3a03eb79 5564 ha->vpd_size = FA_NVRAM_VPD_SIZE;
7ec0effd
AD		 5565 if (IS_P3P_TYPE(ha) || IS_QLA8031(ha))
5566 ha->vpd_size = FA_VPD_SIZE_82XX;
3a03eb79
AV		 5567
5568 /* Get VPD data into cache */
5569 ha->vpd = ha->nvram + VPD_OFFSET;
3d79038f
AV		 5570 ha->isp_ops->read_optrom(vha, ha->vpd, ha->flt_region_vpd << 2,
5571 ha->vpd_size);
3a03eb79
AV		 5572
5573 /* Get NVRAM data into cache and calculate checksum. */
3d79038f 5574 ha->isp_ops->read_optrom(vha, ha->nvram, ha->flt_region_nvram << 2,
3a03eb79 5575 ha->nvram_size);
3d79038f 5576 dptr = (uint32_t *)nv;
3a03eb79
AV		 5577 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++)
5578 chksum += le32_to_cpu(*dptr++);
5579
7c3df132
SK		 5580 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0111,
5581 "Contents of NVRAM:\n");
5582 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0112,
5583 (uint8_t *)nv, ha->nvram_size);
3a03eb79
AV		 5584
5585 /* Bad NVRAM data, set defaults parameters. */
5586 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
5587 || nv->id[3] != ' ' ||
5588 nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) {
5589 /* Reset NVRAM data. */
7c3df132 5590 ql_log(ql_log_info, vha, 0x0073,
9e336520 5591 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
7c3df132 5592 "version=0x%x.\n", chksum, nv->id[0],
3a03eb79 5593 le16_to_cpu(nv->nvram_version));
7c3df132
SK		 5594 ql_log(ql_log_info, vha, 0x0074,
5595 "Falling back to functioning (yet invalid -- WWPN) "
5596 "defaults.\n");
3a03eb79
AV		 5597
5598 /*
5599 * Set default initialization control block.
5600 */
5601 memset(nv, 0, ha->nvram_size);
5602 nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION);
5603 nv->version = __constant_cpu_to_le16(ICB_VERSION);
5604 nv->frame_payload_size = __constant_cpu_to_le16(2048);
5605 nv->execution_throttle = __constant_cpu_to_le16(0xFFFF);
5606 nv->exchange_count = __constant_cpu_to_le16(0);
5607 nv->port_name[0] = 0x21;
e5b68a61 5608 nv->port_name[1] = 0x00 + ha->port_no;
3a03eb79
AV		 5609 nv->port_name[2] = 0x00;
5610 nv->port_name[3] = 0xe0;
5611 nv->port_name[4] = 0x8b;
5612 nv->port_name[5] = 0x1c;
5613 nv->port_name[6] = 0x55;
5614 nv->port_name[7] = 0x86;
5615 nv->node_name[0] = 0x20;
5616 nv->node_name[1] = 0x00;
5617 nv->node_name[2] = 0x00;
5618 nv->node_name[3] = 0xe0;
5619 nv->node_name[4] = 0x8b;
5620 nv->node_name[5] = 0x1c;
5621 nv->node_name[6] = 0x55;
5622 nv->node_name[7] = 0x86;
5623 nv->login_retry_count = __constant_cpu_to_le16(8);
5624 nv->interrupt_delay_timer = __constant_cpu_to_le16(0);
5625 nv->login_timeout = __constant_cpu_to_le16(0);
5626 nv->firmware_options_1 =
5627 __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
5628 nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4);
5629 nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12);
5630 nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13);
5631 nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10);
5632 nv->efi_parameters = __constant_cpu_to_le32(0);
5633 nv->reset_delay = 5;
5634 nv->max_luns_per_target = __constant_cpu_to_le16(128);
5635 nv->port_down_retry_count = __constant_cpu_to_le16(30);
6246b8a1 5636 nv->link_down_timeout = __constant_cpu_to_le16(180);
eeebcc92 5637 nv->enode_mac[0] = 0x00;
6246b8a1
GM		 5638 nv->enode_mac[1] = 0xC0;
5639 nv->enode_mac[2] = 0xDD;
3a03eb79
AV		 5640 nv->enode_mac[3] = 0x04;
5641 nv->enode_mac[4] = 0x05;
e5b68a61 5642 nv->enode_mac[5] = 0x06 + ha->port_no;
3a03eb79
AV		 5643
5644 rval = 1;
5645 }
5646
9e522cd8
AE		 5647 if (IS_T10_PI_CAPABLE(ha))
5648 nv->frame_payload_size &= ~7;
5649
aa230bc5
AE		 5650 qlt_81xx_config_nvram_stage1(vha, nv);
5651
3a03eb79 5652 /* Reset Initialization control block */
773120e4 5653 memset(icb, 0, ha->init_cb_size);
3a03eb79
AV		 5654
5655 /* Copy 1st segment. */
5656 dptr1 = (uint8_t *)icb;
5657 dptr2 = (uint8_t *)&nv->version;
5658 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
5659 while (cnt--)
5660 *dptr1++ = *dptr2++;
5661
5662 icb->login_retry_count = nv->login_retry_count;
5663
5664 /* Copy 2nd segment. */
5665 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
5666 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
5667 cnt = (uint8_t *)&icb->reserved_5 -
5668 (uint8_t *)&icb->interrupt_delay_timer;
5669 while (cnt--)
5670 *dptr1++ = *dptr2++;
5671
5672 memcpy(icb->enode_mac, nv->enode_mac, sizeof(icb->enode_mac));
5673 /* Some boards (with valid NVRAMs) still have NULL enode_mac!! */
5674 if (!memcmp(icb->enode_mac, "\0\0\0\0\0\0", sizeof(icb->enode_mac))) {
69e5f1ea
AV		 5675 icb->enode_mac[0] = 0x00;
5676 icb->enode_mac[1] = 0xC0;
5677 icb->enode_mac[2] = 0xDD;
3a03eb79
AV		 5678 icb->enode_mac[3] = 0x04;
5679 icb->enode_mac[4] = 0x05;
e5b68a61 5680 icb->enode_mac[5] = 0x06 + ha->port_no;
3a03eb79
AV		 5681 }
5682
b64b0e8f
AV		 5683 /* Use extended-initialization control block. */
5684 memcpy(ha->ex_init_cb, &nv->ex_version, sizeof(*ha->ex_init_cb));
5685
3a03eb79
AV		 5686 /*
5687 * Setup driver NVRAM options.
5688 */
5689 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
a9083016 5690 "QLE8XXX");
3a03eb79 5691
aa230bc5
AE		 5692 qlt_81xx_config_nvram_stage2(vha, icb);
5693
3a03eb79
AV		 5694 /* Use alternate WWN? */
5695 if (nv->host_p & __constant_cpu_to_le32(BIT_15)) {
5696 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
5697 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
5698 }
5699
5700 /* Prepare nodename */
5701 if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) {
5702 /*
5703 * Firmware will apply the following mask if the nodename was
5704 * not provided.
5705 */
5706 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
5707 icb->node_name[0] &= 0xF0;
5708 }
5709
5710 /* Set host adapter parameters. */
5711 ha->flags.disable_risc_code_load = 0;
5712 ha->flags.enable_lip_reset = 0;
5713 ha->flags.enable_lip_full_login =
5714 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
5715 ha->flags.enable_target_reset =
5716 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
5717 ha->flags.enable_led_scheme = 0;
5718 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
5719
5720 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
5721 (BIT_6 | BIT_5 | BIT_4)) >> 4;
5722
5723 /* save HBA serial number */
5724 ha->serial0 = icb->port_name[5];
5725 ha->serial1 = icb->port_name[6];
5726 ha->serial2 = icb->port_name[7];
5727 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
5728 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
5729
5730 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
5731
5732 ha->retry_count = le16_to_cpu(nv->login_retry_count);
5733
5734 /* Set minimum login_timeout to 4 seconds. */
5735 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
5736 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
5737 if (le16_to_cpu(nv->login_timeout) < 4)
5738 nv->login_timeout = __constant_cpu_to_le16(4);
5739 ha->login_timeout = le16_to_cpu(nv->login_timeout);
5740 icb->login_timeout = nv->login_timeout;
5741
5742 /* Set minimum RATOV to 100 tenths of a second. */
5743 ha->r_a_tov = 100;
5744
5745 ha->loop_reset_delay = nv->reset_delay;
5746
5747 /* Link Down Timeout = 0:
5748 *
7ec0effd 5749 * When Port Down timer expires we will start returning
3a03eb79
AV		 5750 * I/O's to OS with "DID_NO_CONNECT".
5751 *
5752 * Link Down Timeout != 0:
5753 *
5754 * The driver waits for the link to come up after link down
5755 * before returning I/Os to OS with "DID_NO_CONNECT".
5756 */
5757 if (le16_to_cpu(nv->link_down_timeout) == 0) {
5758 ha->loop_down_abort_time =
5759 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
5760 } else {
5761 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
5762 ha->loop_down_abort_time =
5763 (LOOP_DOWN_TIME - ha->link_down_timeout);
5764 }
5765
5766 /* Need enough time to try and get the port back. */
5767 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
5768 if (qlport_down_retry)
5769 ha->port_down_retry_count = qlport_down_retry;
5770
5771 /* Set login_retry_count */
5772 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
5773 if (ha->port_down_retry_count ==
5774 le16_to_cpu(nv->port_down_retry_count) &&
5775 ha->port_down_retry_count > 3)
5776 ha->login_retry_count = ha->port_down_retry_count;
5777 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
5778 ha->login_retry_count = ha->port_down_retry_count;
5779 if (ql2xloginretrycount)
5780 ha->login_retry_count = ql2xloginretrycount;
5781
6246b8a1
GM		 5782 /* if not running MSI-X we need handshaking on interrupts */
5783 if (!vha->hw->flags.msix_enabled && IS_QLA83XX(ha))
5784 icb->firmware_options_2 |= __constant_cpu_to_le32(BIT_22);
5785
3a03eb79
AV		 5786 /* Enable ZIO. */
5787 if (!vha->flags.init_done) {
5788 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
5789 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
5790 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
5791 le16_to_cpu(icb->interrupt_delay_timer): 2;
5792 }
5793 icb->firmware_options_2 &= __constant_cpu_to_le32(
5794 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
5795 vha->flags.process_response_queue = 0;
5796 if (ha->zio_mode != QLA_ZIO_DISABLED) {
5797 ha->zio_mode = QLA_ZIO_MODE_6;
5798
7c3df132 5799 ql_log(ql_log_info, vha, 0x0075,
3a03eb79 5800 "ZIO mode %d enabled; timer delay (%d us).\n",
7c3df132
SK		 5801 ha->zio_mode,
5802 ha->zio_timer * 100);
3a03eb79
AV		 5803
5804 icb->firmware_options_2 |= cpu_to_le32(
5805 (uint32_t)ha->zio_mode);
5806 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
5807 vha->flags.process_response_queue = 1;
5808 }
5809
5810 if (rval) {
7c3df132
SK		 5811 ql_log(ql_log_warn, vha, 0x0076,
5812 "NVRAM configuration failed.\n");
3a03eb79
AV		 5813 }
5814 return (rval);
5815}
5816
a9083016
GM		 5817int
5818qla82xx_restart_isp(scsi_qla_host_t *vha)
5819{
5820 int status, rval;
5821 uint32_t wait_time;
5822 struct qla_hw_data *ha = vha->hw;
5823 struct req_que *req = ha->req_q_map[0];
5824 struct rsp_que *rsp = ha->rsp_q_map[0];
5825 struct scsi_qla_host *vp;
feafb7b1 5826 unsigned long flags;
a9083016
GM		 5827
5828 status = qla2x00_init_rings(vha);
5829 if (!status) {
5830 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
5831 ha->flags.chip_reset_done = 1;
5832
5833 status = qla2x00_fw_ready(vha);
5834 if (!status) {
7c3df132
SK		 5835 ql_log(ql_log_info, vha, 0x803c,
5836 "Start configure loop, status =%d.\n", status);
a9083016
GM		 5837
5838 /* Issue a marker after FW becomes ready. */
5839 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
5840
5841 vha->flags.online = 1;
5842 /* Wait at most MAX_TARGET RSCNs for a stable link. */
5843 wait_time = 256;
5844 do {
5845 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5846 qla2x00_configure_loop(vha);
5847 wait_time--;
5848 } while (!atomic_read(&vha->loop_down_timer) &&
5849 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) &&
5850 wait_time &&
5851 (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)));
5852 }
5853
5854 /* if no cable then assume it's good */
5855 if ((vha->device_flags & DFLG_NO_CABLE))
5856 status = 0;
5857
cfb0919c 5858 ql_log(ql_log_info, vha, 0x8000,
7c3df132 5859 "Configure loop done, status = 0x%x.\n", status);
a9083016
GM		 5860 }
5861
5862 if (!status) {
5863 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
5864
5865 if (!atomic_read(&vha->loop_down_timer)) {
5866 /*
5867 * Issue marker command only when we are going
5868 * to start the I/O .
5869 */
5870 vha->marker_needed = 1;
5871 }
5872
5873 vha->flags.online = 1;
5874
5875 ha->isp_ops->enable_intrs(ha);
5876
5877 ha->isp_abort_cnt = 0;
5878 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
5879
53296788 5880 /* Update the firmware version */
3173167f 5881 status = qla82xx_check_md_needed(vha);
53296788 5882
a9083016
GM		 5883 if (ha->fce) {
5884 ha->flags.fce_enabled = 1;
5885 memset(ha->fce, 0,
5886 fce_calc_size(ha->fce_bufs));
5887 rval = qla2x00_enable_fce_trace(vha,
5888 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
5889 &ha->fce_bufs);
5890 if (rval) {
cfb0919c 5891 ql_log(ql_log_warn, vha, 0x8001,
7c3df132
SK		 5892 "Unable to reinitialize FCE (%d).\n",
5893 rval);
a9083016
GM		 5894 ha->flags.fce_enabled = 0;
5895 }
5896 }
5897
5898 if (ha->eft) {
5899 memset(ha->eft, 0, EFT_SIZE);
5900 rval = qla2x00_enable_eft_trace(vha,
5901 ha->eft_dma, EFT_NUM_BUFFERS);
5902 if (rval) {
cfb0919c 5903 ql_log(ql_log_warn, vha, 0x8010,
7c3df132
SK		 5904 "Unable to reinitialize EFT (%d).\n",
5905 rval);
a9083016
GM		 5906 }
5907 }
a9083016
GM		 5908 }
5909
5910 if (!status) {
cfb0919c 5911 ql_dbg(ql_dbg_taskm, vha, 0x8011,
7c3df132 5912 "qla82xx_restart_isp succeeded.\n");
feafb7b1
AE		 5913
5914 spin_lock_irqsave(&ha->vport_slock, flags);
5915 list_for_each_entry(vp, &ha->vp_list, list) {
5916 if (vp->vp_idx) {
5917 atomic_inc(&vp->vref_count);
5918 spin_unlock_irqrestore(&ha->vport_slock, flags);
5919
a9083016 5920 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 5921
5922 spin_lock_irqsave(&ha->vport_slock, flags);
5923 atomic_dec(&vp->vref_count);
5924 }
a9083016 5925 }
feafb7b1
AE		 5926 spin_unlock_irqrestore(&ha->vport_slock, flags);
5927
a9083016 5928 } else {
cfb0919c 5929 ql_log(ql_log_warn, vha, 0x8016,
7c3df132 5930 "qla82xx_restart_isp **** FAILED ****.\n");
a9083016
GM		 5931 }
5932
5933 return status;
5934}
5935
3a03eb79 5936void
ae97c91e 5937qla81xx_update_fw_options(scsi_qla_host_t *vha)
3a03eb79 5938{
ae97c91e
AV		 5939 struct qla_hw_data *ha = vha->hw;
5940
5941 if (!ql2xetsenable)
5942 return;
5943
5944 /* Enable ETS Burst. */
5945 memset(ha->fw_options, 0, sizeof(ha->fw_options));
5946 ha->fw_options[2] |= BIT_9;
5947 qla2x00_set_fw_options(vha, ha->fw_options);
3a03eb79 5948}
09ff701a
SR		 5949
5950/*
5951 * qla24xx_get_fcp_prio
5952 * Gets the fcp cmd priority value for the logged in port.
5953 * Looks for a match of the port descriptors within
5954 * each of the fcp prio config entries. If a match is found,
5955 * the tag (priority) value is returned.
5956 *
5957 * Input:
21090cbe 5958 * vha = scsi host structure pointer.
09ff701a
SR		 5959 * fcport = port structure pointer.
5960 *
5961 * Return:
6c452a45 5962 * non-zero (if found)
f28a0a96 5963 * -1 (if not found)
09ff701a
SR		 5964 *
5965 * Context:
5966 * Kernel context
5967 */
f28a0a96 5968static int
09ff701a
SR		 5969qla24xx_get_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
5970{
5971 int i, entries;
5972 uint8_t pid_match, wwn_match;
f28a0a96 5973 int priority;
09ff701a
SR		 5974 uint32_t pid1, pid2;
5975 uint64_t wwn1, wwn2;
5976 struct qla_fcp_prio_entry *pri_entry;
5977 struct qla_hw_data *ha = vha->hw;
5978
5979 if (!ha->fcp_prio_cfg || !ha->flags.fcp_prio_enabled)
f28a0a96 5980 return -1;
09ff701a 5981
f28a0a96 5982 priority = -1;
09ff701a
SR		 5983 entries = ha->fcp_prio_cfg->num_entries;
5984 pri_entry = &ha->fcp_prio_cfg->entry[0];
5985
5986 for (i = 0; i < entries; i++) {
5987 pid_match = wwn_match = 0;
5988
5989 if (!(pri_entry->flags & FCP_PRIO_ENTRY_VALID)) {
5990 pri_entry++;
5991 continue;
5992 }
5993
5994 /* check source pid for a match */
5995 if (pri_entry->flags & FCP_PRIO_ENTRY_SPID_VALID) {
5996 pid1 = pri_entry->src_pid & INVALID_PORT_ID;
5997 pid2 = vha->d_id.b24 & INVALID_PORT_ID;
5998 if (pid1 == INVALID_PORT_ID)
5999 pid_match++;
6000 else if (pid1 == pid2)
6001 pid_match++;
6002 }
6003
6004 /* check destination pid for a match */
6005 if (pri_entry->flags & FCP_PRIO_ENTRY_DPID_VALID) {
6006 pid1 = pri_entry->dst_pid & INVALID_PORT_ID;
6007 pid2 = fcport->d_id.b24 & INVALID_PORT_ID;
6008 if (pid1 == INVALID_PORT_ID)
6009 pid_match++;
6010 else if (pid1 == pid2)
6011 pid_match++;
6012 }
6013
6014 /* check source WWN for a match */
6015 if (pri_entry->flags & FCP_PRIO_ENTRY_SWWN_VALID) {
6016 wwn1 = wwn_to_u64(vha->port_name);
6017 wwn2 = wwn_to_u64(pri_entry->src_wwpn);
6018 if (wwn2 == (uint64_t)-1)
6019 wwn_match++;
6020 else if (wwn1 == wwn2)
6021 wwn_match++;
6022 }
6023
6024 /* check destination WWN for a match */
6025 if (pri_entry->flags & FCP_PRIO_ENTRY_DWWN_VALID) {
6026 wwn1 = wwn_to_u64(fcport->port_name);
6027 wwn2 = wwn_to_u64(pri_entry->dst_wwpn);
6028 if (wwn2 == (uint64_t)-1)
6029 wwn_match++;
6030 else if (wwn1 == wwn2)
6031 wwn_match++;
6032 }
6033
6034 if (pid_match == 2 || wwn_match == 2) {
6035 /* Found a matching entry */
6036 if (pri_entry->flags & FCP_PRIO_ENTRY_TAG_VALID)
6037 priority = pri_entry->tag;
6038 break;
6039 }
6040
6041 pri_entry++;
6042 }
6043
6044 return priority;
6045}
6046
6047/*
6048 * qla24xx_update_fcport_fcp_prio
6049 * Activates fcp priority for the logged in fc port
6050 *
6051 * Input:
21090cbe 6052 * vha = scsi host structure pointer.
09ff701a
SR		 6053 * fcp = port structure pointer.
6054 *
6055 * Return:
6056 * QLA_SUCCESS or QLA_FUNCTION_FAILED
6057 *
6058 * Context:
6059 * Kernel context.
6060 */
6061int
21090cbe 6062qla24xx_update_fcport_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
09ff701a
SR		 6063{
6064 int ret;
f28a0a96 6065 int priority;
09ff701a
SR		 6066 uint16_t mb[5];
6067
21090cbe
MI		 6068 if (fcport->port_type != FCT_TARGET ||
6069 fcport->loop_id == FC_NO_LOOP_ID)
09ff701a
SR		 6070 return QLA_FUNCTION_FAILED;
6071
21090cbe 6072 priority = qla24xx_get_fcp_prio(vha, fcport);
f28a0a96
AV		 6073 if (priority < 0)
6074 return QLA_FUNCTION_FAILED;
6075
7ec0effd 6076 if (IS_P3P_TYPE(vha->hw)) {
a00f6296
SK		 6077 fcport->fcp_prio = priority & 0xf;
6078 return QLA_SUCCESS;
6079 }
6080
21090cbe 6081 ret = qla24xx_set_fcp_prio(vha, fcport->loop_id, priority, mb);
cfb0919c
CD		 6082 if (ret == QLA_SUCCESS) {
6083 if (fcport->fcp_prio != priority)
6084 ql_dbg(ql_dbg_user, vha, 0x709e,
6085 "Updated FCP_CMND priority - value=%d loop_id=%d "
6086 "port_id=%02x%02x%02x.\n", priority,
6087 fcport->loop_id, fcport->d_id.b.domain,
6088 fcport->d_id.b.area, fcport->d_id.b.al_pa);
a00f6296 6089 fcport->fcp_prio = priority & 0xf;
cfb0919c 6090 } else
7c3df132 6091 ql_dbg(ql_dbg_user, vha, 0x704f,
cfb0919c
CD		 6092 "Unable to update FCP_CMND priority - ret=0x%x for "
6093 "loop_id=%d port_id=%02x%02x%02x.\n", ret, fcport->loop_id,
6094 fcport->d_id.b.domain, fcport->d_id.b.area,
6095 fcport->d_id.b.al_pa);
09ff701a
SR		 6096 return ret;
6097}
6098
6099/*
6100 * qla24xx_update_all_fcp_prio
6101 * Activates fcp priority for all the logged in ports
6102 *
6103 * Input:
6104 * ha = adapter block pointer.
6105 *
6106 * Return:
6107 * QLA_SUCCESS or QLA_FUNCTION_FAILED
6108 *
6109 * Context:
6110 * Kernel context.
6111 */
6112int
6113qla24xx_update_all_fcp_prio(scsi_qla_host_t *vha)
6114{
6115 int ret;
6116 fc_port_t *fcport;
6117
6118 ret = QLA_FUNCTION_FAILED;
6119 /* We need to set priority for all logged in ports */
6120 list_for_each_entry(fcport, &vha->vp_fcports, list)
6121 ret = qla24xx_update_fcport_fcp_prio(vha, fcport);
6122
6123 return ret;
6124}
Linux kernel - Deliverables
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