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8ae6d9c7 GM |
1 | /* |
2 | * QLogic Fibre Channel HBA Driver | |
bd21eaf9 | 3 | * Copyright (c) 2003-2014 QLogic Corporation |
8ae6d9c7 GM |
4 | * |
5 | * See LICENSE.qla2xxx for copyright and licensing details. | |
6 | */ | |
7 | #ifndef __QLA_MR_H | |
8 | #define __QLA_MR_H | |
9 | ||
10 | /* | |
11 | * The PCI VendorID and DeviceID for our board. | |
12 | */ | |
13 | #define PCI_DEVICE_ID_QLOGIC_ISPF001 0xF001 | |
14 | ||
15 | /* FX00 specific definitions */ | |
16 | ||
17 | #define FX00_COMMAND_TYPE_7 0x07 /* Command Type 7 entry for 7XXX */ | |
18 | struct cmd_type_7_fx00 { | |
19 | uint8_t entry_type; /* Entry type. */ | |
20 | uint8_t entry_count; /* Entry count. */ | |
21 | uint8_t sys_define; /* System defined. */ | |
22 | uint8_t entry_status; /* Entry Status. */ | |
23 | ||
24 | uint32_t handle; /* System handle. */ | |
d68b3e01 AB |
25 | uint8_t reserved_0; |
26 | uint8_t port_path_ctrl; | |
27 | uint16_t reserved_1; | |
8ae6d9c7 | 28 | |
1f8deefe | 29 | __le16 tgt_idx; /* Target Idx. */ |
8ae6d9c7 GM |
30 | uint16_t timeout; /* Command timeout. */ |
31 | ||
1f8deefe | 32 | __le16 dseg_count; /* Data segment count. */ |
d68b3e01 AB |
33 | uint8_t scsi_rsp_dsd_len; |
34 | uint8_t reserved_2; | |
8ae6d9c7 GM |
35 | |
36 | struct scsi_lun lun; /* LUN (LE). */ | |
37 | ||
38 | uint8_t cntrl_flags; | |
39 | ||
40 | uint8_t task_mgmt_flags; /* Task management flags. */ | |
41 | ||
42 | uint8_t task; | |
43 | ||
44 | uint8_t crn; | |
45 | ||
46 | uint8_t fcp_cdb[MAX_CMDSZ]; /* SCSI command words. */ | |
1f8deefe | 47 | __le32 byte_count; /* Total byte count. */ |
8ae6d9c7 GM |
48 | |
49 | uint32_t dseg_0_address[2]; /* Data segment 0 address. */ | |
50 | uint32_t dseg_0_len; /* Data segment 0 length. */ | |
51 | }; | |
52 | ||
8ae6d9c7 GM |
53 | #define STATUS_TYPE_FX00 0x01 /* Status entry. */ |
54 | struct sts_entry_fx00 { | |
55 | uint8_t entry_type; /* Entry type. */ | |
56 | uint8_t entry_count; /* Entry count. */ | |
57 | uint8_t sys_define; /* System defined. */ | |
58 | uint8_t entry_status; /* Entry Status. */ | |
59 | ||
60 | uint32_t handle; /* System handle. */ | |
d68b3e01 | 61 | uint32_t reserved_3; /* System handle. */ |
8ae6d9c7 | 62 | |
1f8deefe | 63 | __le16 comp_status; /* Completion status. */ |
8ae6d9c7 GM |
64 | uint16_t reserved_0; /* OX_ID used by the firmware. */ |
65 | ||
1f8deefe | 66 | __le32 residual_len; /* FW calc residual transfer length. */ |
8ae6d9c7 GM |
67 | |
68 | uint16_t reserved_1; | |
69 | uint16_t state_flags; /* State flags. */ | |
70 | ||
71 | uint16_t reserved_2; | |
1f8deefe | 72 | __le16 scsi_status; /* SCSI status. */ |
8ae6d9c7 GM |
73 | |
74 | uint32_t sense_len; /* FCP SENSE length. */ | |
75 | uint8_t data[32]; /* FCP response/sense information. */ | |
76 | }; | |
77 | ||
78 | ||
79 | #define MAX_HANDLE_COUNT 15 | |
80 | #define MULTI_STATUS_TYPE_FX00 0x0D | |
81 | ||
82 | struct multi_sts_entry_fx00 { | |
83 | uint8_t entry_type; /* Entry type. */ | |
d68b3e01 | 84 | uint8_t entry_count; /* Entry count. */ |
8ae6d9c7 GM |
85 | uint8_t handle_count; |
86 | uint8_t entry_status; | |
87 | ||
1f8deefe | 88 | __le32 handles[MAX_HANDLE_COUNT]; |
8ae6d9c7 GM |
89 | }; |
90 | ||
91 | #define TSK_MGMT_IOCB_TYPE_FX00 0x05 | |
92 | struct tsk_mgmt_entry_fx00 { | |
93 | uint8_t entry_type; /* Entry type. */ | |
94 | uint8_t entry_count; /* Entry count. */ | |
95 | uint8_t sys_define; | |
96 | uint8_t entry_status; /* Entry Status. */ | |
97 | ||
1f8deefe | 98 | __le32 handle; /* System handle. */ |
8ae6d9c7 | 99 | |
d68b3e01 | 100 | uint32_t reserved_0; |
8ae6d9c7 | 101 | |
1f8deefe | 102 | __le16 tgt_id; /* Target Idx. */ |
8ae6d9c7 GM |
103 | |
104 | uint16_t reserved_1; | |
d68b3e01 AB |
105 | uint16_t reserved_3; |
106 | uint16_t reserved_4; | |
8ae6d9c7 GM |
107 | |
108 | struct scsi_lun lun; /* LUN (LE). */ | |
109 | ||
1f8deefe | 110 | __le32 control_flags; /* Control Flags. */ |
8ae6d9c7 GM |
111 | |
112 | uint8_t reserved_2[32]; | |
113 | }; | |
114 | ||
115 | ||
116 | #define ABORT_IOCB_TYPE_FX00 0x08 /* Abort IOCB status. */ | |
117 | struct abort_iocb_entry_fx00 { | |
118 | uint8_t entry_type; /* Entry type. */ | |
119 | uint8_t entry_count; /* Entry count. */ | |
120 | uint8_t sys_define; /* System defined. */ | |
121 | uint8_t entry_status; /* Entry Status. */ | |
122 | ||
1f8deefe | 123 | __le32 handle; /* System handle. */ |
d68b3e01 | 124 | __le32 reserved_0; |
8ae6d9c7 | 125 | |
1f8deefe SK |
126 | __le16 tgt_id_sts; /* Completion status. */ |
127 | __le16 options; | |
8ae6d9c7 | 128 | |
1f8deefe | 129 | __le32 abort_handle; /* System handle. */ |
d68b3e01 | 130 | __le32 reserved_2; |
8ae6d9c7 | 131 | |
1f8deefe | 132 | __le16 req_que_no; |
8ae6d9c7 GM |
133 | uint8_t reserved_1[38]; |
134 | }; | |
135 | ||
136 | #define IOCTL_IOSB_TYPE_FX00 0x0C | |
137 | struct ioctl_iocb_entry_fx00 { | |
138 | uint8_t entry_type; /* Entry type. */ | |
139 | uint8_t entry_count; /* Entry count. */ | |
140 | uint8_t sys_define; /* System defined. */ | |
141 | uint8_t entry_status; /* Entry Status. */ | |
142 | ||
143 | uint32_t handle; /* System handle. */ | |
144 | uint32_t reserved_0; /* System handle. */ | |
145 | ||
146 | uint16_t comp_func_num; | |
1f8deefe | 147 | __le16 fw_iotcl_flags; |
8ae6d9c7 | 148 | |
1f8deefe | 149 | __le32 dataword_r; /* Data word returned */ |
8ae6d9c7 | 150 | uint32_t adapid; /* Adapter ID */ |
d68b3e01 | 151 | uint32_t dataword_r_extra; |
8ae6d9c7 | 152 | |
1f8deefe | 153 | __le32 seq_no; |
8ae6d9c7 GM |
154 | uint8_t reserved_2[20]; |
155 | uint32_t residuallen; | |
1f8deefe | 156 | __le32 status; |
8ae6d9c7 GM |
157 | }; |
158 | ||
159 | #define STATUS_CONT_TYPE_FX00 0x04 | |
160 | ||
161 | #define FX00_IOCB_TYPE 0x0B | |
162 | struct fxdisc_entry_fx00 { | |
163 | uint8_t entry_type; /* Entry type. */ | |
164 | uint8_t entry_count; /* Entry count. */ | |
165 | uint8_t sys_define; /* System Defined. */ | |
166 | uint8_t entry_status; /* Entry Status. */ | |
167 | ||
1f8deefe SK |
168 | __le32 handle; /* System handle. */ |
169 | __le32 reserved_0; /* System handle. */ | |
8ae6d9c7 | 170 | |
1f8deefe SK |
171 | __le16 func_num; |
172 | __le16 req_xfrcnt; | |
173 | __le16 req_dsdcnt; | |
174 | __le16 rsp_xfrcnt; | |
175 | __le16 rsp_dsdcnt; | |
8ae6d9c7 GM |
176 | uint8_t flags; |
177 | uint8_t reserved_1; | |
178 | ||
1f8deefe SK |
179 | __le32 dseg_rq_address[2]; /* Data segment 0 address. */ |
180 | __le32 dseg_rq_len; /* Data segment 0 length. */ | |
181 | __le32 dseg_rsp_address[2]; /* Data segment 1 address. */ | |
182 | __le32 dseg_rsp_len; /* Data segment 1 length. */ | |
8ae6d9c7 | 183 | |
1f8deefe SK |
184 | __le32 dataword; |
185 | __le32 adapid; | |
186 | __le32 adapid_hi; | |
187 | __le32 dataword_extra; | |
8ae6d9c7 GM |
188 | }; |
189 | ||
190 | struct qlafx00_tgt_node_info { | |
191 | uint8_t tgt_node_wwpn[WWN_SIZE]; | |
192 | uint8_t tgt_node_wwnn[WWN_SIZE]; | |
193 | uint32_t tgt_node_state; | |
194 | uint8_t reserved[128]; | |
195 | uint32_t reserved_1[8]; | |
196 | uint64_t reserved_2[4]; | |
197 | } __packed; | |
198 | ||
199 | #define QLAFX00_TGT_NODE_INFO sizeof(struct qlafx00_tgt_node_info) | |
200 | ||
201 | #define QLAFX00_LINK_STATUS_DOWN 0x10 | |
202 | #define QLAFX00_LINK_STATUS_UP 0x11 | |
203 | ||
204 | #define QLAFX00_PORT_SPEED_2G 0x2 | |
205 | #define QLAFX00_PORT_SPEED_4G 0x4 | |
206 | #define QLAFX00_PORT_SPEED_8G 0x8 | |
207 | #define QLAFX00_PORT_SPEED_10G 0xa | |
208 | struct port_info_data { | |
209 | uint8_t port_state; | |
210 | uint8_t port_type; | |
211 | uint16_t port_identifier; | |
212 | uint32_t up_port_state; | |
213 | uint8_t fw_ver_num[32]; | |
214 | uint8_t portal_attrib; | |
215 | uint16_t host_option; | |
216 | uint8_t reset_delay; | |
217 | uint8_t pdwn_retry_cnt; | |
218 | uint16_t max_luns2tgt; | |
219 | uint8_t risc_ver; | |
220 | uint8_t pconn_option; | |
221 | uint16_t risc_option; | |
222 | uint16_t max_frame_len; | |
223 | uint16_t max_iocb_alloc; | |
224 | uint16_t exec_throttle; | |
225 | uint8_t retry_cnt; | |
226 | uint8_t retry_delay; | |
227 | uint8_t port_name[8]; | |
228 | uint8_t port_id[3]; | |
229 | uint8_t link_status; | |
230 | uint8_t plink_rate; | |
231 | uint32_t link_config; | |
232 | uint16_t adap_haddr; | |
233 | uint8_t tgt_disc; | |
234 | uint8_t log_tout; | |
235 | uint8_t node_name[8]; | |
236 | uint16_t erisc_opt1; | |
237 | uint8_t resp_acc_tmr; | |
238 | uint8_t intr_del_tmr; | |
239 | uint8_t erisc_opt2; | |
240 | uint8_t alt_port_name[8]; | |
241 | uint8_t alt_node_name[8]; | |
242 | uint8_t link_down_tout; | |
243 | uint8_t conn_type; | |
244 | uint8_t fc_fw_mode; | |
245 | uint32_t uiReserved[48]; | |
246 | } __packed; | |
247 | ||
248 | /* OS Type Designations */ | |
249 | #define OS_TYPE_UNKNOWN 0 | |
250 | #define OS_TYPE_LINUX 2 | |
251 | ||
252 | /* Linux Info */ | |
253 | #define SYSNAME_LENGTH 128 | |
254 | #define NODENAME_LENGTH 64 | |
255 | #define RELEASE_LENGTH 64 | |
256 | #define VERSION_LENGTH 64 | |
257 | #define MACHINE_LENGTH 64 | |
258 | #define DOMNAME_LENGTH 64 | |
259 | ||
260 | struct host_system_info { | |
261 | uint32_t os_type; | |
262 | char sysname[SYSNAME_LENGTH]; | |
263 | char nodename[NODENAME_LENGTH]; | |
264 | char release[RELEASE_LENGTH]; | |
265 | char version[VERSION_LENGTH]; | |
266 | char machine[MACHINE_LENGTH]; | |
267 | char domainname[DOMNAME_LENGTH]; | |
268 | char hostdriver[VERSION_LENGTH]; | |
269 | uint32_t reserved[64]; | |
270 | } __packed; | |
271 | ||
272 | struct register_host_info { | |
273 | struct host_system_info hsi; /* host system info */ | |
274 | uint64_t utc; /* UTC (system time) */ | |
275 | uint32_t reserved[64]; /* future additions */ | |
276 | } __packed; | |
277 | ||
278 | ||
279 | #define QLAFX00_PORT_DATA_INFO (sizeof(struct port_info_data)) | |
280 | #define QLAFX00_TGT_NODE_LIST_SIZE (sizeof(uint32_t) * 32) | |
281 | ||
282 | struct config_info_data { | |
03eb912a AB |
283 | uint8_t model_num[16]; |
284 | uint8_t model_description[80]; | |
285 | uint8_t reserved0[160]; | |
8ae6d9c7 GM |
286 | uint8_t symbolic_name[64]; |
287 | uint8_t serial_num[32]; | |
288 | uint8_t hw_version[16]; | |
289 | uint8_t fw_version[16]; | |
290 | uint8_t uboot_version[16]; | |
291 | uint8_t fru_serial_num[32]; | |
292 | ||
293 | uint8_t fc_port_count; | |
294 | uint8_t iscsi_port_count; | |
295 | uint8_t reserved1[2]; | |
296 | ||
297 | uint8_t mode; | |
298 | uint8_t log_level; | |
299 | uint8_t reserved2[2]; | |
300 | ||
301 | uint32_t log_size; | |
302 | ||
303 | uint8_t tgt_pres_mode; | |
304 | uint8_t iqn_flags; | |
305 | uint8_t lun_mapping; | |
306 | ||
307 | uint64_t adapter_id; | |
308 | ||
309 | uint32_t cluster_key_len; | |
71e56003 | 310 | uint8_t cluster_key[16]; |
8ae6d9c7 GM |
311 | |
312 | uint64_t cluster_master_id; | |
313 | uint64_t cluster_slave_id; | |
314 | uint8_t cluster_flags; | |
71e56003 AB |
315 | uint32_t enabled_capabilities; |
316 | uint32_t nominal_temp_value; | |
8ae6d9c7 GM |
317 | } __packed; |
318 | ||
319 | #define FXDISC_GET_CONFIG_INFO 0x01 | |
320 | #define FXDISC_GET_PORT_INFO 0x02 | |
321 | #define FXDISC_GET_TGT_NODE_INFO 0x80 | |
322 | #define FXDISC_GET_TGT_NODE_LIST 0x81 | |
323 | #define FXDISC_REG_HOST_INFO 0x99 | |
767157c5 | 324 | #define FXDISC_ABORT_IOCTL 0xff |
8ae6d9c7 | 325 | |
966460d8 | 326 | #define QLAFX00_HBA_ICNTRL_REG 0x20B08 |
8ae6d9c7 GM |
327 | #define QLAFX00_ICR_ENB_MASK 0x80000000 |
328 | #define QLAFX00_ICR_DIS_MASK 0x7fffffff | |
329 | #define QLAFX00_HST_RST_REG 0x18264 | |
71e56003 | 330 | #define QLAFX00_SOC_TEMP_REG 0x184C4 |
8ae6d9c7 GM |
331 | #define QLAFX00_HST_TO_HBA_REG 0x20A04 |
332 | #define QLAFX00_HBA_TO_HOST_REG 0x21B70 | |
333 | #define QLAFX00_HST_INT_STS_BITS 0x7 | |
334 | #define QLAFX00_BAR1_BASE_ADDR_REG 0x40018 | |
335 | #define QLAFX00_PEX0_WIN0_BASE_ADDR_REG 0x41824 | |
336 | ||
337 | #define QLAFX00_INTR_MB_CMPLT 0x1 | |
338 | #define QLAFX00_INTR_RSP_CMPLT 0x2 | |
8ae6d9c7 | 339 | #define QLAFX00_INTR_ASYNC_CMPLT 0x4 |
8ae6d9c7 GM |
340 | |
341 | #define QLAFX00_MBA_SYSTEM_ERR 0x8002 | |
71e56003 AB |
342 | #define QLAFX00_MBA_TEMP_OVER 0x8005 |
343 | #define QLAFX00_MBA_TEMP_NORM 0x8006 | |
344 | #define QLAFX00_MBA_TEMP_CRIT 0x8007 | |
8ae6d9c7 GM |
345 | #define QLAFX00_MBA_LINK_UP 0x8011 |
346 | #define QLAFX00_MBA_LINK_DOWN 0x8012 | |
347 | #define QLAFX00_MBA_PORT_UPDATE 0x8014 | |
348 | #define QLAFX00_MBA_SHUTDOWN_RQSTD 0x8062 | |
349 | ||
350 | #define SOC_SW_RST_CONTROL_REG_CORE0 0x0020800 | |
351 | #define SOC_FABRIC_RST_CONTROL_REG 0x0020840 | |
352 | #define SOC_FABRIC_CONTROL_REG 0x0020200 | |
353 | #define SOC_FABRIC_CONFIG_REG 0x0020204 | |
42543fb9 | 354 | #define SOC_PWR_MANAGEMENT_PWR_DOWN_REG 0x001820C |
8ae6d9c7 GM |
355 | |
356 | #define SOC_INTERRUPT_SOURCE_I_CONTROL_REG 0x0020B00 | |
357 | #define SOC_CORE_TIMER_REG 0x0021850 | |
358 | #define SOC_IRQ_ACK_REG 0x00218b4 | |
359 | ||
360 | #define CONTINUE_A64_TYPE_FX00 0x03 /* Continuation entry. */ | |
361 | ||
362 | #define QLAFX00_SET_HST_INTR(ha, value) \ | |
363 | WRT_REG_DWORD((ha)->cregbase + QLAFX00_HST_TO_HBA_REG, \ | |
364 | value) | |
365 | ||
366 | #define QLAFX00_CLR_HST_INTR(ha, value) \ | |
367 | WRT_REG_DWORD((ha)->cregbase + QLAFX00_HBA_TO_HOST_REG, \ | |
368 | ~value) | |
369 | ||
370 | #define QLAFX00_RD_INTR_REG(ha) \ | |
371 | RD_REG_DWORD((ha)->cregbase + QLAFX00_HBA_TO_HOST_REG) | |
372 | ||
373 | #define QLAFX00_CLR_INTR_REG(ha, value) \ | |
374 | WRT_REG_DWORD((ha)->cregbase + QLAFX00_HBA_TO_HOST_REG, \ | |
375 | ~value) | |
376 | ||
377 | #define QLAFX00_SET_HBA_SOC_REG(ha, off, val)\ | |
378 | WRT_REG_DWORD((ha)->cregbase + off, val) | |
379 | ||
380 | #define QLAFX00_GET_HBA_SOC_REG(ha, off)\ | |
381 | RD_REG_DWORD((ha)->cregbase + off) | |
382 | ||
383 | #define QLAFX00_HBA_RST_REG(ha, val)\ | |
384 | WRT_REG_DWORD((ha)->cregbase + QLAFX00_HST_RST_REG, val) | |
385 | ||
386 | #define QLAFX00_RD_ICNTRL_REG(ha) \ | |
387 | RD_REG_DWORD((ha)->cregbase + QLAFX00_HBA_ICNTRL_REG) | |
388 | ||
389 | #define QLAFX00_ENABLE_ICNTRL_REG(ha) \ | |
390 | WRT_REG_DWORD((ha)->cregbase + QLAFX00_HBA_ICNTRL_REG, \ | |
391 | (QLAFX00_GET_HBA_SOC_REG(ha, QLAFX00_HBA_ICNTRL_REG) | \ | |
392 | QLAFX00_ICR_ENB_MASK)) | |
393 | ||
394 | #define QLAFX00_DISABLE_ICNTRL_REG(ha) \ | |
395 | WRT_REG_DWORD((ha)->cregbase + QLAFX00_HBA_ICNTRL_REG, \ | |
396 | (QLAFX00_GET_HBA_SOC_REG(ha, QLAFX00_HBA_ICNTRL_REG) & \ | |
397 | QLAFX00_ICR_DIS_MASK)) | |
398 | ||
399 | #define QLAFX00_RD_REG(ha, off) \ | |
400 | RD_REG_DWORD((ha)->cregbase + off) | |
401 | ||
402 | #define QLAFX00_WR_REG(ha, off, val) \ | |
403 | WRT_REG_DWORD((ha)->cregbase + off, val) | |
404 | ||
405 | struct qla_mt_iocb_rqst_fx00 { | |
1f8deefe | 406 | __le32 reserved_0; |
8ae6d9c7 | 407 | |
1f8deefe | 408 | __le16 func_type; |
8ae6d9c7 GM |
409 | uint8_t flags; |
410 | uint8_t reserved_1; | |
411 | ||
1f8deefe | 412 | __le32 dataword; |
8ae6d9c7 | 413 | |
1f8deefe SK |
414 | __le32 adapid; |
415 | __le32 adapid_hi; | |
8ae6d9c7 | 416 | |
1f8deefe | 417 | __le32 dataword_extra; |
8ae6d9c7 | 418 | |
0a77b586 SK |
419 | __le16 req_len; |
420 | __le16 reserved_2; | |
8ae6d9c7 | 421 | |
0a77b586 SK |
422 | __le16 rsp_len; |
423 | __le16 reserved_3; | |
8ae6d9c7 GM |
424 | }; |
425 | ||
426 | struct qla_mt_iocb_rsp_fx00 { | |
427 | uint32_t reserved_1; | |
428 | ||
429 | uint16_t func_type; | |
1f8deefe | 430 | __le16 ioctl_flags; |
8ae6d9c7 | 431 | |
1f8deefe | 432 | __le32 ioctl_data; |
8ae6d9c7 GM |
433 | |
434 | uint32_t adapid; | |
435 | uint32_t adapid_hi; | |
436 | ||
437 | uint32_t reserved_2; | |
1f8deefe | 438 | __le32 seq_number; |
8ae6d9c7 GM |
439 | |
440 | uint8_t reserved_3[20]; | |
441 | ||
442 | int32_t res_count; | |
443 | ||
1f8deefe | 444 | __le32 status; |
8ae6d9c7 GM |
445 | }; |
446 | ||
447 | ||
448 | #define MAILBOX_REGISTER_COUNT_FX00 16 | |
449 | #define AEN_MAILBOX_REGISTER_COUNT_FX00 8 | |
450 | #define MAX_FIBRE_DEVICES_FX00 512 | |
451 | #define MAX_LUNS_FX00 0x1024 | |
452 | #define MAX_TARGETS_FX00 MAX_ISA_DEVICES | |
453 | #define REQUEST_ENTRY_CNT_FX00 512 /* Number of request entries. */ | |
454 | #define RESPONSE_ENTRY_CNT_FX00 256 /* Number of response entries.*/ | |
455 | ||
456 | /* | |
457 | * Firmware state codes for QLAFX00 adapters | |
458 | */ | |
459 | #define FSTATE_FX00_CONFIG_WAIT 0x0000 /* Waiting for driver to issue | |
460 | * Initialize FW Mbox cmd | |
461 | */ | |
462 | #define FSTATE_FX00_INITIALIZED 0x1000 /* FW has been initialized by | |
463 | * the driver | |
464 | */ | |
465 | ||
466 | #define FX00_DEF_RATOV 10 | |
467 | ||
468 | struct mr_data_fx00 { | |
8ae6d9c7 GM |
469 | uint8_t symbolic_name[64]; |
470 | uint8_t serial_num[32]; | |
471 | uint8_t hw_version[16]; | |
472 | uint8_t fw_version[16]; | |
473 | uint8_t uboot_version[16]; | |
474 | uint8_t fru_serial_num[32]; | |
475 | fc_port_t fcport; /* fcport used for requests | |
476 | * that are not linked | |
477 | * to a particular target | |
478 | */ | |
479 | uint8_t fw_hbt_en; | |
480 | uint8_t fw_hbt_cnt; | |
481 | uint8_t fw_hbt_miss_cnt; | |
482 | uint32_t old_fw_hbt_cnt; | |
483 | uint16_t fw_reset_timer_tick; | |
484 | uint8_t fw_reset_timer_exp; | |
71e56003 | 485 | uint16_t fw_critemp_timer_tick; |
8ae6d9c7 | 486 | uint32_t old_aenmbx0_state; |
71e56003 | 487 | uint32_t critical_temperature; |
1fe19ee4 | 488 | bool extended_io_enabled; |
e8f5e95d AB |
489 | bool host_info_resend; |
490 | uint8_t hinfo_resend_timer_tick; | |
8ae6d9c7 GM |
491 | }; |
492 | ||
1fe19ee4 AB |
493 | #define QLAFX00_EXTENDED_IO_EN_MASK 0x20 |
494 | ||
71e56003 AB |
495 | /* |
496 | * SoC Junction Temperature is stored in | |
497 | * bits 9:1 of SoC Junction Temperature Register | |
498 | * in a firmware specific format format. | |
499 | * To get the temperature in Celsius degrees | |
500 | * the value from this bitfiled should be converted | |
501 | * using this formula: | |
502 | * Temperature (degrees C) = ((3,153,000 - (10,000 * X)) / 13,825) | |
503 | * where X is the bit field value | |
504 | * this macro reads the register, extracts the bitfield value, | |
505 | * performs the calcualtions and returns temperature in Celsius | |
506 | */ | |
507 | #define QLAFX00_GET_TEMPERATURE(ha) ((3153000 - (10000 * \ | |
508 | ((QLAFX00_RD_REG(ha, QLAFX00_SOC_TEMP_REG) & 0x3FE) >> 1))) / 13825) | |
509 | ||
510 | ||
8ae6d9c7 GM |
511 | #define QLAFX00_LOOP_DOWN_TIME 615 /* 600 */ |
512 | #define QLAFX00_HEARTBEAT_INTERVAL 6 /* number of seconds */ | |
513 | #define QLAFX00_HEARTBEAT_MISS_CNT 3 /* number of miss */ | |
514 | #define QLAFX00_RESET_INTERVAL 120 /* number of seconds */ | |
515 | #define QLAFX00_MAX_RESET_INTERVAL 600 /* number of seconds */ | |
71e56003 | 516 | #define QLAFX00_CRITEMP_INTERVAL 60 /* number of seconds */ |
e8f5e95d | 517 | #define QLAFX00_HINFO_RESEND_INTERVAL 60 /* number of seconds */ |
f875cd4c AB |
518 | |
519 | #define QLAFX00_CRITEMP_THRSHLD 80 /* Celsius degrees */ | |
520 | ||
a4e04d9a AB |
521 | /* Max conncurrent IOs that can be queued */ |
522 | #define QLAFX00_MAX_CANQUEUE 1024 | |
523 | ||
b593931d AB |
524 | /* IOCTL IOCB abort success */ |
525 | #define QLAFX00_IOCTL_ICOB_ABORT_SUCCESS 0x68 | |
526 | ||
8ae6d9c7 | 527 | #endif |