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Drivers: scsi: remove __dev* attributes.
[deliverable/linux.git] / drivers / scsi / qla2xxx / qla_os.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
46152ceb 3 * Copyright (c) 2003-2012 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
8
9#include <linux/moduleparam.h>
10#include <linux/vmalloc.h>
1da177e4 11#include <linux/delay.h>
39a11240 12#include <linux/kthread.h>
e1e82b6f 13#include <linux/mutex.h>
3420d36c 14#include <linux/kobject.h>
5a0e3ad6 15#include <linux/slab.h>
1da177e4
LT		 16#include <scsi/scsi_tcq.h>
17#include <scsi/scsicam.h>
18#include <scsi/scsi_transport.h>
19#include <scsi/scsi_transport_fc.h>
20
2d70c103
NB		 21#include "qla_target.h"
22
1da177e4
LT		 23/*
24 * Driver version
25 */
26char qla2x00_version_str[40];
27
6a03b4cd
HZ		 28static int apidev_major;
29
1da177e4
LT		 30/*
31 * SRB allocation cache
32 */
e18b890b 33static struct kmem_cache *srb_cachep;
1da177e4 34
a9083016
GM		 35/*
36 * CT6 CTX allocation cache
37 */
38static struct kmem_cache *ctx_cachep;
3ce8866c
SK		 39/*
40 * error level for logging
41 */
42int ql_errlev = ql_log_all;
a9083016 43
fa492630 44static int ql2xenableclass2;
2d70c103
NB		 45module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
46MODULE_PARM_DESC(ql2xenableclass2,
47 "Specify if Class 2 operations are supported from the very "
48 "beginning. Default is 0 - class 2 not supported.");
49
1da177e4 50int ql2xlogintimeout = 20;
f2019cb1 51module_param(ql2xlogintimeout, int, S_IRUGO);
1da177e4
LT		 52MODULE_PARM_DESC(ql2xlogintimeout,
53 "Login timeout value in seconds.");
54
a7b61842 55int qlport_down_retry;
f2019cb1 56module_param(qlport_down_retry, int, S_IRUGO);
1da177e4 57MODULE_PARM_DESC(qlport_down_retry,
900d9f98 58 "Maximum number of command retries to a port that returns "
1da177e4
LT		 59 "a PORT-DOWN status.");
60
1da177e4
LT		 61int ql2xplogiabsentdevice;
62module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
63MODULE_PARM_DESC(ql2xplogiabsentdevice,
64 "Option to enable PLOGI to devices that are not present after "
900d9f98 65 "a Fabric scan. This is needed for several broken switches. "
1da177e4
LT		 66 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
67
1da177e4 68int ql2xloginretrycount = 0;
f2019cb1 69module_param(ql2xloginretrycount, int, S_IRUGO);
1da177e4
LT		 70MODULE_PARM_DESC(ql2xloginretrycount,
71 "Specify an alternate value for the NVRAM login retry count.");
72
a7a167bf 73int ql2xallocfwdump = 1;
f2019cb1 74module_param(ql2xallocfwdump, int, S_IRUGO);
a7a167bf
AV		 75MODULE_PARM_DESC(ql2xallocfwdump,
76 "Option to enable allocation of memory for a firmware dump "
77 "during HBA initialization. Memory allocation requirements "
78 "vary by ISP type. Default is 1 - allocate memory.");
79
11010fec 80int ql2xextended_error_logging;
27d94035 81module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
11010fec 82MODULE_PARM_DESC(ql2xextended_error_logging,
3ce8866c
SK		 83 "Option to enable extended error logging,\n"
84 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
85 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
86 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
87 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
88 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
89 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
90 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
91 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
29f9f90c
CD		 92 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
93 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
3ce8866c 94 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
cfb0919c
CD		 95 "\t\t0x1e400000 - Preferred value for capturing essential "
96 "debug information (equivalent to old "
97 "ql2xextended_error_logging=1).\n"
3ce8866c 98 "\t\tDo LOGICAL OR of the value to enable more than one level");
0181944f 99
a9083016 100int ql2xshiftctondsd = 6;
f2019cb1 101module_param(ql2xshiftctondsd, int, S_IRUGO);
a9083016
GM		 102MODULE_PARM_DESC(ql2xshiftctondsd,
103 "Set to control shifting of command type processing "
104 "based on total number of SG elements.");
105
1da177e4
LT		 106static void qla2x00_free_device(scsi_qla_host_t *);
107
7e47e5ca 108int ql2xfdmienable=1;
f2019cb1 109module_param(ql2xfdmienable, int, S_IRUGO);
cca5335c 110MODULE_PARM_DESC(ql2xfdmienable,
7794a5af
FW		 111 "Enables FDMI registrations. "
112 "0 - no FDMI. Default is 1 - perform FDMI.");
cca5335c 113
df7baa50
AV		 114#define MAX_Q_DEPTH 32
115static int ql2xmaxqdepth = MAX_Q_DEPTH;
116module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
117MODULE_PARM_DESC(ql2xmaxqdepth,
e92e4a8f
CD		 118 "Maximum queue depth to set for each LUN. "
119 "Default is 32.");
df7baa50 120
9e522cd8
AE		 121int ql2xenabledif = 2;
122module_param(ql2xenabledif, int, S_IRUGO);
bad75002
AE		 123MODULE_PARM_DESC(ql2xenabledif,
124 " Enable T10-CRC-DIF "
8cb2049c
AE		 125 " Default is 0 - No DIF Support. 1 - Enable it"
126 ", 2 - Enable DIF for all types, except Type 0.");
bad75002 127
8cb2049c 128int ql2xenablehba_err_chk = 2;
bad75002
AE		 129module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
130MODULE_PARM_DESC(ql2xenablehba_err_chk,
8cb2049c
AE		 131 " Enable T10-CRC-DIF Error isolation by HBA:\n"
132 " Default is 1.\n"
133 " 0 -- Error isolation disabled\n"
134 " 1 -- Error isolation enabled only for DIX Type 0\n"
135 " 2 -- Error isolation enabled for all Types\n");
bad75002 136
e5896bd5 137int ql2xiidmaenable=1;
f2019cb1 138module_param(ql2xiidmaenable, int, S_IRUGO);
e5896bd5
AV		 139MODULE_PARM_DESC(ql2xiidmaenable,
140 "Enables iIDMA settings "
141 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
142
73208dfd 143int ql2xmaxqueues = 1;
f2019cb1 144module_param(ql2xmaxqueues, int, S_IRUGO);
73208dfd
AC		 145MODULE_PARM_DESC(ql2xmaxqueues,
146 "Enables MQ settings "
ae68230c
JP		 147 "Default is 1 for single queue. Set it to number "
148 "of queues in MQ mode.");
68ca949c
AC		 149
150int ql2xmultique_tag;
f2019cb1 151module_param(ql2xmultique_tag, int, S_IRUGO);
68ca949c
AC		 152MODULE_PARM_DESC(ql2xmultique_tag,
153 "Enables CPU affinity settings for the driver "
154 "Default is 0 for no affinity of request and response IO. "
155 "Set it to 1 to turn on the cpu affinity.");
e337d907
AV		 156
157int ql2xfwloadbin;
86e45bf6 158module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
e337d907 159MODULE_PARM_DESC(ql2xfwloadbin,
7c3df132
SK		 160 "Option to specify location from which to load ISP firmware:.\n"
161 " 2 -- load firmware via the request_firmware() (hotplug).\n"
e337d907
AV		 162 " interface.\n"
163 " 1 -- load firmware from flash.\n"
164 " 0 -- use default semantics.\n");
165
ae97c91e 166int ql2xetsenable;
f2019cb1 167module_param(ql2xetsenable, int, S_IRUGO);
ae97c91e
AV		 168MODULE_PARM_DESC(ql2xetsenable,
169 "Enables firmware ETS burst."
170 "Default is 0 - skip ETS enablement.");
171
6907869d 172int ql2xdbwr = 1;
86e45bf6 173module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
a9083016 174MODULE_PARM_DESC(ql2xdbwr,
08de2844
GM		 175 "Option to specify scheme for request queue posting.\n"
176 " 0 -- Regular doorbell.\n"
177 " 1 -- CAMRAM doorbell (faster).\n");
a9083016 178
f4c496c1 179int ql2xtargetreset = 1;
f2019cb1 180module_param(ql2xtargetreset, int, S_IRUGO);
f4c496c1
GM		 181MODULE_PARM_DESC(ql2xtargetreset,
182 "Enable target reset."
183 "Default is 1 - use hw defaults.");
184
4da26e16 185int ql2xgffidenable;
f2019cb1 186module_param(ql2xgffidenable, int, S_IRUGO);
4da26e16
CD		 187MODULE_PARM_DESC(ql2xgffidenable,
188 "Enables GFF_ID checks of port type. "
189 "Default is 0 - Do not use GFF_ID information.");
a9083016 190
3822263e 191int ql2xasynctmfenable;
f2019cb1 192module_param(ql2xasynctmfenable, int, S_IRUGO);
3822263e
MI		 193MODULE_PARM_DESC(ql2xasynctmfenable,
194 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
195 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
ed0de87c
GM		 196
197int ql2xdontresethba;
86e45bf6 198module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
ed0de87c 199MODULE_PARM_DESC(ql2xdontresethba,
08de2844
GM		 200 "Option to specify reset behaviour.\n"
201 " 0 (Default) -- Reset on failure.\n"
202 " 1 -- Do not reset on failure.\n");
ed0de87c 203
82515920
AV		 204uint ql2xmaxlun = MAX_LUNS;
205module_param(ql2xmaxlun, uint, S_IRUGO);
206MODULE_PARM_DESC(ql2xmaxlun,
207 "Defines the maximum LU number to register with the SCSI "
208 "midlayer. Default is 65535.");
209
08de2844
GM		 210int ql2xmdcapmask = 0x1F;
211module_param(ql2xmdcapmask, int, S_IRUGO);
212MODULE_PARM_DESC(ql2xmdcapmask,
213 "Set the Minidump driver capture mask level. "
6e96fa7b 214 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
08de2844 215
3aadff35 216int ql2xmdenable = 1;
08de2844
GM		 217module_param(ql2xmdenable, int, S_IRUGO);
218MODULE_PARM_DESC(ql2xmdenable,
219 "Enable/disable MiniDump. "
3aadff35
GM		 220 "0 - MiniDump disabled. "
221 "1 (Default) - MiniDump enabled.");
08de2844 222
1da177e4 223/*
fa2a1ce5 224 * SCSI host template entry points
1da177e4
LT		 225 */
226static int qla2xxx_slave_configure(struct scsi_device * device);
f4f051eb 227static int qla2xxx_slave_alloc(struct scsi_device *);
1e99e33a
AV		 228static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
229static void qla2xxx_scan_start(struct Scsi_Host *);
f4f051eb 230static void qla2xxx_slave_destroy(struct scsi_device *);
f281233d 231static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
1da177e4
LT		 232static int qla2xxx_eh_abort(struct scsi_cmnd *);
233static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
523ec773 234static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
1da177e4
LT		 235static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
236static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
1da177e4 237
e881a172 238static int qla2x00_change_queue_depth(struct scsi_device *, int, int);
ce7e4af7
AV		 239static int qla2x00_change_queue_type(struct scsi_device *, int);
240
a5326f86 241struct scsi_host_template qla2xxx_driver_template = {
1da177e4 242 .module = THIS_MODULE,
cb63067a 243 .name = QLA2XXX_DRIVER_NAME,
a5326f86 244 .queuecommand = qla2xxx_queuecommand,
fca29703
AV		 245
246 .eh_abort_handler = qla2xxx_eh_abort,
247 .eh_device_reset_handler = qla2xxx_eh_device_reset,
523ec773 248 .eh_target_reset_handler = qla2xxx_eh_target_reset,
fca29703
AV		 249 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
250 .eh_host_reset_handler = qla2xxx_eh_host_reset,
251
252 .slave_configure = qla2xxx_slave_configure,
253
254 .slave_alloc = qla2xxx_slave_alloc,
255 .slave_destroy = qla2xxx_slave_destroy,
ed677086
AV		 256 .scan_finished = qla2xxx_scan_finished,
257 .scan_start = qla2xxx_scan_start,
ce7e4af7
AV		 258 .change_queue_depth = qla2x00_change_queue_depth,
259 .change_queue_type = qla2x00_change_queue_type,
fca29703
AV		 260 .this_id = -1,
261 .cmd_per_lun = 3,
262 .use_clustering = ENABLE_CLUSTERING,
263 .sg_tablesize = SG_ALL,
264
265 .max_sectors = 0xFFFF,
afb046e2 266 .shost_attrs = qla2x00_host_attrs,
2d70c103
NB		 267
268 .supported_mode = MODE_INITIATOR,
fca29703
AV		 269};
270
1da177e4 271static struct scsi_transport_template *qla2xxx_transport_template = NULL;
2c3dfe3f 272struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
1da177e4 273
1da177e4
LT		 274/* TODO Convert to inlines
275 *
276 * Timer routines
277 */
1da177e4 278
2c3dfe3f 279__inline__ void
e315cd28 280qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
1da177e4 281{
e315cd28
AC		 282 init_timer(&vha->timer);
283 vha->timer.expires = jiffies + interval * HZ;
284 vha->timer.data = (unsigned long)vha;
285 vha->timer.function = (void (*)(unsigned long))func;
286 add_timer(&vha->timer);
287 vha->timer_active = 1;
1da177e4
LT		 288}
289
290static inline void
e315cd28 291qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 292{
a9083016 293 /* Currently used for 82XX only. */
7c3df132
SK		 294 if (vha->device_flags & DFLG_DEV_FAILED) {
295 ql_dbg(ql_dbg_timer, vha, 0x600d,
296 "Device in a failed state, returning.\n");
a9083016 297 return;
7c3df132 298 }
a9083016 299
e315cd28 300 mod_timer(&vha->timer, jiffies + interval * HZ);
1da177e4
LT		 301}
302
a824ebb3 303static __inline__ void
e315cd28 304qla2x00_stop_timer(scsi_qla_host_t *vha)
1da177e4 305{
e315cd28
AC		 306 del_timer_sync(&vha->timer);
307 vha->timer_active = 0;
1da177e4
LT		 308}
309
1da177e4
LT		 310static int qla2x00_do_dpc(void *data);
311
312static void qla2x00_rst_aen(scsi_qla_host_t *);
313
73208dfd
AC		 314static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
315 struct req_que **, struct rsp_que **);
e30d1756 316static void qla2x00_free_fw_dump(struct qla_hw_data *);
e315cd28 317static void qla2x00_mem_free(struct qla_hw_data *);
1da177e4 318
1da177e4 319/* -------------------------------------------------------------------------- */
9a347ff4
CD		 320static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
321 struct rsp_que *rsp)
73208dfd 322{
7c3df132 323 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2afa19a9 324 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
73208dfd
AC		 325 GFP_KERNEL);
326 if (!ha->req_q_map) {
7c3df132
SK		 327 ql_log(ql_log_fatal, vha, 0x003b,
328 "Unable to allocate memory for request queue ptrs.\n");
73208dfd
AC		 329 goto fail_req_map;
330 }
331
2afa19a9 332 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
73208dfd
AC		 333 GFP_KERNEL);
334 if (!ha->rsp_q_map) {
7c3df132
SK		 335 ql_log(ql_log_fatal, vha, 0x003c,
336 "Unable to allocate memory for response queue ptrs.\n");
73208dfd
AC		 337 goto fail_rsp_map;
338 }
9a347ff4
CD		 339 /*
340 * Make sure we record at least the request and response queue zero in
341 * case we need to free them if part of the probe fails.
342 */
343 ha->rsp_q_map[0] = rsp;
344 ha->req_q_map[0] = req;
73208dfd
AC		 345 set_bit(0, ha->rsp_qid_map);
346 set_bit(0, ha->req_qid_map);
347 return 1;
348
349fail_rsp_map:
350 kfree(ha->req_q_map);
351 ha->req_q_map = NULL;
352fail_req_map:
353 return -ENOMEM;
354}
355
2afa19a9 356static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
73208dfd 357{
73208dfd
AC		 358 if (req && req->ring)
359 dma_free_coherent(&ha->pdev->dev,
360 (req->length + 1) * sizeof(request_t),
361 req->ring, req->dma);
362
363 kfree(req);
364 req = NULL;
365}
366
2afa19a9
AC		 367static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
368{
369 if (rsp && rsp->ring)
370 dma_free_coherent(&ha->pdev->dev,
371 (rsp->length + 1) * sizeof(response_t),
372 rsp->ring, rsp->dma);
373
374 kfree(rsp);
375 rsp = NULL;
376}
377
73208dfd
AC		 378static void qla2x00_free_queues(struct qla_hw_data *ha)
379{
380 struct req_que *req;
381 struct rsp_que *rsp;
382 int cnt;
383
2afa19a9 384 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
73208dfd 385 req = ha->req_q_map[cnt];
2afa19a9 386 qla2x00_free_req_que(ha, req);
73208dfd 387 }
73208dfd
AC		 388 kfree(ha->req_q_map);
389 ha->req_q_map = NULL;
2afa19a9
AC		 390
391 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
392 rsp = ha->rsp_q_map[cnt];
393 qla2x00_free_rsp_que(ha, rsp);
394 }
395 kfree(ha->rsp_q_map);
396 ha->rsp_q_map = NULL;
73208dfd
AC		 397}
398
68ca949c
AC		 399static int qla25xx_setup_mode(struct scsi_qla_host *vha)
400{
401 uint16_t options = 0;
402 int ques, req, ret;
403 struct qla_hw_data *ha = vha->hw;
404
7163ea81 405 if (!(ha->fw_attributes & BIT_6)) {
7c3df132
SK		 406 ql_log(ql_log_warn, vha, 0x00d8,
407 "Firmware is not multi-queue capable.\n");
7163ea81
AC		 408 goto fail;
409 }
68ca949c 410 if (ql2xmultique_tag) {
68ca949c
AC		 411 /* create a request queue for IO */
412 options |= BIT_7;
413 req = qla25xx_create_req_que(ha, options, 0, 0, -1,
414 QLA_DEFAULT_QUE_QOS);
415 if (!req) {
7c3df132
SK		 416 ql_log(ql_log_warn, vha, 0x00e0,
417 "Failed to create request queue.\n");
68ca949c
AC		 418 goto fail;
419 }
278274d5 420 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1);
68ca949c
AC		 421 vha->req = ha->req_q_map[req];
422 options |= BIT_1;
423 for (ques = 1; ques < ha->max_rsp_queues; ques++) {
424 ret = qla25xx_create_rsp_que(ha, options, 0, 0, req);
425 if (!ret) {
7c3df132
SK		 426 ql_log(ql_log_warn, vha, 0x00e8,
427 "Failed to create response queue.\n");
68ca949c
AC		 428 goto fail2;
429 }
430 }
7163ea81 431 ha->flags.cpu_affinity_enabled = 1;
7c3df132
SK		 432 ql_dbg(ql_dbg_multiq, vha, 0xc007,
433 "CPU affinity mode enalbed, "
434 "no. of response queues:%d no. of request queues:%d.\n",
435 ha->max_rsp_queues, ha->max_req_queues);
436 ql_dbg(ql_dbg_init, vha, 0x00e9,
437 "CPU affinity mode enalbed, "
438 "no. of response queues:%d no. of request queues:%d.\n",
439 ha->max_rsp_queues, ha->max_req_queues);
68ca949c
AC		 440 }
441 return 0;
442fail2:
443 qla25xx_delete_queues(vha);
7163ea81
AC		 444 destroy_workqueue(ha->wq);
445 ha->wq = NULL;
0cd33fcf 446 vha->req = ha->req_q_map[0];
68ca949c
AC		 447fail:
448 ha->mqenable = 0;
7163ea81
AC		 449 kfree(ha->req_q_map);
450 kfree(ha->rsp_q_map);
451 ha->max_req_queues = ha->max_rsp_queues = 1;
68ca949c
AC		 452 return 1;
453}
454
1da177e4 455static char *
e315cd28 456qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
1da177e4 457{
e315cd28 458 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 459 static char *pci_bus_modes[] = {
460 "33", "66", "100", "133",
461 };
462 uint16_t pci_bus;
463
464 strcpy(str, "PCI");
465 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
466 if (pci_bus) {
467 strcat(str, "-X (");
468 strcat(str, pci_bus_modes[pci_bus]);
469 } else {
470 pci_bus = (ha->pci_attr & BIT_8) >> 8;
471 strcat(str, " (");
472 strcat(str, pci_bus_modes[pci_bus]);
473 }
474 strcat(str, " MHz)");
475
476 return (str);
477}
478
fca29703 479static char *
e315cd28 480qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
fca29703
AV		 481{
482 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
e315cd28 483 struct qla_hw_data *ha = vha->hw;
fca29703
AV		 484 uint32_t pci_bus;
485 int pcie_reg;
486
e67f1321 487 pcie_reg = pci_pcie_cap(ha->pdev);
fca29703
AV		 488 if (pcie_reg) {
489 char lwstr[6];
490 uint16_t pcie_lstat, lspeed, lwidth;
491
e67f1321 492 pcie_reg += PCI_EXP_LNKCAP;
fca29703
AV		 493 pci_read_config_word(ha->pdev, pcie_reg, &pcie_lstat);
494 lspeed = pcie_lstat & (BIT_0 | BIT_1 | BIT_2 | BIT_3);
495 lwidth = (pcie_lstat &
496 (BIT_4 | BIT_5 | BIT_6 | BIT_7 | BIT_8 | BIT_9)) >> 4;
497
498 strcpy(str, "PCIe (");
49300af7
SK		 499 switch (lspeed) {
500 case 1:
c87a0d8c 501 strcat(str, "2.5GT/s ");
49300af7
SK		 502 break;
503 case 2:
c87a0d8c 504 strcat(str, "5.0GT/s ");
49300af7
SK		 505 break;
506 case 3:
507 strcat(str, "8.0GT/s ");
508 break;
509 default:
fca29703 510 strcat(str, "<unknown> ");
49300af7
SK		 511 break;
512 }
fca29703
AV		 513 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
514 strcat(str, lwstr);
515
516 return str;
517 }
518
519 strcpy(str, "PCI");
520 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
521 if (pci_bus == 0 || pci_bus == 8) {
522 strcat(str, " (");
523 strcat(str, pci_bus_modes[pci_bus >> 3]);
524 } else {
525 strcat(str, "-X ");
526 if (pci_bus & BIT_2)
527 strcat(str, "Mode 2");
528 else
529 strcat(str, "Mode 1");
530 strcat(str, " (");
531 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
532 }
533 strcat(str, " MHz)");
534
535 return str;
536}
537
e5f82ab8 538static char *
e315cd28 539qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str)
1da177e4
LT		 540{
541 char un_str[10];
e315cd28 542 struct qla_hw_data *ha = vha->hw;
fa2a1ce5 543
1da177e4
LT		 544 sprintf(str, "%d.%02d.%02d ", ha->fw_major_version,
545 ha->fw_minor_version,
546 ha->fw_subminor_version);
547
548 if (ha->fw_attributes & BIT_9) {
549 strcat(str, "FLX");
550 return (str);
551 }
552
553 switch (ha->fw_attributes & 0xFF) {
554 case 0x7:
555 strcat(str, "EF");
556 break;
557 case 0x17:
558 strcat(str, "TP");
559 break;
560 case 0x37:
561 strcat(str, "IP");
562 break;
563 case 0x77:
564 strcat(str, "VI");
565 break;
566 default:
567 sprintf(un_str, "(%x)", ha->fw_attributes);
568 strcat(str, un_str);
569 break;
570 }
571 if (ha->fw_attributes & 0x100)
572 strcat(str, "X");
573
574 return (str);
575}
576
e5f82ab8 577static char *
e315cd28 578qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str)
fca29703 579{
e315cd28 580 struct qla_hw_data *ha = vha->hw;
f0883ac6 581
3a03eb79
AV		 582 sprintf(str, "%d.%02d.%02d (%x)", ha->fw_major_version,
583 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
fca29703 584 return str;
fca29703
AV		 585}
586
9ba56b95
GM		 587void
588qla2x00_sp_free_dma(void *vha, void *ptr)
fca29703 589{
9ba56b95
GM		 590 srb_t *sp = (srb_t *)ptr;
591 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
592 struct qla_hw_data *ha = sp->fcport->vha->hw;
593 void *ctx = GET_CMD_CTX_SP(sp);
fca29703 594
9ba56b95
GM		 595 if (sp->flags & SRB_DMA_VALID) {
596 scsi_dma_unmap(cmd);
597 sp->flags &= ~SRB_DMA_VALID;
7c3df132 598 }
fca29703 599
9ba56b95
GM		 600 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
601 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
602 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
603 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
604 }
605
606 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
607 /* List assured to be having elements */
608 qla2x00_clean_dsd_pool(ha, sp);
609 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
610 }
611
612 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
613 dma_pool_free(ha->dl_dma_pool, ctx,
614 ((struct crc_context *)ctx)->crc_ctx_dma);
615 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
616 }
617
618 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
619 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx;
fca29703 620
9ba56b95
GM		 621 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
622 ctx1->fcp_cmnd_dma);
623 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
624 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
625 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
626 mempool_free(ctx1, ha->ctx_mempool);
627 ctx1 = NULL;
628 }
629
630 CMD_SP(cmd) = NULL;
631 mempool_free(sp, ha->srb_mempool);
632}
633
634static void
635qla2x00_sp_compl(void *data, void *ptr, int res)
636{
637 struct qla_hw_data *ha = (struct qla_hw_data *)data;
638 srb_t *sp = (srb_t *)ptr;
639 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
640
641 cmd->result = res;
642
643 if (atomic_read(&sp->ref_count) == 0) {
644 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015,
645 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
646 sp, GET_CMD_SP(sp));
647 if (ql2xextended_error_logging & ql_dbg_io)
648 BUG();
649 return;
650 }
651 if (!atomic_dec_and_test(&sp->ref_count))
652 return;
653
654 qla2x00_sp_free_dma(ha, sp);
655 cmd->scsi_done(cmd);
fca29703
AV		 656}
657
1da177e4 658static int
f5e3e40b 659qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
fca29703 660{
134ae078 661 scsi_qla_host_t *vha = shost_priv(host);
fca29703 662 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
19a7b4ae 663 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
e315cd28
AC		 664 struct qla_hw_data *ha = vha->hw;
665 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
fca29703
AV		 666 srb_t *sp;
667 int rval;
668
85880801 669 if (ha->flags.eeh_busy) {
7c3df132 670 if (ha->flags.pci_channel_io_perm_failure) {
5f28d2d7 671 ql_dbg(ql_dbg_aer, vha, 0x9010,
7c3df132
SK		 672 "PCI Channel IO permanent failure, exiting "
673 "cmd=%p.\n", cmd);
b9b12f73 674 cmd->result = DID_NO_CONNECT << 16;
7c3df132 675 } else {
5f28d2d7 676 ql_dbg(ql_dbg_aer, vha, 0x9011,
7c3df132 677 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
85880801 678 cmd->result = DID_REQUEUE << 16;
7c3df132 679 }
14e660e6
SJ		 680 goto qc24_fail_command;
681 }
682
19a7b4ae
JSEC		 683 rval = fc_remote_port_chkready(rport);
684 if (rval) {
685 cmd->result = rval;
5f28d2d7 686 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
7c3df132
SK		 687 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
688 cmd, rval);
fca29703
AV		 689 goto qc24_fail_command;
690 }
691
bad75002
AE		 692 if (!vha->flags.difdix_supported &&
693 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
7c3df132
SK		 694 ql_dbg(ql_dbg_io, vha, 0x3004,
695 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
696 cmd);
bad75002
AE		 697 cmd->result = DID_NO_CONNECT << 16;
698 goto qc24_fail_command;
699 }
aa651be8
CD		 700
701 if (!fcport) {
702 cmd->result = DID_NO_CONNECT << 16;
703 goto qc24_fail_command;
704 }
705
fca29703
AV		 706 if (atomic_read(&fcport->state) != FCS_ONLINE) {
707 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
38170fa8 708 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
7c3df132
SK		 709 ql_dbg(ql_dbg_io, vha, 0x3005,
710 "Returning DNC, fcport_state=%d loop_state=%d.\n",
711 atomic_read(&fcport->state),
712 atomic_read(&base_vha->loop_state));
fca29703
AV		 713 cmd->result = DID_NO_CONNECT << 16;
714 goto qc24_fail_command;
715 }
7b594131 716 goto qc24_target_busy;
fca29703
AV		 717 }
718
9ba56b95 719 sp = qla2x00_get_sp(base_vha, fcport, GFP_ATOMIC);
fca29703 720 if (!sp)
f5e3e40b 721 goto qc24_host_busy;
fca29703 722
9ba56b95
GM		 723 sp->u.scmd.cmd = cmd;
724 sp->type = SRB_SCSI_CMD;
725 atomic_set(&sp->ref_count, 1);
726 CMD_SP(cmd) = (void *)sp;
727 sp->free = qla2x00_sp_free_dma;
728 sp->done = qla2x00_sp_compl;
729
e315cd28 730 rval = ha->isp_ops->start_scsi(sp);
7c3df132 731 if (rval != QLA_SUCCESS) {
53016ed3 732 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
7c3df132 733 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
fca29703 734 goto qc24_host_busy_free_sp;
7c3df132 735 }
fca29703 736
fca29703
AV		 737 return 0;
738
739qc24_host_busy_free_sp:
9ba56b95 740 qla2x00_sp_free_dma(ha, sp);
fca29703 741
f5e3e40b 742qc24_host_busy:
fca29703
AV		 743 return SCSI_MLQUEUE_HOST_BUSY;
744
7b594131
MC		 745qc24_target_busy:
746 return SCSI_MLQUEUE_TARGET_BUSY;
747
fca29703 748qc24_fail_command:
f5e3e40b 749 cmd->scsi_done(cmd);
fca29703
AV		 750
751 return 0;
752}
753
1da177e4
LT		 754/*
755 * qla2x00_eh_wait_on_command
756 * Waits for the command to be returned by the Firmware for some
757 * max time.
758 *
759 * Input:
1da177e4 760 * cmd = Scsi Command to wait on.
1da177e4
LT		 761 *
762 * Return:
763 * Not Found : 0
764 * Found : 1
765 */
766static int
e315cd28 767qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1da177e4 768{
fe74c71f
AV		 769#define ABORT_POLLING_PERIOD 1000
770#define ABORT_WAIT_ITER ((10 * 1000) / (ABORT_POLLING_PERIOD))
f4f051eb 771 unsigned long wait_iter = ABORT_WAIT_ITER;
85880801
AV		 772 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
773 struct qla_hw_data *ha = vha->hw;
f4f051eb 774 int ret = QLA_SUCCESS;
1da177e4 775
85880801 776 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
7c3df132
SK		 777 ql_dbg(ql_dbg_taskm, vha, 0x8005,
778 "Return:eh_wait.\n");
85880801
AV		 779 return ret;
780 }
781
d970432c 782 while (CMD_SP(cmd) && wait_iter--) {
fe74c71f 783 msleep(ABORT_POLLING_PERIOD);
f4f051eb 784 }
785 if (CMD_SP(cmd))
786 ret = QLA_FUNCTION_FAILED;
1da177e4 787
f4f051eb 788 return ret;
1da177e4
LT		 789}
790
791/*
792 * qla2x00_wait_for_hba_online
fa2a1ce5 793 * Wait till the HBA is online after going through
1da177e4
LT		 794 * <= MAX_RETRIES_OF_ISP_ABORT or
795 * finally HBA is disabled ie marked offline
796 *
797 * Input:
798 * ha - pointer to host adapter structure
fa2a1ce5
AV		 799 *
800 * Note:
1da177e4
LT		 801 * Does context switching-Release SPIN_LOCK
802 * (if any) before calling this routine.
803 *
804 * Return:
805 * Success (Adapter is online) : 0
806 * Failed (Adapter is offline/disabled) : 1
807 */
854165f4 808int
e315cd28 809qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1da177e4 810{
fca29703
AV		 811 int return_status;
812 unsigned long wait_online;
e315cd28
AC		 813 struct qla_hw_data *ha = vha->hw;
814 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 815
fa2a1ce5 816 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
e315cd28
AC		 817 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
818 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
819 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
820 ha->dpc_active) && time_before(jiffies, wait_online)) {
1da177e4
LT		 821
822 msleep(1000);
823 }
e315cd28 824 if (base_vha->flags.online)
fa2a1ce5 825 return_status = QLA_SUCCESS;
1da177e4
LT		 826 else
827 return_status = QLA_FUNCTION_FAILED;
828
1da177e4
LT		 829 return (return_status);
830}
831
86fbee86
LC		 832/*
833 * qla2x00_wait_for_reset_ready
834 * Wait till the HBA is online after going through
835 * <= MAX_RETRIES_OF_ISP_ABORT or
836 * finally HBA is disabled ie marked offline or flash
837 * operations are in progress.
838 *
839 * Input:
840 * ha - pointer to host adapter structure
841 *
842 * Note:
843 * Does context switching-Release SPIN_LOCK
844 * (if any) before calling this routine.
845 *
846 * Return:
847 * Success (Adapter is online/no flash ops) : 0
848 * Failed (Adapter is offline/disabled/flash ops in progress) : 1
849 */
3dbe756a 850static int
86fbee86
LC		 851qla2x00_wait_for_reset_ready(scsi_qla_host_t *vha)
852{
853 int return_status;
854 unsigned long wait_online;
855 struct qla_hw_data *ha = vha->hw;
856 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
857
858 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
859 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
860 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
861 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
862 ha->optrom_state != QLA_SWAITING ||
863 ha->dpc_active) && time_before(jiffies, wait_online))
864 msleep(1000);
865
866 if (base_vha->flags.online && ha->optrom_state == QLA_SWAITING)
867 return_status = QLA_SUCCESS;
868 else
869 return_status = QLA_FUNCTION_FAILED;
870
7c3df132
SK		 871 ql_dbg(ql_dbg_taskm, vha, 0x8019,
872 "%s return status=%d.\n", __func__, return_status);
86fbee86
LC		 873
874 return return_status;
875}
876
2533cf67
LC		 877int
878qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
879{
880 int return_status;
881 unsigned long wait_reset;
882 struct qla_hw_data *ha = vha->hw;
883 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
884
885 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
886 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
887 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
888 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
889 ha->dpc_active) && time_before(jiffies, wait_reset)) {
890
891 msleep(1000);
892
893 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
894 ha->flags.chip_reset_done)
895 break;
896 }
897 if (ha->flags.chip_reset_done)
898 return_status = QLA_SUCCESS;
899 else
900 return_status = QLA_FUNCTION_FAILED;
901
902 return return_status;
903}
904
083a469d
GM		 905static void
906sp_get(struct srb *sp)
907{
908 atomic_inc(&sp->ref_count);
909}
910
1da177e4
LT		 911/**************************************************************************
912* qla2xxx_eh_abort
913*
914* Description:
915* The abort function will abort the specified command.
916*
917* Input:
918* cmd = Linux SCSI command packet to be aborted.
919*
920* Returns:
921* Either SUCCESS or FAILED.
922*
923* Note:
2ea00202 924* Only return FAILED if command not returned by firmware.
1da177e4 925**************************************************************************/
e5f82ab8 926static int
1da177e4
LT		 927qla2xxx_eh_abort(struct scsi_cmnd *cmd)
928{
e315cd28 929 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
f4f051eb 930 srb_t *sp;
4e98d3b8 931 int ret;
f4f051eb 932 unsigned int id, lun;
18e144d3 933 unsigned long flags;
2ea00202 934 int wait = 0;
e315cd28 935 struct qla_hw_data *ha = vha->hw;
1da177e4 936
f4f051eb 937 if (!CMD_SP(cmd))
2ea00202 938 return SUCCESS;
1da177e4 939
4e98d3b8
AV		 940 ret = fc_block_scsi_eh(cmd);
941 if (ret != 0)
942 return ret;
943 ret = SUCCESS;
944
f4f051eb 945 id = cmd->device->id;
946 lun = cmd->device->lun;
1da177e4 947
e315cd28 948 spin_lock_irqsave(&ha->hardware_lock, flags);
170babc3
MC		 949 sp = (srb_t *) CMD_SP(cmd);
950 if (!sp) {
951 spin_unlock_irqrestore(&ha->hardware_lock, flags);
952 return SUCCESS;
953 }
1da177e4 954
7c3df132 955 ql_dbg(ql_dbg_taskm, vha, 0x8002,
cfb0919c
CD		 956 "Aborting from RISC nexus=%ld:%d:%d sp=%p cmd=%p\n",
957 vha->host_no, id, lun, sp, cmd);
17d98630 958
170babc3
MC		 959 /* Get a reference to the sp and drop the lock.*/
960 sp_get(sp);
083a469d 961
e315cd28 962 spin_unlock_irqrestore(&ha->hardware_lock, flags);
170babc3 963 if (ha->isp_ops->abort_command(sp)) {
a55aac79 964 ret = FAILED;
7c3df132 965 ql_dbg(ql_dbg_taskm, vha, 0x8003,
cfb0919c 966 "Abort command mbx failed cmd=%p.\n", cmd);
170babc3 967 } else {
7c3df132 968 ql_dbg(ql_dbg_taskm, vha, 0x8004,
cfb0919c 969 "Abort command mbx success cmd=%p.\n", cmd);
170babc3
MC		 970 wait = 1;
971 }
75942064
SK		 972
973 spin_lock_irqsave(&ha->hardware_lock, flags);
9ba56b95 974 sp->done(ha, sp, 0);
75942064 975 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4 976
bc91ade9
CD		 977 /* Did the command return during mailbox execution? */
978 if (ret == FAILED && !CMD_SP(cmd))
979 ret = SUCCESS;
980
f4f051eb 981 /* Wait for the command to be returned. */
2ea00202 982 if (wait) {
e315cd28 983 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
7c3df132 984 ql_log(ql_log_warn, vha, 0x8006,
cfb0919c 985 "Abort handler timed out cmd=%p.\n", cmd);
2ea00202 986 ret = FAILED;
f4f051eb 987 }
1da177e4 988 }
1da177e4 989
7c3df132 990 ql_log(ql_log_info, vha, 0x801c,
cfb0919c
CD		 991 "Abort command issued nexus=%ld:%d:%d -- %d %x.\n",
992 vha->host_no, id, lun, wait, ret);
1da177e4 993
f4f051eb 994 return ret;
995}
1da177e4 996
4d78c973 997int
e315cd28 998qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
4d78c973 999 unsigned int l, enum nexus_wait_type type)
f4f051eb 1000{
17d98630 1001 int cnt, match, status;
18e144d3 1002 unsigned long flags;
e315cd28 1003 struct qla_hw_data *ha = vha->hw;
73208dfd 1004 struct req_que *req;
4d78c973 1005 srb_t *sp;
9ba56b95 1006 struct scsi_cmnd *cmd;
1da177e4 1007
523ec773 1008 status = QLA_SUCCESS;
17d98630 1009
e315cd28 1010 spin_lock_irqsave(&ha->hardware_lock, flags);
67c2e93a 1011 req = vha->req;
17d98630
AC		 1012 for (cnt = 1; status == QLA_SUCCESS &&
1013 cnt < MAX_OUTSTANDING_COMMANDS; cnt++) {
1014 sp = req->outstanding_cmds[cnt];
1015 if (!sp)
523ec773 1016 continue;
9ba56b95 1017 if (sp->type != SRB_SCSI_CMD)
cf53b069 1018 continue;
17d98630
AC		 1019 if (vha->vp_idx != sp->fcport->vha->vp_idx)
1020 continue;
1021 match = 0;
9ba56b95 1022 cmd = GET_CMD_SP(sp);
17d98630
AC		 1023 switch (type) {
1024 case WAIT_HOST:
1025 match = 1;
1026 break;
1027 case WAIT_TARGET:
9ba56b95 1028 match = cmd->device->id == t;
17d98630
AC		 1029 break;
1030 case WAIT_LUN:
9ba56b95
GM		 1031 match = (cmd->device->id == t &&
1032 cmd->device->lun == l);
17d98630 1033 break;
73208dfd 1034 }
17d98630
AC		 1035 if (!match)
1036 continue;
1037
1038 spin_unlock_irqrestore(&ha->hardware_lock, flags);
9ba56b95 1039 status = qla2x00_eh_wait_on_command(cmd);
17d98630 1040 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 1041 }
e315cd28 1042 spin_unlock_irqrestore(&ha->hardware_lock, flags);
523ec773
AV		 1043
1044 return status;
1da177e4
LT		 1045}
1046
523ec773
AV		 1047static char *reset_errors[] = {
1048 "HBA not online",
1049 "HBA not ready",
1050 "Task management failed",
1051 "Waiting for command completions",
1052};
1da177e4 1053
e5f82ab8 1054static int
523ec773 1055__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
2afa19a9 1056 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, unsigned int, int))
1da177e4 1057{
e315cd28 1058 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1059 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
523ec773 1060 int err;
1da177e4 1061
7c3df132 1062 if (!fcport) {
523ec773 1063 return FAILED;
7c3df132 1064 }
1da177e4 1065
4e98d3b8
AV		 1066 err = fc_block_scsi_eh(cmd);
1067 if (err != 0)
1068 return err;
1069
7c3df132 1070 ql_log(ql_log_info, vha, 0x8009,
cfb0919c 1071 "%s RESET ISSUED nexus=%ld:%d:%d cmd=%p.\n", name, vha->host_no,
7c3df132 1072 cmd->device->id, cmd->device->lun, cmd);
1da177e4 1073
523ec773 1074 err = 0;
7c3df132
SK		 1075 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1076 ql_log(ql_log_warn, vha, 0x800a,
1077 "Wait for hba online failed for cmd=%p.\n", cmd);
523ec773 1078 goto eh_reset_failed;
7c3df132 1079 }
523ec773 1080 err = 2;
2afa19a9 1081 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
7c3df132
SK		 1082 != QLA_SUCCESS) {
1083 ql_log(ql_log_warn, vha, 0x800c,
1084 "do_reset failed for cmd=%p.\n", cmd);
523ec773 1085 goto eh_reset_failed;
7c3df132 1086 }
523ec773 1087 err = 3;
e315cd28 1088 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
7c3df132
SK		 1089 cmd->device->lun, type) != QLA_SUCCESS) {
1090 ql_log(ql_log_warn, vha, 0x800d,
d6a03581 1091 "wait for pending cmds failed for cmd=%p.\n", cmd);
523ec773 1092 goto eh_reset_failed;
7c3df132 1093 }
523ec773 1094
7c3df132 1095 ql_log(ql_log_info, vha, 0x800e,
cfb0919c
CD		 1096 "%s RESET SUCCEEDED nexus:%ld:%d:%d cmd=%p.\n", name,
1097 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
523ec773
AV		 1098
1099 return SUCCESS;
1100
4d78c973 1101eh_reset_failed:
7c3df132 1102 ql_log(ql_log_info, vha, 0x800f,
cfb0919c
CD		 1103 "%s RESET FAILED: %s nexus=%ld:%d:%d cmd=%p.\n", name,
1104 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1105 cmd);
523ec773
AV		 1106 return FAILED;
1107}
1da177e4 1108
523ec773
AV		 1109static int
1110qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1111{
e315cd28
AC		 1112 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1113 struct qla_hw_data *ha = vha->hw;
1da177e4 1114
523ec773
AV		 1115 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1116 ha->isp_ops->lun_reset);
1da177e4
LT		 1117}
1118
1da177e4 1119static int
523ec773 1120qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1da177e4 1121{
e315cd28
AC		 1122 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1123 struct qla_hw_data *ha = vha->hw;
1da177e4 1124
523ec773
AV		 1125 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1126 ha->isp_ops->target_reset);
1da177e4
LT		 1127}
1128
1da177e4
LT		 1129/**************************************************************************
1130* qla2xxx_eh_bus_reset
1131*
1132* Description:
1133* The bus reset function will reset the bus and abort any executing
1134* commands.
1135*
1136* Input:
1137* cmd = Linux SCSI command packet of the command that cause the
1138* bus reset.
1139*
1140* Returns:
1141* SUCCESS/FAILURE (defined as macro in scsi.h).
1142*
1143**************************************************************************/
e5f82ab8 1144static int
1da177e4
LT		 1145qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1146{
e315cd28 1147 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1148 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
2c3dfe3f 1149 int ret = FAILED;
f4f051eb 1150 unsigned int id, lun;
f4f051eb 1151
f4f051eb 1152 id = cmd->device->id;
1153 lun = cmd->device->lun;
1da177e4 1154
7c3df132 1155 if (!fcport) {
f4f051eb 1156 return ret;
7c3df132 1157 }
1da177e4 1158
4e98d3b8
AV		 1159 ret = fc_block_scsi_eh(cmd);
1160 if (ret != 0)
1161 return ret;
1162 ret = FAILED;
1163
7c3df132 1164 ql_log(ql_log_info, vha, 0x8012,
46270afe 1165 "BUS RESET ISSUED nexus=%ld:%d:%d.\n", vha->host_no, id, lun);
1da177e4 1166
e315cd28 1167 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
7c3df132
SK		 1168 ql_log(ql_log_fatal, vha, 0x8013,
1169 "Wait for hba online failed board disabled.\n");
f4f051eb 1170 goto eh_bus_reset_done;
1da177e4
LT		 1171 }
1172
ad537689
SK		 1173 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1174 ret = SUCCESS;
1175
f4f051eb 1176 if (ret == FAILED)
1177 goto eh_bus_reset_done;
1da177e4 1178
9a41a62b 1179 /* Flush outstanding commands. */
4d78c973 1180 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
7c3df132
SK		 1181 QLA_SUCCESS) {
1182 ql_log(ql_log_warn, vha, 0x8014,
1183 "Wait for pending commands failed.\n");
9a41a62b 1184 ret = FAILED;
7c3df132 1185 }
1da177e4 1186
f4f051eb 1187eh_bus_reset_done:
7c3df132 1188 ql_log(ql_log_warn, vha, 0x802b,
cfb0919c 1189 "BUS RESET %s nexus=%ld:%d:%d.\n",
d6a03581 1190 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1191
f4f051eb 1192 return ret;
1da177e4
LT		 1193}
1194
1195/**************************************************************************
1196* qla2xxx_eh_host_reset
1197*
1198* Description:
1199* The reset function will reset the Adapter.
1200*
1201* Input:
1202* cmd = Linux SCSI command packet of the command that cause the
1203* adapter reset.
1204*
1205* Returns:
1206* Either SUCCESS or FAILED.
1207*
1208* Note:
1209**************************************************************************/
e5f82ab8 1210static int
1da177e4
LT		 1211qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1212{
e315cd28 1213 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
e315cd28 1214 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 1215 int ret = FAILED;
f4f051eb 1216 unsigned int id, lun;
e315cd28 1217 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1218
f4f051eb 1219 id = cmd->device->id;
1220 lun = cmd->device->lun;
f4f051eb 1221
7c3df132 1222 ql_log(ql_log_info, vha, 0x8018,
cfb0919c 1223 "ADAPTER RESET ISSUED nexus=%ld:%d:%d.\n", vha->host_no, id, lun);
1da177e4 1224
86fbee86 1225 if (qla2x00_wait_for_reset_ready(vha) != QLA_SUCCESS)
f4f051eb 1226 goto eh_host_reset_lock;
1da177e4 1227
e315cd28
AC		 1228 if (vha != base_vha) {
1229 if (qla2x00_vp_abort_isp(vha))
f4f051eb 1230 goto eh_host_reset_lock;
e315cd28 1231 } else {
a9083016
GM		 1232 if (IS_QLA82XX(vha->hw)) {
1233 if (!qla82xx_fcoe_ctx_reset(vha)) {
1234 /* Ctx reset success */
1235 ret = SUCCESS;
1236 goto eh_host_reset_lock;
1237 }
1238 /* fall thru if ctx reset failed */
1239 }
68ca949c
AC		 1240 if (ha->wq)
1241 flush_workqueue(ha->wq);
1242
e315cd28 1243 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 1244 if (ha->isp_ops->abort_isp(base_vha)) {
e315cd28
AC		 1245 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1246 /* failed. schedule dpc to try */
1247 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1248
7c3df132
SK		 1249 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1250 ql_log(ql_log_warn, vha, 0x802a,
1251 "wait for hba online failed.\n");
e315cd28 1252 goto eh_host_reset_lock;
7c3df132 1253 }
e315cd28
AC		 1254 }
1255 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
fa2a1ce5 1256 }
1da177e4 1257
e315cd28 1258 /* Waiting for command to be returned to OS.*/
4d78c973 1259 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
e315cd28 1260 QLA_SUCCESS)
f4f051eb 1261 ret = SUCCESS;
1da177e4 1262
f4f051eb 1263eh_host_reset_lock:
cfb0919c
CD		 1264 ql_log(ql_log_info, vha, 0x8017,
1265 "ADAPTER RESET %s nexus=%ld:%d:%d.\n",
1266 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1267
f4f051eb 1268 return ret;
1269}
1da177e4
LT		 1270
1271/*
1272* qla2x00_loop_reset
1273* Issue loop reset.
1274*
1275* Input:
1276* ha = adapter block pointer.
1277*
1278* Returns:
1279* 0 = success
1280*/
a4722cf2 1281int
e315cd28 1282qla2x00_loop_reset(scsi_qla_host_t *vha)
1da177e4 1283{
0c8c39af 1284 int ret;
bdf79621 1285 struct fc_port *fcport;
e315cd28 1286 struct qla_hw_data *ha = vha->hw;
1da177e4 1287
f4c496c1 1288 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
55e5ed27
AV		 1289 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1290 if (fcport->port_type != FCT_TARGET)
1291 continue;
1292
1293 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1294 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1295 ql_dbg(ql_dbg_taskm, vha, 0x802c,
1296 "Bus Reset failed: Target Reset=%d "
1297 "d_id=%x.\n", ret, fcport->d_id.b24);
55e5ed27
AV		 1298 }
1299 }
1300 }
1301
6246b8a1 1302 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
e315cd28 1303 ret = qla2x00_full_login_lip(vha);
0c8c39af 1304 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1305 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1306 "full_login_lip=%d.\n", ret);
749af3d5
AC		 1307 }
1308 atomic_set(&vha->loop_state, LOOP_DOWN);
1309 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1310 qla2x00_mark_all_devices_lost(vha, 0);
0c8c39af
AV		 1311 }
1312
0d6e61bc 1313 if (ha->flags.enable_lip_reset) {
e315cd28 1314 ret = qla2x00_lip_reset(vha);
ad537689 1315 if (ret != QLA_SUCCESS)
7c3df132
SK		 1316 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1317 "lip_reset failed (%d).\n", ret);
1da177e4
LT		 1318 }
1319
1da177e4 1320 /* Issue marker command only when we are going to start the I/O */
e315cd28 1321 vha->marker_needed = 1;
1da177e4 1322
0c8c39af 1323 return QLA_SUCCESS;
1da177e4
LT		 1324}
1325
df4bf0bb 1326void
e315cd28 1327qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
df4bf0bb 1328{
73208dfd 1329 int que, cnt;
df4bf0bb
AV		 1330 unsigned long flags;
1331 srb_t *sp;
e315cd28 1332 struct qla_hw_data *ha = vha->hw;
73208dfd 1333 struct req_que *req;
df4bf0bb
AV		 1334
1335 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 1336 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe 1337 req = ha->req_q_map[que];
73208dfd
AC		 1338 if (!req)
1339 continue;
1340 for (cnt = 1; cnt < MAX_OUTSTANDING_COMMANDS; cnt++) {
1341 sp = req->outstanding_cmds[cnt];
e612d465 1342 if (sp) {
73208dfd 1343 req->outstanding_cmds[cnt] = NULL;
9ba56b95 1344 sp->done(vha, sp, res);
73208dfd 1345 }
df4bf0bb
AV		 1346 }
1347 }
1348 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1349}
1350
f4f051eb 1351static int
1352qla2xxx_slave_alloc(struct scsi_device *sdev)
1da177e4 1353{
bdf79621 1354 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1da177e4 1355
19a7b4ae 1356 if (!rport || fc_remote_port_chkready(rport))
f4f051eb 1357 return -ENXIO;
bdf79621 1358
19a7b4ae 1359 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1da177e4 1360
f4f051eb 1361 return 0;
1362}
1da177e4 1363
f4f051eb 1364static int
1365qla2xxx_slave_configure(struct scsi_device *sdev)
1366{
e315cd28 1367 scsi_qla_host_t *vha = shost_priv(sdev->host);
2afa19a9 1368 struct req_que *req = vha->req;
8482e118 1369
9e522cd8
AE		 1370 if (IS_T10_PI_CAPABLE(vha->hw))
1371 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1372
f4f051eb 1373 if (sdev->tagged_supported)
73208dfd 1374 scsi_activate_tcq(sdev, req->max_q_depth);
f4f051eb 1375 else
73208dfd 1376 scsi_deactivate_tcq(sdev, req->max_q_depth);
f4f051eb 1377 return 0;
1378}
1da177e4 1379
f4f051eb 1380static void
1381qla2xxx_slave_destroy(struct scsi_device *sdev)
1382{
1383 sdev->hostdata = NULL;
1da177e4
LT		 1384}
1385
c45dd305
GM		 1386static void qla2x00_handle_queue_full(struct scsi_device *sdev, int qdepth)
1387{
1388 fc_port_t *fcport = (struct fc_port *) sdev->hostdata;
1389
1390 if (!scsi_track_queue_full(sdev, qdepth))
1391 return;
1392
7c3df132 1393 ql_dbg(ql_dbg_io, fcport->vha, 0x3029,
cfb0919c
CD		 1394 "Queue depth adjusted-down to %d for nexus=%ld:%d:%d.\n",
1395 sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun);
c45dd305
GM		 1396}
1397
1398static void qla2x00_adjust_sdev_qdepth_up(struct scsi_device *sdev, int qdepth)
1399{
1400 fc_port_t *fcport = sdev->hostdata;
1401 struct scsi_qla_host *vha = fcport->vha;
c45dd305
GM		 1402 struct req_que *req = NULL;
1403
1404 req = vha->req;
1405 if (!req)
1406 return;
1407
1408 if (req->max_q_depth <= sdev->queue_depth || req->max_q_depth < qdepth)
1409 return;
1410
1411 if (sdev->ordered_tags)
1412 scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG, qdepth);
1413 else
1414 scsi_adjust_queue_depth(sdev, MSG_SIMPLE_TAG, qdepth);
1415
7c3df132 1416 ql_dbg(ql_dbg_io, vha, 0x302a,
cfb0919c
CD		 1417 "Queue depth adjusted-up to %d for nexus=%ld:%d:%d.\n",
1418 sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun);
c45dd305
GM		 1419}
1420
ce7e4af7 1421static int
e881a172 1422qla2x00_change_queue_depth(struct scsi_device *sdev, int qdepth, int reason)
ce7e4af7 1423{
c45dd305
GM		 1424 switch (reason) {
1425 case SCSI_QDEPTH_DEFAULT:
1426 scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth);
1427 break;
1428 case SCSI_QDEPTH_QFULL:
1429 qla2x00_handle_queue_full(sdev, qdepth);
1430 break;
1431 case SCSI_QDEPTH_RAMP_UP:
1432 qla2x00_adjust_sdev_qdepth_up(sdev, qdepth);
1433 break;
1434 default:
08002af2 1435 return -EOPNOTSUPP;
c45dd305 1436 }
e881a172 1437
ce7e4af7
AV		 1438 return sdev->queue_depth;
1439}
1440
1441static int
1442qla2x00_change_queue_type(struct scsi_device *sdev, int tag_type)
1443{
1444 if (sdev->tagged_supported) {
1445 scsi_set_tag_type(sdev, tag_type);
1446 if (tag_type)
1447 scsi_activate_tcq(sdev, sdev->queue_depth);
1448 else
1449 scsi_deactivate_tcq(sdev, sdev->queue_depth);
1450 } else
1451 tag_type = 0;
1452
1453 return tag_type;
1454}
1455
1da177e4
LT		 1456/**
1457 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1458 * @ha: HA context
1459 *
1460 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1461 * supported addressing method.
1462 */
1463static void
53303c42 1464qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1da177e4 1465{
7524f9b9 1466 /* Assume a 32bit DMA mask. */
1da177e4 1467 ha->flags.enable_64bit_addressing = 0;
1da177e4 1468
6a35528a 1469 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
7524f9b9
AV		 1470 /* Any upper-dword bits set? */
1471 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
6a35528a 1472 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
7524f9b9 1473 /* Ok, a 64bit DMA mask is applicable. */
1da177e4 1474 ha->flags.enable_64bit_addressing = 1;
fd34f556
AV		 1475 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1476 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
7524f9b9 1477 return;
1da177e4 1478 }
1da177e4 1479 }
7524f9b9 1480
284901a9
YH		 1481 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1482 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1da177e4
LT		 1483}
1484
fd34f556 1485static void
e315cd28 1486qla2x00_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1487{
1488 unsigned long flags = 0;
1489 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1490
1491 spin_lock_irqsave(&ha->hardware_lock, flags);
1492 ha->interrupts_on = 1;
1493 /* enable risc and host interrupts */
1494 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1495 RD_REG_WORD(&reg->ictrl);
1496 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1497
1498}
1499
1500static void
e315cd28 1501qla2x00_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1502{
1503 unsigned long flags = 0;
1504 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1505
1506 spin_lock_irqsave(&ha->hardware_lock, flags);
1507 ha->interrupts_on = 0;
1508 /* disable risc and host interrupts */
1509 WRT_REG_WORD(&reg->ictrl, 0);
1510 RD_REG_WORD(&reg->ictrl);
1511 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1512}
1513
1514static void
e315cd28 1515qla24xx_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1516{
1517 unsigned long flags = 0;
1518 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1519
1520 spin_lock_irqsave(&ha->hardware_lock, flags);
1521 ha->interrupts_on = 1;
1522 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1523 RD_REG_DWORD(&reg->ictrl);
1524 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1525}
1526
1527static void
e315cd28 1528qla24xx_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1529{
1530 unsigned long flags = 0;
1531 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1532
124f85e6
AV		 1533 if (IS_NOPOLLING_TYPE(ha))
1534 return;
fd34f556
AV		 1535 spin_lock_irqsave(&ha->hardware_lock, flags);
1536 ha->interrupts_on = 0;
1537 WRT_REG_DWORD(&reg->ictrl, 0);
1538 RD_REG_DWORD(&reg->ictrl);
1539 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1540}
1541
706f457d
GM		 1542static int
1543qla2x00_iospace_config(struct qla_hw_data *ha)
1544{
1545 resource_size_t pio;
1546 uint16_t msix;
1547 int cpus;
1548
706f457d
GM		 1549 if (pci_request_selected_regions(ha->pdev, ha->bars,
1550 QLA2XXX_DRIVER_NAME)) {
1551 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1552 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1553 pci_name(ha->pdev));
1554 goto iospace_error_exit;
1555 }
1556 if (!(ha->bars & 1))
1557 goto skip_pio;
1558
1559 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1560 pio = pci_resource_start(ha->pdev, 0);
1561 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1562 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1563 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1564 "Invalid pci I/O region size (%s).\n",
1565 pci_name(ha->pdev));
1566 pio = 0;
1567 }
1568 } else {
1569 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1570 "Region #0 no a PIO resource (%s).\n",
1571 pci_name(ha->pdev));
1572 pio = 0;
1573 }
1574 ha->pio_address = pio;
1575 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1576 "PIO address=%llu.\n",
1577 (unsigned long long)ha->pio_address);
1578
1579skip_pio:
1580 /* Use MMIO operations for all accesses. */
1581 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1582 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1583 "Region #1 not an MMIO resource (%s), aborting.\n",
1584 pci_name(ha->pdev));
1585 goto iospace_error_exit;
1586 }
1587 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1588 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1589 "Invalid PCI mem region size (%s), aborting.\n",
1590 pci_name(ha->pdev));
1591 goto iospace_error_exit;
1592 }
1593
1594 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1595 if (!ha->iobase) {
1596 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1597 "Cannot remap MMIO (%s), aborting.\n",
1598 pci_name(ha->pdev));
1599 goto iospace_error_exit;
1600 }
1601
1602 /* Determine queue resources */
1603 ha->max_req_queues = ha->max_rsp_queues = 1;
1604 if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) ||
1605 (ql2xmaxqueues > 1 && ql2xmultique_tag) ||
1606 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
1607 goto mqiobase_exit;
1608
1609 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1610 pci_resource_len(ha->pdev, 3));
1611 if (ha->mqiobase) {
1612 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
1613 "MQIO Base=%p.\n", ha->mqiobase);
1614 /* Read MSIX vector size of the board */
1615 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
1616 ha->msix_count = msix;
1617 /* Max queues are bounded by available msix vectors */
1618 /* queue 0 uses two msix vectors */
1619 if (ql2xmultique_tag) {
1620 cpus = num_online_cpus();
1621 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1622 (cpus + 1) : (ha->msix_count - 1);
1623 ha->max_req_queues = 2;
1624 } else if (ql2xmaxqueues > 1) {
1625 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1626 QLA_MQ_SIZE : ql2xmaxqueues;
1627 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc008,
1628 "QoS mode set, max no of request queues:%d.\n",
1629 ha->max_req_queues);
1630 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0019,
1631 "QoS mode set, max no of request queues:%d.\n",
1632 ha->max_req_queues);
1633 }
1634 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
1635 "MSI-X vector count: %d.\n", msix);
1636 } else
1637 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
1638 "BAR 3 not enabled.\n");
1639
1640mqiobase_exit:
1641 ha->msix_count = ha->max_rsp_queues + 1;
1642 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
1643 "MSIX Count:%d.\n", ha->msix_count);
1644 return (0);
1645
1646iospace_error_exit:
1647 return (-ENOMEM);
1648}
1649
1650
6246b8a1
GM		 1651static int
1652qla83xx_iospace_config(struct qla_hw_data *ha)
1653{
1654 uint16_t msix;
1655 int cpus;
1656
1657 if (pci_request_selected_regions(ha->pdev, ha->bars,
1658 QLA2XXX_DRIVER_NAME)) {
1659 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
1660 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1661 pci_name(ha->pdev));
1662
1663 goto iospace_error_exit;
1664 }
1665
1666 /* Use MMIO operations for all accesses. */
1667 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
1668 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
1669 "Invalid pci I/O region size (%s).\n",
1670 pci_name(ha->pdev));
1671 goto iospace_error_exit;
1672 }
1673 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1674 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
1675 "Invalid PCI mem region size (%s), aborting\n",
1676 pci_name(ha->pdev));
1677 goto iospace_error_exit;
1678 }
1679
1680 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
1681 if (!ha->iobase) {
1682 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
1683 "Cannot remap MMIO (%s), aborting.\n",
1684 pci_name(ha->pdev));
1685 goto iospace_error_exit;
1686 }
1687
1688 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
1689 /* 83XX 26XX always use MQ type access for queues
1690 * - mbar 2, a.k.a region 4 */
1691 ha->max_req_queues = ha->max_rsp_queues = 1;
1692 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
1693 pci_resource_len(ha->pdev, 4));
1694
1695 if (!ha->mqiobase) {
1696 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
1697 "BAR2/region4 not enabled\n");
1698 goto mqiobase_exit;
1699 }
1700
1701 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
1702 pci_resource_len(ha->pdev, 2));
1703 if (ha->msixbase) {
1704 /* Read MSIX vector size of the board */
1705 pci_read_config_word(ha->pdev,
1706 QLA_83XX_PCI_MSIX_CONTROL, &msix);
1707 ha->msix_count = msix;
1708 /* Max queues are bounded by available msix vectors */
1709 /* queue 0 uses two msix vectors */
1710 if (ql2xmultique_tag) {
1711 cpus = num_online_cpus();
1712 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1713 (cpus + 1) : (ha->msix_count - 1);
1714 ha->max_req_queues = 2;
1715 } else if (ql2xmaxqueues > 1) {
1716 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1717 QLA_MQ_SIZE : ql2xmaxqueues;
1718 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc00c,
1719 "QoS mode set, max no of request queues:%d.\n",
1720 ha->max_req_queues);
1721 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
1722 "QoS mode set, max no of request queues:%d.\n",
1723 ha->max_req_queues);
1724 }
1725 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
1726 "MSI-X vector count: %d.\n", msix);
1727 } else
1728 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
1729 "BAR 1 not enabled.\n");
1730
1731mqiobase_exit:
1732 ha->msix_count = ha->max_rsp_queues + 1;
1733 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
1734 "MSIX Count:%d.\n", ha->msix_count);
1735 return 0;
1736
1737iospace_error_exit:
1738 return -ENOMEM;
1739}
1740
fd34f556
AV		 1741static struct isp_operations qla2100_isp_ops = {
1742 .pci_config = qla2100_pci_config,
1743 .reset_chip = qla2x00_reset_chip,
1744 .chip_diag = qla2x00_chip_diag,
1745 .config_rings = qla2x00_config_rings,
1746 .reset_adapter = qla2x00_reset_adapter,
1747 .nvram_config = qla2x00_nvram_config,
1748 .update_fw_options = qla2x00_update_fw_options,
1749 .load_risc = qla2x00_load_risc,
1750 .pci_info_str = qla2x00_pci_info_str,
1751 .fw_version_str = qla2x00_fw_version_str,
1752 .intr_handler = qla2100_intr_handler,
1753 .enable_intrs = qla2x00_enable_intrs,
1754 .disable_intrs = qla2x00_disable_intrs,
1755 .abort_command = qla2x00_abort_command,
523ec773
AV		 1756 .target_reset = qla2x00_abort_target,
1757 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1758 .fabric_login = qla2x00_login_fabric,
1759 .fabric_logout = qla2x00_fabric_logout,
1760 .calc_req_entries = qla2x00_calc_iocbs_32,
1761 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1762 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1763 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1764 .read_nvram = qla2x00_read_nvram_data,
1765 .write_nvram = qla2x00_write_nvram_data,
1766 .fw_dump = qla2100_fw_dump,
1767 .beacon_on = NULL,
1768 .beacon_off = NULL,
1769 .beacon_blink = NULL,
1770 .read_optrom = qla2x00_read_optrom_data,
1771 .write_optrom = qla2x00_write_optrom_data,
1772 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1773 .start_scsi = qla2x00_start_scsi,
a9083016 1774 .abort_isp = qla2x00_abort_isp,
706f457d 1775 .iospace_config = qla2x00_iospace_config,
fd34f556
AV		 1776};
1777
1778static struct isp_operations qla2300_isp_ops = {
1779 .pci_config = qla2300_pci_config,
1780 .reset_chip = qla2x00_reset_chip,
1781 .chip_diag = qla2x00_chip_diag,
1782 .config_rings = qla2x00_config_rings,
1783 .reset_adapter = qla2x00_reset_adapter,
1784 .nvram_config = qla2x00_nvram_config,
1785 .update_fw_options = qla2x00_update_fw_options,
1786 .load_risc = qla2x00_load_risc,
1787 .pci_info_str = qla2x00_pci_info_str,
1788 .fw_version_str = qla2x00_fw_version_str,
1789 .intr_handler = qla2300_intr_handler,
1790 .enable_intrs = qla2x00_enable_intrs,
1791 .disable_intrs = qla2x00_disable_intrs,
1792 .abort_command = qla2x00_abort_command,
523ec773
AV		 1793 .target_reset = qla2x00_abort_target,
1794 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1795 .fabric_login = qla2x00_login_fabric,
1796 .fabric_logout = qla2x00_fabric_logout,
1797 .calc_req_entries = qla2x00_calc_iocbs_32,
1798 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1799 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1800 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1801 .read_nvram = qla2x00_read_nvram_data,
1802 .write_nvram = qla2x00_write_nvram_data,
1803 .fw_dump = qla2300_fw_dump,
1804 .beacon_on = qla2x00_beacon_on,
1805 .beacon_off = qla2x00_beacon_off,
1806 .beacon_blink = qla2x00_beacon_blink,
1807 .read_optrom = qla2x00_read_optrom_data,
1808 .write_optrom = qla2x00_write_optrom_data,
1809 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1810 .start_scsi = qla2x00_start_scsi,
a9083016 1811 .abort_isp = qla2x00_abort_isp,
706f457d 1812 .iospace_config = qla2x00_iospace_config,
fd34f556
AV		 1813};
1814
1815static struct isp_operations qla24xx_isp_ops = {
1816 .pci_config = qla24xx_pci_config,
1817 .reset_chip = qla24xx_reset_chip,
1818 .chip_diag = qla24xx_chip_diag,
1819 .config_rings = qla24xx_config_rings,
1820 .reset_adapter = qla24xx_reset_adapter,
1821 .nvram_config = qla24xx_nvram_config,
1822 .update_fw_options = qla24xx_update_fw_options,
1823 .load_risc = qla24xx_load_risc,
1824 .pci_info_str = qla24xx_pci_info_str,
1825 .fw_version_str = qla24xx_fw_version_str,
1826 .intr_handler = qla24xx_intr_handler,
1827 .enable_intrs = qla24xx_enable_intrs,
1828 .disable_intrs = qla24xx_disable_intrs,
1829 .abort_command = qla24xx_abort_command,
523ec773
AV		 1830 .target_reset = qla24xx_abort_target,
1831 .lun_reset = qla24xx_lun_reset,
fd34f556
AV		 1832 .fabric_login = qla24xx_login_fabric,
1833 .fabric_logout = qla24xx_fabric_logout,
1834 .calc_req_entries = NULL,
1835 .build_iocbs = NULL,
1836 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1837 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1838 .read_nvram = qla24xx_read_nvram_data,
1839 .write_nvram = qla24xx_write_nvram_data,
1840 .fw_dump = qla24xx_fw_dump,
1841 .beacon_on = qla24xx_beacon_on,
1842 .beacon_off = qla24xx_beacon_off,
1843 .beacon_blink = qla24xx_beacon_blink,
1844 .read_optrom = qla24xx_read_optrom_data,
1845 .write_optrom = qla24xx_write_optrom_data,
1846 .get_flash_version = qla24xx_get_flash_version,
e315cd28 1847 .start_scsi = qla24xx_start_scsi,
a9083016 1848 .abort_isp = qla2x00_abort_isp,
706f457d 1849 .iospace_config = qla2x00_iospace_config,
fd34f556
AV		 1850};
1851
c3a2f0df
AV		 1852static struct isp_operations qla25xx_isp_ops = {
1853 .pci_config = qla25xx_pci_config,
1854 .reset_chip = qla24xx_reset_chip,
1855 .chip_diag = qla24xx_chip_diag,
1856 .config_rings = qla24xx_config_rings,
1857 .reset_adapter = qla24xx_reset_adapter,
1858 .nvram_config = qla24xx_nvram_config,
1859 .update_fw_options = qla24xx_update_fw_options,
1860 .load_risc = qla24xx_load_risc,
1861 .pci_info_str = qla24xx_pci_info_str,
1862 .fw_version_str = qla24xx_fw_version_str,
1863 .intr_handler = qla24xx_intr_handler,
1864 .enable_intrs = qla24xx_enable_intrs,
1865 .disable_intrs = qla24xx_disable_intrs,
1866 .abort_command = qla24xx_abort_command,
523ec773
AV		 1867 .target_reset = qla24xx_abort_target,
1868 .lun_reset = qla24xx_lun_reset,
c3a2f0df
AV		 1869 .fabric_login = qla24xx_login_fabric,
1870 .fabric_logout = qla24xx_fabric_logout,
1871 .calc_req_entries = NULL,
1872 .build_iocbs = NULL,
1873 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1874 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1875 .read_nvram = qla25xx_read_nvram_data,
1876 .write_nvram = qla25xx_write_nvram_data,
1877 .fw_dump = qla25xx_fw_dump,
1878 .beacon_on = qla24xx_beacon_on,
1879 .beacon_off = qla24xx_beacon_off,
1880 .beacon_blink = qla24xx_beacon_blink,
338c9161 1881 .read_optrom = qla25xx_read_optrom_data,
c3a2f0df
AV		 1882 .write_optrom = qla24xx_write_optrom_data,
1883 .get_flash_version = qla24xx_get_flash_version,
bad75002 1884 .start_scsi = qla24xx_dif_start_scsi,
a9083016 1885 .abort_isp = qla2x00_abort_isp,
706f457d 1886 .iospace_config = qla2x00_iospace_config,
c3a2f0df
AV		 1887};
1888
3a03eb79
AV		 1889static struct isp_operations qla81xx_isp_ops = {
1890 .pci_config = qla25xx_pci_config,
1891 .reset_chip = qla24xx_reset_chip,
1892 .chip_diag = qla24xx_chip_diag,
1893 .config_rings = qla24xx_config_rings,
1894 .reset_adapter = qla24xx_reset_adapter,
1895 .nvram_config = qla81xx_nvram_config,
1896 .update_fw_options = qla81xx_update_fw_options,
eaac30be 1897 .load_risc = qla81xx_load_risc,
3a03eb79
AV		 1898 .pci_info_str = qla24xx_pci_info_str,
1899 .fw_version_str = qla24xx_fw_version_str,
1900 .intr_handler = qla24xx_intr_handler,
1901 .enable_intrs = qla24xx_enable_intrs,
1902 .disable_intrs = qla24xx_disable_intrs,
1903 .abort_command = qla24xx_abort_command,
1904 .target_reset = qla24xx_abort_target,
1905 .lun_reset = qla24xx_lun_reset,
1906 .fabric_login = qla24xx_login_fabric,
1907 .fabric_logout = qla24xx_fabric_logout,
1908 .calc_req_entries = NULL,
1909 .build_iocbs = NULL,
1910 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1911 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
3d79038f
AV		 1912 .read_nvram = NULL,
1913 .write_nvram = NULL,
3a03eb79
AV		 1914 .fw_dump = qla81xx_fw_dump,
1915 .beacon_on = qla24xx_beacon_on,
1916 .beacon_off = qla24xx_beacon_off,
6246b8a1 1917 .beacon_blink = qla83xx_beacon_blink,
3a03eb79
AV		 1918 .read_optrom = qla25xx_read_optrom_data,
1919 .write_optrom = qla24xx_write_optrom_data,
1920 .get_flash_version = qla24xx_get_flash_version,
ba77ef53 1921 .start_scsi = qla24xx_dif_start_scsi,
a9083016 1922 .abort_isp = qla2x00_abort_isp,
706f457d 1923 .iospace_config = qla2x00_iospace_config,
a9083016
GM		 1924};
1925
1926static struct isp_operations qla82xx_isp_ops = {
1927 .pci_config = qla82xx_pci_config,
1928 .reset_chip = qla82xx_reset_chip,
1929 .chip_diag = qla24xx_chip_diag,
1930 .config_rings = qla82xx_config_rings,
1931 .reset_adapter = qla24xx_reset_adapter,
1932 .nvram_config = qla81xx_nvram_config,
1933 .update_fw_options = qla24xx_update_fw_options,
1934 .load_risc = qla82xx_load_risc,
9d55ca66 1935 .pci_info_str = qla24xx_pci_info_str,
a9083016
GM		 1936 .fw_version_str = qla24xx_fw_version_str,
1937 .intr_handler = qla82xx_intr_handler,
1938 .enable_intrs = qla82xx_enable_intrs,
1939 .disable_intrs = qla82xx_disable_intrs,
1940 .abort_command = qla24xx_abort_command,
1941 .target_reset = qla24xx_abort_target,
1942 .lun_reset = qla24xx_lun_reset,
1943 .fabric_login = qla24xx_login_fabric,
1944 .fabric_logout = qla24xx_fabric_logout,
1945 .calc_req_entries = NULL,
1946 .build_iocbs = NULL,
1947 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1948 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1949 .read_nvram = qla24xx_read_nvram_data,
1950 .write_nvram = qla24xx_write_nvram_data,
1951 .fw_dump = qla24xx_fw_dump,
999916dc
SK		 1952 .beacon_on = qla82xx_beacon_on,
1953 .beacon_off = qla82xx_beacon_off,
1954 .beacon_blink = NULL,
a9083016
GM		 1955 .read_optrom = qla82xx_read_optrom_data,
1956 .write_optrom = qla82xx_write_optrom_data,
1957 .get_flash_version = qla24xx_get_flash_version,
1958 .start_scsi = qla82xx_start_scsi,
1959 .abort_isp = qla82xx_abort_isp,
706f457d 1960 .iospace_config = qla82xx_iospace_config,
3a03eb79
AV		 1961};
1962
6246b8a1
GM		 1963static struct isp_operations qla83xx_isp_ops = {
1964 .pci_config = qla25xx_pci_config,
1965 .reset_chip = qla24xx_reset_chip,
1966 .chip_diag = qla24xx_chip_diag,
1967 .config_rings = qla24xx_config_rings,
1968 .reset_adapter = qla24xx_reset_adapter,
1969 .nvram_config = qla81xx_nvram_config,
1970 .update_fw_options = qla81xx_update_fw_options,
1971 .load_risc = qla81xx_load_risc,
1972 .pci_info_str = qla24xx_pci_info_str,
1973 .fw_version_str = qla24xx_fw_version_str,
1974 .intr_handler = qla24xx_intr_handler,
1975 .enable_intrs = qla24xx_enable_intrs,
1976 .disable_intrs = qla24xx_disable_intrs,
1977 .abort_command = qla24xx_abort_command,
1978 .target_reset = qla24xx_abort_target,
1979 .lun_reset = qla24xx_lun_reset,
1980 .fabric_login = qla24xx_login_fabric,
1981 .fabric_logout = qla24xx_fabric_logout,
1982 .calc_req_entries = NULL,
1983 .build_iocbs = NULL,
1984 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1985 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1986 .read_nvram = NULL,
1987 .write_nvram = NULL,
1988 .fw_dump = qla83xx_fw_dump,
1989 .beacon_on = qla24xx_beacon_on,
1990 .beacon_off = qla24xx_beacon_off,
1991 .beacon_blink = qla83xx_beacon_blink,
1992 .read_optrom = qla25xx_read_optrom_data,
1993 .write_optrom = qla24xx_write_optrom_data,
1994 .get_flash_version = qla24xx_get_flash_version,
1995 .start_scsi = qla24xx_dif_start_scsi,
1996 .abort_isp = qla2x00_abort_isp,
1997 .iospace_config = qla83xx_iospace_config,
1998};
1999
ea5b6382 2000static inline void
e315cd28 2001qla2x00_set_isp_flags(struct qla_hw_data *ha)
ea5b6382 2002{
2003 ha->device_type = DT_EXTENDED_IDS;
2004 switch (ha->pdev->device) {
2005 case PCI_DEVICE_ID_QLOGIC_ISP2100:
2006 ha->device_type |= DT_ISP2100;
2007 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2008 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382 2009 break;
2010 case PCI_DEVICE_ID_QLOGIC_ISP2200:
2011 ha->device_type |= DT_ISP2200;
2012 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2013 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382 2014 break;
2015 case PCI_DEVICE_ID_QLOGIC_ISP2300:
2016 ha->device_type |= DT_ISP2300;
4a59f71d 2017 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2018 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2019 break;
2020 case PCI_DEVICE_ID_QLOGIC_ISP2312:
2021 ha->device_type |= DT_ISP2312;
4a59f71d 2022 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2023 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2024 break;
2025 case PCI_DEVICE_ID_QLOGIC_ISP2322:
2026 ha->device_type |= DT_ISP2322;
4a59f71d 2027 ha->device_type |= DT_ZIO_SUPPORTED;
ea5b6382 2028 if (ha->pdev->subsystem_vendor == 0x1028 &&
2029 ha->pdev->subsystem_device == 0x0170)
2030 ha->device_type |= DT_OEM_001;
441d1072 2031 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2032 break;
2033 case PCI_DEVICE_ID_QLOGIC_ISP6312:
2034 ha->device_type |= DT_ISP6312;
441d1072 2035 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2036 break;
2037 case PCI_DEVICE_ID_QLOGIC_ISP6322:
2038 ha->device_type |= DT_ISP6322;
441d1072 2039 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2040 break;
2041 case PCI_DEVICE_ID_QLOGIC_ISP2422:
2042 ha->device_type |= DT_ISP2422;
4a59f71d 2043 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2044 ha->device_type |= DT_FWI2;
c76f2c01 2045 ha->device_type |= DT_IIDMA;
441d1072 2046 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2047 break;
2048 case PCI_DEVICE_ID_QLOGIC_ISP2432:
2049 ha->device_type |= DT_ISP2432;
4a59f71d 2050 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2051 ha->device_type |= DT_FWI2;
c76f2c01 2052 ha->device_type |= DT_IIDMA;
441d1072 2053 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2054 break;
4d4df193
HK		 2055 case PCI_DEVICE_ID_QLOGIC_ISP8432:
2056 ha->device_type |= DT_ISP8432;
2057 ha->device_type |= DT_ZIO_SUPPORTED;
2058 ha->device_type |= DT_FWI2;
2059 ha->device_type |= DT_IIDMA;
2060 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2061 break;
044cc6c8 2062 case PCI_DEVICE_ID_QLOGIC_ISP5422:
2063 ha->device_type |= DT_ISP5422;
e428924c 2064 ha->device_type |= DT_FWI2;
441d1072 2065 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2066 break;
044cc6c8 2067 case PCI_DEVICE_ID_QLOGIC_ISP5432:
2068 ha->device_type |= DT_ISP5432;
e428924c 2069 ha->device_type |= DT_FWI2;
441d1072 2070 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2071 break;
c3a2f0df
AV		 2072 case PCI_DEVICE_ID_QLOGIC_ISP2532:
2073 ha->device_type |= DT_ISP2532;
2074 ha->device_type |= DT_ZIO_SUPPORTED;
2075 ha->device_type |= DT_FWI2;
2076 ha->device_type |= DT_IIDMA;
441d1072 2077 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2078 break;
3a03eb79
AV		 2079 case PCI_DEVICE_ID_QLOGIC_ISP8001:
2080 ha->device_type |= DT_ISP8001;
2081 ha->device_type |= DT_ZIO_SUPPORTED;
2082 ha->device_type |= DT_FWI2;
2083 ha->device_type |= DT_IIDMA;
2084 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2085 break;
a9083016
GM		 2086 case PCI_DEVICE_ID_QLOGIC_ISP8021:
2087 ha->device_type |= DT_ISP8021;
2088 ha->device_type |= DT_ZIO_SUPPORTED;
2089 ha->device_type |= DT_FWI2;
2090 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2091 /* Initialize 82XX ISP flags */
2092 qla82xx_init_flags(ha);
2093 break;
6246b8a1
GM		 2094 case PCI_DEVICE_ID_QLOGIC_ISP2031:
2095 ha->device_type |= DT_ISP2031;
2096 ha->device_type |= DT_ZIO_SUPPORTED;
2097 ha->device_type |= DT_FWI2;
2098 ha->device_type |= DT_IIDMA;
2099 ha->device_type |= DT_T10_PI;
2100 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2101 break;
2102 case PCI_DEVICE_ID_QLOGIC_ISP8031:
2103 ha->device_type |= DT_ISP8031;
2104 ha->device_type |= DT_ZIO_SUPPORTED;
2105 ha->device_type |= DT_FWI2;
2106 ha->device_type |= DT_IIDMA;
2107 ha->device_type |= DT_T10_PI;
2108 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2109 break;
ea5b6382 2110 }
e5b68a61 2111
a9083016
GM		 2112 if (IS_QLA82XX(ha))
2113 ha->port_no = !(ha->portnum & 1);
2114 else
2115 /* Get adapter physical port no from interrupt pin register. */
2116 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
2117
e5b68a61
AC		 2118 if (ha->port_no & 1)
2119 ha->flags.port0 = 1;
2120 else
2121 ha->flags.port0 = 0;
7c3df132 2122 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
d8424f68 2123 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
7c3df132 2124 ha->device_type, ha->flags.port0, ha->fw_srisc_address);
ea5b6382 2125}
2126
1e99e33a
AV		 2127static void
2128qla2xxx_scan_start(struct Scsi_Host *shost)
2129{
e315cd28 2130 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2131
cbc8eb67
AV		 2132 if (vha->hw->flags.running_gold_fw)
2133 return;
2134
e315cd28
AC		 2135 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2136 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2137 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2138 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
1e99e33a
AV		 2139}
2140
2141static int
2142qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2143{
e315cd28 2144 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2145
e315cd28 2146 if (!vha->host)
1e99e33a 2147 return 1;
e315cd28 2148 if (time > vha->hw->loop_reset_delay * HZ)
1e99e33a
AV		 2149 return 1;
2150
e315cd28 2151 return atomic_read(&vha->loop_state) == LOOP_READY;
1e99e33a
AV		 2152}
2153
1da177e4
LT		 2154/*
2155 * PCI driver interface
2156 */
6f039790 2157static int
7ee61397 2158qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1da177e4 2159{
a1541d5a 2160 int ret = -ENODEV;
1da177e4 2161 struct Scsi_Host *host;
e315cd28
AC		 2162 scsi_qla_host_t *base_vha = NULL;
2163 struct qla_hw_data *ha;
29856e28 2164 char pci_info[30];
7d613ac6 2165 char fw_str[30], wq_name[30];
5433383e 2166 struct scsi_host_template *sht;
642ef983 2167 int bars, mem_only = 0;
e315cd28 2168 uint16_t req_length = 0, rsp_length = 0;
73208dfd
AC		 2169 struct req_que *req = NULL;
2170 struct rsp_que *rsp = NULL;
1da177e4 2171
285d0321 2172 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
a5326f86 2173 sht = &qla2xxx_driver_template;
5433383e 2174 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
8bc69e7d 2175 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
4d4df193 2176 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
8bc69e7d 2177 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
c3a2f0df 2178 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
3a03eb79 2179 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
a9083016 2180 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
6246b8a1
GM		 2181 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2182 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
2183 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031) {
285d0321 2184 bars = pci_select_bars(pdev, IORESOURCE_MEM);
09483916 2185 mem_only = 1;
7c3df132
SK		 2186 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2187 "Mem only adapter.\n");
285d0321 2188 }
7c3df132
SK		 2189 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2190 "Bars=%d.\n", bars);
285d0321 2191
09483916
BH		 2192 if (mem_only) {
2193 if (pci_enable_device_mem(pdev))
2194 goto probe_out;
2195 } else {
2196 if (pci_enable_device(pdev))
2197 goto probe_out;
2198 }
285d0321 2199
0927678f
JB		 2200 /* This may fail but that's ok */
2201 pci_enable_pcie_error_reporting(pdev);
285d0321 2202
e315cd28
AC		 2203 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2204 if (!ha) {
7c3df132
SK		 2205 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2206 "Unable to allocate memory for ha.\n");
e315cd28 2207 goto probe_out;
1da177e4 2208 }
7c3df132
SK		 2209 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2210 "Memory allocated for ha=%p.\n", ha);
e315cd28 2211 ha->pdev = pdev;
2d70c103 2212 ha->tgt.enable_class_2 = ql2xenableclass2;
1da177e4
LT		 2213
2214 /* Clear our data area */
285d0321 2215 ha->bars = bars;
09483916 2216 ha->mem_only = mem_only;
df4bf0bb 2217 spin_lock_init(&ha->hardware_lock);
339aa70e 2218 spin_lock_init(&ha->vport_slock);
a9b6f722 2219 mutex_init(&ha->selflogin_lock);
1da177e4 2220
ea5b6382 2221 /* Set ISP-type information. */
2222 qla2x00_set_isp_flags(ha);
ca79cf66
DG		 2223
2224 /* Set EEH reset type to fundamental if required by hba */
95676112
JC		 2225 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
2226 IS_QLA83XX(ha))
ca79cf66 2227 pdev->needs_freset = 1;
ca79cf66 2228
cba1e47f
CD		 2229 ha->prev_topology = 0;
2230 ha->init_cb_size = sizeof(init_cb_t);
2231 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2232 ha->optrom_size = OPTROM_SIZE_2300;
2233
abbd8870 2234 /* Assign ISP specific operations. */
1da177e4 2235 if (IS_QLA2100(ha)) {
642ef983 2236 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2237 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
e315cd28
AC		 2238 req_length = REQUEST_ENTRY_CNT_2100;
2239 rsp_length = RESPONSE_ENTRY_CNT_2100;
2240 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2241 ha->gid_list_info_size = 4;
3a03eb79
AV		 2242 ha->flash_conf_off = ~0;
2243 ha->flash_data_off = ~0;
2244 ha->nvram_conf_off = ~0;
2245 ha->nvram_data_off = ~0;
fd34f556 2246 ha->isp_ops = &qla2100_isp_ops;
1da177e4 2247 } else if (IS_QLA2200(ha)) {
642ef983 2248 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
67ddda35 2249 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
e315cd28
AC		 2250 req_length = REQUEST_ENTRY_CNT_2200;
2251 rsp_length = RESPONSE_ENTRY_CNT_2100;
2252 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2253 ha->gid_list_info_size = 4;
3a03eb79
AV		 2254 ha->flash_conf_off = ~0;
2255 ha->flash_data_off = ~0;
2256 ha->nvram_conf_off = ~0;
2257 ha->nvram_data_off = ~0;
fd34f556 2258 ha->isp_ops = &qla2100_isp_ops;
fca29703 2259 } else if (IS_QLA23XX(ha)) {
642ef983 2260 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2261 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2262 req_length = REQUEST_ENTRY_CNT_2200;
2263 rsp_length = RESPONSE_ENTRY_CNT_2300;
2264 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
abbd8870 2265 ha->gid_list_info_size = 6;
854165f4 2266 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2267 ha->optrom_size = OPTROM_SIZE_2322;
3a03eb79
AV		 2268 ha->flash_conf_off = ~0;
2269 ha->flash_data_off = ~0;
2270 ha->nvram_conf_off = ~0;
2271 ha->nvram_data_off = ~0;
fd34f556 2272 ha->isp_ops = &qla2300_isp_ops;
4d4df193 2273 } else if (IS_QLA24XX_TYPE(ha)) {
642ef983 2274 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
fca29703 2275 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2276 req_length = REQUEST_ENTRY_CNT_24XX;
2277 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2278 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2279 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2c3dfe3f 2280 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
fca29703 2281 ha->gid_list_info_size = 8;
854165f4 2282 ha->optrom_size = OPTROM_SIZE_24XX;
73208dfd 2283 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
fd34f556 2284 ha->isp_ops = &qla24xx_isp_ops;
3a03eb79
AV		 2285 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2286 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2287 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2288 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
c3a2f0df 2289 } else if (IS_QLA25XX(ha)) {
642ef983 2290 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
c3a2f0df 2291 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2292 req_length = REQUEST_ENTRY_CNT_24XX;
2293 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2294 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2295 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
c3a2f0df 2296 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
c3a2f0df
AV		 2297 ha->gid_list_info_size = 8;
2298 ha->optrom_size = OPTROM_SIZE_25XX;
73208dfd 2299 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
c3a2f0df 2300 ha->isp_ops = &qla25xx_isp_ops;
3a03eb79
AV		 2301 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2302 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2303 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2304 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2305 } else if (IS_QLA81XX(ha)) {
642ef983 2306 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3a03eb79
AV		 2307 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2308 req_length = REQUEST_ENTRY_CNT_24XX;
2309 rsp_length = RESPONSE_ENTRY_CNT_2300;
2310 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2311 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2312 ha->gid_list_info_size = 8;
2313 ha->optrom_size = OPTROM_SIZE_81XX;
40859ae5 2314 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3a03eb79
AV		 2315 ha->isp_ops = &qla81xx_isp_ops;
2316 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2317 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2318 ha->nvram_conf_off = ~0;
2319 ha->nvram_data_off = ~0;
a9083016 2320 } else if (IS_QLA82XX(ha)) {
642ef983 2321 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
a9083016
GM		 2322 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2323 req_length = REQUEST_ENTRY_CNT_82XX;
2324 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2325 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2326 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2327 ha->gid_list_info_size = 8;
2328 ha->optrom_size = OPTROM_SIZE_82XX;
087c621e 2329 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
a9083016
GM		 2330 ha->isp_ops = &qla82xx_isp_ops;
2331 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2332 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2333 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2334 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
6246b8a1 2335 } else if (IS_QLA83XX(ha)) {
7d613ac6 2336 ha->portnum = PCI_FUNC(ha->pdev->devfn);
642ef983 2337 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
6246b8a1
GM		 2338 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2339 req_length = REQUEST_ENTRY_CNT_24XX;
2340 rsp_length = RESPONSE_ENTRY_CNT_2300;
2341 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2342 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2343 ha->gid_list_info_size = 8;
2344 ha->optrom_size = OPTROM_SIZE_83XX;
2345 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2346 ha->isp_ops = &qla83xx_isp_ops;
2347 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2348 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2349 ha->nvram_conf_off = ~0;
2350 ha->nvram_data_off = ~0;
1da177e4 2351 }
6246b8a1 2352
7c3df132
SK		 2353 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2354 "mbx_count=%d, req_length=%d, "
2355 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
642ef983
CD		 2356 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
2357 "max_fibre_devices=%d.\n",
7c3df132
SK		 2358 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2359 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
642ef983 2360 ha->nvram_npiv_size, ha->max_fibre_devices);
7c3df132
SK		 2361 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2362 "isp_ops=%p, flash_conf_off=%d, "
2363 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2364 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2365 ha->nvram_conf_off, ha->nvram_data_off);
706f457d
GM		 2366
2367 /* Configure PCI I/O space */
2368 ret = ha->isp_ops->iospace_config(ha);
2369 if (ret)
0a63ad12 2370 goto iospace_config_failed;
706f457d
GM		 2371
2372 ql_log_pci(ql_log_info, pdev, 0x001d,
2373 "Found an ISP%04X irq %d iobase 0x%p.\n",
2374 pdev->device, pdev->irq, ha->iobase);
6c2f527c 2375 mutex_init(&ha->vport_lock);
0b05a1f0
MB		 2376 init_completion(&ha->mbx_cmd_comp);
2377 complete(&ha->mbx_cmd_comp);
2378 init_completion(&ha->mbx_intr_comp);
23f2ebd1 2379 init_completion(&ha->dcbx_comp);
1da177e4 2380
2c3dfe3f 2381 set_bit(0, (unsigned long *) ha->vp_idx_map);
1da177e4 2382
53303c42 2383 qla2x00_config_dma_addressing(ha);
7c3df132
SK		 2384 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
2385 "64 Bit addressing is %s.\n",
2386 ha->flags.enable_64bit_addressing ? "enable" :
2387 "disable");
73208dfd 2388 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
e315cd28 2389 if (!ret) {
7c3df132
SK		 2390 ql_log_pci(ql_log_fatal, pdev, 0x0031,
2391 "Failed to allocate memory for adapter, aborting.\n");
1da177e4 2392
e315cd28
AC		 2393 goto probe_hw_failed;
2394 }
2395
73208dfd 2396 req->max_q_depth = MAX_Q_DEPTH;
e315cd28 2397 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
73208dfd
AC		 2398 req->max_q_depth = ql2xmaxqdepth;
2399
e315cd28
AC		 2400
2401 base_vha = qla2x00_create_host(sht, ha);
2402 if (!base_vha) {
a1541d5a 2403 ret = -ENOMEM;
6e9f21f3 2404 qla2x00_mem_free(ha);
2afa19a9
AC		 2405 qla2x00_free_req_que(ha, req);
2406 qla2x00_free_rsp_que(ha, rsp);
e315cd28 2407 goto probe_hw_failed;
1da177e4
LT		 2408 }
2409
e315cd28
AC		 2410 pci_set_drvdata(pdev, base_vha);
2411
e315cd28 2412 host = base_vha->host;
2afa19a9 2413 base_vha->req = req;
73208dfd
AC		 2414 host->can_queue = req->length + 128;
2415 if (IS_QLA2XXX_MIDTYPE(ha))
e315cd28 2416 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
73208dfd 2417 else
e315cd28
AC		 2418 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
2419 base_vha->vp_idx;
58548cb5
GM		 2420
2421 /* Set the SG table size based on ISP type */
2422 if (!IS_FWI2_CAPABLE(ha)) {
2423 if (IS_QLA2100(ha))
2424 host->sg_tablesize = 32;
2425 } else {
2426 if (!IS_QLA82XX(ha))
2427 host->sg_tablesize = QLA_SG_ALL;
2428 }
7c3df132
SK		 2429 ql_dbg(ql_dbg_init, base_vha, 0x0032,
2430 "can_queue=%d, req=%p, "
2431 "mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
2432 host->can_queue, base_vha->req,
2433 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
642ef983 2434 host->max_id = ha->max_fibre_devices;
e315cd28
AC		 2435 host->cmd_per_lun = 3;
2436 host->unique_id = host->host_no;
e02587d7 2437 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
0c470874
AE		 2438 host->max_cmd_len = 32;
2439 else
2440 host->max_cmd_len = MAX_CMDSZ;
e315cd28 2441 host->max_channel = MAX_BUSES - 1;
82515920 2442 host->max_lun = ql2xmaxlun;
e315cd28 2443 host->transportt = qla2xxx_transport_template;
9a069e19 2444 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
e315cd28 2445
7c3df132
SK		 2446 ql_dbg(ql_dbg_init, base_vha, 0x0033,
2447 "max_id=%d this_id=%d "
2448 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
d8424f68 2449 "max_lun=%d transportt=%p, vendor_id=%llu.\n", host->max_id,
7c3df132
SK		 2450 host->this_id, host->cmd_per_lun, host->unique_id,
2451 host->max_cmd_len, host->max_channel, host->max_lun,
2452 host->transportt, sht->vendor_id);
2453
9a347ff4
CD		 2454que_init:
2455 /* Alloc arrays of request and response ring ptrs */
2456 if (!qla2x00_alloc_queues(ha, req, rsp)) {
2457 ql_log(ql_log_fatal, base_vha, 0x003d,
2458 "Failed to allocate memory for queue pointers..."
2459 "aborting.\n");
2460 goto probe_init_failed;
2461 }
2462
2d70c103 2463 qlt_probe_one_stage1(base_vha, ha);
9a347ff4 2464
73208dfd
AC		 2465 /* Set up the irqs */
2466 ret = qla2x00_request_irqs(ha, rsp);
2467 if (ret)
6e9f21f3 2468 goto probe_init_failed;
90a86fc0
JC		 2469
2470 pci_save_state(pdev);
2471
9a347ff4 2472 /* Assign back pointers */
2afa19a9
AC		 2473 rsp->req = req;
2474 req->rsp = rsp;
9a347ff4 2475
08029990
AV		 2476 /* FWI2-capable only. */
2477 req->req_q_in = &ha->iobase->isp24.req_q_in;
2478 req->req_q_out = &ha->iobase->isp24.req_q_out;
2479 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
2480 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
6246b8a1 2481 if (ha->mqenable || IS_QLA83XX(ha)) {
08029990
AV		 2482 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
2483 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
2484 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
2485 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
17d98630
AC		 2486 }
2487
a9083016
GM		 2488 if (IS_QLA82XX(ha)) {
2489 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
2490 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
2491 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
2492 }
2493
7c3df132
SK		 2494 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
2495 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2496 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2497 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
2498 "req->req_q_in=%p req->req_q_out=%p "
2499 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2500 req->req_q_in, req->req_q_out,
2501 rsp->rsp_q_in, rsp->rsp_q_out);
2502 ql_dbg(ql_dbg_init, base_vha, 0x003e,
2503 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2504 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2505 ql_dbg(ql_dbg_init, base_vha, 0x003f,
2506 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2507 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
1da177e4 2508
7c3df132
SK		 2509 if (qla2x00_initialize_adapter(base_vha)) {
2510 ql_log(ql_log_fatal, base_vha, 0x00d6,
2511 "Failed to initialize adapter - Adapter flags %x.\n",
2512 base_vha->device_flags);
1da177e4 2513
a9083016
GM		 2514 if (IS_QLA82XX(ha)) {
2515 qla82xx_idc_lock(ha);
2516 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 2517 QLA8XXX_DEV_FAILED);
a9083016 2518 qla82xx_idc_unlock(ha);
7c3df132
SK		 2519 ql_log(ql_log_fatal, base_vha, 0x00d7,
2520 "HW State: FAILED.\n");
a9083016
GM		 2521 }
2522
a1541d5a 2523 ret = -ENODEV;
1da177e4
LT		 2524 goto probe_failed;
2525 }
2526
7163ea81
AC		 2527 if (ha->mqenable) {
2528 if (qla25xx_setup_mode(base_vha)) {
7c3df132
SK		 2529 ql_log(ql_log_warn, base_vha, 0x00ec,
2530 "Failed to create queues, falling back to single queue mode.\n");
7163ea81
AC		 2531 goto que_init;
2532 }
2533 }
68ca949c 2534
cbc8eb67
AV		 2535 if (ha->flags.running_gold_fw)
2536 goto skip_dpc;
2537
1da177e4
LT		 2538 /*
2539 * Startup the kernel thread for this host adapter
2540 */
39a11240 2541 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
7c3df132 2542 "%s_dpc", base_vha->host_str);
39a11240 2543 if (IS_ERR(ha->dpc_thread)) {
7c3df132
SK		 2544 ql_log(ql_log_fatal, base_vha, 0x00ed,
2545 "Failed to start DPC thread.\n");
39a11240 2546 ret = PTR_ERR(ha->dpc_thread);
1da177e4
LT		 2547 goto probe_failed;
2548 }
7c3df132
SK		 2549 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
2550 "DPC thread started successfully.\n");
1da177e4 2551
2d70c103
NB		 2552 /*
2553 * If we're not coming up in initiator mode, we might sit for
2554 * a while without waking up the dpc thread, which leads to a
2555 * stuck process warning. So just kick the dpc once here and
2556 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
2557 */
2558 qla2xxx_wake_dpc(base_vha);
2559
81178772
SK		 2560 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
2561 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
2562 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
2563 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
2564
2565 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
2566 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
2567 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
2568 INIT_WORK(&ha->idc_state_handler,
2569 qla83xx_idc_state_handler_work);
2570 INIT_WORK(&ha->nic_core_unrecoverable,
2571 qla83xx_nic_core_unrecoverable_work);
2572 }
2573
cbc8eb67 2574skip_dpc:
e315cd28
AC		 2575 list_add_tail(&base_vha->list, &ha->vp_list);
2576 base_vha->host->irq = ha->pdev->irq;
1da177e4
LT		 2577
2578 /* Initialized the timer */
e315cd28 2579 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
7c3df132
SK		 2580 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
2581 "Started qla2x00_timer with "
2582 "interval=%d.\n", WATCH_INTERVAL);
2583 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
2584 "Detected hba at address=%p.\n",
2585 ha);
d19044c3 2586
e02587d7 2587 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
bad75002 2588 if (ha->fw_attributes & BIT_4) {
9e522cd8 2589 int prot = 0, guard;
bad75002 2590 base_vha->flags.difdix_supported = 1;
7c3df132
SK		 2591 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
2592 "Registering for DIF/DIX type 1 and 3 protection.\n");
8cb2049c
AE		 2593 if (ql2xenabledif == 1)
2594 prot = SHOST_DIX_TYPE0_PROTECTION;
bad75002 2595 scsi_host_set_prot(host,
8cb2049c 2596 prot | SHOST_DIF_TYPE1_PROTECTION
0c470874 2597 | SHOST_DIF_TYPE2_PROTECTION
bad75002
AE		 2598 | SHOST_DIF_TYPE3_PROTECTION
2599 | SHOST_DIX_TYPE1_PROTECTION
0c470874 2600 | SHOST_DIX_TYPE2_PROTECTION
bad75002 2601 | SHOST_DIX_TYPE3_PROTECTION);
9e522cd8
AE		 2602
2603 guard = SHOST_DIX_GUARD_CRC;
2604
2605 if (IS_PI_IPGUARD_CAPABLE(ha) &&
2606 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
2607 guard |= SHOST_DIX_GUARD_IP;
2608
2609 scsi_host_set_guard(host, guard);
bad75002
AE		 2610 } else
2611 base_vha->flags.difdix_supported = 0;
2612 }
2613
a9083016
GM		 2614 ha->isp_ops->enable_intrs(ha);
2615
a1541d5a
AV		 2616 ret = scsi_add_host(host, &pdev->dev);
2617 if (ret)
2618 goto probe_failed;
2619
1486400f
MR		 2620 base_vha->flags.init_done = 1;
2621 base_vha->flags.online = 1;
2622
7c3df132
SK		 2623 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
2624 "Init done and hba is online.\n");
2625
2d70c103
NB		 2626 if (qla_ini_mode_enabled(base_vha))
2627 scsi_scan_host(host);
2628 else
2629 ql_dbg(ql_dbg_init, base_vha, 0x0122,
2630 "skipping scsi_scan_host() for non-initiator port\n");
1e99e33a 2631
e315cd28 2632 qla2x00_alloc_sysfs_attr(base_vha);
a1541d5a 2633
e315cd28 2634 qla2x00_init_host_attr(base_vha);
a1541d5a 2635
e315cd28 2636 qla2x00_dfs_setup(base_vha);
df613b96 2637
7c3df132
SK		 2638 ql_log(ql_log_info, base_vha, 0x00fb,
2639 "QLogic %s - %s.\n",
2640 ha->model_number, ha->model_desc ? ha->model_desc : "");
2641 ql_log(ql_log_info, base_vha, 0x00fc,
2642 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
2643 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
2644 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
2645 base_vha->host_no,
e315cd28 2646 ha->isp_ops->fw_version_str(base_vha, fw_str));
1da177e4 2647
2d70c103
NB		 2648 qlt_add_target(ha, base_vha);
2649
1da177e4
LT		 2650 return 0;
2651
6e9f21f3 2652probe_init_failed:
2afa19a9 2653 qla2x00_free_req_que(ha, req);
9a347ff4
CD		 2654 ha->req_q_map[0] = NULL;
2655 clear_bit(0, ha->req_qid_map);
2afa19a9 2656 qla2x00_free_rsp_que(ha, rsp);
9a347ff4
CD		 2657 ha->rsp_q_map[0] = NULL;
2658 clear_bit(0, ha->rsp_qid_map);
2afa19a9 2659 ha->max_req_queues = ha->max_rsp_queues = 0;
6e9f21f3 2660
1da177e4 2661probe_failed:
b9978769
AV		 2662 if (base_vha->timer_active)
2663 qla2x00_stop_timer(base_vha);
2664 base_vha->flags.online = 0;
2665 if (ha->dpc_thread) {
2666 struct task_struct *t = ha->dpc_thread;
2667
2668 ha->dpc_thread = NULL;
2669 kthread_stop(t);
2670 }
2671
e315cd28 2672 qla2x00_free_device(base_vha);
1da177e4 2673
e315cd28 2674 scsi_host_put(base_vha->host);
1da177e4 2675
e315cd28 2676probe_hw_failed:
a9083016
GM		 2677 if (IS_QLA82XX(ha)) {
2678 qla82xx_idc_lock(ha);
2679 qla82xx_clear_drv_active(ha);
2680 qla82xx_idc_unlock(ha);
0a63ad12
SK		 2681 }
2682iospace_config_failed:
2683 if (IS_QLA82XX(ha)) {
2684 if (!ha->nx_pcibase)
2685 iounmap((device_reg_t __iomem *)ha->nx_pcibase);
a9083016
GM		 2686 if (!ql2xdbwr)
2687 iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr);
2688 } else {
2689 if (ha->iobase)
2690 iounmap(ha->iobase);
2691 }
e315cd28
AC		 2692 pci_release_selected_regions(ha->pdev, ha->bars);
2693 kfree(ha);
2694 ha = NULL;
1da177e4 2695
a1541d5a 2696probe_out:
e315cd28 2697 pci_disable_device(pdev);
a1541d5a 2698 return ret;
1da177e4 2699}
1da177e4 2700
2d70c103
NB		 2701static void
2702qla2x00_stop_dpc_thread(scsi_qla_host_t *vha)
2703{
2704 struct qla_hw_data *ha = vha->hw;
2705 struct task_struct *t = ha->dpc_thread;
2706
2707 if (ha->dpc_thread == NULL)
2708 return;
2709 /*
2710 * qla2xxx_wake_dpc checks for ->dpc_thread
2711 * so we need to zero it out.
2712 */
2713 ha->dpc_thread = NULL;
2714 kthread_stop(t);
2715}
2716
e30d1756
MI		 2717static void
2718qla2x00_shutdown(struct pci_dev *pdev)
2719{
2720 scsi_qla_host_t *vha;
2721 struct qla_hw_data *ha;
2722
2723 vha = pci_get_drvdata(pdev);
2724 ha = vha->hw;
2725
2726 /* Turn-off FCE trace */
2727 if (ha->flags.fce_enabled) {
2728 qla2x00_disable_fce_trace(vha, NULL, NULL);
2729 ha->flags.fce_enabled = 0;
2730 }
2731
2732 /* Turn-off EFT trace */
2733 if (ha->eft)
2734 qla2x00_disable_eft_trace(vha);
2735
2736 /* Stop currently executing firmware. */
2737 qla2x00_try_to_stop_firmware(vha);
2738
2739 /* Turn adapter off line */
2740 vha->flags.online = 0;
2741
2742 /* turn-off interrupts on the card */
2743 if (ha->interrupts_on) {
2744 vha->flags.init_done = 0;
2745 ha->isp_ops->disable_intrs(ha);
2746 }
2747
2748 qla2x00_free_irqs(vha);
2749
2750 qla2x00_free_fw_dump(ha);
2751}
2752
4c993f76 2753static void
7ee61397 2754qla2x00_remove_one(struct pci_dev *pdev)
1da177e4 2755{
feafb7b1 2756 scsi_qla_host_t *base_vha, *vha;
e315cd28 2757 struct qla_hw_data *ha;
feafb7b1 2758 unsigned long flags;
e315cd28 2759
9a347ff4
CD		 2760 /*
2761 * If the PCI device is disabled that means that probe failed and any
2762 * resources should be have cleaned up on probe exit.
2763 */
2764 if (!atomic_read(&pdev->enable_cnt))
2765 return;
2766
e315cd28
AC		 2767 base_vha = pci_get_drvdata(pdev);
2768 ha = base_vha->hw;
2769
2d70c103
NB		 2770 ha->flags.host_shutting_down = 1;
2771
220d36b4 2772 set_bit(UNLOADING, &base_vha->dpc_flags);
43ebf16d
AE		 2773 mutex_lock(&ha->vport_lock);
2774 while (ha->cur_vport_count) {
2775 struct Scsi_Host *scsi_host;
feafb7b1 2776
43ebf16d 2777 spin_lock_irqsave(&ha->vport_slock, flags);
feafb7b1 2778
43ebf16d
AE		 2779 BUG_ON(base_vha->list.next == &ha->vp_list);
2780 /* This assumes first entry in ha->vp_list is always base vha */
2781 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
2782 scsi_host = scsi_host_get(vha->host);
feafb7b1 2783
43ebf16d
AE		 2784 spin_unlock_irqrestore(&ha->vport_slock, flags);
2785 mutex_unlock(&ha->vport_lock);
2786
2787 fc_vport_terminate(vha->fc_vport);
2788 scsi_host_put(vha->host);
feafb7b1 2789
43ebf16d 2790 mutex_lock(&ha->vport_lock);
e315cd28 2791 }
43ebf16d 2792 mutex_unlock(&ha->vport_lock);
1da177e4 2793
7d613ac6
SV		 2794 if (IS_QLA8031(ha)) {
2795 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
2796 "Clearing fcoe driver presence.\n");
2797 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
2798 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
2799 "Error while clearing DRV-Presence.\n");
2800 }
2801
b9978769
AV		 2802 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
2803
e315cd28 2804 qla2x00_dfs_remove(base_vha);
c795c1e4 2805
e315cd28 2806 qla84xx_put_chip(base_vha);
c795c1e4 2807
b9978769
AV		 2808 /* Disable timer */
2809 if (base_vha->timer_active)
2810 qla2x00_stop_timer(base_vha);
2811
2812 base_vha->flags.online = 0;
2813
68ca949c
AC		 2814 /* Flush the work queue and remove it */
2815 if (ha->wq) {
2816 flush_workqueue(ha->wq);
2817 destroy_workqueue(ha->wq);
2818 ha->wq = NULL;
2819 }
2820
7d613ac6
SV		 2821 /* Cancel all work and destroy DPC workqueues */
2822 if (ha->dpc_lp_wq) {
2823 cancel_work_sync(&ha->idc_aen);
2824 destroy_workqueue(ha->dpc_lp_wq);
2825 ha->dpc_lp_wq = NULL;
2826 }
2827
2828 if (ha->dpc_hp_wq) {
2829 cancel_work_sync(&ha->nic_core_reset);
2830 cancel_work_sync(&ha->idc_state_handler);
2831 cancel_work_sync(&ha->nic_core_unrecoverable);
2832 destroy_workqueue(ha->dpc_hp_wq);
2833 ha->dpc_hp_wq = NULL;
2834 }
2835
b9978769
AV		 2836 /* Kill the kernel thread for this host */
2837 if (ha->dpc_thread) {
2838 struct task_struct *t = ha->dpc_thread;
2839
2840 /*
2841 * qla2xxx_wake_dpc checks for ->dpc_thread
2842 * so we need to zero it out.
2843 */
2844 ha->dpc_thread = NULL;
2845 kthread_stop(t);
2846 }
2d70c103 2847 qlt_remove_target(ha, base_vha);
b9978769 2848
e315cd28 2849 qla2x00_free_sysfs_attr(base_vha);
df613b96 2850
e315cd28 2851 fc_remove_host(base_vha->host);
4d4df193 2852
e315cd28 2853 scsi_remove_host(base_vha->host);
1da177e4 2854
e315cd28 2855 qla2x00_free_device(base_vha);
bdf79621 2856
e315cd28 2857 scsi_host_put(base_vha->host);
1da177e4 2858
a9083016 2859 if (IS_QLA82XX(ha)) {
b963752f
GM		 2860 qla82xx_idc_lock(ha);
2861 qla82xx_clear_drv_active(ha);
2862 qla82xx_idc_unlock(ha);
2863
a9083016
GM		 2864 iounmap((device_reg_t __iomem *)ha->nx_pcibase);
2865 if (!ql2xdbwr)
2866 iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr);
2867 } else {
2868 if (ha->iobase)
2869 iounmap(ha->iobase);
1da177e4 2870
a9083016
GM		 2871 if (ha->mqiobase)
2872 iounmap(ha->mqiobase);
6246b8a1
GM		 2873
2874 if (IS_QLA83XX(ha) && ha->msixbase)
2875 iounmap(ha->msixbase);
a9083016 2876 }
73208dfd 2877
e315cd28
AC		 2878 pci_release_selected_regions(ha->pdev, ha->bars);
2879 kfree(ha);
2880 ha = NULL;
1da177e4 2881
90a86fc0
JC		 2882 pci_disable_pcie_error_reporting(pdev);
2883
665db93b 2884 pci_disable_device(pdev);
1da177e4
LT		 2885 pci_set_drvdata(pdev, NULL);
2886}
1da177e4
LT		 2887
2888static void
e315cd28 2889qla2x00_free_device(scsi_qla_host_t *vha)
1da177e4 2890{
e315cd28 2891 struct qla_hw_data *ha = vha->hw;
1da177e4 2892
85880801
AV		 2893 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
2894
2895 /* Disable timer */
2896 if (vha->timer_active)
2897 qla2x00_stop_timer(vha);
2898
2d70c103 2899 qla2x00_stop_dpc_thread(vha);
85880801 2900
2afa19a9 2901 qla25xx_delete_queues(vha);
df613b96 2902 if (ha->flags.fce_enabled)
e315cd28 2903 qla2x00_disable_fce_trace(vha, NULL, NULL);
df613b96 2904
a7a167bf 2905 if (ha->eft)
e315cd28 2906 qla2x00_disable_eft_trace(vha);
a7a167bf 2907
f6ef3b18 2908 /* Stop currently executing firmware. */
e315cd28 2909 qla2x00_try_to_stop_firmware(vha);
1da177e4 2910
85880801
AV		 2911 vha->flags.online = 0;
2912
f6ef3b18 2913 /* turn-off interrupts on the card */
a9083016
GM		 2914 if (ha->interrupts_on) {
2915 vha->flags.init_done = 0;
fd34f556 2916 ha->isp_ops->disable_intrs(ha);
a9083016 2917 }
f6ef3b18 2918
e315cd28 2919 qla2x00_free_irqs(vha);
1da177e4 2920
8867048b
CD		 2921 qla2x00_free_fcports(vha);
2922
e315cd28 2923 qla2x00_mem_free(ha);
73208dfd 2924
08de2844
GM		 2925 qla82xx_md_free(vha);
2926
73208dfd 2927 qla2x00_free_queues(ha);
1da177e4
LT		 2928}
2929
8867048b
CD		 2930void qla2x00_free_fcports(struct scsi_qla_host *vha)
2931{
2932 fc_port_t *fcport, *tfcport;
2933
2934 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
2935 list_del(&fcport->list);
5f16b331 2936 qla2x00_clear_loop_id(fcport);
8867048b
CD		 2937 kfree(fcport);
2938 fcport = NULL;
2939 }
2940}
2941
d97994dc 2942static inline void
e315cd28 2943qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
d97994dc 2944 int defer)
2945{
d97994dc 2946 struct fc_rport *rport;
67becc00 2947 scsi_qla_host_t *base_vha;
044d78e1 2948 unsigned long flags;
d97994dc 2949
2950 if (!fcport->rport)
2951 return;
2952
2953 rport = fcport->rport;
2954 if (defer) {
67becc00 2955 base_vha = pci_get_drvdata(vha->hw->pdev);
044d78e1 2956 spin_lock_irqsave(vha->host->host_lock, flags);
d97994dc 2957 fcport->drport = rport;
044d78e1 2958 spin_unlock_irqrestore(vha->host->host_lock, flags);
67becc00
AV		 2959 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
2960 qla2xxx_wake_dpc(base_vha);
2d70c103 2961 } else {
d97994dc 2962 fc_remote_port_delete(rport);
2d70c103
NB		 2963 qlt_fc_port_deleted(vha, fcport);
2964 }
d97994dc 2965}
2966
1da177e4
LT		 2967/*
2968 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
2969 *
2970 * Input: ha = adapter block pointer. fcport = port structure pointer.
2971 *
2972 * Return: None.
2973 *
2974 * Context:
2975 */
e315cd28 2976void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
d97994dc 2977 int do_login, int defer)
1da177e4 2978{
2c3dfe3f 2979 if (atomic_read(&fcport->state) == FCS_ONLINE &&
c6d39e23 2980 vha->vp_idx == fcport->vha->vp_idx) {
ec426e10 2981 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
e315cd28
AC		 2982 qla2x00_schedule_rport_del(vha, fcport, defer);
2983 }
fa2a1ce5 2984 /*
1da177e4
LT		 2985 * We may need to retry the login, so don't change the state of the
2986 * port but do the retries.
2987 */
2988 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
ec426e10 2989 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 2990
2991 if (!do_login)
2992 return;
2993
2994 if (fcport->login_retry == 0) {
e315cd28
AC		 2995 fcport->login_retry = vha->hw->login_retry_count;
2996 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1da177e4 2997
7c3df132
SK		 2998 ql_dbg(ql_dbg_disc, vha, 0x2067,
2999 "Port login retry "
1da177e4 3000 "%02x%02x%02x%02x%02x%02x%02x%02x, "
7c3df132
SK		 3001 "id = 0x%04x retry cnt=%d.\n",
3002 fcport->port_name[0], fcport->port_name[1],
3003 fcport->port_name[2], fcport->port_name[3],
3004 fcport->port_name[4], fcport->port_name[5],
3005 fcport->port_name[6], fcport->port_name[7],
3006 fcport->loop_id, fcport->login_retry);
1da177e4
LT		 3007 }
3008}
3009
3010/*
3011 * qla2x00_mark_all_devices_lost
3012 * Updates fcport state when device goes offline.
3013 *
3014 * Input:
3015 * ha = adapter block pointer.
3016 * fcport = port structure pointer.
3017 *
3018 * Return:
3019 * None.
3020 *
3021 * Context:
3022 */
3023void
e315cd28 3024qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
1da177e4
LT		 3025{
3026 fc_port_t *fcport;
3027
e315cd28 3028 list_for_each_entry(fcport, &vha->vp_fcports, list) {
c6d39e23 3029 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
1da177e4 3030 continue;
0d6e61bc 3031
1da177e4
LT		 3032 /*
3033 * No point in marking the device as lost, if the device is
3034 * already DEAD.
3035 */
3036 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3037 continue;
e315cd28 3038 if (atomic_read(&fcport->state) == FCS_ONLINE) {
ec426e10 3039 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
0d6e61bc
AV		 3040 if (defer)
3041 qla2x00_schedule_rport_del(vha, fcport, defer);
c6d39e23 3042 else if (vha->vp_idx == fcport->vha->vp_idx)
0d6e61bc
AV		 3043 qla2x00_schedule_rport_del(vha, fcport, defer);
3044 }
1da177e4
LT		 3045 }
3046}
3047
3048/*
3049* qla2x00_mem_alloc
3050* Allocates adapter memory.
3051*
3052* Returns:
3053* 0 = success.
e8711085 3054* !0 = failure.
1da177e4 3055*/
e8711085 3056static int
73208dfd
AC		 3057qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3058 struct req_que **req, struct rsp_que **rsp)
1da177e4
LT		 3059{
3060 char name[16];
1da177e4 3061
e8711085 3062 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
e315cd28 3063 &ha->init_cb_dma, GFP_KERNEL);
e8711085 3064 if (!ha->init_cb)
e315cd28 3065 goto fail;
e8711085 3066
2d70c103
NB		 3067 if (qlt_mem_alloc(ha) < 0)
3068 goto fail_free_init_cb;
3069
642ef983
CD		 3070 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3071 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
e315cd28 3072 if (!ha->gid_list)
2d70c103 3073 goto fail_free_tgt_mem;
1da177e4 3074
e8711085
AV		 3075 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3076 if (!ha->srb_mempool)
e315cd28 3077 goto fail_free_gid_list;
e8711085 3078
a9083016
GM		 3079 if (IS_QLA82XX(ha)) {
3080 /* Allocate cache for CT6 Ctx. */
3081 if (!ctx_cachep) {
3082 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
3083 sizeof(struct ct6_dsd), 0,
3084 SLAB_HWCACHE_ALIGN, NULL);
3085 if (!ctx_cachep)
3086 goto fail_free_gid_list;
3087 }
3088 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
3089 ctx_cachep);
3090 if (!ha->ctx_mempool)
3091 goto fail_free_srb_mempool;
7c3df132
SK		 3092 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
3093 "ctx_cachep=%p ctx_mempool=%p.\n",
3094 ctx_cachep, ha->ctx_mempool);
a9083016
GM		 3095 }
3096
e8711085
AV		 3097 /* Get memory for cached NVRAM */
3098 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
3099 if (!ha->nvram)
a9083016 3100 goto fail_free_ctx_mempool;
e8711085 3101
e315cd28
AC		 3102 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
3103 ha->pdev->device);
3104 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3105 DMA_POOL_SIZE, 8, 0);
3106 if (!ha->s_dma_pool)
3107 goto fail_free_nvram;
3108
7c3df132
SK		 3109 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
3110 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
3111 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
3112
bad75002 3113 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3114 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3115 DSD_LIST_DMA_POOL_SIZE, 8, 0);
3116 if (!ha->dl_dma_pool) {
7c3df132
SK		 3117 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
3118 "Failed to allocate memory for dl_dma_pool.\n");
a9083016
GM		 3119 goto fail_s_dma_pool;
3120 }
3121
3122 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3123 FCP_CMND_DMA_POOL_SIZE, 8, 0);
3124 if (!ha->fcp_cmnd_dma_pool) {
7c3df132
SK		 3125 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
3126 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
a9083016
GM		 3127 goto fail_dl_dma_pool;
3128 }
7c3df132
SK		 3129 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
3130 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
3131 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
a9083016
GM		 3132 }
3133
e8711085
AV		 3134 /* Allocate memory for SNS commands */
3135 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
e315cd28 3136 /* Get consistent memory allocated for SNS commands */
e8711085 3137 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3138 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
e8711085 3139 if (!ha->sns_cmd)
e315cd28 3140 goto fail_dma_pool;
7c3df132 3141 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
d8424f68 3142 "sns_cmd: %p.\n", ha->sns_cmd);
e8711085 3143 } else {
e315cd28 3144 /* Get consistent memory allocated for MS IOCB */
e8711085 3145 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
e315cd28 3146 &ha->ms_iocb_dma);
e8711085 3147 if (!ha->ms_iocb)
e315cd28
AC		 3148 goto fail_dma_pool;
3149 /* Get consistent memory allocated for CT SNS commands */
e8711085 3150 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3151 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
e8711085
AV		 3152 if (!ha->ct_sns)
3153 goto fail_free_ms_iocb;
7c3df132
SK		 3154 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
3155 "ms_iocb=%p ct_sns=%p.\n",
3156 ha->ms_iocb, ha->ct_sns);
1da177e4
LT		 3157 }
3158
e315cd28 3159 /* Allocate memory for request ring */
73208dfd
AC		 3160 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
3161 if (!*req) {
7c3df132
SK		 3162 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
3163 "Failed to allocate memory for req.\n");
e315cd28
AC		 3164 goto fail_req;
3165 }
73208dfd
AC		 3166 (*req)->length = req_len;
3167 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
3168 ((*req)->length + 1) * sizeof(request_t),
3169 &(*req)->dma, GFP_KERNEL);
3170 if (!(*req)->ring) {
7c3df132
SK		 3171 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
3172 "Failed to allocate memory for req_ring.\n");
e315cd28
AC		 3173 goto fail_req_ring;
3174 }
3175 /* Allocate memory for response ring */
73208dfd
AC		 3176 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
3177 if (!*rsp) {
7c3df132
SK		 3178 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
3179 "Failed to allocate memory for rsp.\n");
e315cd28
AC		 3180 goto fail_rsp;
3181 }
73208dfd
AC		 3182 (*rsp)->hw = ha;
3183 (*rsp)->length = rsp_len;
3184 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
3185 ((*rsp)->length + 1) * sizeof(response_t),
3186 &(*rsp)->dma, GFP_KERNEL);
3187 if (!(*rsp)->ring) {
7c3df132
SK		 3188 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
3189 "Failed to allocate memory for rsp_ring.\n");
e315cd28
AC		 3190 goto fail_rsp_ring;
3191 }
73208dfd
AC		 3192 (*req)->rsp = *rsp;
3193 (*rsp)->req = *req;
7c3df132
SK		 3194 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
3195 "req=%p req->length=%d req->ring=%p rsp=%p "
3196 "rsp->length=%d rsp->ring=%p.\n",
3197 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
3198 (*rsp)->ring);
73208dfd
AC		 3199 /* Allocate memory for NVRAM data for vports */
3200 if (ha->nvram_npiv_size) {
3201 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
7c3df132 3202 ha->nvram_npiv_size, GFP_KERNEL);
73208dfd 3203 if (!ha->npiv_info) {
7c3df132
SK		 3204 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
3205 "Failed to allocate memory for npiv_info.\n");
73208dfd
AC		 3206 goto fail_npiv_info;
3207 }
3208 } else
3209 ha->npiv_info = NULL;
e8711085 3210
b64b0e8f 3211 /* Get consistent memory allocated for EX-INIT-CB. */
6246b8a1 3212 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha)) {
b64b0e8f
AV		 3213 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3214 &ha->ex_init_cb_dma);
3215 if (!ha->ex_init_cb)
3216 goto fail_ex_init_cb;
7c3df132
SK		 3217 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
3218 "ex_init_cb=%p.\n", ha->ex_init_cb);
b64b0e8f
AV		 3219 }
3220
a9083016
GM		 3221 INIT_LIST_HEAD(&ha->gbl_dsd_list);
3222
5ff1d584
AV		 3223 /* Get consistent memory allocated for Async Port-Database. */
3224 if (!IS_FWI2_CAPABLE(ha)) {
3225 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3226 &ha->async_pd_dma);
3227 if (!ha->async_pd)
3228 goto fail_async_pd;
7c3df132
SK		 3229 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
3230 "async_pd=%p.\n", ha->async_pd);
5ff1d584
AV		 3231 }
3232
e315cd28 3233 INIT_LIST_HEAD(&ha->vp_list);
5f16b331
CD		 3234
3235 /* Allocate memory for our loop_id bitmap */
3236 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long),
3237 GFP_KERNEL);
3238 if (!ha->loop_id_map)
3239 goto fail_async_pd;
3240 else {
3241 qla2x00_set_reserved_loop_ids(ha);
3242 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
3243 "loop_id_map=%p. \n", ha->loop_id_map);
3244 }
3245
e315cd28
AC		 3246 return 1;
3247
5ff1d584
AV		 3248fail_async_pd:
3249 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f
AV		 3250fail_ex_init_cb:
3251 kfree(ha->npiv_info);
73208dfd
AC		 3252fail_npiv_info:
3253 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
3254 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
3255 (*rsp)->ring = NULL;
3256 (*rsp)->dma = 0;
e315cd28 3257fail_rsp_ring:
73208dfd 3258 kfree(*rsp);
e315cd28 3259fail_rsp:
73208dfd
AC		 3260 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
3261 sizeof(request_t), (*req)->ring, (*req)->dma);
3262 (*req)->ring = NULL;
3263 (*req)->dma = 0;
e315cd28 3264fail_req_ring:
73208dfd 3265 kfree(*req);
e315cd28
AC		 3266fail_req:
3267 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
3268 ha->ct_sns, ha->ct_sns_dma);
3269 ha->ct_sns = NULL;
3270 ha->ct_sns_dma = 0;
e8711085
AV		 3271fail_free_ms_iocb:
3272 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3273 ha->ms_iocb = NULL;
3274 ha->ms_iocb_dma = 0;
e315cd28 3275fail_dma_pool:
bad75002 3276 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3277 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3278 ha->fcp_cmnd_dma_pool = NULL;
3279 }
3280fail_dl_dma_pool:
bad75002 3281 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3282 dma_pool_destroy(ha->dl_dma_pool);
3283 ha->dl_dma_pool = NULL;
3284 }
3285fail_s_dma_pool:
e315cd28
AC		 3286 dma_pool_destroy(ha->s_dma_pool);
3287 ha->s_dma_pool = NULL;
e8711085
AV		 3288fail_free_nvram:
3289 kfree(ha->nvram);
3290 ha->nvram = NULL;
a9083016
GM		 3291fail_free_ctx_mempool:
3292 mempool_destroy(ha->ctx_mempool);
3293 ha->ctx_mempool = NULL;
e8711085
AV		 3294fail_free_srb_mempool:
3295 mempool_destroy(ha->srb_mempool);
3296 ha->srb_mempool = NULL;
e8711085 3297fail_free_gid_list:
642ef983
CD		 3298 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3299 ha->gid_list,
e315cd28 3300 ha->gid_list_dma);
e8711085
AV		 3301 ha->gid_list = NULL;
3302 ha->gid_list_dma = 0;
2d70c103
NB		 3303fail_free_tgt_mem:
3304 qlt_mem_free(ha);
e315cd28
AC		 3305fail_free_init_cb:
3306 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
3307 ha->init_cb_dma);
3308 ha->init_cb = NULL;
3309 ha->init_cb_dma = 0;
e8711085 3310fail:
7c3df132
SK		 3311 ql_log(ql_log_fatal, NULL, 0x0030,
3312 "Memory allocation failure.\n");
e8711085 3313 return -ENOMEM;
1da177e4
LT		 3314}
3315
3316/*
e30d1756
MI		 3317* qla2x00_free_fw_dump
3318* Frees fw dump stuff.
1da177e4
LT		 3319*
3320* Input:
e30d1756 3321* ha = adapter block pointer.
1da177e4 3322*/
a824ebb3 3323static void
e30d1756 3324qla2x00_free_fw_dump(struct qla_hw_data *ha)
1da177e4 3325{
df613b96
AV		 3326 if (ha->fce)
3327 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
e30d1756 3328 ha->fce_dma);
df613b96 3329
a7a167bf
AV		 3330 if (ha->fw_dump) {
3331 if (ha->eft)
3332 dma_free_coherent(&ha->pdev->dev,
e30d1756 3333 ntohl(ha->fw_dump->eft_size), ha->eft, ha->eft_dma);
a7a167bf
AV		 3334 vfree(ha->fw_dump);
3335 }
e30d1756
MI		 3336 ha->fce = NULL;
3337 ha->fce_dma = 0;
3338 ha->eft = NULL;
3339 ha->eft_dma = 0;
3340 ha->fw_dump = NULL;
3341 ha->fw_dumped = 0;
3342 ha->fw_dump_reading = 0;
3343}
3344
3345/*
3346* qla2x00_mem_free
3347* Frees all adapter allocated memory.
3348*
3349* Input:
3350* ha = adapter block pointer.
3351*/
3352static void
3353qla2x00_mem_free(struct qla_hw_data *ha)
3354{
3355 qla2x00_free_fw_dump(ha);
3356
81178772
SK		 3357 if (ha->mctp_dump)
3358 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
3359 ha->mctp_dump_dma);
3360
e30d1756
MI		 3361 if (ha->srb_mempool)
3362 mempool_destroy(ha->srb_mempool);
a7a167bf 3363
11bbc1d8
AV		 3364 if (ha->dcbx_tlv)
3365 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
3366 ha->dcbx_tlv, ha->dcbx_tlv_dma);
3367
ce0423f4
AV		 3368 if (ha->xgmac_data)
3369 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
3370 ha->xgmac_data, ha->xgmac_data_dma);
3371
1da177e4
LT		 3372 if (ha->sns_cmd)
3373 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
e315cd28 3374 ha->sns_cmd, ha->sns_cmd_dma);
1da177e4
LT		 3375
3376 if (ha->ct_sns)
3377 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
e315cd28 3378 ha->ct_sns, ha->ct_sns_dma);
1da177e4 3379
88729e53
AV		 3380 if (ha->sfp_data)
3381 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
3382
1da177e4
LT		 3383 if (ha->ms_iocb)
3384 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3385
b64b0e8f 3386 if (ha->ex_init_cb)
a9083016
GM		 3387 dma_pool_free(ha->s_dma_pool,
3388 ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f 3389
5ff1d584
AV		 3390 if (ha->async_pd)
3391 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
3392
1da177e4
LT		 3393 if (ha->s_dma_pool)
3394 dma_pool_destroy(ha->s_dma_pool);
3395
1da177e4 3396 if (ha->gid_list)
642ef983
CD		 3397 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3398 ha->gid_list, ha->gid_list_dma);
1da177e4 3399
a9083016
GM		 3400 if (IS_QLA82XX(ha)) {
3401 if (!list_empty(&ha->gbl_dsd_list)) {
3402 struct dsd_dma *dsd_ptr, *tdsd_ptr;
3403
3404 /* clean up allocated prev pool */
3405 list_for_each_entry_safe(dsd_ptr,
3406 tdsd_ptr, &ha->gbl_dsd_list, list) {
3407 dma_pool_free(ha->dl_dma_pool,
3408 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
3409 list_del(&dsd_ptr->list);
3410 kfree(dsd_ptr);
3411 }
3412 }
3413 }
3414
3415 if (ha->dl_dma_pool)
3416 dma_pool_destroy(ha->dl_dma_pool);
3417
3418 if (ha->fcp_cmnd_dma_pool)
3419 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3420
3421 if (ha->ctx_mempool)
3422 mempool_destroy(ha->ctx_mempool);
3423
2d70c103
NB		 3424 qlt_mem_free(ha);
3425
e315cd28
AC		 3426 if (ha->init_cb)
3427 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
a9083016 3428 ha->init_cb, ha->init_cb_dma);
e315cd28
AC		 3429 vfree(ha->optrom_buffer);
3430 kfree(ha->nvram);
73208dfd 3431 kfree(ha->npiv_info);
7a67735b 3432 kfree(ha->swl);
5f16b331 3433 kfree(ha->loop_id_map);
1da177e4 3434
e8711085 3435 ha->srb_mempool = NULL;
a9083016 3436 ha->ctx_mempool = NULL;
1da177e4
LT		 3437 ha->sns_cmd = NULL;
3438 ha->sns_cmd_dma = 0;
3439 ha->ct_sns = NULL;
3440 ha->ct_sns_dma = 0;
3441 ha->ms_iocb = NULL;
3442 ha->ms_iocb_dma = 0;
1da177e4
LT		 3443 ha->init_cb = NULL;
3444 ha->init_cb_dma = 0;
b64b0e8f
AV		 3445 ha->ex_init_cb = NULL;
3446 ha->ex_init_cb_dma = 0;
5ff1d584
AV		 3447 ha->async_pd = NULL;
3448 ha->async_pd_dma = 0;
1da177e4
LT		 3449
3450 ha->s_dma_pool = NULL;
a9083016
GM		 3451 ha->dl_dma_pool = NULL;
3452 ha->fcp_cmnd_dma_pool = NULL;
1da177e4 3453
1da177e4
LT		 3454 ha->gid_list = NULL;
3455 ha->gid_list_dma = 0;
2d70c103
NB		 3456
3457 ha->tgt.atio_ring = NULL;
3458 ha->tgt.atio_dma = 0;
3459 ha->tgt.tgt_vp_map = NULL;
e315cd28 3460}
1da177e4 3461
e315cd28
AC		 3462struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
3463 struct qla_hw_data *ha)
3464{
3465 struct Scsi_Host *host;
3466 struct scsi_qla_host *vha = NULL;
854165f4 3467
e315cd28
AC		 3468 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
3469 if (host == NULL) {
7c3df132
SK		 3470 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
3471 "Failed to allocate host from the scsi layer, aborting.\n");
e315cd28
AC		 3472 goto fail;
3473 }
3474
3475 /* Clear our data area */
3476 vha = shost_priv(host);
3477 memset(vha, 0, sizeof(scsi_qla_host_t));
3478
3479 vha->host = host;
3480 vha->host_no = host->host_no;
3481 vha->hw = ha;
3482
3483 INIT_LIST_HEAD(&vha->vp_fcports);
3484 INIT_LIST_HEAD(&vha->work_list);
3485 INIT_LIST_HEAD(&vha->list);
3486
f999f4c1
AV		 3487 spin_lock_init(&vha->work_lock);
3488
e315cd28 3489 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
7c3df132
SK		 3490 ql_dbg(ql_dbg_init, vha, 0x0041,
3491 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
3492 vha->host, vha->hw, vha,
3493 dev_name(&(ha->pdev->dev)));
3494
e315cd28
AC		 3495 return vha;
3496
3497fail:
3498 return vha;
1da177e4
LT		 3499}
3500
01ef66bb 3501static struct qla_work_evt *
f999f4c1 3502qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
0971de7f
AV		 3503{
3504 struct qla_work_evt *e;
feafb7b1
AE		 3505 uint8_t bail;
3506
3507 QLA_VHA_MARK_BUSY(vha, bail);
3508 if (bail)
3509 return NULL;
0971de7f 3510
f999f4c1 3511 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
feafb7b1
AE		 3512 if (!e) {
3513 QLA_VHA_MARK_NOT_BUSY(vha);
0971de7f 3514 return NULL;
feafb7b1 3515 }
0971de7f
AV		 3516
3517 INIT_LIST_HEAD(&e->list);
3518 e->type = type;
3519 e->flags = QLA_EVT_FLAG_FREE;
3520 return e;
3521}
3522
01ef66bb 3523static int
f999f4c1 3524qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
0971de7f 3525{
f999f4c1 3526 unsigned long flags;
0971de7f 3527
f999f4c1 3528 spin_lock_irqsave(&vha->work_lock, flags);
e315cd28 3529 list_add_tail(&e->list, &vha->work_list);
f999f4c1 3530 spin_unlock_irqrestore(&vha->work_lock, flags);
e315cd28 3531 qla2xxx_wake_dpc(vha);
f999f4c1 3532
0971de7f
AV		 3533 return QLA_SUCCESS;
3534}
3535
3536int
e315cd28 3537qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
0971de7f
AV		 3538 u32 data)
3539{
3540 struct qla_work_evt *e;
3541
f999f4c1 3542 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
0971de7f
AV		 3543 if (!e)
3544 return QLA_FUNCTION_FAILED;
3545
3546 e->u.aen.code = code;
3547 e->u.aen.data = data;
f999f4c1 3548 return qla2x00_post_work(vha, e);
0971de7f
AV		 3549}
3550
8a659571
AV		 3551int
3552qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
3553{
3554 struct qla_work_evt *e;
3555
f999f4c1 3556 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
8a659571
AV		 3557 if (!e)
3558 return QLA_FUNCTION_FAILED;
3559
3560 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
f999f4c1 3561 return qla2x00_post_work(vha, e);
8a659571
AV		 3562}
3563
ac280b67
AV		 3564#define qla2x00_post_async_work(name, type) \
3565int qla2x00_post_async_##name##_work( \
3566 struct scsi_qla_host *vha, \
3567 fc_port_t *fcport, uint16_t *data) \
3568{ \
3569 struct qla_work_evt *e; \
3570 \
3571 e = qla2x00_alloc_work(vha, type); \
3572 if (!e) \
3573 return QLA_FUNCTION_FAILED; \
3574 \
3575 e->u.logio.fcport = fcport; \
3576 if (data) { \
3577 e->u.logio.data[0] = data[0]; \
3578 e->u.logio.data[1] = data[1]; \
3579 } \
3580 return qla2x00_post_work(vha, e); \
3581}
3582
3583qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
3584qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE);
3585qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
3586qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
5ff1d584
AV		 3587qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
3588qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
ac280b67 3589
3420d36c
AV		 3590int
3591qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
3592{
3593 struct qla_work_evt *e;
3594
3595 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
3596 if (!e)
3597 return QLA_FUNCTION_FAILED;
3598
3599 e->u.uevent.code = code;
3600 return qla2x00_post_work(vha, e);
3601}
3602
3603static void
3604qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
3605{
3606 char event_string[40];
3607 char *envp[] = { event_string, NULL };
3608
3609 switch (code) {
3610 case QLA_UEVENT_CODE_FW_DUMP:
3611 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
3612 vha->host_no);
3613 break;
3614 default:
3615 /* do nothing */
3616 break;
3617 }
3618 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
3619}
3620
ac280b67 3621void
e315cd28 3622qla2x00_do_work(struct scsi_qla_host *vha)
0971de7f 3623{
f999f4c1
AV		 3624 struct qla_work_evt *e, *tmp;
3625 unsigned long flags;
3626 LIST_HEAD(work);
0971de7f 3627
f999f4c1
AV		 3628 spin_lock_irqsave(&vha->work_lock, flags);
3629 list_splice_init(&vha->work_list, &work);
3630 spin_unlock_irqrestore(&vha->work_lock, flags);
3631
3632 list_for_each_entry_safe(e, tmp, &work, list) {
0971de7f 3633 list_del_init(&e->list);
0971de7f
AV		 3634
3635 switch (e->type) {
3636 case QLA_EVT_AEN:
e315cd28 3637 fc_host_post_event(vha->host, fc_get_event_number(),
0971de7f
AV		 3638 e->u.aen.code, e->u.aen.data);
3639 break;
8a659571
AV		 3640 case QLA_EVT_IDC_ACK:
3641 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
3642 break;
ac280b67
AV		 3643 case QLA_EVT_ASYNC_LOGIN:
3644 qla2x00_async_login(vha, e->u.logio.fcport,
3645 e->u.logio.data);
3646 break;
3647 case QLA_EVT_ASYNC_LOGIN_DONE:
3648 qla2x00_async_login_done(vha, e->u.logio.fcport,
3649 e->u.logio.data);
3650 break;
3651 case QLA_EVT_ASYNC_LOGOUT:
3652 qla2x00_async_logout(vha, e->u.logio.fcport);
3653 break;
3654 case QLA_EVT_ASYNC_LOGOUT_DONE:
3655 qla2x00_async_logout_done(vha, e->u.logio.fcport,
3656 e->u.logio.data);
3657 break;
5ff1d584
AV		 3658 case QLA_EVT_ASYNC_ADISC:
3659 qla2x00_async_adisc(vha, e->u.logio.fcport,
3660 e->u.logio.data);
3661 break;
3662 case QLA_EVT_ASYNC_ADISC_DONE:
3663 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
3664 e->u.logio.data);
3665 break;
3420d36c
AV		 3666 case QLA_EVT_UEVENT:
3667 qla2x00_uevent_emit(vha, e->u.uevent.code);
3668 break;
0971de7f
AV		 3669 }
3670 if (e->flags & QLA_EVT_FLAG_FREE)
3671 kfree(e);
feafb7b1
AE		 3672
3673 /* For each work completed decrement vha ref count */
3674 QLA_VHA_MARK_NOT_BUSY(vha);
e315cd28 3675 }
e315cd28 3676}
f999f4c1 3677
e315cd28
AC		 3678/* Relogins all the fcports of a vport
3679 * Context: dpc thread
3680 */
3681void qla2x00_relogin(struct scsi_qla_host *vha)
3682{
3683 fc_port_t *fcport;
c6b2fca8 3684 int status;
e315cd28
AC		 3685 uint16_t next_loopid = 0;
3686 struct qla_hw_data *ha = vha->hw;
ac280b67 3687 uint16_t data[2];
e315cd28
AC		 3688
3689 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3690 /*
3691 * If the port is not ONLINE then try to login
3692 * to it if we haven't run out of retries.
3693 */
5ff1d584
AV		 3694 if (atomic_read(&fcport->state) != FCS_ONLINE &&
3695 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
ac280b67 3696 fcport->login_retry--;
e315cd28 3697 if (fcport->flags & FCF_FABRIC_DEVICE) {
f08b7251 3698 if (fcport->flags & FCF_FCP2_DEVICE)
e315cd28
AC		 3699 ha->isp_ops->fabric_logout(vha,
3700 fcport->loop_id,
3701 fcport->d_id.b.domain,
3702 fcport->d_id.b.area,
3703 fcport->d_id.b.al_pa);
3704
03bcfb57
JC		 3705 if (fcport->loop_id == FC_NO_LOOP_ID) {
3706 fcport->loop_id = next_loopid =
3707 ha->min_external_loopid;
3708 status = qla2x00_find_new_loop_id(
3709 vha, fcport);
3710 if (status != QLA_SUCCESS) {
3711 /* Ran out of IDs to use */
3712 break;
3713 }
3714 }
3715
ac280b67 3716 if (IS_ALOGIO_CAPABLE(ha)) {
5ff1d584 3717 fcport->flags |= FCF_ASYNC_SENT;
ac280b67
AV		 3718 data[0] = 0;
3719 data[1] = QLA_LOGIO_LOGIN_RETRIED;
3720 status = qla2x00_post_async_login_work(
3721 vha, fcport, data);
3722 if (status == QLA_SUCCESS)
3723 continue;
3724 /* Attempt a retry. */
3725 status = 1;
aaf4d3e2 3726 } else {
ac280b67
AV		 3727 status = qla2x00_fabric_login(vha,
3728 fcport, &next_loopid);
aaf4d3e2
SK		 3729 if (status == QLA_SUCCESS) {
3730 int status2;
3731 uint8_t opts;
3732
3733 opts = 0;
3734 if (fcport->flags &
3735 FCF_FCP2_DEVICE)
3736 opts |= BIT_1;
03003960
SK		 3737 status2 =
3738 qla2x00_get_port_database(
3739 vha, fcport, opts);
aaf4d3e2
SK		 3740 if (status2 != QLA_SUCCESS)
3741 status = 1;
3742 }
3743 }
e315cd28
AC		 3744 } else
3745 status = qla2x00_local_device_login(vha,
3746 fcport);
3747
e315cd28
AC		 3748 if (status == QLA_SUCCESS) {
3749 fcport->old_loop_id = fcport->loop_id;
3750
7c3df132
SK		 3751 ql_dbg(ql_dbg_disc, vha, 0x2003,
3752 "Port login OK: logged in ID 0x%x.\n",
3753 fcport->loop_id);
e315cd28
AC		 3754
3755 qla2x00_update_fcport(vha, fcport);
3756
3757 } else if (status == 1) {
3758 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
3759 /* retry the login again */
7c3df132
SK		 3760 ql_dbg(ql_dbg_disc, vha, 0x2007,
3761 "Retrying %d login again loop_id 0x%x.\n",
3762 fcport->login_retry, fcport->loop_id);
e315cd28
AC		 3763 } else {
3764 fcport->login_retry = 0;
3765 }
3766
3767 if (fcport->login_retry == 0 && status != QLA_SUCCESS)
5f16b331 3768 qla2x00_clear_loop_id(fcport);
e315cd28
AC		 3769 }
3770 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
3771 break;
0971de7f 3772 }
0971de7f
AV		 3773}
3774
7d613ac6
SV		 3775/* Schedule work on any of the dpc-workqueues */
3776void
3777qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
3778{
3779 struct qla_hw_data *ha = base_vha->hw;
3780
3781 switch (work_code) {
3782 case MBA_IDC_AEN: /* 0x8200 */
3783 if (ha->dpc_lp_wq)
3784 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
3785 break;
3786
3787 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
3788 if (!ha->flags.nic_core_reset_hdlr_active) {
3789 if (ha->dpc_hp_wq)
3790 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
3791 } else
3792 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
3793 "NIC Core reset is already active. Skip "
3794 "scheduling it again.\n");
3795 break;
3796 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
3797 if (ha->dpc_hp_wq)
3798 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
3799 break;
3800 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
3801 if (ha->dpc_hp_wq)
3802 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
3803 break;
3804 default:
3805 ql_log(ql_log_warn, base_vha, 0xb05f,
3806 "Unknow work-code=0x%x.\n", work_code);
3807 }
3808
3809 return;
3810}
3811
3812/* Work: Perform NIC Core Unrecoverable state handling */
3813void
3814qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
3815{
3816 struct qla_hw_data *ha =
2ad1b67c 3817 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
7d613ac6
SV		 3818 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
3819 uint32_t dev_state = 0;
3820
3821 qla83xx_idc_lock(base_vha, 0);
3822 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
3823 qla83xx_reset_ownership(base_vha);
3824 if (ha->flags.nic_core_reset_owner) {
3825 ha->flags.nic_core_reset_owner = 0;
3826 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
3827 QLA8XXX_DEV_FAILED);
3828 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
3829 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
3830 }
3831 qla83xx_idc_unlock(base_vha, 0);
3832}
3833
3834/* Work: Execute IDC state handler */
3835void
3836qla83xx_idc_state_handler_work(struct work_struct *work)
3837{
3838 struct qla_hw_data *ha =
2ad1b67c 3839 container_of(work, struct qla_hw_data, idc_state_handler);
7d613ac6
SV		 3840 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
3841 uint32_t dev_state = 0;
3842
3843 qla83xx_idc_lock(base_vha, 0);
3844 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
3845 if (dev_state == QLA8XXX_DEV_FAILED ||
3846 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
3847 qla83xx_idc_state_handler(base_vha);
3848 qla83xx_idc_unlock(base_vha, 0);
3849}
3850
fa492630 3851static int
7d613ac6
SV		 3852qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
3853{
3854 int rval = QLA_SUCCESS;
3855 unsigned long heart_beat_wait = jiffies + (1 * HZ);
3856 uint32_t heart_beat_counter1, heart_beat_counter2;
3857
3858 do {
3859 if (time_after(jiffies, heart_beat_wait)) {
3860 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
3861 "Nic Core f/w is not alive.\n");
3862 rval = QLA_FUNCTION_FAILED;
3863 break;
3864 }
3865
3866 qla83xx_idc_lock(base_vha, 0);
3867 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
3868 &heart_beat_counter1);
3869 qla83xx_idc_unlock(base_vha, 0);
3870 msleep(100);
3871 qla83xx_idc_lock(base_vha, 0);
3872 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
3873 &heart_beat_counter2);
3874 qla83xx_idc_unlock(base_vha, 0);
3875 } while (heart_beat_counter1 == heart_beat_counter2);
3876
3877 return rval;
3878}
3879
3880/* Work: Perform NIC Core Reset handling */
3881void
3882qla83xx_nic_core_reset_work(struct work_struct *work)
3883{
3884 struct qla_hw_data *ha =
3885 container_of(work, struct qla_hw_data, nic_core_reset);
3886 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
3887 uint32_t dev_state = 0;
3888
81178772
SK		 3889 if (IS_QLA2031(ha)) {
3890 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
3891 ql_log(ql_log_warn, base_vha, 0xb081,
3892 "Failed to dump mctp\n");
3893 return;
3894 }
3895
7d613ac6
SV		 3896 if (!ha->flags.nic_core_reset_hdlr_active) {
3897 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
3898 qla83xx_idc_lock(base_vha, 0);
3899 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
3900 &dev_state);
3901 qla83xx_idc_unlock(base_vha, 0);
3902 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
3903 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
3904 "Nic Core f/w is alive.\n");
3905 return;
3906 }
3907 }
3908
3909 ha->flags.nic_core_reset_hdlr_active = 1;
3910 if (qla83xx_nic_core_reset(base_vha)) {
3911 /* NIC Core reset failed. */
3912 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
3913 "NIC Core reset failed.\n");
3914 }
3915 ha->flags.nic_core_reset_hdlr_active = 0;
3916 }
3917}
3918
3919/* Work: Handle 8200 IDC aens */
3920void
3921qla83xx_service_idc_aen(struct work_struct *work)
3922{
3923 struct qla_hw_data *ha =
3924 container_of(work, struct qla_hw_data, idc_aen);
3925 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
3926 uint32_t dev_state, idc_control;
3927
3928 qla83xx_idc_lock(base_vha, 0);
3929 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
3930 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
3931 qla83xx_idc_unlock(base_vha, 0);
3932 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
3933 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
3934 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
3935 "Application requested NIC Core Reset.\n");
3936 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
3937 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
3938 QLA_SUCCESS) {
3939 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
3940 "Other protocol driver requested NIC Core Reset.\n");
3941 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
3942 }
3943 } else if (dev_state == QLA8XXX_DEV_FAILED ||
3944 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
3945 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
3946 }
3947}
3948
3949static void
3950qla83xx_wait_logic(void)
3951{
3952 int i;
3953
3954 /* Yield CPU */
3955 if (!in_interrupt()) {
3956 /*
3957 * Wait about 200ms before retrying again.
3958 * This controls the number of retries for single
3959 * lock operation.
3960 */
3961 msleep(100);
3962 schedule();
3963 } else {
3964 for (i = 0; i < 20; i++)
3965 cpu_relax(); /* This a nop instr on i386 */
3966 }
3967}
3968
fa492630 3969static int
7d613ac6
SV		 3970qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
3971{
3972 int rval;
3973 uint32_t data;
3974 uint32_t idc_lck_rcvry_stage_mask = 0x3;
3975 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
3976 struct qla_hw_data *ha = base_vha->hw;
3977
3978 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
3979 if (rval)
3980 return rval;
3981
3982 if ((data & idc_lck_rcvry_stage_mask) > 0) {
3983 return QLA_SUCCESS;
3984 } else {
3985 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
3986 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
3987 data);
3988 if (rval)
3989 return rval;
3990
3991 msleep(200);
3992
3993 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
3994 &data);
3995 if (rval)
3996 return rval;
3997
3998 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
3999 data &= (IDC_LOCK_RECOVERY_STAGE2 |
4000 ~(idc_lck_rcvry_stage_mask));
4001 rval = qla83xx_wr_reg(base_vha,
4002 QLA83XX_IDC_LOCK_RECOVERY, data);
4003 if (rval)
4004 return rval;
4005
4006 /* Forcefully perform IDC UnLock */
4007 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
4008 &data);
4009 if (rval)
4010 return rval;
4011 /* Clear lock-id by setting 0xff */
4012 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4013 0xff);
4014 if (rval)
4015 return rval;
4016 /* Clear lock-recovery by setting 0x0 */
4017 rval = qla83xx_wr_reg(base_vha,
4018 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
4019 if (rval)
4020 return rval;
4021 } else
4022 return QLA_SUCCESS;
4023 }
4024
4025 return rval;
4026}
4027
fa492630 4028static int
7d613ac6
SV		 4029qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
4030{
4031 int rval = QLA_SUCCESS;
4032 uint32_t o_drv_lockid, n_drv_lockid;
4033 unsigned long lock_recovery_timeout;
4034
4035 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
4036retry_lockid:
4037 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
4038 if (rval)
4039 goto exit;
4040
4041 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
4042 if (time_after_eq(jiffies, lock_recovery_timeout)) {
4043 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
4044 return QLA_SUCCESS;
4045 else
4046 return QLA_FUNCTION_FAILED;
4047 }
4048
4049 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
4050 if (rval)
4051 goto exit;
4052
4053 if (o_drv_lockid == n_drv_lockid) {
4054 qla83xx_wait_logic();
4055 goto retry_lockid;
4056 } else
4057 return QLA_SUCCESS;
4058
4059exit:
4060 return rval;
4061}
4062
4063void
4064qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4065{
4066 uint16_t options = (requester_id << 15) | BIT_6;
4067 uint32_t data;
4068 struct qla_hw_data *ha = base_vha->hw;
4069
4070 /* IDC-lock implementation using driver-lock/lock-id remote registers */
4071retry_lock:
4072 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
4073 == QLA_SUCCESS) {
4074 if (data) {
4075 /* Setting lock-id to our function-number */
4076 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4077 ha->portnum);
4078 } else {
4079 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
4080 "Failed to acquire IDC lock. retrying...\n");
4081
4082 /* Retry/Perform IDC-Lock recovery */
4083 if (qla83xx_idc_lock_recovery(base_vha)
4084 == QLA_SUCCESS) {
4085 qla83xx_wait_logic();
4086 goto retry_lock;
4087 } else
4088 ql_log(ql_log_warn, base_vha, 0xb075,
4089 "IDC Lock recovery FAILED.\n");
4090 }
4091
4092 }
4093
4094 return;
4095
4096 /* XXX: IDC-lock implementation using access-control mbx */
4097retry_lock2:
4098 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4099 ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
4100 "Failed to acquire IDC lock. retrying...\n");
4101 /* Retry/Perform IDC-Lock recovery */
4102 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
4103 qla83xx_wait_logic();
4104 goto retry_lock2;
4105 } else
4106 ql_log(ql_log_warn, base_vha, 0xb076,
4107 "IDC Lock recovery FAILED.\n");
4108 }
4109
4110 return;
4111}
4112
4113void
4114qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4115{
4116 uint16_t options = (requester_id << 15) | BIT_7, retry;
4117 uint32_t data;
4118 struct qla_hw_data *ha = base_vha->hw;
4119
4120 /* IDC-unlock implementation using driver-unlock/lock-id
4121 * remote registers
4122 */
4123 retry = 0;
4124retry_unlock:
4125 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
4126 == QLA_SUCCESS) {
4127 if (data == ha->portnum) {
4128 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
4129 /* Clearing lock-id by setting 0xff */
4130 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
4131 } else if (retry < 10) {
4132 /* SV: XXX: IDC unlock retrying needed here? */
4133
4134 /* Retry for IDC-unlock */
4135 qla83xx_wait_logic();
4136 retry++;
4137 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
4138 "Failed to release IDC lock, retyring=%d\n", retry);
4139 goto retry_unlock;
4140 }
4141 } else if (retry < 10) {
4142 /* Retry for IDC-unlock */
4143 qla83xx_wait_logic();
4144 retry++;
4145 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
4146 "Failed to read drv-lockid, retyring=%d\n", retry);
4147 goto retry_unlock;
4148 }
4149
4150 return;
4151
4152 /* XXX: IDC-unlock implementation using access-control mbx */
4153 retry = 0;
4154retry_unlock2:
4155 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4156 if (retry < 10) {
4157 /* Retry for IDC-unlock */
4158 qla83xx_wait_logic();
4159 retry++;
4160 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
4161 "Failed to release IDC lock, retyring=%d\n", retry);
4162 goto retry_unlock2;
4163 }
4164 }
4165
4166 return;
4167}
4168
4169int
4170__qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4171{
4172 int rval = QLA_SUCCESS;
4173 struct qla_hw_data *ha = vha->hw;
4174 uint32_t drv_presence;
4175
4176 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4177 if (rval == QLA_SUCCESS) {
4178 drv_presence |= (1 << ha->portnum);
4179 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4180 drv_presence);
4181 }
4182
4183 return rval;
4184}
4185
4186int
4187qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4188{
4189 int rval = QLA_SUCCESS;
4190
4191 qla83xx_idc_lock(vha, 0);
4192 rval = __qla83xx_set_drv_presence(vha);
4193 qla83xx_idc_unlock(vha, 0);
4194
4195 return rval;
4196}
4197
4198int
4199__qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4200{
4201 int rval = QLA_SUCCESS;
4202 struct qla_hw_data *ha = vha->hw;
4203 uint32_t drv_presence;
4204
4205 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4206 if (rval == QLA_SUCCESS) {
4207 drv_presence &= ~(1 << ha->portnum);
4208 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4209 drv_presence);
4210 }
4211
4212 return rval;
4213}
4214
4215int
4216qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4217{
4218 int rval = QLA_SUCCESS;
4219
4220 qla83xx_idc_lock(vha, 0);
4221 rval = __qla83xx_clear_drv_presence(vha);
4222 qla83xx_idc_unlock(vha, 0);
4223
4224 return rval;
4225}
4226
fa492630 4227static void
7d613ac6
SV		 4228qla83xx_need_reset_handler(scsi_qla_host_t *vha)
4229{
4230 struct qla_hw_data *ha = vha->hw;
4231 uint32_t drv_ack, drv_presence;
4232 unsigned long ack_timeout;
4233
4234 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
4235 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
4236 while (1) {
4237 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4238 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
807fb6d8 4239 if ((drv_ack & drv_presence) == drv_presence)
7d613ac6
SV		 4240 break;
4241
4242 if (time_after_eq(jiffies, ack_timeout)) {
4243 ql_log(ql_log_warn, vha, 0xb067,
4244 "RESET ACK TIMEOUT! drv_presence=0x%x "
4245 "drv_ack=0x%x\n", drv_presence, drv_ack);
4246 /*
4247 * The function(s) which did not ack in time are forced
4248 * to withdraw any further participation in the IDC
4249 * reset.
4250 */
4251 if (drv_ack != drv_presence)
4252 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4253 drv_ack);
4254 break;
4255 }
4256
4257 qla83xx_idc_unlock(vha, 0);
4258 msleep(1000);
4259 qla83xx_idc_lock(vha, 0);
4260 }
4261
4262 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
4263 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
4264}
4265
fa492630 4266static int
7d613ac6
SV		 4267qla83xx_device_bootstrap(scsi_qla_host_t *vha)
4268{
4269 int rval = QLA_SUCCESS;
4270 uint32_t idc_control;
4271
4272 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
4273 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
4274
4275 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
4276 __qla83xx_get_idc_control(vha, &idc_control);
4277 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
4278 __qla83xx_set_idc_control(vha, 0);
4279
4280 qla83xx_idc_unlock(vha, 0);
4281 rval = qla83xx_restart_nic_firmware(vha);
4282 qla83xx_idc_lock(vha, 0);
4283
4284 if (rval != QLA_SUCCESS) {
4285 ql_log(ql_log_fatal, vha, 0xb06a,
4286 "Failed to restart NIC f/w.\n");
4287 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
4288 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
4289 } else {
4290 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
4291 "Success in restarting nic f/w.\n");
4292 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
4293 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
4294 }
4295
4296 return rval;
4297}
4298
4299/* Assumes idc_lock always held on entry */
4300int
4301qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
4302{
4303 struct qla_hw_data *ha = base_vha->hw;
4304 int rval = QLA_SUCCESS;
4305 unsigned long dev_init_timeout;
4306 uint32_t dev_state;
4307
4308 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
4309 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
4310
4311 while (1) {
4312
4313 if (time_after_eq(jiffies, dev_init_timeout)) {
4314 ql_log(ql_log_warn, base_vha, 0xb06e,
4315 "Initialization TIMEOUT!\n");
4316 /* Init timeout. Disable further NIC Core
4317 * communication.
4318 */
4319 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4320 QLA8XXX_DEV_FAILED);
4321 ql_log(ql_log_info, base_vha, 0xb06f,
4322 "HW State: FAILED.\n");
4323 }
4324
4325 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4326 switch (dev_state) {
4327 case QLA8XXX_DEV_READY:
4328 if (ha->flags.nic_core_reset_owner)
4329 qla83xx_idc_audit(base_vha,
4330 IDC_AUDIT_COMPLETION);
4331 ha->flags.nic_core_reset_owner = 0;
4332 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
4333 "Reset_owner reset by 0x%x.\n",
4334 ha->portnum);
4335 goto exit;
4336 case QLA8XXX_DEV_COLD:
4337 if (ha->flags.nic_core_reset_owner)
4338 rval = qla83xx_device_bootstrap(base_vha);
4339 else {
4340 /* Wait for AEN to change device-state */
4341 qla83xx_idc_unlock(base_vha, 0);
4342 msleep(1000);
4343 qla83xx_idc_lock(base_vha, 0);
4344 }
4345 break;
4346 case QLA8XXX_DEV_INITIALIZING:
4347 /* Wait for AEN to change device-state */
4348 qla83xx_idc_unlock(base_vha, 0);
4349 msleep(1000);
4350 qla83xx_idc_lock(base_vha, 0);
4351 break;
4352 case QLA8XXX_DEV_NEED_RESET:
4353 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
4354 qla83xx_need_reset_handler(base_vha);
4355 else {
4356 /* Wait for AEN to change device-state */
4357 qla83xx_idc_unlock(base_vha, 0);
4358 msleep(1000);
4359 qla83xx_idc_lock(base_vha, 0);
4360 }
4361 /* reset timeout value after need reset handler */
4362 dev_init_timeout = jiffies +
4363 (ha->fcoe_dev_init_timeout * HZ);
4364 break;
4365 case QLA8XXX_DEV_NEED_QUIESCENT:
4366 /* XXX: DEBUG for now */
4367 qla83xx_idc_unlock(base_vha, 0);
4368 msleep(1000);
4369 qla83xx_idc_lock(base_vha, 0);
4370 break;
4371 case QLA8XXX_DEV_QUIESCENT:
4372 /* XXX: DEBUG for now */
4373 if (ha->flags.quiesce_owner)
4374 goto exit;
4375
4376 qla83xx_idc_unlock(base_vha, 0);
4377 msleep(1000);
4378 qla83xx_idc_lock(base_vha, 0);
4379 dev_init_timeout = jiffies +
4380 (ha->fcoe_dev_init_timeout * HZ);
4381 break;
4382 case QLA8XXX_DEV_FAILED:
4383 if (ha->flags.nic_core_reset_owner)
4384 qla83xx_idc_audit(base_vha,
4385 IDC_AUDIT_COMPLETION);
4386 ha->flags.nic_core_reset_owner = 0;
4387 __qla83xx_clear_drv_presence(base_vha);
4388 qla83xx_idc_unlock(base_vha, 0);
4389 qla8xxx_dev_failed_handler(base_vha);
4390 rval = QLA_FUNCTION_FAILED;
4391 qla83xx_idc_lock(base_vha, 0);
4392 goto exit;
4393 case QLA8XXX_BAD_VALUE:
4394 qla83xx_idc_unlock(base_vha, 0);
4395 msleep(1000);
4396 qla83xx_idc_lock(base_vha, 0);
4397 break;
4398 default:
4399 ql_log(ql_log_warn, base_vha, 0xb071,
4400 "Unknow Device State: %x.\n", dev_state);
4401 qla83xx_idc_unlock(base_vha, 0);
4402 qla8xxx_dev_failed_handler(base_vha);
4403 rval = QLA_FUNCTION_FAILED;
4404 qla83xx_idc_lock(base_vha, 0);
4405 goto exit;
4406 }
4407 }
4408
4409exit:
4410 return rval;
4411}
4412
1da177e4
LT		 4413/**************************************************************************
4414* qla2x00_do_dpc
4415* This kernel thread is a task that is schedule by the interrupt handler
4416* to perform the background processing for interrupts.
4417*
4418* Notes:
4419* This task always run in the context of a kernel thread. It
4420* is kick-off by the driver's detect code and starts up
4421* up one per adapter. It immediately goes to sleep and waits for
4422* some fibre event. When either the interrupt handler or
4423* the timer routine detects a event it will one of the task
4424* bits then wake us up.
4425**************************************************************************/
4426static int
4427qla2x00_do_dpc(void *data)
4428{
2c3dfe3f 4429 int rval;
e315cd28
AC		 4430 scsi_qla_host_t *base_vha;
4431 struct qla_hw_data *ha;
1da177e4 4432
e315cd28
AC		 4433 ha = (struct qla_hw_data *)data;
4434 base_vha = pci_get_drvdata(ha->pdev);
1da177e4 4435
1da177e4
LT		 4436 set_user_nice(current, -20);
4437
563585ec 4438 set_current_state(TASK_INTERRUPTIBLE);
39a11240 4439 while (!kthread_should_stop()) {
7c3df132
SK		 4440 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
4441 "DPC handler sleeping.\n");
1da177e4 4442
39a11240
CH		 4443 schedule();
4444 __set_current_state(TASK_RUNNING);
1da177e4 4445
c142caf0
AV		 4446 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
4447 goto end_loop;
1da177e4 4448
85880801 4449 if (ha->flags.eeh_busy) {
7c3df132
SK		 4450 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
4451 "eeh_busy=%d.\n", ha->flags.eeh_busy);
c142caf0 4452 goto end_loop;
85880801
AV		 4453 }
4454
1da177e4
LT		 4455 ha->dpc_active = 1;
4456
5f28d2d7
SK		 4457 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
4458 "DPC handler waking up, dpc_flags=0x%lx.\n",
4459 base_vha->dpc_flags);
1da177e4 4460
e315cd28 4461 qla2x00_do_work(base_vha);
0971de7f 4462
a9083016
GM		 4463 if (IS_QLA82XX(ha)) {
4464 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4465 &base_vha->dpc_flags)) {
4466 qla82xx_idc_lock(ha);
4467 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 4468 QLA8XXX_DEV_FAILED);
a9083016 4469 qla82xx_idc_unlock(ha);
7c3df132
SK		 4470 ql_log(ql_log_info, base_vha, 0x4004,
4471 "HW State: FAILED.\n");
a9083016
GM		 4472 qla82xx_device_state_handler(base_vha);
4473 continue;
4474 }
4475
4476 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
4477 &base_vha->dpc_flags)) {
4478
7c3df132
SK		 4479 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
4480 "FCoE context reset scheduled.\n");
a9083016
GM		 4481 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
4482 &base_vha->dpc_flags))) {
4483 if (qla82xx_fcoe_ctx_reset(base_vha)) {
4484 /* FCoE-ctx reset failed.
4485 * Escalate to chip-reset
4486 */
4487 set_bit(ISP_ABORT_NEEDED,
4488 &base_vha->dpc_flags);
4489 }
4490 clear_bit(ABORT_ISP_ACTIVE,
4491 &base_vha->dpc_flags);
4492 }
4493
7c3df132
SK		 4494 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
4495 "FCoE context reset end.\n");
a9083016
GM		 4496 }
4497 }
4498
e315cd28
AC		 4499 if (test_and_clear_bit(ISP_ABORT_NEEDED,
4500 &base_vha->dpc_flags)) {
1da177e4 4501
7c3df132
SK		 4502 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
4503 "ISP abort scheduled.\n");
1da177e4 4504 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
e315cd28 4505 &base_vha->dpc_flags))) {
1da177e4 4506
a9083016 4507 if (ha->isp_ops->abort_isp(base_vha)) {
1da177e4
LT		 4508 /* failed. retry later */
4509 set_bit(ISP_ABORT_NEEDED,
e315cd28 4510 &base_vha->dpc_flags);
99363ef8 4511 }
e315cd28
AC		 4512 clear_bit(ABORT_ISP_ACTIVE,
4513 &base_vha->dpc_flags);
99363ef8
SJ		 4514 }
4515
7c3df132
SK		 4516 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
4517 "ISP abort end.\n");
1da177e4
LT		 4518 }
4519
a394aac8
DJ		 4520 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
4521 &base_vha->dpc_flags)) {
e315cd28 4522 qla2x00_update_fcports(base_vha);
c9c5ced9 4523 }
d97994dc 4524
2d70c103
NB		 4525 if (test_bit(SCR_PENDING, &base_vha->dpc_flags)) {
4526 int ret;
4527 ret = qla2x00_send_change_request(base_vha, 0x3, 0);
4528 if (ret != QLA_SUCCESS)
4529 ql_log(ql_log_warn, base_vha, 0x121,
4530 "Failed to enable receiving of RSCN "
4531 "requests: 0x%x.\n", ret);
4532 clear_bit(SCR_PENDING, &base_vha->dpc_flags);
4533 }
4534
579d12b5 4535 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7c3df132
SK		 4536 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
4537 "Quiescence mode scheduled.\n");
8fcd6b8b
CD		 4538 if (IS_QLA82XX(ha)) {
4539 qla82xx_device_state_handler(base_vha);
4540 clear_bit(ISP_QUIESCE_NEEDED,
4541 &base_vha->dpc_flags);
4542 if (!ha->flags.quiesce_owner) {
4543 qla2x00_perform_loop_resync(base_vha);
4544
4545 qla82xx_idc_lock(ha);
4546 qla82xx_clear_qsnt_ready(base_vha);
4547 qla82xx_idc_unlock(ha);
4548 }
4549 } else {
4550 clear_bit(ISP_QUIESCE_NEEDED,
4551 &base_vha->dpc_flags);
4552 qla2x00_quiesce_io(base_vha);
579d12b5 4553 }
7c3df132
SK		 4554 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
4555 "Quiescence mode end.\n");
579d12b5
SK		 4556 }
4557
e315cd28
AC		 4558 if (test_and_clear_bit(RESET_MARKER_NEEDED,
4559 &base_vha->dpc_flags) &&
4560 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
1da177e4 4561
7c3df132
SK		 4562 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
4563 "Reset marker scheduled.\n");
e315cd28
AC		 4564 qla2x00_rst_aen(base_vha);
4565 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7c3df132
SK		 4566 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
4567 "Reset marker end.\n");
1da177e4
LT		 4568 }
4569
4570 /* Retry each device up to login retry count */
e315cd28
AC		 4571 if ((test_and_clear_bit(RELOGIN_NEEDED,
4572 &base_vha->dpc_flags)) &&
4573 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
4574 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
1da177e4 4575
7c3df132
SK		 4576 ql_dbg(ql_dbg_dpc, base_vha, 0x400d,
4577 "Relogin scheduled.\n");
e315cd28 4578 qla2x00_relogin(base_vha);
7c3df132
SK		 4579 ql_dbg(ql_dbg_dpc, base_vha, 0x400e,
4580 "Relogin end.\n");
1da177e4
LT		 4581 }
4582
e315cd28
AC		 4583 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
4584 &base_vha->dpc_flags)) {
1da177e4 4585
7c3df132
SK		 4586 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
4587 "Loop resync scheduled.\n");
1da177e4
LT		 4588
4589 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
e315cd28 4590 &base_vha->dpc_flags))) {
1da177e4 4591
e315cd28 4592 rval = qla2x00_loop_resync(base_vha);
1da177e4 4593
e315cd28
AC		 4594 clear_bit(LOOP_RESYNC_ACTIVE,
4595 &base_vha->dpc_flags);
1da177e4
LT		 4596 }
4597
7c3df132
SK		 4598 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
4599 "Loop resync end.\n");
1da177e4
LT		 4600 }
4601
e315cd28
AC		 4602 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
4603 atomic_read(&base_vha->loop_state) == LOOP_READY) {
4604 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
4605 qla2xxx_flash_npiv_conf(base_vha);
272976ca
AV		 4606 }
4607
1da177e4 4608 if (!ha->interrupts_on)
fd34f556 4609 ha->isp_ops->enable_intrs(ha);
1da177e4 4610
e315cd28
AC		 4611 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
4612 &base_vha->dpc_flags))
4613 ha->isp_ops->beacon_blink(base_vha);
f6df144c 4614
e315cd28 4615 qla2x00_do_dpc_all_vps(base_vha);
2c3dfe3f 4616
1da177e4 4617 ha->dpc_active = 0;
c142caf0 4618end_loop:
563585ec 4619 set_current_state(TASK_INTERRUPTIBLE);
1da177e4 4620 } /* End of while(1) */
563585ec 4621 __set_current_state(TASK_RUNNING);
1da177e4 4622
7c3df132
SK		 4623 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
4624 "DPC handler exiting.\n");
1da177e4
LT		 4625
4626 /*
4627 * Make sure that nobody tries to wake us up again.
4628 */
1da177e4
LT		 4629 ha->dpc_active = 0;
4630
ac280b67
AV		 4631 /* Cleanup any residual CTX SRBs. */
4632 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
4633
39a11240
CH		 4634 return 0;
4635}
4636
4637void
e315cd28 4638qla2xxx_wake_dpc(struct scsi_qla_host *vha)
39a11240 4639{
e315cd28 4640 struct qla_hw_data *ha = vha->hw;
c795c1e4
AV		 4641 struct task_struct *t = ha->dpc_thread;
4642
e315cd28 4643 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
c795c1e4 4644 wake_up_process(t);
1da177e4
LT		 4645}
4646
1da177e4
LT		 4647/*
4648* qla2x00_rst_aen
4649* Processes asynchronous reset.
4650*
4651* Input:
4652* ha = adapter block pointer.
4653*/
4654static void
e315cd28 4655qla2x00_rst_aen(scsi_qla_host_t *vha)
1da177e4 4656{
e315cd28
AC		 4657 if (vha->flags.online && !vha->flags.reset_active &&
4658 !atomic_read(&vha->loop_down_timer) &&
4659 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
1da177e4 4660 do {
e315cd28 4661 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4
LT		 4662
4663 /*
4664 * Issue marker command only when we are going to start
4665 * the I/O.
4666 */
e315cd28
AC		 4667 vha->marker_needed = 1;
4668 } while (!atomic_read(&vha->loop_down_timer) &&
4669 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
1da177e4
LT		 4670 }
4671}
4672
1da177e4
LT		 4673/**************************************************************************
4674* qla2x00_timer
4675*
4676* Description:
4677* One second timer
4678*
4679* Context: Interrupt
4680***************************************************************************/
2c3dfe3f 4681void
e315cd28 4682qla2x00_timer(scsi_qla_host_t *vha)
1da177e4 4683{
1da177e4 4684 unsigned long cpu_flags = 0;
1da177e4
LT		 4685 int start_dpc = 0;
4686 int index;
4687 srb_t *sp;
85880801 4688 uint16_t w;
e315cd28 4689 struct qla_hw_data *ha = vha->hw;
73208dfd 4690 struct req_que *req;
85880801 4691
a5b36321 4692 if (ha->flags.eeh_busy) {
7c3df132
SK		 4693 ql_dbg(ql_dbg_timer, vha, 0x6000,
4694 "EEH = %d, restarting timer.\n",
4695 ha->flags.eeh_busy);
a5b36321
LC		 4696 qla2x00_restart_timer(vha, WATCH_INTERVAL);
4697 return;
4698 }
4699
85880801
AV		 4700 /* Hardware read to raise pending EEH errors during mailbox waits. */
4701 if (!pci_channel_offline(ha->pdev))
4702 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
1da177e4 4703
cefcaba6
SK		 4704 /* Make sure qla82xx_watchdog is run only for physical port */
4705 if (!vha->vp_idx && IS_QLA82XX(ha)) {
579d12b5
SK		 4706 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
4707 start_dpc++;
4708 qla82xx_watchdog(vha);
4709 }
4710
1da177e4 4711 /* Loop down handler. */
e315cd28 4712 if (atomic_read(&vha->loop_down_timer) > 0 &&
8f7daead
GM		 4713 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
4714 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
e315cd28 4715 && vha->flags.online) {
1da177e4 4716
e315cd28
AC		 4717 if (atomic_read(&vha->loop_down_timer) ==
4718 vha->loop_down_abort_time) {
1da177e4 4719
7c3df132
SK		 4720 ql_log(ql_log_info, vha, 0x6008,
4721 "Loop down - aborting the queues before time expires.\n");
1da177e4 4722
e315cd28
AC		 4723 if (!IS_QLA2100(ha) && vha->link_down_timeout)
4724 atomic_set(&vha->loop_state, LOOP_DEAD);
1da177e4 4725
f08b7251
AV		 4726 /*
4727 * Schedule an ISP abort to return any FCP2-device
4728 * commands.
4729 */
2c3dfe3f 4730 /* NPIV - scan physical port only */
e315cd28 4731 if (!vha->vp_idx) {
2c3dfe3f
SJ		 4732 spin_lock_irqsave(&ha->hardware_lock,
4733 cpu_flags);
73208dfd 4734 req = ha->req_q_map[0];
2c3dfe3f
SJ		 4735 for (index = 1;
4736 index < MAX_OUTSTANDING_COMMANDS;
4737 index++) {
4738 fc_port_t *sfcp;
4739
e315cd28 4740 sp = req->outstanding_cmds[index];
2c3dfe3f
SJ		 4741 if (!sp)
4742 continue;
9ba56b95 4743 if (sp->type != SRB_SCSI_CMD)
cf53b069 4744 continue;
2c3dfe3f 4745 sfcp = sp->fcport;
f08b7251 4746 if (!(sfcp->flags & FCF_FCP2_DEVICE))
2c3dfe3f 4747 continue;
bdf79621 4748
8f7daead
GM		 4749 if (IS_QLA82XX(ha))
4750 set_bit(FCOE_CTX_RESET_NEEDED,
4751 &vha->dpc_flags);
4752 else
4753 set_bit(ISP_ABORT_NEEDED,
e315cd28 4754 &vha->dpc_flags);
2c3dfe3f
SJ		 4755 break;
4756 }
4757 spin_unlock_irqrestore(&ha->hardware_lock,
e315cd28 4758 cpu_flags);
1da177e4 4759 }
1da177e4
LT		 4760 start_dpc++;
4761 }
4762
4763 /* if the loop has been down for 4 minutes, reinit adapter */
e315cd28 4764 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
0d6e61bc 4765 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132 4766 ql_log(ql_log_warn, vha, 0x6009,
1da177e4
LT		 4767 "Loop down - aborting ISP.\n");
4768
8f7daead
GM		 4769 if (IS_QLA82XX(ha))
4770 set_bit(FCOE_CTX_RESET_NEEDED,
4771 &vha->dpc_flags);
4772 else
4773 set_bit(ISP_ABORT_NEEDED,
4774 &vha->dpc_flags);
1da177e4
LT		 4775 }
4776 }
7c3df132
SK		 4777 ql_dbg(ql_dbg_timer, vha, 0x600a,
4778 "Loop down - seconds remaining %d.\n",
4779 atomic_read(&vha->loop_down_timer));
1da177e4
LT		 4780 }
4781
cefcaba6
SK		 4782 /* Check if beacon LED needs to be blinked for physical host only */
4783 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
999916dc
SK		 4784 /* There is no beacon_blink function for ISP82xx */
4785 if (!IS_QLA82XX(ha)) {
4786 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
4787 start_dpc++;
4788 }
f6df144c 4789 }
4790
550bf57d 4791 /* Process any deferred work. */
e315cd28 4792 if (!list_empty(&vha->work_list))
550bf57d
AV		 4793 start_dpc++;
4794
1da177e4 4795 /* Schedule the DPC routine if needed */
e315cd28
AC		 4796 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
4797 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
4798 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
1da177e4 4799 start_dpc ||
e315cd28
AC		 4800 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
4801 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
a9083016
GM		 4802 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
4803 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
e315cd28 4804 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
7c3df132
SK		 4805 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
4806 ql_dbg(ql_dbg_timer, vha, 0x600b,
4807 "isp_abort_needed=%d loop_resync_needed=%d "
4808 "fcport_update_needed=%d start_dpc=%d "
4809 "reset_marker_needed=%d",
4810 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
4811 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
4812 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
4813 start_dpc,
4814 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
4815 ql_dbg(ql_dbg_timer, vha, 0x600c,
4816 "beacon_blink_needed=%d isp_unrecoverable=%d "
4817 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
4818 "relogin_needed=%d.\n",
4819 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
4820 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
4821 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
4822 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
4823 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
e315cd28 4824 qla2xxx_wake_dpc(vha);
7c3df132 4825 }
1da177e4 4826
e315cd28 4827 qla2x00_restart_timer(vha, WATCH_INTERVAL);
1da177e4
LT		 4828}
4829
5433383e
AV		 4830/* Firmware interface routines. */
4831
6246b8a1 4832#define FW_BLOBS 10
5433383e
AV		 4833#define FW_ISP21XX 0
4834#define FW_ISP22XX 1
4835#define FW_ISP2300 2
4836#define FW_ISP2322 3
48c02fde 4837#define FW_ISP24XX 4
c3a2f0df 4838#define FW_ISP25XX 5
3a03eb79 4839#define FW_ISP81XX 6
a9083016 4840#define FW_ISP82XX 7
6246b8a1
GM		 4841#define FW_ISP2031 8
4842#define FW_ISP8031 9
5433383e 4843
bb8ee499
AV		 4844#define FW_FILE_ISP21XX "ql2100_fw.bin"
4845#define FW_FILE_ISP22XX "ql2200_fw.bin"
4846#define FW_FILE_ISP2300 "ql2300_fw.bin"
4847#define FW_FILE_ISP2322 "ql2322_fw.bin"
4848#define FW_FILE_ISP24XX "ql2400_fw.bin"
c3a2f0df 4849#define FW_FILE_ISP25XX "ql2500_fw.bin"
3a03eb79 4850#define FW_FILE_ISP81XX "ql8100_fw.bin"
a9083016 4851#define FW_FILE_ISP82XX "ql8200_fw.bin"
6246b8a1
GM		 4852#define FW_FILE_ISP2031 "ql2600_fw.bin"
4853#define FW_FILE_ISP8031 "ql8300_fw.bin"
bb8ee499 4854
e1e82b6f 4855static DEFINE_MUTEX(qla_fw_lock);
5433383e
AV		 4856
4857static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
bb8ee499
AV		 4858 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
4859 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
4860 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
4861 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
4862 { .name = FW_FILE_ISP24XX, },
c3a2f0df 4863 { .name = FW_FILE_ISP25XX, },
3a03eb79 4864 { .name = FW_FILE_ISP81XX, },
a9083016 4865 { .name = FW_FILE_ISP82XX, },
6246b8a1
GM		 4866 { .name = FW_FILE_ISP2031, },
4867 { .name = FW_FILE_ISP8031, },
5433383e
AV		 4868};
4869
4870struct fw_blob *
e315cd28 4871qla2x00_request_firmware(scsi_qla_host_t *vha)
5433383e 4872{
e315cd28 4873 struct qla_hw_data *ha = vha->hw;
5433383e
AV		 4874 struct fw_blob *blob;
4875
5433383e
AV		 4876 if (IS_QLA2100(ha)) {
4877 blob = &qla_fw_blobs[FW_ISP21XX];
4878 } else if (IS_QLA2200(ha)) {
4879 blob = &qla_fw_blobs[FW_ISP22XX];
48c02fde 4880 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5433383e 4881 blob = &qla_fw_blobs[FW_ISP2300];
48c02fde 4882 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5433383e 4883 blob = &qla_fw_blobs[FW_ISP2322];
4d4df193 4884 } else if (IS_QLA24XX_TYPE(ha)) {
5433383e 4885 blob = &qla_fw_blobs[FW_ISP24XX];
c3a2f0df
AV		 4886 } else if (IS_QLA25XX(ha)) {
4887 blob = &qla_fw_blobs[FW_ISP25XX];
3a03eb79
AV		 4888 } else if (IS_QLA81XX(ha)) {
4889 blob = &qla_fw_blobs[FW_ISP81XX];
a9083016
GM		 4890 } else if (IS_QLA82XX(ha)) {
4891 blob = &qla_fw_blobs[FW_ISP82XX];
6246b8a1
GM		 4892 } else if (IS_QLA2031(ha)) {
4893 blob = &qla_fw_blobs[FW_ISP2031];
4894 } else if (IS_QLA8031(ha)) {
4895 blob = &qla_fw_blobs[FW_ISP8031];
8a655229
DC		 4896 } else {
4897 return NULL;
5433383e
AV		 4898 }
4899
e1e82b6f 4900 mutex_lock(&qla_fw_lock);
5433383e
AV		 4901 if (blob->fw)
4902 goto out;
4903
4904 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7c3df132
SK		 4905 ql_log(ql_log_warn, vha, 0x0063,
4906 "Failed to load firmware image (%s).\n", blob->name);
5433383e
AV		 4907 blob->fw = NULL;
4908 blob = NULL;
4909 goto out;
4910 }
4911
4912out:
e1e82b6f 4913 mutex_unlock(&qla_fw_lock);
5433383e
AV		 4914 return blob;
4915}
4916
4917static void
4918qla2x00_release_firmware(void)
4919{
4920 int idx;
4921
e1e82b6f 4922 mutex_lock(&qla_fw_lock);
5433383e 4923 for (idx = 0; idx < FW_BLOBS; idx++)
cf92549f 4924 release_firmware(qla_fw_blobs[idx].fw);
e1e82b6f 4925 mutex_unlock(&qla_fw_lock);
5433383e
AV		 4926}
4927
14e660e6
SJ		 4928static pci_ers_result_t
4929qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
4930{
85880801
AV		 4931 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
4932 struct qla_hw_data *ha = vha->hw;
4933
7c3df132
SK		 4934 ql_dbg(ql_dbg_aer, vha, 0x9000,
4935 "PCI error detected, state %x.\n", state);
b9b12f73 4936
14e660e6
SJ		 4937 switch (state) {
4938 case pci_channel_io_normal:
85880801 4939 ha->flags.eeh_busy = 0;
14e660e6
SJ		 4940 return PCI_ERS_RESULT_CAN_RECOVER;
4941 case pci_channel_io_frozen:
85880801 4942 ha->flags.eeh_busy = 1;
a5b36321
LC		 4943 /* For ISP82XX complete any pending mailbox cmd */
4944 if (IS_QLA82XX(ha)) {
7190575f 4945 ha->flags.isp82xx_fw_hung = 1;
c8f6544e
CD		 4946 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
4947 qla82xx_clear_pending_mbx(vha);
a5b36321 4948 }
90a86fc0 4949 qla2x00_free_irqs(vha);
14e660e6 4950 pci_disable_device(pdev);
bddd2d65
LC		 4951 /* Return back all IOs */
4952 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
14e660e6
SJ		 4953 return PCI_ERS_RESULT_NEED_RESET;
4954 case pci_channel_io_perm_failure:
85880801
AV		 4955 ha->flags.pci_channel_io_perm_failure = 1;
4956 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
14e660e6
SJ		 4957 return PCI_ERS_RESULT_DISCONNECT;
4958 }
4959 return PCI_ERS_RESULT_NEED_RESET;
4960}
4961
4962static pci_ers_result_t
4963qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
4964{
4965 int risc_paused = 0;
4966 uint32_t stat;
4967 unsigned long flags;
e315cd28
AC		 4968 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
4969 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 4970 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
4971 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
4972
bcc5b6d3
SK		 4973 if (IS_QLA82XX(ha))
4974 return PCI_ERS_RESULT_RECOVERED;
4975
14e660e6
SJ		 4976 spin_lock_irqsave(&ha->hardware_lock, flags);
4977 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
4978 stat = RD_REG_DWORD(&reg->hccr);
4979 if (stat & HCCR_RISC_PAUSE)
4980 risc_paused = 1;
4981 } else if (IS_QLA23XX(ha)) {
4982 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
4983 if (stat & HSR_RISC_PAUSED)
4984 risc_paused = 1;
4985 } else if (IS_FWI2_CAPABLE(ha)) {
4986 stat = RD_REG_DWORD(&reg24->host_status);
4987 if (stat & HSRX_RISC_PAUSED)
4988 risc_paused = 1;
4989 }
4990 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4991
4992 if (risc_paused) {
7c3df132
SK		 4993 ql_log(ql_log_info, base_vha, 0x9003,
4994 "RISC paused -- mmio_enabled, Dumping firmware.\n");
e315cd28 4995 ha->isp_ops->fw_dump(base_vha, 0);
14e660e6
SJ		 4996
4997 return PCI_ERS_RESULT_NEED_RESET;
4998 } else
4999 return PCI_ERS_RESULT_RECOVERED;
5000}
5001
fa492630
SK		 5002static uint32_t
5003qla82xx_error_recovery(scsi_qla_host_t *base_vha)
a5b36321
LC		 5004{
5005 uint32_t rval = QLA_FUNCTION_FAILED;
5006 uint32_t drv_active = 0;
5007 struct qla_hw_data *ha = base_vha->hw;
5008 int fn;
5009 struct pci_dev *other_pdev = NULL;
5010
7c3df132
SK		 5011 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
5012 "Entered %s.\n", __func__);
a5b36321
LC		 5013
5014 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5015
5016 if (base_vha->flags.online) {
5017 /* Abort all outstanding commands,
5018 * so as to be requeued later */
5019 qla2x00_abort_isp_cleanup(base_vha);
5020 }
5021
5022
5023 fn = PCI_FUNC(ha->pdev->devfn);
5024 while (fn > 0) {
5025 fn--;
7c3df132
SK		 5026 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
5027 "Finding pci device at function = 0x%x.\n", fn);
a5b36321
LC		 5028 other_pdev =
5029 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
5030 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
5031 fn));
5032
5033 if (!other_pdev)
5034 continue;
5035 if (atomic_read(&other_pdev->enable_cnt)) {
7c3df132
SK		 5036 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
5037 "Found PCI func available and enable at 0x%x.\n",
5038 fn);
a5b36321
LC		 5039 pci_dev_put(other_pdev);
5040 break;
5041 }
5042 pci_dev_put(other_pdev);
5043 }
5044
5045 if (!fn) {
5046 /* Reset owner */
7c3df132
SK		 5047 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
5048 "This devfn is reset owner = 0x%x.\n",
5049 ha->pdev->devfn);
a5b36321
LC		 5050 qla82xx_idc_lock(ha);
5051
5052 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5053 QLA8XXX_DEV_INITIALIZING);
a5b36321
LC		 5054
5055 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
5056 QLA82XX_IDC_VERSION);
5057
5058 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
7c3df132
SK		 5059 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
5060 "drv_active = 0x%x.\n", drv_active);
a5b36321
LC		 5061
5062 qla82xx_idc_unlock(ha);
5063 /* Reset if device is not already reset
5064 * drv_active would be 0 if a reset has already been done
5065 */
5066 if (drv_active)
5067 rval = qla82xx_start_firmware(base_vha);
5068 else
5069 rval = QLA_SUCCESS;
5070 qla82xx_idc_lock(ha);
5071
5072 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5073 ql_log(ql_log_info, base_vha, 0x900b,
5074 "HW State: FAILED.\n");
a5b36321
LC		 5075 qla82xx_clear_drv_active(ha);
5076 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5077 QLA8XXX_DEV_FAILED);
a5b36321 5078 } else {
7c3df132
SK		 5079 ql_log(ql_log_info, base_vha, 0x900c,
5080 "HW State: READY.\n");
a5b36321 5081 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5082 QLA8XXX_DEV_READY);
a5b36321 5083 qla82xx_idc_unlock(ha);
7190575f 5084 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 5085 rval = qla82xx_restart_isp(base_vha);
5086 qla82xx_idc_lock(ha);
5087 /* Clear driver state register */
5088 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
5089 qla82xx_set_drv_active(base_vha);
5090 }
5091 qla82xx_idc_unlock(ha);
5092 } else {
7c3df132
SK		 5093 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
5094 "This devfn is not reset owner = 0x%x.\n",
5095 ha->pdev->devfn);
a5b36321 5096 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
7d613ac6 5097 QLA8XXX_DEV_READY)) {
7190575f 5098 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 5099 rval = qla82xx_restart_isp(base_vha);
5100 qla82xx_idc_lock(ha);
5101 qla82xx_set_drv_active(base_vha);
5102 qla82xx_idc_unlock(ha);
5103 }
5104 }
5105 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5106
5107 return rval;
5108}
5109
14e660e6
SJ		 5110static pci_ers_result_t
5111qla2xxx_pci_slot_reset(struct pci_dev *pdev)
5112{
5113 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
e315cd28
AC		 5114 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5115 struct qla_hw_data *ha = base_vha->hw;
90a86fc0
JC		 5116 struct rsp_que *rsp;
5117 int rc, retries = 10;
09483916 5118
7c3df132
SK		 5119 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
5120 "Slot Reset.\n");
85880801 5121
90a86fc0
JC		 5122 /* Workaround: qla2xxx driver which access hardware earlier
5123 * needs error state to be pci_channel_io_online.
5124 * Otherwise mailbox command timesout.
5125 */
5126 pdev->error_state = pci_channel_io_normal;
5127
5128 pci_restore_state(pdev);
5129
8c1496bd
RL		 5130 /* pci_restore_state() clears the saved_state flag of the device
5131 * save restored state which resets saved_state flag
5132 */
5133 pci_save_state(pdev);
5134
09483916
BH		 5135 if (ha->mem_only)
5136 rc = pci_enable_device_mem(pdev);
5137 else
5138 rc = pci_enable_device(pdev);
14e660e6 5139
09483916 5140 if (rc) {
7c3df132 5141 ql_log(ql_log_warn, base_vha, 0x9005,
14e660e6 5142 "Can't re-enable PCI device after reset.\n");
a5b36321 5143 goto exit_slot_reset;
14e660e6 5144 }
14e660e6 5145
90a86fc0
JC		 5146 rsp = ha->rsp_q_map[0];
5147 if (qla2x00_request_irqs(ha, rsp))
a5b36321 5148 goto exit_slot_reset;
90a86fc0 5149
e315cd28 5150 if (ha->isp_ops->pci_config(base_vha))
a5b36321
LC		 5151 goto exit_slot_reset;
5152
5153 if (IS_QLA82XX(ha)) {
5154 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
5155 ret = PCI_ERS_RESULT_RECOVERED;
5156 goto exit_slot_reset;
5157 } else
5158 goto exit_slot_reset;
5159 }
14e660e6 5160
90a86fc0
JC		 5161 while (ha->flags.mbox_busy && retries--)
5162 msleep(1000);
85880801 5163
e315cd28 5164 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 5165 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
14e660e6 5166 ret = PCI_ERS_RESULT_RECOVERED;
e315cd28 5167 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
14e660e6 5168
90a86fc0 5169
a5b36321 5170exit_slot_reset:
7c3df132
SK		 5171 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
5172 "slot_reset return %x.\n", ret);
85880801 5173
14e660e6
SJ		 5174 return ret;
5175}
5176
5177static void
5178qla2xxx_pci_resume(struct pci_dev *pdev)
5179{
e315cd28
AC		 5180 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5181 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 5182 int ret;
5183
7c3df132
SK		 5184 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
5185 "pci_resume.\n");
85880801 5186
e315cd28 5187 ret = qla2x00_wait_for_hba_online(base_vha);
14e660e6 5188 if (ret != QLA_SUCCESS) {
7c3df132
SK		 5189 ql_log(ql_log_fatal, base_vha, 0x9002,
5190 "The device failed to resume I/O from slot/link_reset.\n");
14e660e6 5191 }
85880801 5192
3e46f031
LC		 5193 pci_cleanup_aer_uncorrect_error_status(pdev);
5194
85880801 5195 ha->flags.eeh_busy = 0;
14e660e6
SJ		 5196}
5197
a55b2d21 5198static const struct pci_error_handlers qla2xxx_err_handler = {
14e660e6
SJ		 5199 .error_detected = qla2xxx_pci_error_detected,
5200 .mmio_enabled = qla2xxx_pci_mmio_enabled,
5201 .slot_reset = qla2xxx_pci_slot_reset,
5202 .resume = qla2xxx_pci_resume,
5203};
5204
5433383e 5205static struct pci_device_id qla2xxx_pci_tbl[] = {
47f5e069
AV		 5206 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
5207 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
5208 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
5209 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
5210 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
5211 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
5212 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
5213 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
5214 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
4d4df193 5215 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
47f5e069
AV		 5216 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
5217 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
c3a2f0df 5218 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
6246b8a1 5219 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
3a03eb79 5220 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
a9083016 5221 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
650f528f 5222 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
5433383e
AV		 5223 { 0 },
5224};
5225MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
5226
fca29703 5227static struct pci_driver qla2xxx_pci_driver = {
cb63067a 5228 .name = QLA2XXX_DRIVER_NAME,
0a21ef1e
JB		 5229 .driver = {
5230 .owner = THIS_MODULE,
5231 },
fca29703 5232 .id_table = qla2xxx_pci_tbl,
7ee61397 5233 .probe = qla2x00_probe_one,
4c993f76 5234 .remove = qla2x00_remove_one,
e30d1756 5235 .shutdown = qla2x00_shutdown,
14e660e6 5236 .err_handler = &qla2xxx_err_handler,
fca29703
AV		 5237};
5238
6a03b4cd
HZ		 5239static struct file_operations apidev_fops = {
5240 .owner = THIS_MODULE,
6038f373 5241 .llseek = noop_llseek,
6a03b4cd
HZ		 5242};
5243
1da177e4
LT		 5244/**
5245 * qla2x00_module_init - Module initialization.
5246 **/
5247static int __init
5248qla2x00_module_init(void)
5249{
fca29703
AV		 5250 int ret = 0;
5251
1da177e4 5252 /* Allocate cache for SRBs. */
354d6b21 5253 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
20c2df83 5254 SLAB_HWCACHE_ALIGN, NULL);
1da177e4 5255 if (srb_cachep == NULL) {
7c3df132
SK		 5256 ql_log(ql_log_fatal, NULL, 0x0001,
5257 "Unable to allocate SRB cache...Failing load!.\n");
1da177e4
LT		 5258 return -ENOMEM;
5259 }
5260
2d70c103
NB		 5261 /* Initialize target kmem_cache and mem_pools */
5262 ret = qlt_init();
5263 if (ret < 0) {
5264 kmem_cache_destroy(srb_cachep);
5265 return ret;
5266 } else if (ret > 0) {
5267 /*
5268 * If initiator mode is explictly disabled by qlt_init(),
5269 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
5270 * performing scsi_scan_target() during LOOP UP event.
5271 */
5272 qla2xxx_transport_functions.disable_target_scan = 1;
5273 qla2xxx_transport_vport_functions.disable_target_scan = 1;
5274 }
5275
1da177e4
LT		 5276 /* Derive version string. */
5277 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
11010fec 5278 if (ql2xextended_error_logging)
0181944f
AV		 5279 strcat(qla2x00_version_str, "-debug");
5280
1c97a12a
AV		 5281 qla2xxx_transport_template =
5282 fc_attach_transport(&qla2xxx_transport_functions);
2c3dfe3f
SJ		 5283 if (!qla2xxx_transport_template) {
5284 kmem_cache_destroy(srb_cachep);
7c3df132
SK		 5285 ql_log(ql_log_fatal, NULL, 0x0002,
5286 "fc_attach_transport failed...Failing load!.\n");
2d70c103 5287 qlt_exit();
1da177e4 5288 return -ENODEV;
2c3dfe3f 5289 }
6a03b4cd
HZ		 5290
5291 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
5292 if (apidev_major < 0) {
7c3df132
SK		 5293 ql_log(ql_log_fatal, NULL, 0x0003,
5294 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6a03b4cd
HZ		 5295 }
5296
2c3dfe3f
SJ		 5297 qla2xxx_transport_vport_template =
5298 fc_attach_transport(&qla2xxx_transport_vport_functions);
5299 if (!qla2xxx_transport_vport_template) {
5300 kmem_cache_destroy(srb_cachep);
2d70c103 5301 qlt_exit();
2c3dfe3f 5302 fc_release_transport(qla2xxx_transport_template);
7c3df132
SK		 5303 ql_log(ql_log_fatal, NULL, 0x0004,
5304 "fc_attach_transport vport failed...Failing load!.\n");
1da177e4 5305 return -ENODEV;
2c3dfe3f 5306 }
7c3df132
SK		 5307 ql_log(ql_log_info, NULL, 0x0005,
5308 "QLogic Fibre Channel HBA Driver: %s.\n",
fd9a29f0 5309 qla2x00_version_str);
7ee61397 5310 ret = pci_register_driver(&qla2xxx_pci_driver);
fca29703
AV		 5311 if (ret) {
5312 kmem_cache_destroy(srb_cachep);
2d70c103 5313 qlt_exit();
fca29703 5314 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 5315 fc_release_transport(qla2xxx_transport_vport_template);
7c3df132
SK		 5316 ql_log(ql_log_fatal, NULL, 0x0006,
5317 "pci_register_driver failed...ret=%d Failing load!.\n",
5318 ret);
fca29703
AV		 5319 }
5320 return ret;
1da177e4
LT		 5321}
5322
5323/**
5324 * qla2x00_module_exit - Module cleanup.
5325 **/
5326static void __exit
5327qla2x00_module_exit(void)
5328{
6a03b4cd 5329 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7ee61397 5330 pci_unregister_driver(&qla2xxx_pci_driver);
5433383e 5331 qla2x00_release_firmware();
354d6b21 5332 kmem_cache_destroy(srb_cachep);
2d70c103 5333 qlt_exit();
a9083016
GM		 5334 if (ctx_cachep)
5335 kmem_cache_destroy(ctx_cachep);
1da177e4 5336 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 5337 fc_release_transport(qla2xxx_transport_vport_template);
1da177e4
LT		 5338}
5339
5340module_init(qla2x00_module_init);
5341module_exit(qla2x00_module_exit);
5342
5343MODULE_AUTHOR("QLogic Corporation");
5344MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
5345MODULE_LICENSE("GPL");
5346MODULE_VERSION(QLA2XXX_VERSION);
bb8ee499
AV		 5347MODULE_FIRMWARE(FW_FILE_ISP21XX);
5348MODULE_FIRMWARE(FW_FILE_ISP22XX);
5349MODULE_FIRMWARE(FW_FILE_ISP2300);
5350MODULE_FIRMWARE(FW_FILE_ISP2322);
5351MODULE_FIRMWARE(FW_FILE_ISP24XX);
61623fc3 5352MODULE_FIRMWARE(FW_FILE_ISP25XX);
Linux kernel - Deliverables
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