Commit | Line | Data |
---|---|---|
fa90c54f AV |
1 | /* |
2 | * QLogic Fibre Channel HBA Driver | |
01e58d8e | 3 | * Copyright (c) 2003-2008 QLogic Corporation |
1da177e4 | 4 | * |
fa90c54f AV |
5 | * See LICENSE.qla2xxx for copyright and licensing details. |
6 | */ | |
1da177e4 LT |
7 | #include "qla_def.h" |
8 | ||
9 | #include <linux/delay.h> | |
2c96d8d0 | 10 | #include <linux/vmalloc.h> |
1da177e4 LT |
11 | #include <asm/uaccess.h> |
12 | ||
13 | static uint16_t qla2x00_nvram_request(scsi_qla_host_t *, uint32_t); | |
14 | static void qla2x00_nv_deselect(scsi_qla_host_t *); | |
15 | static void qla2x00_nv_write(scsi_qla_host_t *, uint16_t); | |
16 | ||
17 | /* | |
18 | * NVRAM support routines | |
19 | */ | |
20 | ||
21 | /** | |
fa2a1ce5 | 22 | * qla2x00_lock_nvram_access() - |
1da177e4 LT |
23 | * @ha: HA context |
24 | */ | |
a824ebb3 | 25 | static void |
1da177e4 LT |
26 | qla2x00_lock_nvram_access(scsi_qla_host_t *ha) |
27 | { | |
28 | uint16_t data; | |
3d71644c | 29 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
1da177e4 LT |
30 | |
31 | if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) { | |
32 | data = RD_REG_WORD(®->nvram); | |
33 | while (data & NVR_BUSY) { | |
34 | udelay(100); | |
35 | data = RD_REG_WORD(®->nvram); | |
36 | } | |
37 | ||
38 | /* Lock resource */ | |
39 | WRT_REG_WORD(®->u.isp2300.host_semaphore, 0x1); | |
40 | RD_REG_WORD(®->u.isp2300.host_semaphore); | |
41 | udelay(5); | |
42 | data = RD_REG_WORD(®->u.isp2300.host_semaphore); | |
43 | while ((data & BIT_0) == 0) { | |
44 | /* Lock failed */ | |
45 | udelay(100); | |
46 | WRT_REG_WORD(®->u.isp2300.host_semaphore, 0x1); | |
47 | RD_REG_WORD(®->u.isp2300.host_semaphore); | |
48 | udelay(5); | |
49 | data = RD_REG_WORD(®->u.isp2300.host_semaphore); | |
50 | } | |
51 | } | |
52 | } | |
53 | ||
54 | /** | |
fa2a1ce5 | 55 | * qla2x00_unlock_nvram_access() - |
1da177e4 LT |
56 | * @ha: HA context |
57 | */ | |
a824ebb3 | 58 | static void |
1da177e4 LT |
59 | qla2x00_unlock_nvram_access(scsi_qla_host_t *ha) |
60 | { | |
3d71644c | 61 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
1da177e4 LT |
62 | |
63 | if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) { | |
64 | WRT_REG_WORD(®->u.isp2300.host_semaphore, 0); | |
65 | RD_REG_WORD(®->u.isp2300.host_semaphore); | |
66 | } | |
67 | } | |
68 | ||
1da177e4 LT |
69 | /** |
70 | * qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the | |
71 | * request routine to get the word from NVRAM. | |
72 | * @ha: HA context | |
73 | * @addr: Address in NVRAM to read | |
74 | * | |
75 | * Returns the word read from nvram @addr. | |
76 | */ | |
a824ebb3 | 77 | static uint16_t |
1da177e4 LT |
78 | qla2x00_get_nvram_word(scsi_qla_host_t *ha, uint32_t addr) |
79 | { | |
80 | uint16_t data; | |
81 | uint32_t nv_cmd; | |
82 | ||
83 | nv_cmd = addr << 16; | |
84 | nv_cmd |= NV_READ_OP; | |
85 | data = qla2x00_nvram_request(ha, nv_cmd); | |
86 | ||
87 | return (data); | |
88 | } | |
89 | ||
90 | /** | |
91 | * qla2x00_write_nvram_word() - Write NVRAM data. | |
92 | * @ha: HA context | |
93 | * @addr: Address in NVRAM to write | |
94 | * @data: word to program | |
95 | */ | |
a824ebb3 | 96 | static void |
1da177e4 LT |
97 | qla2x00_write_nvram_word(scsi_qla_host_t *ha, uint32_t addr, uint16_t data) |
98 | { | |
99 | int count; | |
100 | uint16_t word; | |
45aeaf1e | 101 | uint32_t nv_cmd, wait_cnt; |
3d71644c | 102 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
1da177e4 LT |
103 | |
104 | qla2x00_nv_write(ha, NVR_DATA_OUT); | |
105 | qla2x00_nv_write(ha, 0); | |
106 | qla2x00_nv_write(ha, 0); | |
107 | ||
108 | for (word = 0; word < 8; word++) | |
109 | qla2x00_nv_write(ha, NVR_DATA_OUT); | |
110 | ||
111 | qla2x00_nv_deselect(ha); | |
112 | ||
113 | /* Write data */ | |
114 | nv_cmd = (addr << 16) | NV_WRITE_OP; | |
115 | nv_cmd |= data; | |
116 | nv_cmd <<= 5; | |
117 | for (count = 0; count < 27; count++) { | |
118 | if (nv_cmd & BIT_31) | |
119 | qla2x00_nv_write(ha, NVR_DATA_OUT); | |
120 | else | |
121 | qla2x00_nv_write(ha, 0); | |
122 | ||
123 | nv_cmd <<= 1; | |
124 | } | |
125 | ||
126 | qla2x00_nv_deselect(ha); | |
127 | ||
128 | /* Wait for NVRAM to become ready */ | |
129 | WRT_REG_WORD(®->nvram, NVR_SELECT); | |
dcb36ce9 | 130 | RD_REG_WORD(®->nvram); /* PCI Posting. */ |
45aeaf1e | 131 | wait_cnt = NVR_WAIT_CNT; |
1da177e4 | 132 | do { |
45aeaf1e RA |
133 | if (!--wait_cnt) { |
134 | DEBUG9_10(printk("%s(%ld): NVRAM didn't go ready...\n", | |
135 | __func__, ha->host_no)); | |
136 | break; | |
137 | } | |
1da177e4 LT |
138 | NVRAM_DELAY(); |
139 | word = RD_REG_WORD(®->nvram); | |
140 | } while ((word & NVR_DATA_IN) == 0); | |
141 | ||
142 | qla2x00_nv_deselect(ha); | |
143 | ||
144 | /* Disable writes */ | |
145 | qla2x00_nv_write(ha, NVR_DATA_OUT); | |
146 | for (count = 0; count < 10; count++) | |
147 | qla2x00_nv_write(ha, 0); | |
148 | ||
149 | qla2x00_nv_deselect(ha); | |
150 | } | |
151 | ||
459c5378 AV |
152 | static int |
153 | qla2x00_write_nvram_word_tmo(scsi_qla_host_t *ha, uint32_t addr, uint16_t data, | |
154 | uint32_t tmo) | |
155 | { | |
156 | int ret, count; | |
157 | uint16_t word; | |
158 | uint32_t nv_cmd; | |
159 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; | |
160 | ||
161 | ret = QLA_SUCCESS; | |
162 | ||
163 | qla2x00_nv_write(ha, NVR_DATA_OUT); | |
164 | qla2x00_nv_write(ha, 0); | |
165 | qla2x00_nv_write(ha, 0); | |
166 | ||
167 | for (word = 0; word < 8; word++) | |
168 | qla2x00_nv_write(ha, NVR_DATA_OUT); | |
169 | ||
170 | qla2x00_nv_deselect(ha); | |
171 | ||
172 | /* Write data */ | |
173 | nv_cmd = (addr << 16) | NV_WRITE_OP; | |
174 | nv_cmd |= data; | |
175 | nv_cmd <<= 5; | |
176 | for (count = 0; count < 27; count++) { | |
177 | if (nv_cmd & BIT_31) | |
178 | qla2x00_nv_write(ha, NVR_DATA_OUT); | |
179 | else | |
180 | qla2x00_nv_write(ha, 0); | |
181 | ||
182 | nv_cmd <<= 1; | |
183 | } | |
184 | ||
185 | qla2x00_nv_deselect(ha); | |
186 | ||
187 | /* Wait for NVRAM to become ready */ | |
188 | WRT_REG_WORD(®->nvram, NVR_SELECT); | |
dcb36ce9 | 189 | RD_REG_WORD(®->nvram); /* PCI Posting. */ |
459c5378 AV |
190 | do { |
191 | NVRAM_DELAY(); | |
192 | word = RD_REG_WORD(®->nvram); | |
193 | if (!--tmo) { | |
194 | ret = QLA_FUNCTION_FAILED; | |
195 | break; | |
196 | } | |
197 | } while ((word & NVR_DATA_IN) == 0); | |
198 | ||
199 | qla2x00_nv_deselect(ha); | |
200 | ||
201 | /* Disable writes */ | |
202 | qla2x00_nv_write(ha, NVR_DATA_OUT); | |
203 | for (count = 0; count < 10; count++) | |
204 | qla2x00_nv_write(ha, 0); | |
205 | ||
206 | qla2x00_nv_deselect(ha); | |
207 | ||
208 | return ret; | |
209 | } | |
210 | ||
1da177e4 LT |
211 | /** |
212 | * qla2x00_nvram_request() - Sends read command to NVRAM and gets data from | |
213 | * NVRAM. | |
214 | * @ha: HA context | |
215 | * @nv_cmd: NVRAM command | |
216 | * | |
217 | * Bit definitions for NVRAM command: | |
218 | * | |
219 | * Bit 26 = start bit | |
220 | * Bit 25, 24 = opcode | |
221 | * Bit 23-16 = address | |
222 | * Bit 15-0 = write data | |
223 | * | |
224 | * Returns the word read from nvram @addr. | |
225 | */ | |
226 | static uint16_t | |
227 | qla2x00_nvram_request(scsi_qla_host_t *ha, uint32_t nv_cmd) | |
228 | { | |
229 | uint8_t cnt; | |
3d71644c | 230 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
1da177e4 LT |
231 | uint16_t data = 0; |
232 | uint16_t reg_data; | |
233 | ||
234 | /* Send command to NVRAM. */ | |
235 | nv_cmd <<= 5; | |
236 | for (cnt = 0; cnt < 11; cnt++) { | |
237 | if (nv_cmd & BIT_31) | |
238 | qla2x00_nv_write(ha, NVR_DATA_OUT); | |
239 | else | |
240 | qla2x00_nv_write(ha, 0); | |
241 | nv_cmd <<= 1; | |
242 | } | |
243 | ||
244 | /* Read data from NVRAM. */ | |
245 | for (cnt = 0; cnt < 16; cnt++) { | |
246 | WRT_REG_WORD(®->nvram, NVR_SELECT | NVR_CLOCK); | |
dcb36ce9 | 247 | RD_REG_WORD(®->nvram); /* PCI Posting. */ |
1da177e4 LT |
248 | NVRAM_DELAY(); |
249 | data <<= 1; | |
250 | reg_data = RD_REG_WORD(®->nvram); | |
251 | if (reg_data & NVR_DATA_IN) | |
252 | data |= BIT_0; | |
253 | WRT_REG_WORD(®->nvram, NVR_SELECT); | |
254 | RD_REG_WORD(®->nvram); /* PCI Posting. */ | |
255 | NVRAM_DELAY(); | |
256 | } | |
257 | ||
258 | /* Deselect chip. */ | |
259 | WRT_REG_WORD(®->nvram, NVR_DESELECT); | |
260 | RD_REG_WORD(®->nvram); /* PCI Posting. */ | |
261 | NVRAM_DELAY(); | |
262 | ||
263 | return (data); | |
264 | } | |
265 | ||
266 | /** | |
267 | * qla2x00_nv_write() - Clean NVRAM operations. | |
268 | * @ha: HA context | |
269 | */ | |
270 | static void | |
271 | qla2x00_nv_deselect(scsi_qla_host_t *ha) | |
272 | { | |
3d71644c | 273 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
1da177e4 LT |
274 | |
275 | WRT_REG_WORD(®->nvram, NVR_DESELECT); | |
276 | RD_REG_WORD(®->nvram); /* PCI Posting. */ | |
277 | NVRAM_DELAY(); | |
278 | } | |
279 | ||
280 | /** | |
281 | * qla2x00_nv_write() - Prepare for NVRAM read/write operation. | |
282 | * @ha: HA context | |
283 | * @data: Serial interface selector | |
284 | */ | |
285 | static void | |
286 | qla2x00_nv_write(scsi_qla_host_t *ha, uint16_t data) | |
287 | { | |
3d71644c | 288 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
1da177e4 LT |
289 | |
290 | WRT_REG_WORD(®->nvram, data | NVR_SELECT | NVR_WRT_ENABLE); | |
291 | RD_REG_WORD(®->nvram); /* PCI Posting. */ | |
292 | NVRAM_DELAY(); | |
293 | WRT_REG_WORD(®->nvram, data | NVR_SELECT| NVR_CLOCK | | |
294 | NVR_WRT_ENABLE); | |
295 | RD_REG_WORD(®->nvram); /* PCI Posting. */ | |
296 | NVRAM_DELAY(); | |
297 | WRT_REG_WORD(®->nvram, data | NVR_SELECT | NVR_WRT_ENABLE); | |
298 | RD_REG_WORD(®->nvram); /* PCI Posting. */ | |
299 | NVRAM_DELAY(); | |
300 | } | |
301 | ||
459c5378 AV |
302 | /** |
303 | * qla2x00_clear_nvram_protection() - | |
304 | * @ha: HA context | |
305 | */ | |
306 | static int | |
307 | qla2x00_clear_nvram_protection(scsi_qla_host_t *ha) | |
308 | { | |
309 | int ret, stat; | |
310 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; | |
45aeaf1e | 311 | uint32_t word, wait_cnt; |
459c5378 AV |
312 | uint16_t wprot, wprot_old; |
313 | ||
314 | /* Clear NVRAM write protection. */ | |
315 | ret = QLA_FUNCTION_FAILED; | |
45aeaf1e RA |
316 | |
317 | wprot_old = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base)); | |
318 | stat = qla2x00_write_nvram_word_tmo(ha, ha->nvram_base, | |
459c5378 | 319 | __constant_cpu_to_le16(0x1234), 100000); |
45aeaf1e RA |
320 | wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base)); |
321 | if (stat != QLA_SUCCESS || wprot != 0x1234) { | |
459c5378 AV |
322 | /* Write enable. */ |
323 | qla2x00_nv_write(ha, NVR_DATA_OUT); | |
324 | qla2x00_nv_write(ha, 0); | |
325 | qla2x00_nv_write(ha, 0); | |
326 | for (word = 0; word < 8; word++) | |
327 | qla2x00_nv_write(ha, NVR_DATA_OUT); | |
328 | ||
329 | qla2x00_nv_deselect(ha); | |
330 | ||
331 | /* Enable protection register. */ | |
332 | qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); | |
333 | qla2x00_nv_write(ha, NVR_PR_ENABLE); | |
334 | qla2x00_nv_write(ha, NVR_PR_ENABLE); | |
335 | for (word = 0; word < 8; word++) | |
336 | qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE); | |
337 | ||
338 | qla2x00_nv_deselect(ha); | |
339 | ||
340 | /* Clear protection register (ffff is cleared). */ | |
341 | qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); | |
342 | qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); | |
343 | qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); | |
344 | for (word = 0; word < 8; word++) | |
345 | qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE); | |
346 | ||
347 | qla2x00_nv_deselect(ha); | |
348 | ||
349 | /* Wait for NVRAM to become ready. */ | |
350 | WRT_REG_WORD(®->nvram, NVR_SELECT); | |
dcb36ce9 | 351 | RD_REG_WORD(®->nvram); /* PCI Posting. */ |
45aeaf1e | 352 | wait_cnt = NVR_WAIT_CNT; |
459c5378 | 353 | do { |
45aeaf1e RA |
354 | if (!--wait_cnt) { |
355 | DEBUG9_10(printk("%s(%ld): NVRAM didn't go " | |
356 | "ready...\n", __func__, | |
357 | ha->host_no)); | |
358 | break; | |
359 | } | |
459c5378 AV |
360 | NVRAM_DELAY(); |
361 | word = RD_REG_WORD(®->nvram); | |
362 | } while ((word & NVR_DATA_IN) == 0); | |
363 | ||
45aeaf1e RA |
364 | if (wait_cnt) |
365 | ret = QLA_SUCCESS; | |
459c5378 | 366 | } else |
45aeaf1e | 367 | qla2x00_write_nvram_word(ha, ha->nvram_base, wprot_old); |
459c5378 AV |
368 | |
369 | return ret; | |
370 | } | |
371 | ||
372 | static void | |
373 | qla2x00_set_nvram_protection(scsi_qla_host_t *ha, int stat) | |
374 | { | |
375 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; | |
45aeaf1e | 376 | uint32_t word, wait_cnt; |
459c5378 AV |
377 | |
378 | if (stat != QLA_SUCCESS) | |
379 | return; | |
380 | ||
381 | /* Set NVRAM write protection. */ | |
382 | /* Write enable. */ | |
383 | qla2x00_nv_write(ha, NVR_DATA_OUT); | |
384 | qla2x00_nv_write(ha, 0); | |
385 | qla2x00_nv_write(ha, 0); | |
386 | for (word = 0; word < 8; word++) | |
387 | qla2x00_nv_write(ha, NVR_DATA_OUT); | |
388 | ||
389 | qla2x00_nv_deselect(ha); | |
390 | ||
391 | /* Enable protection register. */ | |
392 | qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); | |
393 | qla2x00_nv_write(ha, NVR_PR_ENABLE); | |
394 | qla2x00_nv_write(ha, NVR_PR_ENABLE); | |
395 | for (word = 0; word < 8; word++) | |
396 | qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE); | |
397 | ||
398 | qla2x00_nv_deselect(ha); | |
399 | ||
400 | /* Enable protection register. */ | |
401 | qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); | |
402 | qla2x00_nv_write(ha, NVR_PR_ENABLE); | |
403 | qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); | |
404 | for (word = 0; word < 8; word++) | |
405 | qla2x00_nv_write(ha, NVR_PR_ENABLE); | |
406 | ||
407 | qla2x00_nv_deselect(ha); | |
408 | ||
409 | /* Wait for NVRAM to become ready. */ | |
410 | WRT_REG_WORD(®->nvram, NVR_SELECT); | |
dcb36ce9 | 411 | RD_REG_WORD(®->nvram); /* PCI Posting. */ |
45aeaf1e | 412 | wait_cnt = NVR_WAIT_CNT; |
459c5378 | 413 | do { |
45aeaf1e RA |
414 | if (!--wait_cnt) { |
415 | DEBUG9_10(printk("%s(%ld): NVRAM didn't go ready...\n", | |
416 | __func__, ha->host_no)); | |
417 | break; | |
418 | } | |
459c5378 AV |
419 | NVRAM_DELAY(); |
420 | word = RD_REG_WORD(®->nvram); | |
421 | } while ((word & NVR_DATA_IN) == 0); | |
422 | } | |
423 | ||
424 | ||
425 | /*****************************************************************************/ | |
426 | /* Flash Manipulation Routines */ | |
427 | /*****************************************************************************/ | |
428 | ||
338c9161 AV |
429 | #define OPTROM_BURST_SIZE 0x1000 |
430 | #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4) | |
431 | ||
459c5378 AV |
432 | static inline uint32_t |
433 | flash_conf_to_access_addr(uint32_t faddr) | |
434 | { | |
435 | return FARX_ACCESS_FLASH_CONF | faddr; | |
436 | } | |
437 | ||
438 | static inline uint32_t | |
439 | flash_data_to_access_addr(uint32_t faddr) | |
440 | { | |
441 | return FARX_ACCESS_FLASH_DATA | faddr; | |
442 | } | |
443 | ||
444 | static inline uint32_t | |
445 | nvram_conf_to_access_addr(uint32_t naddr) | |
446 | { | |
447 | return FARX_ACCESS_NVRAM_CONF | naddr; | |
448 | } | |
449 | ||
450 | static inline uint32_t | |
451 | nvram_data_to_access_addr(uint32_t naddr) | |
452 | { | |
453 | return FARX_ACCESS_NVRAM_DATA | naddr; | |
454 | } | |
455 | ||
e5f82ab8 | 456 | static uint32_t |
459c5378 AV |
457 | qla24xx_read_flash_dword(scsi_qla_host_t *ha, uint32_t addr) |
458 | { | |
459 | int rval; | |
460 | uint32_t cnt, data; | |
461 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; | |
462 | ||
463 | WRT_REG_DWORD(®->flash_addr, addr & ~FARX_DATA_FLAG); | |
464 | /* Wait for READ cycle to complete. */ | |
465 | rval = QLA_SUCCESS; | |
466 | for (cnt = 3000; | |
467 | (RD_REG_DWORD(®->flash_addr) & FARX_DATA_FLAG) == 0 && | |
468 | rval == QLA_SUCCESS; cnt--) { | |
469 | if (cnt) | |
470 | udelay(10); | |
471 | else | |
472 | rval = QLA_FUNCTION_TIMEOUT; | |
40a2e34a | 473 | cond_resched(); |
459c5378 AV |
474 | } |
475 | ||
476 | /* TODO: What happens if we time out? */ | |
477 | data = 0xDEADDEAD; | |
478 | if (rval == QLA_SUCCESS) | |
479 | data = RD_REG_DWORD(®->flash_data); | |
480 | ||
481 | return data; | |
482 | } | |
483 | ||
484 | uint32_t * | |
485 | qla24xx_read_flash_data(scsi_qla_host_t *ha, uint32_t *dwptr, uint32_t faddr, | |
486 | uint32_t dwords) | |
487 | { | |
488 | uint32_t i; | |
459c5378 AV |
489 | |
490 | /* Dword reads to flash. */ | |
491 | for (i = 0; i < dwords; i++, faddr++) | |
492 | dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha, | |
493 | flash_data_to_access_addr(faddr))); | |
494 | ||
459c5378 AV |
495 | return dwptr; |
496 | } | |
497 | ||
e5f82ab8 | 498 | static int |
459c5378 AV |
499 | qla24xx_write_flash_dword(scsi_qla_host_t *ha, uint32_t addr, uint32_t data) |
500 | { | |
501 | int rval; | |
502 | uint32_t cnt; | |
503 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; | |
504 | ||
505 | WRT_REG_DWORD(®->flash_data, data); | |
506 | RD_REG_DWORD(®->flash_data); /* PCI Posting. */ | |
507 | WRT_REG_DWORD(®->flash_addr, addr | FARX_DATA_FLAG); | |
508 | /* Wait for Write cycle to complete. */ | |
509 | rval = QLA_SUCCESS; | |
510 | for (cnt = 500000; (RD_REG_DWORD(®->flash_addr) & FARX_DATA_FLAG) && | |
511 | rval == QLA_SUCCESS; cnt--) { | |
512 | if (cnt) | |
513 | udelay(10); | |
514 | else | |
515 | rval = QLA_FUNCTION_TIMEOUT; | |
40a2e34a | 516 | cond_resched(); |
459c5378 AV |
517 | } |
518 | return rval; | |
519 | } | |
520 | ||
e5f82ab8 | 521 | static void |
459c5378 AV |
522 | qla24xx_get_flash_manufacturer(scsi_qla_host_t *ha, uint8_t *man_id, |
523 | uint8_t *flash_id) | |
524 | { | |
525 | uint32_t ids; | |
526 | ||
527 | ids = qla24xx_read_flash_dword(ha, flash_data_to_access_addr(0xd03ab)); | |
528 | *man_id = LSB(ids); | |
529 | *flash_id = MSB(ids); | |
45aeaf1e RA |
530 | |
531 | /* Check if man_id and flash_id are valid. */ | |
532 | if (ids != 0xDEADDEAD && (*man_id == 0 || *flash_id == 0)) { | |
533 | /* Read information using 0x9f opcode | |
534 | * Device ID, Mfg ID would be read in the format: | |
535 | * <Ext Dev Info><Device ID Part2><Device ID Part 1><Mfg ID> | |
536 | * Example: ATMEL 0x00 01 45 1F | |
537 | * Extract MFG and Dev ID from last two bytes. | |
538 | */ | |
539 | ids = qla24xx_read_flash_dword(ha, | |
540 | flash_data_to_access_addr(0xd009f)); | |
541 | *man_id = LSB(ids); | |
542 | *flash_id = MSB(ids); | |
543 | } | |
459c5378 AV |
544 | } |
545 | ||
c00d8994 AV |
546 | static int |
547 | qla2xxx_find_flt_start(scsi_qla_host_t *ha, uint32_t *start) | |
548 | { | |
549 | const char *loc, *locations[] = { "DEF", "PCI" }; | |
550 | uint32_t pcihdr, pcids; | |
551 | uint32_t *dcode; | |
552 | uint8_t *buf, *bcode, last_image; | |
553 | uint16_t cnt, chksum, *wptr; | |
554 | struct qla_flt_location *fltl; | |
555 | ||
556 | /* | |
557 | * FLT-location structure resides after the last PCI region. | |
558 | */ | |
559 | ||
560 | /* Begin with sane defaults. */ | |
561 | loc = locations[0]; | |
562 | *start = IS_QLA24XX_TYPE(ha) ? FA_FLASH_LAYOUT_ADDR_24: | |
563 | FA_FLASH_LAYOUT_ADDR; | |
564 | ||
565 | /* Begin with first PCI expansion ROM header. */ | |
566 | buf = (uint8_t *)ha->request_ring; | |
567 | dcode = (uint32_t *)ha->request_ring; | |
568 | pcihdr = 0; | |
569 | last_image = 1; | |
570 | do { | |
571 | /* Verify PCI expansion ROM header. */ | |
572 | qla24xx_read_flash_data(ha, dcode, pcihdr >> 2, 0x20); | |
573 | bcode = buf + (pcihdr % 4); | |
574 | if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa) | |
575 | goto end; | |
576 | ||
577 | /* Locate PCI data structure. */ | |
578 | pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]); | |
579 | qla24xx_read_flash_data(ha, dcode, pcids >> 2, 0x20); | |
580 | bcode = buf + (pcihdr % 4); | |
581 | ||
582 | /* Validate signature of PCI data structure. */ | |
583 | if (bcode[0x0] != 'P' || bcode[0x1] != 'C' || | |
584 | bcode[0x2] != 'I' || bcode[0x3] != 'R') | |
585 | goto end; | |
586 | ||
587 | last_image = bcode[0x15] & BIT_7; | |
588 | ||
589 | /* Locate next PCI expansion ROM. */ | |
590 | pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512; | |
591 | } while (!last_image); | |
592 | ||
593 | /* Now verify FLT-location structure. */ | |
594 | fltl = (struct qla_flt_location *)ha->request_ring; | |
595 | qla24xx_read_flash_data(ha, dcode, pcihdr >> 2, | |
596 | sizeof(struct qla_flt_location) >> 2); | |
597 | if (fltl->sig[0] != 'Q' || fltl->sig[1] != 'F' || | |
598 | fltl->sig[2] != 'L' || fltl->sig[3] != 'T') | |
599 | goto end; | |
600 | ||
601 | wptr = (uint16_t *)ha->request_ring; | |
602 | cnt = sizeof(struct qla_flt_location) >> 1; | |
603 | for (chksum = 0; cnt; cnt--) | |
604 | chksum += le16_to_cpu(*wptr++); | |
605 | if (chksum) { | |
606 | qla_printk(KERN_ERR, ha, | |
607 | "Inconsistent FLTL detected: checksum=0x%x.\n", chksum); | |
608 | qla2x00_dump_buffer(buf, sizeof(struct qla_flt_location)); | |
609 | return QLA_FUNCTION_FAILED; | |
610 | } | |
611 | ||
612 | /* Good data. Use specified location. */ | |
613 | loc = locations[1]; | |
614 | *start = le16_to_cpu(fltl->start_hi) << 16 | | |
615 | le16_to_cpu(fltl->start_lo); | |
616 | end: | |
617 | DEBUG2(qla_printk(KERN_DEBUG, ha, "FLTL[%s] = 0x%x.\n", loc, *start)); | |
618 | return QLA_SUCCESS; | |
619 | } | |
620 | ||
621 | static void | |
622 | qla2xxx_get_flt_info(scsi_qla_host_t *ha, uint32_t flt_addr) | |
623 | { | |
624 | const char *loc, *locations[] = { "DEF", "FLT" }; | |
625 | uint16_t *wptr; | |
626 | uint16_t cnt, chksum; | |
627 | uint32_t start; | |
628 | struct qla_flt_header *flt; | |
629 | struct qla_flt_region *region; | |
630 | ||
631 | ha->flt_region_flt = flt_addr; | |
632 | wptr = (uint16_t *)ha->request_ring; | |
633 | flt = (struct qla_flt_header *)ha->request_ring; | |
634 | region = (struct qla_flt_region *)&flt[1]; | |
635 | ha->isp_ops->read_optrom(ha, (uint8_t *)ha->request_ring, | |
636 | flt_addr << 2, OPTROM_BURST_SIZE); | |
637 | if (*wptr == __constant_cpu_to_le16(0xffff)) | |
638 | goto no_flash_data; | |
639 | if (flt->version != __constant_cpu_to_le16(1)) { | |
640 | DEBUG2(qla_printk(KERN_INFO, ha, "Unsupported FLT detected: " | |
641 | "version=0x%x length=0x%x checksum=0x%x.\n", | |
642 | le16_to_cpu(flt->version), le16_to_cpu(flt->length), | |
643 | le16_to_cpu(flt->checksum))); | |
644 | goto no_flash_data; | |
645 | } | |
646 | ||
647 | cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1; | |
648 | for (chksum = 0; cnt; cnt--) | |
649 | chksum += le16_to_cpu(*wptr++); | |
650 | if (chksum) { | |
651 | DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent FLT detected: " | |
652 | "version=0x%x length=0x%x checksum=0x%x.\n", | |
653 | le16_to_cpu(flt->version), le16_to_cpu(flt->length), | |
654 | chksum)); | |
655 | goto no_flash_data; | |
656 | } | |
657 | ||
658 | loc = locations[1]; | |
659 | cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region); | |
660 | for ( ; cnt; cnt--, region++) { | |
661 | /* Store addresses as DWORD offsets. */ | |
662 | start = le32_to_cpu(region->start) >> 2; | |
663 | ||
664 | DEBUG3(qla_printk(KERN_DEBUG, ha, "FLT[%02x]: start=0x%x " | |
665 | "end=0x%x size=0x%x.\n", le32_to_cpu(region->code), start, | |
666 | le32_to_cpu(region->end) >> 2, le32_to_cpu(region->size))); | |
667 | ||
668 | switch (le32_to_cpu(region->code)) { | |
669 | case FLT_REG_FW: | |
670 | ha->flt_region_fw = start; | |
671 | break; | |
672 | case FLT_REG_BOOT_CODE: | |
673 | ha->flt_region_boot = start; | |
674 | break; | |
675 | case FLT_REG_VPD_0: | |
676 | ha->flt_region_vpd_nvram = start; | |
677 | break; | |
678 | case FLT_REG_FDT: | |
679 | ha->flt_region_fdt = start; | |
680 | break; | |
681 | case FLT_REG_HW_EVENT_0: | |
682 | if (!PCI_FUNC(ha->pdev->devfn)) | |
683 | ha->flt_region_hw_event = start; | |
684 | break; | |
685 | case FLT_REG_HW_EVENT_1: | |
686 | if (PCI_FUNC(ha->pdev->devfn)) | |
687 | ha->flt_region_hw_event = start; | |
688 | break; | |
272976ca AV |
689 | case FLT_REG_NPIV_CONF_0: |
690 | if (!PCI_FUNC(ha->pdev->devfn)) | |
691 | ha->flt_region_npiv_conf = start; | |
692 | break; | |
693 | case FLT_REG_NPIV_CONF_1: | |
694 | if (PCI_FUNC(ha->pdev->devfn)) | |
695 | ha->flt_region_npiv_conf = start; | |
696 | break; | |
c00d8994 AV |
697 | } |
698 | } | |
699 | goto done; | |
700 | ||
701 | no_flash_data: | |
702 | /* Use hardcoded defaults. */ | |
703 | loc = locations[0]; | |
704 | ha->flt_region_fw = FA_RISC_CODE_ADDR; | |
705 | ha->flt_region_boot = FA_BOOT_CODE_ADDR; | |
706 | ha->flt_region_vpd_nvram = FA_VPD_NVRAM_ADDR; | |
707 | ha->flt_region_fdt = IS_QLA24XX_TYPE(ha) ? FA_FLASH_DESCR_ADDR_24: | |
708 | FA_FLASH_DESCR_ADDR; | |
709 | ha->flt_region_hw_event = !PCI_FUNC(ha->pdev->devfn) ? | |
710 | FA_HW_EVENT0_ADDR: FA_HW_EVENT1_ADDR; | |
272976ca AV |
711 | ha->flt_region_npiv_conf = !PCI_FUNC(ha->pdev->devfn) ? |
712 | (IS_QLA24XX_TYPE(ha) ? FA_NPIV_CONF0_ADDR_24: FA_NPIV_CONF0_ADDR): | |
713 | (IS_QLA24XX_TYPE(ha) ? FA_NPIV_CONF1_ADDR_24: FA_NPIV_CONF1_ADDR); | |
c00d8994 AV |
714 | done: |
715 | DEBUG2(qla_printk(KERN_DEBUG, ha, "FLT[%s]: boot=0x%x fw=0x%x " | |
272976ca | 716 | "vpd_nvram=0x%x fdt=0x%x flt=0x%x hwe=0x%x npiv=0x%x.\n", loc, |
c00d8994 | 717 | ha->flt_region_boot, ha->flt_region_fw, ha->flt_region_vpd_nvram, |
272976ca AV |
718 | ha->flt_region_fdt, ha->flt_region_flt, ha->flt_region_hw_event, |
719 | ha->flt_region_npiv_conf)); | |
c00d8994 AV |
720 | } |
721 | ||
722 | static void | |
723 | qla2xxx_get_fdt_info(scsi_qla_host_t *ha) | |
7d232c74 | 724 | { |
821b3996 | 725 | #define FLASH_BLK_SIZE_4K 0x1000 |
7d232c74 AV |
726 | #define FLASH_BLK_SIZE_32K 0x8000 |
727 | #define FLASH_BLK_SIZE_64K 0x10000 | |
c00d8994 | 728 | const char *loc, *locations[] = { "MID", "FDT" }; |
7d232c74 AV |
729 | uint16_t cnt, chksum; |
730 | uint16_t *wptr; | |
731 | struct qla_fdt_layout *fdt; | |
732 | uint8_t man_id, flash_id; | |
c00d8994 | 733 | uint16_t mid, fid; |
7d232c74 AV |
734 | |
735 | wptr = (uint16_t *)ha->request_ring; | |
736 | fdt = (struct qla_fdt_layout *)ha->request_ring; | |
737 | ha->isp_ops->read_optrom(ha, (uint8_t *)ha->request_ring, | |
c00d8994 | 738 | ha->flt_region_fdt << 2, OPTROM_BURST_SIZE); |
7d232c74 AV |
739 | if (*wptr == __constant_cpu_to_le16(0xffff)) |
740 | goto no_flash_data; | |
741 | if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' || | |
742 | fdt->sig[3] != 'D') | |
743 | goto no_flash_data; | |
744 | ||
745 | for (cnt = 0, chksum = 0; cnt < sizeof(struct qla_fdt_layout) >> 1; | |
746 | cnt++) | |
747 | chksum += le16_to_cpu(*wptr++); | |
748 | if (chksum) { | |
749 | DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent FDT detected: " | |
750 | "checksum=0x%x id=%c version=0x%x.\n", chksum, fdt->sig[0], | |
751 | le16_to_cpu(fdt->version))); | |
752 | DEBUG9(qla2x00_dump_buffer((uint8_t *)fdt, sizeof(*fdt))); | |
753 | goto no_flash_data; | |
754 | } | |
755 | ||
c00d8994 AV |
756 | loc = locations[1]; |
757 | mid = le16_to_cpu(fdt->man_id); | |
758 | fid = le16_to_cpu(fdt->id); | |
7d232c74 AV |
759 | ha->fdt_wrt_disable = fdt->wrt_disable_bits; |
760 | ha->fdt_erase_cmd = flash_conf_to_access_addr(0x0300 | fdt->erase_cmd); | |
761 | ha->fdt_block_size = le32_to_cpu(fdt->block_size); | |
762 | if (fdt->unprotect_sec_cmd) { | |
763 | ha->fdt_unprotect_sec_cmd = flash_conf_to_access_addr(0x0300 | | |
764 | fdt->unprotect_sec_cmd); | |
765 | ha->fdt_protect_sec_cmd = fdt->protect_sec_cmd ? | |
766 | flash_conf_to_access_addr(0x0300 | fdt->protect_sec_cmd): | |
767 | flash_conf_to_access_addr(0x0336); | |
768 | } | |
c00d8994 | 769 | goto done; |
7d232c74 | 770 | no_flash_data: |
c00d8994 | 771 | loc = locations[0]; |
7d232c74 | 772 | qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id); |
c00d8994 AV |
773 | mid = man_id; |
774 | fid = flash_id; | |
7d232c74 AV |
775 | ha->fdt_wrt_disable = 0x9c; |
776 | ha->fdt_erase_cmd = flash_conf_to_access_addr(0x03d8); | |
777 | switch (man_id) { | |
778 | case 0xbf: /* STT flash. */ | |
779 | if (flash_id == 0x8e) | |
780 | ha->fdt_block_size = FLASH_BLK_SIZE_64K; | |
781 | else | |
782 | ha->fdt_block_size = FLASH_BLK_SIZE_32K; | |
783 | ||
784 | if (flash_id == 0x80) | |
785 | ha->fdt_erase_cmd = flash_conf_to_access_addr(0x0352); | |
786 | break; | |
787 | case 0x13: /* ST M25P80. */ | |
788 | ha->fdt_block_size = FLASH_BLK_SIZE_64K; | |
789 | break; | |
790 | case 0x1f: /* Atmel 26DF081A. */ | |
821b3996 | 791 | ha->fdt_block_size = FLASH_BLK_SIZE_4K; |
7d232c74 AV |
792 | ha->fdt_erase_cmd = flash_conf_to_access_addr(0x0320); |
793 | ha->fdt_unprotect_sec_cmd = flash_conf_to_access_addr(0x0339); | |
794 | ha->fdt_protect_sec_cmd = flash_conf_to_access_addr(0x0336); | |
795 | break; | |
796 | default: | |
797 | /* Default to 64 kb sector size. */ | |
798 | ha->fdt_block_size = FLASH_BLK_SIZE_64K; | |
799 | break; | |
800 | } | |
c00d8994 AV |
801 | done: |
802 | DEBUG2(qla_printk(KERN_DEBUG, ha, "FDT[%s]: (0x%x/0x%x) erase=0x%x " | |
821b3996 | 803 | "pro=%x upro=%x wrtd=0x%x blk=0x%x.\n", loc, mid, fid, |
7d232c74 | 804 | ha->fdt_erase_cmd, ha->fdt_protect_sec_cmd, |
821b3996 | 805 | ha->fdt_unprotect_sec_cmd, ha->fdt_wrt_disable, |
7d232c74 AV |
806 | ha->fdt_block_size)); |
807 | } | |
808 | ||
c00d8994 AV |
809 | int |
810 | qla2xxx_get_flash_info(scsi_qla_host_t *ha) | |
811 | { | |
812 | int ret; | |
813 | uint32_t flt_addr; | |
814 | ||
815 | if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha)) | |
816 | return QLA_SUCCESS; | |
817 | ||
818 | ret = qla2xxx_find_flt_start(ha, &flt_addr); | |
819 | if (ret != QLA_SUCCESS) | |
820 | return ret; | |
821 | ||
822 | qla2xxx_get_flt_info(ha, flt_addr); | |
823 | qla2xxx_get_fdt_info(ha); | |
824 | ||
825 | return QLA_SUCCESS; | |
826 | } | |
827 | ||
272976ca AV |
828 | void |
829 | qla2xxx_flash_npiv_conf(scsi_qla_host_t *ha) | |
830 | { | |
831 | #define NPIV_CONFIG_SIZE (16*1024) | |
832 | void *data; | |
833 | uint16_t *wptr; | |
834 | uint16_t cnt, chksum; | |
835 | struct qla_npiv_header hdr; | |
836 | struct qla_npiv_entry *entry; | |
837 | ||
838 | if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha)) | |
839 | return; | |
840 | ||
841 | ha->isp_ops->read_optrom(ha, (uint8_t *)&hdr, | |
842 | ha->flt_region_npiv_conf << 2, sizeof(struct qla_npiv_header)); | |
843 | if (hdr.version == __constant_cpu_to_le16(0xffff)) | |
844 | return; | |
845 | if (hdr.version != __constant_cpu_to_le16(1)) { | |
846 | DEBUG2(qla_printk(KERN_INFO, ha, "Unsupported NPIV-Config " | |
847 | "detected: version=0x%x entries=0x%x checksum=0x%x.\n", | |
848 | le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries), | |
849 | le16_to_cpu(hdr.checksum))); | |
850 | return; | |
851 | } | |
852 | ||
853 | data = kmalloc(NPIV_CONFIG_SIZE, GFP_KERNEL); | |
854 | if (!data) { | |
855 | DEBUG2(qla_printk(KERN_INFO, ha, "NPIV-Config: Unable to " | |
856 | "allocate memory.\n")); | |
857 | return; | |
858 | } | |
859 | ||
860 | ha->isp_ops->read_optrom(ha, (uint8_t *)data, | |
861 | ha->flt_region_npiv_conf << 2, NPIV_CONFIG_SIZE); | |
862 | ||
863 | cnt = (sizeof(struct qla_npiv_header) + le16_to_cpu(hdr.entries) * | |
864 | sizeof(struct qla_npiv_entry)) >> 1; | |
865 | for (wptr = data, chksum = 0; cnt; cnt--) | |
866 | chksum += le16_to_cpu(*wptr++); | |
867 | if (chksum) { | |
868 | DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent NPIV-Config " | |
869 | "detected: version=0x%x entries=0x%x checksum=0x%x.\n", | |
870 | le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries), | |
871 | chksum)); | |
872 | goto done; | |
873 | } | |
874 | ||
875 | entry = data + sizeof(struct qla_npiv_header); | |
876 | cnt = le16_to_cpu(hdr.entries); | |
877 | for ( ; cnt; cnt--, entry++) { | |
878 | uint16_t flags; | |
879 | struct fc_vport_identifiers vid; | |
880 | struct fc_vport *vport; | |
881 | ||
882 | flags = le16_to_cpu(entry->flags); | |
883 | if (flags == 0xffff) | |
884 | continue; | |
885 | if ((flags & BIT_0) == 0) | |
886 | continue; | |
887 | ||
888 | memset(&vid, 0, sizeof(vid)); | |
889 | vid.roles = FC_PORT_ROLE_FCP_INITIATOR; | |
890 | vid.vport_type = FC_PORTTYPE_NPIV; | |
891 | vid.disable = false; | |
892 | vid.port_name = wwn_to_u64(entry->port_name); | |
893 | vid.node_name = wwn_to_u64(entry->node_name); | |
894 | ||
895 | DEBUG2(qla_printk(KERN_DEBUG, ha, "NPIV[%02x]: wwpn=%llx " | |
4a3e1ea8 AB |
896 | "wwnn=%llx vf_id=0x%x qos=0x%x.\n", cnt, |
897 | (unsigned long long)vid.port_name, | |
898 | (unsigned long long)vid.node_name, | |
899 | le16_to_cpu(entry->vf_id), le16_to_cpu(entry->qos))); | |
272976ca AV |
900 | |
901 | vport = fc_vport_create(ha->host, 0, &vid); | |
902 | if (!vport) | |
903 | qla_printk(KERN_INFO, ha, "NPIV-Config: Failed to " | |
904 | "create vport [%02x]: wwpn=%llx wwnn=%llx.\n", cnt, | |
4a3e1ea8 AB |
905 | (unsigned long long)vid.port_name, |
906 | (unsigned long long)vid.node_name); | |
272976ca AV |
907 | } |
908 | done: | |
909 | kfree(data); | |
910 | } | |
911 | ||
cb8dacbf AV |
912 | static void |
913 | qla24xx_unprotect_flash(scsi_qla_host_t *ha) | |
914 | { | |
915 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; | |
916 | ||
917 | /* Enable flash write. */ | |
918 | WRT_REG_DWORD(®->ctrl_status, | |
919 | RD_REG_DWORD(®->ctrl_status) | CSRX_FLASH_ENABLE); | |
920 | RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */ | |
921 | ||
7d232c74 AV |
922 | if (!ha->fdt_wrt_disable) |
923 | return; | |
924 | ||
cb8dacbf AV |
925 | /* Disable flash write-protection. */ |
926 | qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0); | |
927 | /* Some flash parts need an additional zero-write to clear bits.*/ | |
928 | qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0); | |
929 | } | |
930 | ||
931 | static void | |
932 | qla24xx_protect_flash(scsi_qla_host_t *ha) | |
933 | { | |
934 | uint32_t cnt; | |
935 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; | |
936 | ||
7d232c74 AV |
937 | if (!ha->fdt_wrt_disable) |
938 | goto skip_wrt_protect; | |
939 | ||
cb8dacbf | 940 | /* Enable flash write-protection and wait for completion. */ |
7d232c74 AV |
941 | qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), |
942 | ha->fdt_wrt_disable); | |
cb8dacbf AV |
943 | for (cnt = 300; cnt && |
944 | qla24xx_read_flash_dword(ha, | |
945 | flash_conf_to_access_addr(0x005)) & BIT_0; | |
946 | cnt--) { | |
947 | udelay(10); | |
948 | } | |
949 | ||
7d232c74 | 950 | skip_wrt_protect: |
cb8dacbf AV |
951 | /* Disable flash write. */ |
952 | WRT_REG_DWORD(®->ctrl_status, | |
953 | RD_REG_DWORD(®->ctrl_status) & ~CSRX_FLASH_ENABLE); | |
954 | RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */ | |
955 | } | |
956 | ||
e5f82ab8 | 957 | static int |
459c5378 AV |
958 | qla24xx_write_flash_data(scsi_qla_host_t *ha, uint32_t *dwptr, uint32_t faddr, |
959 | uint32_t dwords) | |
960 | { | |
961 | int ret; | |
338c9161 | 962 | uint32_t liter, miter; |
7d232c74 | 963 | uint32_t sec_mask, rest_addr; |
cb8dacbf | 964 | uint32_t fdata, findex; |
338c9161 AV |
965 | dma_addr_t optrom_dma; |
966 | void *optrom = NULL; | |
967 | uint32_t *s, *d; | |
459c5378 AV |
968 | |
969 | ret = QLA_SUCCESS; | |
970 | ||
338c9161 | 971 | /* Prepare burst-capable write on supported ISPs. */ |
b7cc176c | 972 | if (IS_QLA25XX(ha) && !(faddr & 0xfff) && |
338c9161 AV |
973 | dwords > OPTROM_BURST_DWORDS) { |
974 | optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, | |
975 | &optrom_dma, GFP_KERNEL); | |
976 | if (!optrom) { | |
977 | qla_printk(KERN_DEBUG, ha, | |
978 | "Unable to allocate memory for optrom burst write " | |
979 | "(%x KB).\n", OPTROM_BURST_SIZE / 1024); | |
980 | } | |
981 | } | |
982 | ||
7d232c74 AV |
983 | rest_addr = (ha->fdt_block_size >> 2) - 1; |
984 | sec_mask = 0x80000 - (ha->fdt_block_size >> 2); | |
459c5378 | 985 | |
cb8dacbf | 986 | qla24xx_unprotect_flash(ha); |
459c5378 | 987 | |
338c9161 | 988 | for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) { |
821b3996 LC |
989 | |
990 | findex = faddr; | |
991 | fdata = (findex & sec_mask) << 2; | |
45aeaf1e | 992 | |
338c9161 AV |
993 | /* Are we at the beginning of a sector? */ |
994 | if ((findex & rest_addr) == 0) { | |
7d232c74 AV |
995 | /* Do sector unprotect. */ |
996 | if (ha->fdt_unprotect_sec_cmd) | |
338c9161 | 997 | qla24xx_write_flash_dword(ha, |
7d232c74 | 998 | ha->fdt_unprotect_sec_cmd, |
338c9161 | 999 | (fdata & 0xff00) | ((fdata << 16) & |
459c5378 | 1000 | 0xff0000) | ((fdata >> 16) & 0xff)); |
7d232c74 | 1001 | ret = qla24xx_write_flash_dword(ha, ha->fdt_erase_cmd, |
338c9161 AV |
1002 | (fdata & 0xff00) |((fdata << 16) & |
1003 | 0xff0000) | ((fdata >> 16) & 0xff)); | |
1004 | if (ret != QLA_SUCCESS) { | |
1005 | DEBUG9(printk("%s(%ld) Unable to flash " | |
1006 | "sector: address=%x.\n", __func__, | |
1007 | ha->host_no, faddr)); | |
1008 | break; | |
459c5378 | 1009 | } |
338c9161 AV |
1010 | } |
1011 | ||
1012 | /* Go with burst-write. */ | |
94d6a2b3 | 1013 | if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) { |
338c9161 AV |
1014 | /* Copy data to DMA'ble buffer. */ |
1015 | for (miter = 0, s = optrom, d = dwptr; | |
1016 | miter < OPTROM_BURST_DWORDS; miter++, s++, d++) | |
1017 | *s = cpu_to_le32(*d); | |
1018 | ||
1019 | ret = qla2x00_load_ram(ha, optrom_dma, | |
459c5378 | 1020 | flash_data_to_access_addr(faddr), |
338c9161 | 1021 | OPTROM_BURST_DWORDS); |
459c5378 | 1022 | if (ret != QLA_SUCCESS) { |
338c9161 AV |
1023 | qla_printk(KERN_WARNING, ha, |
1024 | "Unable to burst-write optrom segment " | |
1025 | "(%x/%x/%llx).\n", ret, | |
1026 | flash_data_to_access_addr(faddr), | |
875baf3c | 1027 | (unsigned long long)optrom_dma); |
338c9161 AV |
1028 | qla_printk(KERN_WARNING, ha, |
1029 | "Reverting to slow-write.\n"); | |
1030 | ||
1031 | dma_free_coherent(&ha->pdev->dev, | |
1032 | OPTROM_BURST_SIZE, optrom, optrom_dma); | |
1033 | optrom = NULL; | |
1034 | } else { | |
1035 | liter += OPTROM_BURST_DWORDS - 1; | |
1036 | faddr += OPTROM_BURST_DWORDS - 1; | |
1037 | dwptr += OPTROM_BURST_DWORDS - 1; | |
1038 | continue; | |
459c5378 | 1039 | } |
338c9161 | 1040 | } |
45aeaf1e | 1041 | |
338c9161 AV |
1042 | ret = qla24xx_write_flash_dword(ha, |
1043 | flash_data_to_access_addr(faddr), cpu_to_le32(*dwptr)); | |
1044 | if (ret != QLA_SUCCESS) { | |
1045 | DEBUG9(printk("%s(%ld) Unable to program flash " | |
1046 | "address=%x data=%x.\n", __func__, | |
1047 | ha->host_no, faddr, *dwptr)); | |
1048 | break; | |
459c5378 | 1049 | } |
338c9161 | 1050 | |
7d232c74 AV |
1051 | /* Do sector protect. */ |
1052 | if (ha->fdt_unprotect_sec_cmd && | |
338c9161 AV |
1053 | ((faddr & rest_addr) == rest_addr)) |
1054 | qla24xx_write_flash_dword(ha, | |
7d232c74 | 1055 | ha->fdt_protect_sec_cmd, |
338c9161 AV |
1056 | (fdata & 0xff00) | ((fdata << 16) & |
1057 | 0xff0000) | ((fdata >> 16) & 0xff)); | |
1058 | } | |
459c5378 | 1059 | |
cb8dacbf | 1060 | qla24xx_protect_flash(ha); |
459c5378 | 1061 | |
338c9161 AV |
1062 | if (optrom) |
1063 | dma_free_coherent(&ha->pdev->dev, | |
1064 | OPTROM_BURST_SIZE, optrom, optrom_dma); | |
1065 | ||
459c5378 AV |
1066 | return ret; |
1067 | } | |
1068 | ||
1069 | uint8_t * | |
1070 | qla2x00_read_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr, | |
1071 | uint32_t bytes) | |
1072 | { | |
1073 | uint32_t i; | |
1074 | uint16_t *wptr; | |
1075 | ||
1076 | /* Word reads to NVRAM via registers. */ | |
1077 | wptr = (uint16_t *)buf; | |
1078 | qla2x00_lock_nvram_access(ha); | |
1079 | for (i = 0; i < bytes >> 1; i++, naddr++) | |
1080 | wptr[i] = cpu_to_le16(qla2x00_get_nvram_word(ha, | |
1081 | naddr)); | |
1082 | qla2x00_unlock_nvram_access(ha); | |
1083 | ||
1084 | return buf; | |
1085 | } | |
1086 | ||
1087 | uint8_t * | |
1088 | qla24xx_read_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr, | |
1089 | uint32_t bytes) | |
1090 | { | |
1091 | uint32_t i; | |
1092 | uint32_t *dwptr; | |
459c5378 AV |
1093 | |
1094 | /* Dword reads to flash. */ | |
1095 | dwptr = (uint32_t *)buf; | |
1096 | for (i = 0; i < bytes >> 2; i++, naddr++) | |
1097 | dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha, | |
1098 | nvram_data_to_access_addr(naddr))); | |
1099 | ||
459c5378 AV |
1100 | return buf; |
1101 | } | |
1102 | ||
1103 | int | |
1104 | qla2x00_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr, | |
1105 | uint32_t bytes) | |
1106 | { | |
1107 | int ret, stat; | |
1108 | uint32_t i; | |
1109 | uint16_t *wptr; | |
2c96d8d0 | 1110 | unsigned long flags; |
459c5378 AV |
1111 | |
1112 | ret = QLA_SUCCESS; | |
1113 | ||
2c96d8d0 | 1114 | spin_lock_irqsave(&ha->hardware_lock, flags); |
459c5378 AV |
1115 | qla2x00_lock_nvram_access(ha); |
1116 | ||
1117 | /* Disable NVRAM write-protection. */ | |
1118 | stat = qla2x00_clear_nvram_protection(ha); | |
1119 | ||
1120 | wptr = (uint16_t *)buf; | |
1121 | for (i = 0; i < bytes >> 1; i++, naddr++) { | |
1122 | qla2x00_write_nvram_word(ha, naddr, | |
1123 | cpu_to_le16(*wptr)); | |
1124 | wptr++; | |
1125 | } | |
1126 | ||
1127 | /* Enable NVRAM write-protection. */ | |
1128 | qla2x00_set_nvram_protection(ha, stat); | |
1129 | ||
1130 | qla2x00_unlock_nvram_access(ha); | |
2c96d8d0 | 1131 | spin_unlock_irqrestore(&ha->hardware_lock, flags); |
459c5378 AV |
1132 | |
1133 | return ret; | |
1134 | } | |
1135 | ||
1136 | int | |
1137 | qla24xx_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr, | |
1138 | uint32_t bytes) | |
1139 | { | |
1140 | int ret; | |
1141 | uint32_t i; | |
1142 | uint32_t *dwptr; | |
1143 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; | |
1144 | ||
1145 | ret = QLA_SUCCESS; | |
1146 | ||
459c5378 AV |
1147 | /* Enable flash write. */ |
1148 | WRT_REG_DWORD(®->ctrl_status, | |
1149 | RD_REG_DWORD(®->ctrl_status) | CSRX_FLASH_ENABLE); | |
1150 | RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */ | |
1151 | ||
1152 | /* Disable NVRAM write-protection. */ | |
1153 | qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101), | |
1154 | 0); | |
1155 | qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101), | |
1156 | 0); | |
1157 | ||
1158 | /* Dword writes to flash. */ | |
1159 | dwptr = (uint32_t *)buf; | |
1160 | for (i = 0; i < bytes >> 2; i++, naddr++, dwptr++) { | |
1161 | ret = qla24xx_write_flash_dword(ha, | |
1162 | nvram_data_to_access_addr(naddr), | |
1163 | cpu_to_le32(*dwptr)); | |
1164 | if (ret != QLA_SUCCESS) { | |
1165 | DEBUG9(printk("%s(%ld) Unable to program " | |
1166 | "nvram address=%x data=%x.\n", __func__, | |
1167 | ha->host_no, naddr, *dwptr)); | |
1168 | break; | |
1169 | } | |
1170 | } | |
1171 | ||
1172 | /* Enable NVRAM write-protection. */ | |
1173 | qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101), | |
1174 | 0x8c); | |
1175 | ||
1176 | /* Disable flash write. */ | |
1177 | WRT_REG_DWORD(®->ctrl_status, | |
1178 | RD_REG_DWORD(®->ctrl_status) & ~CSRX_FLASH_ENABLE); | |
1179 | RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */ | |
1180 | ||
459c5378 AV |
1181 | return ret; |
1182 | } | |
f6df144c | 1183 | |
c3a2f0df AV |
1184 | uint8_t * |
1185 | qla25xx_read_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr, | |
1186 | uint32_t bytes) | |
1187 | { | |
1188 | uint32_t i; | |
1189 | uint32_t *dwptr; | |
1190 | ||
1191 | /* Dword reads to flash. */ | |
1192 | dwptr = (uint32_t *)buf; | |
1193 | for (i = 0; i < bytes >> 2; i++, naddr++) | |
1194 | dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha, | |
c00d8994 AV |
1195 | flash_data_to_access_addr(ha->flt_region_vpd_nvram | |
1196 | naddr))); | |
c3a2f0df AV |
1197 | |
1198 | return buf; | |
1199 | } | |
1200 | ||
1201 | int | |
1202 | qla25xx_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr, | |
1203 | uint32_t bytes) | |
1204 | { | |
2c96d8d0 AV |
1205 | #define RMW_BUFFER_SIZE (64 * 1024) |
1206 | uint8_t *dbuf; | |
1207 | ||
1208 | dbuf = vmalloc(RMW_BUFFER_SIZE); | |
1209 | if (!dbuf) | |
1210 | return QLA_MEMORY_ALLOC_FAILED; | |
c00d8994 | 1211 | ha->isp_ops->read_optrom(ha, dbuf, ha->flt_region_vpd_nvram << 2, |
2c96d8d0 AV |
1212 | RMW_BUFFER_SIZE); |
1213 | memcpy(dbuf + (naddr << 2), buf, bytes); | |
c00d8994 | 1214 | ha->isp_ops->write_optrom(ha, dbuf, ha->flt_region_vpd_nvram << 2, |
2c96d8d0 AV |
1215 | RMW_BUFFER_SIZE); |
1216 | vfree(dbuf); | |
1217 | ||
1218 | return QLA_SUCCESS; | |
c3a2f0df | 1219 | } |
f6df144c | 1220 | |
1221 | static inline void | |
1222 | qla2x00_flip_colors(scsi_qla_host_t *ha, uint16_t *pflags) | |
1223 | { | |
1224 | if (IS_QLA2322(ha)) { | |
1225 | /* Flip all colors. */ | |
1226 | if (ha->beacon_color_state == QLA_LED_ALL_ON) { | |
1227 | /* Turn off. */ | |
1228 | ha->beacon_color_state = 0; | |
1229 | *pflags = GPIO_LED_ALL_OFF; | |
1230 | } else { | |
1231 | /* Turn on. */ | |
1232 | ha->beacon_color_state = QLA_LED_ALL_ON; | |
1233 | *pflags = GPIO_LED_RGA_ON; | |
1234 | } | |
1235 | } else { | |
1236 | /* Flip green led only. */ | |
1237 | if (ha->beacon_color_state == QLA_LED_GRN_ON) { | |
1238 | /* Turn off. */ | |
1239 | ha->beacon_color_state = 0; | |
1240 | *pflags = GPIO_LED_GREEN_OFF_AMBER_OFF; | |
1241 | } else { | |
1242 | /* Turn on. */ | |
1243 | ha->beacon_color_state = QLA_LED_GRN_ON; | |
1244 | *pflags = GPIO_LED_GREEN_ON_AMBER_OFF; | |
1245 | } | |
1246 | } | |
1247 | } | |
1248 | ||
948882f6 AV |
1249 | #define PIO_REG(h, r) ((h)->pio_address + offsetof(struct device_reg_2xxx, r)) |
1250 | ||
f6df144c | 1251 | void |
1252 | qla2x00_beacon_blink(struct scsi_qla_host *ha) | |
1253 | { | |
1254 | uint16_t gpio_enable; | |
1255 | uint16_t gpio_data; | |
1256 | uint16_t led_color = 0; | |
1257 | unsigned long flags; | |
1258 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; | |
1259 | ||
f6df144c | 1260 | spin_lock_irqsave(&ha->hardware_lock, flags); |
1261 | ||
1262 | /* Save the Original GPIOE. */ | |
1263 | if (ha->pio_address) { | |
948882f6 AV |
1264 | gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe)); |
1265 | gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod)); | |
f6df144c | 1266 | } else { |
1267 | gpio_enable = RD_REG_WORD(®->gpioe); | |
1268 | gpio_data = RD_REG_WORD(®->gpiod); | |
1269 | } | |
1270 | ||
1271 | /* Set the modified gpio_enable values */ | |
1272 | gpio_enable |= GPIO_LED_MASK; | |
1273 | ||
1274 | if (ha->pio_address) { | |
948882f6 | 1275 | WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable); |
f6df144c | 1276 | } else { |
1277 | WRT_REG_WORD(®->gpioe, gpio_enable); | |
1278 | RD_REG_WORD(®->gpioe); | |
1279 | } | |
1280 | ||
1281 | qla2x00_flip_colors(ha, &led_color); | |
1282 | ||
1283 | /* Clear out any previously set LED color. */ | |
1284 | gpio_data &= ~GPIO_LED_MASK; | |
1285 | ||
1286 | /* Set the new input LED color to GPIOD. */ | |
1287 | gpio_data |= led_color; | |
1288 | ||
1289 | /* Set the modified gpio_data values */ | |
1290 | if (ha->pio_address) { | |
948882f6 | 1291 | WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data); |
f6df144c | 1292 | } else { |
1293 | WRT_REG_WORD(®->gpiod, gpio_data); | |
1294 | RD_REG_WORD(®->gpiod); | |
1295 | } | |
1296 | ||
1297 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1298 | } | |
1299 | ||
1300 | int | |
1301 | qla2x00_beacon_on(struct scsi_qla_host *ha) | |
1302 | { | |
1303 | uint16_t gpio_enable; | |
1304 | uint16_t gpio_data; | |
1305 | unsigned long flags; | |
1306 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; | |
1307 | ||
1308 | ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING; | |
1309 | ha->fw_options[1] |= FO1_DISABLE_GPIO6_7; | |
1310 | ||
1311 | if (qla2x00_set_fw_options(ha, ha->fw_options) != QLA_SUCCESS) { | |
1312 | qla_printk(KERN_WARNING, ha, | |
1313 | "Unable to update fw options (beacon on).\n"); | |
1314 | return QLA_FUNCTION_FAILED; | |
1315 | } | |
1316 | ||
f6df144c | 1317 | /* Turn off LEDs. */ |
1318 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
1319 | if (ha->pio_address) { | |
948882f6 AV |
1320 | gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe)); |
1321 | gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod)); | |
f6df144c | 1322 | } else { |
1323 | gpio_enable = RD_REG_WORD(®->gpioe); | |
1324 | gpio_data = RD_REG_WORD(®->gpiod); | |
1325 | } | |
1326 | gpio_enable |= GPIO_LED_MASK; | |
1327 | ||
1328 | /* Set the modified gpio_enable values. */ | |
1329 | if (ha->pio_address) { | |
948882f6 | 1330 | WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable); |
f6df144c | 1331 | } else { |
1332 | WRT_REG_WORD(®->gpioe, gpio_enable); | |
1333 | RD_REG_WORD(®->gpioe); | |
1334 | } | |
1335 | ||
1336 | /* Clear out previously set LED colour. */ | |
1337 | gpio_data &= ~GPIO_LED_MASK; | |
1338 | if (ha->pio_address) { | |
948882f6 | 1339 | WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data); |
f6df144c | 1340 | } else { |
1341 | WRT_REG_WORD(®->gpiod, gpio_data); | |
1342 | RD_REG_WORD(®->gpiod); | |
1343 | } | |
1344 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1345 | ||
1346 | /* | |
1347 | * Let the per HBA timer kick off the blinking process based on | |
1348 | * the following flags. No need to do anything else now. | |
1349 | */ | |
1350 | ha->beacon_blink_led = 1; | |
1351 | ha->beacon_color_state = 0; | |
1352 | ||
1353 | return QLA_SUCCESS; | |
1354 | } | |
1355 | ||
1356 | int | |
1357 | qla2x00_beacon_off(struct scsi_qla_host *ha) | |
1358 | { | |
1359 | int rval = QLA_SUCCESS; | |
1360 | ||
1361 | ha->beacon_blink_led = 0; | |
1362 | ||
1363 | /* Set the on flag so when it gets flipped it will be off. */ | |
1364 | if (IS_QLA2322(ha)) | |
1365 | ha->beacon_color_state = QLA_LED_ALL_ON; | |
1366 | else | |
1367 | ha->beacon_color_state = QLA_LED_GRN_ON; | |
1368 | ||
fd34f556 | 1369 | ha->isp_ops->beacon_blink(ha); /* This turns green LED off */ |
f6df144c | 1370 | |
1371 | ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING; | |
1372 | ha->fw_options[1] &= ~FO1_DISABLE_GPIO6_7; | |
1373 | ||
1374 | rval = qla2x00_set_fw_options(ha, ha->fw_options); | |
1375 | if (rval != QLA_SUCCESS) | |
1376 | qla_printk(KERN_WARNING, ha, | |
1377 | "Unable to update fw options (beacon off).\n"); | |
1378 | return rval; | |
1379 | } | |
1380 | ||
1381 | ||
1382 | static inline void | |
1383 | qla24xx_flip_colors(scsi_qla_host_t *ha, uint16_t *pflags) | |
1384 | { | |
1385 | /* Flip all colors. */ | |
1386 | if (ha->beacon_color_state == QLA_LED_ALL_ON) { | |
1387 | /* Turn off. */ | |
1388 | ha->beacon_color_state = 0; | |
1389 | *pflags = 0; | |
1390 | } else { | |
1391 | /* Turn on. */ | |
1392 | ha->beacon_color_state = QLA_LED_ALL_ON; | |
1393 | *pflags = GPDX_LED_YELLOW_ON | GPDX_LED_AMBER_ON; | |
1394 | } | |
1395 | } | |
1396 | ||
1397 | void | |
1398 | qla24xx_beacon_blink(struct scsi_qla_host *ha) | |
1399 | { | |
1400 | uint16_t led_color = 0; | |
1401 | uint32_t gpio_data; | |
1402 | unsigned long flags; | |
1403 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; | |
1404 | ||
1405 | /* Save the Original GPIOD. */ | |
1406 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
1407 | gpio_data = RD_REG_DWORD(®->gpiod); | |
1408 | ||
1409 | /* Enable the gpio_data reg for update. */ | |
1410 | gpio_data |= GPDX_LED_UPDATE_MASK; | |
1411 | ||
1412 | WRT_REG_DWORD(®->gpiod, gpio_data); | |
1413 | gpio_data = RD_REG_DWORD(®->gpiod); | |
1414 | ||
1415 | /* Set the color bits. */ | |
1416 | qla24xx_flip_colors(ha, &led_color); | |
1417 | ||
1418 | /* Clear out any previously set LED color. */ | |
1419 | gpio_data &= ~GPDX_LED_COLOR_MASK; | |
1420 | ||
1421 | /* Set the new input LED color to GPIOD. */ | |
1422 | gpio_data |= led_color; | |
1423 | ||
1424 | /* Set the modified gpio_data values. */ | |
1425 | WRT_REG_DWORD(®->gpiod, gpio_data); | |
1426 | gpio_data = RD_REG_DWORD(®->gpiod); | |
1427 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1428 | } | |
1429 | ||
1430 | int | |
1431 | qla24xx_beacon_on(struct scsi_qla_host *ha) | |
1432 | { | |
1433 | uint32_t gpio_data; | |
1434 | unsigned long flags; | |
1435 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; | |
1436 | ||
1437 | if (ha->beacon_blink_led == 0) { | |
1438 | /* Enable firmware for update */ | |
1439 | ha->fw_options[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL; | |
1440 | ||
1441 | if (qla2x00_set_fw_options(ha, ha->fw_options) != QLA_SUCCESS) | |
1442 | return QLA_FUNCTION_FAILED; | |
1443 | ||
1444 | if (qla2x00_get_fw_options(ha, ha->fw_options) != | |
1445 | QLA_SUCCESS) { | |
1446 | qla_printk(KERN_WARNING, ha, | |
1447 | "Unable to update fw options (beacon on).\n"); | |
1448 | return QLA_FUNCTION_FAILED; | |
1449 | } | |
1450 | ||
1451 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
1452 | gpio_data = RD_REG_DWORD(®->gpiod); | |
1453 | ||
1454 | /* Enable the gpio_data reg for update. */ | |
1455 | gpio_data |= GPDX_LED_UPDATE_MASK; | |
1456 | WRT_REG_DWORD(®->gpiod, gpio_data); | |
1457 | RD_REG_DWORD(®->gpiod); | |
1458 | ||
1459 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1460 | } | |
1461 | ||
1462 | /* So all colors blink together. */ | |
1463 | ha->beacon_color_state = 0; | |
1464 | ||
1465 | /* Let the per HBA timer kick off the blinking process. */ | |
1466 | ha->beacon_blink_led = 1; | |
1467 | ||
1468 | return QLA_SUCCESS; | |
1469 | } | |
1470 | ||
1471 | int | |
1472 | qla24xx_beacon_off(struct scsi_qla_host *ha) | |
1473 | { | |
1474 | uint32_t gpio_data; | |
1475 | unsigned long flags; | |
1476 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; | |
1477 | ||
1478 | ha->beacon_blink_led = 0; | |
1479 | ha->beacon_color_state = QLA_LED_ALL_ON; | |
1480 | ||
fd34f556 | 1481 | ha->isp_ops->beacon_blink(ha); /* Will flip to all off. */ |
f6df144c | 1482 | |
1483 | /* Give control back to firmware. */ | |
1484 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
1485 | gpio_data = RD_REG_DWORD(®->gpiod); | |
1486 | ||
1487 | /* Disable the gpio_data reg for update. */ | |
1488 | gpio_data &= ~GPDX_LED_UPDATE_MASK; | |
1489 | WRT_REG_DWORD(®->gpiod, gpio_data); | |
1490 | RD_REG_DWORD(®->gpiod); | |
1491 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1492 | ||
1493 | ha->fw_options[1] &= ~ADD_FO1_DISABLE_GPIO_LED_CTRL; | |
1494 | ||
1495 | if (qla2x00_set_fw_options(ha, ha->fw_options) != QLA_SUCCESS) { | |
1496 | qla_printk(KERN_WARNING, ha, | |
1497 | "Unable to update fw options (beacon off).\n"); | |
1498 | return QLA_FUNCTION_FAILED; | |
1499 | } | |
1500 | ||
1501 | if (qla2x00_get_fw_options(ha, ha->fw_options) != QLA_SUCCESS) { | |
1502 | qla_printk(KERN_WARNING, ha, | |
1503 | "Unable to get fw options (beacon off).\n"); | |
1504 | return QLA_FUNCTION_FAILED; | |
1505 | } | |
1506 | ||
1507 | return QLA_SUCCESS; | |
1508 | } | |
854165f4 | 1509 | |
1510 | ||
1511 | /* | |
1512 | * Flash support routines | |
1513 | */ | |
1514 | ||
1515 | /** | |
1516 | * qla2x00_flash_enable() - Setup flash for reading and writing. | |
1517 | * @ha: HA context | |
1518 | */ | |
1519 | static void | |
1520 | qla2x00_flash_enable(scsi_qla_host_t *ha) | |
1521 | { | |
1522 | uint16_t data; | |
1523 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; | |
1524 | ||
1525 | data = RD_REG_WORD(®->ctrl_status); | |
1526 | data |= CSR_FLASH_ENABLE; | |
1527 | WRT_REG_WORD(®->ctrl_status, data); | |
1528 | RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ | |
1529 | } | |
1530 | ||
1531 | /** | |
1532 | * qla2x00_flash_disable() - Disable flash and allow RISC to run. | |
1533 | * @ha: HA context | |
1534 | */ | |
1535 | static void | |
1536 | qla2x00_flash_disable(scsi_qla_host_t *ha) | |
1537 | { | |
1538 | uint16_t data; | |
1539 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; | |
1540 | ||
1541 | data = RD_REG_WORD(®->ctrl_status); | |
1542 | data &= ~(CSR_FLASH_ENABLE); | |
1543 | WRT_REG_WORD(®->ctrl_status, data); | |
1544 | RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ | |
1545 | } | |
1546 | ||
1547 | /** | |
1548 | * qla2x00_read_flash_byte() - Reads a byte from flash | |
1549 | * @ha: HA context | |
1550 | * @addr: Address in flash to read | |
1551 | * | |
1552 | * A word is read from the chip, but, only the lower byte is valid. | |
1553 | * | |
1554 | * Returns the byte read from flash @addr. | |
1555 | */ | |
1556 | static uint8_t | |
1557 | qla2x00_read_flash_byte(scsi_qla_host_t *ha, uint32_t addr) | |
1558 | { | |
1559 | uint16_t data; | |
1560 | uint16_t bank_select; | |
1561 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; | |
1562 | ||
1563 | bank_select = RD_REG_WORD(®->ctrl_status); | |
1564 | ||
1565 | if (IS_QLA2322(ha) || IS_QLA6322(ha)) { | |
1566 | /* Specify 64K address range: */ | |
1567 | /* clear out Module Select and Flash Address bits [19:16]. */ | |
1568 | bank_select &= ~0xf8; | |
1569 | bank_select |= addr >> 12 & 0xf0; | |
1570 | bank_select |= CSR_FLASH_64K_BANK; | |
1571 | WRT_REG_WORD(®->ctrl_status, bank_select); | |
1572 | RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ | |
1573 | ||
1574 | WRT_REG_WORD(®->flash_address, (uint16_t)addr); | |
1575 | data = RD_REG_WORD(®->flash_data); | |
1576 | ||
1577 | return (uint8_t)data; | |
1578 | } | |
1579 | ||
1580 | /* Setup bit 16 of flash address. */ | |
1581 | if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) { | |
1582 | bank_select |= CSR_FLASH_64K_BANK; | |
1583 | WRT_REG_WORD(®->ctrl_status, bank_select); | |
1584 | RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ | |
1585 | } else if (((addr & BIT_16) == 0) && | |
1586 | (bank_select & CSR_FLASH_64K_BANK)) { | |
1587 | bank_select &= ~(CSR_FLASH_64K_BANK); | |
1588 | WRT_REG_WORD(®->ctrl_status, bank_select); | |
1589 | RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ | |
1590 | } | |
1591 | ||
1592 | /* Always perform IO mapped accesses to the FLASH registers. */ | |
1593 | if (ha->pio_address) { | |
1594 | uint16_t data2; | |
1595 | ||
948882f6 | 1596 | WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr); |
854165f4 | 1597 | do { |
948882f6 | 1598 | data = RD_REG_WORD_PIO(PIO_REG(ha, flash_data)); |
854165f4 | 1599 | barrier(); |
1600 | cpu_relax(); | |
948882f6 | 1601 | data2 = RD_REG_WORD_PIO(PIO_REG(ha, flash_data)); |
854165f4 | 1602 | } while (data != data2); |
1603 | } else { | |
1604 | WRT_REG_WORD(®->flash_address, (uint16_t)addr); | |
1605 | data = qla2x00_debounce_register(®->flash_data); | |
1606 | } | |
1607 | ||
1608 | return (uint8_t)data; | |
1609 | } | |
1610 | ||
1611 | /** | |
1612 | * qla2x00_write_flash_byte() - Write a byte to flash | |
1613 | * @ha: HA context | |
1614 | * @addr: Address in flash to write | |
1615 | * @data: Data to write | |
1616 | */ | |
1617 | static void | |
1618 | qla2x00_write_flash_byte(scsi_qla_host_t *ha, uint32_t addr, uint8_t data) | |
1619 | { | |
1620 | uint16_t bank_select; | |
1621 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; | |
1622 | ||
1623 | bank_select = RD_REG_WORD(®->ctrl_status); | |
1624 | if (IS_QLA2322(ha) || IS_QLA6322(ha)) { | |
1625 | /* Specify 64K address range: */ | |
1626 | /* clear out Module Select and Flash Address bits [19:16]. */ | |
1627 | bank_select &= ~0xf8; | |
1628 | bank_select |= addr >> 12 & 0xf0; | |
1629 | bank_select |= CSR_FLASH_64K_BANK; | |
1630 | WRT_REG_WORD(®->ctrl_status, bank_select); | |
1631 | RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ | |
1632 | ||
1633 | WRT_REG_WORD(®->flash_address, (uint16_t)addr); | |
1634 | RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ | |
1635 | WRT_REG_WORD(®->flash_data, (uint16_t)data); | |
1636 | RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ | |
1637 | ||
1638 | return; | |
1639 | } | |
1640 | ||
1641 | /* Setup bit 16 of flash address. */ | |
1642 | if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) { | |
1643 | bank_select |= CSR_FLASH_64K_BANK; | |
1644 | WRT_REG_WORD(®->ctrl_status, bank_select); | |
1645 | RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ | |
1646 | } else if (((addr & BIT_16) == 0) && | |
1647 | (bank_select & CSR_FLASH_64K_BANK)) { | |
1648 | bank_select &= ~(CSR_FLASH_64K_BANK); | |
1649 | WRT_REG_WORD(®->ctrl_status, bank_select); | |
1650 | RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ | |
1651 | } | |
1652 | ||
1653 | /* Always perform IO mapped accesses to the FLASH registers. */ | |
1654 | if (ha->pio_address) { | |
948882f6 AV |
1655 | WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr); |
1656 | WRT_REG_WORD_PIO(PIO_REG(ha, flash_data), (uint16_t)data); | |
854165f4 | 1657 | } else { |
1658 | WRT_REG_WORD(®->flash_address, (uint16_t)addr); | |
1659 | RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ | |
1660 | WRT_REG_WORD(®->flash_data, (uint16_t)data); | |
1661 | RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ | |
1662 | } | |
1663 | } | |
1664 | ||
1665 | /** | |
1666 | * qla2x00_poll_flash() - Polls flash for completion. | |
1667 | * @ha: HA context | |
1668 | * @addr: Address in flash to poll | |
1669 | * @poll_data: Data to be polled | |
1670 | * @man_id: Flash manufacturer ID | |
1671 | * @flash_id: Flash ID | |
1672 | * | |
1673 | * This function polls the device until bit 7 of what is read matches data | |
1674 | * bit 7 or until data bit 5 becomes a 1. If that hapens, the flash ROM timed | |
1675 | * out (a fatal error). The flash book recommeds reading bit 7 again after | |
1676 | * reading bit 5 as a 1. | |
1677 | * | |
1678 | * Returns 0 on success, else non-zero. | |
1679 | */ | |
1680 | static int | |
1681 | qla2x00_poll_flash(scsi_qla_host_t *ha, uint32_t addr, uint8_t poll_data, | |
1682 | uint8_t man_id, uint8_t flash_id) | |
1683 | { | |
1684 | int status; | |
1685 | uint8_t flash_data; | |
1686 | uint32_t cnt; | |
1687 | ||
1688 | status = 1; | |
1689 | ||
1690 | /* Wait for 30 seconds for command to finish. */ | |
1691 | poll_data &= BIT_7; | |
1692 | for (cnt = 3000000; cnt; cnt--) { | |
1693 | flash_data = qla2x00_read_flash_byte(ha, addr); | |
1694 | if ((flash_data & BIT_7) == poll_data) { | |
1695 | status = 0; | |
1696 | break; | |
1697 | } | |
1698 | ||
1699 | if (man_id != 0x40 && man_id != 0xda) { | |
1700 | if ((flash_data & BIT_5) && cnt > 2) | |
1701 | cnt = 2; | |
1702 | } | |
1703 | udelay(10); | |
1704 | barrier(); | |
40a2e34a | 1705 | cond_resched(); |
854165f4 | 1706 | } |
1707 | return status; | |
1708 | } | |
1709 | ||
854165f4 | 1710 | /** |
1711 | * qla2x00_program_flash_address() - Programs a flash address | |
1712 | * @ha: HA context | |
1713 | * @addr: Address in flash to program | |
1714 | * @data: Data to be written in flash | |
1715 | * @man_id: Flash manufacturer ID | |
1716 | * @flash_id: Flash ID | |
1717 | * | |
1718 | * Returns 0 on success, else non-zero. | |
1719 | */ | |
1720 | static int | |
1721 | qla2x00_program_flash_address(scsi_qla_host_t *ha, uint32_t addr, uint8_t data, | |
1722 | uint8_t man_id, uint8_t flash_id) | |
1723 | { | |
1724 | /* Write Program Command Sequence. */ | |
1725 | if (IS_OEM_001(ha)) { | |
1726 | qla2x00_write_flash_byte(ha, 0xaaa, 0xaa); | |
1727 | qla2x00_write_flash_byte(ha, 0x555, 0x55); | |
1728 | qla2x00_write_flash_byte(ha, 0xaaa, 0xa0); | |
1729 | qla2x00_write_flash_byte(ha, addr, data); | |
1730 | } else { | |
1731 | if (man_id == 0xda && flash_id == 0xc1) { | |
1732 | qla2x00_write_flash_byte(ha, addr, data); | |
1733 | if (addr & 0x7e) | |
1734 | return 0; | |
1735 | } else { | |
1736 | qla2x00_write_flash_byte(ha, 0x5555, 0xaa); | |
1737 | qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); | |
1738 | qla2x00_write_flash_byte(ha, 0x5555, 0xa0); | |
1739 | qla2x00_write_flash_byte(ha, addr, data); | |
1740 | } | |
1741 | } | |
1742 | ||
1743 | udelay(150); | |
1744 | ||
1745 | /* Wait for write to complete. */ | |
1746 | return qla2x00_poll_flash(ha, addr, data, man_id, flash_id); | |
1747 | } | |
1748 | ||
1749 | /** | |
1750 | * qla2x00_erase_flash() - Erase the flash. | |
1751 | * @ha: HA context | |
1752 | * @man_id: Flash manufacturer ID | |
1753 | * @flash_id: Flash ID | |
1754 | * | |
1755 | * Returns 0 on success, else non-zero. | |
1756 | */ | |
1757 | static int | |
1758 | qla2x00_erase_flash(scsi_qla_host_t *ha, uint8_t man_id, uint8_t flash_id) | |
1759 | { | |
1760 | /* Individual Sector Erase Command Sequence */ | |
1761 | if (IS_OEM_001(ha)) { | |
1762 | qla2x00_write_flash_byte(ha, 0xaaa, 0xaa); | |
1763 | qla2x00_write_flash_byte(ha, 0x555, 0x55); | |
1764 | qla2x00_write_flash_byte(ha, 0xaaa, 0x80); | |
1765 | qla2x00_write_flash_byte(ha, 0xaaa, 0xaa); | |
1766 | qla2x00_write_flash_byte(ha, 0x555, 0x55); | |
1767 | qla2x00_write_flash_byte(ha, 0xaaa, 0x10); | |
1768 | } else { | |
1769 | qla2x00_write_flash_byte(ha, 0x5555, 0xaa); | |
1770 | qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); | |
1771 | qla2x00_write_flash_byte(ha, 0x5555, 0x80); | |
1772 | qla2x00_write_flash_byte(ha, 0x5555, 0xaa); | |
1773 | qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); | |
1774 | qla2x00_write_flash_byte(ha, 0x5555, 0x10); | |
1775 | } | |
1776 | ||
1777 | udelay(150); | |
1778 | ||
1779 | /* Wait for erase to complete. */ | |
1780 | return qla2x00_poll_flash(ha, 0x00, 0x80, man_id, flash_id); | |
1781 | } | |
1782 | ||
1783 | /** | |
1784 | * qla2x00_erase_flash_sector() - Erase a flash sector. | |
1785 | * @ha: HA context | |
1786 | * @addr: Flash sector to erase | |
1787 | * @sec_mask: Sector address mask | |
1788 | * @man_id: Flash manufacturer ID | |
1789 | * @flash_id: Flash ID | |
1790 | * | |
1791 | * Returns 0 on success, else non-zero. | |
1792 | */ | |
1793 | static int | |
1794 | qla2x00_erase_flash_sector(scsi_qla_host_t *ha, uint32_t addr, | |
1795 | uint32_t sec_mask, uint8_t man_id, uint8_t flash_id) | |
1796 | { | |
1797 | /* Individual Sector Erase Command Sequence */ | |
1798 | qla2x00_write_flash_byte(ha, 0x5555, 0xaa); | |
1799 | qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); | |
1800 | qla2x00_write_flash_byte(ha, 0x5555, 0x80); | |
1801 | qla2x00_write_flash_byte(ha, 0x5555, 0xaa); | |
1802 | qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); | |
1803 | if (man_id == 0x1f && flash_id == 0x13) | |
1804 | qla2x00_write_flash_byte(ha, addr & sec_mask, 0x10); | |
1805 | else | |
1806 | qla2x00_write_flash_byte(ha, addr & sec_mask, 0x30); | |
1807 | ||
1808 | udelay(150); | |
1809 | ||
1810 | /* Wait for erase to complete. */ | |
1811 | return qla2x00_poll_flash(ha, addr, 0x80, man_id, flash_id); | |
1812 | } | |
1813 | ||
1814 | /** | |
1815 | * qla2x00_get_flash_manufacturer() - Read manufacturer ID from flash chip. | |
1816 | * @man_id: Flash manufacturer ID | |
1817 | * @flash_id: Flash ID | |
1818 | */ | |
1819 | static void | |
1820 | qla2x00_get_flash_manufacturer(scsi_qla_host_t *ha, uint8_t *man_id, | |
1821 | uint8_t *flash_id) | |
1822 | { | |
1823 | qla2x00_write_flash_byte(ha, 0x5555, 0xaa); | |
1824 | qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); | |
1825 | qla2x00_write_flash_byte(ha, 0x5555, 0x90); | |
1826 | *man_id = qla2x00_read_flash_byte(ha, 0x0000); | |
1827 | *flash_id = qla2x00_read_flash_byte(ha, 0x0001); | |
1828 | qla2x00_write_flash_byte(ha, 0x5555, 0xaa); | |
1829 | qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); | |
1830 | qla2x00_write_flash_byte(ha, 0x5555, 0xf0); | |
1831 | } | |
1832 | ||
30c47662 AV |
1833 | static void |
1834 | qla2x00_read_flash_data(scsi_qla_host_t *ha, uint8_t *tmp_buf, uint32_t saddr, | |
1835 | uint32_t length) | |
1836 | { | |
1837 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; | |
1838 | uint32_t midpoint, ilength; | |
1839 | uint8_t data; | |
1840 | ||
1841 | midpoint = length / 2; | |
1842 | ||
1843 | WRT_REG_WORD(®->nvram, 0); | |
1844 | RD_REG_WORD(®->nvram); | |
1845 | for (ilength = 0; ilength < length; saddr++, ilength++, tmp_buf++) { | |
1846 | if (ilength == midpoint) { | |
1847 | WRT_REG_WORD(®->nvram, NVR_SELECT); | |
1848 | RD_REG_WORD(®->nvram); | |
1849 | } | |
1850 | data = qla2x00_read_flash_byte(ha, saddr); | |
1851 | if (saddr % 100) | |
1852 | udelay(10); | |
1853 | *tmp_buf = data; | |
40a2e34a | 1854 | cond_resched(); |
30c47662 AV |
1855 | } |
1856 | } | |
854165f4 | 1857 | |
1858 | static inline void | |
1859 | qla2x00_suspend_hba(struct scsi_qla_host *ha) | |
1860 | { | |
1861 | int cnt; | |
1862 | unsigned long flags; | |
1863 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; | |
1864 | ||
1865 | /* Suspend HBA. */ | |
1866 | scsi_block_requests(ha->host); | |
fd34f556 | 1867 | ha->isp_ops->disable_intrs(ha); |
854165f4 | 1868 | set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); |
1869 | ||
1870 | /* Pause RISC. */ | |
1871 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
1872 | WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); | |
1873 | RD_REG_WORD(®->hccr); | |
1874 | if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) { | |
1875 | for (cnt = 0; cnt < 30000; cnt++) { | |
1876 | if ((RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) != 0) | |
1877 | break; | |
1878 | udelay(100); | |
1879 | } | |
1880 | } else { | |
1881 | udelay(10); | |
1882 | } | |
1883 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1884 | } | |
1885 | ||
1886 | static inline void | |
1887 | qla2x00_resume_hba(struct scsi_qla_host *ha) | |
1888 | { | |
1889 | /* Resume HBA. */ | |
1890 | clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); | |
1891 | set_bit(ISP_ABORT_NEEDED, &ha->dpc_flags); | |
39a11240 | 1892 | qla2xxx_wake_dpc(ha); |
854165f4 | 1893 | qla2x00_wait_for_hba_online(ha); |
1894 | scsi_unblock_requests(ha->host); | |
1895 | } | |
1896 | ||
1897 | uint8_t * | |
1898 | qla2x00_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf, | |
1899 | uint32_t offset, uint32_t length) | |
1900 | { | |
854165f4 | 1901 | uint32_t addr, midpoint; |
1902 | uint8_t *data; | |
1903 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; | |
1904 | ||
1905 | /* Suspend HBA. */ | |
1906 | qla2x00_suspend_hba(ha); | |
1907 | ||
1908 | /* Go with read. */ | |
854165f4 | 1909 | midpoint = ha->optrom_size / 2; |
1910 | ||
1911 | qla2x00_flash_enable(ha); | |
1912 | WRT_REG_WORD(®->nvram, 0); | |
1913 | RD_REG_WORD(®->nvram); /* PCI Posting. */ | |
1914 | for (addr = offset, data = buf; addr < length; addr++, data++) { | |
1915 | if (addr == midpoint) { | |
1916 | WRT_REG_WORD(®->nvram, NVR_SELECT); | |
1917 | RD_REG_WORD(®->nvram); /* PCI Posting. */ | |
1918 | } | |
1919 | ||
1920 | *data = qla2x00_read_flash_byte(ha, addr); | |
1921 | } | |
1922 | qla2x00_flash_disable(ha); | |
854165f4 | 1923 | |
1924 | /* Resume HBA. */ | |
1925 | qla2x00_resume_hba(ha); | |
1926 | ||
1927 | return buf; | |
1928 | } | |
1929 | ||
1930 | int | |
1931 | qla2x00_write_optrom_data(struct scsi_qla_host *ha, uint8_t *buf, | |
1932 | uint32_t offset, uint32_t length) | |
1933 | { | |
1934 | ||
1935 | int rval; | |
854165f4 | 1936 | uint8_t man_id, flash_id, sec_number, data; |
1937 | uint16_t wd; | |
1938 | uint32_t addr, liter, sec_mask, rest_addr; | |
1939 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; | |
1940 | ||
1941 | /* Suspend HBA. */ | |
1942 | qla2x00_suspend_hba(ha); | |
1943 | ||
1944 | rval = QLA_SUCCESS; | |
1945 | sec_number = 0; | |
1946 | ||
1947 | /* Reset ISP chip. */ | |
854165f4 | 1948 | WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET); |
1949 | pci_read_config_word(ha->pdev, PCI_COMMAND, &wd); | |
1950 | ||
1951 | /* Go with write. */ | |
1952 | qla2x00_flash_enable(ha); | |
1953 | do { /* Loop once to provide quick error exit */ | |
1954 | /* Structure of flash memory based on manufacturer */ | |
1955 | if (IS_OEM_001(ha)) { | |
1956 | /* OEM variant with special flash part. */ | |
1957 | man_id = flash_id = 0; | |
1958 | rest_addr = 0xffff; | |
1959 | sec_mask = 0x10000; | |
1960 | goto update_flash; | |
1961 | } | |
1962 | qla2x00_get_flash_manufacturer(ha, &man_id, &flash_id); | |
1963 | switch (man_id) { | |
1964 | case 0x20: /* ST flash. */ | |
1965 | if (flash_id == 0xd2 || flash_id == 0xe3) { | |
1966 | /* | |
1967 | * ST m29w008at part - 64kb sector size with | |
1968 | * 32kb,8kb,8kb,16kb sectors at memory address | |
1969 | * 0xf0000. | |
1970 | */ | |
1971 | rest_addr = 0xffff; | |
1972 | sec_mask = 0x10000; | |
1973 | break; | |
1974 | } | |
1975 | /* | |
1976 | * ST m29w010b part - 16kb sector size | |
1977 | * Default to 16kb sectors | |
1978 | */ | |
1979 | rest_addr = 0x3fff; | |
1980 | sec_mask = 0x1c000; | |
1981 | break; | |
1982 | case 0x40: /* Mostel flash. */ | |
1983 | /* Mostel v29c51001 part - 512 byte sector size. */ | |
1984 | rest_addr = 0x1ff; | |
1985 | sec_mask = 0x1fe00; | |
1986 | break; | |
1987 | case 0xbf: /* SST flash. */ | |
1988 | /* SST39sf10 part - 4kb sector size. */ | |
1989 | rest_addr = 0xfff; | |
1990 | sec_mask = 0x1f000; | |
1991 | break; | |
1992 | case 0xda: /* Winbond flash. */ | |
1993 | /* Winbond W29EE011 part - 256 byte sector size. */ | |
1994 | rest_addr = 0x7f; | |
1995 | sec_mask = 0x1ff80; | |
1996 | break; | |
1997 | case 0xc2: /* Macronix flash. */ | |
1998 | /* 64k sector size. */ | |
1999 | if (flash_id == 0x38 || flash_id == 0x4f) { | |
2000 | rest_addr = 0xffff; | |
2001 | sec_mask = 0x10000; | |
2002 | break; | |
2003 | } | |
2004 | /* Fall through... */ | |
2005 | ||
2006 | case 0x1f: /* Atmel flash. */ | |
2007 | /* 512k sector size. */ | |
2008 | if (flash_id == 0x13) { | |
2009 | rest_addr = 0x7fffffff; | |
2010 | sec_mask = 0x80000000; | |
2011 | break; | |
2012 | } | |
2013 | /* Fall through... */ | |
2014 | ||
2015 | case 0x01: /* AMD flash. */ | |
2016 | if (flash_id == 0x38 || flash_id == 0x40 || | |
2017 | flash_id == 0x4f) { | |
2018 | /* Am29LV081 part - 64kb sector size. */ | |
2019 | /* Am29LV002BT part - 64kb sector size. */ | |
2020 | rest_addr = 0xffff; | |
2021 | sec_mask = 0x10000; | |
2022 | break; | |
2023 | } else if (flash_id == 0x3e) { | |
2024 | /* | |
2025 | * Am29LV008b part - 64kb sector size with | |
2026 | * 32kb,8kb,8kb,16kb sector at memory address | |
2027 | * h0xf0000. | |
2028 | */ | |
2029 | rest_addr = 0xffff; | |
2030 | sec_mask = 0x10000; | |
2031 | break; | |
2032 | } else if (flash_id == 0x20 || flash_id == 0x6e) { | |
2033 | /* | |
2034 | * Am29LV010 part or AM29f010 - 16kb sector | |
2035 | * size. | |
2036 | */ | |
2037 | rest_addr = 0x3fff; | |
2038 | sec_mask = 0x1c000; | |
2039 | break; | |
2040 | } else if (flash_id == 0x6d) { | |
2041 | /* Am29LV001 part - 8kb sector size. */ | |
2042 | rest_addr = 0x1fff; | |
2043 | sec_mask = 0x1e000; | |
2044 | break; | |
2045 | } | |
2046 | default: | |
2047 | /* Default to 16 kb sector size. */ | |
2048 | rest_addr = 0x3fff; | |
2049 | sec_mask = 0x1c000; | |
2050 | break; | |
2051 | } | |
2052 | ||
2053 | update_flash: | |
2054 | if (IS_QLA2322(ha) || IS_QLA6322(ha)) { | |
2055 | if (qla2x00_erase_flash(ha, man_id, flash_id)) { | |
2056 | rval = QLA_FUNCTION_FAILED; | |
2057 | break; | |
2058 | } | |
2059 | } | |
2060 | ||
2061 | for (addr = offset, liter = 0; liter < length; liter++, | |
2062 | addr++) { | |
2063 | data = buf[liter]; | |
2064 | /* Are we at the beginning of a sector? */ | |
2065 | if ((addr & rest_addr) == 0) { | |
2066 | if (IS_QLA2322(ha) || IS_QLA6322(ha)) { | |
2067 | if (addr >= 0x10000UL) { | |
2068 | if (((addr >> 12) & 0xf0) && | |
2069 | ((man_id == 0x01 && | |
2070 | flash_id == 0x3e) || | |
2071 | (man_id == 0x20 && | |
2072 | flash_id == 0xd2))) { | |
2073 | sec_number++; | |
2074 | if (sec_number == 1) { | |
2075 | rest_addr = | |
2076 | 0x7fff; | |
2077 | sec_mask = | |
2078 | 0x18000; | |
2079 | } else if ( | |
2080 | sec_number == 2 || | |
2081 | sec_number == 3) { | |
2082 | rest_addr = | |
2083 | 0x1fff; | |
2084 | sec_mask = | |
2085 | 0x1e000; | |
2086 | } else if ( | |
2087 | sec_number == 4) { | |
2088 | rest_addr = | |
2089 | 0x3fff; | |
2090 | sec_mask = | |
2091 | 0x1c000; | |
2092 | } | |
2093 | } | |
2094 | } | |
2095 | } else if (addr == ha->optrom_size / 2) { | |
2096 | WRT_REG_WORD(®->nvram, NVR_SELECT); | |
2097 | RD_REG_WORD(®->nvram); | |
2098 | } | |
2099 | ||
2100 | if (flash_id == 0xda && man_id == 0xc1) { | |
2101 | qla2x00_write_flash_byte(ha, 0x5555, | |
2102 | 0xaa); | |
2103 | qla2x00_write_flash_byte(ha, 0x2aaa, | |
2104 | 0x55); | |
2105 | qla2x00_write_flash_byte(ha, 0x5555, | |
2106 | 0xa0); | |
2107 | } else if (!IS_QLA2322(ha) && !IS_QLA6322(ha)) { | |
2108 | /* Then erase it */ | |
2109 | if (qla2x00_erase_flash_sector(ha, | |
2110 | addr, sec_mask, man_id, | |
2111 | flash_id)) { | |
2112 | rval = QLA_FUNCTION_FAILED; | |
2113 | break; | |
2114 | } | |
2115 | if (man_id == 0x01 && flash_id == 0x6d) | |
2116 | sec_number++; | |
2117 | } | |
2118 | } | |
2119 | ||
2120 | if (man_id == 0x01 && flash_id == 0x6d) { | |
2121 | if (sec_number == 1 && | |
2122 | addr == (rest_addr - 1)) { | |
2123 | rest_addr = 0x0fff; | |
2124 | sec_mask = 0x1f000; | |
2125 | } else if (sec_number == 3 && (addr & 0x7ffe)) { | |
2126 | rest_addr = 0x3fff; | |
2127 | sec_mask = 0x1c000; | |
2128 | } | |
2129 | } | |
2130 | ||
2131 | if (qla2x00_program_flash_address(ha, addr, data, | |
2132 | man_id, flash_id)) { | |
2133 | rval = QLA_FUNCTION_FAILED; | |
2134 | break; | |
2135 | } | |
40a2e34a | 2136 | cond_resched(); |
854165f4 | 2137 | } |
2138 | } while (0); | |
2139 | qla2x00_flash_disable(ha); | |
854165f4 | 2140 | |
2141 | /* Resume HBA. */ | |
2142 | qla2x00_resume_hba(ha); | |
2143 | ||
2144 | return rval; | |
2145 | } | |
2146 | ||
2147 | uint8_t * | |
2148 | qla24xx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf, | |
2149 | uint32_t offset, uint32_t length) | |
2150 | { | |
2151 | /* Suspend HBA. */ | |
2152 | scsi_block_requests(ha->host); | |
854165f4 | 2153 | set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); |
2154 | ||
2155 | /* Go with read. */ | |
2156 | qla24xx_read_flash_data(ha, (uint32_t *)buf, offset >> 2, length >> 2); | |
2157 | ||
2158 | /* Resume HBA. */ | |
2159 | clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); | |
854165f4 | 2160 | scsi_unblock_requests(ha->host); |
2161 | ||
2162 | return buf; | |
2163 | } | |
2164 | ||
2165 | int | |
2166 | qla24xx_write_optrom_data(struct scsi_qla_host *ha, uint8_t *buf, | |
2167 | uint32_t offset, uint32_t length) | |
2168 | { | |
2169 | int rval; | |
2170 | ||
2171 | /* Suspend HBA. */ | |
2172 | scsi_block_requests(ha->host); | |
854165f4 | 2173 | set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); |
2174 | ||
2175 | /* Go with write. */ | |
2176 | rval = qla24xx_write_flash_data(ha, (uint32_t *)buf, offset >> 2, | |
2177 | length >> 2); | |
2178 | ||
2179 | /* Resume HBA -- RISC reset needed. */ | |
2180 | clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); | |
2181 | set_bit(ISP_ABORT_NEEDED, &ha->dpc_flags); | |
39a11240 | 2182 | qla2xxx_wake_dpc(ha); |
854165f4 | 2183 | qla2x00_wait_for_hba_online(ha); |
2184 | scsi_unblock_requests(ha->host); | |
2185 | ||
2186 | return rval; | |
2187 | } | |
30c47662 | 2188 | |
338c9161 AV |
2189 | uint8_t * |
2190 | qla25xx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf, | |
2191 | uint32_t offset, uint32_t length) | |
2192 | { | |
2193 | int rval; | |
2194 | dma_addr_t optrom_dma; | |
2195 | void *optrom; | |
2196 | uint8_t *pbuf; | |
2197 | uint32_t faddr, left, burst; | |
2198 | ||
b7cc176c | 2199 | if (offset & 0xfff) |
338c9161 AV |
2200 | goto slow_read; |
2201 | if (length < OPTROM_BURST_SIZE) | |
2202 | goto slow_read; | |
2203 | ||
2204 | optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, | |
2205 | &optrom_dma, GFP_KERNEL); | |
2206 | if (!optrom) { | |
2207 | qla_printk(KERN_DEBUG, ha, | |
2208 | "Unable to allocate memory for optrom burst read " | |
2209 | "(%x KB).\n", OPTROM_BURST_SIZE / 1024); | |
2210 | ||
2211 | goto slow_read; | |
2212 | } | |
2213 | ||
2214 | pbuf = buf; | |
2215 | faddr = offset >> 2; | |
2216 | left = length >> 2; | |
2217 | burst = OPTROM_BURST_DWORDS; | |
2218 | while (left != 0) { | |
2219 | if (burst > left) | |
2220 | burst = left; | |
2221 | ||
2222 | rval = qla2x00_dump_ram(ha, optrom_dma, | |
2223 | flash_data_to_access_addr(faddr), burst); | |
2224 | if (rval) { | |
2225 | qla_printk(KERN_WARNING, ha, | |
2226 | "Unable to burst-read optrom segment " | |
2227 | "(%x/%x/%llx).\n", rval, | |
875baf3c AM |
2228 | flash_data_to_access_addr(faddr), |
2229 | (unsigned long long)optrom_dma); | |
338c9161 AV |
2230 | qla_printk(KERN_WARNING, ha, |
2231 | "Reverting to slow-read.\n"); | |
2232 | ||
2233 | dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, | |
2234 | optrom, optrom_dma); | |
2235 | goto slow_read; | |
2236 | } | |
2237 | ||
2238 | memcpy(pbuf, optrom, burst * 4); | |
2239 | ||
2240 | left -= burst; | |
2241 | faddr += burst; | |
2242 | pbuf += burst * 4; | |
2243 | } | |
2244 | ||
2245 | dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, optrom, | |
2246 | optrom_dma); | |
2247 | ||
2248 | return buf; | |
2249 | ||
2250 | slow_read: | |
2251 | return qla24xx_read_optrom_data(ha, buf, offset, length); | |
2252 | } | |
2253 | ||
30c47662 AV |
2254 | /** |
2255 | * qla2x00_get_fcode_version() - Determine an FCODE image's version. | |
2256 | * @ha: HA context | |
2257 | * @pcids: Pointer to the FCODE PCI data structure | |
2258 | * | |
2259 | * The process of retrieving the FCODE version information is at best | |
2260 | * described as interesting. | |
2261 | * | |
2262 | * Within the first 100h bytes of the image an ASCII string is present | |
2263 | * which contains several pieces of information including the FCODE | |
2264 | * version. Unfortunately it seems the only reliable way to retrieve | |
2265 | * the version is by scanning for another sentinel within the string, | |
2266 | * the FCODE build date: | |
2267 | * | |
2268 | * ... 2.00.02 10/17/02 ... | |
2269 | * | |
2270 | * Returns QLA_SUCCESS on successful retrieval of version. | |
2271 | */ | |
2272 | static void | |
2273 | qla2x00_get_fcode_version(scsi_qla_host_t *ha, uint32_t pcids) | |
2274 | { | |
2275 | int ret = QLA_FUNCTION_FAILED; | |
2276 | uint32_t istart, iend, iter, vend; | |
2277 | uint8_t do_next, rbyte, *vbyte; | |
2278 | ||
2279 | memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); | |
2280 | ||
2281 | /* Skip the PCI data structure. */ | |
2282 | istart = pcids + | |
2283 | ((qla2x00_read_flash_byte(ha, pcids + 0x0B) << 8) | | |
2284 | qla2x00_read_flash_byte(ha, pcids + 0x0A)); | |
2285 | iend = istart + 0x100; | |
2286 | do { | |
2287 | /* Scan for the sentinel date string...eeewww. */ | |
2288 | do_next = 0; | |
2289 | iter = istart; | |
2290 | while ((iter < iend) && !do_next) { | |
2291 | iter++; | |
2292 | if (qla2x00_read_flash_byte(ha, iter) == '/') { | |
2293 | if (qla2x00_read_flash_byte(ha, iter + 2) == | |
2294 | '/') | |
2295 | do_next++; | |
2296 | else if (qla2x00_read_flash_byte(ha, | |
2297 | iter + 3) == '/') | |
2298 | do_next++; | |
2299 | } | |
2300 | } | |
2301 | if (!do_next) | |
2302 | break; | |
2303 | ||
2304 | /* Backtrack to previous ' ' (space). */ | |
2305 | do_next = 0; | |
2306 | while ((iter > istart) && !do_next) { | |
2307 | iter--; | |
2308 | if (qla2x00_read_flash_byte(ha, iter) == ' ') | |
2309 | do_next++; | |
2310 | } | |
2311 | if (!do_next) | |
2312 | break; | |
2313 | ||
2314 | /* | |
2315 | * Mark end of version tag, and find previous ' ' (space) or | |
2316 | * string length (recent FCODE images -- major hack ahead!!!). | |
2317 | */ | |
2318 | vend = iter - 1; | |
2319 | do_next = 0; | |
2320 | while ((iter > istart) && !do_next) { | |
2321 | iter--; | |
2322 | rbyte = qla2x00_read_flash_byte(ha, iter); | |
2323 | if (rbyte == ' ' || rbyte == 0xd || rbyte == 0x10) | |
2324 | do_next++; | |
2325 | } | |
2326 | if (!do_next) | |
2327 | break; | |
2328 | ||
2329 | /* Mark beginning of version tag, and copy data. */ | |
2330 | iter++; | |
2331 | if ((vend - iter) && | |
2332 | ((vend - iter) < sizeof(ha->fcode_revision))) { | |
2333 | vbyte = ha->fcode_revision; | |
2334 | while (iter <= vend) { | |
2335 | *vbyte++ = qla2x00_read_flash_byte(ha, iter); | |
2336 | iter++; | |
2337 | } | |
2338 | ret = QLA_SUCCESS; | |
2339 | } | |
2340 | } while (0); | |
2341 | ||
2342 | if (ret != QLA_SUCCESS) | |
2343 | memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); | |
2344 | } | |
2345 | ||
2346 | int | |
2347 | qla2x00_get_flash_version(scsi_qla_host_t *ha, void *mbuf) | |
2348 | { | |
2349 | int ret = QLA_SUCCESS; | |
2350 | uint8_t code_type, last_image; | |
2351 | uint32_t pcihdr, pcids; | |
2352 | uint8_t *dbyte; | |
2353 | uint16_t *dcode; | |
2354 | ||
2355 | if (!ha->pio_address || !mbuf) | |
2356 | return QLA_FUNCTION_FAILED; | |
2357 | ||
2358 | memset(ha->bios_revision, 0, sizeof(ha->bios_revision)); | |
2359 | memset(ha->efi_revision, 0, sizeof(ha->efi_revision)); | |
2360 | memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); | |
2361 | memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); | |
2362 | ||
2363 | qla2x00_flash_enable(ha); | |
2364 | ||
2365 | /* Begin with first PCI expansion ROM header. */ | |
2366 | pcihdr = 0; | |
2367 | last_image = 1; | |
2368 | do { | |
2369 | /* Verify PCI expansion ROM header. */ | |
2370 | if (qla2x00_read_flash_byte(ha, pcihdr) != 0x55 || | |
2371 | qla2x00_read_flash_byte(ha, pcihdr + 0x01) != 0xaa) { | |
2372 | /* No signature */ | |
2373 | DEBUG2(printk("scsi(%ld): No matching ROM " | |
2374 | "signature.\n", ha->host_no)); | |
2375 | ret = QLA_FUNCTION_FAILED; | |
2376 | break; | |
2377 | } | |
2378 | ||
2379 | /* Locate PCI data structure. */ | |
2380 | pcids = pcihdr + | |
2381 | ((qla2x00_read_flash_byte(ha, pcihdr + 0x19) << 8) | | |
2382 | qla2x00_read_flash_byte(ha, pcihdr + 0x18)); | |
2383 | ||
2384 | /* Validate signature of PCI data structure. */ | |
2385 | if (qla2x00_read_flash_byte(ha, pcids) != 'P' || | |
2386 | qla2x00_read_flash_byte(ha, pcids + 0x1) != 'C' || | |
2387 | qla2x00_read_flash_byte(ha, pcids + 0x2) != 'I' || | |
2388 | qla2x00_read_flash_byte(ha, pcids + 0x3) != 'R') { | |
2389 | /* Incorrect header. */ | |
2390 | DEBUG2(printk("%s(): PCI data struct not found " | |
2391 | "pcir_adr=%x.\n", __func__, pcids)); | |
2392 | ret = QLA_FUNCTION_FAILED; | |
2393 | break; | |
2394 | } | |
2395 | ||
2396 | /* Read version */ | |
2397 | code_type = qla2x00_read_flash_byte(ha, pcids + 0x14); | |
2398 | switch (code_type) { | |
2399 | case ROM_CODE_TYPE_BIOS: | |
2400 | /* Intel x86, PC-AT compatible. */ | |
2401 | ha->bios_revision[0] = | |
2402 | qla2x00_read_flash_byte(ha, pcids + 0x12); | |
2403 | ha->bios_revision[1] = | |
2404 | qla2x00_read_flash_byte(ha, pcids + 0x13); | |
2405 | DEBUG3(printk("%s(): read BIOS %d.%d.\n", __func__, | |
2406 | ha->bios_revision[1], ha->bios_revision[0])); | |
2407 | break; | |
2408 | case ROM_CODE_TYPE_FCODE: | |
2409 | /* Open Firmware standard for PCI (FCode). */ | |
2410 | /* Eeeewww... */ | |
2411 | qla2x00_get_fcode_version(ha, pcids); | |
2412 | break; | |
2413 | case ROM_CODE_TYPE_EFI: | |
2414 | /* Extensible Firmware Interface (EFI). */ | |
2415 | ha->efi_revision[0] = | |
2416 | qla2x00_read_flash_byte(ha, pcids + 0x12); | |
2417 | ha->efi_revision[1] = | |
2418 | qla2x00_read_flash_byte(ha, pcids + 0x13); | |
2419 | DEBUG3(printk("%s(): read EFI %d.%d.\n", __func__, | |
2420 | ha->efi_revision[1], ha->efi_revision[0])); | |
2421 | break; | |
2422 | default: | |
2423 | DEBUG2(printk("%s(): Unrecognized code type %x at " | |
2424 | "pcids %x.\n", __func__, code_type, pcids)); | |
2425 | break; | |
2426 | } | |
2427 | ||
2428 | last_image = qla2x00_read_flash_byte(ha, pcids + 0x15) & BIT_7; | |
2429 | ||
2430 | /* Locate next PCI expansion ROM. */ | |
2431 | pcihdr += ((qla2x00_read_flash_byte(ha, pcids + 0x11) << 8) | | |
2432 | qla2x00_read_flash_byte(ha, pcids + 0x10)) * 512; | |
2433 | } while (!last_image); | |
2434 | ||
2435 | if (IS_QLA2322(ha)) { | |
2436 | /* Read firmware image information. */ | |
2437 | memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); | |
2438 | dbyte = mbuf; | |
2439 | memset(dbyte, 0, 8); | |
2440 | dcode = (uint16_t *)dbyte; | |
2441 | ||
c00d8994 | 2442 | qla2x00_read_flash_data(ha, dbyte, ha->flt_region_fw * 4 + 10, |
30c47662 AV |
2443 | 8); |
2444 | DEBUG3(printk("%s(%ld): dumping fw ver from flash:\n", | |
2445 | __func__, ha->host_no)); | |
2446 | DEBUG3(qla2x00_dump_buffer((uint8_t *)dbyte, 8)); | |
2447 | ||
2448 | if ((dcode[0] == 0xffff && dcode[1] == 0xffff && | |
2449 | dcode[2] == 0xffff && dcode[3] == 0xffff) || | |
2450 | (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 && | |
2451 | dcode[3] == 0)) { | |
2452 | DEBUG2(printk("%s(): Unrecognized fw revision at " | |
c00d8994 | 2453 | "%x.\n", __func__, ha->flt_region_fw * 4)); |
30c47662 AV |
2454 | } else { |
2455 | /* values are in big endian */ | |
2456 | ha->fw_revision[0] = dbyte[0] << 16 | dbyte[1]; | |
2457 | ha->fw_revision[1] = dbyte[2] << 16 | dbyte[3]; | |
2458 | ha->fw_revision[2] = dbyte[4] << 16 | dbyte[5]; | |
2459 | } | |
2460 | } | |
2461 | ||
2462 | qla2x00_flash_disable(ha); | |
2463 | ||
2464 | return ret; | |
2465 | } | |
2466 | ||
2467 | int | |
2468 | qla24xx_get_flash_version(scsi_qla_host_t *ha, void *mbuf) | |
2469 | { | |
2470 | int ret = QLA_SUCCESS; | |
2471 | uint32_t pcihdr, pcids; | |
2472 | uint32_t *dcode; | |
2473 | uint8_t *bcode; | |
2474 | uint8_t code_type, last_image; | |
2475 | int i; | |
2476 | ||
2477 | if (!mbuf) | |
2478 | return QLA_FUNCTION_FAILED; | |
2479 | ||
2480 | memset(ha->bios_revision, 0, sizeof(ha->bios_revision)); | |
2481 | memset(ha->efi_revision, 0, sizeof(ha->efi_revision)); | |
2482 | memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); | |
2483 | memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); | |
2484 | ||
2485 | dcode = mbuf; | |
2486 | ||
2487 | /* Begin with first PCI expansion ROM header. */ | |
c00d8994 | 2488 | pcihdr = ha->flt_region_boot; |
30c47662 AV |
2489 | last_image = 1; |
2490 | do { | |
2491 | /* Verify PCI expansion ROM header. */ | |
2492 | qla24xx_read_flash_data(ha, dcode, pcihdr >> 2, 0x20); | |
2493 | bcode = mbuf + (pcihdr % 4); | |
2494 | if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa) { | |
2495 | /* No signature */ | |
2496 | DEBUG2(printk("scsi(%ld): No matching ROM " | |
2497 | "signature.\n", ha->host_no)); | |
2498 | ret = QLA_FUNCTION_FAILED; | |
2499 | break; | |
2500 | } | |
2501 | ||
2502 | /* Locate PCI data structure. */ | |
2503 | pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]); | |
2504 | ||
2505 | qla24xx_read_flash_data(ha, dcode, pcids >> 2, 0x20); | |
2506 | bcode = mbuf + (pcihdr % 4); | |
2507 | ||
2508 | /* Validate signature of PCI data structure. */ | |
2509 | if (bcode[0x0] != 'P' || bcode[0x1] != 'C' || | |
2510 | bcode[0x2] != 'I' || bcode[0x3] != 'R') { | |
2511 | /* Incorrect header. */ | |
2512 | DEBUG2(printk("%s(): PCI data struct not found " | |
2513 | "pcir_adr=%x.\n", __func__, pcids)); | |
2514 | ret = QLA_FUNCTION_FAILED; | |
2515 | break; | |
2516 | } | |
2517 | ||
2518 | /* Read version */ | |
2519 | code_type = bcode[0x14]; | |
2520 | switch (code_type) { | |
2521 | case ROM_CODE_TYPE_BIOS: | |
2522 | /* Intel x86, PC-AT compatible. */ | |
2523 | ha->bios_revision[0] = bcode[0x12]; | |
2524 | ha->bios_revision[1] = bcode[0x13]; | |
2525 | DEBUG3(printk("%s(): read BIOS %d.%d.\n", __func__, | |
2526 | ha->bios_revision[1], ha->bios_revision[0])); | |
2527 | break; | |
2528 | case ROM_CODE_TYPE_FCODE: | |
2529 | /* Open Firmware standard for PCI (FCode). */ | |
2530 | ha->fcode_revision[0] = bcode[0x12]; | |
2531 | ha->fcode_revision[1] = bcode[0x13]; | |
2532 | DEBUG3(printk("%s(): read FCODE %d.%d.\n", __func__, | |
2533 | ha->fcode_revision[1], ha->fcode_revision[0])); | |
2534 | break; | |
2535 | case ROM_CODE_TYPE_EFI: | |
2536 | /* Extensible Firmware Interface (EFI). */ | |
2537 | ha->efi_revision[0] = bcode[0x12]; | |
2538 | ha->efi_revision[1] = bcode[0x13]; | |
2539 | DEBUG3(printk("%s(): read EFI %d.%d.\n", __func__, | |
2540 | ha->efi_revision[1], ha->efi_revision[0])); | |
2541 | break; | |
2542 | default: | |
2543 | DEBUG2(printk("%s(): Unrecognized code type %x at " | |
2544 | "pcids %x.\n", __func__, code_type, pcids)); | |
2545 | break; | |
2546 | } | |
2547 | ||
2548 | last_image = bcode[0x15] & BIT_7; | |
2549 | ||
2550 | /* Locate next PCI expansion ROM. */ | |
2551 | pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512; | |
2552 | } while (!last_image); | |
2553 | ||
2554 | /* Read firmware image information. */ | |
2555 | memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); | |
2556 | dcode = mbuf; | |
2557 | ||
c00d8994 | 2558 | qla24xx_read_flash_data(ha, dcode, ha->flt_region_fw + 4, 4); |
30c47662 AV |
2559 | for (i = 0; i < 4; i++) |
2560 | dcode[i] = be32_to_cpu(dcode[i]); | |
2561 | ||
2562 | if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff && | |
2563 | dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) || | |
2564 | (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 && | |
2565 | dcode[3] == 0)) { | |
2566 | DEBUG2(printk("%s(): Unrecognized fw version at %x.\n", | |
c00d8994 | 2567 | __func__, ha->flt_region_fw)); |
30c47662 AV |
2568 | } else { |
2569 | ha->fw_revision[0] = dcode[0]; | |
2570 | ha->fw_revision[1] = dcode[1]; | |
2571 | ha->fw_revision[2] = dcode[2]; | |
2572 | ha->fw_revision[3] = dcode[3]; | |
2573 | } | |
2574 | ||
2575 | return ret; | |
2576 | } | |
cb8dacbf | 2577 | |
1ee27146 JC |
2578 | static int |
2579 | qla2xxx_is_vpd_valid(uint8_t *pos, uint8_t *end) | |
2580 | { | |
2581 | if (pos >= end || *pos != 0x82) | |
2582 | return 0; | |
2583 | ||
2584 | pos += 3 + pos[1]; | |
2585 | if (pos >= end || *pos != 0x90) | |
2586 | return 0; | |
2587 | ||
2588 | pos += 3 + pos[1]; | |
2589 | if (pos >= end || *pos != 0x78) | |
2590 | return 0; | |
2591 | ||
2592 | return 1; | |
2593 | } | |
2594 | ||
2595 | int | |
2596 | qla2xxx_get_vpd_field(scsi_qla_host_t *ha, char *key, char *str, size_t size) | |
2597 | { | |
2598 | uint8_t *pos = ha->vpd; | |
2599 | uint8_t *end = pos + ha->vpd_size; | |
2600 | int len = 0; | |
2601 | ||
2602 | if (!IS_FWI2_CAPABLE(ha) || !qla2xxx_is_vpd_valid(pos, end)) | |
2603 | return 0; | |
2604 | ||
2605 | while (pos < end && *pos != 0x78) { | |
2606 | len = (*pos == 0x82) ? pos[1] : pos[2]; | |
2607 | ||
2608 | if (!strncmp(pos, key, strlen(key))) | |
2609 | break; | |
2610 | ||
2611 | if (*pos != 0x90 && *pos != 0x91) | |
2612 | pos += len; | |
2613 | ||
2614 | pos += 3; | |
2615 | } | |
2616 | ||
2617 | if (pos < end - len && *pos != 0x78) | |
2618 | return snprintf(str, size, "%.*s", len, pos + 3); | |
2619 | ||
2620 | return 0; | |
2621 | } | |
2622 | ||
cb8dacbf AV |
2623 | static int |
2624 | qla2xxx_hw_event_store(scsi_qla_host_t *ha, uint32_t *fdata) | |
2625 | { | |
2626 | uint32_t d[2], faddr; | |
2627 | ||
2628 | /* Locate first empty entry. */ | |
2629 | for (;;) { | |
2630 | if (ha->hw_event_ptr >= | |
c00d8994 | 2631 | ha->flt_region_hw_event + FA_HW_EVENT_SIZE) { |
cb8dacbf AV |
2632 | DEBUG2(qla_printk(KERN_WARNING, ha, |
2633 | "HW event -- Log Full!\n")); | |
2634 | return QLA_MEMORY_ALLOC_FAILED; | |
2635 | } | |
2636 | ||
2637 | qla24xx_read_flash_data(ha, d, ha->hw_event_ptr, 2); | |
2638 | faddr = flash_data_to_access_addr(ha->hw_event_ptr); | |
2639 | ha->hw_event_ptr += FA_HW_EVENT_ENTRY_SIZE; | |
2640 | if (d[0] == __constant_cpu_to_le32(0xffffffff) && | |
2641 | d[1] == __constant_cpu_to_le32(0xffffffff)) { | |
2642 | qla24xx_unprotect_flash(ha); | |
2643 | ||
2644 | qla24xx_write_flash_dword(ha, faddr++, | |
2645 | cpu_to_le32(jiffies)); | |
2646 | qla24xx_write_flash_dword(ha, faddr++, 0); | |
2647 | qla24xx_write_flash_dword(ha, faddr++, *fdata++); | |
2648 | qla24xx_write_flash_dword(ha, faddr++, *fdata); | |
2649 | ||
2650 | qla24xx_protect_flash(ha); | |
2651 | break; | |
2652 | } | |
2653 | } | |
2654 | return QLA_SUCCESS; | |
2655 | } | |
2656 | ||
2657 | int | |
2658 | qla2xxx_hw_event_log(scsi_qla_host_t *ha, uint16_t code, uint16_t d1, | |
2659 | uint16_t d2, uint16_t d3) | |
2660 | { | |
2661 | #define QMARK(a, b, c, d) \ | |
2662 | cpu_to_le32(LSB(a) << 24 | LSB(b) << 16 | LSB(c) << 8 | LSB(d)) | |
2663 | ||
2664 | int rval; | |
2665 | uint32_t marker[2], fdata[4]; | |
2666 | ||
c00d8994 | 2667 | if (ha->flt_region_hw_event == 0) |
cb8dacbf AV |
2668 | return QLA_FUNCTION_FAILED; |
2669 | ||
2670 | DEBUG2(qla_printk(KERN_WARNING, ha, | |
2671 | "HW event -- code=%x, d1=%x, d2=%x, d3=%x.\n", code, d1, d2, d3)); | |
2672 | ||
2673 | /* If marker not already found, locate or write. */ | |
2674 | if (!ha->flags.hw_event_marker_found) { | |
2675 | /* Create marker. */ | |
2676 | marker[0] = QMARK('L', ha->fw_major_version, | |
2677 | ha->fw_minor_version, ha->fw_subminor_version); | |
2678 | marker[1] = QMARK(QLA_DRIVER_MAJOR_VER, QLA_DRIVER_MINOR_VER, | |
2679 | QLA_DRIVER_PATCH_VER, QLA_DRIVER_BETA_VER); | |
2680 | ||
2681 | /* Locate marker. */ | |
c00d8994 | 2682 | ha->hw_event_ptr = ha->flt_region_hw_event; |
cb8dacbf AV |
2683 | for (;;) { |
2684 | qla24xx_read_flash_data(ha, fdata, ha->hw_event_ptr, | |
2685 | 4); | |
2686 | if (fdata[0] == __constant_cpu_to_le32(0xffffffff) && | |
2687 | fdata[1] == __constant_cpu_to_le32(0xffffffff)) | |
2688 | break; | |
2689 | ha->hw_event_ptr += FA_HW_EVENT_ENTRY_SIZE; | |
2690 | if (ha->hw_event_ptr >= | |
c00d8994 | 2691 | ha->flt_region_hw_event + FA_HW_EVENT_SIZE) { |
cb8dacbf AV |
2692 | DEBUG2(qla_printk(KERN_WARNING, ha, |
2693 | "HW event -- Log Full!\n")); | |
2694 | return QLA_MEMORY_ALLOC_FAILED; | |
2695 | } | |
2696 | if (fdata[2] == marker[0] && fdata[3] == marker[1]) { | |
2697 | ha->flags.hw_event_marker_found = 1; | |
2698 | break; | |
2699 | } | |
2700 | } | |
2701 | /* No marker, write it. */ | |
2702 | if (!ha->flags.hw_event_marker_found) { | |
2703 | rval = qla2xxx_hw_event_store(ha, marker); | |
2704 | if (rval != QLA_SUCCESS) { | |
2705 | DEBUG2(qla_printk(KERN_WARNING, ha, | |
2706 | "HW event -- Failed marker write=%x.!\n", | |
2707 | rval)); | |
2708 | return rval; | |
2709 | } | |
2710 | ha->flags.hw_event_marker_found = 1; | |
2711 | } | |
2712 | } | |
2713 | ||
2714 | /* Store error. */ | |
2715 | fdata[0] = cpu_to_le32(code << 16 | d1); | |
2716 | fdata[1] = cpu_to_le32(d2 << 16 | d3); | |
2717 | rval = qla2xxx_hw_event_store(ha, fdata); | |
2718 | if (rval != QLA_SUCCESS) { | |
2719 | DEBUG2(qla_printk(KERN_WARNING, ha, | |
2720 | "HW event -- Failed error write=%x.!\n", | |
2721 | rval)); | |
2722 | } | |
2723 | ||
2724 | return rval; | |
2725 | } |